EE-231 Electronics I: Engr. Dr. Hadeed Ahmed Sher

EE-231 Electronics I
Engr. Dr. Hadeed Ahmed Sher
Ghulam Ishaq Khan Institute of Engineering Sciences and Technology, TOPI 23460
hadeed@giki.edu.pk
May 9, 2018
Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 15 Resources May 9, 2018 1 / 22
1 Self bias circuit
2 JFET applications
The JFET as a current source
The JFET as an analog switch
The JFET as a chopper
3 The JFET data sheet
4 Metal Oxide Semiconductor FET

Enhancement type MOSFET
Transfer characteristics
5 Enhancement MOSFET biasing circuit
Self bias circuit
Self bias circuit
A self bias circuit utilizes only one power supply.

The circuit is a simple circuit with more stability compared to the fixed
bias circuit.
It is called self-bias because the voltage drop across Rs is due to the flow
of ID . The current ID creates a voltage drop of Vs = ID Rs . This means
that the gate to source voltage is VGS = VG − VS = 0 − ID RS = −ID RS
Self bias circuit
Self bias circuit
The equation
VGS = −ID RS (1)
describe straight line when plotted on VGS − ID axes.
The Q-point of ID in this biasing circuit can be graphically determined by
plotting the bias line on the same set of axes with the transfer
characteristic.
The intersection of two locates the Q-point.
Algebraically, this can be solved by simultaneously solving the load line
and square-law equation.
The Q-point of VDS can be found by applying KVL around the outer loop.
VDS = VDD − ID (RD + RS ) (2)
Example 5.5 explains the graphical method.
Self bias circuit
Self bias circuit- Algebraic solution
Simultaneous solution of load line and square law equation lead to the
algebraic solution of the circuit. However, this is valid only if the Q-point
is in the pinch-off region i.e., if |VDS —> |VP | − |VGS | . The simultaneous
solution leads to the following quadratic equation.
√
−B − B 2 − 4AC
ID = (3)
2A

Vp2
where, A=RS , B=- 2|Vp |RS + IDSS and C=Vp2 .
2
Note that VDS is positive and VGS is negative for n-channel JFET.
JFET applications The JFET as a current source
A JFET can be used as a constant current to the variable load by the

connection as shown below.
The load is RD . If the JFET is operated in its pinch-off region the current
is constant. The only condition to operate JFET as a current source is
|VDS |>|Vp |. Note that the gate to source voltage is zero in this circuit.
JFET applications The JFET as a current source
Looking onto the characteristic curve of drain the IDSS is practically not a
straight line. It do have some slope i.e., a slight rise towards the right, this
means that the current source is not perfect.
For an ideal current source the resistance rd should be infinite. This means
for an ideal current source the IDSS should be a straight line.
Practically it is not a straight line but it can be modeled close to an ideal
current source by proper biasing.
JFET applications The JFET as an analog switch
A JFET can be used as a switch if the gate to source voltage is switched

between 0 and −Vp as shown below.
The load is RL and it is connected in parallel with the switch. This way
the load voltage will appear only if the switch is open. The switch is open
when VGS = Vp otherwise it is close. Note that as an analog switch the
JFET is operated in voltage controlled resistance region.
JFET applications The JFET as an analog switch

A JFET can be used as a switch if the gate to source voltage is switched
between 0 and −Vp as shown below.
The load is RL and it is connected in parallel with the switch. This way
the load voltage will appear only if the switch is open. The switch is open
when VGS = Vp otherwise it is close. Note that as an analog switch the
JFET is operated in voltage controlled resistance region. In this region a
small ON resistance comes in . It is called RD(ON) and typically it varies
from 20-100 ohms.
JFET applications The JFET as a chopper
The JFET as a chopper

A JFET as a switch if comes in series with the load the circuit is called a
chopper circuit as shown below.
The on and off conditions of JFET as same as that of an analog switch.

the output voltage is now an application of VDR.

RL vd
vL = (4)
RL + rs + RD(ON)
If the load resistance RL is much greater than the other two resistances
then load voltage is approximately equal to the input vd
The JFET data sheet
The JFET data sheet
A JFET datasheet provide similar information as that for a BJT. However,

an important parameters is the IDSS i.e., the reverse saturation current of
reverse biased gate to source junction. Note that the value of IDSS varies
with temperature in the same manner as that of a reverse biased diode.
The value of IDSS provides useful means of calculating the input resistance
of the device by using the following expression.
VGS
R= (5)
IDSS
Using the datasheet of 2N4222 the input resistance at 25◦ and at VDS =0
the value is 150×109 Ω.
Metal Oxide Semiconductor FET
Metal Oxide Semiconductor FET
Gate, source and drain are connected to the base material through a
metal. Silicon dioxide is used as in insulator and because the base in a
semiconductor , therefore it is called metal oxide semiconductor FET.
It is of two types
Depletion type MOSFET
They are often called insulated-gate FET or IGFET.
In JFET the gate signal seize the flow of current, in contrast, in MOSFET
the gate voltage is applied to let the current flow.
Metal Oxide Semiconductor FET Enhancement type MOSFET
The structure of an n-channel Figure shows electrical connections

enhancement type MOSFET is of the drain, source and gate.
shown below.
The positive VGS attracts electrons

VGS is connected such that gate is from the p type substrate to the
positive with respect to the source. region close to the insulating layer.
If the gate voltage is made
sufficiently positive then enough free
electrons are aligned to convert it in
an n-type material.
This conversion of p material into an
n-type material is called as “induced
n-channel”.
For an n-channel enhancement
MOSFET, an n-channel exists only
when it is induced from the p-type
substrate by a positive VGS .

When the VGS reaches a certain threshold voltage VT the induced
n-channel becomes sufficiently conductive.
The typical value of VT range from 1-3 V.
If VT =2 and the VGS is a value much greater than VT say 10V. Under
this condition if the VDS is increased above 0V the current rises linearly
with increase in VDS because of ohm’s law as shown below. As VDS
continues to increase the channel becomes narrower at the drain end as
shown in slide14, because VGD becomes smaller as VDS becomes larger
thus reducing the positive filed at the drain terminal.

For example if VGS =10V and VDS =3V then VGD =10-3=7V. If VDS is
increased to 4V, VGD =10-4=6V. This means that as the VDS increases
the VGD decreases and therefore the channel is narrowed at the drain end.
This means that the resistance of the channel begins to decrease and the
drain current begins to level off. This is shown below. When VDS =8V,
then VGD =2V=VT i.e., positive voltage at the drain end reaches the VT
and the channel width at that end shrinks to zero. Further increase in VDS
makes no increment in the drain current and ID saturates.
Now if VGS =12V and VDS is

increased then saturation occurs at
VDS =12-2=10V. If this saturation
voltage is designated as VDS(sat) then
VDS(sat) = VGS − VT (6)
Figure shows drain characteristics

with varying values of VGS . Note
that for VGS less than VT =2V, the
current ID is reduced to zero. Also
note that the characteristics are
similar to JFET except that the VGS
values are positive.

The saturation voltages are joined with the dashed parabolic line. The
region to the left of this parabolic line is called
voltage-controlled-resistance region.The region to the right of this
parabolic line is called active region and in this region small-signal
amplification is accomplished.
Figure shows the schematic symbols typically used to represent an
n-channel and a p-channel mosfet. If the bulk substrate is shown then
Symbol I(a) and (b) are used. The broken line represents that the channel
is induced rather than a permanent part of the structure. But this symbol
is not always used.
Transfer characteristics
For a MOSFET, in active region, the

drain current and gate-to-source
voltage are related as
ID = 0.5β(VGS −VT )2 VGS ≥ VT

(7)
Where β is a constant whose value
depends on the geometry of the
device. Typically its value is
0.5 × 10−3 A/V 2 . Figure shows the
transfer characteristics at VT =2V
Enhancement MOSFET biasing circuit

A voltage divider biasing circuit is shown below. The procedure of finding
the key parameters is the same as that of a JFET and a BJT.
The resistor Rs does not provide self-bias because self-bias is not possible
with enhancement devices. This resistance provides the feedback for bias
stabilization. Larger the value of Rs less sensitive the bias point is to
changes in mosfet against variations in temperature.
From the figure shown,

R2
VG = VDD (8)
R1 + R2
The values of R1 and R2 are very high to keep the ac input resistance
high. Writing KVL around the gate to source loop,
VGS = VG − ID Rs (9)
Applying KVL around the drain to source loop
VDS = VDD − ID (RD + Rs ) (10)
1 VG
Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) ID = −(
Week 15 )V GS +
Resources May 9, 2018 (11)
21 / 22
The general algebraic expressions for the bias point can be expressed as
R2
)|VDD |
|VG | = ( (12)
R1 + R2
√
−B − B 2 − 4AC
ID = (13)
2A

Where A=Rs2 , B = −2 (|VG | − |VD |)Rs + β1 and C = (|VG | − |Vr |)2
Note that VDS and VGS are positive for N-channel MOSFET.

EE-231 Electronics I: Engr. Dr. Hadeed Ahmed Sher

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EE-231 Electronics I

Engr. Dr. Hadeed Ahmed Sher

3 The JFET data sheet

4 Metal Oxide Semiconductor FET

5 Enhancement MOSFET biasing circuit

Self bias circuit

A self bias circuit utilizes only one power supply.

Self bias circuit

VDS = VDD − ID (RD + RS ) (2)

Example 5.5 explains the graphical method.

Self bias circuit- Algebraic solution

The JFET as a current source

A JFET can be used as a constant current to the variable load by the

The JFET as a current source

The JFET as an analog switch

A JFET can be used as a switch if the gate to source voltage is switched

The JFET as an analog switch

The JFET as a chopper

The on and off conditions of JFET as same as that of an analog switch.

The JFET data sheet

A JFET datasheet provide similar information as that for a BJT. However,

Metal Oxide Semiconductor FET

Enhancement type MOSFET

The structure of an n-channel Figure shows electrical connections

Enhancement type MOSFET

The positive VGS attracts electrons

Enhancement type MOSFET

Enhancement type MOSFET

Enhancement type MOSFET

Now if VGS =12V and VDS is

VDS(sat) = VGS − VT (6)

Figure shows drain characteristics

Enhancement type MOSFET

For a MOSFET, in active region, the

ID = 0.5β(VGS −VT )2 VGS ≥ VT

Enhancement MOSFET biasing circuit

Enhancement MOSFET biasing circuit

From the figure shown,

Enhancement MOSFET biasing circuit

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