EDA Playground Documentation: Release

EDA Playground Documentation
Release
Doulos
December 21, 2016

Contents
1 Table of Contents: 1
i
ii
CHAPTER 1
Table of Contents:
1.1 FAQ
1.1.1 Account Validation and Logging In
How do I validate my account?
ou can reach the validation page by clicking run whilst having selected either Synopsys VCS or Cadence Incisive from
the Tools & Simulators menu or by visiting: https://www.edaplayground.com/validate directly. You will need to
supply some additional indentification information, including a company, organisational or institutional email address.
Enter your details in the form; read the terms and conditions carefully and, if you agree, click I Agree. An email will
then be sent to the email address you entered. Open that email and click on the link it contains and your account will
be validated.
I don’t have a company or institutional email address. How can I validate my account?
Are you sure? Are you perhaps a member of a professional institution that gives you an email address?
Are you sure you need to? Using Aldec Riviera Pro does not require account validation: this is a commercial simu-
lator, which supports VHDL, Verilog, System-Verilog and UVM. Using Cadence Specman does not require account
validation, either.
Which simulators require account validation?
• Synopsys VCS
• Cadence Incisive
What can I do without account validation?
Pretty much everything. Using Aldec Riviera Pro does not require account validation: this is a commercial simula-
tor, which supports VHDL, Verilog, System-Verilog and UVM. Using Cadence Specman does not require account
validation, either.
1
EDA Playground Documentation, Release
I’m a Doulos customer; can I validate my account without access to a company or institutional email
address?
I am looking into this.
I didn’t receive your email, what can I do?
Unfortunately, we put some code in to prevent multiple people validating using the same email address, which also
prevents you resending to your email address. This will be fixed soon. So, just filling in the validation form again is
not an option.
So, first check you spam folder to make sure our email is not stuck there. If not, check the email address you entered
was correct (for example, people often seem to add ‘.com’ instead of ‘.edu’; people often seem to be combining gmail
addresses with work, for example people often seem to type something like ‘myname1982@somerealcompany.com‘).
If all that fails, get in touch with me (Matthew) at getedaplayground@gmail.com.
Why is account validation necessary?
Unfortunately, following some abuse of this privilige on EDA Playground, we have had to restrict access to some of
the simulators. EDA Playground enables you to use some commercial, professional simulators, completely free of
charge. In order to use some simulators, asking for some identification information and the agreement not to abuse
this privilige doesn’t seem much to ask.
How do I log in if I don’t have a Google or Facebook account?
If you have an organisational/company/institutional email address then you can register from the login page. Click on
Register for a full account or No Google or Facebook account?.
1.1.2 Using EDA Playground
How do I start a blank playground design?
When working on code at https://www.edaplayground.com, you can start a blank design by clicking the EDA Play-
ground logo in the top left. (Before doing that, please ensure that your existing code edits are saved.)
How do I modify one of the examples? How do I modify someone else’s playground?
After making code edits, you can save your own version by clicking ==Copy==.
How Can I search for one of my Playgrounds?
Click on your username (top-right) to go to the user pages; the “Playgrounds” tab will be selected. You can see your
playgrounds listed and can change the listing order by clicking on one of the headings.
You can also search for one of your playgrounds by entering search terms in the search box and clicking “Search your
playgrounds”. The search terms search the Name and Descriptions of each playground. You can narrow down your
search by selecting the various menus underneath the search box.
Notice how selecting a menu adds search terms. You can type these in manually if you prefer.
2 Chapter 1. Table of Contents:

How can I publish one of my Playgrounds?
Select “Published (will appear in search results)” from the drop-down menu bottom-right of the share tab and then
save your playground.
How Can I search for one of someone else’s Playgrounds?
Click on your username (top-right) to go to the user pages; then select the “Community” tab. You can see your
playgrounds listed and can change the listing order by clicking on one of the headings.
You can also search for one of someone else’s playgrounds by entering search terms in the search box and clicking
“Search all playgrounds”. The search terms search the Name and Descriptions of each playground. You can narrow
down your search by selecting the various menus underneath the search box.
Notice how selecting a menu adds search terms. You can type these in manually if you prefer.
What if I accidently delete a playground? Can I get it back?
Playgrounds are never actually deleted from the database. So, if you have linked to one of your playgrounds from some
other page you don’t need to worry about accidently deleting it - the URL will be preserved. (Deleting a playground
simply removes it from your list.)
You can find your deleted playgrounds by adding the search term ‘deleted:true’ to the search box. Your deleted
playgrounds will then be listed and you can undelete any one of them by clicking on the arrow to the right of each one.
What is EPWave?
EPWave (EDA Playground Wave) is the first web browser-based wave viewer. It is part of EDA Playground.
Can I view the waves from my EDA Playground sim using EPWaves?
Yes, waves are supported for all languages, frameworks, and libraries. See Loading Waves from EDA Playground
How do I get updates about new EDA Playground features?
New features are frequently being added to EDA Playground. Follow the updates on your favorite social media site:
• @EDAPlayground on Twitter
• EDA Playground on Facebook
• EDA Playground on Google+
What are the resource limits for running my code?
Each run is limited to 60 seconds runtime and 100MB of memory.
1.1. FAQ 3
Which web browsers are supported?
To be honest, I wish I could say I support any browser. To me it goes against the fundamental brilliance of Sir Tim’s
marvellous invention, to then make a website that is only compatible with such-and-such a version of such-and-such
a browser. Unfortunately, it’s quite a complicated site and testing resources are limited. So, as far as I know these are
supported:
• Firefox
• Chrome
• Safari
• Internet Explorer 9 or higher
I’d certainly be interested in hearing about any browser-compatibility issues you come across.
I have more questions. How do I get support?
==EDA Playground== is actively being improved. If you need help or have suggestions, support is available on EDA
Playground forum
If you see a bug, however minor, please post on the forum or file a new issue at httpss://github.com/edaplayground/eda-
playground/issues (requires GitHub account)
For simulator support, please contact the appropriate simulator vendor.
1.2 EDA Playground Help
1.2.1 Quick Start
1. Log in. Click the Log in button (top right) and click either your Google or Facebook.
2. Select your language from the Testbench + Design menu.
3. Select your simulator from the Tools & Simulators menu. Using certain simulators will require you to supply
additional identifcation information.
4. Type in your code in the testbench and design windows.
5. Click Run.
Tutorial
EDA Playground on YouTube - Tutorials for Verilog, SystemVerilog, UVM, and VHDL, interview questions, news
and features, etc.
1.2.2 What is EDA Playground?
EDA Playground gives engineers immediate hands-on exposure to simulating SystemVerilog, Verilog, VHDL,
C++/SystemC, and other HDLs. All you need is a web browser. The goal is to accelerate learning of design/testbench
development with easier code sharing and simpler access to EDA tools and libraries.
• With a simple click, run your code and see console output in real time.

• View waves for your simulation using EPWave browser-based wave viewer.
• Save your code snippets (“Playgrounds”).
• Share your code and simulation results with a web link. Perfect for web forum discussions or emails. Great for
asking questions or sharing your knowledge.
• Quickly try something out
– Try out a language feature with a small example.
– Try out a library that you’re thinking of using.
1.2.3 Example Usecases
• Quick prototyping – try out syntax or a library/language feature.

• When asking questions on Stack Overflow or other online forums, attach a link to the code and simulation
results.
• Use during technical interviews to test candidates’ SystemVerilog/Verilog coding and debug skills.
• Try verifying using different verification frameworks: UVM, SVUnit, plain Verilog, or Python.
1.2.4 Tools & Simulators
For settings and options documentation, see Tools & Simulators Options
Available tools and simulators are below. EDA Playground can support many different tools. Contact us to add your
EDA tool to EDA Playground.
1.2. EDA Playground Help 5

Simulators
• Synopsys VCS
– Commercial simulator for VHDL and SystemVerilog
– Commercial simulator for VHDL and SystemVerilog (VHDL simulation not yet implemented on EDA
Playground)
• Aldec Riviera-PRO
– Commercial simulator for VHDL and SystemVerilog
– Riviera-PRO Product Manual (registration required)
• Incisive Specman Elite
– Commercial simulator that supports e Verification Language, IEEE 1647
– Works with Icarus Verilog 0.10.0 (contact Doulos regarding EDA Playground support for other simulators)
– Hello e World Video Tutorial
• Icarus Verilog
– Version 0.10.0 (devel) supports several SystemVerilog features.
• GPL Cver
• VeriWell
Compilers and Interpreters
• C++
• Perl
• Python
• Csh (C Shell)
Synthesis Tools
NOTE: The synthesis tools will only process code in the right Design pane. The code in the left Testbench pane will
be ignored.
• Yosys
– Yosys on GitHub
• The Verilog-to-Routing (VTR) Project
1.2.5 Libraries & Methodologies
For settings and options documentation, see Languages & Libraries Options
Available libraries and methodologies:

SystemVerilog and Verilog
• UVM - Universal Verification Methodology

– UVM 1.2 Class Reference
* What’s New in UVM 1.2 on YouTube

– UVM 1.1d Class Reference
– Doulos *Easier UVM*
• OVM - Open Verification Methodology
– OVM 2.1.2 Class Reference
– OVM 2.1.2 User Guide
• SVUnit - unit testing framework for Verilog/SystemVerilog modules, classes, etc.
– SVUnit on SourceForge
• OVL - Open Verification Library
– OVL Library Reference Manual
– OVL Quick Reference
• ClueLib - A generic class library in SystemVerilog
– ClueLib API Documentation
• svlib - A Programmer’s Utility Library for SystemVerilog
– svlib User Guide
VHDL
• OVL - Open Verification Library

– OVL Library Reference Manual
– OVL Quick Reference
• PSL - Property Specification Language
– Natively supported by Riviera-PRO
• OSVVM - Open Source VHDL Verification Methodology
C++
• SystemC - system level design and simulation in C++

– SystemC 2.3.1 Class Reference
– TLM 2.0 Class Reference
1.2. EDA Playground Help 7

Python
• MyHDL - a Python based hardware description language (HDL)

– MyHDL Manual
– MyHDL on Bitbucket
• Migen - a Python toolbox for building complex digital hardware
– Migen on GitHub
– Migen from M-Labs
• cocotb - a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
– cocotb on GitHub
1.2.6 What Users are Saying
“This is a really useful web-based utility for anyone who is discussing/sharing/debugging a code segment
with a colleague or a support person. Also, a very useful follow-up tool for post-training help among
students or between instructor and students. Simple, easy, useful.”
—Hemendra Talesara, Verification Technologist at Synapse Design Automation Inc.
“I think EDA Playground is awesome! Great resource to learn without the hassle of setting up tools!”
—Alan Langman, Engineering Consultant
“I’ve used it a few times now to just check out some issues related to SV syntax and it’s been a big
timesaver!”
—Eric White, MTS Design Engineer at AMD
“EDA Playground is sooo useful for interviews. I got a lot more feedback from being able to watch
someone compile and debug errors. I would highly recommend others to use it if they are asking SV
related questions.”
—Ricardo Goto, Verification Engineer
“I have recommended to use EDAPlayground.com to my team and am also trying to use it more for my
debug. I find EDAPlayground.com is much easier than logging into my Unix machines.”
—Subhash Bhogadi, Verification Consultant
“I just wanted to thank you a lot for creating EDA Playground. I’ve been using it a lot lately together with
StackOverflow and it makes asking and answering questions much easier.”
—Tudor Timisescu, System Verification Engineer at Infineon Technologies
1.2.7 Support, Feature Requests and Bug Fixes
Support available on EDA Playground forum

Or open a bug here: https://github.com/edaplayground/eda-playground/issues (requires GitHub account).

1.2.8 News and Site Updates
New features are frequently being added to EDA Playground. Follow the updates on your favorite social media site:
• @EDAPlayground on Twitter
• EDA Playground on Facebook
• EDA Playground on Google+
1.2.9 Credits
EDA Playground is maintained by Doulos.
1.3 Logging in
1.3.1 Logging in with either Google or Facebook
You can log in very simply using either your Google or your Facebook account. Simply click on either the Google
button or the Facebook button on the log in page.
1.3.2 Validating your Account
In order to use certain simulators on EDA Playground (currently Synopsys VCS and Cadence Incisive), you will
need to supply some additional indentification information, including a company, organisational or institutional email
address.
You can reach the validation page by clicking run whilst having selected either Synopsys VCS or Cadence Incisive
from the Tools & Simulators menu or by visiting: http://www.edaplayground.com/validate directly.
Enter your details in the form; read the terms and conditions carefully and, if you agree, click I Agree. An email will
then be sent to the email address you entered. Open that email and click on the link it contains and your account will
be validated.
1.3.3 Doulos Online Training Customers
If you have purchased a place on a Doulos online training course and have been sent a username and password, you
can enter them in the Username and Password boxes and then can log in by clicking on Login. You will then be
directed to the main EDA Playground page and you will see your training course listed on the left hand side. If you
click on that, you will see links to some further instructions and to all the exercises for your training course.
1.3.4 FAQ
I don’t have a company or institutional email address. How can I validate my account?
Are you sure? Are you perhaps a member of a professional institution that gives you an email address?
Are you sure you need to? Using Aldec Riviera Pro does not require account validation: this is a commercial simu-
lator, which supports VHDL, Verilog, System-Verilog and UVM. Using Cadence Specman does not require account
validation, either.
1.3. Logging in 9
Which simulators require account validation?
• Synopsys VCS
What can I do without account validation?
Pretty much everything. Using Aldec Riviera Pro does not require account validation: this is a commercial simula-
tor, which supports VHDL, Verilog, System-Verilog and UVM. Using Cadence Specman does not require account
validation, either.
I’m a Doulos customer; can I validate my account without access to a company or institutional email
address?
I am looking into this.
I didn’t receive your email, what can I do?
Unfortunately, we put some code in to prevent multiple people validating using the same email address, which also
prevents you resending to your email address. This will be fixed soon. So, just filling in the validation form again is
not an option.
So, first check you spam folder to make sure our email is not stuck there. If not, check the email address you entered
was correct (for example, people often seem to add ‘.com’ instead of ‘.edu’; people often seem to be combining gmail
addresses with work, for example people often seem to type something like ‘myname1982@somerealcompany.com‘).
If all that fails, get in touch with me (Matthew) at getedaplayground@gmail.com.
Why is account validation necessary?
Unfortunately, following some abuse of this privilige on EDA Playground, we have had to restrict access to some of
the simulators. EDA Playground enables you to use some commercial, professional simulators, completely free of
charge. In order to use some simulators, asking for some identification information and the agreement not to abuse
this privilige doesn’t seem much to ask.
How do I log in if I don’t have a Google or Facebook account?
We are working on providing additional ways to sign into ==EDA Playground==. I know it has said this for years, but
now we are. We really are. Meanwhile, please create a new Google account at https://accounts.google.com/SignUp
and use that to sign in.
1.4 Tutorial
This Quick Start is intended for users of http://www.edaplayground.com.

1. In a separate web browser window, log in to EDA Playground at: http://www.edaplayground.com
2. In either the Design or Testbench window pane, type in the following code:

module test;
initial
$display("Hello World!");
endmodule
(Note: The code in the right Design pane is compiled first, followed by code in the left Testbench pane.)
3. Click
Yes, running a sim is as simple as that!
4. In the bottom pane, you should see real-time results as your code is being compiled and then run. A run typically
takes 1-5 seconds, depending on network traffic and simulator. Near the bottom of result output, you should see:
Hello World!
5. Now, let’s save our good work. Type in a descriptive name in the Details area on the left.
and click
6. The browser page will reload and the browser address bar will change. This is a persistent link to your saved
code. You can send the link by email, post it on a web page, post it on Stack Overflow forums, etc. Here is what
the link looks like for one user’s Hello World! playground: http://www.edaplayground.com/s/3/12
7. Now, let’s try modifying existing code. Load the following example: RAM
8. On the left editor pane, before the end of initial block, add the following:
write_enable = 1;
data_write = 8'h2C;
toggle_clk_write;
toggle_clk_read;
$display("data[%0h]: %0h",
address_read, data_read);
The above code will write new data and read it out again. ( address_read and address_write should be the same).
9. Run the sim. In the results you should see this new message:
data[1b]: 2c
10. Optional. Click Copy to save a personal version of the modified RAM code, including the simulation results.
1.4.1 Loading Waves from EDA Playground
You can run a simulation on EDA Playground and load the resulting waves in EPWave.
Loading Waves for SystemVerilog and Verilog Simulations
• Go to your code on EDA Playground. For example: RAM Design and Test
• Make sure your code contains appropriate function calls to create a *.vcd file. For example:
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
• Select a simulator and check the Open EPWave after run checkbox. (Not all simulators may have this run
option.)
1.4. Tutorial 11
• Click Run. After the run completes, the resulting waves will load in a new EPWave window. (Pop-ups must be
enabled.)
Loading Waves for VHDL Simulations
• Check the Open EPWave after run checkbox.

• Specify the Top entity to simulate.
• Click Run. After the run completes, the resulting waves will load in a new EPWave window. (Pop-ups must be
enabled.)
– The waves for all signals in the specified Top entity and any of its components will be dumped.
– In EPWave window, click Get Signals to select the signals to view.
1.4.2 Verilog Synthesis on EDA Playground
1.5 Settings & Buttons
1.5.1 Adding Files
EDA Playground supports up to 10 files. The files may be HDL source files, or text files to be used as inputs to the
testbench.
To add a file, click the + sign in the testbench or design pane. Then create a new file or upload an existing file. The
filename may not contain special characters.
Simulating code with multiple files
• For SystemVerilog, use include statements such as the following to include the added source files in the compile:
`include "adpcm_seq_item.svh"
• For VHDL, all files with the .vhd and .vhdl extensions are automatically included in the compile.
• For Python, use import statements:
from design import *
To rename a file, double click the tab name. (The initial testbench and design files cannot be renamed.)
1.5.2 Sidebar Options
EDA Playground provides many options that can be configured for running your code.

Languages & Libraries
This section allows selection of coding languages and the available libraries for those languages.
Testbench + Design
The testbench (left editor pane) and design (right editor pane) may be written using one of these languages:
• Verilog/SystemVerilog for both
• VHDL for both
• e for testbench, and SystemVerilog/Verilog for design
1.5. Settings & Buttons 13

• Python for testbench, and SystemVerilog/Verilog for design

• Python for both
UVM / OVM (SystemVerilog)
When language is Verilog/SystemVerilog, a UVM or OVM library can be used for both the design and testbench. The
following libraries are available:
• UVM 1.2
• UVM 1.1d
• OVM 2.1.2
Other Libraries (SystemVerilog/Verilog)
When language is Verilog/SystemVerilog, other Verilog libraries can be used for both the design and testbench. These
libraries may be used along with UVM/OVM. Multiple libraries may be selected at the same time. Ctrl+Click to select
multiple libraries. Available libraries:
• OVL 2.8.1
• SVUnit 2.11
• ClueLib 0.2.0
• svlib 0.3
Libraries (VHDL)
When language is VHDL, the following VHDL libraries can be used for both design and testbench.
• OVL 2.8.1
• OSVVM 2014.01
Top entity (VHDL)
When language is VHDL, the top entity of the design must be specified before running a simulation.
Specman
When testbench language is e, one of the following Specman versions must be used.
• Specman 2014.10
Libraries (C++)
When language is C++/SystemC, the following libraries can be used for both design and testbench.
• SystemC 2.3.1
• SystemC 2.3.0

Methodology (Python + Verilog or Python only)
When testbench language is Python and design language is Verilog/SystemVerilog, the following verification environ-
ments are available:
• cocotb 0.4
• cocotb 0.3
• cocotb 0.2
When testbench and design language is Python, the following methodologies are available:
• MyHDL 0.8
• Migen X
Migen Before running synthesis on a Migen design, the Top class corresponding to the top module must be specified.
The Top class is the class instantiation to use when converting the Migen design to Verilog. Some examples:
• MyModule()
• Divisor(4)
• MyMemory(16, 2**12, init=list(range(20)))
Tools & Simulators
For running the code, several tools/simulators may be selected. Many simulators have additional options that may be
specified. Any options needed for languages and libraries will automatically be included.
Open EPWave after run
Checking this option will open EPWave wave viewer in a new window after the simulation run completes (pop-ups
must be enabled). It is available for all simulators that have a run step.
Download files after run
Checking this option will download the run directory as a ZIP file after the simulation run (pop-ups must be enabled).
The simulation run does not have to be successful for the download to occur. The ZIP file will include all the code
files as well as any generated files such as wave dumps, log files, etc.
YouTube video: How to download code and results from EDA Playground

Riviera-PRO EDU
Additional command-line compile options and run options may be specified in the bottom textboxes.
The Run Time option can be used to specify the number of timesteps for the simulation to run. By default, the
simulation runs forever until it hits a breakpoint or $finish.
The Use run.do Tcl file option is for using a custom run.do DO file for specifying simulation commands.
Riviera-PRO Compile Options for SystemVerilog/Verilog For SystemVerilog and Verilog simulations, Riviera-
PRO compile options are prepopulated with -timescale 1ns/1ns -sv2k9 and run options are prepopulated with +ac-
cess+r
Riviera-PRO Compile Options for VHDL For VHDL simulations, Riviera-PRO compile options are prepopulated
with -2008
Icarus Verilog
Icarus Verilog 0.9.7 and Icarus Verilog 0.9.6 compile options are pre-populated with -Wall
Icarus Verilog 0.10.0 compile options are prepopulated with -Wall -g2012
An example of custom compile and run options is here: http://www.edaplayground.com/s/4/202
Note: When using Migen co-simulation, the compile/run options are not available.
GPL Cver
Currently, no additional options for this simulator are available.

VeriWell
Currently, no additional options for this simulator are available.
C++
This is a g++ Linux compiler for C++. It is used for C++ and SystemC runs.
Csh
This is a standard Csh (C Shell) interpreter. Currently, no additional options are available for Csh.
Perl
This is a standard Perl compiler. Currently, no additional options are available for Perl.
Python
This is a standard Python compiler. It is only used for MyHDL when both testbench and design are written in Python.
Currently, no additional options are available for Python.
Yosys
Yosis is a synthesis tool for performing logical synthesis and creating a netlist. It supports using ABC to synthesize
for a sample cell library.
Yosys will only process code in the right Design pane. The code in the left Testbench pane will be ignored.
UVM/OVM/Methodology/Libraries selections are also ignored.
The following synthesis options are available:
• use ABC with cell library - synthesize for a demo cell library using ABC
• memory -nomap - skip memory_map step
• fsm -nomap - skip fsm_map step
• skip FSM step
• Show diagram after run - open the generated circuit diagram after synthesis flow completes (pop-ups must be
enabled).

When using Yosys with Migen, the Top class must be specified, which is used to convert Migen design to Verilog.
When using Yosys with MyHDL, the Testbench pane must contain code to convert MyHDL design to a Verilog file.
The Verilog file must have suffix .v, and can be named anything EXCEPT tb_* or a Verilog reserved keyword. Thus,
when running Yosys on MyHDL code, the Testbench code will be run first before synthesis.
VTR
Verilog-to-Routing is a complete physical design flow that includes elaboration, logical sysnthesis, FPGA technology
mapping, packing, placement, and routing. The recommended architecture file k6_frac_N10_mem32K_40nm.xml is
used for the flow. In addition, route channel width is set at a high 100 to ensure no routing issues with dense designs.
VTR will only process code in the right Design pane. The code in the left Testbench pane will be ignored.
UVM/OVM/Methodology/Libraries selections are also ignored. Currently, no additional options are available for
VTR.
Currently, VTR cannot be used with MyHDL or Migen.
Details
The options in this section are only used when saving the playground.
Name
A brief name/title of the playground. Visible by others when they open a saved playground.
Description
A longer description of the playground. Visible by others when they open a saved playground.
Public
Whether this playground should be publicly accessible after being saved. When checked, anyone will be able to view
this playground. When unchecked, only the creator will be able to view the playground.
Examples
Links to code examples created on EDA Playground. Some examples may have additional documentation provided in
the (docs) link.

1.5.3 Editor Modes and Shortcuts
The editor supports the following modes:

• Default
• Vim
• Emacs
The user may select the mode in the User Options on the user page:
Note that Vim and Emacs modes are only loose approximations of the actual bindings.
Default Mode
The default mode comes with search/replace functionality. The keybindings are:
• Ctrl-F / Cmd-F - Start searching
• Ctrl-G / Cmd-G - Find next
• Shift-Ctrl-G / Shift-Cmd-G - Find previous
• Shift-Ctrl-F / Cmd-Option-F - Replace

• Shift-Ctrl-R / Shift-Cmd-Option-F - Replace all

The default mode uses the following shortcuts. Note that the shortcuts are different for PC and MAC users.
// For All
keyMap.basic = {
"Left": "goCharLeft", "Right": "goCharRight", "Up": "goLineUp", "Down": "goLineDown",
"End": "goLineEnd", "Home": "goLineStartSmart", "PageUp": "goPageUp", "PageDown": "goPageDown",
"Delete": "delCharAfter", "Backspace": "delCharBefore", "Tab": "defaultTab", "Shift-Tab": "indentAu
"Enter": "newlineAndIndent", "Insert": "toggleOverwrite"
};
// For PC
keyMap.pcDefault = {
"Ctrl-A": "selectAll", "Ctrl-D": "deleteLine", "Ctrl-Z": "undo", "Shift-Ctrl-Z": "redo", "Ctrl-Y":
"Ctrl-Home": "goDocStart", "Alt-Up": "goDocStart", "Ctrl-End": "goDocEnd", "Ctrl-Down": "goDocEnd",
"Ctrl-Left": "goGroupLeft", "Ctrl-Right": "goGroupRight", "Alt-Left": "goLineStart", "Alt-Right": "
"Ctrl-Backspace": "delGroupBefore", "Ctrl-Delete": "delGroupAfter", "Ctrl-F": "find",
"Ctrl-G": "findNext", "Shift-Ctrl-G": "findPrev",
"Ctrl-[": "indentLess", "Ctrl-]": "indentMore",
fallthrough: "basic"
};
// For MAC
keyMap.macDefault = {
"Cmd-A": "selectAll", "Cmd-D": "deleteLine", "Cmd-Z": "undo", "Shift-Cmd-Z": "redo", "Cmd-Y": "redo
"Cmd-Up": "goDocStart", "Cmd-End": "goDocEnd", "Cmd-Down": "goDocEnd", "Alt-Left": "goGroupLeft",
"Alt-Right": "goGroupRight", "Cmd-Left": "goLineStart", "Cmd-Right": "goLineEnd", "Alt-Backspace":
"Ctrl-Alt-Backspace": "delGroupAfter", "Alt-Delete": "delGroupAfter", "Cmd-F": "find",
"Cmd-G": "findNext", "Shift-Cmd-G": "findPrev",
"Cmd-[": "indentLess", "Cmd-]": "indentMore",
fallthrough: ["basic", "emacsy"]
};
keyMap.emacsy = {
"Ctrl-F": "goCharRight", "Ctrl-B": "goCharLeft", "Ctrl-P": "goLineUp", "Ctrl-N": "goLineDown",
"Alt-F": "goWordRight", "Alt-B": "goWordLeft", "Ctrl-A": "goLineStart", "Ctrl-E": "goLineEnd",
"Ctrl-V": "goPageDown", "Shift-Ctrl-V": "goPageUp", "Ctrl-D": "delCharAfter", "Ctrl-H": "delCharBef
"Alt-D": "delWordAfter", "Alt-Backspace": "delWordBefore", "Ctrl-K": "killLine", "Ctrl-T": "transpo
};
1.5.4 Buttons
Log In
The user must be logged in to save or run playground code. Playground code and results may be viewed without
logging in.
Run
Shortcut: Ctrl+Enter
Run the current code using the selected tool/simulator and options. The code runs on the EDA Playground server and
the results are printed in the bottom Results pane.

Save
Shortcut: Ctrl+S
Save the current playground, including code, bottom 200 lines of results, and options. Once the playground is saved,
the page reloads. The location specified in the address bar is a static link to this playground – this link can be shared
with others.
If the playground has been saved previously, clicking on Save updates the currently saved playground. The static link
does not change.
If you modified a code example but did not save, you’ll see an asterisk in the Save button.
Copy
This button shows up for everyone when viewing a saved playground. Clicking on it creates a new copy of the current
playground. The copy will be complitely separate from the original, and it will have its own link that can be shared
with others.
If you modified a code example but did not save, you’ll see an asterisk in the Copy button.
Share
This button only shows up for saved playgrounds. It displays a modal pop-up with a static link to the current play-
ground. Also, it displays buttons for sharing on Twitter, Facebook, or LinkedIn.
Collaborate
Allows real-time collaborations where multiple users can edit code simultaneously.
Real-Time Collaboration Intro on YouTube.
About
Links to EDA Playground documentation (these pages).
Apps
Shows links to other apps available on EDA Playground, such as EPWave.
1.6 Yosys Circuit Diagrams
NOTE: Multiple top-level design modules are not supported by Yosys Cicruit Diagrams.
1.6. Yosys Circuit Diagrams 21

The Yosys synthesis flow can create circuit diagrams.

• Square boxes are cells. Outputs on the right, inputs and unrecognized ports on the left. The first line of text in
the box in the cell name, or _<number>_ for internal cells. The 2nd line is the cell type. Internal cell types start
with a dollar sign. (There is a chapter in the manual about the internal cell library used in yosys.)
• Diamond-shaped nodes are wires that are not ports. Octagon-shaped nodes are ports.
• Elliptical nodes are constant drivers. The label has the format <width>’<bits> or simply <number> for 32 bit
integers.
• Boxes with round corners with lines such as 0:0 - 42:42 are used to break out and re-combine nets from busses.
So for example
wire [3:0] a, b;
wire [7:0] y = {a,b};
will create the following box:
The numbers tell you which bits on which side are connected. for example ‘3:0 - 7:4’ means that the bits 3:0
from the left net are connected to bits 7:4 from the right net. Usually the box has a single connection on one
side and individual connections on the other side. When such boxes are connected to each other or to a cell port,
the connections have little diamonds on the ends instead of arrows. That’s because its not an actual connection
in the sense of the internal RTLIL netlist format.
• For a detailed explanation, see Yosys Application Note 011: Interactive Design Investigation

1.7 Tutorials and Code Examples
1.7.1 Verilog Tutorials and Examples
Doulos Verilog Knowhow - Free Verilog Technical Resources
http://www.doulos.com/knowhow/verilog_designers_guide/
D Flip-Flop (DFF)
Code located at: Verilog D Flip-Flop

This example demonstrates the design and verification of a simple D flip-flop (Wikipedia link).
Design
The DFF module has the following pins:

Name Type Description
clk input the clock; rising edge of the clock captures the value
reset input asynchronous reset; when reset is high, the DFF output q is 0
d input the main input
q output the d value captured at the last rising clock edge
qb output inverted version of q
Testbench
The testbench is a simple directed test which toggles the DFF inputs and displays the outputs to the console.
The reg signals are used to drive inputs, and wire signals are used to observe outputs:
reg clk;
reg reset;
reg d;
wire q;
wire qb;
The DFF design is instantiated:

dff DFF(.clk(clk), .reset(reset),
.d(d), .q(q), .qb(qb));
The initial block contains the actual test. First, reset is driven to 1 to reset the flop, while d is driven with an X:
clk = 0;
reset = 1;
d = 1'bx;
From the console display, we see that the flop has been properly reset with q == 0
Reset flop.
d:x, q:0, qb:1
1.7. Tutorials and Code Examples 23

Next, reset is released, while input d is driven to 1:

d = 1;
reset = 0;
The output q remains at 0 because the design did not see a rising edge of clk and did not capture the d input:
Release reset.
d:1, q:0, qb:1
Finally, we drive clk to 1 to create a rising edge:

clk = 1;
Now we see q output change to match the d input:

Toggle clk.
d:1, q:1, qb:0
Note: Before calling the $display task, we always tell simulation to proceed for 1 time unit #1 to allow the output
signals to propagate.
Ripple Carry Counter
Code located at: Verilog Ripple Carry Counter
$display System Task
Code located at: Verilog $display System Task
‘define Text Macros
Code located at: Verilog ‘define Text Macros
Port Declaration & Connection
Code located at: Verilog Module Ports for Ripple Carry Counter
Ripple Carry Full Adder
Code located at: Verilog Ripple Carry Full Adder
Blocking and Nonblocking Assignments
Code located at: Verilog Blocking and Nonblocking Assignments
always @ event wait
Code located at: Verilog always @ event wait

if-else conditional and case statements
Code located at: Verilog if-else and case statements
Parameters
Code located at: Verilog Parameter
Generate Blocks
• The StackOverflow question mentioned in this Verilog tutorial: http://stackoverflow.com/questions/18153405/parameterized-

number-of-cycle-delays-in-verilog
• The generate example from the StackOverflow question: Delay with Verilog generate
• The generate conditional example from this Verilog tutorial: Verilog generate conditional
Verilog Tutorials on YouTube
1.7.2 SystemVerilog Tutorials and Examples
Doulos SystemVerilog Knowhow - Free SystemVerilog Technical Resources

Doulos UVM Knowhow - Free UVM Technical Resources including Doulos *Easier UVM*
SystemVerilog Interview Questions on YouTube
1.7.3 UVM (Universal Verification Methodology) Tutorials and Examples
Doulos UVM Knowhow - Free UVM Technical Resources
UVM Hello World Tutorial on YouTube

What’s New in UVM 1.2 on YouTube
1.7.4 Specman e Tutorials and Examples
Hello e World Video Tutorial
1.7.5 SystemVerilog Unit Testing (SVUnit) Tutorials and Examples
Hands-on SVUnit Tutorial
Time to learn the basics of unit testing with SVUnit!

Edit the code and run it here: Hands-on SVUnit Tutorial on EDA Playground
Here’s a simple set of unit tests for an interface called svunitOnSwitch. The purpose of the design is to offer a
few utility functions as well as to operate an on/off output.
The API of the svunitOnSwitch is as follows:

output logic on;

function logic true();
function logic false();
function int return43();
turn_on();
turn_off();
The svunitOnSwitch is defined as:

interface svunitOnSwitch (
output logic on
);
initial on = 'hx;
function logic true();

// no implementation yet
endfunction
function logic false();

endfunction
function int return43();

endfunction
function void turn_on();

endfunction
function void turn_off();

endfunction
endinterface
The SVTESTs below are the acceptance unit tests that verify the functionality of the svunitOnSwitch. If you
run the tests on EDA Playground you’ll see all the tests fail because none of the svunitOnSwitch functionality is
implemented. Your job is to build a complete svunitOnSwitch, one requirement at a time, by:
• examining the requirement defined in the unit test
(HINT: a unit test is marked by the ‘SVTEST macro)
• implementng the corresponding code in the svunitOnSwitch
(HINT: watch for the “no implementation yet” comment)
• running the test suite to make sure your implementation satisfies the unit test
When you’ve gone through all the tests and your entire test suite passes, you’re done! You’ve verified the
svunitOnSwitch and learned the basics of SVUnit!
Ready... set... go!
Edit the code and run it here: Hands-on SVUnit Tutorial on EDA Playground
`include "svunit_defines.svh"
import svunit_pkg::*;
module svunitDemo_unit_test;
`SVUNIT_TESTS_BEGIN

//------------------------------
// test: true_test
// the true() function should
// return 1
//------------------------------
`SVTEST(true_returns_1)
`FAIL_UNLESS(uut.true() === 1);
`SVTEST_END
//------------------------------
// test: false_test
// the false() function should
// return 0
//------------------------------
`SVTEST(false_returns_0)
`FAIL_UNLESS(uut.false() === 0);
`SVTEST_END
//-----------------------------------
// test: return43
// The function return43() returns
// a value. this test should fail
// if that doesn't happen.
//-----------------------------------
`SVTEST(return43)
`FAIL_UNLESS(uut.return43() === 43);
`SVTEST_END
//---------------------------------
// test: turn_on
// our uut has an output pin
// called 'on' that we can
// assert via turn_on()
//---------------------------------
`SVTEST(turn_on)
uut.turn_on();
`FAIL_UNLESS(uut.on === 1);
`SVTEST_END
//---------------------------------
// test: turn_off
// we can turn 'on' off using
// turn_off() method
//---------------------------------
`SVTEST(turn_off)
uut.turn_off();
`FAIL_UNLESS(uut.on === 0);
`SVTEST_END
/*
----------------------------------------
----------------------------------------
For more SVUnit, Remember to visit:

www.AgileSoC.com/svunit
And try the other SVUnit examples at:
www.edaplayground.com
----------------------------------------
----------------------------------------
*/
`SVUNIT_TESTS_END
string name = "svunitDemo_ut";

svunit_testcase svunit_ut;
//===================================
// This is the UUT that we're
// running the Unit Tests on
//===================================
svunitOnSwitch uut();
//===================================
// Build. Runs once
//===================================
function void build();
svunit_ut = new(name);
endfunction
//===================================
// Setup for running the Unit Tests
// Runs before every SVTEST.
//===================================
task setup();
svunit_ut.setup();
/* Place Setup Code Here */
endtask
//===================================
// Here we deconstruct anything we
// need after running the Unit Tests
// Runs after every SVTEST.
//===================================
task teardown();
svunit_ut.teardown();
/* Place Teardown Code Here */
endtask
endmodule
You can do a lot more than test a simple svunitOnSwith with SVUnit. When you’re ready to test your own design
and testbench IP visit: http://www.AgileSoC.com/svunit

SVUnit Examples on YouTube
1.7.6 VHDL Tutorials and Examples
Doulos VHDL Knowhow - Free VHDL Technical Resources
VHDL Basic Tutorials on YouTube
1.7.7 cocotb Tutorials and Examples
Endian Swapper Design and Testbench Tutorial
1.8 Privacy Policy
This Privacy Policy governs the manner in which Doulos, Ltd. collects, uses, maintains and discloses information
collected from users (each, a “User”) of the http://www.edaplayground.com website (“Site”).
Personal identification information
We may collect personal identification information from Users in a variety of ways, including, but not limited to, when
Users visit our Site, register on the Site, and in connection with other activities, services, features or resources we
make available on our Site. Users may be asked for, as appropriate, email address. Users may, however, visit our
Site anonymously. We will collect personal identification information from Users only if they voluntarily submit such
information to us. Users can always refuse to supply personally identification information, except that it may prevent
them from engaging in certain Site related activities.
Non-personal identification information
We may collect non-personal identification information about Users whenever they interact with our Site. Non-
personal identification information may include the browser name, the type of computer and technical information
about Users means of connection to our Site, such as the operating system and the Internet service providers utilized
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Web browser cookies
Our Site may use “cookies” to enhance User experience. User’s web browser places cookies on their hard drive for
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How we use collected information
Doulos, Ltd. may collect and use Users personal information for the following purposes:
• To improve customer service
Information you provide helps us respond to your customer service requests and support needs more efficiently.
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We may use information in the aggregate to understand how our Users as a group use the services and resources
provided on our Site.
• To improve our Site
We may use feedback you provide to improve our products and services.
1.8. Privacy Policy 29

• To run a promotion, contest, survey or other Site feature

To send Users information they agreed to receive about topics we think will be of interest to them.
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Users may receive emails that may include company news, updates, related product or service information, etc.
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Contacting us
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contact us at: http://www.doulos.com
This document was last updated on April 1, 2015

EDA Playground on YouTube - Tutorials for Verilog, SystemVerilog, UVM, and VHDL, interview questions, news
and features, etc.
EDA Playground web application located at http://www.edaplayground.com/

EPWave documentation located at http://epwave.readthedocs.org
1.8. Privacy Policy 31

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December 21, 2016

1.1.1 Account Validation and Logging In

How do I validate my account?

Which simulators require account validation?

What can I do without account validation?

I am looking into this.

I didn’t receive your email, what can I do?

Why is account validation necessary?

How do I log in if I don’t have a Google or Facebook account?

1.1.2 Using EDA Playground

How do I start a blank playground design?

How Can I search for one of my Playgrounds?

2 Chapter 1. Table of Contents:

How can I publish one of my Playgrounds?

How Can I search for one of someone else’s Playgrounds?

What if I accidently delete a playground? Can I get it back?

How do I get updates about new EDA Playground features?

What are the resource limits for running my code?

Each run is limited to 60 seconds runtime and 100MB of memory.

Which web browsers are supported?

I have more questions. How do I get support?

1.2 EDA Playground Help

1.2.1 Quick Start

1.2.2 What is EDA Playground?

4 Chapter 1. Table of Contents:

1.2.3 Example Usecases

• Quick prototyping – try out syntax or a library/language feature.

1.2.4 Tools & Simulators

1.2. EDA Playground Help 5

Compilers and Interpreters

1.2.5 Libraries & Methodologies

6 Chapter 1. Table of Contents:

SystemVerilog and Verilog

• UVM - Universal Verification Methodology

* What’s New in UVM 1.2 on YouTube

• OVL - Open Verification Library

• SystemC - system level design and simulation in C++

1.2. EDA Playground Help 7

• MyHDL - a Python based hardware description language (HDL)

1.2.6 What Users are Saying

1.2.7 Support, Feature Requests and Bug Fixes

Support available on EDA Playground forum

8 Chapter 1. Table of Contents:

1.2.8 News and Site Updates

EDA Playground is maintained by Doulos.

1.3.1 Logging in with either Google or Facebook

1.3.2 Validating your Account

1.3.3 Doulos Online Training Customers

Which simulators require account validation?

What can I do without account validation?

I am looking into this.

I didn’t receive your email, what can I do?

Why is account validation necessary?

How do I log in if I don’t have a Google or Facebook account?

This Quick Start is intended for users of http://www.edaplayground.com.

10 Chapter 1. Table of Contents:

1.4.1 Loading Waves from EDA Playground

Loading Waves for SystemVerilog and Verilog Simulations

Loading Waves for VHDL Simulations

• Check the Open EPWave after run checkbox.

1.4.2 Verilog Synthesis on EDA Playground

1.5 Settings & Buttons