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Abstract
V
2 C3
Z Z
1
I DC1 T1,1 LG
I DC L1 Rp
I DC 2 D1,1 c1 Vc H1 VH 1
T1, 2 1
VGRID
VDC IG
m1
D1, 2
Buck 1
T2,1
L2 Vout
D 2 ,1 c 2 Vc H2 VH2
T2,2 2
D2,2
Buck 2
m2
Fig. 2.- Single DC 9-Levels DC/AC Hybrid Proposed Topology
To achieve the continuous high impedance states
Although the high number of level helps to between VC1 and VC2 tensions generated by the Bucks
thoroughly decrease THD, the total number of switches and converters, as detailed in the next section.
the need of various high-frequency transformers put this
option out of residential renewable energy generation. 2.1.- Isolated Bucks Converters
The topology [9] showed an interesting modification
of a 3-levels Buck converter with two DC sources in series in Using the example of converter Buck1 of Fig. 2, the
cascade with an H-bridge. This topology is based on the use proposal modification consist on add an additional power
of two DC sources in series; such condition can be seen as an switch in Buck converter (T1,2), opening the ground node of
advantage because non-isolated DC sources are no longer the circuit of VDC source. In addition, a diode D1,2, is added in
required as is the case for converters with cascaded cells. series with T1,2 in order to ensure the flow of current only in
Worth to mention that, in addition to the use of a DC direction the collector-emitter of T1,2 power switch.
source, it is necessary: 1) extra DC-DC converters; 2) As shown on Fig. 1 in Buck1 converter, the
voltage/current monitoring; and 3) it is necessary additional commutation states of the switches T1, 1 and T1, 2 are
PWM control. All together decreases reliability and increases controlled in parallel by the modulation variable m1, while
complexity and cost of the converter. If the DC sources are T2,1 and T2,2 are controlled by m2, on Buck2 converter.
replaced with capacitors, the unbalance between DC levels The PWM pulses, m1 and m2, are generated based on
can increase the harmonic distortion at the output. the magnitude comparison between D1, D2 and carry1,
In [10] the author presents the proposal of a seven carry2, variables shown in equations 1 and 2, using a
levels DC-AC converter, based on only a DC source, eight switching frequency, FCBuck
power switches and application of a high frequency
transformer, it should be noted that the number of switches is 1 when D1 ! Carry1 (1)
lower compared to flying capacitor and clamping diode m1 ®
¯0 when D1 Carry1
topologies, for the same number of voltage levels, but the
application of a transformer increases the cost and reduces the
1 when D2 ! Carry2 (2)
power density of the proposal. m2 ®
This paper introduces a novel multilevel hybrid ¯0 when D2 Carry2
topology conversion which integrates two basic topologies,
DC/DC Buck converter and DC/AC Multilevel hybrid From 1 and 2 we can deduce a number of topology
cascaded cell, to obtain a 9-levels DC-AC structure using a combinations between Buck2 and Buck1 converters, as shown
single DC input for a single-phase output, whit only 12 power in Table I.
switches. The actual research considering a transformerless
architectures in order to reduce costs, weight and improve the TABLE I
COMMUTATION FUNCTIONS FOR BUKS CONVERTERS
efficiency. Topological
State m1 m2 IL1 IL2 ID1 ID2
2 Operation principle i) 0 0 ΔIL1off ΔIL2off 0 0
ii) 1 0 ΔIL1on ΔIL2off ΔIL1on 0
The main objective of this proposal, is the generation iii) 0 1 ΔIL1off ΔIL2on 0 ΔIL2on
1 1 Prohibited
of two isolated DC sources, named VC1 and VC2, from a single
power supply VDC, without use of transformers , these isolated
DC sources are required for the proper performance of As seen in Table I, the Buck converters can take a
cascaded cells topology. To achieve this objective this paper series of topological combinations, considering that switching
proposes the modification in structure of conventional DC / variables m1 and m2 do not acquire state 1 at the same instant
DC Buck Converter, without producing changes in the of time, which has been termed as a prohibited state for this
operating principle. The purpose of this modification is to application.
generate time-lapse high impedance between each Buck
converter and the power supply VDC.
2
Figures 3 and 4 shows the main topological states Parallel to this process on the current IDC2 in the
proposed for the Bucks converters, specifically Fig. 3 shows Buck2 converter, flows from the power supply VDC, followed
the topological state ii) of table I, which meets the switching by collector to emitter of T2,1 switch, then the L2 inductance
state m1 = 1, where the Buck1 converter, acquiring ΔIL1on towar the capacitor C2, closing the circuit to ground through
current state, which is dependent on the potential difference D2,2 and emitter to collector of switch T2,2.
between VDC and VC1 as shown in equation 3: It is observed that this mesh diode D2,1 is not
polarized, the topological state described (ΔIL2on ) fulfilling by
1
t1on
VDC Vc1 VDC Vc1 t1on I q (3)
Equation 6:
'I L1on
T ³ L1
dt I Lq1
L1 T
L1
0
1
t2 on
VDC Vc2 VDC Vc2 t2on I q (6)
'I L 2on
T ³ L2
dt I Lq 2
L2 T
L2
From Fig. 3, can be deduced that current IDC1 flows 0
In Fig. 3, referring to Buck2 converter, it can be seen Note that this switching state is complementary to
that the T2,1 and T2,2 switches are on open condition, due to state ii) in Table I. The VDC power supply is directly
m2 = 0, in this way, a high impedance state is generated connected to the voltage VC2, but in a state of high impedance
between the positive and negative source terminals VDC and voltage VC1, we concludes again there is no direct connection
the level of voltage VC2, where the current IL2, flows from the between VC1 and VC2.
positive terminal of the inductance to the cathode of the diode Finally the topological state i), of the switching table
D1,1 to the negative terminal of the capacitor C2. I, can be defined as dead time and total disconnection of the
power supply VDC with the VC1 and VC2 voltage where the
T1,1 Buck1 and Buck2 converters acquired a complementary
I DC I DC1 L1 behavior, as Indicated in the equations 4 and 5.
c1 Figure 5 shows the main waveforms involved in the
T1, 2
D1,1
' I L1on
H1 process of DC-DC conversion, to generate two voltage
VDC sources isolated from one.
D1, 2
The carry1 and carry2 variables are displayed by Fig.
T2,1 L2 5 a) and d) respectively, in which is seen a 180° of constant
phase shift, the control pulses coming from the comparison in
D2,1 c2 H2 magnitude between the carry1 and carry2 signals and m1 and
T2,2 'I L2off m2 variable modulation are shown in Fig. 1 b) and e), which
D2,2 can be seen complementary behavior, and dead time between
the rising and falling edges, where the generation of m1 and
Fig. 3.- topological state ii), m1=1, m2=0. m2 is based on equations 1 and 2. These pulses are applied
Note that in this commutation state, the VDC power directly to control circuit breakers, being T1,1 and T1,2
supply is directly connected to the voltage VC1, but in a high controlled by m1 and T2,1 and T2,2 controlled by m2, as
previously indicated.
impedance state with VC2 voltage, we concluded that there is
Currents IL1 and IL2 inductances are shown in red
no direct connection between VC1 and VC2.
color on Fig. 5 c) and f), which can be observed continuous
Moreover, Fig. 4 shows the next commutation stage
iii), of the Table I, which shows that the converter Buck1 is in conduction mode behavior, at the same figure, in blue color
state ΔIL1off current, where this current is dependent only of are shown the waveforms of current IDC1 and IDC2 generated in
voltage VC1, and the initial condition IL1°, as described in 5: each Buck converter, which are depend on the product of the
inductance current , and control drive variable m1 and m2, as
t2 off is stated in the equations 7 and 8.
1 Vc2 Vc2 t2off (5)
'I L 2off ³ dt I Lq 2 I Lq 2 I DC1 I L1 m1 (7)
T L2 L2 T
0
I DC 2 I L 2 m2 (8)
3
In addition the hybrid topology has no need of
Carry 1 capacitors or transformers for its basic operation. As
a) D1 consequence, using the latter configuration an arbitrary
waveform can be reproduced with lower harmonics distortion
T t1on t than with other multilevel topologies.
m1 The generation of different voltage levels in Vout of
b)
I L1 the cascade cell converter are shown on Fig. 7, this voltages
t
are obtained based on the algebraic sum of voltages VC1 and
c) I DC1 VC2 as shown in Table II, where H1 and H2 bridges generate
t combinations independent of voltage versus time, being VH1 є
Carry2
{+ VC1, 0, - VC1}; and VH2, є {+ VC2, 0,- VC2}; respectively.
d) D2 The generations of these voltage levels are
t2on t performed based on switching states in Table II.
T
m2
e) TABLE II
SWITCHING STATES AND RESPECTIVE VOLTAGE LEVELS
I L2 t Vout H1 H2
Level S1,1 S1,2 S1,3 S1,4 S2,1 S2,2 S2,3 S2,4
I DC 2
f) Vc1+Vc2 1 0 0 1 1 0 0 1
t Vc1 1 0 0 1 1 0 1 1
m1 1
I DC Vc2 1 0 0 1 0 1 1 1
g) Vc1-Vc2 1 0 1 0 1 0 0 1
0 1 0 1 0 1 0 1 1
m1 1 m1 0 m1 0
t -Vc1+Vc2 1 0 1 0 0 1 1 1
m2 0 m2 0 m2 1 -Vc2 0 1 1 0 1 0 0 0
-Vc1 0 1 1 0 1 0 1 0
Fig.- 5 Principal waveforms for Buck1 and Buck2 converters
-Vc1-Vc2 0 1 1 0 0 1 1 0
Vb
respectively.
-0.5 p.u.
Va
To obtain the correct control pulses applied to the
inverter power switches in cascade, is necessary to implement
-1 p.u.
Va Vb a multilevel modulation SPWM process, which is discussed
in the next section.
Fig 6.- Multilevel Vout for cascaded hybrid converter.
4
2.3.- Nine Levels SPWM Modulation TABLE III
PARAMETER VALUES FOR THE SIMULATION OF THE PROPOSED CONVERTER
The multilevel modulation process employed for the Switching frequency Bucks 16kHz
topology in Fig. 8, is obtained based on the magnitude L1=L2 6mH
comparison between eight modulating waves carry-j and C1=C2 2200uF
carry+j where j є (1,2,3,4) with a modulating signal mi. VDC 200v
2
5
5
and VC2 voltages, IL1 and IL2 current waveforms are shown by
C1
1
5 Fig. 1 b) and c) respectively, and checking the performance of
15 t C1 these variables on the basis of equations 3,4,5 and 6.
25
C2
35
C3
1
a)
C4
1 when carryi ! mi (12)
°
ci ®
°̄0 when carry mi
i
In order to obtain the necessary topological stages, Fig 10.- IL1 and IL2 currents for Bucks converters.
described by the table II, the combinational logic stage are
necessary to obtain the necessary pulses for the cascaded The waveforms of current IDC1 and IDC2 generated by
multilevel converter, The logical diagram implemented are each Bucks converters, are shown in Fig 11 a) and b),
shown in the figure 9. respectively, which can be checked again alternating
switching times between each converter.
C1 C2
C1 C1
Finally the total current IDC supplied by the voltage
C1 C2 source VDC, is shown by Fig. 11 c), which is dependent on the
C2 Out 1 C3 Out 3 instantaneous sum of IDC1 and IDC2, fulfilling in equation 9.
C3 C4
C1 C2 Voltage levels output on stable state of the converters Bucks,
C1 C2
VC1 and VC2, are shown in Fig. 12 a), in this figure the relative
C1 C1
voltage for proper operation of the hybrid converter cascaded
C2 C3
Out 2 Out 4
cells is observed, as indicated by equation 10.
C3 C4
Fig 9.- Combinational logic for IGBT pulses, on cascaded cell topology
a)
In order to verify the full operation of the converter
stages, Buck converters and cascaded cells with their
respective modulations, a series of simulations have been
developed and presented in the next section. b)
3 Simulation
c)
The proposed converter is analyzed through the Saber
simulation platform, showing the main variables of voltage,
current and pulses control involved in the conversion process
of DC-DC through the Buck converters, and DC-AC through
hybrid cascade converter cells. Fig 11.- Current Waveform: a) IDC1 b) IDC2 c) IDC
5
The voltage waveforms generated by the H-Bridge
converters, VH1 and VH2 are shown in graphs 12 b) and c)
respectively, which can be seen, the topological combinations
versus time dependent modulation process, meeting the states
switching table II.
Finally the stepped waveform voltage Vout, is
shown by Figure 12 d), which is dependent on the algebraic
sum of the instantaneous VH1 and VH2 voltages.
a)
a) VH1 b) VH2
4 Experimental Test Fig. 15.- Independent H-Bridge voltajes.
In Figures 13 a) and b) can be corroborated experimentally Based on the voltages shown by Figures 15 a) and
modulation process of Buck1 and Buck2 converters
b), it is possible to corroborate the ratio of voltages between
respectively, showing the variables modulation m1 and m2,
VC1 and VC2 1:1.5, as stated by equation 10.
compared to current inductance IL1 and IL2, ending in the The algebraic sum of the VH1 and VH2, corresponding
currents supplied by the source IDC1 and ICD2. to the output voltage Vout is shown by Figure 16, where 16 a)
shows an experimental validation of staggered signal and Fig.
16 b) shows the same output signal SPWM modulation
applied.
a) m1, IL1 and IDC1 for Buck1 b) m2, IL2 and IDC2 for Buck2
Fig. 13. Principal wave forms for bucks converters.
Under the same case study, Fig 14 shows current IDC, which
corresponds to the sum of the currents IDC1 and IDC2 with a) Multilevel Vout b) SPWM Multilevel Vout
Fig. 16. Vout.
respect to the control pulse m1.
6
The multilevel voltage output Vout of the proposed explore the application possibilities related to the integration
converter still requires filtering to reduce THD and bring the of large photovoltaic fields.
signal closer to the ideal sinusoidal waveform. As the The authors expect that the step-up multilevel converter
frequency spectrum of the 3 and 5-level converter is wider introduced in this paper will become a useful alternative for
than the one of the 9-level, the filtering requirement of the research and development in the area of DC-AC converters.
latter are less demanding.
6 References
4.1.- Discussion
[1] Jih-Sheng Lai, Fang ZhengPeng, "Multilevel converters-
The Table IV shows the number of elements required for a new breed of power converters," IEEE Trans.Ind.
9-level DC/AC converters of different topologies. As can be Appl., vol.32, no.3, pp.509-517, May/Jun 1996.
notice, the 9-level converter presented in this work needs
fewer elements than the clamped diode and flying capacitor [2] Rodriguez, J.,Jih-Sheng Lai, Fang ZhengPeng,
configurations. "Multilevel inverters: a survey of topologies, controls,
Comparatively to the cascaded-cells topology, the novel and applications," IEEE Trans. Ind. Elec., vol.49, no.4,
9-levels converter is less complex in construction because it pp. 724- 738, Aug 2002.
uses only one power source instead of 2.
A general advantage of the proposed 9-levels converter [3] Tolbert, L.M.,Peng, F.Z , "Multilevel converters as a
over the other configurations is its relative simpler control utility interface for renewable energy systems," in 2000
algorithm, without the need of a transformer. These enhanced Power Engineering Society Summer Meeting, vol.2, no.,
features make the 9-levels converter introduced in this paper pp.1271-1274 vol. 2, 2000.
very suitable to application in micro-grids.
[4] Walker, G.R.,Sernia, P.C , "Cascaded DC-DC converter
TABLE III
connection of photovoltaic modules," in 2002 33rd
COMPARATIVE ANALYSIS FOR 9 LEVELS CD/CA
CONVERTERS .Annual Power Electronics Specialists Conference, vol.1,
No. No. No. no., pp. 24- 29 vol.1, 2002.
IGBTs Capacitors Diodes
Proposed Topology 12 2 6 [5] Gonzalez, R., Gubia, E., Lopez, J.,Marroyo, L.,
Clamped Diode 16 8 32 "Transformerless Single-Phase Multilevel-Based
Flying Capacitor 16 32 0 Photovoltaic Inverter," IEEE Trans. Ind. Electron.,
vol.55, no.7, pp.2694-2702, July 2008.
The solutions and capabilities proposed can be further
enhanced. Additional future advances from this work focus [6] Sung Geun Song, Feel Soon Kang, Sung-Jun Park,
on: i) Minimizing the voltage and current harmonic distortion "Cascaded Multilevel Inverter Employing Three-Phase
by means of a suitable modulation scheme, ii) Obtaining a Transformers and Single DC Input," IEEE Trans. Ind.
mathematical model of the dynamic behavior of the 9-level Electron., vol.56, no.6, pp.2005-2014, June 2009.
converter and its interaction with distribution grid and a
microgrids, iii) Evaluating the benefits of using various types [7] Zhong Du, Tolbert, L.M.,Ozpineci, B.,Chiasson, J.N.,
of LC and LCL filter for the interconnection of the 9-level "Fundamental Frequency Switching Strategies of a
converter with the grid, iv) Incorporating the converter to the Seven-Level Hybrid Cascaded H-Bridge Multilevel
Smart Grid concept, v) Analyzing the transient behavior of Inverter," IEEE Trans. Power Electron., vol.24, no.1,
the converter. pp.25-33, Jan. 2009.