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    Interrupt controller

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    Interrupt controller

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
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    11 views11 pages

    Patent 9575911

    Uploaded by

    jwrodgers
    Interrupt controller

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
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    of 11
    2) United States Patent ‘McMenamin et al. US00937S911B2 (a0) Patent No.: 4s) Date of Patent: US 9,575,911 B2 Feb. 21,2017 o om 0) o en @ 65) on 2 58) INTERRUPT CONTROLLER AND A METHOD OF CONTROLLING PROC OF INTERRUPT REQUESTS BY A PLURALITY OF PROCESSING UNITS Applicans-David MeMenamin, Glasgow (GB) ‘ames Andrew Collier Seele, Helensburgh (GB). Inventors: David McMenamin, Glasgow (GB) ames Andrew Collier Scoble, Helessburgh (GB) Assignee: NNPUSA, INC, Anstio, TX (US) Notice: Subject oany disclaimer. the tem of this patent is extended or adnate under 38 USC. 18405) by 488 days Appl. Nos 1472465832 Filed: Apr 7, 2014 Prior Publication Data US 201510286595 AL Ost. 8, 2015 Int. CL Gu6F 1100 (200601) GOP 1326 (200601) Goer 11720 (2006001) us. cee G06E 1326 (201300); GEE 1172069 (201801) GO6E 1172092 (2013.01): GaaF {1172094 (2013.01): GO6F 11/2089 (2013.01) (GO6P 2201808 201301) Field of Classifeation Search cee (GOGF 11/2092; Goo 11/2094; Gost 71/2069 GSP 11/2089; GOSF 1/1446; ‘GOGE 11/201; Gost 2201/805 ‘Se application file foe complete sexsi history eigen a. a sca ee oe eet ee OTHER PUBLICATIONS. Gountans, RJ. tl, “A Matha of Processor Selection for IneripeHaning in 4 Magrosesor Sytem,” Goansni and VISS: Proceso Selection fr lnterupt Handling. roeedags a the IEEE, vl 4 se 12, Dos 1966 pp. 1812-1819, * cited by examiner Primary Ksaminer — Eanes Une 6 ABSTRACT Aa inerupt controller for controlling processing of inter rupt requests by a plralily of processing unit Tho pro- ‘esting tts have at last two modes. an ative mode and fn inactive mode. "The intempt controller comprises 2 ‘controle ipo, an inten mer coupled to the coirller input and a monitoring un. The monitoring wnt outputs 3 routing change signal to the interrupt router it determines that a selected processing unt to Which, in response toa received infernipe request, an execution of an ieript Service routine Wasnialy routed isin inactive mode while 2 preselected one isin the eetive mode, The interop rove reroute the excetio ofthe interrupt service outine to the preseleted procesing unit 18 Claims, 4 Drawing Sheets U.S. Patent Feb. 21,2017 Sheet 1 of 4 US 9,575,911 B2 US 9,575,911 B2 Sheet 2 of 4 Feb. 21, 2017 U.S. Patent Fig. 4 U.S. Patent Feb. 21,2017 Sheet 3 of 4 US 9,575,911 B2 110 120 routing IR to a sel. CPU 130 140 ‘monitoring CPUs to 145 obtain RCS 150 Susp. exec. routing exec. IsRPL ISRto routing exec. is below preselected ISR toa threshold CPU if PL preselected Inge Fig. 5 U.S. Patent Feb. 21,2017 Sheet 4 of 4 US 9,575,911 B2 500 Fig. 6 US 9,575,911 B2 1 INTERRUPT CONTROLLER AND A METHOD OF CONTROLLING PROCESSING ‘OF INTERRUPT REQUESTS BY A PLURALITY OF PROCESSING UNITS LLD OF THE INVENTION This invention relates to an interrupt coatrllr and 10 2 method of controling processing of interrupt requests by a pluliyof processing unis. The invention further eats to S microprocessor hat incides said inert contol futomotive vehicle that inclades any of said intemup con- toller of microprocessor and. wa computer readable ‘medi BACKGROUND OP THE INVENTION When in operation, CPUs of microprocessors, such 38 general purpose microprocessors, mierbcontoles, digital Signal processors or other ypes of microprocessors perfonm 2 ‘eran task, sich asthe exeention of series of sie tions defined by, for example, computer program, Other devices or computer progrums can have the CPU perform requested services by peering interrupt requests An intr rp request may for example be transmit bya peripheral device of the microprocessor to the CPU. The interupt request may for example be seat by aa external memory device (extemal othe microprocessor, sch a. hark, to signal the completion of tsk, seh as a data tansfer fom for 0 the peripheral Also the intsrapt request may for txample be used to transmit information to the CPU Por instane, a system timer may periodically transmit interupt requests which can be used by the CPU to establish a Time-bave The inlerupt raquests are propagated to an intemupt controller via multiple intermpt request lines. Oace the Jnterrpt eonller identifies an aetive interrpt request ie, Stay grant he interrupt request and forward the interupt request tothe CPU. in response othe inteupt request the CPU will ntomupt the tsk being porfomed and perform a exqunce of seps, generally refered to as a interupt handler of interupt service routine, associated. with the requested iterypt. After handling the inerupt the CPU stu Gano eperatns) the previous ire However in case a CPU becomes unavailable, the han ding of the interrupts and of the processing sks essocieted to the corresponding interups cangot be guaranteed any~ more. For example, in appiations where safety may be ‘valved, suchas sutomosive applications there i @ need to provide fail safe or fail-opeational systems. In typical Injcroconitller or microprocessor units sed in sve ppl tations, CPU of the microcontroller microprocessor unit 5s shut dovsnor halted when the CPU becomes unavailable (eg. reduce power consumption inthe microcontroller or ‘wae a fal is detected inthe CPU of the microprocessor. ‘When the CPU is shut down o halted, the tasks handled by the processing unit are suspended, together with the pr cssing tink assessed with the interrpts handling, ‘Gountanis, RJ Viss, N.L-, “A method of processor selection for Imerrpt handling ina multiprocessor ssten™ Procoeding of the IEEE, vol. 84, m0. 12, pp- 1812-1819, December 1966 discloses @ method of assigning exteral terrps to CPUs in « multiprocessor sytem. hardware component called Tnternpt Diretory selects a most app priate CPU in the multiprocessor system according 10 an Interrupt Priority (1?) number associate with each possible 2 ‘extemal interop ontion ad an Intrrptibility ade (11) assigned to cach tas in every CPU of the multiprocessor System. Ifthe Intemupt print is greater dhan the Inverrupe- ibility Index, then the external intemupt is routed to a CPU ‘executing tsk with the eomesponding.Interruptbility Inde, A disadvantage of the disclosed multiprocessor system described in this document i that only the processing asks signaled with inerupts with igh priority are asighod in ‘he multiprocessor system based on comparison between the Interepe Priory (IP) and te Intrrpibility Index (0). Furthermore although the dselosed multiprocessor systems radistibutes the load between the CPUs inthe mutipoces- sor systems, i lacks safety funtinaliy. as desirable in far ‘example, in fail-operational systems. SUMMARY OF THE INVENTION ‘The present invention provides an interrupt controller, method of controlling processing of inteript request, & Iicroprocessor, an automotive vehele and a nn-tenstory ‘compiler readable medi st desenbed in the appended claims ‘Specific embodiments ofthe invention are set oth the dependent eins These and ater aspects ofthe invention willbe apparent from and elucidate with reference Wo the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS Purther dtl, specs and embodiments ofthe invention ‘will be describes, by way of example only, with slerence 2 the drawings FIG. 1 schematically shows a block diagram of & fst ‘cxample of a micmprocesson, FIG. 2 schematically shows a block diagram of second ‘oxample of a mictpmmcesso. FIG. 3 schematically shows block diagram of 2 thint ‘example of microprocessor. FIG. 4 schemutically shows a block diagram of a fount ‘example of a mieriprocesson. FIG. § schematically shows a Now diggram of a method of contolling processing of interrupt requests. FIG. 6 shows «computer readable medium. ements inthe figures are illustrate for simplicity and larity and have not necessarily heen dean fo sale nthe Figures, elements which correspond to elements already described may have the same relernce numerals, DETAILED DESCRIPTION OF THE, PREFERRED EMBODIMENTS FIG. 1 schematieally shows a block diagram of a fist ‘example of @ microprocessor 1. The microprocessor 1 includes «plurality of central processing units or processing cores 22, 24 snd 26 snd at interupt contler 10. The Imicroprocessor 1 may be any suitable type of miroproces- Sor, sch as general purpose microprcessr, a mierocon- troller, 4 digital signal processor, et. The microprocessor imay for example comprise one, two oF more ental pro- ‘esting units (CPU) oF cores. Adltionally, The micropro ‘cetor miy comprise one or more periphers, set = hardware aecelerators, UO ports, co-procesors or otherwise andlor memory, such is volatile nonvolatile memory, for ‘example on-chip lsh or RAM, The microprocessor 1 my he provided as single die or mliple des ins integrated US 9,575,911 B2 3 circuit package. The microprocessor I may e.g. be a micro controller ina. multiprocessor system, ed in a safety critical application or in anyother stable aplication. ‘The mierprocessor T may be for example used ina motive vehicles and may contain hardware features that allow the microprocessor It achive high soley integrity Jevels and ray: Those hardware Features may include redundant logic crit, intemal sleet funstionaliy out fontol handling and redundancy checkers. The ineript tontollr 10 is one ofthe hardware estes that an make the microprocessor more sete Tu FIG. 1 thee processing units 22,24 and 26 ae shown, The microprocessor Tay include two, thee oF more processing units. Each ofthe processing units 22, 24 or 26 ff the plurality is sraaged to handle interup-base tasks (ie. an intemipt handle) associted with each processing ‘nit 22, 24 oF 26. For example, a fixed andor configurable {nial association can be established betwoon each type of Jnteryptrouest to be handled ad an associated one ofthe Pluality of processing unis 22,24 or 26 so that when an 2 fnteript rogues recived, am asoeied processing Unit services the request by executing the inerript handler belonging fo dat ype of interrpt request. Thereby the Fad ofthe associated interop base tsk among the processing ‘nis 22,24 and 26 ca be Know a pia “The interop controler 10 controls processing of inte: ‘pt request atthe plurality of procesing units 22,24 snd 26. The processing units 22,24 and 26 have at last (vo rode, un ative mode ala ingetive mode, The ineript contoller 10 comprises a conuoller iaput 18 weciving an Interrupt request I and an interaptrouter 48 coupled othe sntoller input 15. The inteript router 45 js aranged to Inially route the eceved inter request I toa Scected processing unit 26 ou ofthe plurality of processing nis 22, 24 and 26, eg. to one ofthe processing units that have been ssoiated with the respostive type of inerupt request. In response 10 the received inert rust IR the selected processing wit 26 execttes an interupt service routine ISR fram iteript hale associated wi the received interrupt request IR The interrupt controller 10 further comprises a monitoring ‘unit 40 which includes « monitoring inp 58 connectable to the pluality of the processing units 22,24 and 26, and a ‘monitoring output 70 connected toa router input 72. The ‘monitoring ouput 70 cups routing change signal RCS to the rose inp 72 ifthe monitoring nit 0 detemnines thatthe selected processing unit 26's in insetive mode while 2 prosloctad processing unit eg. the processing unit 2 oF the processing unit 24, is in the ative mode, The inerupe router 4 is further arranged to reroute the cexocution of the requested intrrapt driven task from the Selected processing unit 2610 the presclected pressing Ut 22 or 24 when in use the slew procersing unit 26 brcomes insctive while te preselected processing unit 22 oF 2s ina active mode. The selected processing uit 26 may fog, become inactive because of a soltware or hardware Tale that causes the selected processing unit 26 to shit doven orto become unavailable. The select! processing unit 26 may for example be shu-down or become otherwise be permanently unavailable. The selected processing it 26 tnay also become temporarily imvctive, and be for example jn an idle or power saving ste, or unavailable due to running an application which inhibits execution of the interphase tasks, Tn this ater situation, tbe monitoring unit 40 determines 1 chinge of mode ofthe selected processing unit 26 and outputs a coresponding routing change signal RCS w the 4 input 72 of the interrupt router 48. In response to the reception of the outing change signal RCS, the interrupt rte 48 motes the exeestion of the ntemupservice rowing ISR oro the intern handler o the preselected processing unit 22 or 24 The interrupt router 4S is eranged to reroute the execu- tion of the lterapt serve routine ISR hands! by the selecied processing unit 26 10 one or more presclccted processing units 22 of 24 which remain active. This allows thatthe execution of interypt driven tasks, all or the most erval, can continue to be performed with a prese- lected rerouting path if least one ofthe processing Unis 22,24 or 26 of te plurality isin the ative mode. Ths, the Safety Tinctionlity of the miexopeocessor is improved Additionally: the rerouting of the inteerapt driven asks from the selected processing unit 26 to the one or more preselected procesing units 22 andior 24 can predter Iined. Thorby, risks such as eg loss of dats, suspending ‘an execution of tasks associated with allure ofa proces ing unit in the system, may be mitigated by using a suitable predetermined remuting sebeme. Furthermore. since the ‘expected (maxinui) loa ean he detemnined the processing tuts 22, 24 and 26 may be suitably designed to beable 10 handle the expected ad. The interrupt controller 10 may be implemented in any ‘manner suitable forthe specific application. For example, ‘he inital routing ofthe received inter! rauest IR may be performed in any manner stole forthe specific imple mentation, ang be base on prioniring the inlerint ‘oguosts any oer suitable mance. “The interrupt quests may any typeof interrupt request suitable forthe specie implementation, svt as hardware interop request, software interapt reques, inter-processor interop reiest et, In one example, he interop rest Re associated with the intermppt service may Be a bon rmaskable-intrrapl request. A. non-maskable inleript request i an interrupt request that should not be capable oF being disabled and should always be able 1 be handled, The monitoring unit 40 may be implemented in any ‘manner suitable forthe spocitic implementation. The moni- toring unit 40 may eg. Be a watebiog timer, Le. an elee- tron timer that my be used to detect and recover from @ ‘malfunctioning of processing units 22,24 and 26. During active mode, the processing units 22, 24 and 26 may regularly resct and restart the watchdog timer to prevent ft from elapsing, or “timing out If, doe to a hardware or software fale, the selected procesing nit 26 fils 10 "estan the watchdog timer. the watchdog timer will lapse And generate a timeout signal. The routing change signal RCS may be for example the timoout signal of may be derived from the timeout signal ofthe watchdog timer. ‘so, the interaptrouter 48 may be implemented in aay rmanoor suitable for dhe specific implementation, and the interop outer 48 eg. be implemented asa state-machine ae ‘other suitable, configurable oF not, opie eteuit which ean ‘operate without control by a software executed by the procestng wns. Thereby, re-routing the excetion of the Interpt service routine ISR aesocisted with the received interop roquest IR can be performed in hardware, theroy improving the speed of rerouting compared 0 for example st software solution The interop router may be arranged 0 route the inter= rupts in any manner sitble forthe specific use of the imiropreessor 1 or 2 For example the interpre may ‘be pre-configured during manuffctring of the microproces- sor, oF configurable and to he configured afer assembling into a system. Likewise, the routing may be slate oF US 9,575,911 B2 5 Adymmie, Por example the interup outer may be arranged to have specified rerouting options or paths during stating tpof the microprocessor tor 2.4, ding starting upof the proceising units 22, 24 andl 26 and daring starting op ofthe Interpt controller 10° or 11. Altematively the inerupt rover may be sranged to have specified rerouting options fr paths during a pase in which al the processing unts 22, 24!and 26 of the multiprocessor 1 o¢ 2 are active and not aifcted by any file or change of state Tn case both the monitoring and inter router operate without control by software executed by the processing Unis, the ned for processing units to moaitor the sates of the elher CPU's belore rerouting ean ake place is obviate Thus, re-routing ean be peeformed without significant ime delays associated with the continuation of the exccuton of the interrpt service routine ISR or of any other stable iteropt driven tanks. FIG. 2 schematically shows a block diagram ofa second example of mieroprocessor 2. The microprocessor 2 om prises an iaterapt controller 11. The intermp controller 1 prises in ition to the inlerapt rote 46 a prorty tcontoller 48 sssigning a priority level PL to the received fiterpt request IR. The prionty controller 48 may be snnected whan ipa eoiectable to the input 13 ofthe interrpt controller 1 and with an ouput connectable t0 2 another inpot ofthe interrupt outer 46. The interrupt router 86 ray be coupled vo the controller input 18 vi the preety ‘onto 48 ‘The inert router 46 may be arrnged w route the exocution of th intemupt service routine ISR fom the felested procesing unt 26 othe wer prescectd process- Jing wit 22 0° 24 if the monitoring wnit 4D determines the felectod processing unit 26 iia inactive mode while the preselete procesing unit 22 or 24 je inthe active mode, Sd ifthe recived interrupt quest IR associated withthe execution afte interpt service tine ISR ss the prorty level PL within a predetermined priority range. In tis ranger the most ential interupt driven tasks essocated withthe particular processing unit 26 may be rerouted upon Tailor shut-down ofthe selected procesing unit 26, For example, only the interrupt driven tasks associated with" received interupe request having priority level higher than a predetemmined priority threshold may be rerouted (0 the other active processing units 22 or 24 In Siion, the infermpe driven tasks associated with the Selected processing unit 26 associated with an intemupt request having a prority level ower than the predterinsd Priority threshold may be suspended. By way ofan example i the selected processing unit 26, (CPUS of FIG. 2 has an associated plurality of inerupt ddiven tasks with a predetemnined priority level ranging Som 1 10 15, the iaterrupt driven wsks can all bo rerouted to a preslocod processing unis 2? andlor 24, independent Tom the preletennined priority level PL However, aleratively, only the interop den tasks executed by the selected processing unit 26 and essociated ‘vith a received priority rogues TR having © high prodty level, within a fist predetermined priory range. for example in the range between 1-18, are rote to first preselected procesing unt for example 10 the processing tit 22 CPUI, Additionally. the interrupt driven tsk as80- aie witha received interrupt request IR having medium Priority level within a second predetermined priority range or example in te range between 610, may be rerouted to ‘another, second preselected processing unt for example to the processing tmit 24, CPU2. In such a cise intemupt dkriven tasks associated wih @ receive inlerupt request 6 Iaaving alow priority level, below a predctennined priority tveshold, for example below priority level 6, can be ss pended and not rerouted. Thereby. an undue processing Foad on the preselected processing units 22 or 24 may be prevented The fist predetermined priority range may have an upper list anda lower lit. Te upper lint may for example be the maximum priority level The second predetermined Priory range may have an upper limit at or below the upper Tinit ofthe Sst predetemnined prodty range, and ot oF low the lower limit ofthe Fist prestermined.prindty range. The predetenined priority threshold my be below the upper limit of the second predetemnined pisity range Anda or below th lower Fmit ofthe second predetermined Priority range, FIG. 3 schematically shows block diagram of 9 thint ‘example ofa mieroprosessr 3. Inthe mieroprocesor 3, the processing units form sos, soc that each of the processing Unit 22, 24 and 26 has second corresponding partner processing unit 28,30, and 32. The processing units a set fare arranged, when operating in loekstep,c simultaneously ‘execute a se sequence of operations in parallel. A. pro cessing unit 22, 24 and 26, and is partner processing unit 28 '30/and 32, may for example, ina synchronised mode, both ru the same computer program A, (eg. in lokstep, that is run the same Se of operations atthe same time) in parallel while running independently from each other in a not synchronised mode. Inthe nt sjachronised mode, the Pro- ‘essing unit 22,24 and 26 may run for example a computer program B whereas is respective partner processing unl 23, 30 and 32 may rum for example a computer program C “The moaitering unit of FIG. 4 may’ be a Hoekstep i= toring unit 41 arranged to monitor a difleence in the ‘exeenin ofthe sme sequence af operations heween cot processing unt 22.24, 26 and the rexpocive puter P= ‘esting unit 28, 30, and 32 in onder to detect & processing ‘ror inthe execution ofthe operation, The lockstep mon toring unit AT may have two iaputs $9 and 60 connectable tothe plurality of processing units 22,24 and 26 and to the luli of comespoading parce processing units 28, 30 fad 32 respectively The fockstep monitoring output 1 may be arranged wo provide the routing change signal RCS tothe input 73 af the interrupt router 46 if she ockstep monitoring tut 41 detects a processing erm. The processing eror may bbe a consequence of a hardware or software fice oF change of sate, eg. change from an active mode 10 an inactive mode or toa power saving mode or shutdown, of the processing unit 22,24 oF 26 ‘Aime sift (00 indicate in FIG. 3) may be troduced btwn the fist mentioned processing units 22,24 and 26 apd the respective pater process wit 28, 30and 3250 that ‘probability of a processing emor detection caused by aa Ihaware oe software failure ine. the sclectd processing unit 26 (or in any other Fully processing unit of the nukprocessor system) is higher than without the time shift. FIG. 4 schematically shows a block diagram of fous ‘example ofa microprocessor 4 in which the monitoring unit 142 free icles fou collection wit $7 tha nay receive information reaive to any error die (0 & hardware oF sofware faite or change of sae of any ofthe processing tit 22,24 oF 26 through the two inp 9 ed 60 ad sores it The fault collection unit 87 may comprise a memory Unit ‘or anyother type of stale string device for storing the received information, The fault clletion unit S7 may ‘Eenerte the routing change signsl RCS. based on the received information, eg- if the fault collection unit $7

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