COLLEGE OF ENGINEERING & TECHNOLOGY DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING COURSE PLAN COURSE TITLE & CODE: Digital Logic Design (ECE3141) ‘Academic year: 2010 EG Semester: Instructors’ name: |. BisrarK. (Ass Lecturer). Mebrahtu ¥.(Ass Lecturer), Abrehet G. (Ass. Lecturer) L.tdentifying Information Coursetite: DigitaLLogic Design Coursecode: ECEG3141 EcTSCredits: 6 Contact hours: (LECHR + Tut. HR + Lab. HR)/WEEK: (7) Course offered to Electrical & Computer Engineering (year Ill,semester 1) Prerequisites: ECEg2113: Applied Electronics I Course team leader: —_Bisrat Kahsay Office location: Block 1 Room 31 Telephone 0914180668, Email: bisatkahsay@zmallcom “Teaching team members & their e-mail: i) Bisrat Kahsay, bisratkahsay@gmail.com Mebrahtu Yohannes, mebrahtuyonni@smailcom il) Abvehet Gebreslassie, abrhten27@emal.com 2, course Description ‘This course provides an overview of the principles underying Number systems, arithmetic operafions, decimal codes, alphanumeric codes, Boolean algebra, Karsugh maps, implementation of dial lop ates sing universal fates (NAND and NOR gates), exclusive-OR gates, iterated circuits, combinational cies, decoders, ender aliplexers, Demitpleses, adders, sub actor, mulipir, sequential circuits, latches, lips, se “reuts analysis and counts, Finally, nder tis cours, Analysis and design of combinational and sequent logic systems wil be done 'B. Course Content and Schedule of Activities ‘Week | Content Testu Turon, Wests, assignments ee Weck] I> Introduction to Digital Systems > Lectures 1&2 1 Digital and analogue guantt 1.2 Binary digit, logic evel and digital waveform ‘Number stems, operations and codes = Lectures 34 2.1, Decimal Numbers é ‘+ Tutorials 1.2 22. Binary Numbers 2.3. Decimal to | Number Conversion own a ay Nunbes5 fiitions 5.2. Axiomatic Definition of Boolean Algebra 33. Boolean Functions 34 Canonial and Standard Forms 4.5, Other Lape Operations 36, Digtal Logie Gates 27, Simplification of Boolean Functions {Combinational loge 4.1 ttrdution 42. Base Combinational Loge Circuits ‘43. implementing Combinational Logie ‘14, Unvversal property of NAND and NOR gates 445. Adders and Subractors 46, Decoders and Encoders 445. Muniplexer and Demutipleves __ Sequential Loge si nioduetion 52. Flip-Flops 53 Tiggering of Flip-Flops $8, Anayss af Clocked Sequential Circuits |. 35. SateRedrtion an Assament 56, Flip-Flop Exiaton Tables | | See [wea] Conners and Regier | week 13 | 6.1. tntroduetion 2. Repaer | | 63 shitresisers |) G4 Ripe counters \ |, G5: Synchronous Counters | 66 Ting Seances | WeacTa—}7. Memory and storage onions [Nexis |" 21'Beses orsemconectr nemon 75: Ransom sree memory (RAND | 73. Rend only memory (ROM) | 72. Progammat ROM PRON [| 1s rashimemori iti A, Assessment eeesainuous Assessment 60% and Final exam 40%: 15, Texts and Supporting Materials + Textbook: LI. Mons M.Mano: Digi! Lops and Computer Desien + References 1], Mano, M- Mon Chas R. Kime and Martin. To sorgial Fundamental, edition Prentice Hal B). TL Foy {BYR Pa: Moser Digital etnies Logic & Computer Design uname T= tecture 36,7 1 Turia 3,4, 5.86 | res 10 1 Tutorial 7 8 1b 82 + Test #2(05%) 1 Lab Report #1 (5%) > Lectures 11 12 {Tutor 9 & 10 rere) + Test 3 (100) Lab Report 2 (5%) [> Cetus 18 {Toto 10. 1 fuses sea, 2015 Hl SiencelEnginering Math edition, 2006