Gate - Ec MCQ - Sample Chapter 2018 PDF

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9e
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ELECTRONICS & COMMUNICATION
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RK Kanodia
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Preface
The 9th edition of GATE MCQ Electronics & Communication Engineering has been revised exhaustively as per new
GATE Syllabus. The book has been completely revised in this edition, with the purpose not only of updating the
material, but just as important, making the book a better learning aid. This new edition is enriched by increasing
the number of problems as well as covering more topics of a subject. The book includes both the Multiple Choice
Questions (MCQ) and Numerical Answer Type (NAT) problems. Each problem is accompanied by a step-by-step and
well-explained solution. To improve the readability, the contents are represented with illustrative diagrams, standard
notations, relatively consistent variable naming and easy-to-understand explanations.
This new edition is the outcome of 10 successive years of compilation, revision & improvement of contents by
the authors and their team. In the past few years, a rumor was spread to defame the book that it has some errors.
After continuously reviewing each edition, we must say that the book is completely error-free from typos or any other
errors. Some of our friends and colleagues teaching in various GATE coachings also claimed that a few solutions in the
books are erroneous. We individually worked on those solutions and discussed them with some distinguish professors of
respective subjects. We must conclude that there is only a difference in method of solving which has been interpreted
as an Error by many readers. Also, the book has been thoroughly edited to remove many errors (mostly typos) which
had crept into the previous editions.
The few significant changes in this edition are as follows:

1. The chapter inclusions and organization of each subject has been modified as per new GATE syllabus.
2. Number of problems in each subject has been increased.
3. Some of the explanations have been simplified to make them more understandable to the students.
A student that has studied almost the syllabus of GATE during his/her B.tech needs to enhance and practice
a standard and vast collection of problems based on fundamentals of the subjects. By studying and reviewing so many
solved problems and seeing how each problem is approached and how it is solved, a student can learn the skills of solving
problems easily and increase his/her store of necessary Knowledge. We would like to emphasize that there is no short
cut to learning except by “doing.”
It is hoped that with these changes the book will prove more useful to the students and the teachers. There is
no doubt that aspirants will benefit from this well placed book to score a good rank.
R. K. Kanodia
Syllabus
Section 1: Engineering Mathematics

Linear Algebra : Vector space, basis, linear dependence and independence, matrix algebra, eigen values and eigen
vectors, rank, solution of linear equations – existence and uniqueness.
Calculus : Mean value theorems, theorems of integral calculus, evaluation of definite and improper integrals, partial
derivatives, maxima and minima, multiple integrals, line, surface and volume integrals, Taylor series.
Differential Equations : First order equations (linear and nonlinear), higher order linear differential equations, Cauchy’s
and Euler’s equations, methods of solution using variation of parameters, complementary function and particular
integral, partial differential equations, variable separable method, initial and boundary value problems.
Vector Analysis : Vectors in plane and space, vector operations, gradient, divergence and curl, Gauss’s, Green’s and
Stoke’s theorems.
Complex Analysis : Analytic functions, Cauchy’s integral theorem, Cauchy’s integral formula; Taylor’s and Laurent’s
series, residue theorem.
Numerical Methods : Solution of nonlinear equations, single and multi-step methods for differential equations, convergence
criteria.
Probability and Statistics : Mean, median, mode and standard deviation; combinatorial probability, probability
distribution functions - binomial, Poisson, exponential and normal; Joint and conditional probability; Correlation and
regression analysis.
Section 2: Networks, Signals and Systems

Network solution methods: nodal and mesh analysis; Network theorems: superposition, Thevenin and Norton’s, maximum
power transfer; Wye -Delta transformation; Steady state sinusoidal analysis using phasors; Time domain analysis of
simple linear circuits; Solution of network equations using Laplace transform; Frequency domain analysis of RLC
circuits; Linear 2-port network parameters: driving point and transfer functions; State equations for networks.
Continuous-time signals: Fourier series and Fourier transform representations, sampling theorem and applications;
Discrete-time signals: discrete-time Fourier transform (DTFT), DFT, FFT, Z-transform, interpolation of discrete-time
signals; LTI systems: definition and properties, causality, stability, impulse response, convolution, poles and zeros,
parallel and cascade structure, frequency response, group delay, phase delay, digital filter design techniques.
Section 3: Electronic Devices

Energy bands in intrinsic and extrinsic silicon; Carrier transport: diffusion current, drift current, mobility and resistivity;
Generation and recombination of carriers; Poisson and continuity equations; P-N junction, Zener diode, BJT, MOS
capacitor, MOSFET, LED, photo diode and solar cell; Integrated circuit fabrication process: oxidation, diffusion, ion
implantation, photolithography and twin-tub CMOS process.
Section 4: Analog Circuits
Small signal equivalent circuits of diodes, BJTs and MOSFETs; Simple diode circuits: clipping, clamping and rectifiers;
Single-stage BJT and MOSFET amplifiers: biasing, bias stability, mid-frequency small signal analysis and frequency
response; BJT and MOSFET amplifiers: multi-stage, differential, feedback, power and operational; Simple op-amp
circuits; Active filters; Sinusoidal oscillators: criterion for oscillation, single-transistor and op-amp configurations;
Function generators, wave-shaping circuits and 555 timers; Voltage reference circuits; Power supplies: ripple removal
and regulation.
Section 5: Digital Circuits

Number systems; Combinatorial circuits: Boolean algebra, minimization of functions using Boolean identities and
Karnaugh map, logic gates and their static CMOS implementations, arithmetic circuits, code converters, multiplexers,
decoders and PLAs; Sequential circuits: latches and flip-flops, counters, shift-registers and finite state machines;
Data converters: sample and hold circuits, ADCs and DACs; Semiconductor memories: ROM, SRAM, DRAM; 8-bit
microprocessor (8085): architecture, programming, memory and I/O interfacing.
Section 6: Control Systems

Basic control system components; Feedback principle; Transfer function; Block diagram representation; Signal flow
graph; Transient and steady-state analysis of LTI systems; Frequency response; Routh-Hurwitz and Nyquist stability
criteria; Bode and root-locus plots; Lag, lead and lag-lead compensation; State variable model and solution of state
equation of LTI systems.
Section 7: Communications
Random processes: autocorrelation and power spectral density, properties of white noise, filtering of random signals through
LTI systems; Analog communications: amplitude modulation and demodulation, angle modulation and demodulation,
spectra of AM and FM, superheterodyne receivers, circuits for analog communications; Information theory: entropy,
mutual information and channel capacity theorem; Digital communications: PCM, DPCM, digital modulation schemes,
amplitude, phase and frequency shift keying (ASK, PSK, FSK), QAM, MAP and ML decoding, matched filter receiver,
calculation of bandwidth, SNR and BER for digital modulation; Fundamentals of error correction, Hamming codes;
Timing and frequency synchronization, inter-symbol interference and its mitigation; Basics of TDMA, FDMA and
CDMA.
Section 8: Electromagnetics
Electrostatics; Maxwell’s equations: differential and integral forms and their interpretation, boundary conditions, wave
equation, Poynting vector; Plane waves and properties: reflection and refraction, polarization, phase and group velocity,
propagation through various media, skin depth; Transmission lines: equations, characteristic impedance, impedance
matching, impedance transformation, S-parameters, Smith chart; Waveguides: modes, boundary conditions, cut-off
frequencies, dispersion relations; Antennas: antenna types, radiation pattern, gain and directivity, return loss, antenna
arrays; Basics of radar; Light propagation in optical fibers.
************
contents
ELECTRONIC devices
CHAPTER 1 Semiconductors in Equilibrium 3-26

CHAPTER 2 Semiconductors in Non Equilibrium 27-46
CHAPTER 3 PN Junction Diode 47-82
CHAPTER 4 BJT 83-110
CHAPTER 5 MOSFET 111-136
CHAPTER 6 JFET 137-150
CHAPTER 7 Integrated Circuit 151-160
ANALOG ELECTRONICS
CHAPTER 1 Diode Circuits 3-52

CHAPTER 2 BJT Biasing 53-104
CHAPTER 3 BJT Amplifiers 105-140
CHAPTER 4 FET Biasing 141-178
CHAPTER 5 FET Amplifiers 179-220
CHAPTER 6 Output Stages and Power Amplifiers 221-248
CHAPTER 7 Op-Amp Characteristics and Basic Circuits 249-288
CHAPTER 8 Op-Amp Application 289-338
CHAPTER 9 Active Filters 339-400
DIGITAL ELECTRONICS
CHAPTER 1 Number System and Codes 3-26

CHAPTER 2 Boolean Algebra and Logic Simplification 27-67
CHAPTER 3 The K-Map 69-88
CHAPTER 4 Combinational Circuits 89-116
CHAPTER 5 Sequential Circuits 117-138
CHAPTER 6 Logic Families 139-166
CHAPTER 7 Logic Families 167-188
CHAPTER 8 Microprocessors 189-208
GATE Electronics & Communication-2018
in 5 Volumes
by R.K. Kanodia
Page 221 Output Stages and Power Amplifiers Chapter 6
Chapter 6
Sample Chapter of GATE Electronics & Communication-2018, Volume-4
Output Stages and Power Amplifiers
QUESTION 6.1 QUESTION 6.4
The output signal power of a power amplifier is several times A power BJT operating at a high current density, IE = 5 A
the input signal power. It is possible because is found to have a base current of 0.2 A and a base-input
resistance of 0.72 W.
n
(A) a positive feedback exists in the circuit
i
The base spreading resistance is
(B) a negative feedback is introduced in the circuit
o.
(A) 0.125 W
c
(C) the circuit converts a part of dc power from the dc
.
(B) 0.72 W
supply into ac signal power
(D) a step-up transformer is used in the circuit
i a (C) 0.595 W
o d (D) 0.835 W
. n
QUESTION 6.2
o p
sh
QUESTION 6.5
Conversion efficiency is defined as
In which of the following amplifier classes, the active device
(A) Power dissipated in the load divided by the power
operates for the whole of the input signal cycle ?
dissipated in the output stage of the amplifier.
(A) Class A
(B) Power dissipated in the load divided by the total power
in
supplied by the power supplies. (B) Class AB
(C) Decreasing gain with increasing frequency.
o.
(C) Class B
(D) First increasing and then decreasing gain with increasing
. c
(D) Class C
a
frequency
d i
n o
QUESTION 6.3
p. QUESTION 6.6
o The feedback in emitter follower circuit is
sh
If the load power is 3 mW and the dc power is 150 mW, the
(A) 50%
efficiency is
(B) 100%
(A) 0%
(C) 0%
(B) 2%
(D) 0.1%
(C) 3%
(D) 20%
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Engineering Mathematics Control Systems,
Communication Systems, Electromagnetics

Which of the following best describes a class A amplifier ? Consider the emitter follower shown in figure. We wish
to deliver a power of 0.5 W to RL = 8 Ω . (Assume
(A) High efficiency and high distortion
VBE (ON) . 800 mV )
(B) Low efficiency and high distortion
(C) Low efficiency and low distortion
(D) High efficiency and low distortion
QUESTION 6.8
The collector circuit efficiency of a single-ended class-A

. i n
o
power amplifier can never be The value of I1 for a small-signal voltage gain of 0.8 will be
(A) 20%
. c
(A) 40 mA
(B) 30%
i a (B) 5 mA
(C) 40%
o d (C) 18 mA
n
(D) 50% (D) 13 mA
p.
o
QUESTION 6.9 sh QUESTION 6.11
The parameters for the transformer-coupled common-emitter Consider the common-source circuit shown in figure below.
circuit shown in figure are VCC = 36 V and n1 : n2 = 4 : 1. If The maximum current, voltage and power ratings of the
in
the signal power delivered to the load is 2 W, what will be power transistor are: 5 A, 80 V and 25 W, respectively. If
.
the rms voltage across the load ? VDD = 80 V , what will be the value of RD ?
c o
a .
d i
n o
p.
o
sh _______ Ω
_______ Volt

in 5 Volumes
by R.K. Kanodia

Consider the class A power amplifier circuit given below. For the transistor in the common-emitter circuit shown in
figure below, the parameters are: b = 100 , PD,max = 2.5 W ,
VCE^sush = 25 V and IC,max = 500 mA .
. i n
o
What is the value of RB that locate the Q -point at the centre
c
of the load line ?
a . Let RL = 100 Ω . What are the required values of VCC and RB
i
_______ kΩ that delivers the maximum power to the load ?
o d VCC (in V) RB (in kW)
n
(A) 20.8 25
p. (B) 19.4 25
o (C) 25 19.4
sh
QUESTION 6.13
(D) 19.4 20.8
The common-emitter circuit shown in figure below is biased at
VCC = 24 V . The maximum transistor power is PD,max = 20 W
and the current gain is b = 80 .
. in
QUESTION 6.15
o
A student designs the emitter follower as shown in figure
c
.
below for a small-signal voltage gain of 0.7 and a load
i a
resistance of 4 W.
o d
. n
o p
sh
What will be the values of RB and base current IB such that
the maximum power is delivered to the load RL ?
RB (in kW) IB (in mA)
(A) 20.8 1.12
(B) 1.12 20.8 For a sinusoidal input, what is the maximum average power
that can be delivered to the load, RL without turning Q1 off ?
(C) 7.2 20.8
(D) 1.12 7.2 _______ Watt



The circuit parameters for the class-A emitter follower shown Consider the circuit class A amplifier shown in figure below.
in figure below are: V+ = 12 V , V− =− 12 V and RL = 100 Ω
. The transistor parameters are : b = 200 , VBE = 0.7 V and
VCE ^sath = 0.2 V .
. i n
o
If transformer has an 80% efficiency, then the maximum
. c
efficiency of the class A amplifier is
i a
(A) 50%
d
If the output voltage is to vary between + 10 V and - 10 V , (B) 33.33%
what are the minimum required values of IQ and R ?
n o (C) 24.6%
IQ ^minh (in mA) R (in W)
p. (D) 78.6%
o
(A) 113 100
sh
(B) 100 113
(C) 10 11.3
(D) 11.3 10 QUESTION 6.19
An emitter follower delivers a peak swing of 0.5 V to an 8 W
in
load with VCC = 2 V . If the bias current is 70 mA, the power
.
efficiency of the circuit will be
QUESTION 6.17
c o
.
_______ %
Consider the case AB stage amplifier shown in figure with
i a
d
Vthermal = 25 mV . If both transistors have reverse saturation
o
current IS = 10−15 A , the value of Quiescent current IC is
. n QUESTION 6.20
o p What is the basic meaning of total harmonic distortion ?
sh
(A) The nonlinearity that arises due to non-constant gain of
the amplifier.
(B) The amount of power that appears in the harmonic
components as a percentage of the power appearing in
the fundamental.
(C) The amount of crossover distortion.
(D) The sum of the voltages of the harmonics divided by the
voltage of the harmonic.
_______ µA

in 5 Volumes
by R.K. Kanodia

Consider the transformer-coupled common-emitter circuit Consider the class-A emitter follower shown in figure. All
shown in figure. The parameters are: VCC = 10 V , RL = 8 Ω the transistor are identical. Assume that VBE = 0.7 V in the
, n1 : n2 = 3 : 1, R1 = 0.73 kΩ , R2 = 1.55 kΩ and RE = 20 Ω . active region and that VCEsat = 0.2 V .
The transistor parameters are b = 25 and VBE ônh = 0.7 V .
The amplitude of the sinusoidal input voltage is 17 mV.
. i n
c o
.
What is the maximum and minimum output voltage Vo for
a
which Q1 remains in the active region.
d i (A) Vo^maxh = 14.8 V , Vo^minh =− 2.86 V
What will be the ac power delivered to the load ?

n o (B) Vo^maxh = 14.8 V , Vo^minh = 0 V
p. (C) Vo^maxh = 2.86 V , Vo^minh = 0 V
o
_______ mW (D) Vo^maxh = 2.86 V , Vo^minh =− 2.86 V
sh
in
The circuit of a class B push-pull amplifier is shown in Fig. Which of the following amplifier class suffers mainly from the
.
If the peak output voltage, Vo is 16 V, the power drawn from problem of crossover distortion ?
o
the dc source would be
c
(A) Class A
a . (B) Class B
d i (C) Class AB
n o (D) Class C
p.
o
sh QUESTION 6.25
The probable cause for harmonic distortion in a two-stage

RC -coupled amplifier is
(A) 10 W (A) the transistor itself
(B) 16 W (B) the stray shunt capacitance, Csh
(C) 20 W (C) the coupling capacitors, CC
(D) 32 W (D) the biasing resistors



Consider the class-B output stage shown in figure below. Consider the push-pull stage depicted in figure, where a
For the transistor, assume the VBE = 0.7 V in the active and current source, I1 , is tied from the output node to ground.
VCE^sath = 0.2 for saturation.
. i n
Suppose vi = 0 . Which of the following condition guarantees
o
that Q1 is ON (i.e., VBE1 . 800 mV ) ?
c
The transfer characteristic (vo versus vi ) for the circuit is
a .(A) I1 RL $ 800 mV
d i (B) I1 RL 1 800 mV
o
I1
(C) RL $ 800 mV
. n 1 800 mV
I1
(D) RL
o p
sh QUESTION 6.28
Consider the class-B output stage with complementary

MOSFETs shown in figure below. The transistor parameters
in
are VTN = VTP = 0 and Kn = K p = 0.4 mA/V2 . Let RL = 5 kΩ
.
o.
. c
i a
o d
. n
o p
sh What is the maximum output voltage such that Mn remains
biased in the saturation region ?
(A) 8 V
(B) 10.25 V
(C) 12.5 V
(D) 20.5 V

in 5 Volumes
by R.K. Kanodia

Consider the circuit shown in figure below. Consider the class-AB stage amplifier shown in figure having
Vthermal = 25 mV .
. i n
c o
.
The maximum ac output power and the dc input power of For the npn transistor, IS = 10-15 A , and for pnp transistor
the amplifier are respectively
i a IS = 10-16 A . Assume that β F is very large and output voltage
d
(A) 12.5 W, 15.5 W is vo = 0 V . If IB = 250 µA , what is the value of quiescent
o
current ICQ ?
n
(B) 3.25 W, 7.96 W
(C) 6.25 W, 3.25 W
p. _______ µA
o
(D) 6.25 W, 7.96 W
sh QUESTION 6.32
QUESTION 6.30 Consider the circuit of class AB stage amplifier shown in
in
figure below. The transistor parameters are:
.
Consider the class-AB stage shown below. The transistor
o
parameters are VTN = 0.75 V , VTP =− 0.75 V
c
K p = 300 µA/V2 = Kn
.
Kn = 250 µA/V2 , K p = 100 µA/V2
a
VTN = 0.75 V What is the value of Quiescent current ID ?
d
VTP =− 0.75 V
What is the value of quiescent current ID1 ?
n o
p.
o
sh
_______ µA
_______ µA



Consider the class-AB output stage shown in figure below. Consider the basic class C amplifier circuit shown in figure
The diodes and transistors are matched with parameters having VCE^sath = 0.3 V .
IS = 6 # 10−12 A and b = 40 .
. i n
o
What is the value of ac output power ?
. c
(A) 47 mW
i a(B) 23.5 mW
o d (C) 94 mW
n
(D) 50 mW
.
At vo = 24 V , if the minimum current in the diodes D1 and
p
D2 is 25 mA, what will be the value of R1 ?
o
sh
(A) 18.52 W
(B) 98.2 W
QUESTION 6.37
(C) 53.97 W
(D) 5.3 W Consider the output stage shown in figure. Assume I1 is an
ideal current source and the load resistance, RL = 8 Ω . If the
in
output must achieve a small-signal voltage gain of 0.8, what
.
is the required bias current of Q1 and Q2 ?
o
(Neglect the incremental resistance of diodes D1 and D2 )
c
QUESTION 6.34
a .
A class-C amplifier is driven by a 200 kHz signal. The
d i
o
transistor is ON for 1 µs and the amplifier is operating over
n
100% of its load line. If IC^sath = 100 mA and VCE^sath = 0.2 V ,
what is the average power dissipation ?
p.
o
_______ mW
sh
QUESTION 6.35
A push-pull stage operating from VCC = 3 V delivers a power

of 0.2 W to an 8 W load. The efficiency of the circuit is _______ mA
_______ %

in 5 Volumes
by R.K. Kanodia

Consider the output stage depicted in figure. A push-pull stage is designed to deliver a peak swing of VP to
a load resistance of RL . What is the efficiency, if the circuit
delivers a swing of only VP /2 ?
_______ %
QUESTION 6.41
The principal harmonic in a certain 15 kHz signal having
i n
a 10 V peak fundamental are the second and fourth. All
.
other harmonics are negligible small. If the total harmonic
o
distortion is 12% and the amplitude of the second harmonic
c
.
is 0.5 V peak, what is the amplitude of the 60 kHz harmonic
Assume that I1 is an ideal current source. The small-signal
a
?
i
voltage gain is (Neglect the incremental resistance of diodes
d
D1 and D2 )
o
_______ Volt
g R
n
(A) m L 1
.
gm 2
p
RL
^ m + gm h
(B)
o
g 1 2
sh
(C) ^gm1 + gm2h RL
QUESTION 6.42
^gm + gm h
(D)
1 2
RL A signal may have frequency components which lie in the

range of 0.001 Hz to 10 Hz. Which one of the following
types of couplings should be chosen in a multistage amplifier
in
designed to amplify this signal ?
.
(A) RC coupling
o
QUESTION 6.39
c
(B) Transformer coupling
.
Consider the composite stage shown in figure. Assume
a
(C) Direct coupling
i
b1 = 40 and b2 = 50 . In the circuit, the value of I1 so as to
d
obtain an output impedance of 1 W is (D) Double-tuned transformer
n o
p.
o
sh
QUESTION 6.43
Negative feedback in amplifiers

(A) lowers its lower cut-off frequency
(B) raises its upper cut-off frequency
(C) increases the bandwidth
(D) all the above
_______ mA



Heat sinks reduce A transistor having a thermal resistance QJA = 2cC/W is
operating at an ambient temperature of 30cC with a collector
(A) the transistor power
emitter voltage of 20 V. If the maximum junction temperature
(B) the ambient temperature is 130cC , what is the maximum average collector current ?
(C) the collector current
_______ A
(D) the junction temperature
QUESTION 6.49
QUESTION 6.45
A BJT must dissipate 25 W of power. The maximum junction

. i n
A power transistor operating at an ambient temperature of
50cC , dissipates power of 30 W. The thermal resistance of
o
temperature is TJ,max = 200cC , the ambient temperature is the transistor is 3c C/W . What is the maximum junction
c
25cC and the device-to-case thermal resistance is 3cC/W .
.
temperature ?
What will be the maximum permissible thermal resistance
between the case and ambient ?
i a _______ cC
d

_______
o
cC/W
n
p.
o QUESTION 6.50
QUESTION 6.46
sh
A BJT has a rated power of 15 W and a maximum junction
A power transistor for which Tj^maxh = 180cC can dissipate
50 W at a case temperature of 50cC if it is connected to a
heat sink using an insulating washer for which the thermal
temperature of 175cC . The ambient temperature is 25cC resistance is 0.6cC/W . What is heat sink temperature
and the thermal resistance parameters are: qsnk − amb = 4cC/W
in
necessary for safe operation at 30 W ?
and qcase − snk = 1cC/W . The actual power (in watts) that can
be safely dissipated in the transistor is
o. _______ cC
_______ Watt
. c
i a
o d QUESTION 6.51
. n
p
QUESTION 6.47 The amplifier in which the emitter and collector leads of one
o
transistor are connected to the base and collector leads of a
The power rating of a transistor can be increased by
sh
second transistor is called a
(A) raising the temperature (A) push-pull amplifier
(B) using a heat sink (B) Darlington amplifier
(C) using class-A operation (C) differential amplifier
(D) operating with no input signal (D) complementary amplifier

in 5 Volumes
by R.K. Kanodia
QUESTION 6.52 (B) Q1 ^184 µA, 7.85 Vh, Q2 ^325 µA. 7.16 Ah
The follower design shown is intended to provide a relatively (C) Q1 ^325 µA, 6.04 Vh, Q2 ^184 µA, 7.85 Vh
high input resistance. Assume VCC = 5 V , VEB = 0.7 V , (D) Q1 ^184 µA, 6.04 Vh, Q2 ^186 µA, 7.85 Vh
VCE sat = 0.2 V (Note the transistor sizing indicated by the
notation # n ) **********
. i n
c o
a .
d i
What is the largest possible unclipped zero-average sine wave
o
output?
. n
(A) 9 V
p
(B) 4.1 V
o
sh
(C) 5.9 V
(D) 0.9 V
QUESTION 6.53
. in
Consider the direct coupled amplifier shown in figure.
c o
a .
d i
n o
p.
o
sh
What are the values of Q -points of the transistors Q1 and

Q2 ?
(A) Q1 ^325 µA, 7.16 Vh, Q2 ^184 µ
A, 7.85 Vh


SOLUTION

SOLUTION 6.1 I E = 5 A
Correct option is (C). IB = 0.2 A

The power amplifier takes power from dc power supply and So, we obtain the parameters of BJT as
n
converts a part of it into useful ac signal power at the output.
i
b = IC = IE − IB
.
So a power amplifier is a dc to ac power convertor, whose
IB IB
o
action is controlled by the input signal.
c
= 5 − 0.2 = 24
.

0.2
i a re = VT
d
IE
SOLUTION 6.2
n o = 25 mV = 5 mΩ

.
5
rp = ^β + 1h re
p
Correct option is (B).
o = ^24 + 1h # 5m
Conversion efficiency
sh
^h h = Power drawn from dc source
maximum signal power output
= 0.125 Ω

Sine Conversion efficiency is defined as ratio of power Therefore, the base input resistance is
dissipated in the load to the total power supplied by the Rib = 0.72 Ω
power supplies. and the base spreading resistance is
in
Rbbl = Rib − rp
o.
= 0.72 − 0.125 = 0.595 Ω

. c
a
SOLUTION 6.3

d i
Efficiency, h =
^Pac ho
^Pdc hi
n o SOLUTION 6.5
p. Correct option is (A).
o
= 3m = 0.02

150m
sh
% of h = 2%
SOLUTION 6.4
Correct option is (C).

From the given data, we have

in 5 Volumes
by R.K. Kanodia
Class-A amplifier operates in centre of the load line so it is SOLUTION 6.8

operates for the whole of the input signal.

Correct option is (D).
For signal ended class-A power amplifier,
Circuit efficiency,
Po âc h
Pi ^dc h
h =
SOLUTION 6.6
^VCE^maxh − VCE^minhhÎC^maxh − IC^minhh
h =
Correct option is (B). 8VCC ICQ
In case of emitter follower, the whole of the output voltage Maximum circuit efficiency,
Vo developed across RL , is returned to the input thus the ^2VCC − 0h^2ICQ − 0h
hmax =
feedback voltage Vf is equal to the output voltage Vo . 8VCC ICQ
= 1 = 50%

n
2
. i
For signal ended class-A power amplifier maximum efficiency
o
is 50%.
c
a .
d i
n o SOLUTION 6.9
p. Correct answer is 6.36.
o Assume that the maximum power is being delivered, i.e.
sh
vol^peakh = 36 V
Also, we have the voltage gain for transformer
Vf vlo = n1 = 4
So, b = =1
Vo vo n2 1
So the feedback in emitter follower is 100%.
in
vo = v o
l
or
4
So,
o. vo = 36 = 9 V
c
4
a . Hence, the rms voltage across the load is
i
SOLUTION 6.7
Vrms = 9 = 6.36 V
d

2
o
. n
o p
sh
SOLUTION 6.10

Given the load power,
P Load = 0.5 Watt
Load resistance,
R L = 8 Ω
So in class-A having low efficiency and low distortion. Small signal voltage gain,
Av = 0.8


Now, we redraw the emitter follower circuit as ID = Pmax

VDS
= 25 = 0.625 Amp

40
So, we obtain the resistance,
RD = VDD − VDS
ID
= 80 − 40 = 64 Ω

0.625
The gain of emitter follower is given by
n
SOLUTION 6.12
i
gm R L
.
A v =
1 + gm R L
o
Correct answer is 11.3.
c
Substituting the given values in above expression, we get
.
For the Q -point to be at the centre of the load line, we have
gm1 ^8 Ωh
a
=
0.8
1 + gm1 ^8 Ωh
(IC = I1 ) VCE = VCC = 12 = 6 V
i

2 2
gm1 = 0.5
o d and IC = 12 − 6 = 60 mA
100
n
Since, the transconductance for the transistor is defined as
gm1 = IC = I1
VT VT
p. Also, IB = 60 mA = 1 mA
60
So, we get I1 = gm1 VT
o
sh
For dc analysis, we redraw the given circuit as
= 0.5 # 26 = 13 mA

SOLUTION 6.11
. in
Correct answer is 64.
c o
We redraw the given circuit as
a .
d i
o
Applying KVL in loop 1, we have
. n 12 - IB RB - 0.7 = 0
o p or RB = 12 − 0.7 = 11.3 kΩ
1m
sh
Since, we have VDD = 80 V SOLUTION 6.13
So, the maximum power occurs, when Correct option is (B).

VDS = VDD = 40 V We obtain the dc equivalent of the common emitter circuit as
2
Therefore, the drain current is given as

in 5 Volumes
by R.K. Kanodia
circuit as
Given circuit DC equivalent circuit
For the given circuit, the maximum power is delivered to the For maximum power delivered to the load, we have
load, when
. i n VCC = VCE^sush = 25 V
o
VCEQ = VCC = 24 = 12 V and VCEQ = VCC = 25 = 12.5 V
2 2
c
2 2
The maximum power is given as
a . ICm = VCC
i
So,
PQ^maxh = ICQ VCEQ RL
or PQ^maxh = ICQ VCC

2
o d = 25 = 250 mA < IC max

0.1k
2PQ^maxh
. n Applying KVL in output loop, we get
p
So, ICQ =
VCC V − VCEQ 25 − 12.5
o
ICQ = CC =
RL 0.1k
sh
= 2 # 20 = 1.67 Amp

24
= 125 mA

Therefore, the base current is
So, IBQ = 125 = 1.25 mA
I 100
IBQ = CQ
β
Again, applying KVL in collector-base loop, we have
in
= 1.67 = 20.8 mA VCC - IBQ RB - VBE = 0
.
80
o
Applying KVL in output, we get So, RB = VCC − VBE
IBQ
c
VCC - ICQ RL - VCEQ = 0
VCC
a . = 25 − 0.7 = 19.4 kΩ

i
VCC − VCEQ VCC − 2 1.25m
So, R L = =
d
ICQ 1.67
= 24 − 12 = 7.2 Ω

n o
.
1.67
VCC - IBQ RB - VBE = 0

o p
Again, applying KVL in collector-base loop, we obtain
SOLUTION 6.15

20.8m
sh
RB = 24 − 0.7 = 1.12 kΩ Correct answer is 0.45.
Av = 0.7 ,
R L = 4 Ω
For sinusoidal input, assume that
SOLUTION 6.14
vo = VP sin wt b ω = 2Tπ l
Correct option is (C). So, average power in the load resistor is
We draw the dc equivalent of the given common-emitter


_vo i IE1 = IQ + IL
2

Pavg = 1
T

T #0 RL
dt
For minimum value of IQ , the load current IL will be
maximum. So, we have
= 1
T
V P2 sin2 wt dt
#
IQ^minh = o^ h
T 0 RL v max

RL
2
= 1VP

2 RL = 10 = 100 mA

100
Q1 turns off when,
By using current mirror circuit, we have
I1 = VP
RL IQ1 = IQ
So, maximum average power is Applying KVL in loop 1, we get
Î R h2 0 − IQ R − VBE + v− = 0
Pavg ^maxh = 1 1 L ...(1)
2 RL
R = 0 − 0.7 + 12 = 113 Ω
n

i
100m
.
Now, we have
o
gm1 RL
Av = 0.7 =
c
1 + gm1 RL
Av
a .
i
gm1 =
^1 − Av h RL
or
=
0.7
^1 − 0.7h^4h
= 0.58 S
o d SOLUTION 6.17
.n Correct answer is 196.
p
So, IC1 = I1 = gm1 VT = 0.015 A For dc analysis, we redraw the circuit as
o
Hence, from equation (1), we get
sh
Pavg ^maxh = 1 I 12 RL
2
= 1 ^0.015 Ah2 ^4 Ωh = 0.45 W

2
. in
c o
.
SOLUTION 6.16

i a
d
For dc analysis, we redraw the circuit as Applying KVL in loop 1, we get
n o VBE1 + VEB2 = 1.3
p. VT ln IC + VT ln IC = 1.3
or
IS IS
o
(IS and VT are same for both transistor)
sh or 2VT ln IC = 1.3
IS
IC = 10−15 eb 2 # 25m l
1.3
So,
= 196 µA

Applying KCL at output,

in 5 Volumes
by R.K. Kanodia
SOLUTION 6.18 Given that VP = 0.5 V ,

Correct option is (C). R L = 8 Ω

For the given circuit, we have dc supply power So, the power efficiency is given by
PR
Pdc = VCC # ICQ Power efficiency = ...(1) L
PR + PI + PQ L
= 13 # 5m = 65 mW
where PR " Power across resistor RL
L
For dc input, inductor behaves as short circuit. Therefore, by PI " Power across current source
dc analysis, we have
VCC - VCEQ - 1k # 5m = 0
^PQ havg " Average power dissipation across transistor
Now, we obtain the power across resistor RL as
or VCEQ = 13 − 5 = 8 V
^VP / 2 h
2
2 2
The maximum ac power delivered to the transformer primary PR = V rms = = VP
L
RL RL 2RL
n
winding is
Plo = 1 VCEQ ICQ
16
. i
= 0.25 = 0.0156 W
o
2
c
The power across current source is
= 1 # 8 # 5m
.

2
a
PI =− IVEE = 70m # 2 = 0.14 W
i
= 20 mW
The average power dissipation across transistor is given as
Since, the transformer efficiency is 80%, so we obtain
o d ^PQ haverage = T1 #I
T
C VCE dt ...(2)
n
Po = hPlo 0
= 0.8 # 20m

p. where T = 2π
ω
= 16 mW

o
sh
Thus, we obtain the maximum efficiency as IC - IE = I1 + Vout
RL
AC power
Maximum efficiency = 100
Power delivered # VCE = VCC − Vout
= Po # 100
= VCC − VP sin wt

Pdc
Substituting the above expressions in equation (2), we get
in
= 16 mW # 100
^PQ haverage = T1
.

b I1 + RL sin ωt l
T
VP
65 mW #
o
0
= 24.6%
^VCC - VP sin ωt h dt ...(3)
a . = I1 bVCC − VP l

i
2
o d = 70m b 2 − 0.5 l

2
SOLUTION 6.19
. n = 0.1225 W

p
Thus, by substituting the obtained values in equation (1),
o
we get
sh
We draw the emitter follower circuit as
Power efficiency = 0.0156
0.0156 + 0.14 + 0.1225
= 0.0156 = 5.6%

0.2781
NOTE
For solving the integration of equation (3) note the following points:
1. The average value of sin ωt over one period of T is zero.
2. For eliminating the squared trigonometric terms, the trigonometric
relation is
sin 2 ωt = 1 − cos 2ωt
2
3. The average value of cos 2ωt over one period T is zero.


SOLUTION 6.20

Total Harmonic Distortion,
THD = D 22 + D 32 + D 42 .......
where D 2 = A 2 ,
A1
D 3 = A 3 , Applying KVL in the loop 1, we get

A1
VTH - IBQ RTH - VBEQ - IE RE = 0
D 4 = A 4 VTH − VBEQ
A1
RTH + ^1 + b h RE
or IBQ =
c A1 m c A1 m c A1 m
THD = A2 2 + A 3 2 + A 4 2 + .....
6.80 − 0.70
0.496 + 26 # ^0.02h
=

i n
2 2 2
= A 2 + A 3 + A 4 + ....
.
= 6 mA

A1
o
So the total harmonic distortion signifies the amount of power So, the collector current is
that appears in the harmonic component as a percentage of
.

c ICQ = bIBQ = 150 mA
a
the power appearing in the fundamental.
i
Therefore, we obtain the circuit parameters as
RlL = a2 RL = ^3h2 8 = 72 Ω
d

n o and g m =
ICQ
.
VT
SOLUTION 6.21
o p = 150m = 5.77 A/V

26m
sh
Correct answer is 345 mW. By using small signal model, the gain of circuit is
For dc analysis, we redraw the circuit as Av =− gm RlL =− 5.77 ^72h =− 415
So, we get vol = Av vi = 415 ^0.017h = 7.06 V

Now, we have the voltage transfer ratio for the transformer
n1 : n2 = 3 : 1. So, we obtain
. in
vlo = 3
vo 1
c o vo = v o
l
.
or
3
i a = 7.06 = 2.35 V

d
3
n o Thus, the ac power delivered to the load is
.
2
P L = 1 v o
p
By using voltage divider rule, we have 2 RL
VTH = R2
o ^2.35h2
sh
R1 + R 2 =
= 345 mW
2#8
=
1.55k 10
1.55k + 0.73k #
= 6.80 V

and RTH = R1 || R 2 = 1.55 || 0.73 = 0.496 kΩ

So, we have the simplified circuit as given below. SOLUTION 6.22

The power drawn from the dc source,

in 5 Volumes
by R.K. Kanodia
V L2 ^P h Again, we consider the circuit for Q1 operating in saturation.

= 16 # 16
Po =
2RL 2#8 So, we have the equivalent circuit as
= 16 W

SOLUTION 6.23
Correct option is (A).

For dc analysis, we redraw the circuit as
. i n
From the circuit, the output voltage is
o
Vo = 15 − VCE^sath
. c
= 15 − 0.2 = 14.8 V

i a Thus, the minimum and maximum output voltage for which
d
Q1 operates in active region is
o
Vo^maxh = 14.8 V ,
. n Vo^minh =− 2.86 V
From the circuit, we obtain

o p
sh
VB2 =− 15 + 0.7 =− 14.3 V
VE2 = VB2 =− 14.3 V

0 − VEQ2 SOLUTION 6.24
ICQ2 =
5k
0 − ^− 14.3h
in
=
= 2.86 mA Crossover distortion refers to the non-linearity in the output
.
5k
signal when the output signal crosses from positive to negative
o
This is a current mirror circuit. So, we have
or from negative to positive.
. c
ICQ3 = ICQ1 = ICQ2 = 2.86 mA Crossover distortion in class-B
a
Now, we consider the circuit for Q1 operating in cutoff. The
equivalent circuit is as shown below.
d i
n o
p.
o
sh
From the circuit, we have the output voltage
Vo =− 2.86m # 1k
=− 2.86 Volt



SOLUTION 6.25

The cause of harmonic distortion is the non linearity in the
dynamic transfer characteristics of the transistor.
SOLUTION 6.26

For positive value of input voltage (if vi $ 1.4 V ), the
transistor Q1 , Q 3 will be ON. So, we have the equivalent SOLUTION 6.27
circuit as
. i n
o
c
We redraw the given push-pull stage as
a .
d i
n o
p.
o
sh
From the circuit, we obtain
vo = vi − 0.7 − 0.7
For the push-pull stage, we consider the condition when Q1 is
in
= vi − 1.4 V
ON and Q2 is OFF. From the circuit, we have
Again, for negative value of vi , we have the equivalent circuit
o. vo = vi − VBE1 ...(1)
c
Applying KCL at output node,
a

. IC1 = I1 + vo ...(2)
i
RL
o d Now, Q1 is guaranteed ON for the condition
n
IC1 $ 0
p. I1 + vo $ 0
RL
[from equation (2)]
o
sh
I1 + vi − VBE $ 0 [from equation (1)]
RL
I1 + 0 − VBE $ 0
RL
From the circuit, we obtain the output voltage
I1 RL - VBE $ 0
vo = vi + 0.7
Thus, the transfer characteristics is I1 RL $ 800 mV

in 5 Volumes
by R.K. Kanodia
SOLUTION 6.28 We redraw the given circuit as


For dc analysis, we have the equivalent circuit as
. i n
o
The maximum peak output voltage is
c
Given the threshold voltage for the FETs,
.
Vout^peakh = VCEQ = VCC
2
a
VTN = VTP = 0 V
Now, for Mn to be biased in the saturation region, we have
VDS1 $ VDS ^sath
d i = 20 = 10 V

2
n
The maximum peak output current is
.
or VDS1 $ VGS1 - VTN
p
V
6VTN = 0@
I out^peakh = CEQ
or VDS $ VGS1 RL
o
sh
Applying KVL in loop 1, we get
= 10 = 1.25 A

10 - VDS1 - vo^maxh = 0 8
So, we obtain the ac output power as
or VDS1 = 10 − vo^maxh = VGS1 ...(1)
For the MOSFET, we have the current equation Pout = 1 ICQ VCC
4
ID = IL = Kn ^VGS − VTN h2
in
= 1 # 1.25 # 20
6VTN = 0@

.
or I D = I L = K n V 2
GS
4
or
vo^maxh
= Kn ^VGS h2
o
= 6.25 W

c
.
RL
The dc input power for the amplifier is
a
vo^maxh
i
or VGS = I V
R L Kn Pdc = CQ CC
d
π
o
vo^maxh
or 10 - vo^maxh = [substituting equation (1)] = 1.25 # 20
n
R L Kn
.
π
p
or v o2^maxh − 20.5vo^maxh + 100 = 0 = 7.96 W

^20.5h2 − 4 ^100h
o
sh
20.5 !
So, vo^maxh =
2
=8V

SOLUTION 6.30

Both MOSFETs are identical, so we have
SOLUTION 6.29 VGS1 = VGS2



= VBE1 + VEB2
1.25

or VT ln IC + VT ln IC = 1.25
IS1 IS2
2
or VT ln IC = 1.25
IS1 IS2
1.25
So, IC = 10−15 # 10−16 e 0.025
= 22.8 µA

Applying KVL in loop 1, we get

2.2 - VGS1 - VSG2 = 0
or VGS1 = VGS2 SOLUTION 6.32
= 2.2 = 1.1 V

. i n
o
2
For dc analysis, we redraw the circuit as shown below
c
or VGS1 =− VGS2
= 1.1 V

a .
So, the drain current is obtained as
d i
ID1 = ID2
n o
= Kn ^VGS − VTH h2

= 300µ ^1.1 − 0.75h2 p.

o

sh
= 36.8 µA

From the circuit, we have

VGS1 + VSG2 = 2
in
SOLUTION 6.31
. Kn c TP Kp m
or VTN + I D1 + − V + I D2 = 2
c o
.
VTN − VTP + c
Kp m
The base current is zero because b is very large. So, IB flows or I D1 + ID1 = 2 (I = I )
D1 D2
Kn
a
through 5 kW resistor. For dc analysis, we redraw the given
circuit as
d i or 1
c 2.5 10−4 +
#
1
1 # 10−4 m
= 2 − ^1.5h
n o or ID1 = 0.5
.
163.3
o p So, ID1 = ID2 = 9.38 µA
sh
SOLUTION 6.33

For dc analysis, we redraw the given circuit as
From the circuit, we have

in 5 Volumes
by R.K. Kanodia
SOLUTION 6.34
The power dissipation during the ON time is
PD, on = IC^sath VCE^sath
The total time period of amplifier is
T = 1 = 5 µ sec
200k
Let the transistor be ON for a short time, ton and OFF for
the rest of the input cycle. Since, the amplifier is operating
over 100% of the load line, so we have
PDâvgh = ton PD, on
T

T
. i n
= ton IC^sath VCE^sath
vo = 24 V ,
c
1µ
o
.
=
100m # 0.2
ID1 = ID2 = 25 mA 5µ #
i
= 4 mW

So, the load current is
iL = vo = 24 = 3 Amp
RL 8
o d
Applying KCL at the output terminal, we have
. n
I N = I L + I P
o p
sh
or IN - IL = 3 Amp SOLUTION 6.35
When diode is ON, QP is in cuttoff. So, we get Correct answer is 46.8.

IBn = IN = 3 = 73.2 mA Given that, VCC = 3 V ,
b + 1 41
Again, we have the diode current PR = 0.2 W ,
L
in
iD = 25 mA R L = 8 Ω
So, the current through resistance R1 is
o.
Since, the power dissipation in load RL is given by
c
2
IR1 = 25m + 73.2 = 98.2 mA PR = V P = 0.2
.
L
2RL
a
From transistor equation,
VBE = VT ln b iN l
IS
d i So, VP = 0.2 # 2 # 8 = 1.8 V
o
Therefore, the power efficiency for the push-pull stage is
n
= 0.026 ln b 3 obtained as
6 # 10−12 l
.
= 0.7004 V
PR
p
h = L
PR + PQ1âveh + PQ2âveh
o
Applying KVL in loop 1, we get L
sh
30 - IR1 R1 - VBE - vo = 0 V P2 /2RL
= 2

30 − ^24 + 0.7h
RL b p 4l
V P + 2VP VCC − VP
So, R 1 = 2R L
98.2m
=
0.2
8 bp p l
= 53.97 Ω
0.2 + 3 . 6 3 − 1.8
= 46.8%



SOLUTION 6.36

The maximum voltage across load is
VP = VCC − VCE^sath
= 10 − 0.3

= 9.7 V

So, we obtain the output ac power as
^VP h2 9.7 # 9.7
Po = =
2RL 2 # 1k
= 47 mW
Given that ideal current source I1 is used for forward biasing
n
of the diode D1 and D2 . So, we have the equivalent circuit
. i
c o
SOLUTION 6.37
a .
d i
o
For the given output stage, the voltage gain is given by
n
Av = vo = ^gm1 + gm2h RL ...(1)
vi
p.
o
sh
Av = 0.8 ,
R L = 8 Ω ,
Since, the incremental resistance of diodes D1 and D2 is to be
and IC1 = IC2 = I Bias neglected, so we redraw the circuit for small signal as
Substituting these values in equation (1), we get
in
Av = b IC1 + IC2 l RL
.
VT VT
= 2RL I Bias (I Bias = IC 1 = IC 2 )

or 0.8
VT
c o
I Bias = 0.8 # VT
a .
i
or
2RL
= 0.8 # 26m

2#8
od
= 0.8 # 26m
. n
p

2#8 From the circuit, we have
= 1.3 mA

o vi = v p1 = v p2
sh
Applying KCL at output, we get
io =− gm1 v p − gm2 v p
=−^gm1 + gm2h v p
^v p = vi h
SOLUTION 6.38 =−^gm1 + gm2h vi

So, the output voltage is
We draw the equivalent circuit for the given output stage vo =− io RL
= ^gm1 + gm2h RL vi


in 5 Volumes
by R.K. Kanodia
Therefore, the voltage gain for the output stage is obtained SOLUTION 6.40
as
Av = vo = ^gm1 + gm2h RL For a push pull stage, the operating mechanism is illustrated
vi
in the following figures.
SOLUTION 6.39

. i n
c o
For Positive Half Cycle
a .
d i
n o
p.
o
sh
The output resistance for the composite stage is given by
1
gm2 ^1 + b 1 + 1/b 2h
Rout =
Since, from the given data, we have Rout = 1 Ω , so by For Negative Half Cycle
substituting it in above expression, we get
in
So, the average power dissipation in Q1 is obtained as
1
.
gm2 = ( b1 = 40 , b2 = 50 ) T/2
1 + 40 + 1/50 PQ1âveh = 1 #V I dt
o
CE C
T 0
= 0.024 S

. c
T 0 ^ CE
V − V lP sin wt hcV lP sin wt m dt
T/2
IC2 = 0.024 = 1
#
a
or RL
i
VT
d
T/2 T/2
= 1 VCC V lP sin wtdt − 1 V lP2 dt
or
b2 IB2
= 0.024

T 0 RL # T # 2R L
o
0
VT
n c # cos 2ωtdt = 0 m
T/2
.
So, IB2 = 0.012 mA (VT = 26 mV , b2 = 50 )
p
0
Applying KCL at output, we get 2
= VCC V P − V lP
l
o

I1 = IE2 + IC1 pR L 4RL
sh
= IC2 + IB2 + b1 IB1
= V lP bVCC − V lP l

RL p 4
= b2 IB2 + IB2 + b1 IC2
Similarly, we obtain power dissipation in Q2
= ^b2 + 1h IB2 + b1 b2 IB2

PQ2âveh = V lP bVCC − V lP l
RL p 4
= ^b1 b2 + b2 + 1h IB2
Also, the power dissipation in resistor RL is obtained as
= 0.012 ^40 # 50 + 50 + 1h
2 2
PR = V rms = V lP
L
RL 2RL
= 24.6 mA
Thus, we get power efficiency


PR SOLUTION 6.42

h = L
PR + PQ1âveh + PQ2âveh
L
^V lP h /2RL 2 Direct coupling amplifiers operate without the use of

=
^V lP h 2 ^V lP h VCC V lP
2 frequency sensitive components like capacitors, inductors
RL b p 4 l
+ − and transformers so they are especially suited for amplifying
2RL
^VP /2h2 /2RL ac signals with frequencies as low as a fraction of a hertz.
=
^VP /2h2 2 ^VP /2h VCC VP /2
So for 0.001 Hz to 10 Hz signal we use direct coupling.
RL c p 4 m
+ −
2RL
(VlP = VP /2 )
V P2 /8RL
= 2

8RL RL b p 8l
V P + VP VCC − VP
SOLUTION 6.43
n
1/8RL Correct option is (D).
i
=

.
Negative feedback amplifier, increase the bandwidth of an
1/8RL + 1 b VCC − 1/8 l
RL pVP
o
amplifier so it is decrease the lower cutoff frequency and
c
1 increase the upper cutoff frequency of the amplifier.
.
=

1 + b CC − 1l
8 V
a
VP p
= p VP

8 VCC
d i
Since, VP - VC , so we obtain
n o
h = 39%
p.
o
sh
fl1 < f1
fl2 > f2
SOLUTION 6.41
in
n th harmonic distortion = %Dn = An # 100%
A1
o.
SOLUTION 6.44
For the given problem, total harmonic distortion is
. c
a
2 2 Heat sinks are used to quickly transfer the heat generated in
i
THD = 0.12 = D + D ...(1)
2 4
the power transistor to the surroundings. The heat generated
d
Since, we have
in transistor in mainly at the junction.
D2 = A2 # 100
A1
n o So Heat sink reduce the junction temperature.
= 0.5 # 100 = 5%

10
p.
o
sh
Substituting it in equation (1), we get
= ^0.05h2 + D 42
0.0144
SOLUTION 6.45
So, D 4 = 0.0144 − 0.0025
= 0.1091 = 10.91%
Again, we have
Since, the 4th harmonic can also be given as TTTotal = θ Total PD
D 4 = A 4 = 0.1091 or Tdev - Tamb = PD ^q dev − case + q case − ambh
A1
So, A 4 = 1.091 V or 200 - 25 = 25 ^3 + θ case − ambh
This is the amplitude of 60 kHz ( = 4 # 15 kHz ) harmonic. So, θ case - amb = 4cC/W

in 5 Volumes
by R.K. Kanodia
SOLUTION 6.46 are related as

TT = θPD
We obtain the temperature coefficient, So, TJ - TA = θ JA PD
T − Tamb TJ = 3 # 30 + 50
qdev - case = J,max Therefore,
PD, rated
= 140cC

= 175 − 25 = 10cC/W

15
Hence, the actual power dissipated in the transistor is
TJ,max − Tamb
PD =
q dev − case + q case − snk + q snk − amb
SOLUTION 6.50
= 175 − 25 = 10 W

10 + 1 + 4
n
. i
The ambient temperature and dissipated power in a transistor
o
are related as
c
TT = θPD
.

SOLUTION 6.47
a
Tj max − TC
i
So, θ JC =
PD
d
o = 180 − 50
The power rating or power handling capability of a transistor
n
can be increased by using a heat sink with the heat sink, the 50
p.
transistor has a larger area to radiate heat into the air = 2.6cC/W

o
Again, we have
sh
TJ - TS = QJS PD
or TJ - TS = ^QJC + QCS h PD
SOLUTION 6.48 or 180 - TS = ^2.6 + 0.6h 30
So, TS = 180 − 96 = 84cC

in
Since, we know that
TT = θPD
o.
. c
So, Tj - TA = QJ − A PD
a
TJ^maxh − TA SOLUTION 6.51
i
Therefore, PD^maxh =
QJ − A
= 130 − 30 = 50 W
2
o d Correct option is (B).
n
Darlington configuration circuit is,
.
Thus, the maximum average collector current is obtained as
p
PD max
IC, max = ^ h
o

VCE
sh
= 50 = 2.5 Amp
(VCE = 20 V)
20
SOLUTION 6.49
So in Darlington configuration circuit emitter of one transistor
is connected to the base of other transistor, and collector are
connected each other.
The ambient temperature and dissipated power in a transistor


SOLUTION 6.52 Applying KVL in loop 1, we have

- 100kIB1 - VBE1 - 24kIE1 - ^- 9h = 0
We draw the equivalent circuit for the given follower design So, IB1 = 9 − 0.7 (put IE1 = ^b + 1h IB1 )
100k + 81 # 24k
as
= 4.06 µA

Therefore, the collector current for transistor Q1 is
IC1 = bIB1 = 80 # 4.06 µ
= 325 µA

The voltage at collector terminal of transistor Q1 is obtained
as
VC1 = 9 − 9.1k # 325µ
= 6.04 V

. i n
o
Applying KVL in loop 2,
c
9 - 12k # IE2 - VEB2 - 9.1 ÎC1 - IB2h = 0
i
In the circuit, the output signal is voltage limited by the
a So, IE2 = 9 − 0.7 − 6.06 = 186 µA
12k
d
saturation of Q1 . So, we obtain the output as
o
vo = VCC − VCE^sat h − VBE and IC2 = 184 µA
= VCC − 0.2 − 0.7

. n From the circuit, we obtain
p
VC1 = 9 − 9.1 ÎC1 − IB2h
o
= 5 − 0.9

sh
= 9 − 2.94 = 6.06 V

= 4.1 V

VE1 =− 9 + IE1 ^24kh
= 10IRL

Thus, for large enough I , the largest possible zero-average =− 1.10 V

unclipped output is 4.1 V peak. VCE1 = 6.06 − ^− 1.10h
in
= 7.16 V

o. VC2 =− 9 + IC2 ^43kh
. c
=− 1.09 V

SOLUTION 6.53
i a VEC2 = VE2 − VC2
d = 6.76 − ^− 1.09h

o
n
= 7.85 V

p. Thus, the Q -points of the transistors Q1 and Q2 are
o Q1 (325 µA , 7.16 V),
sh
Q2 ^184 µA, 7.85 Vh
**************


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QUESTION 6.29 QUESTION 6.31