VLSI Lab Viva questions and answers

1. What is Intrinsic and Extrinsic Semiconductor?

The pure Silicon is known as Intrinsic Semiconductor.
When impurity is added with pure Silicon, its electrical properties are varied. This is known as
Extrinsic Semiconductor.
2. What is CMOS Technology?
The fabrication of an IC using CMOS transistors is known as CMOS Technology.
CMOS transistor is nothing but an inverter, made up of an n-MOS and p-MOS transistor
connected in series.
3. Give the advantages of CMOS IC?
• Size is less
• High Speed
• Less Power Dissipation
4. What are four generations of Integration Circuits?
• SSI (Small Scale Integration)
• MSI (Medium Scale Integration)
• LSI (Large Scale Integration)
• VLSI (Very Large Scale Integration)
5. Give the variety of Integrated Circuits?
• More Specialized Circuits
• Application Specific Integrated Circuits (ASICs)
• Systems-On-Chips
6. Why NMOS technology is preferred more than PMOS technology?
N-channel transistors have greater switching speed when compared to PMOS transistors. Hence,
NMOS is preferred than PMOS.
7. What are the different MOS layers?
• n-diffusion
• p-diffusion
• Polysilicon
• Metal
8. What are the different layers in MOS transistor?

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 VLSI Lab Viva questions and answers
The layers are Substrate, diffused Drain & Source, Insulator (SiO2) & Gate.

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9. What are the different operating regions for an MOS transistor?
• Cutoff Region
• Non- Saturated (Linear) Region
• Saturated Region
10. What is Enhancement mode transistor?
The device that is normally cut-off with zero gate bias is called Enhancement mode transistor.
11. What is Depletion mode device?
The Device that conducts with zero gate bias is called Depletion mode device.
12. When the channel is said to be pinched off?
If a large Vds is applied, this voltage will deplete the inversion layer. This Voltage effectively
pinches off the channel near the drain.
13. What are the steps involved in manufacturing of IC?
• Silicon wafer Preparation
• Epitaxial Growth
• Oxidation
• Photo-lithography
• Diffusion
• Ion Implantation
• Isolation technique
• Metallization
• Assembly processing & Packaging
14. What is meant by Epitaxy?
Epitaxy means arranging atoms in single crystal fashion upon a single crystal substrate.
15. What are the processes involved in photo lithography?
(1) Masking process (2) Photo etching process.
These are important processes involved in photolithography.
16. What is the purpose of masking in fabrication of IC?
Masking is used to identify the location in which Ion-Implantation should not take place.
17. What lire the materials used for masking?
Photo resist, Si02, SiN, Poly Silicon.
18. What are the types of Photo etching?
Wet etching and dry etching are the types of photo etching.
19. What is diffusion process? What are doping impurities?
Diffusion is a process in which impurities are diffused into the Silicon chip at 1000 C
temperature
20. What is Ion-Implantation process?
It is process in which the Si material is doped with an impurity by making the accelerated
impurity atoms to strike the Si layer at high temperature.
21. What are the various Silicon wafer Preparation?
• Crystal growth & doping
• Ingot trimming & grinding
• Ingot slicing
• Wafer polishing & etching
• Wafer cleaning.
22. What are the different types of oxidation?
The two types of oxidation are Dry & Wet Oxidation.
23. What is Isolation?
It is a process used to provide electrical isolation between different components and
interconnections.
24. Give the different types of CMOS process?
• p-well process
• n-well process
• twin-tub process
• SOI process
25. What is Channel-stop Implantation?
In n-well fabrication, n-well is protected with the resist material. (Because, it should not
be affected during Boron implantation). Then Boron is implanted except n-well. The
above said process is done using photo resist mask. This type of implantation is known
as Channel-stop implantation.
26. What is LOCOS?
LOCOS mean Local Oxidation of Silicon. This is one type of oxide construction.
27. What is SWAMI?
SWAMI means Side Wall Masked Isolation. It is used to reduce bird's beak effect.
28. What is LDD?
LDD means Lightly Doped Drain Structures. It is used for implantation of n- region in n-well
process.
29. What is Twin-tub process? Why it is called so?
Twin-tub process is one of the CMOS technologies. Two wells (the other name for well is Tub)
are created in this process. So, because of these two tubs, this process is known as Twin-
tub process.
30. What are the steps involved in twin-tub process?
• Tub Formation
• Thin-oxide Construction
• Source & Drain Implantation
• Contact cut definition
• Metallization.
31. What are the special features of Twin-tub process?
In Twin-tub process, Threshold voltage, body effects of n and p devices are independently
optimized.
32. What are the advantages of Twin-tub process?
Advantages of Twin-tub process are (1) Separate optimized wells are available. (2) Balanced
performance is obtained for n and p transistors.
33. What is SOI? What is the material used as Insulator?
SOI means Silicon-on-Insulator. In this process, a Silicon based transistor is built on an
insulating material like Sapphire or SiO2.
34. What are the advantages and disadvantages of SOI process?
Advantages of SOI process: 1. There is no well formation in this process. 2. There is no field-
Inversion problem. 3. There is no body effect problem.
Disadvantages of SOI process: 1. It is very difficult to protect inputs in this process. 2. Device
gain is low. 3. The coupling capacitance between wires always exists.
35. What are the advantages of CMOS process?
• Low Input Impedance
• Low delay Sensitivity to load.
36. What are the various etching processes used in SOI process?
Various etching processes used in SOI are, Dry and Wet etching
37. What is BiCMOS Technology?
It is the combination of Bipolar technology & CMOS technology.
38. What are the basic processing steps involved in BiCMOS process?
Additional masks defining P base region
• N Collector area
• Buried Sub collector (SCCD)
• Processing steps in CMOS process
39. What is meant by interconnect? What are the types are of interconnect?
Interconnect means connection between various components in an IC.
Types of Inter connect: 1. Metal Inter connect 2. PolySilicon Inter connect 3. Local Inter
connect.
40. What is Silicide?
The combination of Silicon and tantaleum is known as Silicide. It is used as gate material in
Polysilicon Interconnect.
41. What is Polycide?
The combination of Silicide and Polysilicon is known as Polycide. It is used as gate material.
42. What is Stick diagram?
The diagram which conveys the layer information through the use of various colours is known as
Stick diagram. It is also the cartoon of a chip layout.
43. What are the uses of Stick diagram?
• It can be drawn much easier and faster than a complex layout.
• These are especially important tools for layout built from large cells.
44. Give the various color coding used in stick diagram?
• Green - n-diffusion
• Red - polysilicon
• Blue - metal
• Yellow - implant
• Black - contact areas.
45. Compare between CMOS and bipolar technologies.
CMOS Technology Bi-polar Technology
• Low static power dissipation
• High input impedance (low drive current)
• Scalable threshold voltage
• High noise margin
• High packing density
• High delay sensitivity to load (fanout limitations)
• Low output drive current
• Low gm (gm α Vin)
• Bidirectional capability
• A near ideal switching device7
• High power dissipation
• Low input impedance (high drive current)
• Low voltage swing logic
• Low packing density
• Low delay sensitivity to load
• High output drive current
• High gm (gm a eVin)
• High ft at low current
• Essentially unidirectional
46. Define Threshold voltage in CMOS?
The Threshold voltage, VT for a MOS transistor can be defined as the voltage applied between
the gate and the source of the MOS transistor below which the drain to source current,
IDS
effectively drops to zero.
47. What is Body effect?
The threshold voltage VTh is not a constant with respect to the voltage difference between the
substrate and the source of MOS transistor. This effect is called substrate-bias effect or body
effect.
48. What is Channel-length modulation?
The current between drain and source terminals is constant and independent of the
applied voltage over the terminals. This is not entirely correct. The effective length of the
conductive channel is actually modulated by the applied VDS, increasing VDS causes the
depletion region
at the drain junction to grow, reducing the length of the effective channel.
49. What is Latch – up?
Latch-up is a condition in which the parasitic components give rise to the establishment of low
resistance conducting paths between VDD and VSS with disastrous results. Careful control
during fabrication is necessary to avoid this problem.
50. What is demarcation line?
Demarcation line is an imaginary line used in stick diagram, to separate p-MOS and n-MOS
transistors.
All p-MOS transistors are placed above demarcation line and n-MOS below the demarcation line
51. What are the two types of Layout design rules?
Lambda design rules and micron rules are major types of layout design rules.
52. What is Lay-out design rule?
The rules followed to prepare the photo mask are known as Layout design rules.
53. What are LVS and DRL tools?
LVS means Layout Versus Schematic. It checks layout against schematic diagram. It is very
important to verify layout.
DRC means Design Rule Checker. This tool checks every occurrence of design rule list on
layout. Width, spacing of every metal line in layout are checked with this tool.
54. What is instance? What is instancing?
To construct big complex circuit, the basic cells (small cells) can be copied. This process is
known as Instancing. The cell which is copied is known as Instance.
55. What is flat cell?
The cell which is independent and not related to other objects is known as flat cell.
56. What are the cells available in primitive library?
NOT, NAND, NOR, are the basic cells in primitive library.
57. What is Design Hierarchy?
When we want to design AND-4 input gate, we use NAND-2 and NOR-2 basic blocks.
By combining NAND-2 and NOR-2, we create AND-4 input gate. This is known as
Design Hierarchy.
58. Which is the software used in this lab?

cadence .

59. What are the other alternative software apart from cadence used for VLSI design?
Microwind, Tanner, Hspice, Pspice, Mentor graphics, Xilinx etc…
60. Name the Simulator used in cadence for simulation ?

Insim or incisive simulator

61. What is RTL ?

RTL stands for Register Transfer Level. It is a high-level hardware description language (HDL)
used for defining digital circuits. The most popular RTL languages are VHDL and Verilog.

62. What is the difference between simulation and synthesis?

Simulation is used to verify the functionality of the circuit.. a)Functional Simulation: study
of ckt's operation independent of timing parameters and gate delays. b) Timing Simulation
:study including estimated delays, verify setup, hold and other timing requirements of devices
like flip flops are met

Synthesis: One of the foremost in back end steps where by synthesizing is nothing
but converting VHDL or VERILOG description to a set of primitives or
components(as in FPGA'S)to fit into the target technology. Basically the synthesis tools
convert the design description into equations or components.

63. Which is the tool used for analog design of vlsi circuits?

Virtuoso

64. What is the platform for virtuoso?

Encounter

65. Why don’t we use just one NMOS or PMOS transistor as a transmission gate?

Because we can't get full voltage swing with only NMOS or PMOS .We have to use both
of them together for that purpose.

66. Why don’t we use just one NMOS or PMOS transistor as a transmission gate?

nmos passes a good 0 and a degraded 1 , whereas pmos passes a good 1 and bad 0. for
pass transistor, both voltage levels need to be passed and hence both nmos and pmos need to be
used.

67. What are set up time & hold time constraints? What do they signify?

Setup time: Time before the active clock edge of the flip-flop, the input should be stable. If the
signal changes state during this interval, the output of that flip-flop cannot be predictable (called
metastable).
Hold Time: The after the active clock edge of the flip-flop, the input should be stable. If
the
signal changes during this interval, the output of that flip-flop cannot be predictable (called
metastable).

68. Explain Clock Skew?

clock skew is the time difference between the arrival of active clock edge to different flip-flops’
of the same chip.

69. Why is not NAND gate preferred over NOR gate for fabrication?

NAND is a better gate for design than NOR because at the transistor level the mobility
of electrons is normally three times that of holes compared to NOR and thus the NAND is a
faster gate. Additionally, the gate-leakage in NAND structures is much lower.

70. What is Body Effect?

In general multiple MOS devices are made on a common substrate. As a result, the
substrate voltage of all devices is normally equal. However while connecting the devices
serially this may result in an increase in source-to-substrate voltage as we proceed vertically
along the series chain (Vsb1=0, Vsb2 0).Which results Vth2>Vth1.

71. Why is the substrate in NMOS connected to Ground and in PMOS to VDD?

we try to reverse bias not the channel and the substrate but we try to maintain the drain,
source junctions reverse biased with respect to the substrate so that we don’t loose our current
into the substrate.

72. What is the fundamental difference between a MOSFET and BJT ?

In MOSFET, current flow is either due to electrons (n-channel MOS) or due to holes(p-
channel MOS) - In BJT, we see current due to both the carriers..Electrons and holes. BJT is
a current controlled device and MOSFET is a voltage controlled device

73. In CMOS technology, in digital design, why do we design the size of pmos to be higher
than the nmos. What determines the size of pmos wrt nmos. Though this is a
simple question try to list all the reasons possible?

In PMOS the carriers are holes whose mobility is less[ aprrox half ] than the electrons,
the carriers in NMOS. That means PMOS is slower than an NMOS. In CMOS technology,
nmos helps in pulling down the output to ground PMOS helps in pulling up the output to Vdd.
If the sizes of PMOS and NMOS are the same, then PMOS takes long time to charge up the
output node. If we have a larger PMOS than there will be more carriers to charge the node
quickly and overcome the slow nature of PMOS . Basically we do all this to get equal rise and
fall times for
the output node.
74. Why PMOS and NMOS are sized equally in a Transmission Gates?

In Transmission Gate, PMOS and NMOS aid each other rather competing with each other. That's
the reason why we need not size them like in CMOS. In CMOS design we have NMOS
and
PMOS competing which is the reason we try to size them proportional to their mobility.

75. What happens when the PMOS and NMOS are interchanged with one another in an
inverter?

If the source & drain also connected properly...it acts as a buffer. But suppose input is logic 1
O/P will be degraded 1 Similarly degraded 0

76. Why are pMOS transistor networks generally used to produce high signals, while
nMOS networks are used to product low signals?

This is because threshold voltage effect. A nMOS device cannot drive a full 1 or high and
pMOS can’t drive full '0' or low. The maximum voltage level in nMOS and minimum voltage
level in pMOS are limited by threshold voltage. Both nMOS and pMOS do not give rail to rail
swing.

77. What’s the difference between Testing & Verification?

Testing: A manufacturing step that ensures that the physical device , manufactured from the
synthesized design, has no manufacturing defect.

Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will
perform the given I/O function

78. What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do
you avoid Latch Up?

A latch up is the inadvertent creation of a low-impedance path between the power supply rails of
an electronic component, triggering a parasitic structure(The parasitic structure is usually
equivalent to a thyristor or SCR), which then acts as a short circuit, disrupting proper functioning
of the part. Depending on the circuits involved, the amount of current flow produced by
this mechanism can be large enough to result in permanent destruction of the device due to
electrical over stress - EOS

79. What is slack?

The slack is the time delay difference from the expected delay(1/clock) to the actual delay in a
particular path. Slack may be +ve or -ve.

80. Explain how logical gates are controlled by Boolean logic?

In Boolean algebra, the true state is denoted by the number one, referred as logic one or logic
high. While, the false state is represented by the number zero, called logic zero or logic low.
And in the digital electronic, the logic high is denoted by the presence of a voltage potential.
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81. Mention what are the different gates where Boolean logic are applicable?
· NOT Gate: It has one out input and one output. For example, if the value of A= 0 then
the Value of B=1 and vice versa
· AND Gate: It has one output due to the combination of two output. For example, if the
value of A and B= 1 then value of Q should be 1
· OR Gate: Either of the value will show the same output. For example, if the value of A
is 1 or B is 0 then value of Q is 1
These are the basic three types of gates where Boolean logic work, apart from these, other gates
that are functional works with the combination of these three basic gates, they are XNOR gate,
NAND gate, Nor gate and XOR gate.

82. Explain how binary number can give a signal or convert into a digital signal?

Binary number consists of either 0 or 1, in simple words number 1 represents the ON state
and number 0 represents OFF state. These binary numbers can combine billion of machines into
one machines or circuit and operate those machines by performing arithmetic calculations and
sorting operations.

83. Mention what is the difference between the TTL chips and CMOS chips?

TTL Chips CMOS Chips

· TTL chips for transistor transistor logic.
It uses two Bi-polar Junction Transistors
in the design of each logic gate
· TTL chips can consist of a substantial
number of parts like resistors
· TTLS chip consumes lot more power
especially at rest. A single gate in TTL
chip consumes about mW of power
· TTL chips can be used in computers
· CMOS stands for Complementary
Metal Oxide Semi-conductor. It is
also an integrated chip but used field
effect transistors in the design
· CMOS has greater density for logic
gates. In a CMOS chip, single logic gate
can comprise of as little as two FETs
· CMOS chips consume less power. A
single CMOS chip consume about
10nW of power
· CMOS chip is used in Mobile phones

84. Explain what is a sequential circuit?

A sequential circuit is a circuit which is created by logic gates such that the required logic at the
output depends not only on the current input logic conditions, but also on the sequences
past inputs and outputs.

85. Explain how Verilog is different to normal programming language?

Verilog can be different to normal programming language in following aspects

· Simulation time concept

· Multiple threads
· Basic circuit concepts like primitive gates and network connections
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86. Explain what is Verilog?
Verilog is an HDL (Hardware Description Language) for describing electronic circuits and
systems. In Verilog, circuit components are prepared inside a Module. It contains both
behavioral and structural statements. Structural statements signify circuit components like
logic gates, counters and micro-processors. Behavioral statements represent programming
aspects like loops, if-then statements and stimulus vectors.

87. In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

In Verilog code, the unit of time is 1 ns and the accuracy/precision will be upto 1ps.

88. Mention what are the two types of procedural blocks in Verilog?
The two types of procedural blocks in Verilog are
· Initial: Initial blocks runs only once at time zero
· Always: This block loop to execute over and again and executes always, as the
name
suggests

89. Explain why present VLSI circuits use MOSFETs instead of BJTs?
In comparison to BJT, MOSFETS can be made very compact as they occupy very small silicon
area on IC chip and also in term of manufacturing they are relatively simple. Moreover,
digital and memory ICs can be employed with circuits that use only MOSFETs, i.e., diodes,
resistors, etc.

90. Mention what are three regions of operation of MOSFET and how are they used?
MOSFET has three regions of operations
· Cut-off region
· Triode region
· Saturation region
The triode and cut-off region are used to function as a switch, while, saturation region is used to
operate as an amplifier.

91. Explain what is the depletion region?

When positive voltage is transmitted across Gate, it causes the free holes (positive charge) to be
pushed back or repelled from the region of the substrate under the Gate. When these holes are
pushed down the substrate, they leave behind a carrier depletion region.

92. Explain why is the number of gate inputs to CMOS gates usually limited to four?
Higher the number of stacks, slower the gate will be. In NOR and NAND gates the number of
gates present in the stack is usually alike as the number of inputs plus one. So input are restricted
to four.

92. Explain what is multiplexer?

A multiplexer is a combination circuit which selects one of the many input signals and direct to
the only output.
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