IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 63, NO.
4, APRIL 2016 341
An Amplifier-Free Pipeline-SAR ADC Architecture
With Enhanced Speed and Energy Efficiency
Junfeng Gao, Guangjun Li, Letian Huang, and Qiang Li
Abstract—A new pipeline-successive approximation regis-
ter (SAR) analog-to-digital converter (ADC) structure without
residue amplifier and timing-interleaving is presented in this
brief. Two redistribution digital-to-analog converters (DACs) and
comparators are adopted in two stages, with DAC1 for most
significant bit (MSB) comparisons and DAC2 for least significant
bit (LSB) comparisons. The previous sampled signal is transferred
from DAC1 to DAC2 through charge sharing so that previous
LSB conversions can operate simultaneously with the next sam-
ple and MSB conversions, which increases the conversion speed.
With a 0.5 scale factor between two stages and multicomparator
offsets, offset calibration has to be obtained to eliminate offset
nonlinearity. The number of conversion cycles required by the
proposed design is only 6 and sampling requires no extra time,
which is 3 cycles fewer than traditional SAR ADC. The behavioral
model of the 8b proposed design proves the performance stability
with parasitic capacitance variation, capacitor mismatch, offset,
and noise errors. An 8b prototype is designed in a 65-nm CMOS
technology. The supply voltage is 1.2 V, with a 500-MS/s sampling
rate. The circuit simulation results achieve 7.49b ENOB with
1.53-mW power consumption. The simulated FoM is 17 fJ/conv.
Index Terms—Amplifier-less, low power, pipeline-successive ap-
proximation register (SAR) analog-to-digital converter (ADC).
I. I NTRODUCTION
S uccessive approximation register (SAR) analog-to-digital
converters (ADCs) are quickly emerging into high-speed
data converters with excellent power efficiency and technology
advantages. Research on single-channel SAR ADCs [1]–[7]
tremendously improve their performance to several tens of
MS/s and GS/s with resolution between 6 bits and 10 bits, while
their FoMs1 remain only dozens of fJ/conv.
The speed of single-channel SAR ADCs is limited by the
comparator latching speed and the number of conversion cycles,
which are difficult to minimize for fixed resolution even with a
Manuscript received June 11, 2015; revised August 9, 2015; accepted
October 10, 2015. Date of publication November 25, 2015; date of current
version March 24, 2016. This work was supported by the National Natural
Science Foundation of China under Grant 61534002 and Grant 61006027, by
the Chinese National Program for Support of Top-Notch Young Professionals
(1st Batch), and by the National Key Laboratory of Analog Integrated Circuits.
This brief was recommended by Associate Editor E. Bonizzoni.
The authors are with the Integrated Systems Laboratory, University of
Electronic Science and Technology of China, Chengdu 610054, China; with
the School of Microelectronics and Solid-State Electronics, University of
Electronic Science and Technology of China, Chengdu 610054, China; with
the National Key Laboratory of Electronic Thin Films and Integrated Circuits,
University of Electronic Science and Technology of China, Chengdu 610054,
China; and also with the School of Communication and Information Engi-
neering, University of Electronic Science and Technology of China, Chengdu
610054, China (e-mail: qli@uestc.edu.cn).
Color versions of one or more of the figures in this brief are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSII.2015.2503705
1 F oM = P owerADC /(2ENOB × fsample )
1549-7747 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
higher voltage and a larger current. Research in [1], [4], and [5]
presents 2-bit/cycle conversion flash-SAR hybrid ADCs with
three redistribution digital-to-analog converters (DACs) and
three comparators converting in the parallel structure. The ben-
efit of the flash-SAR structure is the half number of conversion
cycles, which greatly enhances the conversion speed. Reference
[5] further removes one DAC from the 2-bit/cycle conversion
system by adopting a reference DAC and a non-radix-2 DAC
structure, which simplifies the control logic and reduces DAC
power. Research in [6] and [7] employs multicomparators op-
erating in serial mode to minimize the delay of control logic
circuits and provide a longer time for switching and more
reset time for comparators to eliminate the memory effect. The
design difficulties of these SAR ADCs are the nonlinearity
errors from the comparator offsets requiring calibration.
To enhance the conversion speed, time-interleaving (TI) SAR
ADCs combined with 2-bit/cycle structures up to GS/s sam-
pling rate are also analyzed [8], [9]. However, the performance
is affected by timing mismatch and comparator offsets. The
pipeline-SAR structure of single-channel ADCs [10] also has
high resolution and speed benefits, resulting in design difficul-
ties of power-consuming residue amplifiers with nonlinearity
errors. Reference [11] replaces amplifiers with a binary-search
structure and a TI system, which reduces power consumption
while leading to timing mismatch and offset nonlinearities.
In this brief, a single-channel pipeline-SAR ADC architecture
without timing mismatch and residue amplifier is presented.
The structure reduces power consumption while enhancing the
conversion speed. The performance of linearity and conversion
speed is analyzed in the behavioral model. An 8b 500-MS/s
SAR ADC with the proposed structure is designed in a 65-nm
CMOS technology. The supply voltage is 1.2 V. The circuit sim-
ulation results show 7.49b ENOB with only 1.53-mW power
consumption. The simulated FoM is 17 fJ/conv.
This brief is organized as follows. Section II discusses the
proposed pipeline-SAR ADC structure. Speed and linearity are
analyzed in Section III. The simulation results are described in
Section IV. Section V gives the conclusion of this brief.
II. A RCHITECTURAL C ONSIDERATION
A. TI-Less Pipeline-SAR ADC Without Amplifiers
In this section, the proposed 8b TI-less pipeline-SAR ADC
is implemented in two stages with two comparators, two DACs,
and overlapped conversion cycles. The detailed structure is
introduced in Fig. 1 with only 3b most significant bits (MSBs)
in stage1 and least significant bit (LSB) conversions overlap
with MSBs of the next sample in stage2.
Without the TI system and residue amplifiers, charge sharing
is adopted to transfer signals from DAC1 in stage1 to DAC2
342 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 63, NO. 4, APRIL 2016
Fig. 1. 8b TI-less pipeline-SAR ADC architecture with offset calibration.
in stage2. The switching logic and charge-sharing architecture
operates in the following way. The analog input Vin is sampled
through Φs and converted on DAC1 . After 3b MSB conversions
on DAC1 , the signal is transferred to DAC2 through charge
sharing cycle Φcs , which avoids timing mismatch errors (no ex-
tra sampling clock). Φcs operates simultaneously with the third
bit DAC redistribution. After charge sharing, LSB conversions
are processed on DAC2 , which operates simultaneously with
the next sample in its sampling phase and MSB conversion. To
eliminate the memory effect of the previous comparison, the
differential-end of DAC2 is connected together by clock Φcm
after LSB decision during the next MSB conversions, which
takes no extra cycles.
To maintain radix-2 conversion, two DACs have equal ca-
pacitances, and the residue voltage of DAC1 is sampled on
DAC2 with a 0.5 scale factor through charge sharing. The
capacitance of either DAC is doubled compared to traditional
SAR ADCs (with the same unit capacitance). However, most of
the capacitance of DAC2 is connected directly to the reference
voltage without switch connections so that the speed of DAC2 is
much faster than the traditional DAC, resulting in shorter LSB
cycles.
The switch parasitic capacitance during Φcs may provide
nonlinearity errors to the residue voltage, so switches with a
smaller parasite are preferred. If the common-mode voltages of
DACs are Vcm and remain stable during conversion [12], the
switches in Φcs have to be complimentary switches or boosted
switches. If the common-mode voltage of DACs is driven
to Vrefn during redistribution by employing the switchback
switching scheme in [13], then DAC2 can be connected to Vrefn
during Φcm with both Φcm and Φcs switches implemented by
a single NMOS, which achieves a small parasitic capacitance.
However, due to common-mode voltage variation, a PMOS
input comparator with good common-mode rejection is also
required.
For SAR ADCs, the number of conversion cycles includ-
ing sampling time dominates their conversion speed. Without
Fig. 2. Comparator circuits with offset calibration.
conversion cycle time adjustment, the MSB cycle can be con-
sidered as the longest conversion cycle, representing the time
of a single conversion cycle. Owing to the overlapped operating
cycles with the next sample, the total conversion cycles of the
proposed architecture can be 6, including sampling and charge
sharing. It can also be expected to employ the 2-bit/cycle struc-
ture in [1] and the TI system to further accelerate the conversion
speed.
B. Comparator With Offset Calibration
Comp1 and comp2 share the same comparator circuits (dif-
ferent transistor sizes), which are illustrated in Fig. 2. The
common-mode voltage of comp2 is around 260 mV for a 1.2-V
supply in the proposed design, requiring a smaller size of
current tail M5 to meet the needs of noise and offset. Therefore,
M5 in comp2 is only half of that in comp1. Comparator offsets
are adjusted by modifying the bulk voltage of input transistors
M1 and M2, which are controlled by 5-bit calibration DACs and
additional 1-bit sign control of offsets. One calibration DAC
with two adjusting circuits for two comparators can be imple-
mented by a resistor ladder with 1-pF decoupling capacitors
connected to each bulk. The total resistance of the calibration
DAC is 13 kΩ with less than 100-μW power consumption. The
smallest calibration voltage on the bulk is 910 mV with more
than ±20-mV offset calibration range. Simulated offset σ of
comparators is less than 6 mV (Monte Carlo simulation).
Calibration codes cal1 (MSB) and cal2 (the fourth bit) provide
digital outputs for the zero input of each comparator during
calibration. Sampling phase Φcs of DAC2 is disabled during
foreground calibration. Based on cal1 and cal2 , offsets are man-
ually adjusted toward zero by calibration DACs by changing
bulk voltages of comparator input transistors.
C. Control Logic With Meta-Stability Reduction
Meta-stability errors are considered to happen at small inputs
less than 1/10 or 1/20 LSB (depending on comparator speed),
which is too slow to switch for the following comparisons
(DAC usually will not be switched). Therefore, if meta-stability
errors are regarded as noise and switching logic operates in nor-
mal state, the following conversion cycles will still get correct
decisions.
The control logic of the proposed design is implemented with
two sets of registers, which can reduce the influence of meta-
stability from comparators. The detailed circuits and timing
GAO et al.: PIPELINE-SAR ADC ARCHITECTURE WITH ENHANCED SPEED AND ENERGY EFFICIENCY
Fig. 3. Control logic and switch generation circuits.
diagram are shown in Fig. 3. Φ2 is the reset signal of the registers
for comp2. rdy1 and rdy2 are the ready signals for comp1 and
comp2. rst1 and rst2 are the clock signals for comp1 and comp2.
rdy1 and rdy2 trigger one set of registers to generate clock
ri (i = 8, 7, . . . , 1) for comparator decisions. Another set of
registers uses ri to register comparator output dp, generating
decisions di . As shown in Fig. 1, the switching logic implemen-
tations depend on the DAC connections during sampling. swi,p
and swi,n are the control signals for the DAC switches. If the
capacitor bottom plate is connected to Vrefp , then the switching
logic uses AND gates to switch to Vrefn during redistribution.
If the capacitor bottom plate is connected to Vrefn , then NAND
gates are adopted.
In the proposed control logic, only one comparator output dp
is registered. Switching logics are generated from dp and ri .
ri signals are triggered by ready signals rdy1 and rdy2 , which
depend on the common mode of the comparator latching nodes
with less than 10% delay variation (75-ps delay from rst1 and
rst2 ). dp is reset to 0. If dp is 1 but has a meta-stability error
(small input result in slow latching speed), then the switching
logic considers the registered value of dp as 0 (small input
regards as noise) and continues switching under control of ri .
Therefore, the switching logic operates normally when small
inputs of comparators leading to meta-stability errors and the
following conversions will not be affected.
III. S PEED AND L INEARITY A NALYSES
A. Speed Analysis
The conversion speed of the proposed design is determined
by the number of conversion cycles. To calculate cycle time, the
MSB cycle with the longest conversion time tmsb is adopted.
tmsb includes comparator latching time tcomp , logic delay tlogic ,
and DAC redistribution time tDAC . To compare with other SAR
343
ADC structures, tcomp and tlogic are considered equal with the
same total DAC capacitance. Also, tcomp and tlogic of each
conversion cycle usually contribute to 40% of a cycle time
(in high-speed SAR ADC) and vary within 10% (on average),
which makes tDAC the most important time variation for each
conversion cycle.
To evaluate sampling time by tmsb , doubled sampling re-
sistance (including sampling switch and DAC switches) and
capacitance compared to MSB have to be considered. Although
larger switches result in faster settling speed and higher ac-
curacy, the sampled signal fluctuates due to the second-order
impact of the parasitic inductance in the bonding wire, which
requires more time to eliminate such fluctuation errors and
achieve higher linearity (without internal input buffer). As a
result, the sampling phase employs at least 2tmsb to maintain
the sampling accuracy. Therefore, the proposed design saves
3 cycles compared to the traditional 8b SAR ADC (LSB does
not need redistribution).
The proposed design operates sampling and comparisons si-
multaneously. Memory effect cancellation phase Φcm of stage2
overlaps with the MSB conversions of the next sample. Charge
sharing cycle Φcs also operates simultaneously with the third
conversion cycle. To evaluate the time of the third cycle com-
bined with Φcs by tmsb , the Φcs requires less time than tDAC ,
which is discussed in the following.
C1 = C2 is the total capacitance of DAC1 and DAC2 . Rb and
Rcs are the ON resistances of the MSB bottom-plate switch of
DAC1 and the Φcs switch. The other bottom-plate switches of
DAC1 are assumed to be scaled down in radix-2. The bottom-
plate switches of DAC2 are ignored because most capacitors
are directly connected to the reference. 32Vlsb is the maximum
voltage variation during charge sharing due to 3 MSB redistrib-
utions already established in stage1 (Vlsb is the LSB voltage of
DAC2 ). The settling error is assumed to be smaller than 0.5Vlsb .
Therefore, the RC time constant of DAC1 satisfies 1/3(Rb +
2/(jωC1 )) during Φcs , and the total RC time constant satisfies
1/3(Rb + 2/(jωC1 )) + Rcs +1/(jωC2 )) = 1/3Rb +Rcs + 5/
(3jωC1 ). Considering first-order step response e−t/τ <
0.5Vlsb , the charge-sharing time tcs,1 requirement is shown in
(1). On the other hand, 128Vlsb is the redistribution voltage in
the MSB cycle. The time for MSB DAC redistribution tDAC is
shown in (2). If Rcs < 0.93Rb, then tcs,1 < tDAC . In the pro-
posed design, Rcs is implemented by a single NMOS switch,
which makes it easy to achieve such resistance with a small
size. As a result, Φcs time is shorter than tDAC and the third
cycle can be evaluated by tmsb
tcs,1  −ln((0.5Vlsb )/(0.6 · 32Vlsb )(0.6Rcs + 0.2Rb )C1
≈ 934C(0.6Rcs + 0.2Rb ) (1)
 
(0.5Vlsb )
tDAC  −0.5 ln Rb C1
(128Vlsb )
≈ 710CRb . (2)
To compare the performance, different SAR ADCs are sum-
marized in Table I, including the conversion time, the sampling
time (cycle), the LSB voltage, the number of comparators, and
the calibration circuits. A traditional SAR ADC has two cycles
for sampling and seven cycles for conversion. A 2-bit/cycle
flash-SAR ADC structure has two cycles for sampling, three
cycles for conversion, and 0.5 cycles for pre-establishing before
344 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 63, NO. 4, APRIL 2016

TABLE I
S UMMARY OF D IFFERENT 8b S INGLE -C HANNEL
SAR ADC S TRUCTURES

MSB comparison (logic delay is ignored). By shifting the

LSB cycles into the next sample, the conversion speed of the
proposed design is greatly enhanced to only six cycles, which
is almost as fast as the 2-bit/cycle structure. The proposed
design also achieves a longer sampling time (three cycles) with
Fig. 4. Influence of the parasitic capacitance of two DACs in 8b TI-less
higher accuracy. If the 2-bit/cycle structure is combined with pipeline-SAR ADCs.
the proposed design, less conversion time can even be expected.
For the 8b design, the LSB voltage of the proposed design is
more than 4 mV (1.2-V supply), which makes it easy to satisfy
the noise requirement. Charge sharing significantly reduces the
power consumption of the proposed design. However, without
residue amplification, the proposed design requires a higher
power of comp2 to reduce noise and more decoupling capac-
itors on the reference.

B. Linearity Analysis
By removing the residue amplifier, the linearity of the pro-
posed design is determined only by the capacitor mismatch and
the parasitic capacitance.
The largest DNL happens at the middle code switching
from 011 · · · 1 to 100 · · · 0, with the maximum 28+1 − 32 ca-
pacitors switched. The√ maximum unit capacitance mismatch
is σmismatch < 0.5/ 28+1 − 32/3 × 4 ≈ 3% for 8b TI-less
pipeline-SAR ADCs. The coefficient 4 means that two capaci-
tors are switched in LSB conversion with doubled LSB voltage
in DAC1 compared to DAC2 . With the same unit capacitance,
the total capacitance of the proposed design is twice
√ of the
switchback switching scheme in [13], resulting in 2 linearity
improvement. Inversely, the same total capacitance of each
DAC (half unit capacitance) can achieve the same linearity.
The influence of the detailed models with parasitic capaci-
tance and capacitor mismatch is analyzed. In the models, the
parasitic capacitance of DAC2 is assumed to be 28.5 fF or
10% of the total capacitance, which is overestimated for the
layout parasite including comparator inputs and switches. The
reference voltage of the behavioral model is Vref = 1 V. Monte
Carlo simulation results are carried out with 3σ capacitor
mismatch, comparator noise, and reference noise. These pa-
rameters come from circuit simulation results with decoupling
capacitors.
Considering the parasitic capacitance variation between two
DACs, the performance of the proposed design is illustrated
in Fig. 4. The performance is affected by the capacitance
ratio of two DACs during charge sharing, which drops to 7b
with a larger parasitic capacitance of DAC1 . According to the
behavioral model, a relatively smaller parasitic capacitance of
DAC1 can keep the performance more stable in the layout
design.
Fig. 5. Performance of the behavioral model (1000 simulations).
The different capacitances between two DACs during charge
sharing mainly come from the layout and switch Rcs . Lay-
out parasitic differences can be minimized through symmetric
geometry and parasitic extraction. Switch size is optimized by
using a single NMOS. In the schematic design, only a 3-μm
NMOS is adopted with a 3-fF maximum parasitic capacitance
and a smaller parasitic variation. NMOS switches only close in
the charge-sharing cycle. Therefore, their connection statuses
are the same for DAC1 and DAC2 during charge sharing and
redistribution. Different voltage drops on the source and drain
of the NMOS switches result in a parasitic variation less than
the unit capacitance. With other static parasitic capacitances,
the parasitic variation is less than 2% of the total parasite, which
does not affect the charge-sharing accuracy.
The 1000 times Monte Carlo simulation results of the behav-
ioral model of the proposed design are shown in Fig. 5 (para-
sitic capacitance included). Capacitor mismatch is σmismatch =
1%. Either comparator noise error or reference noise error is
σnoise = 0.5 mV. The comparator offset is σoffset = 7 mV. The
reference voltage is 1 V. The offset calibration accuracy is 1 mV.
With offset calibration, the average ENOB of the behavioral
model is over 7.6b.
GAO et al.: PIPELINE-SAR ADC ARCHITECTURE WITH ENHANCED SPEED AND ENERGY EFFICIENCY
Fig. 6. Dynamic performance of the schematic simulation of the proposed
design. (a) Low-frequency input. (b) Near-Nyquist-frequency input.
IV. S IMULATION R ESULTS
To verify the proposed structure, a prototype TI-less pipeline-
SAR ADC is designed in a 65-nm CMOS technology with
simulated transient noise up to 200 GHz. A MOM capacitor
with unit capacitance C = 0.5 fF is adopted with mismatch
σmismatch < 1% (a 2.4-fF MOM capacitor can obtain less
than 0.43% mismatch from technology documents). The total
capacitance for either DAC1 or DAC2 is 128 fF. The sampling
rate of the prototype SAR ADC is 500 MS/s at 1.2-V voltage
supply (the LSB voltage is 4.4 mV). The circuits include a
bonding wire model with 3-nH parasitic inductance and 500-fF
parasitic capacitance. 3σ comparator offset errors are added
(comp1 and comp2 have different sign 3σ offsets) with offset
calibration based on bulk voltage adjustment through a 5-bit
calibration DAC. Through schematic simulation, the dynamic
performance of the prototype ADC is shown in Fig. 6. The sim-
ulated performance has 7.49b ENOB at near-Nyquist frequency
including noise and offset errors.
The simulated power consumption of the prototype is
1.53 mW, including the calibration DAC without layout para-
site. The prototype pipeline-SAR ADC has a 17-fJ/conv FoM.
comp2 consumes about 30% of the total power consumption,
while comp1 consumes about 17%. However, comp2 has 2
345
more cycles in each conversion, which means comp2 only
consumes 6% more power than comp1. In fact, the power
consumption of comparators is mainly determined by the high
speed and mismatch requirements.
V. C ONCLUSION
In this brief, a single-channel pipeline-SAR ADC structure
without residue amplifier and TI has been proposed with speed
enhancement. Compared to the conventional SAR ADC, the
con of the proposed design is the smaller LSB voltage, result-
ing in larger noise performance. The positive aspects of the
proposed design is fewer conversion cycles, no additional
cycle time for sampling, and longer sampling time resulting
in smaller sampling switches. Compared to traditional pipeline-
SAR ADCs, the residue amplifier is removed from the proposed
design with less nonlinearity errors and power consumption.
Compared to the TI SAR ADCs, the architecture introduces
zero timing mismatch error. From the behavioral model, the sta-
tistical results prove the stability of the introduced architecture
with mismatch, offset, noise, and parasitic variation considered.
From the schematic simulation results, the proposed design
with 3σ offsets and offset calibration technique achieves 7.49b
ENOB at 500 MS/s with 1.2-V supply and bonding wire
parasites.
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