LiU Tek Lic 2003 E - Hjalmarson

Linköping Studies in Science and Technology
Thesis No. 1065
STUDIES ON DESIGN AUTOMATION

OF ANALOG CIRCUITS
– THE DESIGN FLOW
Emil Hjalmarson
LiU-Tek-Lic-2003:30
Department of Electrical Engineering
Linköpings universitet, SE-581 83 Linköping, Sweden
Linköping, December 2003
Studies on Design Automation of Analog Circuits – The Design Flow
Copyright © 2003 Emil Hjalmarson
Department of Electrical Engineering

Linköpings universitet
SE-581 83 Linköping
Sweden
ISBN 91-7373-878-6 ISSN 0280-7971

ABSTRACT
During the past few years the concept of system-on-chip (SoC) have become an
important segment in the market of integrated circuits. This recent development
have increased not only the number of devices and the functionality that can be
put on a chip, but the chips now includes both digital and analog circuits.
In digital design the level of abstraction and automation in the design flow have
manage to keep in phase with this development. However, this is not the case for
analog circuits. The analog design flow suffers from a low-level of abstraction
and automation, making it one of the major bottlenecks in mixed-signal design.
Here we address the problem of automating the analog design flow. Specifically,
the problem of determining the design parameters for an analog integrated circuit
at the cell level is considered. An optimization method in conjunction with auto-
matically derived equations for the circuit performance is used to solve this task.
The methods and algorithms used have been implemented into a tool that can be
used to design continuous-time analog amplifiers. Using this approach the
design time can be reduced from weeks to hours, at the same time the circuit per-
formance can potentially be increased.
The coupling between the device sizing and layout generation is also addressed.
A parasitic feedback approach is used in order to make sure that the performance
requirements are met for the circuit layout.
The tool is also used to explore the design space in analog amplifier design and
find trade-offs. An example where three different amplifier topologies are com-
pared is given. It shows that large savings can be made, with respect to both area
and power consumption, by selecting the best topology to meet a specific perfor-
mance specification.
i
ii
ACKNOWLEDGEMENTS
First, I would like to thank my supervisor, Professor Lars Wanhammar, for his
support, valuable discussions, and granting me the opportunity to pursue this
work.
Further, I would like to direct a special gratitude to my co-worker and friend,
M.Sc. Robert Hägglund, for always supporting the project and for sharing his
skills in the field of analog circuit design. Also, I would like to thank M.Sc.
Jonas Carlsson, Dr. Per Löwenborg, and Tekn. Lic. Henrik Ohlsson for proof-
reading this thesis.
A big thanks goes out to the rest of the staff at Electronics Systems for their sup-
port and friendship.
The work was financially supported by the Swedish Foundation for Strategic
Research (SSF).
Finally, I would like to thank my family, friends and my beautiful girlfriend
Rebecca for their support and love.
iii
iv
TABLE OF CONTENTS
I. INTRODUCTION ........................................................................................... 1
1.1. Analog Integrated Circuits ............................................................. 2
1.2. The Analog Design Flow ............................................................... 3
1.2.1. The Manual Design Methodology.............................................. 4
Topology section .................................................................... 5
Device Sizing ......................................................................... 6
Layout Generation.................................................................. 7
1.3. Challenges in Analog Design ......................................................... 7
1.4. Motivation ...................................................................................... 10
1.4.1. Goals in Analog Design Automation ......................................... 11
1.5. Scope of this Thesis........................................................................ 11
1.6. Publications Related to this Thesis................................................. 12
II. PERFORMANCE METRICS AND DESIGN ISSUES FOR ANALOG AMPLIFIERS 15

2.1. The Process Technology ................................................................ 15
2.1.1. The CMOS Devices.................................................................... 16
Large-Signal Model................................................................ 16
Small-Signal Model................................................................ 18
2.2. Performance Metrics in Amplifier Design ..................................... 19
Bandwidth and Unity-Gain Frequency .................................. 19
Phase Margin.......................................................................... 20
Positive and Negative Power Supply Rejection Ratio ........... 20
Common Mode Rejection Ratio............................................. 21
Slew Rate................................................................................ 21
Distortion................................................................................ 21
Noise....................................................................................... 23
Common-Mode Range and Output Range ............................. 24
Settling time ........................................................................... 24
v
Circuit Area, Power Consumption, and Yield ........................24
2.3. Circuit Layout .................................................................................25
Interconnect Parasitics ............................................................26
Process Tolerances..................................................................26
Thermal Effects.......................................................................28
Substrate Coupling..................................................................28
2.4. Trade-Offs in Analog Amplifier Design .........................................29
III. COMPUTER AIDED DESIGN OF ANALOG CIRCUITS ...................................31

3.1. The Automated Design Flow ..........................................................31
3.1.1. Topology Selection .....................................................................33
3.1.2. Sizing and Biasing ......................................................................33
3.1.3. Layout Generation.......................................................................34
Template-Based Layout Generation .......................................34
Rule-Based Layout Generation...............................................34
Performance Driven Layout Generation .................................35
3.2. The Knowledge-Based Approach ...................................................35
IDAC.......................................................................................37
OASYS ...................................................................................38
BLADES .................................................................................39
ISAID ......................................................................................39
3.3. Optimization-Based Device Sizing .................................................40
3.3.1. The Simulation-Based Approach ................................................40
DELIGHT.SPICE ...................................................................40
FRIDGE ..................................................................................41
MAELSTROM/ANACONDA ...............................................42
3.3.2. The Equation-Based Approach ...................................................43
OPASYN.................................................................................43
STAIC .....................................................................................44
Maulik .....................................................................................45
ASTRX/OBLX .......................................................................46
AMGIE ...................................................................................46
GPCAD ...................................................................................48
SD-OPT...................................................................................48
3.3.3. The Neural-Network Approach ..................................................49
Alpaydin..................................................................................50
3.4. Commercial Device Sizing Tools ...................................................50
vi
NEOLINEAR..........................................................................51
ANALOG DESIGN AUTOMATION ....................................51
BARCELONA DESIGN ........................................................51
ANASIFT................................................................................52
3.5. Summary of Existing Approaches ..................................................52
3.5.1. The Knowledge-Based vs. the Optimization-Based Approach ..56
3.5.2. Comparison of Optimization-Based Approaches .......................57
Preparatory Effort ...................................................................57
Execution Time .......................................................................58
Generality and Complexity .....................................................59
Accuracy .................................................................................61
Conclusion ..............................................................................61
IV. THE DESIGN PLATFORM ...........................................................................63

4.1. The Design Platform .......................................................................64
4.2. Device Size Optimization ...............................................................66
4.2.1. Entering the Circuit Topology ....................................................66
4.2.2. Optimization Parameters.............................................................66
4.3. Derivation of Performance Metrics and Constraints.......................68
Constraints ..............................................................................68
Large-Signal Metrics...............................................................68
Small-Signal Metrics ..............................................................68
Nonlinear Metrics ...................................................................68
Time-Domain Metrics.............................................................69
Other Performance Metrics.....................................................69
4.3.1. Constraints ..................................................................................69
4.3.2. Large Signal Performance Metrics .............................................70
Common-Mode Range and Output Range..............................70
4.3.3. Small-Signal Performance Metrics .............................................72
Symbolic Analysis and Modified Nodal Analysis..................72
Deriving Poles and Zeros........................................................74
Unity-Gain Frequency, Phase Margin, and DC Gain .............75
Output Noise Spectral Density................................................75
4.3.4. Nonlinear Metrics .......................................................................75
4.3.5. Time-Domain Performance Metrics ...........................................76
4.3.6. Other Performance Metrics.........................................................76
Power Consumption................................................................76
vii
Chip Area ................................................................................76
4.4. The Cost Function ...........................................................................77
4.5. Optimization Method ......................................................................78
4.6. Distributing the Optimization Tasks ...............................................79
4.7. Device Models ................................................................................80
V. LAYOUT GENERATION AND PARASITIC FEEDBACK ...................................85

5.1. Layout Generation...........................................................................85
5.1.1. Building Blocks...........................................................................86
5.1.2. Templates ....................................................................................89
5.2. Parasitics Feedback .........................................................................91
5.2.1. Convergence Issues.....................................................................92
5.3. Design Example ..............................................................................93
5.3.1. Optimization results ....................................................................94
5.4. Concluding Remarks.......................................................................97
VI. EXPLORATION AND TRADE-OFFS IN ANALOG AMPLIFIER DESIGN ..........99

6.1. The Design Space Exploration Tool ...............................................100
6.2. Design Case.....................................................................................103
6.2.1. Performance Specification ..........................................................103
6.2.2. Optimization Setup .....................................................................105
6.2.3. Optimization Results...................................................................106
6.2.4. Impact of Scaling the Power Supply Voltage .............................107
6.2.5. Impact of Scaling the Unity-Gain Frequency .............................110
6.2.6. Trade-Off of Circuit Area and Power Consumption...................111
6.2.7. Design Example Summary..........................................................113
VII. CONCLUSIONS .........................................................................................117

7.1. Summary .........................................................................................117
7.2. Future work .....................................................................................118
REFERENCES ....................................................................................................119
viii
ABBRIVATIONS
AI artificial intelligence
AMD advanced micro devices
AMS austrian micro systems
BiCMOS bipolar complementary metal-oxide semiconductor
CAD computer aided design
CMOS complementary metal-oxide semiconductor
CMR common-mode range
CMRR common-mode rejection ratio
CPU central processing unit
GA genetic algorithms
GP geometrical programming
GUI graphical user interface
IP intellectual property
KCL Kirchhoff’s current law
MNA modified nodal analysis
OR output range
OTA operational transconductance amplifier
Pcell parametrized cell
PSRR power supply rejection ratio
RF radio frequency
SA simulated annealing
SC switched capacitor
ix
SNR signal-to-noise-ratio
SNDR signal-to-noise-plus-distortion-ratio
SFDR spurious-free dynamic range
SoC system-on-chip
SQP sequential quadratic programming
TCP/IP Transfer Control Protocol/Internet Protocol
THD total harmonic distortion
UGBW unity-gain bandwidth
VHDL very high speed integrated circuits hardware description lan-
guage
x
CHAPTER I
INTRODUCTION
In the last few decades we have experienced a revolution in the field of electron-
ics. Going from one single transistor to multi million transistor circuits have pro-
vided us with the functionality that past generations could only dream of. The
level of integration will continue to increase and the buzzword of today is “ Sys-
tem-on-chip” (SoC).
With the rising level of integration the complexity of integrated circuits
increases. More and more functionality can be added as new process technolo-
gies evolves. With the increasing complexity the use of CAD tools that supports
design on a hierarchy of abstractions becomes more important. For digital circuit
design there exist a large variety of tools and design methodologies that effi-
ciently supports designs using several levels of abstraction. This is required in
order to keep in phase with the new capabilities offered by technology.
For analog circuit design the situation is different. The level of abstraction is still
kept at very low levels and there are not that many CAD tools available. The lack
of a structured design flow is one of the major problems in analog circuit design.
This becomes obvious when analog and digital circuits are put on the same chip,
as in mixed-signal SoCs. In general, the digital parts account for about 90% of an
integrated circuit while only 10% is analog. However, most of the time and effort
are spent on the analog parts [62].
1
Introduction
In this work we address the shortcomings of the analog design methodology

used today. Our approach is based upon a set of tools for automating parts of the
design flow in order to increase the efficiency of analog circuit design.
1.1 Analog Integrated Circuits

Even though the trend is to replace analog circuits with digital wherever possible
there are still some functions where analog parts can not be avoided. The most
obvious are the communication with the “ real” world outside the chip. Since the
world consists of analog signals we must be able to interpret and convert these
signals to something that can be fed as an input signal to a circuit. We may for
example use a microphone to pick up variations in the air-pressure, a sensor to
measure the intensity of light, or an antenna to transmit and receive radio fre-
quency signals.
Some of the most important applications of analog circuits is to bridge the gap
between the “ real” world and the digital domain. The need to go from analog to
digital processing have made the use of analog-to-digital and digital-to-analog
converters indispensable. Requirements of high-speed communications have
made these circuits some of the most critical components in mixed-signal chips.
Filters are other important components in such applications. Antialiasing filters
are required whenever we sample an analog signal, thus an analog filter is neces-
sary in, e.g., all communication systems. Analog filters may also be found in,
e.g., hard disc drives where they perform antialiasing and equalizing of the sig-
nals read from the disc.
Another important application of analog circuits are in radio frequency (RF) cir-
cuits. Here analog circuits are operating at frequencies in the range of several
GHz in order to realize the functions required in modern wireless communica-
tion systems.
Yet another important class of analog circuits are the reference circuits required
to, e.g., provide the above circuits with stable biasing conditions. These circuits
may also be important part of otherwise pure digital chips by providing clock
generation and clock drivers.
In all of the above analog circuits, amplifiers are one of the most important
building blocks.
It is thus clear that analog circuit integration are important and necessary in a
large range of applications. This is especially true when considering SoCs where
the link between the analog and the digital domain will be required in practically
every circuit. The graph in Fig. 1.1 shows a prediction of the percentage of all
SoC circuits that will contain both analog and digital parts. To conclude, analog
2
The Analog Design Flow
90
80
70
Mixed−signal circuits [%]
60
50
40
30
20
10
1998 1999 2000 2001 2002 2003 2004 2005 2006

Year
Figure 1.1 Number of SoCs that will contain both analog and digital parts. The graph is
based on predictions from the IBS Corporation [29].
circuits are, and will remain, an important component in many integrated cir-
cuits.
1.2 The Analog Design Flow

A simplified view of an analog design flow is shown in Fig. 1.2. The starting
point is an idea of the functionality to implement.
The function is mapped onto an architectural description. In this process the
functionality is decomposed into a set of high-level building blocks. The decom-
position is continued until the functional block can be mapped onto a set of
lower-level analog building blocks. The simulations done at this level are typi-
cally carried out using high-level models in order to validate the functionality of
the concept. From these simulations, the specification on the low-level blocks
are extracted.
The performance specification contains requirements on the various perfor-
mance metric of the circuit. Here the performance metric are measures of proper-
ties that are used to characterize the behavior of a cell. For example an amplifier
must have at least a specific unity-gain frequency in order for a filter to work
properly.
3
Introduction
Analog
Function
Architectural Simulation
Design &
validation
Simulation
Cell Design &
validation
Simulation
Cell Layout &
validation
Ba
ck Simulation
tra System
ck &
ing Assembly
an validation
dr
ed
esi
gn
Fabrication
Figure 1.2 The analog design flow [48].
In the next step these cells are realized by designing the low-level building
blocks that comply with the previously derived performance specification. The
cell design step include choosing between several possible realizations in order
to implement the functionality in the most efficient way.
During the layout phase the geometries for the functional blocks is determined.
Finally the building blocks are assembled to implement the desired functionality.
Throughout the design process excessive simulations and validation steps are
required. If the circuit fail to meet the specification at some level the proceeding
design steps must be revised. This may include backtracking several steps in the
design process.
In this work we concentrate on cell design and cell layout. In the next section the
aspects of the traditional, manual methodology, concerning these parts is dis-
cussed in more detail
1.2.1 The Manual Design Methodology

In Fig. 1.3 a flow graph for traditional manual cell-level analog circuit design is
shown. The circuit specification puts lower and/or upper limits on some perfor-
mance metrics while other may be less precisely specified.
4
The Analog Design Flow
Circuit specification
Circuit topology selection
Device sizing
Iterations
Iterations
Simulation
Performance evaluation
Iterations
Circuit layout
Iterations
Extraction and simulation
Circuit
Figure 1.3 Flow graph of the cell-level manual analog circuit design.
Topology section
Based on these requirements the designer have to choose a suitable circuit topol-
ogy that is able to meet the specification. Usually there exists several topologies
that implements a particular functionality.
In order to select the best topology for a specific task the designer must rely on
his or hers knowledge in order to select the candidate with the best prospect of
finally meeting the specification. Even though the number of possible candidates
could be reduced by qualitative reasoning there would still be several promising
topologies left. The designer have to decide upon one of them based on experi-
ence, simple hand calculations and rules of thumb.
Also, the designers choice may be influenced by other aspects than the actual
performance of the circuit. If time limits are tight, properties such as the circuit
complexity, how familiar the designer is with the topology, and so on, may be
given some consideration even though it may not favour a good outcome of the
design process.
5
Introduction
Device Sizing
In the component sizing step, the size of all transistors, resistors, capacitors, and
biasing voltages and currents are determined. These parameters are referred to as
the design parameters. Determining the values of the design parameters is a com-
plicated task since the relation between the parameters and the resulting perfor-
mance is a nonlinear function.
To get the approximative sizes of the components simplified hand-calculation
models may be used. The formulas are usually based on simple approximations
of the transistor characteristics that may differ significantly from the real
devices. The designers previous experience with analog circuit design may give
additional directions on what choices to make. Rules of thumb are also com-
monly used in order to reduce the large design space.
In order to evaluate the performance of the initial sizing of the devices a circuit
simulator, such as HSPICE [28] or Spectre [9], is used. A test bench is cre-
ated where a set of suitable input signals are applied to the circuit in order to
extract the performance metrics of interest. Most certainly the performance spec-
ification is not met at the beginning, and, thus, the device sizes must be adjusted.
The tools available to aid the designer when adjusting the design parameters are
not efficient. Many circuit simulator offers the ability to sweep the value of the
design parameters and determine their impact on the overall performance.
Sweeping a large number of design parameters are, however, costly in terms of
computational time. Thus, the search is, in practice, limited in the number of
design parameters that can be swept.
Some simulators, e.g., Spectre, offers a simple form of performance optimiza-
tion. Typically a few design parameters may be adjusted using optimization in
order to fine-tune a set of performance metrics. However, in practice these opti-
mization routines are only capable of handling a small number of design param-
eters. It also requires a good initial starting point. Thus, only minor
improvements are achieved. The time required to perform the optimization task
is also long, since the circuit simulator must be called repeatedly.
If no feasible solution is found after performing several iterations with parameter
adjustment and simulation the design process have failed and the designer have
to go back and select a different circuit topology. Thus, it is, important that a
suitable topology is chosen at the beginning of the design process. In a worst
case scenario the specification for a particular cell have been set to tight, if this
occurs the overall performance specification must be revisited.
6
Challenges in Analog Design
Layout Generation
Layout generation is a time consuming part in analog design. In the layout phase,
the device sizes from the previous design step are mapped onto a physical imple-
mentation.
The tools available at this level are, traditionally, basic module generators, tools
for checking deign rules, and the correctness of the interconnect. Even though
the situation is slightly better than for the device sizing step the task of generat-
ing a full-custom layout for a cell is a difficult task. While the goal, in most
cases, is to make the design as dense as possible other aspects such as the impact
of parasitic effects on the final circuit performance, matching conditions, and
yield degradation are also important.
In order to determine the layout-induced performance-shift an extraction tool is
used. Given the geometries of the layout, the tool extract the interconnect para-
sitics of the circuit. In order to meet the performance specification the designer
have to consider the degrading effect of the layout phase during the previous
step. Thus, some extra design margins have to be added.
If the margin is made to small, changes in the layout as well as resizing of the
devices might have to be performed. Such tasks are, of course, time consuming
and even a small change in the size of some devices might require large changes
in the layout. On the other hand, if the design margin is made to large, the pen-
alty will be, e.g., increased power consumption and larger chip area.
1.3 Challenges in Analog Design

The traditional analog design flow suffers from several problems. In this section
some of these issues will be discussed in more detail.
One of the most important aspects are the time spent on designing the low-level
cells. The time required to design an amplifier might be in the order of weeks
[24, 58] when all design steps are considered. Since a large amount of all chips
contains both analog and digital components this poses a severe bottleneck due
to the gap between analog and digital design efficiency. Decreasing the time
spent on the design of analog parts in a chip will have a large impact on the time-
to-market for the whole chip.
Another important aspect is the circuit performance. A circuit specification may
contain requirements on tens of different performance metric. When sizing a cir-
cuit manually the designer have to understand how these performance metric are
effected by changes in the design parameters. Even if all relations are known it is
still hard for the human mind to keep track of the changes that a certain adjust-
ment will cause. In a worst-case scenario the designer will, e.g., adjust the width
7
Introduction
of the transistors in order to meet the requirement on bandwidth, however, while

doing this the requirement on distortion is violated. It is clear that with an
increasing number of effects and performance metrics taken into account the
problem becomes difficult for a designer to comprehend.
Depending on the application some of the performance metric will not effect the
actual function of the circuit. Two examples of such properties are the power
consumption and the total area used by the circuit. Two amplifiers with different
power consumption may have similar operation characteristics. In for example a
mobile application it is therefore important to find the amplifier with the lowest
power consumption while still meeting the specification. Since each iteration in
Fig. 1.3 is costly, the number of circuits that can be examined in order to mini-
mize the power consumption is limited.
As illustrated in Fig. 1.4 we assume that there are a restricted parameter space in
which the device sizes can be chosen. With repeated iterations in which the
device sizes are adjusted to meet the specification different points in the design
space is visited. Continuing the process some part of the space where the perfor-
mance specification is met can be found. Further, by exploring the feasible
design space, e.g., the power consumption could be minimized.
Specification met
Minimum power consumption

Parameter space
Figure 1.4 The design parameter space.
However, since the performance metric are nonlinear functions of the design
parameters the chance of finding the global, or even a local minima is small. Fur-
thermore, due to the time involved, only a small fraction of the design space may
be explored using manual design.
8
Challenges in Analog Design
In order to fully explore the potential of the process technology several circuit
topologies might have to be investigated. Due to the cost of designing several
candidate circuits this is often overlooked.
Yield is an important factor when considering the cost of the chip. Usually, man-
ual design is carried out using nominal process parameters. When the device
sizes have been determined the design is simulated using worst-case process
parameters in order to measure the effect of process variations. The worst-case
design parameters are derived by the process vendor in order to simulate process
corners. Also, Monte Carlo simulations, where design and process parameters
are varied according to a statistical distributions, are used for this purpose.
These methods provides a way of predicting the circuit yield. However, the
Monte Carlo simulations are time consuming. Also when a simulation fails there
are no way of identifying what design parameters is causing the failure. The use
of multiple sets of worst-case parameters will produce a large number of simula-
tion results to take into account, further complicating the design process. conse-
quently these approaches are only used at the end of the design procedure to
validate the performance. The actual device sizing is carried out using nominal
process parameters. Adjustments to the design parameters are usually required in
order for the circuit to work under several sets of worst-case parameters.
During the layout phase many effects that will increase the yield and ensure good
circuit behavior must be taken under consideration. The number of constraints
on an analog layout can be huge and it is hard for a human designer to keep them
in mind and make the appropriate choices. Also, the number of layout solutions
that can be tried out is limited by the time consuming task of producing them.
When migrating from one process technology to the next, the process parameters
determining the performance of the circuit are changed. Also, layout rules, such
as minimum spacing rules and so on, change. This usually require a complete
redesign of the circuit, both with respect to the sizing and the layout. Thus, the
level of reuse of analog circuits is low.
To conclude the following drawbacks of the manual design methodology are
identified:
z Time consuming and therefore costly.
z Insufficient exploration of available design space, i.e., low utilization of
existing process technology.
z Hard to reuse previous designs.
z High risk of errors being introduced.
z Yield is not taken into account during the design process.
9
Introduction
1.4 Motivation
It is clear from the previous section that the manual analog design flow suffers
from serious problems. The situation becomes more critical when entering the
era of SoC. Due to the high level of automation and abstraction, digital design
manage to keep in phase with the rapid change in process technology and the
increasing demands on a short time-to-market. For analog design the situation is
completely different, since the level of automation is low.
The main tool used by analog designers today is the circuit simulator. Apart from
this and a few surrounding tools such as layout editors and validation utilities the
design process involves little automation. Thus, the analog design process of
today is based on manual efforts.
There are numerous reasons for this situation. The high level of automation in
digital design may partly depend on the fact that the digital design flow is con-
sidered more suited for automation. For example, a digital functionality can be
represented by Boolean expression and programing languages such as VHDL.
Further, in order to implement a logical function we require only a few logical
building blocks. Thus standard cell libraries containing only a limited number of
blocks can cover a large portion of the functionality in digital circuitry.
In analog design the number of performance specifications to take into account is
higher. Thus, the approach with standard cells is not feasible. Making libraries
with analog standard cells would require an enormous number of cells in order to
cover the range of specifications appearing in analog design.
One reason for the shortcomings of analog design automation tools is the lack of
a structured design flow. Despite the systematic flow shown in Fig. 1.2 the pro-
cess of analog design involves taking all design steps into account concurrently.
For example, the designer must consider layout effects when choosing the topol-
ogy. This is due to that a decision taken at one level of the design flow will effect
the design on several other levels. This complicated design flow have led to that
there have been little success in quantifying the work of an experienced designer.
Also, the complicated relations between the design parameters and the resulting
performance in analog design poses a challenging task.
Yet another important factor is that the market for digital circuits is much larger
than for analog circuits. Thus, the interests in the research areas involved with
analog design automation have been lower than for the digital counterpart. How-
ever, with the recent interest in mixed-signal chips this ought to change.
10
Scope of this Thesis
1.4.1 Goals in Analog Design Automation

Analog design automation can provide solutions to some of, or reduce, the prob-
lems in analog circuit design. The main goals of analog design automation are:
z Decrease the design time: The time required to complete the manual design
flow is long. Thus decreasing the time spent on designing analog circuits is
crucial in mixed-signal chips where the analog design must keep in phase
with the highly automated digital counterpart. This in turn will lead to
decreased time-to-market and improve productivity.
z Reduced cost: Reducing the time spent on designing analog circuits will
have a positive effect on the cost of a chip. Generally the design task is
demanding when human resources are considered. Thus, automating the
design task will reduce the number of man hours spent on cell-level synthesis
tasks.
z Increased performance: In traditional analog design only a small fraction of
the available design space is explored during synthesis. Exploring a large part
of the design space requires a large number of iterations and extensive circuit
simulation. Analog design automation strive to examine a larger portion of
the available design space. Thus, finding at least as good solutions as in man-
ual design.
z Independent of process technology: Increasing the level of reuse in analog
circuit design is an important issue. In manual design methods migrating
from one process technology to the next often requires a complete redesign of
the circuit. An analog design tool should be able to perform its task on a large
range of process technologies.
z Increase yield: Beside being a tedious task the design of analog integrated
circuits are also error-prone. A highly automated design flow will reduce the
risk of introducing errors. Also, yield may be incorporated as an additional
performance metric during the design.
1.5 Scope of this Thesis

In this thesis ongoing work is presented. The focus is on creating a design plat-
form for analog amplifiers. However, the approach is general enough to be
extended to include other types of circuits as well. Our long-term goal is to auto-
mate large parts of the analog cell design, and possibly design larger structures
such as complete analog filters.
Even though the whole design flow is part of the problem addressed in this thesis
the focus is on automating the devices sizing. The device sizing tool is able to
determine the nominal set of device sizes for an analog amplifier circuit in order
to meet the performance specifications. Other important parts of the design flow,
11
Introduction
such as layout generation are also addressed. These tools are, however, in their
infancy and much work still remains.
The work have been carried out in close collaboration with Robert Hägglund
who is also working in the same research project. Most of the progress within the
project have been the result of joint efforts.
In this thesis the emphasis, beside the design tool in general, are on layout gener-
ation with parasitic feedback and the exploration of trade-offs within analog
design. However, some important parts of the device sizing tool, such as the gen-
eration of symbolic expressions required to compute noise and distortion are dis-
cussed in more detail by Robert Hägglund.
The outline of the work is as follows. In chapter 2 an overview of performance
metrics and design issues in analog amplifier design is given. Chapter 3 dis-
cusses the current state of analog design automation. The emphasis in this chap-
ter are on automated device sizing and several existing tools are reviewed. In
chapter 4 our proposed design platform is discussed. A more detailed description
of the device sizing tool is also given. The layout generation and parasitic feed-
back tools are discussed in chapter 5 together with a design example. Chapter 6
introduces the design space exploration tool used to identify trade-offs in analog
amplifier design. An example, involving the comparison of three different ampli-
fier structures, is given.
1.6 Publications Related to this Thesis

The publications related to this thesis are listed below. In [9] and [10] the first
version of the design tool is described. Layout aspects of integrated capacitors,
partly used in this work are discussed in [8]. The current version of the tool is
described in [3, 4, 6, 7]. In [3, 4] the method of parasitic feedback is presented.
Design space exploration and trade-offs are treated in [1, 2, 5].
[1] E. Hjalmarson, R. Hägglund, and L. Wanhammar, “Design Space Explo-

ration and Trade-Offs in Analog Amplifier Design,” Proc. Int. Workshop
Power Timing Modeling, Optimization Simulation (PATMOS), pp. 338-
347, Torino, Italy, Sept. 10-12, 2003.
[2] E. Hjalmarson, R. Hägglund, and L. Wanhammar, “Optimization-Based

Design Space Exploration of Analog Circuits,” Proc. European Confer-
ence on Circuit Theory Design, pp. 393-396, Krakow, Poland, Sept. 1-4,
2003.
12
Publications Related to this Thesis
[3] E. Hjalmarson, R. Hägglund, and Lars Wanhammar, “An Optimization-

Based Approach for Analog Circuit Design,” Proc. European Confer-
ence on Circuit Theory Design, pp. 369-372, Krakow, Poland, Sept. 1-4,
2003.
[4] E. Hjalmarson, R. Hägglund, and L. Wanhammar, “An Equation-Based

Optimization Approach for Analog Circuit Design,” Proc. Int. Symp. on
Signals, Circuits Systems, pp. 77-80, Iasi, Romania, July 10-11, 2003.
[5] R. Hägglund, E. Hjalmarson, and L. Wanhammar, “Using Optimization

to Find Design Trade-Offs in Analog Amplifier Design,” Proc. Swedish
System-on-Chip Conf., Eskilstuna, Sweden, Apr. 8-9, 2003.
[6] E. Hjalmarson, R. Hägglund, and L. Wanhammar, “A Design Platform

for Computer-Aided Design of Analog Amplifiers,” Proc. Swedish Sys-
tem-on-Chip Conf., Eskilstuna, Sweden, Apr. 8-9, 2003.
[7] R. Hägglund, E. Hjalmarson, and L. Wanhammar, “A Design Path for

Optimization-Based Analog Circuit Design,” in Proc. IEEE Midwest
Symp. Circuits Syst., pp. 287-290, Tulsa, OK, USA, Aug. 4-7, 2002.
[8] E. Hjalmarson, R. Hägglund, P. Löwenborg, and L. Wanhammar, “Auto-

matic layout Generation of Matched Capacitors,” Proc. National Conf.
Radio Science (RVK), pp. 182-186, Stockholm, Sweden, June 2002.
[9] R. Hägglund, E. Hjalmarson, and L. Wanhammar, “Automatic Device

Sizing in Analog Circuit Design,” Proc. National Conf. Radio Science
(RVK), pp. 187-191, Stockholm, Sweden, June 10-13, 2002.
[10] R. Hägglund, E. Hjalmarson, and L. Wanhammar, “Optimization-Based

Device Sizing in Analog Circuit Design,” Proc. Swedish System-on-Chip
Conf., Falkenberg, Sweden, Mar. 18-19, 2002.
13
Introduction
14
CHAPTER II
PERFORMANCE METRICS AND DESIGN ISSUES
FOR ANALOG AMPLIFIERS
In this chapter the basics of analog circuit design are discussed. The fundamental
small-signal models and hand-calculation formulas are presented. Also, some
important performance metrics in analog design are discussed. The performance
metrics of interest depends on the circuit, in this case we focus on analog
amplifiers. However, some of these measures are commonly used in other ana-
log circuits as well. At the end of the chapter analog layout is briefly discussed.
Some of the common techniques used to improve the performance during this
phase are also presented.
2.1 The Process Technology

Today there exist several process technologies for realizing integrated circuits.
The most popular of these is the complementary metal-oxide semiconductor
(CMOS). CMOS is the dominating process technology for digital integrated cir-
cuits today.
In the CMOS process both n-channel (NMOS) and p-channel (PMOS) MOS-
FETs are used to realize the logical functions. Since the PMOS transistor is “on”
when a low voltage level (zero) is applied to the gate, and the NMOS transistor is
“on” when the gate potential is high (one) these devices can be used to form
complementary circuits where the static power consumption is small. The area
required to implement a specific function is also small, i.e., the amount of func-
tionality that can be implemented on a chip is large.
15
Performance Metrics and Design Issues for Analog Amplifiers
The low power consumption and the fact that the manufacturing cost of CMOS
circuits is low compared to, e.g., bipolar circuits, has made CMOS the most pop-
ular process technology for digital circuits.
Even though the bipolar transistors can work at higher frequencies, the proper-
ties discussed above and the fact that analog and digital circuits are used on the
same chip have made the CMOS process important for analog design as well.
Special processes, such as BiCMOS, combine the bipolar technology with the
CMOS technology. In this way the designer can use bipolar devices for perfor-
mance-critical analog parts and CMOS for digital parts on the same chip.
However, in this work the process technology considered is standard CMOS.
Since our target is analog amplifiers working at baseband frequencies this pro-
cess technology is sufficient in most cases.
2.1.1 The CMOS Devices

In this section, a simple model for the CMOS transistor is discussed. Even
though this model do not predict the behavior of the sub-micron transistor accu-
rately, the relations are still valuable to understand the relationship between dif-
ferent properties of the devices. Also, some of the concepts presented here are
used in more accurate models as well.
The equations presented are those normally used when performing hand calcula-
tions. They are also an integral part of the manual device sizing approach.
Large-Signal Model
The symbols of the NMOS and PMOS transistors are shown in Fig. 2.1. These
symbols are the four-terminal version of the transistor. In this simple model the
transistors are assumed to have three operating regions. Here the equations for
the NMOS transistor are given. However, the corresponding relations and equa-
tions for the PMOS transistor are similar. For the NMOS transistor the cut-off,
linear, and saturated regions are defined by the following relations
cut-off VDS < V GS – V TH (2.1)
linear V DS ≤ V GS – V TH and VGS > V TH (2.2)
saturated V DS ≥ V GS – V TH and V GS > V TH (2.3)
Here VTH, the threshold voltage, is the minimum gate to channel voltage
required in order to create a conducting channel between the drain and source in
the transistor. The threshold voltage is modelled by
V TH = V TH0 + γ ( 2φ F – V BS – 2φ F ) (2.4)
16
The Process Technology
VD VS
+ + + +
ID
VSG VSB
VB - - VB
VG VDS VG VSD
+ +
VBS
VGS - ID -
- -
VS VD
(a) (b)
Figure 2.1 Voltage and current definitions for four-terminal NMOS (a) and PMOS (b)
transistors.
where VTH0 is the threshold voltage when VBS is zero. The additional terms are
results of the body-effect. The body-effect is an increase in the threshold voltage
due to the voltage difference between the substrate (bulk) and the source of the
transistor. In (2.4) φ F is the difference between the Fermi potential at the gate
and the Fermi potential at the substrate. γ is the body-constant determined by the
process parameters.
Depending on the operating region the current through the transistor, ID, is given
by
cut-off I D ≈ 0 (2.5)
V2
linear I D = µ n Cox -----  ( VGS – V TH )VDS – ---------
DS 
W
 (2.6)
L 2
µ C
n ox W
- ----- ( V GS – V TH ) 2 [ 1 + λV DS ]
saturated I D = -------------- (2.7)
2 L
where µn is the mobility of electrons near the silicon surface for the NMOS tran-
sistor, Cox is the gate capacitance per unit area, λ is the output impedance con-
stant, and W and L are the width and channel length of the transistor.
In analog amplifiers the transistors are usually biased to work in the saturated
region. The reason for this is that when a transistor operates in that region the
current is controlled mainly by the gate-source voltage. However, as stated in
(2.7) the nonzero λ will introduce an unwanted dependency on the drain-source
voltage as well.
The concept, used in high accuracy models such as BSIM3v3 [36, 10], EKV [14]
or Phillips MOS level 9 [64], is similar to the simplified models shown here.
17
However, the expressions for computing, e.g., the drain current of the transistor
include many more effects. Thus, the expressions used within these models are
not suited for hand calculations.
Small-Signal Model
For large signal variations the large-signal model can be used to calculate the
behavior of the circuit. However, if only small signal variations are considered
the nonlinear large-signal model can be linearized. The small-signal model is a
linearization of the large-signal model around the operating point of the circuit.
This model is only valid for small perturbations from the operating point. The
models can be used in order to simplify the calculation of, e.g., the frequency
dependent properties of the circuit.
Gate Drain
g m V gs g ds g mbs V bs
Source
Figure 2.2 Simple small-signal model of a MOS transistor.
A simple small-signal model for the NMOS transistor is shown in Fig. 2.2. Here
gm is the transconductance and gds is the output conductance. The small-signal
parameters are derived using the following expressions:
∂I D 1 W
- = --- µ n C ox ----- ( V GS – V TH ) 2 λ
g ds = ----------- (2.8)
∂V DS 2 L
∂I D W
- = µ n C ox ----- ( VGS – V TH )
g m = ----------- (2.9)
∂V GS L
∂I D ∂V TH γ
g mbs = ------------ ------------ = g m -------------------------------- = ηgm (2.10)
∂V BS ∂V BS 2 2φ F + V BS
As in the case with the large-signal model more accurate small-signal transistor
models take into account several additional parameters. The small-signal model
used within the BSIM3v3 model will be presented in Sec. 4.7.
18
Performance Metrics in Amplifier Design
2.2 Performance Metrics in Amplifier Design

There are several important performance metrics that must be taken into account
when designing an analog amplifier. The importance of these metrics are of
course highly dependent on what application of the amplifier is intended to be
used in. In this section some commonly used performance metrics for analog
amplifiers are discussed. Depending on the application of the amplifier, other
performance metrics might also be of interest. The purpose of this section is not
to give a full coverage of all existing performance metrics in analog circuit
design, but to introduce and explain some of the concepts used later on.
For some of the performance metrics discussed, there exist alternative defini-
tions. Thus, stating the definitions used in this work is important.
The general amplifier transfer function is
A 0  1 + ---- s  …  1 + ---- s
z1   z n
A ( s ) = ----------------------------------------------------
- (2.11)
 1 + ---- s- …  1 + ----- s-
 p   p 
1 m
Here z denotes a zero and p denotes a pole. A0 is the DC gain, i.e., the gain when
s is equal to zero.
Further, the output signal of a differential amplifier can be written as
Vp ( s ) + Vp ( s )
V out ( s ) = A CM ( s ) --------------------------------- + A DM ( s ) [ V p ( s ) – V n ( s ) ] (2.12)
2
where ACM(s) is the common mode gain and ADM(s) is the differential gain.
Vp(s) is the positive input signal while Vn(s) is the negative input signal.
Bandwidth and Unity-Gain Frequency

In Fig. 2.3 the magnitude and phase response of an amplifier with two-poles are
shown. The bandwidth of an amplifier is defined as the frequency band for
which the amplitude is within 3dB of its maximum value. The bandwidth for the
amplifier in Fig. 2.3 is about 100 rad/s.
Another performance metric is the unity-gain bandwidth (UGBW). The UGBW
is defined as the frequency range for which the amplifier has a gain that is at
least equal to unity.
Further, at the unity-gain frequency, ωu, the amplification of the input signal is
equal to unity, i.e., above this frequency the input signal is no longer amplified.
The unity-gain frequency is defined as
A ( jω u ) = 1 (2.13)
19
A0 80
60
Magnitude [dB]
40
20
0
−20
−40
−60
−80
0 1 2 3 4 5 6 7 8
10 10 10 10 10 10 10 10 10
Frequency [rad/s] ωu
0
Phase [degrees]
−45
−90
−135 ϕm
−180
0 1 2 3 4 5 6 7 8
10 10 10 10 10 10 10 10 10
Frequency [rad/s]
Figure 2.3 Magnitude and phase response of an amplifier.
Phase Margin
The phase margin,ϕm, is defined as
ϕ m = arg ( βA ( jω u ) ) – ( – π ) (2.14)
here β is the feedback factor in a closed-loop amplifier configuration. The phase
margin is a stability measure for the amplifier.
Positive and Negative Power Supply Rejection Ratio

The power supply rejection ratio (PSRR) measures the amplifiers ability to sup-
press variations in the power supply voltages. In the ideal case, a change in sup-
ply voltage will not effect the performance of the amplifier. However, in reality,
changing the power supply voltage will affect the bias levels and thereby the
operation of the circuit. If large variations in the power supply voltage is present
due to, e.g., high switching activity in surrounding digital circuitry, it is impor-
tant that these variations have small impact of the performance of the amplifier.
Both positive PSRR, i.e., the suppressions of variation in the positive power sup-
ply voltage, and negative PSRR, i.e., the suppression of variations in the nega-
tive power supply voltage are of interest. The definitions are
20
A DM ( jω )
PSRRp ( jω ) = 20 log  ------------------------- (2.15)
A VDD ( jω )
A DM ( jω )
PSRRn ( jω ) = 20 log  ----------------------- (2.16)
 A VSS ( jω )
where AVDD is the magnitude of the frequency response from the positive power
supply to the output terminal and AVSS is the magnitude of the frequency
response from the negative power supply to the output terminal.
Common Mode Rejection Ratio

The common mode rejection ratio (CMRR) is a measure of how unwanted com-
mon mode signals on the amplifier input terminal are suppressed. In
A DM ( jω )
CMRR ( jω ) = 20 log  ---------------------- (2.17)
A CM ( jω )
the gain of the common-mode signal is compared to gain of the differential sig-
nal. In the ideal case the CMRR is infinitely large, i.e., the common-mode signal
is not amplified of at all.
Slew Rate
The slew rate is defined as the maximum slope at an amplifiers output.
dV out
SR = max ------------- (2.18)
dt
It is measured by applying a large step to the input terminal and measure the
slope at the output terminal. When slew-rate limitation occurs the amplifier will
not act as a linear system. For example, if a large step is applied on the amplifiers
input terminal, the output signal is a linear ramp with a constant slope (the SR).
Distortion
When, e.g., a sinusoidal signal is used as the input to an amplifier the output sig-
nal, in the ideal case, is a linear amplification of that signal. However, in reality
this is not the case. Instead the shape of the output signal deviates from that at its
input. This is due to that nonlinearities in the amplifier distort the signal.
There are several types of nonlinearities in analog amplifiers. First of all, the cir-
cuit elements, i.e., transistors, capacitors, and resistors are nonlinear elements.
Secondly, other effects such as slew rate limitation causes nonlinear behavior.
Distortion appears as unwanted frequency components at the circuits output.
One way of measuring the harmonic distortion, i.e., the effect of higher-order
harmonics, is by measuring the total harmonic distortion (THD). THD, relates
21
output power level
SFDR
3dB
Fundamental
2nd 3rd
harmonic harmonic
Noise floor
input
IIP2 IIP3 power
level
Figure 2.4 Intercept points and spurious-free dynamic range.
the fundamental and the higher order harmonics. It is calculated by summing the
higher order harmonics and comparing them to the fundamental according to
∞
∑ Pn
n=2
THD = 10 log ----------------------------
- (2.19)
P fundamental
where Pn is the power of the nth harmonic while Pfundamental is the power of the
fundamental.
Other performance metrics for linearity are harmonic distortion, compression
and intercept points, and inter modulation distortion [67]. The concept of inter-
cept points is illustrated in the Fig. 2.4.
The intercept points are computed by extrapolating the curves of the fundamen-
tal, second and third harmonic according to Fig. 2.4. Since the second harmonic
increases quadratically, it will intersect with the fundamental at some point, IIP2.
The higher the interception is located, the better is the suppression of the har-
22
monic. IIP3 is calculated in a similar manner. It is also possible to compute

higher-order distortion terms in this way.
Noise
In MOSFETs there are mainly two types of noise sources, thermal and flicker
noise (1/f noise) [31]. Thermal noise arise in resistors and is the result of random
motions of electrons due to thermal effects. Flicker noise is believed to be the
result of charges being “trapped” in the device for various reasons and later
released. Unlike thermal noise flicker noise is frequency dependent and
decreases inversely with the frequency.
The noise spectral density at the circuit output is computed by summarizing the
contribution of all independent noise sources in the circuit according to
N
S out ( ω ) = ∑ Sn Hn ( ω ) 2 (2.20)
n=1
Here N is the number of noise sources, Si is the spectral density of the noise
source, and Hn is the magnitude response from the noise source to the output of
the circuit. By integrating the noise over a frequency band the noise power is
obtained.
A common performance metric for noise is the signal-to-noise-ratio (SNR)
defined by
P signal
SNR = 10 log  ---------------- (2.21)
P noise
where the Psignal is the signal power and Pnoise is the noise power. It is defined
for a specific frequency range over which the corresponding signal and noise
power is integrated.
Other measures include the combined effect of noise and distortion. The signal-
to-noise plus distortion ratio, SNDR, measures the degradation due to the com-
bined effect of noise and distortion within a frequency band. The SNDR is
defined as the ratio of the signal power of the fundamental to the sum of the
power of all of the harmonic, all of the aliased harmonics, and all of the noise.
P signal
SNDR = 10 log ------------------------------------
∞
- (2.22)
Pnoise + ∑ Pn
n=2
Another metric, indicated in Fig. 2.4, is the spurious-free dynamic range, SFDR.
SFDR is defined as the dynamic range where the signal is (fairly) unaffected by
23
noise and distortion in a specific frequency band. While the noise floor sets a
lower limit on the signal power the distortion implies an upper limit.
Common-Mode Range and Output Range

The common-mode range (CMR) is defined as the range of the common-mode
level at which the circuit responds properly to differential input signals. In order
to determine the CMR, an acceptable level of distortion at the circuit output may
be defined.
The output range (OR) is defined as the range in which the output signal can
vary, given that the distortion must be lower than some threshold value.
Settling time
The settling time denotes the time required for the output signal of an amplifier
to adjust when a step is applied to the input. Depending on the magnitude of the
step, the settling can be linear or nonlinear. For a small step, only the bandwidth
of the amplifier limits the settling time. In this case the settling is linear. The lin-
ear settling determines an overall upper limit of the settling time. However, when
a large step is applied to the input terminal, the amplifier experience slew rate
limitation due to the finite current that can be supplied to the capacitive nodes. In
this case the settling is nonlinear.
The settling is computed by applying a step to the amplifiers input terminal and
measure the time until the output signal is within a certain range of its final value
as shown in Fig. 2.5. The exact range may vary depending on the application of
the amplifier.
Circuit Area, Power Consumption, and Yield

Some performance metrics do not directly affect the functionality of the circuit
but are of interest since they are associated with its cost. A typical example of
such performance metrics is the silicon area occupied by the circuit. The area of
the chip directly affects the manufacturing costs and it is therefore of interest to
make the circuit as small as possible.
The power consumption is more important then ever with a large number of
applications nowadays running on battery. The power consumption directly
affect the operation times for such products and is therefore an important perfor-
mance metric.
During the manufacturing process, a certain percentage of all circuits will, due to
various reasons, not operate according to the specification. Yield is defined as
the number of circuits, out of a set, that do operate according to the given speci-
24
Circuit Layout
Vin
Vout
Upper tolerance level
Lower tolerance level
Settling time
Figure 2.5 Measurement of the settling time from the circuit step response.
fications. Maximizing the yield directly effects the cost of manufacturing a chip.
Designing for high yield is therefore important.
Further, the yield is partly depending on the chip area since the number of pro-
cess errors is approximately the same per unit area. Thus, a lower percentage of
the chips will be affected by these errors if each chip is made smaller.
2.3 Circuit Layout

When all device sizes are determined, the design process enters the layout phase.
Producing a full-custom layout of a circuit is a tedious and error-prone task. In
digital circuit design, the layout phase is a highly automated procedure, using a
standard cell library in conjunction with a place and route tool, most circuits can
be realized. Unfortunately the same level of automation is not available in analog
circuit design.
To some extent the concepts used in automated digital layout generation can be
reused in analog layout. Newertheless, the circuit layout is, to a large extent, still
carried out using traditional, manual design methods, where all devices and the
interconnects are placed by hand.
There are several layout-dependent aspects to take into account when drawing
the layout of the circuit. Some of them have been listed here.
25
Interconnect Parasitics
Interconnect parasitics appear due to that the wires not only form a physical con-
nection in the circuit but add unwanted, parasitic, elements such as capacitors,
resistors, and inductors to the circuit. This effect the circuit performance.
The extra load introduced by the interconnect parasitics, may, affect performance
metrics such as the unity-gain frequency and the phase margin. Further, if the
parasitic load is large in comparison to the load at the amplifiers output, the slew
rate may be reduced.
Another problem is the effect of cross coupling created by interconnect parasit-
ics. Cross coupling appears when two wires are placed closely together and a
parasitic connection is created. If one of the wires carries a sensitive analog sig-
nal while the other carries noisy signal, e.g., a clock signal, noise will be intro-
duced in the sensitive signal. An example would be the amplifier input and the
power supply voltage. If these two are heavily coupled, the PSRR will be
reduced.
Process Tolerances
The process tolerances when manufacturing an integrated circuit are large. In the
case of on-chip resistors, chip-to-chip variations of 30% are reported [23]. Other
devices, such as capacitors and transistors, also experience large variations.
In order to cope with large chip-to-chip variations, analog functions tend to
depend on the ratio between two or several components rather than their absolute
value. In, e.g., switched capacitor (SC) filters the frequency characteristics are
determined by the clock frequency and the ratio of capacitance values. Since all
components on the same chip will experience approximately the same process
variations, ratios between components of the same type are preserved.
There are, however, some variations even between devices on the same chip.
These variations are called mismatch and is defined in [50] as “the process that
causes process-induced, time-independent random variations in physical quanti-
ties of identically designed devices”. Keeping the components well matched is
therefor fundamental when designing high-performance circuits.
The reason for mismatch is that the devices experience different process biases,
caused by systematic and random variations during the manufacturing process.
The details of mismatch will not discuss further here. An overview of the process
dependent effects causing mismatch is given in [23].
A set of layout rules to improve matching is reported in [65]. A short summary
of the rules, generally accepted by analog designers, are given here.
26
Circuit Layout
C3 C1 C2 C3
C2 C2 C1 C1 Center of mass
C1 C1 C2 C2
C3 C2 C1 C3
Figure 2.6 Common-centroid placement for a matched capacitor array.
A set of matched components should use the same structure in order for all
matched devices to experience the same process bias. If, for example, two
matched capacitors are implemented as a poly-poly capacitor and a metal-metal
capacitor, the process bias will affect the capacitive value of these components
differently.
Common-centroid placement should be applied to all matched devices in order
to reduce the effect of first-order parameter variations across the chip. The prin-
ciple of common centroid is shown in Fig. 2.6. Here three capacitors are placed
using the common-centroid technique. In order to reduce gradient errors the
capacitors are divided into a set of unit-size elements and placed in such a fash-
ion that their center of mass coincide.
The matched device should experience the same surrounding structures. This is
to avoid various end effects that appear during manufacturing of the chip. For
example in Fig. 2.6 the transistors in the middle of the capacitor array are sur-
rounded by other capacitors in all directions. The capacitors at the edge of the
array will however only have a neighboring capacitor at two or three sides. In
27
order to reduce the impact of edge effects additional dummy elements may be
placed at the edge of the array in order to simulate a neighboring capacitor.
The principle with common-centroid placement and dummy element insertion is
applicable not only to capacitors but widely used for transistors and resistors as
well.
The devices should experience the same temperature shifts. This can be accom-
plished by placing the matched devices so that they are equally influenced by
high-power devices present on the chip.
All devices should have the same shape and size. For example two matched
capacitors should have the same aspect ratio, and matched transistors should
have the same length and width and use the same number of fingers.
The distance between the devices should be minimized in order to reduce the
effect of fluctuations in the physical parameters across the chip. By placing the
components close, the local correlation between these parameters can be
exploited.
All devices should be oriented in the same way in order to reduce the effects of
non-symmetries in the process parameters due to anisotropic process steps.
Especially the source and drain of transistors should be oriented in the same way
in order to facilitate strictly parallel current flows.
To reduce edge effects, minimal sizes for the devices should be avoided. In this
way the relative influence of edge variations are reduced.
Thermal Effects
Due to the miniaturization of integrated circuits the power densities on a chip
might be high in some areas. This is especially true for circuits with, e.g., high-
frequency digital processor cores. High-power densities means high tempera-
tures which will affect the performance of the circuit elements [35].
Temperature gradients on a chip may cause, e.g., the threshold voltage and the
transconductance of a MOS transistor to change. Also, the long term effect with
increasing temperatures on chip is a problem since the failure rate increases with
a factor of two for every 10 ° C rise in temperature [35].
To reduce the temperature dependent errors, sensitive parts must be well sepa-
rated from power intensive circuits. If this is not possible, matched components
must be placed so that they experience a similar shift in temperature.
Substrate Coupling
When analog and digital circuits are integrated on the same chip, the effect of
substrate coupling is a serious problem. The effect appears due to the coupling of
28
Trade-Offs in Analog Amplifier Design
noise from the digital circuits, which can be very noisy, to the noise sensitive
analog parts through the substrate.
Substrate coupling is the effect of limited isolation between analog and digital
circuits on the same chip provided by the substrate. Due to this currents are flow-
ing between the analog and the digital circuits throughout the substrate.
There are two methods commonly used to reduce substrate coupling in analog
layout. The first is to increase the distance between the noise source and the sen-
sitive circuits. This is however only effective if a high impedance substrate is
used. The second method is to use guard rings to isolate the sensitive parts from
the rest of the circuit. More details on substrate coupling may be found in [61].
All of the effects discussed above are hard to take into account during the layout
phase and may, if the design margins from the previous sizing phase are not large
enough, cause the circuit to violate the performance specification. If this occurs
changes must be made to the layout and/or the device sizes. Even small changes
in a compact layout can result in a complete redesign.
2.4 Trade-Offs in Analog Amplifier Design

It is clear that there are numerous performance metrics used for analog circuits.
What makes the design process even more challenging is the nonlinear relation
between them.
In Fig. 2.7 some of these relations, present in analog amplifier design, are illus-
trated. For example, when trying to lower the power supply voltage the voltage
swing is reduced. If the voltage swing is reduced the SNR is decreased and so
on. Thus, determining the relations between the performance metrics is crucial in
analog circuit design. Simple device models can give some information of possi-
ble trade-offs. However, the real value of the performance may not be accurately
predicted until simulated using high-order device models.
29
Noise Linearity
Power Gain
consumption
Input/output Power supply

impedances voltage
Voltage
Speed swings
Figure 2.7 Trade-offs in analog amplifier design.
30
CHAPTER III
COMPUTER AIDED DESIGN OF
ANALOG CIRCUITS
The objective of design automation is to address the drawbacks in manual

design, discussed in Chapter 1. In the manual design flow, there are several pos-
sible iteration loops. All of these iterations include time consuming adjustments
and validation tasks.
The design flow presented in Chapter 1 also shows that the level of automation is
low in analog design today. In comparison with digital design, where the level of
automation is high, the analog design flow is ineffective and unstructured. Some-
times the design of analog circuits are considered to be more of an art. In many
cases the only tools used, besides pure GUI based interfaces for entering circuit
descriptions and layouts, are layout verification utilities and circuit simulators.
There are however alternatives to the manual design flow. In this chapter the
basic principles of such approaches are described. A survey of existing design
tools are also given. Since the focus in this work are on automating the process
of determining the design parameters in analog circuits, methods on how to
accomplish this are discussed in more detail.
3.1 The Automated Design Flow

The typical design flow in an analog design tool at cell level is shown in Fig. 3.1.
In principle the flow is partitioned in the same way as in manual design. The dif-
ferences lays in that the analog design flow relies on a set of tools to solve each
31
Computer Aided Design of Analog Circuits
Performance specification
¤
Topology selection
32/0.7 32/0.7
Sizing and biasing 10/0.7 10/0.7
64/0.7
Layout generation
Figure 3.1 Typical design path for an analog design automation platform.
of the steps in the flow. By automating the design flow the design times of the
manual design methodology can be reduced from weeks to days or even hours
[24, 58].
Most of the design tools available do not cover the complete design process.
Instead they target a specific part of the design flow, such as the topology selec-
tion and device sizing while there are other tools that address the task of generat-
ing a circuit layout.
32
The Automated Design Flow
Also, the tasks are more or less loosely coupled. Most tools do not take into
account, the effect of design decisions taken at different levels in the design flow.
For example, the layout generation tool do not communicate with the device siz-
ing tool in order to get information on, e.g., current densities that could be used
to predict the required width of the wires.
3.1.1 Topology Selection

Here the tool selects the most promising topology to meet the specification. The
topology selection may be based on rules created in order to characterize a
library of predefined circuit structures. Other approaches include the creation of
a circuit topology that will meet the specifications.
The tools that first incorporated the topology selection as part of the design flow
where based on heuristic, rule based selection [13]. A set of topologies, that the
tool could design, where characterized through a set of properties. That is, a
stage could have the property of high gain, low swing and so on. When a specifi-
cation is set the tool looks through all rules and decides which topology that is
the most promising.
Other methods computes the performance space of each topology in the library
[63]. The performance space is later compared to the actual specification. By
checking whether or not the feasible performance space and the specified perfor-
mance overlap the topology may be accepted or rejected.
In [40] the device sizing and the topology selection is carried out simultaneously.
In this approach the topology is controlled by additional optimization parameters
as an integrated part of the optimization problem.
Even though some design tools feature topology selection, the trend in recent
years is to let the designer make the selection. Some systems can, however, plot
trade-off curves where the designer may examine and compare the performance
of topologies. This may serve as a guide when selecting the most competitive
topology
3.1.2 Sizing and Biasing

There are two main approaches to solve the sizing problem, knowledge-based
and optimization-based. Knowledge-based methods use a predefined design plan
in order to size the components. The optimization-based approach on the other
hand uses various optimization methods to solve the task. The optimization-
based approach can be further categorized into simulation-based, equation-
based, or neural-network-based device sizing. A detailed description of these
approaches are given in Sec. 3.2 and Sec. 3.3.
33
3.1.3 Layout Generation

Layout generation is often one of the most time consuming parts of an analog
design. Also, the quality of the layout effects the performance of the circuit due
to effects such as interconnect parasitics, mismatch, and thermal gradients. Here
an overview of the approaches for layout generation is presented.
Template-Based Layout Generation

The first generation of analog layout tools where similar to digital module gener-
ators [16]. In a module generator the location of all devices and their intercon-
nect are fixed relative to the surrounding objects. A few parameters passed to the
module generator determines, e.g., the number of bits in a counter or the size of a
memory. The module generator then generates the structure according to the pre-
defined plan.
A similar approach can be use for module generators in analog design automa-
tion. The knowledge of an experienced designer is captured in a tool that auto-
matically generate the layout. The experienced designer create a so called
template for the design. The template consists of all of the objects in the design
as well as the interconnects.
This approach can be used to generate high-quality layouts since all analog
design techniques such as matching, symmetries, and so on can be included
directly into the template. It is also possible to perform simple optimization tasks
inside the template in order to achieve, e.g., a small circuit area or a specific
aspect ratio.
However, the approach have a major disadvantage when generality is concerned.
Since the template must be created specifically for each topology, this requires a
large effort. Also, as technology shift from on level to the next the template must
be updated. Thus it is expensive and time consuming to keep a large number of
templates updated. Templates are therefore only applicable if the reuse factor is
high.
Rule-Based Layout Generation

Rule-based layout generators make use of a predefined set of rules, defining
good analog layout. The placement and routing algorithms strive to obey these
rules when generating the layout. The rules are supplied by the designer and may
incorporate several effects such as grouping of specific building blocks or sym-
metry constraints.
However, the quality of the layout is highly dependent on the rules. Further, the
rules must be specifically adjusted for each new topology. Hence, creating a
good set of rules can be time consuming.
34
The Knowledge-Based Approach
Performance Driven Layout Generation

In performance driven layout generation the impact on the performance of the
circuit is taken into account. These tools uses optimization methods for perform-
ing the placement and routing of the circuit.
The first generation of analog performance driven layout tools borrowed many
features from performance driven digital layout generators. These digital tools
where adapted to handle analog constraints such as matching and symmetry. The
performance degradation was taken under consideration by classifying the sig-
nals with respect to parasitic sensitivity. For example, the wires with sensitive
signals where routed so that they experienced a small influence of parasitic cou-
pling [56].
One drawback of the first generation of performance driven tools, where that
they relied upon a library of module generators to realize relatively complicated
building blocks. Maintaining these generators proved to be costly. To solve this,
following tools where able to work with lower-level building blocks and by
themselves find the appropriate merging of blocks in order to save area and
reduce parasitics. Using lower-level building blocks limits the number of module
generators that must be maintained and upgraded as the process technology
evolves.
Another drawback in the early approaches was that there is no direct coupling
between the amount of performance degradation and the actual layout. Thus, it is
not possible to tell if the performance specification is violated or not.
To improve on this, the impact of layout introduced effects can be modelled at an
early stage in the deign process in order to find upper or lower limits on, e.g.,
interconnect parasitics [8, 11]. When the limits of parasitic influence in a partic-
ular node is known the layout tool strive to keep the parasitic load within these
boundaries. A major problem with this approach is to map the specification on a
set of performance metrics onto upper and lower bounds for the parasitics.
A later approach, referred to as direct performance driven layout generation [35],
relies on the computation of the node sensitivity with respect to parasitics. These
sensitivities are then used to generate a model to approximate the performance
characteristics of the circuit as it is influenced by parasitics. Thus, no intermedi-
ate step is required to determine the boundaries.
3.2 The Knowledge-Based Approach

The first automated device sizing schemes, presented in the mid 1980s, was
based on the knowledge-based approach. The basic idea is to have a predefined
plan on how the circuit components are to be sized in order to meet the perfor-
35
m
Expert designer
Performance specification
¤
4
Library of sizing plans
:
Execute sizing plan
Device sizes and biasing 32/0.7 32/0.7
10/0.7 10/0.7
64/0.7
Figure 3.2 Knowledge-based device sizing.
mance specification. The design plan consist of design equations and a design
strategy.
Design equations are usually formulated in such a way that given the component
sizes, the performance metric can be calculated. In the knowledge-based
approach these equations are reformulated so that given a set of performance
requirements, the device sizes can be computed. In order to accomplish this the
equation complexity must be kept at a low level, hence, only simple device mod-
els may be used.
Since the number of design parameters usually exceeds the number of perfor-
mance metric the parameters can not be determined explicitly by the equations.
To handle the extra degree of freedom some of the design parameters must be
chosen by other means.
In the knowledge-based approach a circuit specific design plan is used for this
purpose. The design plan contains information on how these design parameters
are to be chosen in order to reduce the degree of freedom and achieve good per-
formance.
In this section a short review of some of the tools that utilize the knowledge-
based approach is given.
36
IDAC
IDAC [12] is one of the first and most well-known knowledge-based design
tools. It was developed in the late 1980´s at the Centre Suisse d’Electronique et
de Microtechnique (CSEM), Switzerland. The tool supports the design of a large
variety of circuits such as amplifiers, voltage and current references, compara-
tors, and A/D converters. It was also released commercially by Mentor Graphics
Corporation.
Being a knowledge-based design tool IDAC relies upon a library of circuit spe-
cific design plans for different circuit topologies. The library is created by an
experienced designer and contains a set of design equations organized in an
appropriate way.
After executing the design plan the tool verifies the performance in a circuit sim-
ulator. If the circuit fails to meet the requirements the tool adjusts the perfor-
mance specification and executes the design plan again.
The procedural execution of design plans offers a short design times for circuits
already in the library enabling, i.e., design space exploration. However, even
though IDAC contains a large library of design plans the number of topologies in
analog design is huge and a designer might want to make small changes to the
topology in order to improve the performance. In such cases a completely new
design plan must be developed. Also, several different design plans might have
to be implemented in order to cover a wide range of possible scenarios.
The resulting performance in this kind of tool is dependent upon the quality of
the design equations and the design plan used. Solving the equation system pro-
duced by high-accuracy device models are not possible (today), thus the method
is limited to simple models. This yields poor estimation of the circuit perfor-
mance.
The IDAC is also accompanied by a layout tool, ILAC [56]. ILAC is based on
the basics of digital layout generators and uses several common digital layout
techniques. However, ILAC have been modified to take into account some ana-
log issues during the routing and placement.
During the placement the tool takes into account, e.g., device matching and sym-
metry. A library consisting of basic building blocks such as current-mirrors and
matched differential pares are used to realize the basic functions in the circuit.
As for the global routing the tool handles net couplings, undesired crossings, and
special routing of power nets. In the channel routing the tool strive to minimize
the parasitics on the sensitive nodes and minimize coupling between sensitive
and noisy nodes.
37
OASYS
OASYS [20, 21] is a knowledge-based design tool where the circuit is parti-
tioned into several sub-blocks. The tool have been developed at the Carnegie
Mellon university in Pittsburgh, USA.
Circuits addressed by the tool are mainly amplifiers for which a few topologies
are available. The tool decomposes the amplifier structure into sub-blocks such
as current mirrors, voltage references, and so on. In this way the topology is
described in several hierarchical levels.
Starting from a performance specification the tool initially decides what topol-
ogy to use. The topology is then divided into several sub-blocks for which the
tool derives the corresponding performance specification. In this way the design
problem is decomposed into several separate design tasks. Since there may be
several possible sub-blocks with the same functionality, the tool generates all
available styles and picks the one yielding the best performance.
The selection of topology at each hierarchal level is referred to as style selection.
The process of mapping the performance specification onto a sub-block is
referred to as translation. In one design their might be several hierarchal levels
and several steps of style selection and translation. The process precedes as a
series of design plan steps.
In order to make the correct decisions at nontransistor level hierarchies, effects
such as parasitic influence on the performance are estimated. At the bottom level
simple device models are used to determine the device sizes in a knowledge-
based manner.
To cope with the possible discrepancy introduced in the estimations of the per-
formance of low-level blocks the design tool utilizes a backtracking strategy in
order to refine the design. The process of repeated backtracking/translation may
be seen as a simple form of optimization in this case.
Besides the use of simple device models the main drawback of this tool is the
task of creating the design plan. It is reported in [21] that the creation of the first
design plan required 18 months. In this case all sub-blocks required in a two-
stage operational amplifier was implemented. However, even though all sub-
blocks are available, the time required to create a design plan is in the order of
months.
For fundamental sub-blocks the level of reuse is high since they can be used
repeatedly in a large range of circuits. It is however a challenging task to make
the blocks general enough.
The layout tool in OASYS, KOAN/ANAGRAM [8, 11], consists of the floor-
planner KOAN, and the router ANAGRAM. The tool have been released in sev-
38
eral versions. The most recent, KOAN/ANAGRAM III [8], is performance

driven. The tool is capable of device merging where it is beneficial from a per-
formance point of view. It uses a small set of low-level building blocks in order
to generate more advanced structures. This facilitates a reduced effort in main-
tain the library of module generators when migrating from one technology to the
next.
KOAN/ANAGRAM uses the technique with upper (and lower) bounds on the
interconnect parasitics. That is, the tool must keep the level of parasitic load in a
specific range when carrying out its task. The bounds can be supplied manually
or generated using a constraint generation algorithm.
BLADES
BLADES (Bell Laboratories Analog Design Expert System) [13] is one of the
first tools to rely on artificial intelligence (AI) to partition and size analog cir-
cuits. The system uses an expert system, built to mimic the behavior of an expert
analog designer.
It features a divide-and-conquer strategy where an operational amplifier is
assembled by combining several sub-circuits. An operational amplifier might,
for example, consist of a differential amplifier, a gain stage and an output stage.
The rules for how to decompose the circuit into blocks are written in a “if-then”
manner. In total the tool consists of about 250 different rules.
At the transistor level the blocks are sized in a similar manner. Here the decisions
are based on rules in combination with look-up tables where simulated results for
each sub-block are stored.
BLADES supports fast design of analog circuits, typically the time to design an
operational amplifier is only a few seconds. The tool however, as all knowledge-
based design systems, requires the adjustment and/or addition of proper design
rules. Since the system bases the sizing of sub-circuits partly on results stored in
look-up tables these have to be created and maintained for a large variety of
device models, manufacturing process, and specifications.
ISAID
ISAID [37] is developed at the Imperial Collage in London. The tool is based on
a the method of qualitative reasoning in order to adjust the performance of the
circuit.
Qualitative reasoning is a method of explaining mechanisms or changes in the
physical world. The approach is based on replacing exact performance relations
with quantitative relations, such as “larger” or “smaller”, and so on. For exam-
39
ple, if the value of one design parameter is made smaller the value of a specific
performance metric will increase.
In this case, the sign of the gradients of a performance metric, when changing a
design parameter, is used to determine what will be the effect of changing a par-
ticular parameter. Using a large number of such predictions, the device sizes are
adjusted.
3.3 Optimization-Based Device Sizing

In order to increase the generality of the sizing tools and remove the need for a
topology specific design plan the optimization-based design strategy was devel-
oped. In this approach the design decisions are made by an optimization algo-
rithm instead of a design plan. An optimization-based device sizing tool
typically consists of an optimization engine and a circuit performance evaluator.
Even though the main idea is the same in all optimization-based design tools
three different classes may be identified. The first set of optimization-based tools
depended on a SPICE like circuit simulator in order to evaluate the circuit per-
formance. At each iteration the simulator is called upon to determine the circuit
performance for a set of design parameters.
Another approach is to derive a set of equations relating the circuit performance
and the design parameters. These methods are called equation-based. The third
approach, the neural network approach, uses neural network models to estimate
the circuit performance.
3.3.1 The Simulation-Based Approach

Simulation-based design tools uses a standard circuit simulator in the optimiza-
tion loop as shown in Fig. 3.3. These tools can handle a large variety of analog
circuits since they are able to include all performance metrics that the circuit
simulator is able to compute into the cost function. Also, the predicted perfor-
mance will have the same accuracy as the models used in the simulator, i.e., the
same accuracy as obtained in traditional, manual design.
In this section a short review of some of the tools that utilize the simulation-
based approach is given.
DELIGHT.SPICE
DELIGHT.SPICE [47], is one of the most well-known simulation-based design
tools developed in the late 1980’s at the University of California, Berkeley, USA.
The tool combines the optimization toolbox, DELIGHT, with a standard circuit
simulator, SPICE.
40
Optimization-Based Device Sizing
System requirements Sized circuit

Optimization engine
Design parameters Circuit performance
Circuit Simulator
Figure 3.3 Simulation-based device sizing.
Beside having the accuracy of the circuit simulator the tool is also capable of
deriving the sensitivity to parameter variations for the performance metric. This
enables design centering and yield optimization.
DELIGHT supports a large range of optimization algorithms. The algorithm
used in DELIGHT.SPICE is called method of feasible directions. This is an
aggressive optimization method where a subset of worst performance and con-
straint functions direct the search.
One of the main reason for choosing an aggressive optimization strategy is to
keep the number of performance evaluations at a low level. Since the tool is
intended as an interactive platform for the designer, the running time must be
short [48].
However, the tool still requires several hours to perform its task due to the use of
a circuit simulator in the optimization loop. Also, due to divergence problems in
the SPICE simulator the optimization must be initiated using relatively good
starting points, i.e., an extensive search over a large parameter space is not possi-
ble. For this reasons the tool is more suited to fine-tune manual designs [48].
FRIDGE
FRIDGE [41] is a simulation-based design tool that perform global optimization
on an arbitrary topology. The tool uses simulated annealing as its optimization
engine. The cooling scheme is, however, modified compared to the traditional
method of slowly decreasing the temperature monotonically during the search.
Instead an adaptive cooling scheme where a series of fast cooling and reheating
schemes are used. It is reported that the proposed method reduces the number of
iterations with about 6 times on average. The use of an aggressive optimization
41
method is important in a simulation-based optimization tool since it is costly in

terms of CPU time to evaluate the circuit performance.
The optimization procedure in FRIDGE is divided into two parts. First the
design parameters are quantized according to a grid. Whenever the performance
of the design parameters, corresponding to one node in the grid, is evaluated, the
result is stored. Hence, some simulations can be avoided if one node is visited
several times. Also, in order to increase the efficiency of the simulator the DC
point at the start of a new simulation run is initiated by using the operation point
from the previous iterations.
When the global search is completed a gradient-based optimization method is
used, to search in the vicinity of the best grid point, and fine-tune the perfor-
mance.
MAELSTROM/ANACONDA
These two simulation-based device sizing tools share the same framework and
differs only in the optimization method used. In MAELSTROM [33] a combined
genetic/annealing algorithm is used whereas in ANACONDA [51] a novel
method referred to as stochastic pattern search is used. Both tools have been
developed at the Carnegie Mellon University (CMU) in Pittsburgh, USA.
Both design systems features a wrapper enabling the optimization engine to
interface with several industrial circuit simulators. In doing this the wrapper also
keeps the circuit simulator “alive” to avoid some of the overhead when initiating
a simulation in a standard circuit simulator. Furthermore, the system is capable
of handling simulator crashes and convergence problems.
The optimization task can be distributed onto a cluster of workstations i order to
reduce the CPU time for optimization. The CPU time required for medium size
circuits, 15-20 transistors, using a cluster of 24, 300 MHz, SUN Ultra 10 work-
stations, are between a few hours up to a day depending on the specification and
the number of optimization parameters.
The optimization algorithms used do not require an initial sizing of the devices
(even though the usage of such information will increase the convergence rate).
However, the resulting performance obtained depends on the initial value of the
optimization parameters [51] indicating the need to evaluate several starting
points in order to perform a sufficient exploration of the available design space.
These tools share several things, e.g., the cost function, with its precursor
ASTRX/OBLX (discussed in the next section) developed by the same group.
The group have also commercialized their research through the simulation-based
device sizing tool NeoCircuit, and the layout tool, NeoCell, supplied by Neo-
linear Inc. [45].
42
3.3.2 The Equation-Based Approach

The equation-based approach uses equations to evaluate the circuit performance
as shown in Fig. 3.4. The equations can be derived manually or using symbolic
analyzers [15]. These tools are capable of deriving the symbolic equations
directly from a netlist description.

Optimization engine
Performance equations
Symbolic analyser
Manually derived
Figure 3.4 Equation-based device sizing.
The accuracy of the performance predictions depend on the quality of the design
equations. If the equations are derived manually the device models are usually
too simplified, comparable to those used in manual design. If a symbolic analy-
ses is used the accuracy can be higher, in principal the same high-accuracy
device models as in circuit simulators can be used.
In this section a short review of some of the tools that utilize the equation-based
approach are given.
OPASYN
OPASYN [32] covers the complete design flow, including topology selection,
device sizing, and circuit layout. The tool have been developed at University of
California in Berkeley, USA. It features a design database that contains informa-
tion on each step in the design flow for a set of supported circuits.
The topology selection is done using a decision tree where all available designs
are classified according to some key criteria. The tree is created out of previous
43
optimization results as well as incorporated designer experience. For each speci-

fication a tree search is performed in order to find a set of suitable topologies.
Analytic circuits models are used to evaluate the circuit performance in the opti-
mization step. The models are specifically developed for each amplifier in the
database. These models consists of manually derived symbolic design equations,
upper and lower bounds for the design parameters, and declaration of the inde-
pendent design parameters. The simple models used are reformulated so that
dependent parameters are eliminated in order to reduce the number of design
parameters considered during the optimization.
The models have an error of over 200% when compared to SPICE simulations.
In order to improve on this, fitting parameters are added to the model. These
parameters are then refined by comparing the optimization results to SPICE level
simulations. However, the error is still in the order of about 20%.
The optimization method used is a steepest descent algorithm initiated in several
starting points. All design parameters are initiated according to a grid. For each
starting point, new nodes (parameter values) in the grid are used. In this way
local minima are avoided.
The layout generator used is based on a slicing tree floorplanner, commonly use
in digital floorplaning. Each amplifier in the database contains its own pre-
defined slicing tree. All basic building blocks are implemented as low-level
module generators.
During the routing and placement analog constraints such as matching and para-
sitic effects are taken into account. Nets are classified by their sensitivity to par-
asitics and routed in a particular order where the sensitive nets are routed first, in
order to reduce their lengths, and thereby their parasitic load.
STAIC
STAIC [22] was developed at the University of Waterloo in Canada. The tool
provides the designer with a framework to explore and find design trade-offs
within reasonable time.
The program feature an analog hardware description language with four different
levels for describing the circuits. A categorical description describes the func-
tionality of a set of blocks. All of these blocks contain a specific block descrip-
tion in which a more detailed realization is given, e.g., in the category amplifiers
there may be a Folded-Cascode OTA as a specific implementation. Each specific
block have one or several layout types. At the lowest level there are devices, with
associated layout generators.
44
Using the hardware description language, code on how the blocks at each
abstraction level are to be implemented is written. Each level contains both sim-
plified model and a more accurate one. The tool feature a coupling between the
levels of description enabling, e.g., layout effects to be taken under consideration
during other stages of the design process.
The device sizing in STAIC is divided in two parts. First a grid-based scan of the
design space using simple device models are performed. In this step possible
trade-offs are visualized to the user. The result of this scan is then used as a start-
ing point for a secondary optimization step where more accurate models are
used.
Typically simulation-based approaches are used to size the components in the
second optimization step. Hence, STAICs main purpose is to provide the initial
starting point to such a tool.
The language make use of several abstraction levels in order to reuse low-level
blocks. However, entering a new circuit description into the tool is a time con-
suming task, especially since several levels of abstractions have to be used. In
[22] it is reported that 10000 lines of C-code was used to implement three
medium size circuits.
Maulik
Maulik [39, 40] have been developed at the Carnegie Mellon University in Pitts-
burg, USA. In this tool the device sizing and the topology selection task is per-
formed simultaneously. The tool assigns additional optimization parameters for
selecting the circuit topology, e.g., one parameter that determines if the input
stage should be cascaded or not. Another parameter may be used to select
between an NMOS or a PMOS input stage. Using this approach a branch-and-
bound optimization technique is used to find the suitable topology and determine
the device sizes.
One different approach when compared to previous tools is that Maulik uses a
relaxed DC formulation. In contrast with many of the early tools that used a DC
solver in each iteration in order to arrive at a physical circuit Maulik considers
the DC solution a part of the cost function. Hence, the circuits visited during the
optimization run may not be physically feasible.
Using a relaxed DC formulation render the possibility to use high accuracy
device models since there is no need to analytically solve the DC equations for
the circuit. In Maulik high-level, BSIM [10, 36], models are used for the devices,
i.e., high accuracy is achieved for the device parameters. However, since Maulik
do not support automatic derivation of the equations required to evaluate the
small-signal performance of the circuit these equations are simple expressions
entered manually.
45
ASTRX/OBLX
ASTRX/OBLX [49] have been developed at the Carnegie Mellon University
(CMU) in Pittsburgh, USA. The tool relies on asymptotic waveform evaluation
(AWE), encapsulated device evaluators, simulated annealing, and a relaxed DC
formulation in order to perform device size optimization. The tool combines the
simulation-based and equation-based approach.
In order to reduce the long simulation times in circuit simulators and the low
accuracy achieved by simple models used in many equation-based design tools,
ASTRX/OBLX uses asymptotic waveform evaluation [55]. AWE is an efficient
approach to analyze linear circuits that is considerably faster than using a SPICE
like circuit simulator. In AWE a reduced complexity model is used to predict the
small-signal performance metrics. All other performance metrics are computed
from circuit equations.
The encapsulated device evaluators are used to evaluate the small-signal param-
eters of a circuit. These evaluators relay on high-accuracy device models used in
industry.
The use of a relaxed DC formulation is done in a similar way as in Maulik. How-
ever, here the DC constraints are automatically generated. In order to solve the
optimization problem a simulated annealing algorithm is used.
One draw back of the AWE approach is that nonlinear circuit behavior can not be
modeled. Furthermore, the approximation of the circuit transfer function with a
lower-order model render some loss in accuracy. However, the designer interac-
tion is made small since the setup for the optimization problem is highly auto-
mated.
AMGIE
The AMGIE [52, 53] design system, developed at Katholieke Universiteit at
Leuven, Belgium, covers the complete design flow from topology selection and
device sizing to layout generation.
Topology selection is performed using a set of three filters applied to a topology
database. The two first filters compare the performance space of the topologies
with the specification provided by the user and rejects the candidates that can not
meet this specification. The remaining topologies are ranked according to a rule-
based scheme in order to pick the most promising one.
The device sizing system is a compilation of several tools combined into a
design framework. It relies on a symbolic analyzer to automatically derive the
small-signal equations required in AC analyses directly from the circuit topol-
ogy. The symbolic equations are simplified in these tools in order to reduce the
46
size of the expressions evaluated inside the optimization loop. Symbolic equa-
tions for the DC constraints are also derived from the topology while all other
(e.g., time-domain equations) must be entered by the designer.
It should be noted that even though the system supports the automated setup of
design equations directly from the circuit topology it is only intended to be used
by expert users. The expert users can create libraries of “sizing plans” which is
later used by ordinary users to size a specific topology. The sizing plan should
not be confused with the design plan used in knowledge based systems. In this
case the plans consists of design equations for the optimization engine to operate
on and additional knowledge added by the designer in order to reduce the size of
the problem. The time to create such a sizing plan for a “moderate-complexity
circuit” is about 8 hours for an expert user.
The optimization engine, supports both global optimization methods such as
simulated annealing and local, gradient-based, methods. During the optimization
phase several methods may be combined on order to increase the convergence
rate. For example a simulated annealing algorithm may be used to search the
design space while a gradient based methods is used to fine tune the final solu-
tion.
The layout generator LAYLA [35], uses a performance driven problem formula-
tion in order to minimize the performance degradation in the layout step. The
simulated annealing optimization algorithm is used to minimize the impact of
interconnect parasitics, mismatch, and thermal effects during the floorplaning. In
the routing phase several routing solutions are examined in order to minimize
performance degradation and increase circuit yield.
In the LAYLA tool the sensitivities of the performance metrics due to changes in
the layout phase are computed before generating the layout. This is referred to as
direct performance driven layout generation, as apposed to the method where
upper and lower bounds on the parasitics where obtained from the performance
specification. The sensitivities are used to derive a first-order model of the rela-
tion between layout induced effects and the circuit performance. This model is
the use to predict the performance degradation when generating the layout.
The tool also has a redesign wizard that steps in whenever a circuit fails to meet
the specification. This tool compares the reason for failing to meet the specifica-
tion against a redesign database which contains of a set of scenarios and possible
solutions. The optimization process is then adjusted and restarted at an appropri-
ate point in the design flow.
47
GPCAD
GPCAD [25, 26] is a device sizing tool dedicated to the design of operational
amplifiers. It have been developed at the Stanford University in Stanford, USA.
The novelty of the tool is to formulate the sizing task using geometrical pro-
graming (GP). In order to accomplish this the design equations are written as
posynomial equations. This results in a convex optimization problem for which a
global optimum can be found in only a few seconds, even for very large circuits.
The function f is a posynomial of x if
t
α 1k α 2k α nk
f ( x 1 , …, x n ) = ∑ ck x1 x 2 …x n (3.1)
k=1
where c j ≥ 0 and α ij ∈ ℜ . When the sum only contains one term, i.e., t equals one
then f is a monomial function. In order to formulate a convex optimization prob-
lem the cost function and the inequality constrains must be formulated as posyn-
omials. Equality constraints must be formulated as monomials.
Even though formulating the design equations as posynomials simplifies the
optimization task the method suffers from accuracy problems. Since all design
equations must be formulated as posynomials, the use of high-accuracy device
models is not possible because they can not be reformulate as posynomials. Fur-
ther, GPCAD do not include an automated approach for generating these equa-
tions, limiting the usage of the tool to handle a few, predefined, circuit structures.
In [25] the design of a two-stage operational amplifier is discussed, the amplifier
is to be synthesized in a 1.2 µm standard CMOS process. The resulting perfor-
mance from the tool is compared to SPICE simulations. Even though the unity-
gain band width is only 8 MHz the phase margin diverges by 6 degrees from that
reported by the simulator. Clearly this problem is increased at higher frequen-
cies.
To conclude, the GPCAD approach offers short execution time at the expense of
accuracy [51].
SD-OPT
SD-OPT [42] have been developed at the University of Sevilla, Spain. The tool is
specifically targeted at designing switched-capacitor delta-sigma modulators.
Two steps of optimization is used, the first at the modulator level and the second
at the cell level. In the first, a behavioral simulator, ASIDES, operating on a
library of design equations is used to explore the design space and perform the
initial sizing at the modulator level. The design equations are pre-defined expres-
sions characterizing the different blocks, including nonidealities, in the modula-
48
tor. The output of the behavioral analysis is a set of performance specifications

for the cell-level blocks.
In the second step a simulation-based approach is used to size all individual cells
in the modulator. In both steps simulated annealing is used as the optimization
engine.
The tool offers an efficient way of designing the modulators supported. How-
ever, adding new modulators to the design database requires “exhaustive analy-
sis of modulator architectures as well as general SC circuits” [42]. Thus, the cost
for implementing a new structure is high.
3.3.3 The Neural-Network Approach

In this approach a neural-network is trained to model the behavior of the circuit
to be optimized. This enables fast evaluation of the performance metric for a set
of design parameters. However, the approach requires that a sufficient number of
training points are supplied in the region of interest. The method is illustrated in
Fig. 3.5.

Optimization engine
Neural network model
Performance evaulator + training data
Figure 3.5 The neural network approach.
Generally there exist a trade-off between the amount of training data to use and
the accuracy of the performance predictions made by the neural network. How-
ever, increasing the training data will require more time in the performance eval-
uator. Usually a high accuracy performance evaluator, like a circuit simulator, is
used to evaluate the performance of the training data.
49
Alpaydin
Alpaydin [2, 7] preforms the device sizing using neural performance models in
combination with user defined equations. It uses a fast circuit simulator in order
to compute the DC operating point.
A neural-fuzzy model is used for some of the performance metrics. The model is
derived by evaluating the performance for a set of training data using a SPICE
simulator. The neural-fuzzy model can approximate the behavior of any linear or
nonlinear circuit behavior.
The training is performed without human intervention. However, accuracy
depends on the number of training points which must cover the parameter space
where the model are to be used. Thus, in order to arrive at accurate predictions of
the performance the network must be trained using a large set of training data.
Other AC performance metric are computed using manually derived perfor-
mance equations. This is a drawback since these equations must be supplied by
the user for each new topology.
In order to maximize the yield during the device sizing the effect of process vari-
ations are modelled and incorporated into the cost function. The tool is, however,
not capable of handling mismatch between devices.
The optimization method used is a combination of evolutionary strategies and
simulated annealing. It is reported that the method is able to find good solutions
starting from a randomly selected design point.
3.4 Commercial Device Sizing Tools

The interest in analog design automation have been lower than in the digital
counterpart due to various reasons discussed in Chapter 1. There are however
clear signs that this is changing. An analyst at Lehman Brothers recently wrote
that the “Analog and mixed-signal semiconductor design is a huge market
growth opportunity, especially considering that the percentage of analog and
mixed-signal IC’s will grow from a current 20% of all IC’s to 70% within five
years. With some of today' s analog and mixed-signal EDA toolsets currently
being based on a very manual methodology, we see automated analog and
mixed-signal toolsets representing a huge market opportunity. It is potentially
among the hottest market segments in EDA that we have seen.”
All of the tools discussed above have been developed within research projects
and can therefore be classified as university tools. There are however a few com-
panies that offers tools for device sizing. Most of these are commercial imple-
mentations of the university tools. Here some of these tools are listed.
50
Commercial Device Sizing Tools
NEOLINEAR
Neolinear [45] was founded by the group behind the sizing tools ANACONDA
[51] and MAELSTROM [33]. The company offers a design suit, covering both
device sizing (NeoCircuit and NeoCircuit-RF), and layout generation (Neo-
Cell) for analog circuits. The sizing tools are simulation-based and interface
with several industrial simulators similar to ANACONDA and MAELSTROM.
The tools have been successfully used to produce high-performance analog inte-
grated circuits in industry [24, 58]. In this case the design time have been
reduced from weeks to days.
ANALOG DESIGN AUTOMATION

The system provided by Analog Design Automation [3] is similar to NeoCir-
cuit. It uses the simulation-based approach and interface with several industrial
circuit simulators. It can optimize any type of analog circuit as long as an appro-
priate test bench is created.
BARCELONA DESIGN
Despite the name Barcelona Design [5] it is situated in Newark, CA, USA, and
was founded by the people behind GPCAD [25]. The company offer synthesize-
ble IP (intellectual property) blocks, i.e., an optimization engine for a specific
circuit is licensed to the customer. These blocks contains the required design
equations written as posynomials. The optimization task is formulated as a geo-
metrical programming problem for which a global optima can be found in a few
seconds.
In contrast to standard IP blocks, which meet a given specifications, these blocks
may be synthesized to meet a range of different specifications. Currently the
company supplies such synthesizeble IP blocks in three different areas, PLLs,
data converters, and amplifiers.
The company do not offer a general solution for sizing the components of inte-
grated circuits. The blocks only supports a fixed topology, with a few minor
modifications. For operational amplifiers, three single-ended topologies are
offered. These blocks are technology dependent, as for today the IP blocks are
available in two processes, TSMC 0.18 and TSMC 0.13. Further, the circuit may
only be optimized with respect to area, power dissipation, and unity-gain band-
width.
This limits the usage of these blocks. However, compared to a traditional IP
block, the approach offer the user an increased level of reuse and flexibility. The
advantage of the method is that it is fast, in the matter of minutes the sizing, and
layout of the component is completed.
51
ANASIFT
The tool offered by Anasift [4] has not yet been officially launched but the com-
panies claims that their tool is capable of sizing circuits with about 100 transis-
tors in the matter of hours. The tool use the equation-based approach to size the
circuit components. Initially the software will target operational amplifiers.
3.5 Summary of Existing Approaches

It is hard to compare the performance of the tools presented here in a qualitative
manner. Table 3.1 through Table 3.3 presents an overview of the tools. The
tables are not a fair comparison between the tools. However, it gives an estima-
tion of the performance that could be expected from an analog design automation
tool.
The circuit complexity may be defined as the number of devices and the relation
between their design parameters and performance metrics. In this case it is hard
to make any comparison between the tools since no independent benchmarking
have been performed. Instead the functionality of the tool is demonstrated by siz-
ing different topologies.
Clearly, Table 3.1 through Table 3.3 shows that the example circuits span over a
large variety of topologies. Comparing the complexity involved with sizing of an
8 transistor circuit with that of sizing a 60 transistor circuit is not possible. Fur-
ther, the number of design parameters subject to optimization is an important
factor as well. In many cases only a subset of design parameters are used as opti-
mization parameters. Since the number of design parameters have a large impact
on the difficulty involved with sizing the circuit this is also an important factor to
take into account.
Furthermore, some tools requires an existing solution as a starting point in order
to converge. There is a difference between tools that size the circuit from start,
without requirements on the starting point, and tools that take a design point and
fine-tunes the performance.
The performance specification also effects the CPU time required. In this case a
large variety of circuits are sized. Even if the circuit complexity is the same the
performance specification will effect the total run time of the tool. Feeding the
tool a specification close to what is feasible will result in a larger run-time com-
pared to a specification that can easily be met.
52
Table 3.1
IDAC OASYS BLADES ISAID DELIGHT.SPICE FRIDGE
Performance Simplified Simplified Lookup Simplified equa- Circuit Simulator Circuit
evaluation. equations equations tables + rules tions + Qualita- Simulator
Comparison of tools for analog device sizing.
tive reasoning
Estimation 15% 25% Not reported 14% 0% 0%
error*
Search method Design plan Design plan + AI Qualitative rea- Feasible direc- SA + local
+ post opti- backtracking soning + post tions method
mization optimization
Synthesis time “A few sec- 5 sec. “A few sec- Not reported 18h (Masscomp 45 min.
onds” (VAX 8800) onds” MC 500)
Effort to add 4-45 6 months, Incorporate Not reported 10-30 lines of 1h
new circuit designer including cir- designer code
months cuit analysis knowledge
Derivation of Symbolic Manually Manually Manually - -
equations analyzer +
Summary of Existing Approaches

manually
Circuit 15 circuit 19 parame- 34 devices 8 parameters, 13 28 transistors, 20 10 parame-
complexity types, from ters, 17 device OpAmp device OpAmp parameters ter OpAmp
5-30 devices OpAmp
* Compared to circuit simulations using accurate device models.

53
54

Table 3.2 MEALSTROM ANACONDA OPASYN STAIC Maulik
Performance Circuit Simulator Circuit Simula- Simplified Simplified Simplified equa-
evaluation. tor equations equations tions + BSIM
Estimation 0% 0% 200% 24% 24%

error*
Search method GA+SA Stochastic pat- Grid + steep- Two step opti- Branch and bound
tern search est descent mization
Synthesis time 3.6 h (15 Sun 10 h (24 Sun 1 min. 3 min. MIPS 1 min. DEC 3100
Sparc - 1, 140 Ultra 10, 300 (VAX 8800) 2000
MHz) MHz)
Effort to add Not reported Not reported 2 weeks for 3 circuits 6 months, includ-
new circuit well under- required ing circuit analy-
stood circuits 10000 lines of sis
code
Derivation of - - Manually Manually Manually
equations /
design plans
Circuit 31 device 37 devices 7 parameters, N/A (22 39 variables, 7 for
complexity OpAmp, 27 power amp. 20 60 device device topology selec-
parameters parameters OpAmp OpAmp) tion. 19 device
OpAmp

Table 3.3 ASTRX/OBLX AMGIE GPCAD SD-OPT Alpaydin
Performance eval- AWE + equa- Simplified Simplified Equations + Fussy neural
uation. tions equations equations + Behavioral sim- network
GP1 ulations
Estimation 30% 10% 30% 0% Not reported

error*
Search method SA SA + several Simple primal SA Evolutionary
local methods barrier method strategies + SA
Synthesis time 11.8h/run 5 min. “a few seconds” 1.5 Weeks 45 min. (124
(IBM RS/6000- min. with mis-
550) match model)
Effort to add new “a few days” 8h Not reported Exhaustive anal- Evaluation of
circuit ysis required training points
Derivation of Automated Symbolic ana- Manually Manually Training points
equations lyzer + circuit simula-

tor
Circuit 33 devices 14 parameters, 9 10 devices Forth-order 31 devices
complexity devices OpAmp sigma-delta OpAmp
modulator

55
When considering the design time it is also important to take into account the
overhead associated with the sizing process. Some methods, like for example
knowledge-based methods, have short optimization times. However the time
required to derive the circuit equations are substantially larger then for e.g. simu-
lation-based sizing.
Other factors such as the development in computer efficiency, the device models,
the number of performance metric taken into account, and the process technol-
ogy effects the result.
There are however some general properties of the tools discussed in this chapter.
Some of these aspects will be addressed below.
3.5.1 The Knowledge-Based vs. the Optimization-Based Approach

The first generation of design tools utilized the knowledge-based approach. In
this approach the design parameters are determined by executing a circuit spe-
cific design plan. It is capable of sizing all circuits for which such a plan can be
derived. Once the design plan have been created the execution time is short, in
most cases in the order of seconds. However, the approach suffers from several
disadvantages.
First, a design plan must be crated for each circuit that are to be designed using
the tool. Developing a new design plan is a tedious task that requires the knowl-
edge of a skilled designer. In [6] it is reported that the average time required to
create such a plan is four times longer than required to manually designing the
circuit. This limits the use of a knowledge-based approach to circuits featuring a
high level of reuse. However, when the design plan is derived the fast evaluation
permits extensive design space exploration, which is more costly using the opti-
mization-based approach.
Furthermore, when the process technology migrates from one generation to the
next the design plans must be updated. Thus maintaining a large library of design
plans is costly and time consuming.
The accuracy of the approach is limited. The basic concept of a knowledge-
based tool is to explicitly solve the design equations and provide additional rules
for how to take care of the degrees of freedom that is left. In order to reformulate
the design equations they are bound to be simple, thus modern device models
can not be used. When modern process technologies are used this may result in
large deviations from the performance predicted by a more accurate model. In a
worst-case situation the error is several hundred percent.
In the optimization-based approach the need for a circuit specific design plan is
circumvented. Instead an optimization engine is used to make all necessary
56
design decisions. This increases the generality of the tool and reduces the setup
time.
The use of optimization methods instead of a design plan also increases the qual-
ity of the solution. While the knowledge-based approach use a set of predefined
rules to arrive at a solution, the optimization-based tool will strive to find an
optimal (local or global) solution. In the case of knowledge-based device sizing
the quality of the solution depends on the skills of the designer that creates the
design plan.
To conclude, the knowledge-based approach offers a time efficient way of
designing analog circuits. However, the overhead in creating a design plan and
the low accuracy makes the method inefficient when modern technologies are
considered. On the other hand, the optimization-based device sizing approach
features a higher level of generality and strives to find optimal solutions to the
device sizing problem.
3.5.2 Comparison of Optimization-Based Approaches

From the previous section it is clear that the knowledge-based approach suffers
from sever disadvantages that is not acceptable in a modern design tool. Thus,
the second-generation of tools for device sizing utilizes an optimization engine
to find the device sizes.
The level of automation is one of the most important factors when implementing
an automated device sizing tool. Clearly the goal is to relive the designer of as
much work as possible. However, in doing this the designer freedom to, e.g.,
examine alternative circuit topologies, must not be restricted too much since this
may have a negative effect on the outcome of the design process.
When looking at the level of automation both the efficiency of the device sizing
part, the execution time, and the work involved with setting up the optimization
problem must be considered.
Preparatory Effort
In the simulation-based approach a circuit simulator is used inside the optimiza-
tion loop. Thus, as long as the circuit performance can be measured using the
output of the simulator, the setup may be accomplished in a short time. In princi-
ple the use of the simulator is similar to that used in manual device sizing meth-
ods, i.e., a test bench in the simulator environment must be created. The test
bench describes how to measure each performance metric that are to be used in
the cost function.
For the equation-based approach the situation is different. Here the performance
is evaluated using a set of equations. For the early tools these equations where
57
supplied manually. This limited the accuracy of the equations. Using simple
design equations clearly effect the accuracy of the resulting performance predic-
tions.
There are however methods of generating the equations automatically via sym-
bolic analyzers. These tools are able to generate the equations required to evalu-
ate several types of performance metric. However the designer must instruct the
tool how to derive the appropriate expressions. This process is similar to setting
up a test bench inside a circuit simulator. Introducing new types of performance
metric into the symbolic analyzer can be time-consuming, however, once the
metric is included it may be used on a large range of circuits.
Using a symbolic analyzer to derive the equations render the possibility to use
accurate device models. Also, the risk of introducing errors when deriving the
equations are eliminated.
The level of automation in the preparatory phase is also high for the neural net-
work approach since it requires little interaction from the user. Basically the pro-
cedure, from a user point of view, is similar to that of the simulation-based
approach.
In order to train the neural-network an accurate evaluation engine for the training
data is required. In most cases a circuit simulator is used to carry out this task.
The user must create an appropriate test bench for the circuit simulator in order
to estimate the corresponding performance of the training data. However, in
order to train the network to achieve high accuracy the number of training points
must be made large. Hence, there is an initial cost to be paid in doing this.
Execution Time
The execution time have traditionally been considered to be one of the most
important parameters when determining the quality of a device sizing tool. The
time spent on sizing the circuit depends on several things.
First, the optimization engine is of importance. Methods that uses classical, gra-
dient-based, optimization algorithms may arrive at a circuit solution in a short
time. However, due to the nonlinear problem these optimization methods are
easily stuck in a local minima. In order to assure good solutions the optimization
process must be initiated in several starting points.
If a global search algorithm is used the convergence time may be much larger but
the risk of getting stuck in a poor local minima is reduced. However, to assure
good solutions global search algorithms should be restarted in different starting
points [57].
58
Secondly, the type of performance evaluation used will affect the execution time.
In the simulation-based approach a circuit simulator is called in each optimiza-
tion run. However, standard circuit simulators are designed to interact with the
the designer and not with an optimization algorithm. A human designer often
invokes the simulator to perform a single, or a small batch of simulation tasks. In
this case an overhead of a few seconds to start the simulator is no problem. An
optimization-based design tool, on the other hand, requires the evaluation of tens
of thousands of circuits.
In order to arrive at a DC solution the circuit simulator must perform internal
iterations. Performing these iteration in each optimization loop is costly when
computational time is concerned, but this can be alleviated by proper control of
the simulator. For example the state of the circuit simulator from the previous
iteration may be used as an initial state in the next.
In the equation based-approach the performance evaluation is performed by
evaluating the symbolic equations. Using a relaxed DC formulation alleviates
the problem of finding a DC solution in each iteration. Thus, the equation-based
approach offers significantly shorter execution times than the simulation-based.
The neural network approach offers fast evaluation of all performance metric
due to the simplified model. However, it may require a circuit simulator to, e.g.,
determine the DC operation point which increase the run time.
Comparing the execution time, the simulation-based approach requires days
while the equation-based and the neural network approach are able to complete
the sizing task in minutes.
Generality and Complexity

The generality of a tool may involve the number of circuit types handled and the
ability to add new circuit. The complexity aspects include the number of devices
that can be automatically sized by the tool and the number of performance metric
that are considered while carrying out the optimization.
The generality of the simulation-based approach is high since the designer can
choose to defined custom performance metric just by extending the test bench.
Thus, new circuit types may be included as long as the circuit simulator is able to
derive the performance metric required. Due to the similarities between the neu-
ral network approach and the simulation based approach the procedure of adding
additional performance metric to the neural network approach is the same.
For the equation-based approach the generality is instead limited by the ability to
derive symbolic equations for the performance metric. A symbolic analyzer may
be used to derive the small-signal performance metric for large circuits using
high accuracy device models. However, for large-signal time-domain metric,
59
such as slew-rate, there are no systematic methods for deriving accurate sym-
bolic equations. Thus, in all equation-based tools these equations must be
derived manually.
Changing the device model is in practice more difficult in the equation-based
approach. For simulation-based tools the process of changing the device model
involves updating the model library of the circuit simulator. If an industrial sim-
ulator, like HSPICE [28] or Spectre [9], is used this will be completed by the
vendors of the respective simulator. For the device models used in equation-
based tools new equations must in general be entered by the vendor of the tool.
This is only a practical problem since the released device models might as well
be exchangeable modules in an equation-based design system.
Many equation-based design systems relay upon a library in which a set of
design equations are stored. These equations are created, either manually or
using symbolic analyzers, by an experienced designer. Thus, the user is only sup-
posed to pick predefined topologies from this library. This might be considered a
restriction since many analog functions require application specific circuit solu-
tions. Also the number of circuit solutions that can be used to implement one
type of functionality is large.
Many of the early simulation-based design tools where only able to fine-tune the
performance of a circuit. That is, the tool requires a good starting point to ensure
convergence. In more recent design tools the requirements on good starting
points are alleviated since global optimization techniques are used. However,
performing an extensive search in the parameter space will result in examining
nonfeasible parameter values. This can cause convergence problems or simply
crash the circuit simulator. Thus such problems must be taken care of when using
a simulator inside the optimization loop.
There are no differences in the size of the design problems that can be handled
by the tools. However, in the neural-network approach the training data increases
rapidly with the number of design parameters. Thus, a large circuit may require
an impractical large number of training points.
As for the equation-based approach the size of the performance equations grow
with the number of design parameters. Due to limited memory resources the size
of the equations may become to large. An alternative way of representing the
equations and symbolic approximation may be used to reduce these problems.
The simulation-based approach suffers from the increased number of calls to the
optimization engine resulting from a large number of design parameters. Since
each call is costly in terms of CPU time this puts a practical limit on the number
of devices that can be handled.
60
The optimization engine itself must also be capable of handling a large number
of design parameters and ensure convergence within reasonable time. This prob-
lem is, however, common to all of the approaches.
Accuracy
The accuracy may be defined as the difference between the performance pre-
dicted by the device sizing tool and the performance of the completed circuit. In
the case of pure device sizing (i.e., the layout induced effects are not considered),
the differences are measured between the performance reported by the sizing
tool and the corresponding performance measured using a circuit simulator and
accurate device models.
In the simulation-based approach accurate device models are usually used. Thus,
the performance prediction in this case is excellent.
For the equation-based approach the situation is more complicated. The accuracy
is dependent on the device models used. Generally, when equations are derived
manually the device models are bounded to be simple. Thus, the accuracy will be
low. For the design tools in Table 3.1 through Table 3.3 the accuracy of the tools
using symbolic analyzers to derive the performance equations is higher. In order
to make accurate prediction of the performance in modern process technology
simple device models can not be used.
Equation-based tools that use accurate device often apply approximation tech-
niques to reduce the size of the expressions for the performance metric. The
result is that the computational efficiency is increased at the expense of accuracy.
It is however possible to obtain the same high accuracy in an equation-based tool
as in simulation-based tool since the same device models may be used in both
cases.
In the neural-network approach there is a trade-off between the number of train-
ing points and the accuracy achieved. Using a large set of training data will result
in an increased accuracy, however, covering a large parameter range in a circuit
with many design parameters require extensive simulations.
Conclusion
It is difficult to give general guidelines on what approach that is the best to use.
All methods have their specific strengths and capabilities.
The equation-based approach offers short setup-times (with the use of a sym-
bolic analyzer), and short execution time. However, the method traditionally suf-
fers from reduced accuracy due to approximations or low-order design
equations. Also, some of the design equations can not be derived in a systematic
way.
61
The simulation-based approach have high accuracy due to the use of circuit sim-
ulators. The generality is also high and a large range of design problems may be
addressed. However, the approach have longer execution times due to the use of
a circuit simulator in the optimization loop.
The neural-network approach have short execution times and large generality.
The drawback is, however, the large time spent in the preparatory phase as well
as accuracy problems.
62
CHAPTER IV
THE DESIGN PLATFORM
The proposed design platform offers an automated alternative to the manual

design flow. Using the platform, both the design efficiency and the circuit perfor-
mance can be improved. The platform covers some of the most time-consuming
and performance-critical parts in analog design; determining the device sizes,
generating the circuit layout, and finding possible trade-offs.
In our tool we have chosen to use the equation-based approach for evaluating the
circuit performance. The advantages/disadvantages with this approach have been
discussed in the previous chapter.
One of the traditional drawbacks of the equation-based approach is the low accu-
racy due to the use of simplified models and approximations. In modern process
technologies, simple models do not accurately account for all effects that must
be considered during the design.
In this work we use the same high-accuracy device models as in modern circuit
simulators. Thus, the accuracy of the predicted performance is as high as in sim-
ulation-based device sizing tools.
The penalty for using accurate device models is increased execution times. How-
ever, the time to find a solution is still in the order of minutes compared to hours
or days for a simulation-based tool. An equation-based design tool is therefore
more suited to, e.g., perform extensive design space exploration in order to fully
explore the potentials of the topology and the process technology.
63
The Design Platform
Traditionally, the setup time for new circuits using the equation-based approach
is long. Here we combine the use of a symbolic analyzer with a netlist parser in
order to automatically derive the design equations. Using this approach the equa-
tions for a new circuit topology can be derived in a few minutes.
The device models are implemented as exchangeable modules. Thus, it is easy to
change the models used to evaluate the circuit performance. Also, the process
parameters may easily be changed in order to ease the migration from one pro-
cess technology to the next.
Furthermore, the platform is a collection of several tools. One tool may be
replaced if there are more efficient alternatives available. It is also possible to
use each part of the design platform separately.
Currently, the platform is not optimized for speed; our focus is on evaluating the
approach. Thus, the performance can be increased further by fine-tuning parts of
the platform. Also, the platform is targeted at time-continuous amplifiers. It is,
however, possible to expand the approach to other types of circuits as well as
adding additional performance metrics.
In this chapter, an overview of the design platform is presented, a more detailed
description of the device sizing part is also given. In the following chapters, the
layout generation, the parasitic feedback, and the design space exploration tools
are discussed.
4.1 The Design Platform

In order to allow easy implementation and experimentation the tools are imple-
mented in MATLAB [38] and SKILL [59]. It interfaces with one of the most
common design environments for analog and mixed-signal circuits, Virtuoso
custom design platform, provided by Cadence design systems inc. [9].
There are several reasons for choosing Virtuoso as the main framework for the
design platform. First, Virtuoso is commonly used in analog and mixed-signal
design. Thus, the designers are already familiar with the environment. Secondly,
it possesses a powerful scripting language, SKILL, which may be used to create
new and control existing functions within the Virtuoso tools. This, in combina-
tion with our previous knowledge of the Virtuoso framework, makes it an attrac-
tive platform to work with. However, other platforms may be supported in the
future.
Our proposed design platform is shown in Fig. 4.1. The starting point is a netlist
of the circuit topology, currently entered in the Virtuoso schematic editor. The
netlist is analyzed by a netlist parser, which generates a set of circuit dependent
constraints and large-signal performance metrics. This parser also generates the
64
The Design Platform
Inputs supplied by the user
Circuit topology User-specified perf. metrics

e.g. large-signal time-domain Performance specification
VirtuosoTM schematic editor
properties, transistor matching
Derivation of
performance metrics
Symbolic analyzer & netlist parser
Process parameters
& Formulation of the Parasitic extraction
transistor model optimization problem
Device size optimization Layout generation
Outputs
Sized circuit Circuit layout
exported back to VirtuosoTM
exported back to VirtuosoTM
(for post verification)
Figure 4.1 Overview of the proposed design platform.
input to the symbolic analyzer program, which is used to derive small-signal and
time-domain performance metrics.
A cost function, is generated by combining the circuit specification and the per-
formance metrics. Additional performance metrics, to be included in the cost
function, may also be added by the user.
In the next step, the design parameters are determined by the circuit optimizer in
order to meet the performance specification. The circuit optimizer exports the
device sizes to the layout generator which generates a template-based layout.
When all physical dimensions are determined, a parasitic extraction tool
retrieves all interconnect parasitics in the layout. Using the extracted parasitics
the optimization problem is reformulated and the circuit optimizer is again used
to determine the device sizes required to meet the performance specification.
This procedure is repeated until the deviation in the cost function from one itera-
tion to the next is smaller than a user-defined threshold value. Due to the feed-
back of parasitics, the device sizes are adjusted in order to meet the performance
specification after completing the layout. At the end the device sizes are
exported back to the Virtuoso schematic editor.
65
The Design Platform
4.2 Device Size Optimization

During the device size optimization, all design parameters are determined in
order to meet the performance specification. In Fig. 4.2 an overview of the
device sizing tool is given.
4.2.1 Entering the Circuit Topology

The starting point of the device sizing procedure is a netlist for the circuit topol-
ogy, entered using the graphical interface of the Virtuoso schematic editor. This
is a commonly used schematic editor and the user is able to perform the optimi-
zation without having to enter the circuit topology into a separate tool. It also has
the advantage that all other tools and functions available within the Virtuoso
framework are available.
When entering the circuit topology, the user may define each component as fixed
or use its design parameters as optimization parameters. Fixing a parameter will
reduce the degrees of freedom and thus the time required for optimization. Typi-
cally, e.g., the load capacitance at the amplifier output may be fixed, while the
transistor widths are optimization parameters. Another example is to fix the
channel length of the transistor and only use the width as an optimization param-
eter.
The designer may also specify matching conditions. Even though it is possible to
let the tool find the device sizes for each transistor itself, it is an advantage to
specify an exact ratio in order to ensure a good analog layout. Further, matched
transistors share the same optimization parameters which will reduce the size of
the optimization problem.
The current version of the tool do not support hierarchical entering of the sche-
matic being optimized. This may be considered a drawback when entering large
circuits, however, since the current goal is to handle amplifiers, which in most
cases are limited to less then 100 devices, the need for abstraction is not critical.
Our aim is to support hierarchal entering of the topology in future versions of the
tool.
4.2.2 Optimization Parameters

The design parameters that are used as optimization parameters are the lengths
and widths of the transistor and the size of resistors and capacitors. In order to
meet the KCL (Kirchhoff’s current law) constraints the node voltages are optimi-
zation parameters as well. Also the biasing voltages and currents are optimiza-
tion parameters.
66
Figure 4.2
Overview of the device size optimization.
Circuit topology Constraints

TM e.g. KCL, Process parameters
Virtuoso schematic editor transistor operation region
Large-signal perf. metrics Circuit optimizer Sized circuit

Netlist parser e.g. power dissipation,
CMR, and OR MATLABTM VirtuosoTM schematic editor
Symbolic analyser Small-signal perf. metrics Performance validation

TM e.g. unity-gain freq., DC gain, Cost-function generator
Analog Insydes phase margin, and PSRR Circuit simulator
User-specified perf. metrics Circuit specification

e.g. time-domain properties, Specification on properties like
transistor matching unity-gain frequency, phase margin
Device Size Optimization

67
The Design Platform
In order to assure a well formulated optimization problem the optimization

parameters are scaled to have the same order of magnitude. The scaling is
straightforward since the parameters are constrained, by physical limitations, to
be within a certain range. The transistor width may, for example, vary between a
few µm up to a few mm while a poly-poly capacitor is in the range of a half pF
up to about a hundred pF.
In order to obtain feasible circuit solutions the optimization parameters are
restricted to be within a certain range. The designer may, however, change these
bounds in order to restrict or expand the search space.
4.3 Derivation of Performance Metrics and Con-

straints
When a netlist is entered, the automated setup of the optimization problem may
commence. The setup is performed by several tools and is one of the most
important parts of the design platform.
The netlist parser is used to derive constraints and large signal performance met-
rics. Further, the parser creates the input to the symbolic analyzer used to derive
small-signal performance metrics. Also, some time-domain performance metrics
are derived. The automatically derived circuit properties are:
Constraints
z KCL requirements
z Device operating regions
Large-Signal Metrics
z Common-mode range
z Output range
Small-Signal Metrics
z DC gain
z Phase margin
z Unity-gain frequency
z Positive and negative power supply rejection ratio (pPSRR, nPSRR)
z Common-mode rejection ratio (CMRR)
z Output noise spectral density
z Poles and zeros
Nonlinear Metrics
z Output and input intercept points
68
Derivation of Performance Metrics and Constraints
Time-Domain Metrics
z Linear settling time
z Linear overshot
Other Performance Metrics

z Chip area
z Power consumption
4.3.1 Constraints
Two types of constraints are derived automatically. First, the branch currents are
constrained so that KCL is met in all electrical nodes. This is a fundamental
requirement that must be met in order for the circuit to be realizable. Secondly,
the operating regions of the transistors are constrained in order to ensure proper
operation of the circuit. Since our currently used optimization method support
the use of both constraints and cost functions, we have chosen to formulate these
properties as constraints.
In analog circuits, such as operational amplifiers, transistors are typically operat-
ing in the saturated region. Thus, this is the default constraint used. There are,
however, other applications where the transistor may be used as, e.g., a voltage
controlled resistor instead. Then, other operating regions might be specified by
the designer. It is, also, possible to not constrain the operation region of the tran-
sistors.
In our approach, we use a relaxed DC formulation, i.e., we do not require a feasi-
ble DC solution in each iteration. Instead we include the KCL requirements as
additional constraints during the optimization. This implies that most points vis-
ited by the optimizer will not correspond to realizable circuits. In this way the
costly process of solving the DC equations for the circuit in each iteration is
avoided.
In order to find a DC operation point, each transistor is modelled as a black box.
Given the node voltages V G , V S , V D , and V B along with the width and length of
the transistor, the drain current, I D , the threshold voltage, V TH , and the saturation
voltage, V DSAT is computed. The actual formulas used depend on the device
model, see Sec. 4.7.
The circuit topology itself introduces constraints on the node voltages and
branch currents. For example, in Fig. 4.3 the voltages at the drain of transistor
M1 and M2 must be equal. Furthermore, in every node, KCL must be met. In the
circuit shown in Fig. 4.3, the current going out of M1 must be the same as the
current going into M2. The constrains may therefore be formulated according to
69
The Design Platform
VS1
I D1
W1 / L1 M1
V G1 VB1
V D1 = V D2
I D2
W2 / L2 M2
V G2 V B2
VS2
Figure 4.3 A simple example of a relaxed DC formulation.
I D1 – I D2 – δ < 0 (4.1)
where δ ≥ 0 is used to set the accuracy.
Ideally δ is zero, however, to facilitate convergence, a small deviation in the
order of a few nA is acceptable for most applications considered here. The
parameter may be compared to setting the accuracy of a circuit simulator.
All of these constraints are automatically derived by the netlist parser by identi-
fying all interconnection networks in the circuit. A voltage parameter is assigned
to each of the nodes and a nodal analysis is performed to generated constraints
on the branch currents.
4.3.2 Large Signal Performance Metrics
Common-Mode Range and Output Range

The common-mode range (CMR) is defined as the range of the common-mode
level at which the circuit respond properly to differential input signals. The out-
put range (OR) is defined as the range in which the output signal can vary. In a
circuit simulator the CMR and OR may be found by time-domain simulations
using a suitable input signal.
In our case such an approach will be costly from a computational point of view.
At the expense of reduced accuracy, an alternative method similar to that used in
70
hand-calculations is used. We define the common-mode and output range as the

largest/smallest signal levels allowed while still remaining in the saturated oper-
ating region.
Expressions for the output range (OR) and the common-mode range (CMR) can
be found by performing a tree search on the netlist. The search is carried out
using a set of rules for traversing the netlist. These rules are shown in Table 4.1.
The empty cells in the table indicates that this transition is not allowed.
Potential decrease/increase
Direction of traversing Lower limitations Upper limitations
NMOS PMOS NMOS PMOS
Drain to source - VDSAT -VDSAT -
Gate to source -VT VT -VT VT
Source to drain VDSAT - - -VDSAT
Source to gate VT -VT VT -VT
Table 4.1 Rules for traversing the netlist.
To determine, for example, the minimum voltage at the output node of the cir-
cuit, the search starts at the lower supply voltage node and identifies all paths to
the output node. Also, the paths from each bias voltage source must be identi-
fied. Using the change of potential for each transitions in the path, expressions
for the minimum voltage is obtained.
There may be several paths connecting two nodes in the circuit. Therefore an
expression is generated for each path. During the circuit optimization all of these
expressions are evaluated in order to find the one that limits the swing. In order
to illustrate the method the simple circuit in Fig. 4.4 is used.
To determine the maximum voltage swing at the positive input node (Vin+) we
will compute all possible paths to the upper power supply voltage node (VDD)
according to Table 4.1.
Starting at VDD we go from source to drain of transistor M4. In order to reach the
input node we will have to go from drain to source of M1 and then from source to
gate of M1. Using this path the following upper limit on the input voltage swing
is obtained:
V DD – VDSAT4 – V DSAT1 + V T1 (4.2)
Continuing with the additional paths the following three expressions are derived
71
The Design Platform
VDD
M4 M3
V ou t
V in + M1 M2 V in -
V bia s M5
V SS
Figure 4.4 Single-ended differential amplifier.
V DD – V T4 – V DSAT1 + V T1
V DD – V T3 – V DSAT1 + V T1 (4.3)
V DD – V DSAT3 – V DSAT2 + V T1
Since the voltages depend on the design parameters, and the operating point, all
of the expressions must be evaluated in each design point. In order to determine
the voltage swing, the path causing the largest voltage drop must be considered.
All of the voltages given in Table 4.1 are computed at the DC operation point of
the circuit. In order to accurately measure the swing, the saturation and threshold
voltages for the transistors must be computed at the outer limits of their opera-
tion region. However, the circuits designed using the tool shows reasonable
agreement with simulation results.
4.3.3 Small-Signal Performance Metrics
Symbolic Analysis and Modified Nodal Analysis

In order to derive expressions for the small-signal performance metrics, a sym-
bolic analysis tool [16] can be used. These tools are capable of deriving the sym-
bolic equations used to characterize the behavior of a circuit. Starting from the
circuit netlist and a linearized model for the MOS transistor, the tool can be used
to, e.g., generate the transfer function from one electrical node to another.
72
In our case we use Analog Insydes [19] which is an add-on to Mathematica

[68]. The tool is used to setup the small signal-model of the circuit. The equa-
tions are derived using the modified nodal analysis (MNA) approach [66].
Using the MNA approach to represent the circuit equations instead of a fully
expanded form reduces the memory requirements. It can be shown that the mem-
ory requirements grow exponentially with the circuit size for the expanded form
[15].
Experimental results also show that the computational efficiency is better for the
MNA approach than using fully expanded expressions for large circuits. In the
conducted experiments, the breaking point is for circuits having more than 6
transistors. Thus, to handle large circuits, the method with fully expanded circuit
equations is not efficient.
It should be noted that there are methods of decreasing the size of the equations,
e.g., using nested forms instead of fully expanded representations. Further by
supplying a set of design points or providing information about the order of mag-
nitude for the design parameters in the expressions, some approximations may
be made. However, this requires a set of suitable design points, i.e., already sized
circuits and can not be considered in our case.
One possibility is to use design points in order to speed up the optimization by
first generating a set of sized circuits using a high-accuracy model. The design
parameters of these circuits can then be used to approximate the expressions by
neglecting small terms at the expense of decreased accuracy. If a sufficiently
large number of design point are taken over a range of performance specifica-
tions, such an approximation may be performed. This might reduce the optimiza-
tion time when a new performance specification are to be met.
In this work such methods have not been used since high accuracy is considered
to be one of the main issues. Analog Insydes, however, supports the approxima-
tion of the equations from a set of design points.
In our case, where amplifier circuits containing a limited number of transistors
are considered, the generation of the expressions is not a critical issue. However,
when the number of transistors increases, other techniques to generate the
expressions might have to be used. In [18], a hierarchical approach to generate
the design equations is presented. Using these type of approaches, large circuits
may be handled and the expressions may be approximated within reasonable
time. Thus, there exist methods for generating symbolic equations for large cir-
cuits.
The MNA is performed in a systematic way described in [66]. In the MNA the
circuit relations are represented by the following
73
The Design Platform
GX = Y (4.4)
where G is an n × n matrix determining the relation between the branch currents
and node voltages in the circuit, X, and the voltage and current sources, Y. Basi-
cally, Analog Insydes derive G, X and Y, from the circuit netlist. However, in
order to compute the node voltages and the branch currents in the circuit G, must
be inverted according to:
X = G –1 Y (4.5)
This matrix inversion, which is equivalent to solving a set of linear equations,
can not be performed symbolically for large circuits due to the limited memory
and computational resources. Instead the inversion is performed numerically in
each iteration.
In our case the number of rows and columns of G is determined by the number of
electrical nodes and voltage sources in the circuit according to
n = n voltagesources + n nodes (4.6)
The transfer functions between all nodes in the circuit may be derived from the
outcome of the MNA. This can be exploited in order to derive the small-signal
equations. In order to, e.g., derive the power supply rejection ratio the frequency
response from the positive (or negative) power supply voltage to the circuits out-
put may first be derived. In the next step the frequency response from the circuit
input to the output is computed. The resulting power supply rejection ratio is
obtained using (2.15) or (2.16). The procedure is similar for the common-mode
range.
Deriving Poles and Zeros

The location of the poles and zeros are extracted by utilizing the QZ-algorithm
[44] directly on the G. Using the poles and zeros the transfer function for the cir-
cuit may be written on the general form
 1 – ---- s   1 – ---- s  …  1 – ---- s
 z1   z2   z n
H ( s ) = K -------------------------------------------------------------------- (4.7)
 1 – ---- s-  1 – ---- s- …  1 – ----- s-
 p1   p2   p m
The poles and zeros of the transfer function control the frequency behavior of the
amplifier. In many cases, we want an amplifier that has only one dominant pole.
The influence of unwanted poles and zeros is reduced if they are well separated
from the dominant pole. Using the poles and zeros, such requirements can be
included in the overall cost function.
74
Unity-Gain Frequency, Phase Margin, and DC Gain

The gain, A0, may be obtained directly from the transfer function in (4.7) by
identifying that the gain is equal to K.
For computing the unity-gain frequency and phase margin, the phase response
and magnitude response are derived from the transfer function in (4.7). From the
magnitude response of an amplifier, it is clear that the unity-gain frequency is
dependent on the dominant pole. If only the dominant pole is taken into account,
the unity-gain frequency could be computed directly. Since the gain decreases
asymptotically with 20 dB per decade, the unity-gain frequency can be approxi-
mated by the following equation
ω u ≈ ω p1 A 0 (4.8)
By using the dominant pole and (4.8), the approximative location of the unity-
gain frequency may be found. However, due to the influence of higher-order
poles and zeros, this, equation is not accurate enough. The accuracy can be
improved by using, e.g., Newton-Raphson or a bisection method. In our case we
use the bisection method with the approximation in (4.8) as a starting point.
The phase margin is derived by taking the argument of the frequency response at
the unity-gain frequency. As a default the feedback factor is set to unity when
computing the phase margin.
Output Noise Spectral Density

Currently, expressions for the thermal and flicker noise in the MOS transistors
are computed according to the BSIM3v3 [10, 36] model. The frequency response
from each noise source to the output of the circuit is computed using the MNA
approach. The equivalent input and output noise can be computed from the fre-
quency response and the spectral density of the noise sources. Hence, the noise
spectral density at different frequencies or the total noise power over the fre-
quency range of interest can be obtained.
Currently, only the transistors are assigned an equivalent noise source, resistors
are assumed to be noise free. However, a noise model for these devices may eas-
ily be incorporate into the overall noise expressions.
4.3.4 Nonlinear Metrics

Computation of the distortion is performed using Volterra series [67]. Volterra
series provides an advantages over other methods such as harmonic balance [67],
since no iterations are required. The metrics generated are the input and output
intercept points, IIP2, IIP3, OIP2, OIP3. A drawback of Volterra series are that
only weakly nonlinear behavior can be analyzed. Also, our current implementa-
tion do not handle the influence of compression.
75
The Design Platform
4.3.5 Time-Domain Performance Metrics

Since the transfer function is available, it may be use to derive some time-
domain performance metrics. The step response for the circuit is computed by
multiplying the transfer function with the Laplace transform of the input signal.
A partial fraction expansion followed by an inverse Laplace transform is then
performed. From the step response we may derive expressions for linear settling
time and overshot.
These expressions give a good estimation of the time-domain properties for
small input signals. If large signals are applied, other circuit characteristics, such
as slew rate limitation, will effect the results. Currently, this is not handled by
our tool.
4.3.6 Other Performance Metrics

Power Consumption
An expression for the currents drawn from the power supply by the circuit can be
formulated by summing the currents flowing from the positive to the negative
power supply voltage nodes. This current may then be multiplied with the power
supply voltage in order to obtain the power consumption.
In practice, the current through all devices with one node connected to the nega-
tive power supply voltage is summed. For the example in Fig. 4.4 the power con-
sumption is computed as the current through M5 times the power supply voltage.
Chip Area
The circuit area is difficult to estimate accurately since it is dependent on the lay-
out style as well as matching properties and additional components such as guard
rings and interconnect. However, in order to include the area in the overall cost
function we estimated the required area by
2 Rc C 4C p
Area = L T ∑ W i + W R ---------- + -----c- + --------- ( 2C p – C c C a + 4C p2 ) (4.9)
R Ca C2
a
where Wi is the width of transistor i, R and C are the total value of all resistors
and capacitors in the circuit. Further, LT is the distance between the center of the
drain and source contacts of the transistor (this is not equal to the transistor chan-
nel length). WR and R are the width of the resistors and the resistivity per
square, respectively. Ca and Cp are the capacitance per unit area and the perime-
ter capacitance for the capacitor, respectively.
LT may be used to adjust the size of the transistor in an appropriate way to accu-
rately measure the area required for implementation. Additional contributions to
76
The Cost Function
the area associated with other devices, or the number of devices, may be added
by the designer.
4.4 The Cost Function

All modules for computing each of the performance metrics are saved as MAT-
LAB files. The tool also sets up the cost functions which is discussed below.
The choice of cost function has a major impact on the convergence of the optimi-
zation process. Here we select the overall cost function, Φ , as a weighted sum of
partial cost functions. This cost function has by experience proven to be efficient
and flexible [43].
Y spec, i Y opt, j
Φ = ∑ ki ⋅ log G  ---------------
Y opt, i  ∑ j
 + k ⋅ log G  --------------- +
 Y spec, j
i j
(4.10)
αm 
∑ log ( 1 + Ymin, l ⋅ αl ) + ∑ log  1 + ----------------
Y max, m
-
l m
where the weight function G is given by
 X – 1 if X > 1
G(X) =  e (4.11)
 1 if X ≤ 1
Yspec and Yopt are the specified and the current value of the performance metrics,
respectively.
The first sum in (4.10) is used for partial cost functions where Yspec should be
smaller than Yopt, i.e., a penalty is generated if Yopt is smaller than Yspec. The sec-
ond sum is used for the opposite case, i.e., when the partial cost function should
be smaller than the specified value.
In order to minimize one or several performance metrics, Ymin, the third sum in
(4.10) is used. Ymin must be formulated in such a way that it is larger or equal to
zero. In a similar way the fourth sum is used to maximize a set of performance
metrics, Ymax.
kn are scaling constants used to weight the importance of each term in the cost
functions. The constant α n is used to normalize the corresponding function so
that each term is of the same order of magnitude. An important property of the
cost function is that the penalty generated is normalized by the specified value. It
is therefore possible to compare performance metrics that differs by several
orders of magnitude. Furthermore, the cost function has continuous derivatives
and can be used with gradient-based optimization methods.
77
The Design Platform
The values of the scaling constants have been determined experimentally. To

acquire proper values for the weights, the same circuit has been evaluated using
a range of different weights. The experimental results show that the circuit is
fairly insensitive to the weights. Several topologies and specifications have been
successfully sized with the selected weights.
4.5 Optimization Method

The cost functions appearing in analog circuit design are nonlinear with many
local minima [33]. To find the global minima of this problem, optimization
methods such as simulated annealing, genetic algorithms, and combinations
thereof can be used. As apposed to classical optimization algorithms these meth-
ods have been specifically developed in order to handle nonlinear optimization
problems. It is, however, possible to use gradient-based optimization methods on
nonlinear cost functions by initiating the optimization parameters in several dif-
ferent starting points.
The simulated annealing algorithms [34] is often the optimization technique cho-
sen when addressing device size optimization due to its global convergence abil-
ities. The method is capable of handling both continuous and discrete
optimization parameters which is an advantage in the case of device sizing since,
e.g., the width and length of the transistor are quantized by the minimum grid.
The drawback of the method is that it may be difficult to find an appropriate
cooling scheme that fits the optimization problem in question. Also, the termina-
tion criterion is of importance. This leads to that the method is not, in practical
implementations, guaranteed to find the global optimum [26].
Genetic algorithms [27] is another class of global optimization algorithms that
has gained much attention in recent years. The idea of these methods are to
mimic the process of evolutionary selection found in nature. Using a starting
population of initial trial solutions, the methods uses mutation to avoid getting
stuck in a local minima and converge towards the global optimum. In practice,
the methods suffers from slow convergence as well as problems with choosing
an appropriate selection criterion, population size, and chromosome encoding
[7].
Some design systems combine these methods in order to increase their effi-
ciency. Examples of such approaches include the use of a simulated annealing
optimization algorithm to find a suitable starting point for a gradient-based
method [52]. Another example is to use genetic evolution in combination with
simulated annealing [33].
In the present version of our tool the optimization engine uses a sequential qua-
dratic programming (SQP) algorithm [46]. Due to the nonconvex nature of our
78
Distributing the Optimization Tasks
optimization problem this algorithm do not guarantee to find the optimal solu-
tion. However, by initiating the optimization with different starting points, the
algorithm can be used to obtain good solutions. At the end of the optimization
phase, the best solution, i.e., the solution with the smallest value of the cost func-
tion, is chosen.
Experimental results show that the SQP algorithm performs well. An acceptable
amount of the starting points result in good solutions while the optimization time
is kept reasonably short. Also, as discussed in the next section, it is easy to dis-
tribute the optimization tasks onto a cluster of workstations.
Since the SQP algorithm can not handle discrete parameters, the optimization is
carried out using continuous parameters. When the optimization engine arrives
at a solution, the device sizes must therefor be rounded to the nearest value that
comply with the grid spacing. If required, the device sizes can be fixed to these
values and a second optimization run performed.
The cost function used in our approach is suitable to be used together with, e.g.,
a simulated annealing optimization algorithm and our intention is to try other
optimization algorithms as well. In order to use the simulated annealing algo-
rithm the cost function must be modified to include the constraints as well.
Only preliminary runs using simulated annealing have been performed. The
algorithm used is the adaptive simulated annealing algorithm [30]. Since the
cooling scheme have not been optimized, long optimization times have been
obtained so far.
4.6 Distributing the Optimization Tasks

To decrease the optimization times, the tasks may be distributed onto a cluster of
workstations. As shown in Fig. 4.5 the master distributes the optimization tasks
onto the cluster. Each of the workstations evaluates different starting points and
report back their results to the master. The master stores the result in a simple
database. From this database the best solution may later on be retrieved.
The communication is done through the standard TCP/IP protocol which allows
distributing the task over a large network of workstations. The cluster have been
successfully tested with about 70 computers using the UNIX, Linux, and Win-
dows operating systems.
Distributing the optimization tasks is important when handling large circuits
where the time to evaluate each starting point might be in the order of 30-40
minutes. Since the computational capacity scales linearly with the number of
workstations, the distribution offers a significant speed-up. The performance
degradation due to the overhead required to manage the cluster is negligible.
79
The Design Platform
Master
: :: :
Workstations
Figure 4.5 The master-slave configuration used for distributed optimization.
4.7 Device Models

The device model is included as an exchangeable module in our tool. It is there-
fore easy to replace the currently used BSIM3v3 model [10, 36] with some other
device models such as the EKV [14] or Phillips MOS level 9 [64].
As discussed in Sec. 4.3.1, the transistor is modelled as a black box with four
voltage terminals. Based on the voltages at these terminals, the drain current
trough the transistor (ID), the threshold voltage (VTH), and the saturation voltage
(VDSAT) as well as the admittances and capacitances of the transistor are com-
puted using the full accuracy of the BSIM3v3 model.
For the small-signal parameters, two models have been used in this work, the full
BSIM3v3 model and a simplified version of the same. The main reason with the
simplified model is that we did not get the full model to work completely in the
beginning of this work. Thus, in all of the published work related to this project
the simplified model have been used. However, the current version includes the
more accurate model.
The simplified model is shown in Fig. 4.6. In this, the number of parasitic capac-
itors has been reduced compared to the full BSIM3v3 model. When choosing
which parasitic capacitors to include in the model, small capacitors have been
removed. For example, the capacitor Cds is ignored since it is small compared to
the other capacitors.
80
Device Models
C dg
Gate Drain
C db
C gs g m V gs g mbs V bs g ds
C sb
Source Bulk
Figure 4.6 Simplified small-signal model for a MOS transistor.
To compute the transconductance, gm , the g mbs , and the output conductance, g ds ,

the full BSIM3v3 model has been used. The parasitic capacitances are modelled
by adjusting a polynomial in a least-square sense to the corresponding parasitics
in the BSIM3v3 model.
The accuracy of the simplified model is acceptable at moderate frequencies, but
at high frequencies the accuracy is reduced since the effect of the neglected
capacitors and the modeling error will be more significant.
In order to accurately predict the performance of the circuits at high frequencies
the accuracy must be increased. For this reason the full BSIM3v3 small-signal
transistor model in Fig. 4.7 is used. In this case all parameters, both small-signal
and large-signal parameters, are included and computed according to the
BSIM3v3 model. Using this model, the accuracy is comparable to HSPICE
[28] and Spectre [9] simulations.
The size of the MNA is also affected by the choice of model. From (4.6), the size
of the MNA can be computed. For the full BSIM3v3 model, the formula
becomes
n = n voltagesources + n nodes + 2n transistors (4.12)
due to the internal nodes introduced by the extra internal nodes, dx and sx, in the
transistor model.
For the circuit in Fig. 4.4 the size of the MNA matrix becomes 13x13 using the
simplified model since the number of voltage sources is 5 and the circuit has 8
nodes. The corresponding size for the full BSIM3v3 model is 23x23. It is thus
clear that the size of the matrix increases faster for the full model. In this case the
matrix for the full model is more than 3 times the size of the simplified model.
This is costly both when considering the memory required to store and to com-
pute the inverse of G.
81
82
The Design Platform

Figure 4.7
Drain
the BSIM3v3 model.
An equivalent small-signal model for a MOS transistor modelled by
s ( C db V b + C dg V g + C dd V dx + C ds V sx ) s ( C bb Vb + C bd V dx + C bg V g + C bs V sx )
Rd
g db
dx Bulk
g m V gsx + gmbs V bsx g ds g bs
Gate sx
Rs
s ( C gb V b + C gd Vdx + C gg Vg + C gs Vsx ) s ( C sb V b + C sd V dx + C sg V g + C ss V sx )
Source
Device Models
Experimental results show that the overall loss in computational efficiency for
the high accuracy model is about 30% compared to the simplified model. Thus
the impact on the optimization speed is not a critical issue in these cases. Fur-
thermore, the size of the matrix is not a problem for circuits that have been
examined within this work, the largest tested circuit having about 60 transistors.
However, if for example a complete filter with several large operational amplifi-
ers are to be sized, this will of course become a problem.
Currently, all lumped devices, such as capacitors and resistors, are assumed to be
ideal. There are, however, no principle problems to changing these models in
order to incorporate a more detailed model for these devices.
The process parameters are stored as variables in MATLAB. A simple tool has
been implemented in order to automatically extract the process parameters from
a SPICE process parameter file. Updating the process parameters is thus done in
a few seconds.
83
The Design Platform
84
CHAPTER V
LAYOUT GENERATION AND
PARASITIC FEEDBACK
In this chapter the layout generation and the parasitic feedback tools are dis-
cussed. It should be noted that the work done on the layout generation is not
intended to be state-of-the-art. Instead the purpose of the layout generator is to
validate the principle of parasitic feedback. However, parts of the generator may
be reused, in future versions.
5.1 Layout Generation

The layout is generated using a template-based approach where each circuit
topology requires its own template. In the template several low-level building
blocks, such as differential pair transistors, resistors, and capacitors are placed
and connected as illustrated in Fig. 5.1. The low-level building blocks are gener-
ated using module generators that are general enough to be used in several tem-
plates. A floorplan is created by placing the building blocks and performing the
preliminary alignment. All wires are placed and related to the surroundings by
the template. In order to cover a large range of device sizes, several templates
may have to be used for the same circuit topology.
In order to produce a compact layout and improve the device matching, the tran-
sistors are divided into several unit-size transistors (fingers). Other components
such as capacitors and resistors can also be divided into several smaller devices
connected in series or parallel. The number of unit-size devices can be used to
control the area and/or the form factor of the circuit. An optimization routine is
85
Layout Generation and Parasitic Feedback
Template Module generators

pcDefinePCell(list(ddGetObj("pcells") "matched_transistors" "layout") /* /*
((trans_w float 30.0) The file twotransistor_procedure_file.il must be loaded before the pcell The file twotransistor_procedure_file.il must be loaded before the pcell
(unit_l float 0.5) is used for the first time. is used for the first time.
(size_ver int 1)
(trans_type string "nmos") loadi("/home/tde/emilh/cadence/skill/pcell/matched_transistors/twotransistor.il") loadi("/home/tde/emilh/cadence/skill/pcell/matched_transistors/twotransistor.il")
twotransistor(180.6 0.7 12 "nmos" "MET2") twotransistor(180.6 0.7 12 "nmos" "MET2")
) Wires of interest: Wires of interest:
let(( Common node: commonnodeMET2 Common node: commonnodeMET2
;parameters Drain right: drainrightMET2 Drain right: drainrightMET2
cv Drain left: drainleftMET2 Drain left: drainleftMET2
desLib Gate left: gateleftMET2 Gate left: gateleftMET2
cover_w */ */
pdiff_poly_dist pcDefinePCell(list(ddGetObj("pcells") "twotransistor" "layout") list("l" "string" sprintf(nil "%nu" l)) pcDefinePCell(list(ddGetObj("pcells") "twotransistor" "layout")
pdiff_m1_dist list("w" "string" sprintf(nil "%nu" fingerwidth)) ((w float 180.6)
pdiff_m2_dist list("wtot" "string" sprintf(nil "%nu" w)) (l float 0.7)
low_pdiff_ypos list("ng" "string" sprintf(nil "%n" fingers)) (fingers int 12)
high_pdiff_ypos list("jg" "string" "no") (type string "nmos")
metal1 if(type == "pmos" then (common_node_layer "MET2")
metal2 cmosId = dbOpenCellViewByType( "PRIMLIB" "pmos4" "layout" "" "r" ) )
poly topdistancemiddle = 4.6 cv = pcCellView
nwell sidedistancegatecontacts = 0.35 ; length between the transistor side to the mt
pimp else if(type == "pmos" then
nimp cmosId = dbOpenCellViewByType( "PRIMLIB" "nmos4" "layout" "" "r" ) cmosId = dbOpenCellViewByType( "PRIMLIB" "pmos4" "layout" "" "r" )
M2_M1 topdistancemiddle = 2.8 topdistancemiddle = 4.6
pmos4 sidedistancegatecontacts = -0.45 ; sidedistancegatecontacts = 0.35 ; length between the transistor side to the mt
nmos4 gatedrainspace = 0.7+0.45*2 ; The drain vertical MET2 l. else
no_pairs gatespace = 0.7+0.45* cmosId = dbOpenCellViewByType( "PRIMLIB" "nmos4" "layout" "" "r" )
fingerwidth = w/fingers topdistancemiddle = 2.8
T1 = dbCreateParamInst(cv sidedistancegatecontacts = -0.45 ; length between the transistor side to the m)
) cmosId gatedrainspace = 0.7+0.45*2 ; The space between the gate and the drain vertical MET2 l.
"T1" gatespace = 0.7+0.45*2
;; Parameter definitions 0:0 fingerwidth = w/fingers
pdiff_poly_dist = 2*0.4 "R0" T1 = dbCreateParamInst(cv
pdiff_m1_dist = 2.0 1 cmosId
pdiff_m2_dist = 4.0 list( "T1"
cover_w = 0.8 list("l" "string" sprintf(nil "%nu" l)) 0:0
cCenterXlist = list() list("w" "string" sprintf(nil "%nu" fingerwidth)) "R0"
list("wtot" "string" sprintf(nil "%nu" w)) 1
no_pairs = (size_ver*2) list("ng" "string" sprintf(nil "%n" fingers)) list(
unit_w = trans_w/no_pairs list("jg" "string" "no") list("l" "string" sprintf(nil "%nu" l))
list("jd" "boolean" nil) list("w" "string" sprintf(nil "%nu" fingerwidth))
low_pdiff_ypos = 0 list("js" "boolean" nil) list("wtot" "string" sprintf(nil "%nu" w))
high_pdiff_ypos = low_pdiff_ypos + unit_w list("ng" "string" sprintf(nil "%n" fingers))
list("jg" "string" "no")
list("jd" "boolean" nil)
list("js" "boolean" nil)
Layout
Figure 5.1 Hierarchical view of the template-based layout generator.
used to determine the appropriate number of units to achieve either the minimal
area or some desirable form factor. From a matching point of view a quadratic
layout should be used since the device variations are proportional to the squared
distance between two objects in a first-order approximation [50].
5.1.1 Building Blocks

Some basic building blocks that are common in analog circuit design have been
implemented in the AMS 0.35 µm process. The blocks are realized as parame-
trized cells (Pcells) within the Virtuoso design framework. In a Pcell the layout is
defined using SKILL [59]. Hence, it is possible to use variables and conditions
in order to change the properties of a specific building block. In this way the
block can be made general enough to be used in several templates.
In Fig. 5.2 the output from a module generator for matched transistors is shown.
Here two transistors are matched. The generator supports matching of more than
two transistors as well. A set of input variables are used to, e.g., set the size of
the unit-size transistors. The connection of the unit-size devices is determined by
other input parameters in order to allow, e.g., a common-centroid placement and/
or a specific ratio between the devices. A guard ring may be placed around the
86
Layout Generation
(a)
(b)
Figure 5.2 The layout of two different differential pair transistors are shown.
In (a) the a guard ring is applied while it is disabled in (b).
87
Figure 5.3 The layout shows two matched capacitors. The covering shield is removed
for the sake of visibility.
transistor and/or as a covering metal layer on top. Several other properties, such
as the width of the internal wiring are also adjustable.
Another example of a parametrized block is shown in Fig. 5.3. This Pcell gener-
ates an array of matched capacitors. The size and the number of unit-size capaci-
tors in the array may be chosen arbitrary in order to cover a large range of
capacitive values. The interconnect network might be chosen to obtain a com-
mon centroid solution. Further an arbitrary number of capacitors may be
matched although the internal busses might become a problem if the number of
capacitors are large.
Dummy capacitors may be placed around the array along with an optional guard
ring. A covering shield on top of the array can be applied. All wires widths are
adjustable in order to handle different requirements on the current density.
The technology dependent parameters, such as minimum spacing rules, are
fetched directly from the process technology file by the module generators.
However, porting a Pcell to a completely new technology may require some
88
Layout Generation
tweaking and adjustments. The time required is dependent on the extent of these
adjustments.
Generally, the low-level building blocks in analog circuits, i.e., transistors, resis-
tors and capacitors, do not change dramatically from one process to the next. The
basic geometries and the layers are similar although the size have shrunk. If only
minor scaling adjustments are required a block may be ported to a new technol-
ogy in a few hours.
The time required to create a Pcell may, however, occupy a skilled programmer
for a few days up to weeks depending on the complexity and the generality of the
block. Thus, there is a large initial cost involved in building a library of parame-
terized blocks. However, if only basic building blocks, like those discussed
above, are considered, the level of reuse is high since they are likely to be found
in most analog circuits. When the module generator is completed the building
block may be generated in seconds.
5.1.2 Templates
Templates are implemented similarly to building blocks, using SKILL. The tem-
plate determines the relative placement of each building block as well as how to
perform the interconnect.
When a the template is evaluated for a specific set of device sizes, fingers and so
on, it first calls all of the module generators to generate the low-level building
blocks. In the next step the blocks are placed and interconnected according to the
template. In this way the template may be reused to generate layouts for several
different sets of device sizes.
The layout for a folded cascode OTA generated from a template is shown in
Fig. 5.4. In Fig. 5.7 the OTA is shown, evaluated with a different set of device
sizes. In this template eight building blocks are used, seven transistor blocks and
one capacitor block.
In order to minimize the circuit area or force it to have a specific form factor a
simple optimization step is applied before the layout is generated. During the
optimization step the shape of each building block is determined by changing the
the number of fingers for each transistor.
Formulas for the width and length of each block as a function of the unit-size
transistor and the number of fingers have been manually derived in order to com-
pute the size of each block during the optimization. Further, the layout is divided
into vertical and horizontal slices. The vertical slices are shown in Fig. 5.4. The
width of each slice is determined by the largest block inside.
89
Figure 5.4 Template-based layout for a folded cascode OTA.
The slices are placed adjacent to each other. Hence, the sum of the slice widths
determines the total width of the circuit. The height of the block is determined in
a similar manner using horizontal slices.
The benefits of the template-based method is that it provides a fast and reliable
(as long as the device sizes are within a reasonable range) way of generating a
layout. There are, however, several disadvantages with this approach. Firstly,
creating a new template is a time consuming task. Secondly, the range of device
sizes that may be used with a single template is limited. To achieve a dense lay-
90
Parasitics Feedback
Parasitics
Device size optimization Parasitic extraction
Iterated until
the impact of
parasitics is
small
Device sizes Circuit layout
Layout generation
Figure 5.5 The parasitic feedback loop
out over a large range of device sizes several templates must be used. Thirdly,
even though a template may be adjusted to work with a new process technology
it requires additional work, especially when several templates are to be con-
verted. In this work the template-based layout generator is used in order to illus-
trate the concept of parasitic feedback.
5.2 Parasitics Feedback

The concept of parasitic feedback is shown in Fig. 5.5. Here the layout parasit-
ics are back annotated into the optimization loop in order to compensate for lay-
out induced effects.
As described in the previous chapter the device sizing tool is used to size the cir-
cuit in order to meet the performance specification. In the next step the device
sizes are exported to the layout generator. By using the template described in the
previous section a layout is generated.
The Diva parasitic extraction tool [9] is used to extract the parasitics in the lay-
out. When the parasitic elements are determined they are fed back to the sche-
matic view. In practice this is done by adding a set of ideal components, capaci-
tors and resistors, with fixed values to the schematic.
In order to include the impact of the parasitic elements all performance metrics
are automatically regenerated from the updated schematic. This is done follow-
ing the procedure described in chapter 4.
Due to the parasitic loads introduced in the layout phase the circuit might fail to
meet the performance specification using the device sizes from the initial device
sizing procedure. Therefore, the device sizing tool is used to resize the circuit in
91
order to meet the performance specification. When resizing the circuit the opti-
mization parameters are initiated close to the previous solution.
Now the loop is restarted by generating the layout for the new device sizes. Since
the sizes have changed from the previous iteration a new set of layout parasitics
are extracted. As in the previous iteration the impact of these parasitics on the
circuit performance might cause the circuit to violate the performance specifica-
tion.
The process is therefore repeated with the updated values of the parasitic. No
regeneration of the symbolic performance equations are required in the later iter-
ations since the symbolic expressions for the parasitics have already been
included. If no significant changes are made to the layout the difference in para-
sitic load will be smaller than in the first iteration. In the following iteration, the
changes in the parasitics are smaller then in the previous and the required adjust-
ment of the device sizes are also smaller. Hence, repeating this process for a few
iterations will result in a reduced deviation from the performance specification.
When the difference in performance, from one iteration to the next, is smaller
than a user-specified threshold value the feedback loop is terminated.
The current version of the program only take into account the interconnect para-
sitics. There are, however, other parasitic effects associated with the drain and
source area of the transistor. Even though they are taken into account in the tran-
sistor model itself the exact values of these parasitics are not determined until the
layout phase is completed. The reason is that the layout style used will affect the
size of these areas. For example, if two transistors have a common drain the tran-
sistor may share the same drain area in the layout. This yields that the total para-
sitic load caused by the drain areas will be half of that implied by the schematic
description of the circuit.
Taking these effects into account may be important in order to fully handle the
effect of layout dependent parasitics.
5.2.1 Convergence Issues

If large changes to the parasitic load occurs in each iteration the optimization
may not converge. It is therefore important that the layout, and thereby the para-
sites, are subject to small changes between each iteration step. Generating a lay-
out that significantly differ from that used in the previous iteration step should be
avoided.
In order to accomplish this the device sizes are initiated in a point close the solu-
tion from the previous iteration when reoptimizing the circuit. That is, the
devices size variations will be kept small and, thus, the changes in the intercon-
nect parasitics.
92
Design Example
In order to further decrease the effect of layout induced changes the number of
fingers for each transistor may have to be fixed. It is possible to have a case
where the number of fingers for one block changes from one iteration to the next
and then back again, preventing the feedback loop from converging.
If a template-based solution, like that presented here, is used to generate the lay-
out, the regularity of the structure ensures that the change of parasitic load in
each node is kept at a low level for small changes in the device sizes. However, if
a more advanced place and route strategy is used where, e.g., global optimization
methods are used to generate the layout, large changes in the layout can occur.
Hence, the changes to the interconnect wire lengths might be large and thereby
the change to the parasitic loads. In order to prevent this the layout from the pre-
vious iteration must be used as a starting point. Also, the deviation from that lay-
out must be made small for small changes of the device sizes.
It should be noted that the parasitic feedback loop have not been carefully inves-
tigated yet. So far the results presented here are based on a limited number of
generations using only one template. No criterion to ensure convergence have
been derived. However, its is clear that the impact of the layout parasitics is an
important source of error to take into account when designing the circuits. Thus,
this will be an important part to cover more in depth in the future.
5.3 Design Example

To illustrate the parasitic feedback approach, the single-ended folded-cascode
operational amplifier shown in Fig. 5.6 is used as a design example. The load
capacitor CL is set to 5 pF. The power supply voltage of the circuit is 3.3 V and
the channel length, L, is fixed to 0.7 µm for all transistors. The circuit has been
designed in the AMS 0.35 µm CMOS process. The bias voltages, V bias, k , are
generated through proper biasing schemes, e.g., current mirrors with a reference
current. These biasing networks are not included in this design example.
No initial assumptions about the transistor widths other than the matching of cer-
tain transistors have been made. A lower and an upper bound on the transistor
widths of 20 µm and 500 µm, respectively, are applied in order to restrict the
parameter space.
The initial values of the node voltages are randomly chosen between the power
supply voltages. However, respect is taken to the limitations implied by the cir-
cuit. For example the voltage at the source of transistor M9 must be lower than
its drain voltage. The initial value of the compensation capacitor, Ccomp, in each
optimization is randomly selected between 3 pF and 7 pF, while it is bounded to
be in the range of 0 nF to 1 nF.
93
V b ia s1
M3 M4
V b ia s5
V b ia s2 V b ia s2 M 13
M6 M1 M2 M7 Vo u t
V in p V in n CL
M 12
V b ia s3
M8 M9
C co m p
M5 V b ia s4
M 10 M 11
Figure 5.6 A folded-cascode operational amplifier.
5.3.1 Optimization results

The objective of the overall optimization is to minimize the power consumption
while maintaining the performance specification. In the first row of Table 5.1 the
circuit specification is given. Only a few of the available performance metrics
used are shown in the table.
We make no initial guess for the sizes of the interconnect parasitics. They are set
to zero in the first iteration. The resulting performance from the device size opti-
mization is shown in the second row. It is clear that the optimization program
have succeeded in finding a circuit that meats the performance goals.
In the next step a layout is generated and the parasitics are extracted. Now the
parasitic loads, previously set to zero, are included when computing the circuit
performance. The result is shown on the third row of Table 5.1. Thus, when tak-
ing into account the interconnect parasitics the performance decreases and the
specification is no longer met.
The device size optimizer is once again called, however, this time the parasitic
values acquired in the first iteration is used. The resulting performance after the
94
Design Example
Performance A0 fu Phase PSRRp PSRRn CMRR Power

metrics [dB] [MHz] margin [dB] [dB] [dB] [mW]
Specification ≥ 70 ≥ 75 ≥ 60 ≥ 60 ≥ 60 ≥ 60 min.
Iteration 1 70.00 75.00 60.00 69.16 62.56 116.9 7.03
no parasitics
Iteration 1 70.00 74.13 59.55 69.16 62.55 116.9 7.03
with parasitics
Iteration 2 70.00 74.99 59.98 69.55 63.78 118.5 7.53
with parasitics
Iteration 3 70.00 75.00 60.00 69.56 63.92 118.7 7.54
with parasitics
Iteration 4 70.00 75.00 60.00 69.56 64.66 119.0 7.54
with parasitics
Iteration 4 70.00 74.50 61.19 69.59 64.67 119.0 7.54
simulated
Table 5.1 The specification, optimization and simulation (Spectre) results for the Folded-
Cascode OTA.
second iteration (row four) shows an improved performance. This is due to the
fact that only moderate changes are required for the device sizes, and, thus, the
wire lengths, in order to restore the performance. Hence, the difference in the
size of the parasitics is small.
As this process continues, in iteration three and four, the circuit performance
converges to the specification. At iteration four, the change in the cost function,
compared to the previous iteration, is less than the user-specified threshold
value. In this case the threshold value is related to the cost function used in the
device sizing. It is, however, possible to use a different cost function in the para-
sitic feedback loop.
When verifying the result by simulating the final circuit in the Spectre [9] simu-
lator (row seven) the result deviates from that reported by the device sizing tool
(row six). This is due to the simplified transistor model (see Sec. 4.7) used in this
example.
As can be seen in Table 5.1 the impact of the interconnect parasitics are rela-
tively moderate for most performance metrics. However, these effects will have
a larger influence on the circuit performance at higher frequencies and for cir-
cuits with smaller load capacitor. In this case the power consumption must be
95
increases by approximately 7% in order to meet the specification when the lay-

out parasitics are taken into account.
To ensure good solutions the optimization routine is initiated in 100 random
starting points (all taken in a near vicinity of the previous solution) at each itera-
tion, resulting in 100 different circuits. The layout generation and parasitic
extraction is performed for the best the of these circuit, i.e., the one with the low-
est power consumption. In this case, 90% of the generated circuits had a power
consumption within a 1% range of the best solution. Furthermore, the time
required for each solution is less than five minutes using an AMD Athlon XP
1800+ PC.
Figure 5.7 Generated circuit layout of the amplifier.
96
Concluding Remarks
Iteration
Design parameter 1 2 3 4 unit

W1 & W2 81.7 91.6 92.6 92.8 µm
W3 & W4 22.7 26.2 26.5 26.4 µm
W5 151.0 143.6 139.7 103.0 µm
W6 & W7 48.0 60.2 61.0 61.0 µm
W8 & W9 45.6 58.2 59.0 58.8 µm
W10 & W11 30.6 40.8 41.2 41.0 µm
W12 500.0 500.0 500.0 500.0 µm
W13 153.1 158.8 158.8 158.8 µm
CC 3.411 3.740 3.737 3.731 pF
Table 5.2 The device sizes yielding the lowest power consumption in each iteration.
The device sizes for each iteration is shown in Table 5.2. It is clear that the first
iteration results in the largest change of the device sizes. As the process contin-
ues the device sizes converges to the their final value at iteration 4. The width of
transistor M5 is changed from about 150 µm down to 103 µm in this process.
The performance of the circuit is, however, fairly insensitive to the width of M5
since the current through the transistor may be maintained by instead increasing
its bias voltage. All other transistor sizes must be increased in order to maintain
the performance when the parasitics are added. The layout of the circuit meeting
the performance specification is shown in Fig. 5.7.
5.4 Concluding Remarks

In this approach the parasitic loads are fixed during the device size optimization.
Continuously computing the values of the parasitics in each iteration is a better
way to address the problem. However, such an approach requires detailed mod-
els of the relation between device sizes and the parasitics or a complete layout
generation with extraction and parasitic feedback for each evaluation of the cost
function. Also, the area/form factor optimization must be performed in each iter-
ation of the device size optimization loop. Even though it is possible to create
such a model for a template-based approach performing the area optimization
will increase the run time significantly.
97
Furthermore, deriving such models for several templates will be a time consum-
ing task. However, by including the layout generation and extraction of the para-
sitics within the optimization loop better results might be achieved.
It is clear from the design example that the parasitics have a degrading effect on
the performance of the circuit. Thus taking into account and compensating for
the parasitics is an important part of the analog design flow.
One fundamental property of our design tool enabling the possibility to perform
the parasitic feedback is the ability to directly, from a schematic description of
the circuit, generate the design equations in short time. Since the equations must
be regenerated at least once (possible several times if more drastic changes in the
layout occurs) this must be performed swiftly.
Also, the first-order approximation of the influence of parasitics used in the
direct performance driven layout generation is not enough for two reasons. First,
there is no guarantee that the layout will meet the performance goals even
though the impact of parasitics on the circuit performance is considered during
the generation. Since the device sizes are fixed during the layout generation large
parasitics can not be compensated for, only reduced. Secondly, the performance
metrics may not be accurately determined by a first-order approximation, thus
the models used during the performance driven layout generation may not be
valid if large changes in the layout parasitics occurs.
In the purposed approach the feedback loop enables us to adjust the device sizes
in order to compensate for the performance degradation during the layout gener-
ation. This, in combination with a (direct) performance driven approach, have
the potential of generating high quality circuit layouts.
98
CHAPTER VI
EXPLORATION AND TRADE-OFFS IN ANALOG
AMPLIFIER DESIGN
As discussed earlier the nonlinear relations between design parameters and cir-
cuit performance in analog circuits are a major obstacle for the designer. In the
previous chapters the design platform of automated analog design have been pre-
sented. The tool render the possibility to design an analog circuits in short time.
When designing a circuit we explore a set of local minima for a particular speci-
fication. In this sense we obtain a range in which we may chose the design
parameters in order to meet the performance specification.
However, no information about the range in which we may select our perfor-
mance metrics is obtained. What are the physical limits of a topology? What is
the cost of increasing one performance metric? How does one topology perform
in comparison to other topologies?
Questions like these are complicated to answer. Simple hand calculations might
give some guidelines. However, the exact effect of increasing/decreasing a spe-
cific performance metric is difficult to anticipate. We might, e.g., assume that the
power consumption will increase when the unity-gain frequency increases. It is,
however, difficult to know the exact increase in terms of Watts. Also, the power
consumption might not be dependent on the unity-gain frequency for a specific
frequency range. In that case the unity-gain frequency may be increased for free,
with respect to the power consumption.
In this chapter we address these questions. We will show how the design tool can
be used to find limitations and possible trade-offs in analog amplifier design.
99
Exploration and Trade-Offs in Analog Amplifier Design
Previous work focused on decreasing the time required to compute the possible
trade-offs at the expense of the accuracy [20, 54]. Another approach, [60], uti-
lizes the multi-objective formulation of the optimization problem in conjunction
with a SPICE like simulator inside the optimization loop. The accuracy of the
results is high, but the use of a SPICE like simulator decreases the computational
efficiency. Hence, a thorough design space exploration is too time consuming.
Further, in simulation-based and equation-based device sizing tools that uses a
DC-solver in its optimization loop a physical circuit solution is obtained in each
iteration. Only the final solution is an optimum for the target specification, all
intermediate solutions are, however, part of the design space, even though they
are no good solutions.
In our case the intermediate solutions are most certainly not physically feasible
since we us a relaxed DC formulation. We may therefore only use the final solu-
tion when exploring the design space. However, this solution is a local minimum
to that specific optimization problem.
Here our emphasis is not to identifying the complete design space, instead we
focus on finding parts of the design space with good solutions. That is, for each
specification we are only interested in the best solution. By the best solution we
mean the local minima, yielding the smallest cost, that the tool is able to find for
a limited set of starting points.
By looking at the best solution, for a set of circuit specifications, the trade-off
between different performance metrics may be obtained. In this chapter the
design tool is used to find trade-offs for a selected set of performance metrics.
6.1 The Design Space Exploration Tool

The design space exploration tool is used to explore the technology limits of
amplifier topologies as well as being able to visualize trade-offs. A simple exam-
ple will be used to illustrate the technique.
Assume that the goal is to visualize the relation between the unity-gain fre-
quency and the power consumption for a specific topology and process technol-
ogy. First the device sizing tool will generate the circuit equations from the
circuit topology and setup the optimization problem as described in chapter 4.
However, in this case the specification is not fixed with respect to the unity-gain
frequency. Instead a set of values for this performance metric is used, e.g., 110
MHz to 130 MHz in steps of 10 MHz. All other performance requirements are
kept fixed.
In order to find the minimum power consumption at 110 MHz the specification
is fixed to that frequency. When fixing the unity-gain frequency we will get the
100
The Design Space Exploration Tool
120MHz
Cost function
110MHz
Design parameters
Figure 6.1 Cost function for two different specifications.
6
Power consumption [mW]
3
Trade-off curve
2
1
100 110 120 130 140
Unity−gain frequency [MHz]
Figure 6.2 Comparison of local minima and the trade-off curve.
cost function indicated in Fig. 6.1. For a unity-gain frequency of 120 MHz we
will get a different cost function. In this case the cost function have been repre-
sented by a two dimensional graph, however, in reality this is an n-dimensional
space.
The device sizing tool is used to find local minima for the different cost func-
tions, one in a turn. These may be used to visualize the design space according to
Fig. 6.2. Also, the best solutions at each point in the design space can be used to
plot the trade-off between the performance metrics.
The number of performance metrics that can be swept are only limited by the
time required to get a sufficient number of sized circuits for each specification.
101
Visualization
12

10
Performance range 8
0
3.4
3.2 200
3 180
2.8 160
2.6 140
Supply voltage [V] 2.4 100
120
2.2 80
2 60 Unity−gain frequency [MHz]
Design space
exploration kernel
Device sizes & Specification &

performance objective
Workstation Workstation Workstation
Figure 6.3 Design space exploration platform.

In this way large parts of the design space can investigated. Further, sweeping
several performance metrics can be seem as a multi-objective optimization.
Also, the curves indicate the physical limitations of a topology. By gradually
increasing the specification and pushing the limits the tool will finally fail in
finding a feasible solution due to the limitations implied by the topology and the
process technology.
In order to reduce the time required to perform an extensive exploration of the
design space the optimization tasks are distributed onto several workstations
according to Fig. 6.3. The design space exploration kernel distributes the specifi-
cations to the workstations that carries out the optimization tasks. The resulting
performance and device sizes are exported back and stored in a database. From
this database the trade-offs are visualized.
In order to illustrate the usefulness of the design space exploration tool a design
case in which three different amplifier topologies are compared is given.
102
Design Case
6.2 Design Case

In this design case three operational transconductance amplifiers (OTA) to be
used as a buffer in an 8-bit sample-and-hold circuit with a 20-MHz sample fre-
quency are evaluated. The goal is to identify possible trade-offs and select the
most appropriate circuit for the task.
The circuit topologies for the three OTAs are shown in Fig. 6.4 (two-stage),
Fig. 6.5 (folded-cascode), and Fig. 6.6 (current-mirror).
VDD
M2b M2a
M4
Cc Rc
Vout
Vin- M1b M1a Vin+
CL
Vbias1 M3 Vbias2 M5
Figure 6.4 The schematic of the two-stage operational transconductance amplifier.
6.2.1 Performance Specification

In Table 6.1 the target specification for the OTAs has been compiled. For the
sake of simplicity, distortion and small-signal time-domain properties are not
included in the cost function, although it would be possible.
Since automatic derivation of expressions for slew rate is not yet available it has
been specified manually. For the OTAs, approximate expressions for the slew
rate are essentially the supply current over the compensation and/or load capaci-
tance according to (6.1)
 I d3 I d5  I d2 2I d7a
SR TS = min  -------, --------------------  , SR FC = -------------------
- , and SR CM = -------------------
- (6.1)
 CC C L + CC  C L + CC CL + C C
for the two-stage, folded-cascode, and current-mirror OTA, respectively. Further,

the currents through the transistors are computed at their operation points.
The area of the circuits is estimated by (4.9). In this case LT is selected to be 2,
i.e., the distance between the drain and source contacts is 2 µm.
103
VDD
Vbias4
M2b M2a
Vbias3 Vbias3
M3b Vin- M1b M1a Vin+ M3a
Vout
Vbias2
M4b M4a
Cc CL
Vbias1
Rc
M5b M5a
Figure 6.5 Folded-cascode operational transconductance amplifier.
VDD
M4b M3b M3a M4a
M2b M2a
M5b M5a
Vbias3
Vout
Vin- M1b M1a Vin+
Vbias2 Vbias2
M6b M6a Cc CL
Vbias1 M8
Rc
M7b M7a
Figure 6.6 Current-mirror operational transconductance amplifier.
104
Design Case
Performance metric Specification Unit

Load capacitance 5.0 pF
Unity-gain frequency > 100 MHz
Power supply voltage 3.3 V
PSRR > 70 dB
CMRR > 70 dB
Input swing [1.0, 2.0] V
Output swing [1.0, 2.0] V
DC gain > 70 dB
Slew rate > 100 V/µs
Phase margin > 60 degrees
Power consumption < 5.0 mW
Equivalent output noise @ 1kHz < 320 µV ⁄ Hz
Table 6.1 The performance specification for the OTAs.
6.2.2 Optimization Setup

The biasing of the amplifiers is performed using external current mirrors and
proper biasing schemes and is not part of the optimization problem. For the RC
stabilization network two optimization parameters are used. In order to decrease
the number of parameters the length of each transistor is fixed to twice the mini-
mum size, i.e., 0.7 µm. Hence, only the width of each transistor is used as an
optimization parameter.
Further, transistors sharing the same index, i.e., M1a and M1b, in Fig. 6.4 to
Fig. 6.6 are assumed to be matched. The input DC voltage of the amplifiers is
fixed to 1.5 V in all three cases. All other node voltages are treated as optimiza-
tion parameters. This leads to 13 optimization parameters for the two-stage OTA,
19 for the folded-cascode OTA, and 24 for the current-mirror OTA.
In order to generate symmetrical circuits, the ratio is set to unity for all matched
transistors. It should though be pointed out that the circuit area and the power
consumption of the current-mirror OTA can be decreased by using different cur-
rents in the left-most and right-most branches, by letting the mirror ratio between
M3b and M4b be unity and the ratio between M6b and M6a (M7b and M7a) be
equal to the ratio between M3a and M4a (M2a and M5a).
The design space is limited by constraining the design parameters within a range
of acceptable values. The transistor widths are therefore limited to be in the
105
range of 20 µm to 1000 µm. The size of the compensation network is constrained

by allowing a capacitor with values in the range of 0.5 pF to 1 nF while the resis-
tor should be in the range of 1 Ω to 1 MΩ. Further, all transistors are constrained
to operate in the saturation region.
Due to the nonlinear nature of the optimization problem, several different start-
ing points are required in order to find several good solutions. The initial values
of the optimization parameters are therefore randomly chosen between their
upper and lower bounds. The node voltages are initially selected between the
positive and negative power supply voltage.
6.2.3 Optimization Results

In the following the optimization results for the OTAs shown in Fig. 6.4 through
Fig. 6.6 are presented. The device sizing tool is directed to generate circuits that
meet the specification in Table 6.1. The tool can simultaneously sweep several
performance metrics in order to explore the design space. However, the graphs
presented are two-dimensional cuts in this space.
In the graphs the performance metric being swept is placed on the x-axis while
the metric being minimized/maximized is on the y-axis. Each point in the graphs
represents the best of several solutions (local minima). The time required to gen-
erate the circuit parameters used for compiling the information in each of the
graphs below is a few hours on a cluster of workstations.
For the circuits examined the average time required to find one solution is about
3 minutes for the two-stage, 6 minutes the folded-cascode, and 8 minutes for the
current-mirror OTA using a single workstation (Intel Pentium 4, 2.6 GHz).
Since the percentage of good solution is high the approximate form of the pre-
sented curves can be generated in short time with low requirements on computa-
tional power.
The curves presented are based on results taken directly from the circuit opti-
mizer, only a limited number of the solutions have been validated in the Spectre
simulator. In this case we have used the simplified transistor model described in
Sec. 4.7. The simulations show, however, good agreement with the optimizer
results.
Furthermore, special care has been taken in order to assure that the presented
results are not affected by the setup and formulation of the optimization problem.
For example the impact of different relative weights of the performance metrics
have been examined. Several different choices of weights have proven to yield
the same results as those presented here.
106
Design Case
6.2.4 Impact of Scaling the Power Supply Voltage

In Fig. 6.7 the power consumption for the three different amplifier topologies are
shown as a function of the power supply voltage. The voltage has been decreased
from 3.3 V until the circuit fails to meet the specification. The circuit area has
not been constrained.
3.6
3.4
3.2
2.8
2.6
2.4
2.2
Current−mirror
Two−stage
2 Folded−cascode
2.2 2.4 2.6 2.8 3 3.2 3.4

Power supply voltage [V]
Figure 6.7 The power consumption vs. the power supply voltage for the three amplifiers.
The graph shows the trade-offs between the power consumption and the power
supply voltage for the circuit topologies. At 3.3 V, the current mirror OTA has
the lowest power consumption, however, when lowering the power supply volt-
age below 2.8 V the two-stage amplifier is instead the best amplifier to use as far
as power is concerned.
For the two-stage amplifier the minimum power consumption, about 2 mW, is
found at the power supply voltage of 2.2 V. Thus, it is possible to decrease the
power supply voltage, and power consumption, without violating the specifica-
tion.
The graph also shows for what power supply voltages the specification can be
met. The two-stage amplifier fails to meet the specification at power supply volt-
ages below 2.15 V. The minimum power supply voltage to meet the input swing
is, using a first-order approximation to guarantee saturated transistors (assuming
that the threshold voltages of M1 and M3 are equal),
107
Current−mirror
Two−stage (deviation of 0.1mW)
8 Two−stage (no limitations)
Folded−cascode
7
Area [1000 µm2]
2.2 2.4 2.6 2.8 3 3.2 3.4

Figure 6.8 The circuit area as a function of the power supply voltage for the three different
amplifiers. An extra curve for the two-stage OTA where the maximum power
consumption is constrained to be within 1 mW of that shown in Fig. 6.7 is
added.
V DD ≥ V in, DC, max + V TH1 + VDS, sat1 – V TH3 ≈ 2.2V (6.2)

The power supply voltage can also be limited by the output swing. To guarantee
saturated transistors in the output stage, we require about 0.2 V across the drain-
source of the output transistors. This yields a minimum power supply voltage at
levels about
V DD ≥ V out, DC, max + V SD, sat6 ≈ 2.2V (6.3)
Thus the lower limit is set by the input and/or output swing of the amplifiers.
Further, as the power supply voltage decreases from 3.3 V the power consump-
tion also decreases linearly (constant power supply current) for the two-stage and
the folded-cascode OTA. This is due to the slew rate limitation.
The minimum circuit areas required to meet the circuit specification as a func-
tion of the power supply voltage are shown in Fig. 6.8. For the two-stage ampli-
fier two curves are plotted. In the lower-most curve no constraints on power
consumption is applied, in the other the maximum power consumption is con-
strained to be within 0.1 mW from the best solution in Fig. 6.7 for each power
supply voltage. For the folded-cascode and current-mirror OTAs the circuit areas
108
Design Case
are not affected by limiting the power consumption as will be discussed in Sec.
6.2.6. However, there exists a trade-off between these two metrics for the two-
stage OTA.
For the two-stage OTA the area is not affected by scaling the power supply volt-
age from 3.3 V to 2.4 V. However, below 2.4 V the area increases rapidly. This is
due to that the slew rate requirement puts a lower limit on the power supply cur-
rent. Since the positive output swing is approximately
I supply
--------------------- ≤ V DD – V out, DC, max (6.4)
µ 0 c ox W 6
---------------------
2L 6
and Isupply cannot be decreased due to the slew rate requirement the width of M6
must be increased.
It is clear that the area rapidly increases when the point where the circuit fails to
meet the specification is approached. When the upper bounds of the transistor
widths are reached the specification can no longer be met.
The number of circuits examined for, e.g., the folded-cascode OTA is in this case
about 2900 out of these 55% met the specification. The other 45% of the circuits
failed to meet one or several performance goals. There may be several reasons
for this. First, it is clear from Fig. 6.7 that there are no possible solutions below
2.5 V for the topology. Hence all circuits that did use a low power supply voltage
will not meet the specification. However, there are circuits failing where the
power supply voltage is higher than 2.5 V. This is because there exists several
bad starting points for which we get poor solutions.
In Fig. 6.9 the solutions for each value specification is shown. It is clear that
there are several solutions that yield much higher power consumption than the
best solution that is found. In order to accurately investigate the trade-off we
have to use several starting points. Thus, the exact number of starting points
depend on the topology, performance specification, and accuracy requirements.
However, the approximative form of this curve may be plotted using a small
number of designs since about 90% of the circuits are within a 10% deviation
from the best solution found.
Also, for some of the curves, the spacing between design points have been
adjusted. In Fig. 6.7 the spacing between design points for the two-stage ampli-
fier is 0.05 V for power supply voltages above 2.4 V while it is 0.01 V for volt-
ages below in order to capture the curve form accurately when large changes
occur. Currently the grid must be changed manually.
109
3.6
3.4
3.2
2.8
2.6
2.4
2.2
2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4
Figure 6.9 The solutions for each specification tested with the folded-cascode OTA.
6.2.5 Impact of Scaling the Unity-Gain Frequency

In the sample-and-hold circuit the output from the buffer must settle before the
clock edge arrives. The linear settling time for the buffer is determined by its
first pole. This is approximately the unity-gain frequency of the open-loop
amplifier. Hence, the circuit area and power consumption as a function of the
unity-gain frequency is of interest.
The possible trade-off between these performance metrics are shown in Fig. 6.10
for a power supply voltage of 3.3 V. The circuit area has not been constrained.
The maximum unity-gain frequency is 360 MHz, 300 MHz, and 260 MHz for
the two-stage, folded-cascode, and current-mirror OTA, respectively.
For frequencies below 150 MHz the slew rate specification is limiting the mini-
mum power consumption for the folded-cascode amplifier. In this case the unity-
gain frequency may thus be increased up to 150 MHz without increasing the
power consumption.
Further, the graph shows that each circuit topology has a specific range in which
minimum power consumption is obtained. Depending on the requirements on
unity-gain frequency different topologies should be chosen. If, e.g., the specifi-
cation on unity-gain frequency is 100 MHz the current-mirror should be used.
On the other hand, if the specification is changed to 150 MHz the folded-cascode
110
Design Case
50 Current−mirror
Two−stage
45 Folded−cascode
40
35 5
30 4
25 3
20 2
50 100 150
15
10
50 100 150 200 250 300 350

Figure 6.10 The power consumption as a function of the unity-gain frequency for the
amplifiers.
is the topology with the lowest power consumption. For all topologies, the power
consumption is increased at high unity-gain frequencies.
The circuit areas for the amplifiers as a function of the unity-gain frequency are
shown in Fig. 6.11. The power consumption is not constrained. The circuit area
must be increased for larger unity-gain frequencies.
6.2.6 Trade-Off of Circuit Area and Power Consumption

The design parameters that usually are to be minimized as long as the specifica-
tion is met are the circuit area and the power consumption. These parameters are
associated with the cost of the chip. The area vs. power consumption trade-off is
shown in Fig. 6.12 where the circuits are forced to have a specific power con-
sumption and the objective is to minimize the area. Increasing the power con-
sumption do not necessarily lead to increased design margins, in fact, all circuits
used in Fig. 6.12 have small margins. Hence, there exist a large number of poor
circuit realizations.
The circuit area of the two-stage amplifier can be made smaller at the expense of
increased power consumption. For the folded-cascode and the current-mirror
OTA there is no trade-off between these performance metrics.
111
14
12
Area [1000 µm2]
10
4
Current−mirror
Two−stage
2 Folded−cascode
50 100 150 200 250 300 350

Figure 6.11 The circuit area as a function of the unity-gain frequency for the amplifiers.
3.6
Current−mirror
3.4 A E Two−stage
Folded−cascode
3.2
B
3
Area [1000 µm2]
2.8
2.6
C
2.4
2.2
1.8
D
1.6
2.5 3 3.5 4 4.5

Figure 6.12 The circuit area as a function of the power consumption for the amplifiers.
112
Design Case
The points (A-D) in Fig. 6.12 indicate the best choices of circuit realizations for
our application. In this case the current-mirror OTA is the best topology with
respect taken to both area and power consumption. Selecting circuit D instead of
A, B, or C will result in a power reduction of 17%, 31%, and 33%, respectively.
For the circuit area the savings are 55%, 47%, and 35% for D compared to A, B,
and C. Selecting the best topology thus yield large savings i terms of both area
and power consumption in this case.
Notice that the selected circuits are most likely not found using manual design
techniques. Hence, the savings can be even larger in that case. Furthermore,
since a large number of poor circuit realizations exist, there is a large risk of end-
ing up with an even worse implementation, e.g., the point E, than indicated by
the curves.
6.2.7 Design Example Summary

The trade-off curves presented in the design example is dependent on the perfor-
mance specification. No general conclusions about the relations between the cir-
cuit topologies can be made. However, the described approach can be used to
explore the design space in order to visualize trade-offs and limitations within
reasonable time for a set of circuit topologies. Thus, increased design efficiency
and circuit performance are obtained.
Also, the curves presented are cuts in the design space that gives a few examples
on what kind of performance curves that can be created. It is up to the designer to
decide how to use the information obtained from the curves and make the design
decision.
Depending on the time available to explore the design space several performance
metrics may be swept and compared. Another possible way of exploring and
using the curves is illustrated in Fig. 6.13. Here the minimum power consump-
tion at each supply voltage was first determined by minimizing the power con-
sumption with no respect taken to the area requirements. In the second run the
area was optimized with different constraints on the maximum power consum-
tion. That is, in each point the power consumption was not allowed to deviate
with more than, e.g., 0.1 mW from that of the minimum power consumption.
The result shows that the circuit area may be decreased if we allow the power
consumption to increase. This approach allow the designer to get an indication of
the technology limits and based upon these make the decision on how important
a specific performance metric is in comparison to another. In this case it might be
more important to reduce the area requirements than to save 0.1 mW in power
consumption.
113
8 Total area (deviation of 0.1mW)

Total area (deviation of 0.01mW)
7.5 Total area (no limitations on power)
6.5
Area [1000 µm2]
5.5
4.5
3.5
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

Figure 6.13 The area requirements of the two-stage amplifier with different constraints on
the total power consumption.
We have also shown how important performance metrics such as power supply
voltage, power consumption, and area may be traded in three OTAs topologies.
By selecting the best circuit topology out of these, large savings in terms of
power consumption and circuit area are obtained. We have illustrated the pro-
posed approach on three small examples, but the principle and the optimization
tool can be applied on larger circuits. The number of design points and the time
required to evaluate the cost function for each topology will, however, put an
upper limit on the parameter space that can be explored.
The comparison with simple approximations also show that the tool is capable of
finding good circuit solutions. Also, it is hard to achieve the same performance
using a manual design approach. Furthermore, since a large number of circuits
have been examined there should be at least some design points that contradict
what seams to be a continuos relation between the performance metrics. How-
ever, no such solutions where found even though the total number of circuit
examined is in the order of 50 000.
Further, one could argue that the results presented here are what we could expect
from a multi objective optimization. The best circuits in Fig. 6.12 could be found
by optimizing both the area and the power consumption simultaneously. How-
ever, such approaches will not contain any information about the cost involved
114
Design Case
with increasing/decreasing a specific performance metric. For example, the pos-

sibility to increase the unity-gain frequency for the folded-cascode OTA in
Fig. 6.10 will not be identified. It is, however, possible to achieve similar results
to those presented by performing a sequence of multi-objective optimizations
with different weights on the objectives.
The use of trade-off curves give the designer increased insight in the complex
relations between the performance metrics in analog circuits. In this approach
some of these relations are visualized. Also, since all points in the curves corre-
sponds to a transistor level implementation a circuit solution is immediately
available when the designer has decided which topology and performance speci-
fication to use.
115
116
CHAPTER VII
CONCLUSIONS
In this chapter we summarize the work done so far and discuss some future
directions of the project.
7.1 Summary
The work done addresses the problem of increasing the level of automation in
the analog design flow. A design platform that automatically sets up the design
equations and uses the equation-based approach to find the device sizes in analog
amplifiers is presented.
In contrast to previous usage of the equation-based approach we do not compro-
mise with the performance accuracy to reduce the run time. Instead, the same
high-accuracy device models as in a standard circuit simulator are used. The
penalty for this is that the run time is increased.
This first version of the design platform is modularized in order to support and
simplify changes of the various sub-tools and algorithms.
Further, the quality of the solutions reported by the design tool is high. Experi-
mental results shows that the tool can produce circuits with at least as good per-
formance as obtained using manual design methods.
The execution time for relatively large circuits is reasonable, although the design
tool is implemented in MATLAB and only minor efforts to improve the speed
117
Conclusions
has been done. Short execution time enables the possibility to explore the design
space and find possible trade-offs in analog circuit design.
Layout induced performance degradation is becoming more important as the
technology scales. In our approach we use a parasitic feedback loop in order to
meet the design goals. The method introduces a coupling between device sizing
and layout generation that is necessary in analog design.
7.2 Future work

It is clear that much work still remains in the field of analog design automation.
Our aim is to improve and extend our design platform to incorporate a larger por-
tion of the analog design flow.
The automated device sizing is the part of the work where most efforts have been
made. So far we have addressed the design of continuos-time amplifiers. Our
aim is to include additional performance metrics, such as yield, and support opti-
mization of other types of circuits.
In the current version of the tool a gradient-based optimization algorithm is used.
By initiating it in different starting points several good local minima are found.
However, other more efficient, optimization algorithms should be investigated.
The template-based approach used for layout generation requires a large initial
effort in implementing new templates. Other approaches uses optimization algo-
rithms and simple building blocks. This yields an increased generality and short
setup-time at the expense of increased generation time. However, in order to pro-
vide a flexible design flow the template-based approach is not an option. Thus,
other approaches should be investigated.
Also, investigating the convergence and robustness of the parasitic feedback
loop is important. Until now, only a few performance specifications on a single
topology have been evaluated.
The design space exploration and identification of possible trade-offs is a useful
tool to increase circuit performance and take full advantage of the available pro-
cess technology. Exploring the usage of this possibility, beyond the simple com-
parison of structures presented here, is an interesting extension to the tool. One
possibility is to perform an extensive design space exploration on all new cir-
cuits added to the system in order to perform an accurate topology selection.
118
REFERENCES
[1] G. Alpaydin, S. Balkir, and G. Dündar, “An Evolutionary Approach to

Automatic Synthesis of High-Performance Analog Integrated Circuits,”
IEEE Trans. Evol. Comput., vol. 7, no. 3, pp. 240-252, June 2003.
[2] G. Alpaydin, S. Balkir, and G. Dündar, “An Evolutionary Approach to

Automatic Synthesis of High-Performance Analog Integrated Circuits,”
IEEE Trans. Evol. Comput., vol. 7, no. 3, pp. 240-252, June 2003.
[3] Analog Design Automation Inc., homepage: www.analogsynthesis.com,

June 2003.
[4] Anasift, homepage: www.anasift.com, June 2003.
[5] Barcelona Design, homepage: www.barcelonadesign.com, June 2003.
[6] G. Beenker, J. Conway, G. Schrooten, and A. Slenter, “Analog CAD for

Consumer ICs,” in Analog Circuit Design, J. Huijsing, R. van der
Plassche, and W. Sansen, Eds. Kluwer, MA, USA, 1993.
[7] S. Balkir, G. Dündar, and A. Selcuk Ögrenci, Analog VLSI Design Auto-
mation, CRC Press, Boca Raton, FL, USA, 2003.
[8] B. Basaran, R.A. Rutenbar, and, L.R. Carley, “Latchup-Aware Place-

ment and Parasitic-Bounded Routing of Custom Analog Cells,” IEEE/
ACM Int. Conf. Computer-Aided Design, pp. 415-421, Santa Clara, CA,
USA, Nov. 7-11, 1993.
119
[9] Cadence Design Systems Inc., homepage: www.cadence.com, Nov.
2003.
[10] Y. Cheng and C. Hu, MOSFET modeling & BSIM3 user’s guide, Kluwer,
Norwell, MA, USA, 1999.
[11] J.M., Cohn, D.J. Garrod, R.A. Rutenbar, and, L.R. Carley, “KOAN/
ANAGRAM II: New Tools for Device-Level Analog Placement and
Routing,” IEEE J. Solid-State Circuits, vol. 26, no 3, pp. 330-342, Mar
1991.
[12] M.G.R Degrauwe, et al., “IDAC: An Interactive Design Tool for Analog
CMOS Circuits,” IEEE J. Solid-State Circuits, vol. 22, no. 6, pp. 1106-
1116, Dec. 1987.
[13] F. El-Turky and E.E. Perry, “BLADES: An Artificial Intelligence

Approach to Analog Circuit Design,” IEEE Trans. Computer-Aided
Design, vol. 8, no. 9, pp. 680-692, June 1989.
[14] C. Enz, F. Krummenacher, and E. Vittoz “An Analytical MOS Transistor

Model Valid in All Regions of Operation and Dedicated to Low-Voltage
and Low-Current Applications,” Kluwer J. Analog Integrated Circuits
Signal Proc., pp. 83–114, vol. 8, July 1995.
[15] F. V. Fernández and A. Rodríguez-Vázquez, “ Symbolic Analysis Tools

- the State-of-the-Art,” Proc. IEEE Int. Conf. Circuits Syst., pp. 798–801,
Atlanta, GA, May 12-15, 1996.
[16] G.G.E. Gielen and R.A. Rutenbar, “Computer-Aided Design of Analog

and Mixed-Signal Integrated Circuits,” Proc. IEEE, vol. 88, no. 12, Dec.
2000.
[17] G.G.E. Gielen and W. Sansen, Symbolic Analysis for Automated Design
of Analog Integrated Circuits, Kluwer, Norwell, MA, USA, 1991.
[18] O. Guerra, E. Roca, F.V. Fernández, and A. Rodríguez-Vázquez, “A

Hierarchical Approach for the Symbolic Analysis of Large Analog Inte-
grated Circuits”, Proc. Design, Automation Test Europe Conf. Exhibition,
pp. 48-52, Paris, France, Mar. 27-30, 2000.
[19] T. Halfmann, E. Henning, M. Thole, and T. Wichmann, Analog Insydes

– Tutorial, ITWM, Kaiserslautern, 1998.
[20] R. Harjani, R.A. Rutenbar, and L.R. Carley, “Analog Circuit Synthesis
and Exploration in OASYS,” Proc. IEEE Int. Conf. Computer Design,
pp. 44-47, Ray Brook, NY, USA, Oct. 3-5, 1988.
120
[21] R. Harjani, R.A. Rutenbar, and L.R. Carley, “OASYS: A Framework for
Analog Circuit Synthesis,” IEEE Trans. Computer-Aided Design, vol. 8,
no. 12, pp. 1247-1266, Dec. 1989.
[22] J.P. Harvey, M.I. Elmasry, and B. Leung, “STAIC: An Interactive Frame-
work for Synthesizing CMOS and BiCMOS Analog Circuits,” IEEE
Trans. Computer-Aided Design, vol. 11, no. 11, pp. 1402-1417, Nov.
1992.
[23] A. Hastings, The Art of Analog Layout, Prentice Hall, Upper Saddle
River, NJ, USA, 2001.
[24] E. Hennig, R. Sommer, and L. Charlack, “An Automated Approach for

Sizing Complex Analog Circuits in a Simulation-Based Flow,” Proc.
Design, Automation Test Europe, Paris, France, Mar. 4-8, 2002.
[25] M. del Mar Hershenson, S.P. Boyd, and T.H. Lee, “GPCAD: A Tool for
CMOS Op-Amp Synthesis,” I EEE/ACM Int. Conf. on Computer-Aided
Design, pp. 296-303, San Jose, CA, USA, Nov. 8-12, 1998.
[26] M. del M. Hershenson, S.P. Boyd, and T.H. Lee, “Optimal Design of a
CMOS Op-Amp Via Geometric Programming,” IEEE Trans. Computer-
Aided Design, vol. 20, no. 1, pp. 1-21, Jan. 2001.
[27] D.H. Horrocks and M.C. Spittle, “Genetic Algorithms,” IEE Colloquium
Circuit Theory and DSP, pp. 4/1-4/5, London, UK, Feb. 18, 1992.
[28] HSPICE users’s manual release H92, Meta-Software Inc., 1992.
[29] IBS Corporation, industry reports, 2002.
[30] L. Ingber, “Adaptive Simulated Annealing for Nonlinear Systems”,

homepage: www.ingber.com, Oct. 2003.
[31] D.A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley
and Sons, New York, NY, USA, 1997.
[32] H.Y. Koh, C.H. Sequin, and P.R. Gray, “OPASYN: A Compiler for
CMOS Operational Amplifiers,” IEEE Trans. Computer-Aided Design,
vol. 9, no. 2, pp. 113-125, Feb. 1990.
[33] M. Krasnicki, R. Phelps, R.A. Rutenbar, and L.R. Carley, “MAEL-

STROM: Efficient Simulation-Based Synthesis for Custom Analog
Cells,” Proc. Design Automation Conf., pp. 945-950, New Orleans, LA,
USA, June 21-25, 1999.
[34] P.J.M. van Laarhoven and E.H.L. Aarts, Simulated Annealing: Theory
and Applications, D. Reidel, Dordrecht, Holland, 1987.
121
[35] K. Lampaert, G. Gielen, and W. Sansen, Analog Layout Generation for
Performance and Manufacturability, Kluwer, Dordrecht, The Nether-
lands, 1999.
[36] W. Liu, et al., Bsim3v3 mosfet Model users’ manual, 1998.
[37] C.A. Makris and C. Toumazou, “Analog IC design automation. II. Auto-
mated circuit correction by qualitative reasoning,” IEEE Trans. Com-
puter-Aided Design, pp. 239-254, vol. 14, no. 2, Feb. 1995
[38] The MathWorks Inc., homepage: www.mathworks.com, Nov. 2003.
[39] P.C. Maulik and L.R. Carley, “Automating Analog Circuit Design Using
Constrained Optimization Techniques,” IEEE Int. Conf. Computer-Aided
Design, pp. 390-393, Santa Clara, CA, USA, Nov. 11-14, 1991.
[40] P.C. Maulik, L.R. Carley, and R.A. Rutenbar, “A Mixed-Integer Nonlin-
ear Programming Approach to Analog Circuit Synthesis,” Proc. Design
Automation Conf., pp. 698-703, Anaheim, CA, USA, June 8-12, 1992.
[41] F. Medeiro, F.V. Fernández, R. Dominguez-Castro, and A. Rodriguez-

Vazquez, “A Statistical Optimization-based Approach for Automated
Sizing of Analog Cells,” IEEE/ACM Int. Conf. Computer-Aided Design,
pp. 594-597, San Jose, CA, USA, Nov. 6-10, 1994.
[42] F. Medeiro, B. Perez-Verdu, A. Rodríguez-Vázquez, and J.L. Huertas,

“A Vertically Integrated Tool for Automated Design of ∆Σ Modulators,”
IEEE J. Solid-State Circuits, pp. 762-772, vol. 30, no. 7, July 1995.
[43] F. Medeiro-Hidalgo, R. Dominguez-Castro, A. Rodríguez-Vázquez, and

J. L. Huertas, “A Prototype Tool for Optimum Analog Sizing Using
Simulated Annealing,” Proc. IEEE Int. Symp. Circuits Syst., pp. 1933-
1936, San Diego, CA, May 3-6, 1992.
[44] C.B. Moler and G.W. Stewart, “An Algorithm for Generalized Matrix
Eigenvalue Problems,” SIAM J. Num. Anal., pp. 241–256, 1973.
[45] Neolinear Inc., homepage: www.neolinear.com, June 2003.
[46] J. Nocedal and S. J. Wright, Numerical optimization, Springer-Verlag,

New York, NY, USA, 1999.
[47] W. Nye, D.C. Riley, A. Sangiovanni-Vincentelli, and A.L. Tits,

“DELIGHT.SPICE: An Optimization-Based System for the Design of
Integrated Circuits” IEEE Trans. Computer-Aided Design, vol. 7 no. 4,
pp. 501-519, April 1988.
[48] Emil S. Ochotta, et al., Practical Synthesis High-Performance Analog

Circuits, Kluwer, Norwell, MA, USA, 1998.
122
[49] E.S. Ochotta, R.A. Rutenbar, and L.R. Carley, “Synthesis of High-Per-
formance Analog Circuits in ASTRX/OBLX,” IEEE Trans. Computer-
Aided Design, vol. 15, no. 3, pp. 273-294, Mar. 1996.
[50] M.J.M. Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers, “Matching

Properties of MOS Transistors,” IEEE J Solid State Circuits, vol. 24, no.
5, pp. 1433-1440, Oct. 1989.
[51] R. Phelps, M. Krasnicki, R.A. Rutenbar, L.R. Carley, and J.R. Hellums,
“Anaconda: Simulation-Based Synthesis of Analog Circuits Via Sto-
chastic Pattern Search,” IEEE Trans. Computer-Aided Design, vol. 19,
no. 6, pp. 703-717, June 2000.
[52] G. Van der Plas, et al., “AMGIE-A Synthesis Environment for CMOS
Analog Integrated Circuits,” IEEE Trans. Computer-Aided Design, vol.
20, no. 9, pp. 1037-1058, Sept. 2001.
[53] G. Van der Plas, G. Gielen, and W. Sansen, A Computer-Aided Design

and Synthesis Environment for Analog Integrated Circuits, Kluwer, Dor-
drecht, The Netherlands, 2002.
[54] G. Van der Plas, J. Vandenbussche, G. Gielen, and W. Sansen, “EsteM-

ate: A Tool for Automated Power and Area Estimation in Analog Top-
Down Design and Synthesis,” Proc. IEEE Cust. Integ. Circuits Conf., pp.
139–142, Santa Clara, CA, USA, May 5-8, 1997.
[55] V. Raghavan, et al., “AWE-Inspired”, Proc. IEEE Custom Integrated

Circuits Conf., pp. 18.1.1-18.1.8, San Diego, CA, USA, May 9-12, 1993.
[56] J. Rijmenants, J.B., Litsios, T.R. Schwarz, and M.G.R. Degrauwe,

“ILAC: An Automated Layout Tool for Analog CMOS Circuits,” IEEE
J. Solid-State Circuits, vol. 24, no. 2, pp. 417-425, April 1989.
[57] R.A. Rutenbar, “Analog Design Automation: Where are We? Where are
We Going?,” Proc. IEEE Custom Integrated Circuits Conf., pp. 13.1.1-
13.1.7, San Diego, CA, USA, May 9-12, 1993.
[58] A. H. Shah, S. Dugalleix, and F. Lemery, “Technology Migration of a

High Performance CMOS Amplifier Using an Automated Front-to-Back
Analog Design Flow,” Proc. Design, Automation Test Europe, Paris,
France, Mar. 4-8, 2002.
[59] SKILL Lanuage and Development, Cadence Design Systems Inc., 1997.
[60] B. De Smedt and G. Gielen, “WATSON: Design Space Boundary Explo-

ration and Model Generation for Analog and RF IC Design,” IEEE
Trans. Computer-Aided Design, vol. 22, no. 2, pp. 213–224, Feb. 2003.
123
[61] D.K. Su, M.J. Loinaz, S. Masui, and B.A. Wooley, “Experimental
Results and Modeling Techniques for Substrate Noise in Mixed-Signal
Integrated Circuits,” IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 420-
430, April 1993.
[62] C. Toumazou, G. Moschytz, and B. Gilbert, Trade-Offs in Analog Circuit

Design, Kluwer, Dordrecht, The Netherlands, 2002.
[63] P. Veselinovic, et al., “A Flexible Topology Selection Program as Part of

an Analog Synthesis System,” Proc. European Design Test Conf., pp.
119-123, Paris, France, Mar. 6-9, 1995.
[64] R.M.D.A. Velghe, D.B.M. Klaasen, and F.M. Klaasen, “Unclassified

report NL-UR 003/94,” Philips Electronics N.V., 1994. See also H. C.
deGraff and F. M. Klaasen, Compact transistor modelling for circuit
design, New York: Springer-Verlag, 1990.
[65] E.A. Vittoz, “The Design of High-Performance Analog Circuits on Digi-

tal CMOS Chips,” IEEE J. Solid-State Circuits, pp. 657-665, vol. 20, no.
3, June 1985.
[66] J. Vlach and K. Singhal, Computer Methods for Circuit Analysis and
Design, Van Nostrand Reinhold, New York, NY, USA, 1983.
[67] P. Wambacq and W. Sansen, Distortion Analysis of Analog Integrated

Circuits, Kluwer, Dordrecht, The Netherlands, 1998.
[68] Wolfram Research Inc., homepage: www.wolfram.com, Nov. 2003.
124

LiU Tek Lic 2003 E - Hjalmarson

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

LiU Tek Lic 2003 E - Hjalmarson

Uploaded by

Copyright:

Available Formats

Linköping Studies in Science and Technology

Thesis No. 1065

STUDIES ON DESIGN AUTOMATION

Copyright © 2003 Emil Hjalmarson

Department of Electrical Engineering

ISBN 91-7373-878-6 ISSN 0280-7971

II. PERFORMANCE METRICS AND DESIGN ISSUES FOR ANALOG AMPLIFIERS 15

III. COMPUTER AIDED DESIGN OF ANALOG CIRCUITS ...................................31

IV. THE DESIGN PLATFORM ...........................................................................63

V. LAYOUT GENERATION AND PARASITIC FEEDBACK ...................................85

VI. EXPLORATION AND TRADE-OFFS IN ANALOG AMPLIFIER DESIGN ..........99

VII. CONCLUSIONS .........................................................................................117

In this work we address the shortcomings of the analog design methodology

1.1 Analog Integrated Circuits

1998 1999 2000 2001 2002 2003 2004 2005 2006

1.2 The Analog Design Flow

Figure 1.2 The analog design flow [48].

1.2.1 The Manual Design Methodology

Circuit topology selection

1.3 Challenges in Analog Design

of the transistors in order to meet the requirement on bandwidth, however, while

Minimum power consumption

Figure 1.4 The design parameter space.

1.4.1 Goals in Analog Design Automation

1.5 Scope of this Thesis

1.6 Publications Related to this Thesis

[1] E. Hjalmarson, R. Hägglund, and L. Wanhammar, “Design Space Explo-

[2] E. Hjalmarson, R. Hägglund, and L. Wanhammar, “Optimization-Based

[3] E. Hjalmarson, R. Hägglund, and Lars Wanhammar, “An Optimization-

[4] E. Hjalmarson, R. Hägglund, and L. Wanhammar, “An Equation-Based

[5] R. Hägglund, E. Hjalmarson, and L. Wanhammar, “Using Optimization

[6] E. Hjalmarson, R. Hägglund, and L. Wanhammar, “A Design Platform

[7] R. Hägglund, E. Hjalmarson, and L. Wanhammar, “A Design Path for

[8] E. Hjalmarson, R. Hägglund, P. Löwenborg, and L. Wanhammar, “Auto-

[9] R. Hägglund, E. Hjalmarson, and L. Wanhammar, “Automatic Device

[10] R. Hägglund, E. Hjalmarson, and L. Wanhammar, “Optimization-Based

2.1 The Process Technology

2.1.1 The CMOS Devices

2.2 Performance Metrics in Amplifier Design

Bandwidth and Unity-Gain Frequency

Figure 2.3 Magnitude and phase response of an amplifier.

Positive and Negative Power Supply Rejection Ratio

Common Mode Rejection Ratio

output power level

monic. IIP3 is calculated in a similar manner. It is also possible to compute

Common-Mode Range and Output Range

Circuit Area, Power Consumption, and Yield

Lower tolerance level

2.3 Circuit Layout

Figure 2.6 Common-centroid placement for a matched capacitor array.

2.4 Trade-Offs in Analog Amplifier Design

Input/output Power supply

The objective of design automation is to address the drawbacks in manual

3.1 The Automated Design Flow

Sizing and biasing 10/0.7 10/0.7

3.1.1 Topology Selection

3.1.2 Sizing and Biasing

3.1.3 Layout Generation

Template-Based Layout Generation

Rule-Based Layout Generation

Performance Driven Layout Generation

3.2 The Knowledge-Based Approach