IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO.
11, NOVEMBER 2010
Understanding LER-Induced MOSFET VT
Variability—Part I: Three-Dimensional
Simulation of Large Statistical Samples
Dave Reid, Campbell Millar, Scott Roy, and Asen Asenov, Senior Member, IEEE
Abstract—In this paper, using computationally intensive 3-D
simulations in a grid computing environment, we perform a de-
tailed study of line-edge-roughness (LER)-induced threshold volt-
age variability in contemporary MOSFET S. Statistical ensembles
of tens of thousands transistors have been simulated. Our analysis
has been predominantly performed on a 35-nm channel-length
bulk MOSFET test bed, widely used in previous studies to investi-
gate the impact of different statistical variability sources. Compre-
hensive data mining and statistical analysis provide information
about the shape of the distribution of the device threshold voltage,
which is significantly non-Gaussian. Strong nonlinear correlation
has been observed between the threshold voltage and the average
channel length of the simulated devices. The width dependence of
LER-induced threshold voltage variability has also been simulated
and analyzed. Additional confirmation of the basic conclusions
from the simulation and statistical analysis of the 35-nm test
bed transistor is provided by the simulation of a 42-nm physical
channel-length bulk LP MOSFET, a 32-nm channel-length thin-
body silicon-on-insulator (SOI) MOSFET, and a 22-nm channel-
length double-gate (DG) MOSFET.
Index Terms—line edge roughness, MOSFET, numerical simu-
lations, statistical analysis, variability.
I. I NTRODUCTION
S TATISTICAL variability, introduced by the discreteness of
charge and the granularity of matter, is one of the major
challenges facing the scaling of contemporary MOSFET S in
future technology generations [1]. Random discrete dopants
(RDD) dominate statistical variability in conventional (bulk)
MOSFET S [2], [3], which remain the workhorse of the semi-
conductor industry [4]. However, the contribution of line-edge
roughness (LER) to statistical variability is becoming increas-
ingly important, due to the fact that LER scaling currently lags
the requirements of the International Technology Roadmap for
Semiconductors [5], [6]. Recent comprehensive simulation of
statistical threshold voltage (VT ) variability in bulk MOSFET S
indicates that failure to reduce LER below its current level
(approximately 5 nm) could promote it to the dominant source
Manuscript received January 20, 2010; revised July 15, 2010; accepted
July 16, 2010. Date of publication September 9, 2010; date of current ver-
sion November 5, 2010. The review of this paper was arranged by Editor
H. S. Momose.
The authors are with the Device Modelling Group, Department of
Electronics and Electrical Engineering, University Of Glasgow, G12 8LT
Glasgow, U.K.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2010.2067731
0018-9383/$26.00 © 2010 IEEE
2801
of statistical variability, when gate lengths are scaled to 20 nm
and below [7]. While new device architectures such as silicon-
on-insulator (SOI) and FinFETs tolerate low-channel doping
which reduces RDD-induced variability, they remain suscep-
tible to LER-induced variability [8]–[10].
LER-induced variability has been the subject of numer-
ous modeling and simulation studies of different degrees of
complexity and sophistication. The use of 2-D simulations of
devices with different channel lengths in combination with
the statistics of different channel length occurrences in the
presence of LER has been popular due to the low computational
burden [11]–[14]. Comprehensive 3-D simulations vary in the
complexity of the LER description from square wave approx-
imations [15], [16] to realistic statistical descriptions of the
gate edge based on different autocorrelation functions fitted to
experimental LER data [17]. More sophisticated 3-D simulation
studies include the confluence of LER and atomic-scale process
simulation [18] and the impact of LER-induced strain variations
[19]. However, a common denominator in all of the published
3-D simulations studies is the relatively small statistical sample,
which rarely exceeds 200 microscopically different devices.
Recent detailed simulation study of RDD-induced variability
have shown that simulations of much larger statistical samples
are needed in order to reveal the actual shape of the resulting
statistical distribution and to understand the physical reasons
behind it [20].
In this paper, we present a comprehensive 3-D simulation
study of LER-induced MOSFET threshold voltage variability
using statistical samples of more than 104 transistors. Contem-
porary bulk, ultrathin-body (UTB) SOI, and double-gate (DG)
MOSFET S have been simulated and analyzed. The large size
of the simulated statistical samples allows accurate estimation of
the higher order moments and the shape of the distributions of
VT . Intensive statistical data mining is also used in order to
explain the specific shape of the simulated distributions.
The simulation methodology and grid technology used to
facilitate simulation of these very large statistical samples is
described in Section II. Section III is dedicated to the com-
prehensive simulation and analysis of LER-induced variability
in a 35-nm gate-length template bulk MOSFET, widely used
before by the authors of this paper to study and compare the
impact of different statistical variability sources [7]. Simula-
tion results for a set of alternative bulk, UTB SOI, and DG
MOSFET S are presented in Section IV and conclusions are
drawn in Section V.
2802 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 11, NOVEMBER 2010

II. S IMULATION M ETHODOLOGY

The simulations presented in this paper were carried out
using the well-established Glasgow 3-D “atomistic” statistical
device simulator, described in detail elsewhere [7]. Random
gate LER patterns are introduced into the simulations using 1-D
Fourier synthesis, as described in [17]. A Gaussian autocorre-
lation function characterized by an RMS amplitude (Δ) and
correlation length (Λ) has been adopted to describe LER, as in
previous LER simulation studies [17]. Following the usual LER
definition, the quoted values for LER magnitude correspond to
3Δ. In all simulations reported in this paper, values of Δ =
1.6667 nm and Λ = 30 nm have been used to generate random
source/drain and gate edges introduced by roughness of the re-
sist and the following gate patterning process. This corresponds
to LER patterns with magnitude 5 nm, which is representative Fig. 1. Comparison of the histograms of VT obtained from RDD-only and
of the state-of-the-art 193-nm lithography expected to be used LER-only simulations at VD = 100 mV.
in manufacturing of the 32- and 22-nm technology generations.
The 3-D doping profile in the presence of LER is generated A. Simulation Results
using 2-D process simulation results and by assuming that
We focus on LER-induced VT variability, which could have
the p-n junctions follow the same pattern as the gate edge.
strong influence on static random access memory performance
This is a reasonable approximation in contemporary CMOS
and yield. The threshold voltage is defined using a current
technology, where laser scan annealing is progressively applied
criterion. 25 000 3-D simulations were carried out at a low
for doping activation.
drain voltage of VD = 100 mV and 10 000 3-D simulations
Grid technology is used to facilitate the handling of the
were carried out at a high drain voltage of VD = 800 mV. Only
large-amount computational resources deployed and the vast
square devices (L = W = 35 nm) are simulated and analyzsed
amount of data generated [21]. The computational resources
in this and the next subsection.
for this paper were provided by the ScotGrid computer system
In order to quantify the relative contributions of RDD and
[22] via the Globus software tool kit, and large-scale job sub-
LER to the overall VT variability of the template transistor, the
mission was achieved using the Ganga frontend [23]. Special
distributions of VT introduced by RDD and LER at low drain
care was taken to track failed and/or numerically unstable
voltage (VD = 100 mV) are compared in Fig. 1. It is clear that
simulations in order to preserve the statistical integrity of the
while RDD is the dominant source of statistical variability in
samples. A data management system based on a PostgreSQL
this device, LER introduces statistical variability of a compara-
database backend was deployed in order to manage the large
ble magnitude, with the standard deviation being ∼40% of the
distributed data sets. The database also facilitated some sem-
RDD-induced standard deviation. There is also a small shift in
blance of live job status monitoring and allowed complex
the central tendency between the distributions, with VT being
data mining searches to be performed on the data via SQL
5 mV higher for LER compared to RDD. Comparison of the
queries and direct interfaces to statistical analysis tools such
simulated distributions with reference Gaussian distributions
as “R” [24].
having mean (μ) and standard deviation (σ) values calculated
from the data clearly shows that the LER-induced distribution
of VT is skewed in the opposite direction compared to the RDD-
III. 35-nm T EST B ENCH MOSFET
induced distribution. This is consistent with the descriptive
The simulated 35-nm physical gate-length n-channel statistics extracted from the distribution presented in Table I,
MOSFET developed and published by Toshiba [25] has a which show negative skew with a large magnitude for the LER-
complex doping profile featuring retrograde Indium channel induced distribution compared to the positive skew due to RDD.
doping and source/drain pockets. It has a 0.88-nm Oxy-Nitride The simulated LER-induced distributions of VT at low and
gate dielectric, 20-nm extension junction depth, and a 26-nm high drain voltages are compared in Fig. 2(a) and (b) with
metallurgical (junction-to-junction) channel length. Details of Gaussian distributions with mean and standard deviation ex-
the calibrated doping profile and the current voltage charac- tracted from the data. It is clear that the threshold voltage
teristics of the transistor are available in [20]. The choice of variation increases and average threshold voltage decreases
this “template” MOSFET is motivated by the fact that it has with drain voltage. This can be attributed to the influence of
been used extensively by the authors to study the individual drain-induced barrier lowering (DIBL). The increase in drain
and combined impact of different statistical variability sources voltage results in a negative mean threshold voltage shift of
[2], [7], including the 105 statistical sample 3-D simulation 56.8 mV (∼25%) and an increase in the standard deviation by
study of RDD variability that motivates this paper [20]. Pre- 6.4 mV (∼50%). We also note that there is a small shift in the
liminary results of the simulations of LER-induced threshold average VT of the ensembles, as compared to that of the uniform
voltage (VT ) variability of the same transistor were reported continuously doped device, with ΔVT = 1.4 mV at low drain
in [26], [27]. and 2 mV at high drain. There is thus a slight increase in DIBL
REID et al.: UNDERSTANDING MOSFET VT : 3-D SIMULATION OF SAMPLES
TABLE I
SUMMARY OF THE STATISTICAL MOMENTS OF THE DATA FOR LER
SIMULATIONS AT VD = 100 mV AND VD = 800 mV. DATA FOR
100 000 RDD SIMULATIONS AT VD = 100 mV IS ALSO
SHOWN FOR COMPARISON
Fig. 2. Comparison of the histograms of VT obtained for LER simulations at
VD = 100 mV and VD = 800 mV. Gaussian distributions with the data mean
and standard deviation are shown for comparison.
from 56.2 to 56.8 mV due to the introduction of LER. Further
examination of the distribution of DIBL indicates that this is
due to the distribution being significantly non-Gaussian, with a
skew of 0.46 and kurtosis of 0.41. Therefore, more devices will
suffer from higher DIBL, leading to an increase in the average
DIBL and the observed negative skew in the distribution of VT .
Furthermore, the data in Table I indicates that the drain voltage
slightly increases the asymmetry of the distribution.
The relative change in the first four statistical moments of
the VT distribution at VD = 100 mV as a function of sample
size is shown in Fig. 3. The relative change is defined as
|xi − xi−1 |/xi−1 , where xi is the current value of the particular
moment and xi−1 is the previous value. Although the trend
is monotonic, there is a statistical noise associated with each
moment, so the relative change is averaged out over a window
of 200 devices, resulting in the smooth trend seen in Fig. 3. This
gives an indication of the rate of convergence of the different
moments of the statistical distribution and the level of statistical
accuracy attained by the simulation of such large statistical
samples. It is clear that the shape of the distribution cannot be
accurately determined from small samples of a few hundreds of
devices.
2803
Fig. 3. Relative change in the first four statistical moments of the distribution
of VT as a function of sample size at VD = 100 mV.
Fig. 4. Scatterplot of VT against minimum, maximum, and average LC .
Strong nonlinear correlation between VT and average LC can be observed.
B. Statistical Analysis
Fig. 4 compares the distributions of VT as a function of the
minimum, maximum, and average value of the channel length
LC . It is visually clear that both the minimum and maximum
values of LC are strongly correlated with the threshold voltage,
with calculated correlation coefficients of ρmin LC ,VT = 0.92
and ρmax LC ,VT = 0.88. The shapes of the two distributions
confirm the expectation that a transistor with LER always has a
larger threshold voltage compared to a uniform transistor with
the channel length equal to the minimum channel length of
the LER transistor, and a smaller threshold voltage compared
to a uniform transistor with the channel length equal to the
maximum channel length of the LER transistor.
However, the correlation between average channel length and
VT is stronger, yielding a correlation coefficient of ρavgLC ,VT =
0.994. Fig. 5 compares the channel length dependence of the
threshold voltage obtained from simulations of transistors with
uniform gate edges with the scatterplot of VT against average
channel length LC at low and high drain voltages. It is clear
that the threshold voltage of the LER MOSFET S is below but
very close to the threshold voltage of a uniform MOSFET
with LC equal to LC of the LER transistor. It was found that
the channel length dependence of the threshold voltage of the
uniform transistors can be accurately fitted by an expression of
2804
Fig. 5. Scatterplot of VT against average LC for low and high drain voltages.
The results of simulations with constant channel lengths are also plotted along
with a curve fit of the form α − β exp(−γx).
Fig. 6. Scatterplot of IOFF against average LC . The results for constant
channel lengths are also plotted.
the form f (x) = α − β exp(−γx) and the results of the fitting
at low and high drain voltages are also plotted in Fig. 5.
Although the focus of this paper is VT variability, we have
also examined the relationship between off-current (IOFF )
and LC , which determines the well-documented LER-induced
leakage current increase [28]. The scatterplot of IOFF against
average LC is presented in Fig. 6 and shows a similarly strong
correlation to the scatterplot of VT . This is not surprising,
bearing in mind that log IOFF = log IVT − (VT /S), where IVT
is the current at threshold and S is the subthreshold slope. The
results for the dependence of IOFF on the channel length of
transistors with uniform gate edges are also plotted. Generally,
the off-current of the LER transistors is higher but very close
to the off-current of a uniform MOSFET with LC equal to
LC of the LER transistor. This indicates that the methodology
presented in Part II of this paper, which allows the LER-induced
distribution of threshold voltage to be easily reconstructed from
the channel length dependence of VT , can be trivially extended
to allow the prediction of the off-current distribution.
C. Width Dependence
In this subsection, the effect of transistor width on LER-
induced VT variations is investigated. Samples of 1000 devices
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 11, NOVEMBER 2010
TABLE II
SUMMARY OF THE DESCRIPTIVE STATISTICS OF THE DISTRIBUTION OF
VT FOR 35-nm DEVICES WITH WIDTHS 1–4. ALL RESULTS
ARE FOR VD = 100 mV
Fig. 7. Scatterplot of VT against LC for devices with different channel width.
Samples of 1000 transistors were used for all channel widths.
were simulated for devices with channel widths two, three, and
four times the minimal channel width (W0 = L) of 35 nm
at a low drain voltage of 100 mV. The moments of the simulated
distributions are presented in Table II together with the values
of
√ the standard deviation of the square MOSFET scaled by
w. It is clear
√ that the standard deviation decreases more
slowly than 1/ w. Despite the relatively large statistical error
associated with samples of this size, the skew shows a clearly
decreasing trend with increasing channel width.
Fig. 7 compares the distributions of VT as a function of LC
for the transistors with different channel widths. A subsample
of 1000 was selected for the square transistors to facilitate the
visual presentation of the decreasing spread of LC for transis-
tors with large channel widths. It is clear that the asymmetry
in the threshold voltage distribution is related to the nonlinear
correlation between VT and LC , with steeper changes at smaller
values of LC . Since for all channel widths, the average LC
is close to 35 nm, it is clear that the reduced spread of LC is
responsible for the more symmetrical VT distribution in wider
devices, which manifests in the smaller absolute values of the
corresponding skews.
REID et al.: UNDERSTANDING MOSFET VT : 3-D SIMULATION OF SAMPLES 2805

Fig. 8. Comparison of the distribution of VT due to LER in the four simulated Fig. 9. Comparison of the relationship between LC and VT in the four
devices at VD = 100 mV. simulated devices at VD = 100 mV.

TABLE III
SUMMARY OF THE STATISTICAL MOMENTS OF THE DISTRIBUTION OF VT
IV. I MPACT ON A LTERNATIVE D EVICE A RCHITECTURES AT L OW D RAIN IN A LL F OUR T RANSISTORS

In order to confirm the trends observed in the simulations

of the bulk 35-nm test bed MOSFET, and to examine the
potential impact of LER on different device architectures,
smaller ensembles of three other devices have been simulated.
The selection includes an LP 42-nm physical gate- length bulk
MOSFET with an oxide thickness of 1.7 nm, developed by
ST Microelectronics and described in detail in [29]; a 32-nm
physical gate-length UTB SOI MOSFET with a body thickness
of 7 nm and equivalent oxide thickness (EOT) of 1.2 nm;
and a 22-nm DG MOSFET with a body thickness of 10 nm
and EOT of 1.1 nm. The last two devices were developed by
the PULNANO consortium [30] and are described in detail in
[8]. The distributions of threshold voltage for 35- and 45-nm
bulk; 32-nm SOI and 22-nm DG devices at low drain voltage
(VD = 100 mV) are presented in Fig. 8. For all devices, the
shape of the distribution of VT is similar and all are negatively case scenario. Modeling the bottom gate with different edges to
skewed. It should be noted that the SOI MOSFET in particular the top gate would likely result in a reduction of the spread of
exhibits good immunity to LER-induced variability, having a VT due to statistical averaging.
standard deviation of VT that is much lower than the other three
devices. This is due to better electrostatic integrity and hence
reduced short-channel effects.
V. C ONCLUSION
Scatterplots illustrating the relationship between VT and LC
in each of the four devices simulated in this paper are shown in Analysis of the simulation results of large statistical samples
Fig. 9. The same strong nonlinear correlation between VT and of a 35-nm test bed MOSFET subject to LER has revealed that
LC initially observed in the 35-nm MOSFET is present for the distribution of the threshold voltage is asymmetrical with
the other three transistors. As mentioned previously, this rela- a negative skew, which increases with drain bias. There is a
tionship provides a mapping between the two random variables very strong nonlinear correlation between the threshold voltage
(LC and VT ), hence the shape of this function, which closely and the average channel length of the LER transistors that very
follows the correlation between VT and LC , will directly affect closely follows the channel length dependence of the threshold
the final distribution of VT . The skew and kurtosis values voltage in transistors with uniform gate edges. Increasing the
for the four simulated devices are given in Table III, along with channel width reduces√the threshold voltage standard deviation
the other moments of the statistical distributions. The values more slowly than 1/ w and improves the symmetry of the
of the moments also confirm the visual observation that the distribution of threshold voltage. The asymmetry of the distrib-
SOI device has significantly better immunity to LER-induced ution and the strong nonlinear correlation between the threshold
fluctuations. While there would appear to be no improvement voltage and the average channel length was also confirmed in
in the VT spread for the DG device compared to the 35-nm bulk the simulation of a 42-nm physical channel-length bulk LP
device, it should be noted that in these simulations, both gates MOSFET, a 32-nm channel-length thin-body SOI MOSFET,
follow the same LER pattern, and therefore represent a worst and a 22-nm channel-length DG MOSFET.
2806 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 11, NOVEMBER 2010
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Dave Reid received the B.Eng. degree in electronics
engineering and the Ph.D. degree in large-scale sim-
ulations of intrinsic parameter fluctuations from the
University of Glasgow, Glasgow, U.K., in 2007 and
2010, respectively.
He is currently a Research Assistant in the Device
Modelling Group of the Electronics Department of
the University of Glasgow, working on large-scale
statistical simulations of intrinsic parameter fluctu-
ations in MOSFETs and CMOS circuits using Grid
and HPC technology. His research interests include
high-performance parallel computing, device modeling, circuit simulation, and
statistical techniques.
Campbell Millar is currently a member of the De-
vice Modelling Group at the University of Glasgow,
Glasgow, U.K. His research interests include semi-
conductor device simulation, statistical device and
circuit simulation techniques, TCAD and ECAD
tool design, High-Performance Computing, and
Biological and Bionanotechnology simulation. He
has published over 50 papers in the above fields. He
is currently a member of the ULIS 2010 organizing
committee.
Scott Roy is currently the Head of the Department of
Electronics and Electrical Engineering at the Univer-
sity of Glasgow, Glasgow, U.K., and a Senior Mem-
ber of the Device Modelling Group with research
interests at the interface of CMOS device simulation
and circuit design. He was promoted to Reader in
2006, and has published approximately 200 papers
in the fields of device transport, MC simulation
(III-V, Si and SiGe devices), device scaling, and the
development of practical compact models for devices
at the nanoscale. He was the Local Chair of the 1st
SINANO Summer School 2005, PNGF4 2009, and is the General Chair of
ULIS 2010.
REID et al.: UNDERSTANDING MOSFET VT : 3-D SIMULATION OF SAMPLES
Asen Asenov (M’96–SM’05) received the M.Sc.
degree in solid-state physics from Sofia University,
Sofia, Bulgaria, in 1979, and the Ph.D. degree in
physics from the Bulgarian Academy of Sciences,
Sofia, in 1989.
He had a ten-year industrial experience as the
Head of the Process and Device Modelling Group,
Institute of Microelectronics, Sofia, where he de-
veloped one of the first integrated process and
device CMOS simulators, IMPEDANCE. During
1989–1991, he was a Visiting Professor with the
Physics Department, Technical University of Munich, Munich, Germany. Since
1991, he has been with the Department of Electronics and Electrical Engi-
neering, University of Glasgow, Glasgow, U.K., where he was the Head in
1999–2003. As a Professor of device modeling, the Leader of the Glasgow
Device Modeling Group, and the Academic Director of the Glasgow Process
and Device Simulation Centre, he coordinates the development of 2-D and
3-D quantum-mechanical, Monte Carlo, and classical device simulators and
2807
their application in the design of advanced and novel CMOS devices. He has pi-
oneered the simulations and the study of various sources of intrinsic parameter
fluctuations in decanano- and nano-CMOS devices, including random dopants,
interface roughness, and LER. He is the Author of over 330 publications in
process and device modeling and simulation, semiconductor device physics,
“atomistic” effects in ultrasmall devices, and impact of variations on circuits
and systems, including, in the last five years, more than 15 papers in the IEEE
TRANSACTIONS ON ELECTRON DEVICES.
Dr. Asenov is a Fellow of the Royal Academy of Scotland and a member
of the IEEE Electron Devices Society Technology Computer-Aided Design
Committee. He is currently a member of the program committees for the Inter-
national Electron Devices Meeting, the European Solid-State Device Research
Conference, the International Workshop on Computational Electronics, the
Silicon Nanoelectronics Workshop, the Hot Carriers in Semiconductors, and the
IEEE Nanotech Conference, and is the forthcoming Program Committee Chair
for the 2006 Silicon Nanoelectronics Workshop. In the last five years, he was
also given more than 65 invited talks at prestigious international conferences
and meetings in Europe, the U.S., and Japan.