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Abstract—In this paper, the isothermal model of power MOS program with integrated circuit emphasis (SPICE) programs,
transistors offered by the producer of these devices and the elec- e.g., PSPICE, IS-SPICE, and HSPICE. The models of semicon-
trothermal model of these devices proposed by the authors are pre- ductor devices—including power MOS transistors are available
sented. The results of experimental verification of both the models
are given as well. (built-in) in these programs. APLAC allows performing the elec-
trothermal analysis, but the ETM of the power MOS transistor
Index Terms—Electrothermal effects, modeling, MOSFETs, is not available in this program [2].
simulation program with integrated circuit emphasis (SPICE).
For a long time, SPICE has been a comfortable, commonly
used tool for the analysis of electronic circuits. Unfortunately,
SPICE built-in MOSFET models of various efficiency (levels)
I. INTRODUCTION [3]–[7], formulated for low-power devices, are the isothermal
URRENTLY, MOS transistors are commonly used in lin- models, which means that self-heating is not included in these
C ear and switched electronic circuits. The computer anal-
ysis of such circuits is of a great importance for engineers,
models.
Apart from this, a lot of isothermal macromodels made by
because it allows investigating a lot of properties of such MOSFETs producers can be found on their Websites [8]–[10].
circuits without their fabrication. To obtain fully credible re- On the other hand, electrothermal macromodels of the power
sults of the simulations, the device models, especially MOS- MOSFETs are also available both in papers, e.g., [11] and [12]
FETs models of proper accuracy and acceptable complexity, as and on the Internet, e.g., [13] and [14]. These macromodels
well as computer tools accepting the form of these models are formulated for SABER or SPICE programs are of the hybrid
needed. or the global form [1], [15]. The hybrid macromodel consists
To reduce the complexity of the device model, only the most of the isothermal built-in model and the additional added ele-
important physical phenomena influencing its terminal charac- ments, describing the changes of the device terminal currents
teristics and parameters have to be taken into account in the and voltages due to self-heating. The electrothermal hybrid
process of model formulating. models of MOS transistors were proposed in [11], [12], [14],
One of the most important physical phenomenon that affects and [16]–[18]. These models are based on the Shichman–
the power MOS transistor properties is self-heating, resulting Hodges model [11], [18], the Dang model [14], [16], the EKV
from the conversion of electrical energy into heat, and thus model [12], or the Berkeley short-channel IGFET model (BSIM)
leading, in the real cooling conditions, to the junction (inner) model [17]. In turn, the electrothermal global models are com-
temperature rise above the ambient one. The power MOS tran- posed of controlled current or voltage sources and passive ele-
sistor characteristics determined in the self-heating conditions, ments, describing nonisothermal characteristics of the consid-
such as the nonisothermal characteristics, can differ from the ered device, e.g., [13] and [19]. Unfortunately, these ETMs
isothermal characteristics corresponding to the ideal cooling are dedicated to low-power planar devices in the integrated
conditions [1]. circuits [11], [12], [14] or to one kind of unipolar devices—
To simulate the nonisothermal characteristics, the electrother- CoolMOS transistors [13].
mal model (ETM) constituting a connection of the electrical In spite of great complexity of some macromodels, the impor-
model, the thermal model, and the dependence of the electrical tant physical phenomena are not included, which results in the
power dissipated into the device on the terminal currents and unacceptably great inaccuracy of the macromodels, e.g., [20]
voltages has to be used [1]. and [21]. The former ETMs of MOS transistors worked out by
There are a lot of computer programs for electronic circuits the authors are dc models [19], [22], [23].
analysis, e.g., SABER or APLAC and some kinds of simulation In this paper, the new large-signal ETM of power MOS
transistors, appropriate for both the dc and transient analy-
Manuscript received May 28, 2009; revised September 24, 2009. Current sis of electronic circuits with this device by SPICE, is pre-
version published May 7, 2010. This work was supported by the Polish Ministry sented. The accuracy of this model was confirmed by mea-
of Science and Higher Education in 2007–2009 under Research Project N N510 surements of the selected vertical diffused MOS (VDMOS)
3425 33. Recommended for publication by Associate Editor E. Santi.
The authors are with the Department of Marine Electronics, Gdynia Mar- and TrenchMOS transistors. The obtained results of the cal-
itime University, Gdynia 81-225, Poland (e-mail: zarebski@am.gdynia.pl; culations and measurements were additionally compared with
gorecki@am.gdynia.pl). the calculation results performed with the use of the isother-
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. mal model available on the device producer Websites [9],
Digital Object Identifier 10.1109/TPEL.2009.2036850 [10].
Fig. 1. Network representation of the proposed model (ETM) of the power MOS transistor.
II. FORM OF THE ETM OF THE POWER MOS TRANSISTOR gate currents, respectively. The elements Rth and Cth repre-
sent the thermal resistance and the thermal capacitance of the
Zare˛bski and Górecki proposed the dc ETM of the power
considered device, respectively.
MOS transistor in [22]. This model is based on the modified
Shichman–Hodges model. The dc component of the drain current is a sum of the currents
of the controlled current sources G1 and G2 , representing the
To formulate the ETM of the considered device, two kinds of
ideal component of the channel current Idr and the subthreshold
dependences are necessary. They represent:
1 the electrical model along with the parameters depending current IP , respectively.
The channel current Idr is given by (2), as shown at the bottom
on the junction temperature;
of this page, where W and L denote the width and the length
2 the thermal model describing the dependence of the junc-
tion device temperature on the electrical power dissipated of the channel, respectively, Vt is the threshold voltage, λ is
the parameter of the output conductance, KP is the parameter
into the device.
The network representation of the new ETM of MOS transis- of transconductance, and VGS and VDS are the gate-to-“inner”
tor is presented in Fig. 1. As seen, the electrical model contains source voltage and the “inner” drain-to-“inner” source voltage,
respectively. The “inner” potential is equal to the external one if
the elements responsible for the dc characteristics shape and
the device electrical inertia. In turn, the thermal model is of the the resistance of the proper part of the MOS transistor is equal
form of the Cauer network [1], [24], [25], where the control to zero.
As it results from (2), the dependence describing the Idr cur-
current source Gp t h represents the thermal power dissipated in
the device, as described by the formula rent is given by splines, whereas the efficiencies of the controlled
generators existing in SPICE have to be described by means of
pth = iD vDS + iG vGS (1) a combination of the SPICE standard functions. Therefore, (2)
has to be transformed into the form given by the composition of
where vGS and vDS denote the gate-source and the drain-source the standard functions accepted by SPICE. The circumstantial
voltages, respectively, whereas iD and iG are the drain and the description of (2), by means of the function LIMIT—available
0, for VGS − Vt ≤ 0
W
Idr = KP (1 + λVDS ) VDS [2 (VGS − Vt ) − VDS ], for VDS ≤ VGS − Vt (2)
2L
W 2
KP (1 + λVDS ) (VGS − Vt ) , for 0 < VGS − Vt < VDS
2L
ZARE˛BSKI AND GÓRECKI: ELECTROTHERMAL LARGE-SIGNAL MODEL OF POWER MOS TRANSISTORS FOR SPICE 1267
in SPICE is given in [19]. As a result, the expression describing The output currents of the controlled sources GRD , GRS , and
the current Idr of the form GRDD , which model the series resistances of the drain, the
VDS W source, and the body diode, respectively, are described by the
Idr = | 2L KP (1 + λ |VDS |) LIMIT LIMIT (VGS , VGD )
|VDS
following formulae:
vRD
− Vt , 0, |VDS | 2 (LIMIT (VGS , VGD , Um ax ) − Vt ) GRD = (12)
RD 0 (1 + αRD (Tj − T0 ))
− LIMIT (LIMIT (VGS , VGD , Um ax ) − Vt , 0, |VDS |) vRS
GRS = (13)
(3) RS 0 (1 + αRS (Tj − T0 ))
vRDD
can be formulated. GRDD = (14)
RDD0 (1 + αRDD (Tj − T0 ))
In (3), the maximum value of the LIMIT function
Um ax =1 kV is arbitrarily used. where vRD , vRS , and vRDD are the voltages on the current
In turn, the subthreshold current Ip is given by the formula sources GRD , GRS , and GRDD , respectively, RD 0 , RS 0 , and
RDD0 denote the series resistances of the drain, the source, and
Tj Ugo
Ip = IP 0 exp − Y [1 − exp (−10 |VDS |)] (4) the body diode, respectively, at the reference temperature T0
T0 hTj
and αRD , αRS , and αRDD are the temperature coefficients of
where the resistances changes.
The resistance of the cutoff channel is modeled by the resis-
0, for V < PHI
GS
tance Rds , whereas the leakage conductance of the body diode
VGS − PHI
Y = exp − 1, for PHI < VGS < Vt and the SiO2 layer is modeled by the resistors Rds1 and Rgs ,
np hTj
respectively.
exp Vnt p−PHI
hT j + 1.5 − 1,
for VGS > Vt . The capacitances between the device terminals are described
(5) by the networks composed of parallelly connected controlled
In (5), PHI is described by the dependence current source and the branch of the series connection of the
two elements—the linear capacitor and the voltage source of
PHI = PHI0 (1 + aPHI (Tj − T0 )) (6) the zero voltage. Therefore, the capacitance between the gate
where IP 0 , np , PHI0 , and aPHI are the model parameters, and the source CGS is modeled by the elements: C1 , VCGS ,
whereas T0 denotes the reference temperature. and GCGS , the capacitance between the gate and the body
In the model, the threshold voltage and the parameter CGB is modeled by the elements: C3 , VCGB , and GCGB , the
of transconductance depend on the junction temperature as capacitance between the gate and the drain CGD is modeled
follows: by the elements: C2 , VCGD , and GCGD , and the capacitance be-
tween the drain and the source CDS is modeled by the elements:
Vt = Vt0 (1 + a (Tj − T0 )) (7) C4 , VCDS , and GCDS . The currents of the respective controlled
−1.5 current sources are expressed as the product of the current of
Tj
KP = KP0 (8) the proper voltage source and the nonlinear capacitance situated
T0 between the considered pair of the terminals, decreased by the
where Ugo = 1.206 V for silicon, Vt0 , KP0 , and a are the tem- capacitance of the linear capacitor and finally divided by this
perature independent parameters. capacitance.
The current of the controlled current source GDb represents In the considered model, the device capacitances are de-
the current of the device body diode. This current is a sum scribed by the authors’ empirical dependences of the form
of three components: the saturation current IS , the generation (15)–(20), as shown at the bottom of the next page, where
current Ig , and the breakdown range current IBR , described by tOX is the thickness of the layer SiO2 , CGDO is the gate–
the following formulae: drain capacitance for the unit of the channel length, CGSO
1.5
is the gate-source capacitance for the unit of the channel
Tj Ugo width, CGBO is the gate-body capacitance for the unit of
IS = I0 exp − (9)
T0 hTj the channel length, CDSO is the drain-body capacitance for
2 the zero drain-body voltage, MJ is the parameter describ-
Tj −Ugo V ing the doping profile of the drain-body junction, ε0 is the
1 − SD + 10−3 (10)
4
Ig = IG exp
T0 mg hTj VJ permittivity of free space, εOX is the relative permittivity
of silicon dioxide, VGSm in , VGSm ax , VGDm ax , VGBm in , VGBm ax ,
V − Up (1 + ap (Tj − T0 ))
IBR = IZ exp − SD (11) CG 1 , CG 2 , CB 1 , and CB 2 are the other model parameters.
N hTj
Equations (15)–(17) and (19) describing the capacitances of
where I0 , IZ , Up , ap , N, IG , VJ, and mg are the model an MOS transistor are of the form that results from the modifica-
parameters. tion of the Meyer model [5]. The (18) describes the capacitance
In (11), the linear dependence of the breakdown voltage on of the body diode. The values of the model parameters are ob-
the temperature is assumed. tained empirically.
1268 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 5, MAY 2010
TABLE I
VALUES OF THE DC MODEL PARAMETERS OF THE TRANSISTORS MTD20N06V AND MTD15N06V
CGS0 W, if VGS < VGS m in + VDS
Cox
CGS0 W + (CG 1 (VGS
− VDS
) + CG 2 ) ,
if VGS m in + VDS < VGS
< VGS m ax + VDS
3
CGS = CGS0 W + Cox (15)
, if VGS < VGS m ax + VDS and VDS <0
4
2
Cox VGS − VDS
C W+ 0.75 + ,
if VGS < VGS m ax + VDS
and VDS >0
GS0 4 +V
2VGS DS
CGD0 W, if VGS < VGD m ax + VDS
2
VGS + VGD m ax − VDS
CGD = CGD0 W + 1.3Cox 1 − 2 (V + V − )−V , if VGD m ax + VDS < VGS < Vt (16)
GS GD m ax V DS GS m ax
C VGS − Vt ,
GD0 W + 6Cox if VGS > Vt
CGB0 L + Cox , if VGB < VGB m in and VDS < (VGS + 1)2 + 1
2
V
−(V
+ 1V ) 2
1V − 1V
DS GS
CGB0 L+Cox 1− 2
, if VGS < VGB m in and VDS > (VGS +1V ) 1V +1V
VDS
CGB =
2 (17)
VGS + 0.5V 2V − VDS
CGB0 L + Cox Min 0.5
VGB m in
+ 0.33 2
VDS + 1.25V 2
,1 , if VGB m in < VGS < VGB m ax
2
2V − VDS
VGS + 0.5V
CGB0 L + Cox 0.5 + 0.33 2 , if VGS > VGB m ax
VGB m in VDS + 1.25V 2
−M J
VDS IS Tt VDS
CDS = CDSO 1 + + exp − + CBDX (18)
VJ hTj hTj
0, if VGS > −0.4V
2
CBDX = VGS + 0.4V − VDS (19)
0.8Cox 1 − 2 (V − 0.4V − V ) + 0.4V
, if VGS < −0.4V
GS DS
ε0 εox LW
Cox = (20)
tOX
ZARE˛BSKI AND GÓRECKI: ELECTROTHERMAL LARGE-SIGNAL MODEL OF POWER MOS TRANSISTORS FOR SPICE 1269
TABLE II
VALUES OF THE DC MODEL PARAMETERS OF THE TRANSISTOR IRF840
Fig. 2. Transfer characteristics of the transistor MTD20N06V operating with- Fig. 4. Output characteristics of the transistor MTD20N06V situated on the
out the heat sink. heat sink.
Fig. 7. Output characteristics of the transistor MTD15N06V situated on the heat sink.
Fig. 9. Output characteristics of the transistor IRF840 in the reverse mode. Fig. 10. Transfer characteristics of the transistor IRF840.
TABLE III
VALUES OF THE DYNAMIC PARAMETERS OF THE TRANSISTOR IRF840
Fig. 12. Calculated and measured dependences of the input capacitance of the Fig. 15. Calculated and measured dependences of the output capacitance of
transistor IRF840 on the voltage v D S . the transistor IRF840 on the voltage v G S .
Fig. 16. Calculated and measured gate charge curves of the transistor IRF840.
Fig. 13. Calculated and measured dependences of the input capacitance of the
transistor IRF840 on the voltage v G S .
very good agreement between the calculations and measuring
results.
The transistor input capacitance is of the constant value for
nonnegative values of the voltage VGS and the voltage VDS
higher than a few volts. At VGS < 0, a decrease in the value
of the capacitance Ciss with an increase in the voltage vDS is
observed. The minimum of the dependence Ciss (vGS ) for the
voltage VGS ≈ −0.5 V occurs.
In turn, the device output capacitance is practically of the
constant value for vGS < 0 (see Fig. 15), whereas the essential
changes of this capacitance at vGS > 0 and vDS < 2 V (see
Fig. 14) are observed.
The gate charge is of a great importance in the device com-
mutation. In Fig. 16, the calculated and measured curves of the
gate charging of the transistor IRF840 at the gate current equal
Fig. 14. Calculated and measured dependences of the output capacitance of to 1 mA and different values of the drain currents are shown.
the transistor IRF840 on the voltage v D S . As seen, the obtained characteristics are of the similar shape,
ZARE˛BSKI AND GÓRECKI: ELECTROTHERMAL LARGE-SIGNAL MODEL OF POWER MOS TRANSISTORS FOR SPICE 1273
Fig. 17. Calculated and measured waveforms of the terminal voltages of the transistor IRF840 operating in the switch network.
80%. The higher value of the storage time obtained from the
model LMOD results from the uncorrected modeling of the
device input capacitance. The value of this capacitance is too
high, which is shown in Figs. 12 and 13.
IV. CONCLUSION
The authors’ ETM of the MOS power transistor has been pro-
posed. The ETM was implemented to PSPICE version 9.0 as a
subcircuit. The model was verified by means of the comparison
of the measured and SPICE calculated characteristics. A good
agreement between the ETM simulations and the experimental
results is observed both for the dc and the dynamic characteris-
Fig. 18. Calculated and measured dependences of the body-diode storage time tics. The important advantage of the model is its simple form,
on the peak-to-peak value of the supply voltage. simple interpretation of the parameters, and simple method of
their estimation.
but qualitative differences are visible. From the model LMOD, It was also proved that due to self-heating, the MOS transistor
the extortionate value of the rise time of the voltage vGS was characteristics can change not only quantitatively, but also qual-
obtained. itatively and the macromodel proposed by ON Semiconductor
In Fig. 17, the calculated and measured time dependences is of poor accuracy. The investigations performed for different
of the voltage vGS [see Fig. 17(a)] and the voltage vDS [see kinds of transistors showed that the proposed ETM is the uni-
Fig. 17(b)] existing in the simple switch with the transistor versal one, ensuring the characteristics of great accuracy both
IRF840 are shown. In the investigated network, the drain-supply for the low-voltage and high-voltage power MOS transistors.
voltage ED is equal to 21 V, the gate resistance RG = 100 Ω The presented results of the investigations show new (not
and the gate is excited by the pulse rectangular train voltage of known so far) features of power MOS transistors. Especially,
the frequency 115 kHz and the pulse amplitude changing from they show a high value of the drain current determining the
−10 to 10 V (see picture in picture). boundary between the saturation and the subthreshold ranges,
As it is seen, the calculation results obtained by ETM fit well the ambiguity of the output characteristics corresponding to the
the measurements. The short pulses visible in the measured values of the control voltage vGS less than the value of the
dependence vDS (t) result from the overvoltage on the parasitic device threshold voltage, and the form of the dependence of
inductances, omitted in the proposed model. the device input and output capacitances on the voltage at its
The dependence of the body-diode storage time in the tran- terminals different from the known dependences corresponding
sistor IRF840 on the peak-to-peak value of the device supply to the planar low-power MOS transistors.
voltage at two ambient temperatures are presented in Fig. 18.
The investigations were performed for the gate shorted with the REFERENCES
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http://www.infineon.com Janusz Zare˛bski (M’05–SM’06) received the M.Sc. and Ph.D. degrees in elec-
[14] A. Laprade, S. Pearson, S. Benczkowski, G. Dolny, and F. Wheatley, tronics from the Technical University of Gdańsk, Gdańsk, Poland, in 1978 and
“A revised MOSFET model with dynamic temperature compensation,” 1986, respectively, and the D.Sc. degree from the Institute of Electron Technol-
Fairchild Semiconductor Corporation, South Portland, ME, Application ogy, Warsaw, Poland, in 1997.
Note 7533, 2003. He is currently the Head of the Department of Marine Electronics, Gdynia
[15] J. Zare˛bski, “Tranzystory MOS mocy,” (in Polish ) Fundacja Rozwoju Maritime University, Gdynia, Poland, where he has been a Full Professor since
Akademii Morskiej w Gdyni, Gdynia, 2007. 2008. His research interests include areas of modeling, analysis, and measure-
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[19] J. Zare˛bski, K. Górecki, and D. Bisewski, “A new electrothermal model
of the power MOSFET for SPICE,” in Proc. 11th Int. Conf. Mixed Des. Krzysztof Górecki (M’05–SM’06) was born in Poland, in 1966. He received
Integr. Circuits Syst. (MIXDES), Szczecin, 2004, pp. 89–93. the M.Sc. and Ph.D. degrees in electronics from the Technical University of
[20] J. Zare˛bski and K. Górecki, “Modelling CoolMOS transistors in SPICE,” Gdańsk, Gdańsk, Poland, in 1990 and 1999, respectively and the D.Sc. degree
Inst. Electr. Eng. Proc. Cicuits, Devices Syst., vol. 153, no. 1, pp. 46–52, from Technical University of Łódź, Lódź, Poland, in 2008.
2006. He is currently an Associate Professor with the Department of Marine Elec-
[21] K. Górecki and J. Zare˛bski, “Modelling CoolMOSC3 transistor charac- tronics, Gdynia Maritime University, Gdynia, Poland. His research interests
teristics in SPICE,” Int. J. Num. Model. Electron. Netw., Devices Fields, include areas of modeling, analysis, and measurements of semiconductor de-
vol. 23, no. 2, pp. 127–139, 2010. vices and electronic circuits, particularly including thermal effects.