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Amplifier System
Steen M. Munk1 and Kennet Skov Andersen1
1
Bang & Olufsen ICEpower a/s, DK-2800 Lyngby, Denmark
Correspondence should be addressed to Steen M. Munk (smu@bang-olufsen.dk)
ABSTRACT
Pulse Modulated Amplifiers of both analog and digital input type, have won great interest during the past
few years. The technology is now so advanced that excellent audio performance can be combined with the
inherent high efficiency of the switching Class-D operation of the output stage.
This paper describes advances made within digital input Pulse Modulated Amplifier based on digital pulse
modulation.
An advanced feedback method is evaluated that does not require A/D conversion - PEDEC (Pulse Edge
Delay Error Correction).
PEDEC decreases significantly harmonic distortion as well as it contributes to minimising the effects of
supply pumping problems.
A PEDEC based digital PMA system is benchmarked against the well known non-feedback digital PMA by
actual hardware measurements.
Lastly a new method, Intelligent Volume Control, is introduced as a solution to overcome the inherent
dynamic range limitations and in addition to offer significant efficiency and Electromagnetic Interference
(EMI) advantages.
is misleading. The digital PMA is not a digital am- This gives rise to quantization noise.
plifier, because it is digital only until the output of
Which again, by making use of the high sampling
the modulator see Figure 1.
frequency, may be shifted away from the audio band
The amplification is entirely analogue. For PMA’s using noise shaping methods.
with “analogue like” digital input the problem is to
Using a sample rate converter at the input allows for
make a good estimate of the instant where the input
various input formats. Presently input is transfor-
signal crosses the triangle reference, see also Figure 6
med into 24 bits @ 96 kHz.
on page 4. In the digital case this instant is most li-
kely located between two sample instants of UPWM The aforementioned dynamic range of 106 dB is ob-
(Uniform Pulse Width Modulation); hence an er- tained using 4× over sampling.
ror will be introduced. The error may be reduced Bit rate at this over sampling rate is: 224 × 96 kHz ×
using the information from two consecutive samples 4 = 6.44 THz!!! By reducing resolution to 8 bits, bit
to form the estimate of the crossing time. This is rate is reduced to 28 × 96 kHz × 4 = 98.304 MHz,
the so-called Weighted PWM. WPWM is well des- which can be accomplished by today’s technology.
cribed in literature, see e.g. [1] and an overview is
given in Section 3.2. 3.1 Noise Shaping
Feedback loops in the compensation stage are im- In Figure 2 the noise shaper is shown. Good per-
plemented using the so-called PEDEC (Pulse Edge formance is obtained using a 7th -order FIR-filter as
Delay and Error Correction), which is patented by H(z). In Equation 1 is shown the Noise Transfer
Bang & Olufsen ICEpower a/s; see [2]. The prin- Function (NTF) as a function of H(z).
ciples of PEDEC are described in [3] and [4] and an
overview is given in Section 4.2.
+ x(n)+e(n)
IVC (Intelligent Volume Control), which also is pa-
tented by Bang & Olufsen ICEpower a/s, is descri-
x(n) + Quantisation
- x error(n)
bed, see [5]. This is done in Section 6. The approach +
is based on switching between power supply ampli- x diff(n)
tudes to the power stage, so that when volume is de- - +
creased supply is switched to a lower voltage. This x error, quantified
(n)
H(z)
approach gives good attenuation as well as good re-
solution between levels, and does not compromise
dynamic range. Fig. 2: Noise Shaper Topology
3 DIGITAL MODULATOR
Figure 1 shows the elements of the digital modulator.
NTF (z) = 1 − H(z) (1)
Sampling frequency is increased as a means for in-
creasing the dynamic range. This, of course, leads PN −1
H(z) being a FIR-filter; H(z) = n=0 an z −n , a0 =
to higher bit rate.
0, and N the filter order.
In order to obtain satisfactory dynamic range, sam-
The noise shaper lets through the signal without
pling frequency should be increased to at least
modification; hence the Signal Transfer Function
384 kHz, which allows for a dynamic range of some
STF = 1 for all frequencies.
106 dB, see e.g. [1]. Even higher sampling frequency
of course gives better dynamic range. Good performance is maintained if the signal is
quantized to 8 bits, and filter coefficients are quan-
Alas, sampling frequency cannot be increased to any
tized to 16 bits.
level, since the hardware cannot operate at arbitrary
high frequencies. Therefore, in order to keep the bit In Figure 3(a) on page 3 is shown H(z) and in Fi-
rate low, samples are quantized to a lower resolution. gure 3(b) NTF (z) = 1 − H(z).
Sample rate
PCM Over sampler WPWM Noise shaper UPWM
converter f s,1 f s,2=I f s,1 f s,3=I f s,2 2
brq
44,1 kHz, 16
bits
Fig. 1: Signal flow in digital modulator. I is the over sampling factor and brq is the number of bits actually
used
14
10
12
0
10
−10
Magnitude (dB)
8 Magnitude (dB)
−20
−30
4
−40
2
−50
0
−2 −60
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18
Frequency (MHz) Frequency (MHz)
3.2 WPWM
THD =−31dB, IMD = −InfdB, D = 106dB, Sig = −4dB, harm[1..5] = −35 −63dB
0 horizontal lines. Where the solid line represents the
value at the present sample, and the dashed line the
−20
value at the next sample. [1] shows that the estimate
of the true crossing time may be expressed as in
−40
Equation 2.
−60
N i
1 X (xn + 1) (xn+1 − xn )
dB
−80
td
n,N = (2)
2 i=0 2i
−100
−20
attains 106 dB.
−40
The WPWM was developed based on the wish to
have a simple algorithm that can approximate the −60
NPWM. In WPWM an estimate is made of the
true instant where the input signal “crosses” the car-
dB
−80
−140
−160
0 5 10 15 20 25 30 35
Frequency (KHz)
Feedback
DC C Error Processing
ve
vr vc
vo
Edge Delay Power Stage and
Fig. 8: Half bridge power stage, demodulation filter PWM input (Edge re-timing) re-timed PWM demodulation filter Audio output
and speaker.
• Non stable supply leads to amplitude errors of Inputs to the Edge Delay (ED) unit, see Figure 9, are
the output PWM signal. an error signal ve and a reference signal vr . Output
from the ED unit is an edge corrected signal vc . The
• Dead time in switches leads to delay of rising ED unit can be realized as seen in Figure 10. To
edges in output PWM signal. realize the ED signal vc , the reference signal vr is
limited integrated. The ED signal is compared to
• Variations in load change the characteristics of the error signal ve . If ve > 0 the pulse width will
the demodulation filter so that the frequency increase and if ve < 0 the pulse width will decrease.
response changes. The control gain KPEDEC in the ED unit can be
expressed as [3]:
• Semiconductor RDS(on) resistance and output
filter resistance lead to output resistance.
t0 V C
• Non linearity of the demodulation filter leads to KPEDEC = 2 , for − VI ≤ ve ≤ VI (3)
errors in the demodulated output signal. tp V I
ED signal and
error signal t0 t0 Since VFC3 is the only topology with feedback af-
ter demodulation filter, it is the only topology that
Vi eliminates errors in the demodulation filter.
ve
time
0
Detailed view of VFC3. A block diagram of
VFC3 is shown in Figure 11. The components of
vi the controller are shown in the following.
-Vi
- + A(s)
+ Feedback filter
Signal on output
of ED unit C(s)
Compensator
Vc Ve
R(s)
Reference filter
time KPEDEC
0 Edge Delay Unit
vc
-Vc Vr + V
c Kp
Vp F(s)
Vo
+ + Power Stage Demodulation filter
KPEDEC
Edge Delay Unit
Demands
for t0/tp
0.5
0.45
0.4 Kp
Power Stage
0.35
0.3
0.25
0.2
F(s)
0.15
Demodulation filter
0.1
1
0.05
0 0.5
0 Duty cycle
0.5
1 d A(s)
Normalized error on positive supply 1.5 2 0
Feedback filter
k
t0
Fig. 12: Demands to tp as a function of the error on
the positive supply Vdiff - Ve
R(s) + C(s)
Reference filter + Compensator
∞
X 8Vr π πtf 2π
f (t) = − sin n sin n sin n t
n=1
nπ 2 tp tp
(16)
Reference vrdelay -
R + A
signal Reference filter + Feedback filter
Vr
C
Compensator
time
ve
0
vr vc vo
vr Edge Delay Unit
Power Stage and
demodulation filter
-Vr
Fig. 16: THD+N vs. FFS of modulator. From the bottom to the top at the right of the figure: 100 Hz,
1 kHz and 6,67 kHz. (The two curves 100Hz and 1kHz are congruent)
The system consists of two parts, hence the bench- filter is 3rd order and does not influence the audio
marking was carried through in two steps: band.
In Figure 16 is shown THD + N vs. FFS at three
1. The digital modulator part, which as input different frequencies.
takes the PCM signal and as output produces
the PWM signal. The effect of the noise shaper is clearly seen in Fi-
gure 18, where the noise floor in the audio band is
2. The amplifier section which amplifies and located around −125 dB, and ascends after 20 kHz.
converts the PWM signal.
An FFT of a 6.67 kHz signal at modulation index
The amplifier section also contains the PEDEC M = 0.85 is shown in (Figure 19). The 3. harmonic
unit. The feedback loop of the PEDEC may is at −70 dB.
be interrupted so that a comparison of perfor-
mance with and without the PEDEC is possible. The dynamic range attains some 100 dB (A-
weighted). The deviation from the theoretical dy-
System switching frequency is 384 kHz, hence input namic range is due to jitter.
is sample rate converted to 24 bits @ 96 kHz and
5.2 Measurements on entire amplifier sys-
over sampled 4 times.
tem
The power stage power rating is 2 × 60 Wcontinous .
To illustrate the power of PEDEC to eliminate er-
5.1 Modulator Measurements rors produced in the power stage and demodulation
During the measurements on the modulator alone, a filter, a set of measurements were carried through
filter was used to convert the PWM signal to an ana- where first the feedback loop was opened, then sub-
logue output that was subsequently analysed. The sequently was closed.
Fig. 18: Wideband FFT of modulator output. Input signal f = 6.67 kHz and M = 0.1
Fig. 19: FFT of modulator output. Input signal f = 6.67 kHz and, M = 0.85
Fig. 20: Frequency response during openloop operation with different loads. From the top to the bottom at
the right of the figure open load, 16 Ω, 8 Ω and 4 Ω
Fig. 21: Frequency response during PEDEC operation with different loads. From the bottom to the top at
the right of the figure: open load, 16 Ω, 8 Ω and 4 Ω
Fig. 22: THD+N vs. power during openloop operation. Frequencies 100 Hz, 1 kHz and 6.67 kHz
Fig. 23: THD+N vs. power during PEDEC operation at different frequencies. From the bottom to the top
at 5 W on the figure: 100 Hz, 1 kHz and 6.67 kHz
Fig. 26: FFT during PEDEC operation, in top without delay of reference, in bottom with with delay of
reference, M = 0.85, f = 6.67 kHz, ZL = 8 Ω
Volume
control
input
Attenuation control Error Processing Gain switch Power supply
Digital vr vc vo
input Digital modulator
Edge Delay Power Stage and
and digital
PWM (Edge re-timing) re-timed PWM demodulation filter Audio output
attenuator
135dB
Fig. 27: Block diagram of IVC volume control sys-
tem
Fig. 28: IVC attenuation
plementation of IVC the supply voltage should only
shift between few levels e.g. 2 levels as the example in
Figure 28. In the example in Figure 28, the volume