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State of the Art Digital Pulse Modulated

Amplifier System
Steen M. Munk1 and Kennet Skov Andersen1
1
Bang & Olufsen ICEpower a/s, DK-2800 Lyngby, Denmark
Correspondence should be addressed to Steen M. Munk (smu@bang-olufsen.dk)

ABSTRACT
Pulse Modulated Amplifiers of both analog and digital input type, have won great interest during the past
few years. The technology is now so advanced that excellent audio performance can be combined with the
inherent high efficiency of the switching Class-D operation of the output stage.
This paper describes advances made within digital input Pulse Modulated Amplifier based on digital pulse
modulation.
An advanced feedback method is evaluated that does not require A/D conversion - PEDEC (Pulse Edge
Delay Error Correction).
PEDEC decreases significantly harmonic distortion as well as it contributes to minimising the effects of
supply pumping problems.
A PEDEC based digital PMA system is benchmarked against the well known non-feedback digital PMA by
actual hardware measurements.
Lastly a new method, Intelligent Volume Control, is introduced as a solution to overcome the inherent
dynamic range limitations and in addition to offer significant efficiency and Electromagnetic Interference
(EMI) advantages.

1 INTRODUCTION Supply pumping is an issue of concern. Measure-


ments show that the PEDEC contributes to minimi-
Advances made by Bang & Olufsen ICEpower a/s sing the effects of this problem.
and the Technical University of Denmark is the foun-
dation of the state of the art within Class-D au- Finally a new approach for implementing an effi-
dio amplification having digital interface described cient volume control, the IVC (Intelligent Volume
in this paper. Control), is introduced.

The term PMA – Pulse Modulated Amplifier – has 2 THEORETICAL BACKGROUND


been previously introduced in literature and is the
term that the authors suggest rather than PWM am- In analogue PMA the input signal is compared to a
plifier (Pulse Width Modulated amplifier). carrier signal. This carrier is often a triangle signal.
The transition to PMA’s with digital interface has
Bang & Olufsen ICEpower a/s suggests using a
been made much like copy and paste of the analogue
feedback compensation stage after the modulator.
approach, though other approaches could be more
The method, PEDEC (Pulse Edge Delay Error
optimal for the digital interface case! This is subject
Correction), is described before performance is eva-
for on-going research.
luated of an amplifier system using PEDEC. PEDEC
is compared to an amplifier without feedback. It should be noticed that the term “digital amplifier”

AES 23RD INTERNATIONAL CONFERENCE, COPENHAGEN, DENMARK, 2003 MAY 23–25 1


MUNK AND ANDERSEN DIGITAL PULSE MODULATED AMPLIFIER SYSTEM

is misleading. The digital PMA is not a digital am- This gives rise to quantization noise.
plifier, because it is digital only until the output of
Which again, by making use of the high sampling
the modulator see Figure 1.
frequency, may be shifted away from the audio band
The amplification is entirely analogue. For PMA’s using noise shaping methods.
with “analogue like” digital input the problem is to
Using a sample rate converter at the input allows for
make a good estimate of the instant where the input
various input formats. Presently input is transfor-
signal crosses the triangle reference, see also Figure 6
med into 24 bits @ 96 kHz.
on page 4. In the digital case this instant is most li-
kely located between two sample instants of UPWM The aforementioned dynamic range of 106 dB is ob-
(Uniform Pulse Width Modulation); hence an er- tained using 4× over sampling.
ror will be introduced. The error may be reduced Bit rate at this over sampling rate is: 224 × 96 kHz ×
using the information from two consecutive samples 4 = 6.44 THz!!! By reducing resolution to 8 bits, bit
to form the estimate of the crossing time. This is rate is reduced to 28 × 96 kHz × 4 = 98.304 MHz,
the so-called Weighted PWM. WPWM is well des- which can be accomplished by today’s technology.
cribed in literature, see e.g. [1] and an overview is
given in Section 3.2. 3.1 Noise Shaping
Feedback loops in the compensation stage are im- In Figure 2 the noise shaper is shown. Good per-
plemented using the so-called PEDEC (Pulse Edge formance is obtained using a 7th -order FIR-filter as
Delay and Error Correction), which is patented by H(z). In Equation 1 is shown the Noise Transfer
Bang & Olufsen ICEpower a/s; see [2]. The prin- Function (NTF) as a function of H(z).
ciples of PEDEC are described in [3] and [4] and an
overview is given in Section 4.2.
+ x(n)+e(n)
IVC (Intelligent Volume Control), which also is pa-
tented by Bang & Olufsen ICEpower a/s, is descri-
x(n) + Quantisation

- x error(n)
bed, see [5]. This is done in Section 6. The approach +
is based on switching between power supply ampli- x diff(n)
tudes to the power stage, so that when volume is de- - +
creased supply is switched to a lower voltage. This x error, quantified
(n)
H(z)
approach gives good attenuation as well as good re-
solution between levels, and does not compromise
dynamic range. Fig. 2: Noise Shaper Topology

3 DIGITAL MODULATOR
Figure 1 shows the elements of the digital modulator.
NTF (z) = 1 − H(z) (1)
Sampling frequency is increased as a means for in-
creasing the dynamic range. This, of course, leads PN −1
H(z) being a FIR-filter; H(z) = n=0 an z −n , a0 =
to higher bit rate.
0, and N the filter order.
In order to obtain satisfactory dynamic range, sam-
The noise shaper lets through the signal without
pling frequency should be increased to at least
modification; hence the Signal Transfer Function
384 kHz, which allows for a dynamic range of some
STF = 1 for all frequencies.
106 dB, see e.g. [1]. Even higher sampling frequency
of course gives better dynamic range. Good performance is maintained if the signal is
quantized to 8 bits, and filter coefficients are quan-
Alas, sampling frequency cannot be increased to any
tized to 16 bits.
level, since the hardware cannot operate at arbitrary
high frequencies. Therefore, in order to keep the bit In Figure 3(a) on page 3 is shown H(z) and in Fi-
rate low, samples are quantized to a lower resolution. gure 3(b) NTF (z) = 1 − H(z).

AES 23RD INTERNATIONAL CONFERENCE, COPENHAGEN, DENMARK, 2003 MAY 23–25 2


MUNK AND ANDERSEN DIGITAL PULSE MODULATED AMPLIFIER SYSTEM

Sample rate
PCM Over sampler WPWM Noise shaper UPWM
converter f s,1 f s,2=I f s,1 f s,3=I f s,2 2
brq

44,1 kHz, 16
bits

Fig. 1: Signal flow in digital modulator. I is the over sampling factor and brq is the number of bits actually
used

Magnitude Response (dB) Magnitude Response (dB)


16 20

14
10

12
0

10

−10
Magnitude (dB)

8 Magnitude (dB)

−20

−30
4

−40
2

−50
0

−2 −60
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18
Frequency (MHz) Frequency (MHz)

(a) H(z) (b) NTF (z) = 1 − H(z)

Fig. 3: Noise Shaper Magnitude Transfer Function

3.2 WPWM

NPWM (Natural Pulse Width Modulation) gives


the best placement of pulses in the analogue do-
main. For digital implementation, NPWM is not
feasible. Instead UPWM is interesting because it is System clk: fs
the simplest topology that can be realised. However, s
Counter /
the price is introduction of an error, since UPWM Parallel input R
comparator PWM
places pulses equividistantely. Figure 4 shows the
basic element of UPWM. Bit clk: f s 2brq
Pre-processing of the UPWM-input may reduce this
error. Fig. 4: UPWM
Figure 5 shows the result of a simulation on an
UPWM MATLAB–implementation using two level
modulation. It is seen that THD is as poor as
−31 dB, which is quite as expected. Dynamic range

AES 23RD INTERNATIONAL CONFERENCE, COPENHAGEN, DENMARK, 2003 MAY 23–25 3


MUNK AND ANDERSEN DIGITAL PULSE MODULATED AMPLIFIER SYSTEM

THD =−31dB, IMD = −InfdB, D = 106dB, Sig = −4dB, harm[1..5] = −35 −63dB
0 horizontal lines. Where the solid line represents the
value at the present sample, and the dashed line the
−20
value at the next sample. [1] shows that the estimate
of the true crossing time may be expressed as in
−40
Equation 2.
−60

N i
1 X (xn + 1) (xn+1 − xn )
dB

−80
td
n,N = (2)
2 i=0 2i
−100

−120 xi is the sample at time ti .


−140 This estimate is initiated by UPWM back-edge mo-
dulation after linear transformation from the range
−160
0 5 10 15 20 25 30 35
[−1; 1] to the range [0; 1].
Frequency (KHz)

It has been shown, [6], that N = 3 gives optimal


Fig. 5: Performance of UPWM for finput = 6.67 kHz, performance.
M = 0.9
THD =−68dB, IMD = −InfdB, D = 106dB, Sig = −4dB, harm[1..5] = −98 −73dB
0

−20
attains 106 dB.
−40
The WPWM was developed based on the wish to
have a simple algorithm that can approximate the −60
NPWM. In WPWM an estimate is made of the
true instant where the input signal “crosses” the car-
dB

−80

rier. The estimate is formed using two consecutive


−100
samples.
−120

−140

−160
0 5 10 15 20 25 30 35
Frequency (KHz)

Fig. 7: Performance of WPWM for finput =


6.67 kHz, M = 0.9 and N = 3

Figure 7 shows a MATLAB simulation result of the


performance of the WPWM. Compared to Figure 5
it is clearly seen that WPWM gives significant bet-
ter performance. THD is −68 dB and the dyna-
mic range is unchanged around 106 dB, compared
Fig. 6: WPWM
to −31 dB and 106 dB respectively for the modula-
tor without compensation.
Figure 6 shows three different input signals (a, b and Further improvement is possible using the WEE-
c) having different amplitudes. Uniform back edge compensation. This, however, is not presently im-
sampling of this signal is seen as the solid and dashed plemented by Bang & Olufsen ICEpower a/s.

AES 23RD INTERNATIONAL CONFERENCE, COPENHAGEN, DENMARK, 2003 MAY 23–25 4


MUNK AND ANDERSEN DIGITAL PULSE MODULATED AMPLIFIER SYSTEM

4 ANALOGUE STAGE an analogue signal as reference. In the case of a di-


The power stage (Figure 8) amplifies the digital gital PMA’s this is not possible. PEDEC is a pulse
PWM signal. Because the power stage is non ideal, referenced control system that eliminates errors by
it will contribute with a considerable amount of error re-timing the edges fed to the output switches, see
to the output signal [3, Chapter 4]. Figure 9. No matter the type of error, the PEDEC
control system cancels the error with pulse re-timing.
4.1 Amplification Errors
Since both the reference signal and the feedback si-
gnal are PWM modulated, the PEDEC control sys-
tem makes an absolute comparison. If there is no
error the difference is zero. The main benefits from
L PEDEC are that it makes an absolute correction and
DC includes no quantization errors.

Feedback

DC C Error Processing

ve

vr vc
vo
Edge Delay Power Stage and
Fig. 8: Half bridge power stage, demodulation filter PWM input (Edge re-timing) re-timed PWM demodulation filter Audio output

and speaker.

Fig. 9: Block diagram of PEDEC control system.


Some error sources:

• Non stable supply leads to amplitude errors of Inputs to the Edge Delay (ED) unit, see Figure 9, are
the output PWM signal. an error signal ve and a reference signal vr . Output
from the ED unit is an edge corrected signal vc . The
• Dead time in switches leads to delay of rising ED unit can be realized as seen in Figure 10. To
edges in output PWM signal. realize the ED signal vc , the reference signal vr is
limited integrated. The ED signal is compared to
• Variations in load change the characteristics of the error signal ve . If ve > 0 the pulse width will
the demodulation filter so that the frequency increase and if ve < 0 the pulse width will decrease.
response changes. The control gain KPEDEC in the ED unit can be
expressed as [3]:
• Semiconductor RDS(on) resistance and output
filter resistance lead to output resistance.
t0 V C
• Non linearity of the demodulation filter leads to KPEDEC = 2 , for − VI ≤ ve ≤ VI (3)
errors in the demodulated output signal. tp V I

Where t0 is the fall and rise time of the edges in


4.2 Pulse Edge Delay Error Correction
the ED signal, tp is the periode time of the PWM
Since the power stage and demodulation filter are
sample.
inherently analogue and the errors that the power
stage and demodulation filter apply are difficult to
predict, it is very difficult to eliminate these errors 4.2.1 PEDEC topologies
in the digital domain. An analogue control system
is desired. Analogue control systems such as MECC At present three topologies of the PEDEC control
(Multivariable Enhanced Cascade Control) [3] use system exist, see [3].

AES 23RD INTERNATIONAL CONFERENCE, COPENHAGEN, DENMARK, 2003 MAY 23–25 5


MUNK AND ANDERSEN DIGITAL PULSE MODULATED AMPLIFIER SYSTEM

VFC1 PEDEC Voltage Feedback Control — Type


1. Is characterized by a voltage feedback from
the switching power stage. The post power
stage PWM is compared with the PWM refe-
rence.

Reference VFC2 PEDEC Voltage Feedback Control — Type


signal 2. Similar to VFC1 but with a first order sha-
ping of the PWM feedback and a similar first
Vr order shaping of the reference feedback.

time VFC3 PEDEC Voltage Feedback Control — Type


0 3. Is significantly different from VFC1 and
VFC2. VFC3 is characterized by a voltage feed-
vr
-Vr back after the demodulation filter. The refe-
rence PWM is shaped with a second order filter
and compared with the demodulated output si-
gnal.

ED signal and
error signal t0 t0 Since VFC3 is the only topology with feedback af-
ter demodulation filter, it is the only topology that
Vi eliminates errors in the demodulation filter.
ve
time
0
Detailed view of VFC3. A block diagram of
VFC3 is shown in Figure 11. The components of
vi the controller are shown in the following.
-Vi

- + A(s)
+ Feedback filter

Signal on output
of ED unit C(s)
Compensator

Vc Ve
R(s)
Reference filter

time KPEDEC
0 Edge Delay Unit

vc
-Vc Vr + V
c Kp
Vp F(s)
Vo
+ + Power Stage Demodulation filter

Fig. 10: Realization of the Edge Delay unit


Fig. 11: Linear model for PEDEC VFC3 topology

The compensator block:

(τz1 s + 1)(τz2 s + 1)(τz3 s + 1)


C(s) = Kc (4)
(τp1 s + 1)(τp2 s + 1)(τp3 s + 1)

AES 23RD INTERNATIONAL CONFERENCE, COPENHAGEN, DENMARK, 2003 MAY 23–25 6


MUNK AND ANDERSEN DIGITAL PULSE MODULATED AMPLIFIER SYSTEM

The feedback block: Amplitude correction limitation is more complex


since an amplitude error is suppressed by re-timing
1
A(s) = (5) the edges.
K
In case a half bridge is used as power stage, a com-
The ED unit and power stage: mon error would be at only one supply. If a supply
has a certain output impedance the supply voltage
B(s) = KPEDEC Kp (6) will drop when current flows from the supply.
Reference filter: In case of a half bridge, the supply voltages can also
rise. This occurs because the power stage and the de-
ω02 modulation filter pump current back to one supply.
R(s) = ω0 (7)
s2 + ( Q )s + ω02 Most supplies can only source and not sink current.
Therefore, the current flows to the charging capaci-
Demodulation filter: tor at the output of the supply. As the current flows
to the capacitor the voltage across the capacitor will
ω02 rise.
F (s) = ω0 (8)
s2 + ( Q )s + ω02
Demands to the ED unit, so an error on a supply
does not lead to saturation of the control system, de-
These lead to the open loop transfer function: fine the parameter k as the change in positive supply
voltage (∆Vd ) relative to the nominal positive sup-
L(s) = C(s)A(s)B(s)F (s) (9) ply voltage (Vd ):

The system transfer function with K = Kp and Vp + ∆Vp


k= (12)
R(s) = F (s): Vp
H(s) = F (s)Kp (10)
An error on the positive supply will not lead to satu-
The control system leads to no bandwidth limitation ration of the control system, if the following demands
of the output signal. Only the demodulation filter are fullfilled:
limits the bandwidth of the output signal.
t0 1 − k t0
For information about loop shaping see [3]. ≥ d for 0 < d ± <1 (13)
tp 1 + k tp

Figure 12 shows a 3D plot of Equation 13. It is seen


4.2.2 Correction Limit
that the demands to ttp0 become larger as the posi-
Because of the limited correction range of the ED tive supply voltage varies from the nominal supply
unit, the control system will saturate if it has to voltage. Errors in the negative supply voltage set
suppress more than a certain amount of error. Since equal demands to ttp0 as errors in the positive supply
the control system cannot suppress errors if it is fully voltage. For the ED unit, so an error on the nega-
saturated, the control system should not saturate tive supply will not lead to saturation of the control
during normal use. system, the demands are:

If a timing error is applied on an edge (te ) the de- t0 1 − k t0
≥ (1 − d)
for 0 < d ± < 1 (14)
mands for re-timing of the ED unit can easily be tp 1 + k tp
seen from Figure 10. To the ED unit so an error
on an edge will not lead to saturation of the control It should be noticed that different kinds of errors
system, the demands are: are summed together. E.g. if two types of errors
separately cannot saturate the control system, it is
t0 2te likely that if the two types of errors are present at
≥ (11) the same time, the control system can saturate.
tp tp

AES 23RD INTERNATIONAL CONFERENCE, COPENHAGEN, DENMARK, 2003 MAY 23–25 7


MUNK AND ANDERSEN DIGITAL PULSE MODULATED AMPLIFIER SYSTEM

KPEDEC
Edge Delay Unit
Demands
for t0/tp

0.5

0.45

0.4 Kp
Power Stage
0.35

0.3

0.25

0.2
F(s)
0.15
Demodulation filter
0.1
1
0.05

0 0.5
0 Duty cycle
0.5
1 d A(s)
Normalized error on positive supply 1.5 2 0
Feedback filter
k

t0
Fig. 12: Demands to tp as a function of the error on
the positive supply Vdiff - Ve
R(s) + C(s)
Reference filter + Compensator

4.2.3 High Frequency Saturation


Fig. 13: The transfer function for HF error for VFC3
The control system can saturate because of a high
frequency difference between the reference signal and
the feedback signal. In most cases the saturation has high frequency difference to the error signal can be
to do with switching residual on the error signal and seen from Figure 13.
will not be permanent but only exist for a relative
short time, in general about 2 times the sampling
period. Ve C(s)R(s)
He (s) = =
If the high frequency saturation lasts a short time, Vdif 1 + C(s)KPEDEC Kp F (s)A(s)
compared with the period time of the highest fre- (15)
quencies of the audio signals, the control system will
A factor that contributes with an amount of high
be partly influenced. The saturation will decrease
frequency difference is the delay (tdelay ) in the ED
the capability of the control system to eliminate er-
unit and the power stage. From Figure 10 it is seen
rors in the audio band. A continuous saturation will
that the delay in the ED unit is t20 , when there is no
also increase the noise level dramatically.
error (ve = 0).
To minimize saturation of the control system due
In many applications the delay in the power stage
to high frequency contents, the switching residual
will be rather large. This is due to the delay in
should be noticed during loop shaping of the control
the driver and the delay in turning on and off the
system. To prevent saturation because of high fre-
MOSFET’s.
quency contents, the control system should be desi-
gned so the ED unit does not saturate. In Figure 14 it is seen how a delay (tdelay ) between
the reference signal Vr and the signal after the power
A high frequency difference Vdif between the refe-
stage Vp will lead to the high frequency difference
rence signal and the feedback signal will influence
Vdif .
the error signal. Figure 13 shows how the control
blocks influence the error signal when there is a high The high frequency difference produced by the delay
frequency difference. The transfer function from the can be expressed as:

AES 23RD INTERNATIONAL CONFERENCE, COPENHAGEN, DENMARK, 2003 MAY 23–25 8


MUNK AND ANDERSEN DIGITAL PULSE MODULATED AMPLIFIER SYSTEM

∞    
X 8Vr  π πtf 2π
f (t) = − sin n sin n sin n t
n=1
nπ 2 tp tp
(16)

Reference vrdelay -
R + A
signal Reference filter + Feedback filter

Vr
C
Compensator

time
ve
0
vr vc vo
vr Edge Delay Unit
Power Stage and
demodulation filter
-Vr

Fig. 15: Block diagram of PEDEC control system


including delay of reference signal
Signal after
power stage tdelay tdelay
The high frequency difference produced by a delay
Vp
leads to a switching residual on the error signal.
The amplitude of this signal can be calculated from
time
0 Equation 15 and 16. If the amplitude is bigger than
the amplitude of the ED signal the control system
vp will saturate.
-Vp
When VFC3 is used, it should be noticed that a dif-
ference between the high frequency characteristics of
the reference filter and demodulation filter will lead
Difference to a high frequency difference. Different loads will
signal
lead to changes in the characteristics of the demo-
2Vr dulation filter. Also if a Zöbel network is applied
to the demodulation filter and not to the reference
filter the high frequency characteristics of the two
vdif filters will be different.
time
0 To minimize the high frequency difference from delay
in the ED unit and in the power stage the reference
can be added a similar delay, see Figure 15.
-2Vr In practical implementation, the delay of the refe-
rence influences the parameters in loop shaping of
the control system. With a delay of the reference
Fig. 14: HF error from a delay
the control system capability of suppressing errors
at high frequencies is increased up to 10 dB.

5 RESULTS FROM BENCHMARKINGS

The benchmarkings were made with one ICEpower


digital amplifier system.

AES 23RD INTERNATIONAL CONFERENCE, COPENHAGEN, DENMARK, 2003 MAY 23–25 9


MUNK AND ANDERSEN DIGITAL PULSE MODULATED AMPLIFIER SYSTEM

Fig. 16: THD+N vs. FFS of modulator. From the bottom to the top at the right of the figure: 100 Hz,
1 kHz and 6,67 kHz. (The two curves 100Hz and 1kHz are congruent)

The system consists of two parts, hence the bench- filter is 3rd order and does not influence the audio
marking was carried through in two steps: band.
In Figure 16 is shown THD + N vs. FFS at three
1. The digital modulator part, which as input different frequencies.
takes the PCM signal and as output produces
the PWM signal. The effect of the noise shaper is clearly seen in Fi-
gure 18, where the noise floor in the audio band is
2. The amplifier section which amplifies and located around −125 dB, and ascends after 20 kHz.
converts the PWM signal.
An FFT of a 6.67 kHz signal at modulation index
The amplifier section also contains the PEDEC M = 0.85 is shown in (Figure 19). The 3. harmonic
unit. The feedback loop of the PEDEC may is at −70 dB.
be interrupted so that a comparison of perfor-
mance with and without the PEDEC is possible. The dynamic range attains some 100 dB (A-
weighted). The deviation from the theoretical dy-
System switching frequency is 384 kHz, hence input namic range is due to jitter.
is sample rate converted to 24 bits @ 96 kHz and
5.2 Measurements on entire amplifier sys-
over sampled 4 times.
tem
The power stage power rating is 2 × 60 Wcontinous .
To illustrate the power of PEDEC to eliminate er-
5.1 Modulator Measurements rors produced in the power stage and demodulation
During the measurements on the modulator alone, a filter, a set of measurements were carried through
filter was used to convert the PWM signal to an ana- where first the feedback loop was opened, then sub-
logue output that was subsequently analysed. The sequently was closed.

AES 23RD INTERNATIONAL CONFERENCE, COPENHAGEN, DENMARK, 2003 MAY 23–25 10


MUNK AND ANDERSEN DIGITAL PULSE MODULATED AMPLIFIER SYSTEM

because of supply pumping. It is faintly seen how the


output signal differs from a sinus wave. The output
signal is distorted because of supply variation. In
Figure 24 an FFT is seen of the output signal. The
3. harmonic is at about −30 dB. The high level is
mainly because supply pumping greatly influences
performance.
Figure 25 shows an FFT of the output during opera-
tion on a 20 Hz signal including the PEDEC control
system. Compared to Figure 24 it is seen how
all harmonics are much attenuated by the PEDEC
control system. The 3. harmonic is at about −75 dB.
This corresponds to 45 dB attenuation of the 3. har-
monic.
Fig. 17: Power Stage Supply Voltages and Output The dynamic range without PEDEC is 95 dB. The
Voltage, f=20Hz, M=0.85 and ZL=4 Ω dynamic range with PEDEC is 100 dB. The dynamic
range is limited by the digital modulator. Dynamic
range of the PEDEC control system is actually about
120dB.
Frequency response without PEDEC is demonstra-
ted in Figure 20. It is seen that the frequency res- In Figure 15 is indicated a delayed reference signal.
ponse at low frequencies very much depends on the This delay is important for optimal performance
load. This is due to the resistance of the power stage which is illustrated in Figure 26, where the upper
and the resistance in the inductor in the demodula- curve illustrates performance without this delay and
tion filter. At high frequencies the frequency res- the lower shows performance with a delay of 250 ns,
ponse varies very much with load variation. This corresponding to the delay in the ED unit and po-
is due to the changes in characteristics of the de- wer stage. When there is no delay of reference the
modulation filter. At 20 kHz different loads lead to control system saturates because of high frequency
a variation in frequency response of approximately difference. This leads to an increased noise level and
±1.5 dB. less attenuation of errors such as harmonics.
In Figure 21 frequency response with PEDEC is de-
monstrated. Compared to Figure 20 it is clearly seen 6 IVC
how the PEDEC control system minimizes variation The volume control is a necessary element of most
in the frequency response. At 20 kHz the frequency audio player media. If a volume control system is
response only varies approximately ±0.2 dB. applied to a digital signal in the form of a digital at-
tenuation, the noise level will stay at the same level
THD + N vs. power without PEDEC is de-
even for an attenuated signal. The digital volume
monstrated in Figure 22. It is seen how the
control will decrease the dynamic range when the
THD + N ([100 mW : 60 W]) at the maximum is
signal is attenuated. Most analogue volume control
1 %. THD + N vs. power with PEDEC is demons-
systems will have a very big dynamic range, hence
trated in Figure 23. It is easily seen how THD + N
the noise is attenuated corresponding to the attenua-
is strongly attenuated at all frequencies and all le-
tion of the signal. An analogue volume control can
vels. It is seen how the THD+N ([100 mW : 60 W])
retain the dynamic range when the signal is attenua-
at the maximum is 0.06 %.
ted. In a digital PMA the signal is modulated (PCM
In Figure 17 is seen the power stage supply voltage or PWM) all the way to the demodulation filter, the-
and the output signal of the amplifier during open- refore an analogue volume control scheme cannot be
loop operation with a 20 Hz output with 0.85 modu- directly applied. A volume control system that does
lation index. It is seen how the supply voltages vary not decrease dynamic range is therefore desired.

AES 23RD INTERNATIONAL CONFERENCE, COPENHAGEN, DENMARK, 2003 MAY 23–25 11


MUNK AND ANDERSEN DIGITAL PULSE MODULATED AMPLIFIER SYSTEM

Fig. 18: Wideband FFT of modulator output. Input signal f = 6.67 kHz and M = 0.1

Fig. 19: FFT of modulator output. Input signal f = 6.67 kHz and, M = 0.85

AES 23RD INTERNATIONAL CONFERENCE, COPENHAGEN, DENMARK, 2003 MAY 23–25 12


MUNK AND ANDERSEN DIGITAL PULSE MODULATED AMPLIFIER SYSTEM

Fig. 20: Frequency response during openloop operation with different loads. From the top to the bottom at
the right of the figure open load, 16 Ω, 8 Ω and 4 Ω

Fig. 21: Frequency response during PEDEC operation with different loads. From the bottom to the top at
the right of the figure: open load, 16 Ω, 8 Ω and 4 Ω

AES 23RD INTERNATIONAL CONFERENCE, COPENHAGEN, DENMARK, 2003 MAY 23–25 13


MUNK AND ANDERSEN DIGITAL PULSE MODULATED AMPLIFIER SYSTEM

Fig. 22: THD+N vs. power during openloop operation. Frequencies 100 Hz, 1 kHz and 6.67 kHz

Fig. 23: THD+N vs. power during PEDEC operation at different frequencies. From the bottom to the top
at 5 W on the figure: 100 Hz, 1 kHz and 6.67 kHz

AES 23RD INTERNATIONAL CONFERENCE, COPENHAGEN, DENMARK, 2003 MAY 23–25 14


MUNK AND ANDERSEN DIGITAL PULSE MODULATED AMPLIFIER SYSTEM

Fig. 24: FFT during openloop operation. M = 0.85, f = 20 Hz, ZL = 4 Ω

Fig. 25: FFT during PEDEC operation. M = 0.85, f = 20 Hz, ZL = 4 Ω

AES 23RD INTERNATIONAL CONFERENCE, COPENHAGEN, DENMARK, 2003 MAY 23–25 15


MUNK AND ANDERSEN DIGITAL PULSE MODULATED AMPLIFIER SYSTEM

Fig. 26: FFT during PEDEC operation, in top without delay of reference, in bottom with with delay of
reference, M = 0.85, f = 6.67 kHz, ZL = 8 Ω

Intelligent Volume Control (IVC) [5] is a volume


control system that operates by combined gain shift
in digital modulator, power stage and control sys-
tem feedback. Figure 27 shows the general structure 0dB
of the IVC control system. A volume control block Digital attenuation 0 - 20dB
controls the attenuation level in the digital modula- Supply ±50V
tor, power stage and feedback. To simplify the im-
20dB Gain shift

Volume
control
input
Attenuation control Error Processing Gain switch Power supply

Supply ±5V Digital attenuation 0 - 115dB


ve Feedback

Digital vr vc vo
input Digital modulator
Edge Delay Power Stage and
and digital
PWM (Edge re-timing) re-timed PWM demodulation filter Audio output
attenuator

135dB
Fig. 27: Block diagram of IVC volume control sys-
tem
Fig. 28: IVC attenuation
plementation of IVC the supply voltage should only
shift between few levels e.g. 2 levels as the example in
Figure 28. In the example in Figure 28, the volume

AES 23RD INTERNATIONAL CONFERENCE, COPENHAGEN, DENMARK, 2003 MAY 23–25 16


MUNK AND ANDERSEN DIGITAL PULSE MODULATED AMPLIFIER SYSTEM

control operates from 0 to -135 dB. The attenuation


from 0 to -20 dB is handled by the digital attenuator.
At −20 dB a gain shift is produced and the supply
voltage for the power stage is decreased by 20 dB,
the feedback is amplified by 20 dB and the digital at-
tenuation is amplified 20 dB. The attenuation from
−20 dB to −135 dB is then handled digitally.
The general control of the attenuation is handled
by an attenuation control unit, which can be a
part of the digital modulator. A simulation of a
gain shift is shown in Figure 29. The gain shift
is 20 dB at −20 dB attenuation, modulation of si-
gnal is M = 0.8. It is seen how the digital mo-
dulator changes output modulation from very large
(M = 0.8) to small (M = 0.08). The digital mo- Fig. 29: IVC gain shift simulation, in top the refe-
dulator changes from 0 dB attenuation to −20 dB rence signal, in middle signal after power stage, in
attenuation. Since the attenuation in the digital mo- bottom demodulated output signal
dulator is digital, the dynamic range in the digital
modulator is lowered at the gain shift. Before the
gain switch the system include full digital dynamic
range, this can be interpreted as a 20 dB boost in 7 CONCLUSION
dynamic range.
For the two major parts of a digital PMA, it was de-
After the power stage it is seen that the amplitude monstrated through simulations and measurements
of the PWM signal is increased by 20 dB at the gain that performance may be improved using compen-
shift. It is obvious that the edge related noise is sation methods.
20 dB lower at the low amplitude before the gain
shift. In the modulator, application of the WPWM com-
pensation leads to improved performance. Espe-
When the power stage switches between low vol-
cially THD is affected.
tages, the efficiency of the power stage is higher. At
idle the switching losses are reduced by the square Presently the digital modulator has inferior perfor-
of the amplitude. Also the EMI of the power stage mance compared to the state of the art analog sys-
is reduced. Two very important additional benefits tem; MECC. This fact is presently the object for
of the IVC algorithm. intensive research. Results so far indicate that it
The demodulated output signal shows that the audio can be expected that the digital PMA will reach
signal is the same before and after the gain switch. and even exceed performance levels of the analogue
At the demodulated output signal it is seen that the PMA.
switch frequency residual is almost eliminated when It was shown that a PMA based on a digital modula-
the power stage switches between low voltages, this tor and with a PEDEC feedback compensation loop
leads to reduced EMI. placed in the analogue part of the amplifier drama-
The main advantages of IVC can be summarised to: tically improves performance.
The different contributions from the power stage to
• Improved dynamic range. the total error was described. It was demonstra-
• Improved edge related noise. ted how using the PEDEC diminishes influence from
non-idealities in the power stage.
• Improved efficiency.
Present overall performance of the digital input
• Improved EMI characteristics. PMA attains the following level:

AES 23RD INTERNATIONAL CONFERENCE, COPENHAGEN, DENMARK, 2003 MAY 23–25 17


MUNK AND ANDERSEN DIGITAL PULSE MODULATED AMPLIFIER SYSTEM

THD+N < 0.06 % 9 LIST OF ABBREVIATIONS


THD @ 1 W, ZL = 8 Ω 0.005 % ED Edge Delay
Dynamic Range 100 dB EMI Electromagnetic Interference
120 dB with IVC FFS Fraction of Full Scale
Frequency response ±0.2 dB IVC Intelligent Volume Control
M Modulation index
MECC Multivariate Enhanced Cascade
Control
8 REFERENCES NPWM Natural Pulse Width Modulation
NTF Noise Transfer Function
[1] Morten Kjær Johansen and Karsten Nielsen. PCM Pulse Code Modulation
A review and comparison of digital PWM me- PEDEC Pulse Edge Delay Error Correction
thods for digtital Pulse Modulation Amplifier PMA Pulse Modulation (power) Amplifier
(PMA) systems. In Proceedings of the 107 th AES PWM Pulse Width Modulation
Convention, 1999. SNR Signal to Noise Ratio
STF Signal Transfer Function
UPWM Uniform Pulse Width Modulation
[2] Pulse referenced control methods for enhan- VFCx Voltage Feedback Control topology,
ced power amplification of pulse modulated si- type x
gnal. International Application Published un- WEE Width Error Estimate
der the Patent Cooperation Treaty (PCT) WO WPWM Weighted Pulse Width Modulation
98/44626, World Intellectual Property Organiza-
tion, 1997.

[3] Karsten Nielsen. Audio Amplifier Techniques


with Energy Efficient Power Conversion. PhD
thesis, The Technical University of Denmark,
Department of Applied Electronics, 1998.

[4] Karsten Nielsen. Digital Pulse Modulation


Amplifier (PMA) topologies based on PEDEC
control. In Proceedings of the 106 th AES
Convention, 1999.

[5] Attenuation control for digital power converters.


Swedish patent SE-0104403-1, AWAPATENT
AB, 2002.

[6] Morten Kjær Johansen. Digital PWM power am-


plifier. Master’s thesis, The Technical University
of Denmark, Department of Applied Electronics,
1999. In Danish.

[7] Bang & Olufsen ICEpower a/s web pages.


http://www.ICEpower.bang-olufsen.com.

AES 23RD INTERNATIONAL CONFERENCE, COPENHAGEN, DENMARK, 2003 MAY 23–25 18

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