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BJT DC ANALYSIS

13. In a switching configuration, a transistor quickly moves


1. No matter what type of configuration a transistor is used in, the between saturation and cutoff, or vice versa. Essentially, the
basic relationships between the currents are always the same , impedance between collector and emitter can be approximated as
and the base-to-emitter voltage is the threshold value if the a short circuit for saturation and an open circuit for cutoff.
transistor is in the “on” state.
14. When checking the operation of a dc transistor network, first
2. The operating point defines where the transistor will operate on check that the base-toemitter voltage is very close to 0.7 V and
its characteristic curves under dc conditions . For linear that the collector-to-emitter voltage is between 25% and 75% of
(minimum distortion) amplification, the dc operating point should the applied voltage V CC .
not be too close to the maximum power, voltage, or current rating
and should avoid the regions of saturation and cutoff. 15. The analysis of pnp configurations is exactly the same as that
applied to npn transistors with the exception that current
3. For most configurations the dc analysis begins with a directions will reverse and voltages will have the opposite
determination of the base current . polarities.

4. For the dc analysis of a transistor network, all capacitors are 16. Beta is very sensitive to temperature , and V BE decreases
replaced by an opencircuit equivalent . about 2.5 mV (0.0025 V) for each 1_ increase in temperature on a
Celsius scale. The reverse saturation current typically doubles for
5. The fixed-bias configuration is the simplest of transistor biasing every 10° increase in Celsius temperature.
arrangements, but it is also quite unstable due its sensitivity to
beta at the operating point. 17. Keep in mind that networks that are the most stable and least
sensitive to temperature changes have the smallest stability
6. Determining the saturation (maximum) collector current for any factors .
configuration can usually be done quite easily if an imaginary
short circuit is superimposed between the collector and emitter
terminals of the transistor. The resulting current through the short BJT AC ANALYSIS
is then the saturation current.
1. Amplification in the ac domain cannot be obtained without the
7. The equation for the load line of a transistor network can be application of dc biasing level .
found by applying Kirchhoff’s voltage law to the output or
collector network. The Q -point is then determined by finding the 2. For most applications the BJT amplifier can be considered
intersection between the base current and the load line drawn on linear, permitting the use of the superposition theorem to
the device characteristics. separate the dc and ac analyses and designs.

8. The emitter-stabilized biasing arrangement is less sensitive to 3. When introducing the ac model for a BJT:
changes in beta— providing more stability for the network. Keep a. All dc sources are set to zero and replaced by a short-circuit
in mind, however, that any resistance in the emitter leg is “seen” connection to ground.
at the base of the transistor as a much larger resistor , a fact that b. All capacitors are replaced by a short-circuit equivalent .
will reduce the base current of the configuration. c. All elements in parallel with an introduced short-circuit
equivalent should be removed from the network.
9. The voltage-divider bias configuration is probably the most d. The network should be redrawn as often as possible.
common of all the configurations.
Its popularity is due primarily to its low sensitivity to changes in 4. The input impedance of an ac network cannot be measured
beta from one transistor to another of the same lot (with the same with an ohmmeter.
transistor label). The exact analysis can be applied to any
configuration, but the approximate one can be applied only if the 5. The output impedance of an amplifier is measured with the a
reflected emitter resistance as seen at the base is much larger pplied signal set to zero . It cannot be measured with an
than the lower resistor of the voltage-divider bias arrangement ohmmeter.
connected to the base of the 6. The output impedance for the r e model can be included only
transistor. if obtained from a data sheet or from a graphical measurement
from the characteristic curves.
10. When analyzing the dc bias with a voltage feedback
configuration, be sure to remember that both the emitter resistor 7. Elements that were isolated by capacitors for the dc analysis
and the collector resistor are reflected back to the base circuit by will appear in the ac analysis due to the short-circuit equivalent
beta. The least sensitivity to beta is obtained when the reflected for the capacitive elements.
resistance is much larger than the feedback resistor between the
base and the collector. 8. The amplification factor (beta, b, or h fe ) is the least sensitive
to changes in collector current , whereas the output
11. For the common-base configuration the emitter current is impedance parameter is the most sensitive. The output
normally determined first due to the presence of the base-to- impedance is also quite sensitive to changes in VCE, whereas the
emitter junction in the same loop. Then the fact that the emitter amplification factor is the least sensitive . However, the output
and the collector currents are essentially of the same magnitude impedance is the least sensitive to changes in temperature ,
is employed. whereas the amplification factor is somewhat sensitive.

12. A clear understanding of the procedure employed to analyze a 9. The r e model for a BJT in the ac domain is sensitive to the
dc transistor network will usually permit a design of the same actual dc operating conditions of the network . This parameter
configuration with a minimum of difficulty and confusion. Simply is normally not provided on a specification sheet, although h ie of
start with those relationships that minimize the number of the normally provided hybrid parameters is equal to b r e , but
unknowns and then proceed to make some decisions about the only under specific operating conditions.
unknown elements of the network.
10. Most specification sheets for BJTs include a list of hybrid 21. Because the total gain is the product of the individual gains of
parameters to establish an ac model for the transistor. One must a cascaded system, the weakest link can have a major effect on
be aware, however, that they are provided for a particular set of the total gain.
dc operating conditions.

11. The CE fixed-bias configuration can have a significant FET


voltage gain characteristic, although its input impedance can
be relatively low . The approximate current gain is given by 1. A current-controlled device is one in which a current defines
simply beta , and the output impedance is normally assumed to the operating conditions of the device, whereas a voltage-
be R C . controlled device is one in which a particular voltage defines the
operating conditions.
12. The voltage-divider bias configuration has a higher
stability than the fixed-bias configuration, but it has about the 2. The JFET can actually be used as a voltage-controlled
same voltage gain, current gain, and output impedance . Due resistor because of a unique sensitivity of the drain-to-source
to the biasing resistors, its input impedance may be lower than impedance to the gate-to-source voltage.
that of the fixed-bias configuration.
3. The maximum current for any JFET is labeled I DSS and
13. The CE emitter-bias configuration with an unbypassed occurs when V GS _ 0 V.
emitter resistor has a larger input resistance than the bypassed
configuration, but it will have a much smaller voltage gain than 4. The minimum current for a JFET occurs at pinch-off defined
the bypassed configuration. For the unbypassed or bypassed by VGS = VP.
situation, the output impedance is normally assumed to be
simply R C . 5. The relationship between the drain current and the gate-to-
source voltage of a JFET is a nonlinear one defined by
14. The emitter-follower configuration will always have an Shockley’s equation. As the current level approaches I DSS , the
output voltage slightly less than the input signal . However, sensitivity of I D to changes in V GS increases significantly.
the input impedance can be very large , making it very useful
for situations where a high-input first stage is needed to “pick up” 6. The transfer characteristics ( I D versus V GS ) are
as much of the applied signal as possible. Its output impedance characteristics of the device itself and are not sensitive to the
is extremely low , making it an excellent signal source for the network in which the JFET is employed.
second stage of a multistage amplifier.
7. When VGS = VP>2, ID = IDSS>4; and at a point where ID =
15. The common-base configuration has a very low input IDSS>2, VGS _ 0.3 V.
impedance , but it can have a significant voltage gain . The
current gain is just less than 1 , and the output impedance is 8. Maximum operating conditions are determined by the product
simply R C . of the drain-to-source voltage and the drain current.

16. The c ollector feedback configuration has an input 9. MOSFETs are available in one of two types: depletion and
impedance that is sensitive to beta and that can be quite low enhancement .
depending on the parameters of the configuration. However, the
voltage gain can be significant and the current gain of some 10. The depletion-type MOSFET has the same transfer
magnitude if the parameters are chosen properly. The output characteristics as a JFET for drain currents up to the I DSS level.
impedance is most often simply the collector resistance R C . At this point the characteristics of a depletion-type MOSFET
continue to levels above I DSS , whereas those of the JFET will
17. The collector dc feedback configuration uses the dc end.
feedback to increase its stability and the changing state of a
capacitor from dc to ac to establish a higher voltage gain than 11. The arrow in the symbol of n -channel JFETs or MOSFETs
obtained with a straight feedback connection. The output will always point in to the center of the symbol , whereas those
impedance is usually close to R C and the input impedance of a p -channel device will always point out of the center of the
relatively close to that obtained with the basic common-emitter symbol.
configuration .
12. The transfer characteristics of an enhancement-type MOSFET
18. The approximate hybrid equivalent network is very similar are not defined by Shockley’s equation but rather by a
in composition to that used with the r e model . In fact, the same nonlinear equation controlled by the gate-to-source voltage, the
methods of analysis can be applied to both models. For the threshold voltage, and a constant k defined by the device
hybrid model the results will be in terms of the network employed. The resulting plot of I D versus V GS rises
parameters and the hybrid parameters, whereas for the r e model exponentially with incrseasing values of V GS .
they will be in terms of the network parameters and b, r e , and r o
. 13. Always handle MOSFETs with additional care due to the
static electricity that exists in places we might least suspect. Do
19. The hybrid model for common-emitter, common-base, and not remove any shorting mechanism between the leads of the
common-collector configurations is the same . The only device until it is installed.
difference will be the magnitude of the parameters of the
equivalent network. 14. A CMOS (complementary MOSFET) device employs a unique
combination of a p -
20. The total gain of a cascaded system is determined by the channel and an n -channel MOSFET with a single set of
product of the gains of each stage . The gain of each stage, external leads. It has the advantages of a very high input
however, must be determined under loaded conditions . impedance, fast switching speeds, and low operating power
levels, all of which make it very useful in logic circuits.
15. A depletion-type MESFET includes a metal–semiconductor
junction, resulting in characteristics that match those of an n - FET AMPLIFIERS
channel depletion-type JFET . Enhancementtype MESFETs
have the same characteristics as enhancement-type MOSFETs. 1. The transconductance parameter g m is determined by the
The result of this similarity is that the same type of dc and ac ratio of the change in drain current associated with a particular
analysis techniques can be applied to MESFETs as was change in gate-to-source voltage in the region of interest. The
applied to JFETs . steeper the slope of the I D -versus- V GS curve, the greater is
the level of g m . In addition, the closer the point or region of
FET BIASING interest to the saturation current I DSS , the greater is the
1. A fixed-bias configuration has, as the label implies, a fixed dc transconductance parameter.
voltage applied from gate to source to establish the operating
point. 2. On specification sheets, gm is provided as y fs .

2. The nonlinear relationship between the gate-to-source voltage 3. When V GS is one-half the pinch-off value , g m is one-half
and the drain current of a JFET requires that a graphical or the maximum value .
mathematical solution (involving the solution of two simultaneous
equations) be used to determine the quiescent point of operation. 4. When I D is one-fourth the saturation level of I DSS , g m is
one-half the value at saturation .
3. All voltages with a single subscript define a voltage from a
specified point to ground . 5. The output impedance of FETs is similar in magnitude to
4. The self-bias configuration is determined by an equation for V that of conventional BJTs .
GS that will always pass through the origin. Any other point
determined by the biasing equation will establish 6. On specification sheets the output impedance r d is provided
a straight line to represent the biasing network. as 1 , y os . The more horizontal the characteristic curves on the
drain characteristics, the greater is the output impedance .
5. For the voltage-divider biasing configuration, one can always
assume that the gate current is 0 A to permit an isolation of the 7. The voltage gain for the fixed-bias and self-bias JFET
voltage-divider network from the output section. The resulting configurations (with a bypassed COMPUTER source capacitance)
gate-to-ground voltage will always be positive for an n –channel is the same .
JFET and negative for a p -channel JFET. Increasing values 8. The ac analysis of JFETs and depletion-type MOSFETs is the
of R S result in lower quiescent values of I D and more same .
negative values of V GS for an n -channel JFET .
9. The ac equivalent network for an enhancement-type
6. The method of analysis applied to depletion-type MOSFETs is MOSFET is the same as that employed for JFETs and depletion-
the same as applied to JFETs, with the only difference being a type MOSFETs. The only difference is the equation for g m .
possible operating point with an I D level above the I DSS value.
10. The magnitude of the gain of FET networks is typically
7. The characteristics and method of analysis applied to between 2 and 20 . The selfbias configuration (without a
enhancement-type MOSFETs are entirely different from those of bypass source capacitance) and the source-follower
JFETs and depletion-type MOSFETs. For values of V GS less are low-gain configurations .
than the threshold value, the drain current is 0 A.
11. There is no phase shift between input and output for the
8. When analyzing networks with a variety of devices, first work source-follower and commongate
with the region of the network that will provide a voltage or configurations . Most others have a 180° phase shift.
current level using the basic relationships associated with those
devices. Then use that level and the appropriate equations to find 12. The output impedance for most FET configurations is
other voltage or current levels of the network in the surrounding determined primarily by R D .
region of the system. For the source-follower configuration it is determined by R S and
gm.
9. The design process often requires finding a resistance level to
establish the desired voltage or current level. With this in mind, 13. The input impedance for most FET configurations is quite
remember that a resistance level is defined by the voltage high . However, it is quite low for the common-gate
across the resistor divided by the current through the resistor. configuration .
In the design process, both of these quantities are often available
for a particular resistive element. 14. When troubleshooting any electronic or mechanical
system , always check the most obvious causes first .
10. The ability to troubleshoot a network requires a clear , firm
understanding of the terminal behavior of each of the devices in
the network. That knowledge will provide an estimate of the
working voltage levels of specific points of the network, which can
be checked with a voltmeter. The ohmmeter section of a
multimeter is particularly helpful in ensuring that there is a true
connection between all the elements of the network.

11. The analysis of p -channel FETs is the same as that applied


to n -channel FETs except for the fact that all the voltages will
have the opposite polarity and the currents the opposite
direction .

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