ADC Techniques For The Nanoscale Era

ADC techniques for the nanoscale era
2010-09-28
Carsten Wulff
Outline
• Who am I, what have I done, and what do I do
• Nanoscale effects to worry about
• Reliability effects
• Nanoscale blocks
• Nanoscale layout
If there is Cme:
• CBSC and my ADC
2 © Carsten Wulff
September 10
Who am I?
• Carsten Wulff
• Born Friday 13. August 1976
• R & D engineer at wireless department at Nordic
Semiconductor
• Married with three kids
• Graduated from NTNU 2002 (Programmable analog integrated
circuit with TOC, 0.6um AMS)
• Ph.D from NTNU in 2008 (Efficient ADCs in nano-‐scale CMOS
technology, 90nm ST)
• Fortunate to spend a year at University of Toronto
(2006-‐2007) with David Johns and Ken MarCn
• h^p://www.scribd.com/carstenwulff
• h^p://www.wulff.no/carsten 3 © Carsten Wulff
September 10
ADC figure of merit
JSSC 1975-2005
ISSCC 2000-2008
10000 Linear Settling FOM limit

Parasitic FOM limit M0=10 C0=1fF
Parasitic FOM limit M0=200 C0=10fF
1000
JSSC 2006 -
Constant FOM limit
100
FOM in fJ/step
10
0.1
0.01
0.001
0.0001
2 4 6 8 10 12 14 16 18 20
Effective Number of Bits

FOM = Power/(2^(2*ENOB)*fs) 4 © Carsten Wulff
September 10
Nanoscale effects
Things to worry about in nanoscale

technologies
Nanoscale papers
Proceedings of the IEEE, october 2009
Norchip 2009
6 © Carsten Wulff
September 10
Headroom
• Most nanoscale processes has a power supply of 1-‐1.2V

• You can run at higher voltages (maybe up to 1.4V), but then
you have to worry about hot electron effects
• Consequences:
• You can’t get everything in strong inversion, so just forget about
it, use weak inversion when needed.
• Don’t stack transistors too high, so forget about
• Telescopic OTA
• Straight cascodes
7 © Carsten Wulff
September 10
Headroom, what works
• Wide swing current mirrors (use everywhere)

• Current mirror OTAs or folded cascode OTAs
• Have good control over what is the maximum raCng for your
process, and run up twoards VMAX (for example in 90nm LP
this can be up to 1.45V on VDS)
8 © Carsten Wulff
September 10
Output resistance
• Output resistance of nanoscale transistors is very poor. Don’t

expect to get more than 20dB(10x) from a single transistor
amplifier
• Use 4F for current mirror transistors
• Use wide swing cascodes everywhere
• Don’t go below 10uA for bias currents unless you really have
to
9 © Carsten Wulff
September 10
Nanoscale transistor
Lewyn, Norchip 2009
New features in sub 100nm technologies:

-‐ Stress is acCvely used to increase mobility
-‐ Very thin oxide, reduced power supply to keep verCcal field in check
-‐ Halo implant that increases drain-‐source conductance at longer
channel lengths
-‐ Hot carrier effects
-‐ Stress from the STI (shallow trench isolaCon)
-‐ Proximity to well edge
-‐ Lithography issues since the minimum dimensions
10
are less than the © Carsten Wulff
wavelength used to expose the photoresist (λ = 193nm) September 10
Well proximity
102*3.4.-2536,+7/
• Threshold voltage increases with
proximity to well edge
• Place switch transistors in a
)*+,+-./0/,
)*+,+-./0/,
transmission gate far from well
edge
• Place bias transistors (diode
!"# !"# !"#
connected transistors) and the $%&&
transistors they bias far from well

edge
• How far is far: ! (
'
! (
'
' '
• Absolute minimum 1.5um !"# !"# !"#
• Recommended > 2um $%&&
11 © Carsten Wulff
September 10
Shallow trench isolation
• Stress is acCvely used in nanoscale transistors to control

threshold voltage
9,..*)*!3-'&7,/,3:-12*-3&-/*!;34-&.-1,..2+,&!
! ! ! !
"#$ "#$ "#$
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7*38**!-+,/,0&!-1,&6,1*-5!1-+,/,0&!
• Use larger than minimum (from DRM) length of diffusion

• Make sure diffusion length set at schemaCc simulaCon
matches the one used in layout
September 10
Reliability effects
DDB: Time dependent dielectric breakdown - Essential for analog design

T
HCI: Hot carrier injection - Essential for analog design
NBTI & PBTI: Negative Bias Temperature instability - Lanny commented it was
not that important for analog design
Time dependent dielectric breakdown (TDDB)
• -‐ Electrons (in NMOS) see a high verCcal electric field and if this field exceeds
around 5MV/cm electrons will go into the gate
• -‐ Trapped charges in the dioxide shios the threshold voltage
• -‐ Can cause a short of the dioxide
• -‐ This effect sets the maximum VGS
September 10
Hot carrier injection
• -‐ Electron is accelerated due to the high horizontal field (high Vds). It
impacts the crystal laqce and generates a electron hole pair.
• -‐ If the impact is high enough energy the electron can pass through
the gate and cause damage
Can occur at moderate VGS and high VDS

September 10
HCI effect: Channel initiated secondary electron
• -‐ An fast electron impacts the laqce and creates a hole-‐electron pair.
• -‐ Due to a high VSB the hole is accelerated towards the substrate. It
can impact the laqce again and make a new hole-‐electron pair.
• -‐ The secondary electron sees a very high electric field and will
accelerate towards the gate
Sets the maximum VSB. VSB ~ 2VDD a factor 10 reduced lifeBme
September 10
Nanoscale blocks
F-based design
Typical differential OTA
Typical bias voltage generator
Typical comparator
Differential reference voltage
F based transistor design
• 1F = 1 gate length
• Why: schemaCc is independent of technology
• Use a small number of different transistors
• Always use larger than 1F25 length for analog transistors
• Widths: 6F, 8F, 24F
Lengths Purpose
1F Digital transistors, posiCve feedback
inverters
1F25 DifferenCal pairs
2F Cascodes
4F Current mirror transistors
12F Standalone current mirrors, cascode
bias transistors
September 10
Differential OTA – CM OTA with CT CMFB
Things to watch out for:

-‐ Common mode stability at high input common modes
,/0/0 ,/0/0 !"# ,/0/0 !"# ,/0/0 ,/0/0 !"#' ,/0/0

23' 23' 23, 23' 23' 23/
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)**+
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23, 23' 23, 23,
$20"
September 10
Differential OTA – Bias voltages
Things to watch out for:

-‐ Current source transistors in saturaCon over PVT
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September 10
Differential pair dynamic comparator
• Also called the

Strongarm latch !"# )*+,+-.
• If mismatch is criCcal add

a preamplifier
(differenCal pair with $%& )*+,+-. )*+,+-. $%'
resisCve or diode
connected load)
-)+,+ -)+,+ $('
$(&
!"# -)+,+ -)+,+ -)+,+ -)+,+ !"#
September 10
Differential reference voltage
• If you don’t care about gain error, use three unity gain
amplifier with a resisCve divider at the input. Remember to
low-‐pass filter the input.
!"#
$%&%$%'(%#
)*+,-.%
!/3
1R
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September 10
Nanoscale Layout
Transistor layout rules

Layout example
Transistor layout rules
Rule Why
Always use two fingers Transistor parameters
change with current
direcCon
Always run all gates in Stress in X and Y
same direcCon direcCon affect transistor
differently
Always have dummy poly Beêr poly control " ! "
during processing
Always have larger than Less stress from shallow
minimum length of trench isolaCon
diffusion
Always place transistors Reduce mismatch in
far from well edge threshold voltage
Be careful with metal Metal changes the stress
rouCng across transistors in the channel
September 10
Layout from Lanny Lewyn
• Extremely uniform poly

• Short distance to
substrate contact
• All gates in same
direcCon
September 10
Things you should know about
Sooware:
SchemaCc (Mentor graphics, Cadence, Synopsys, Tanner tools)
Layout (Mentor graphics, Cadence, Synopsys, Tanner tools)
SimulaCon (Eldo, Spectre, Hspice, SMASH)
ScripCng (Bash, Perl, TCL, LISP)
Editors (Emacs)
Math sooware (Matlab, Maple, Octave)
InformaCon sources:
h^p://ieeexplore.ieee.org
h^p://webcast.berkeley.edu/
EE240 spring 2007 to spring 2010
For new tricks, scan JSSC (all papers) each month
September 10
CBSC pipelined ADC with comparator preset, and
comparator delay compensation
Carsten Wulff1, Trond Ytterdal2

1. Nordic Semiconductor ASA, Trondheim Norway
2. Norwegian University of Science and Technology, Trondheim, Norway
Outline
• What are comparator based switched capacitor circuits?
• How was our ADC implemented?
• What was the measured performance of our ADC?
28 © Carsten Wulff September 10

Session_12_Penmor Sepke1/7/06
et al, ISSCC 2006,
3:32 PM Page 2208.5-bit, 8MHz, 2.5mW
ISSCC 2006 / SESSION 12 / NYQUIST ADCs / 12.4
12.4 Comparator-Based Switched-Capacitor Circuits is a constant offset in the output if the ramp rate a
delay are constant. The current source I2 turns o
For Scaled CMOS Technologies
after the switch opens, but this does not affect the
Todd Sepke1, John K. Fiorenza1, Charles G. Sodini1, Peter Holloway2, Preliminary analysis indicate CBSC circuits are m
Hae-Seung Lee1 cient than conventional opamp-based circuits, be
the virtual-ground condition is more energy efficie
MIT, Cambridge, MA
1 the virtual ground.
National Semiconductor, Salem, NH
2
The CBSC concept is general and can be applied t

Two side effects of technology scaling that have a significant data analog circuit. For example, the CBSC desig
impact on analog circuit design are the reduced signal swing and be applied to a pipelined ADC signal path, as
the decrease in intrinsic device gain. Gain is important in feed- 12.4.3. The comparator now controls both the s
back-based analog signal-processing systems, because it deter- and the strobe time for the bit-decision comparato
+ Completely minesnew
the aaccuracy
pproach of tthe
o switched-‐capacitor
output value. Cascodedcircuits
amplifier CBSC pipeline ADC is constructed and operates
-‐ Limited sstages
peed have
(dual
been ramp system)
a popular solution to increase amplifier gain, opamp version of the ADC. Figure 12.4.4 show
but they further reduce the signal swings of scaled technologies. schematic of the first two stages of the prototype C
-‐ Single ended
An alternative method for achieving high gain in an operational pipeline ADC.
amplifier without reducing signal swing is to cascade several
lower-gain amplifiers. Nested-Miller compensation approaches To make its decisions quickly, the comparator mu
[1] can be used to stabilize the cascaded feedback system, but the gain and minimum delay. Unlike the opamp, the
frequency response of the closed-loop system is significantly sac- achieve the required gain with the cascade of seve
rificed to ensure stability. A recent development in the area of erate-gain stages without concern for stabilit
pipeline ADCs avoids these problems by using open-loop ampli- Figure 12.4.5 shows the schematic of the compara
fiers with digital calibration to compensate for the gain variation pipeline. The first stage is a band-limited stage t
[2]. In this paper, a comparator-based switched-capacitor (CBSC) noise in the comparator decision. Two diode-con
circuit design methodology is described that 29 eliminates the use of © Carsten Wulff September 10
devices clamp the output swing for faster recovery
opamps in sampled-data systems. band-limiting stage is a cascade of three broadban
ferential amplifier stages with PMOS triode load
What we wanted to do
Primary goals:
Increase Speed (target 100MHz)
Differential circuit
Secondary goals:
Keep resolution (target 8.5-bits)
High efficiency < 10mW

What we achieved
Increased Speed (60MHz)

Differential Circuit
Resolution not as high as wanted (7.05-bit)

High efficiency (8.5mW)

How does a comparator-based switched-capacitor circuit work?
!" #$!%& +,$-,$*2#*#'3-0"1
!"
!"#"$ %&'()"*+,$-,$ ./01
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+
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#%
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#$ !"
!#'()(*

Implementation

ADC system block diagram
G6-
+#
3 "A1
;+,+1)(-&''"'-."''&.1+"#-<"77-.9+*-+#-8"71=)'&> H+,+1)(-
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The pipelined stage
BCC0?20$,!!.D/
2E90F+.2 *"!
%A' !# !" %GHI'
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FJ$$.10/2CJ$F.
0# !"
!#,
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!+$
The comparator !"# !,. /)0
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Results

Lab setup
1
#
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,-
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1'&*0(2"7,'&/"1()*680.
!"#"$"%&'()*"+,-./0
19:

Improvement INL & DNL
40 2
30
1
INL [LSB]
INL [LSB]
20
0
10
0 −1
−10 −2
0 50 100 150 200 250 0 50 100 150 200 250
Output Code
Output Code
50 2
40
1
DNL [LSB]
DNL [LSB]
30
20 0
10
−1
0
−10 −2
0 50 100 150 200 250 0 50 100 150 200 250
Output Code Output Code
Default values (set before producCon) With calibraCon

ENOB = 2.5-‐bit ENOB = 7.05-‐bit

FFT, SNR, SNDR & SFDR
0 70
−20 60
−40 50
Magnitude [dB]
Magnitude [dB]
−60 40
−80 30
−100 20
−120
10 SNDR
SNR
−140 SFDR
0 5 10 15 20 25 30 0
5 10 15 20 25 30 35 40
Frequency [MHz]
Input Frequency [MHz]

Summary of calibrated ADC performance
Table 10.1: Summary of calibrated ADC performance
Technology 1.2V/1.8V 90nm CMOS
Sampling Frequency 60 MS/s
Resolution 8 bits
Full scale input 0.8V
Size 0.85mm x0.35 mm
DNL (LSB) 0.52 / -0.54
INL (LSB) 0.6 / -0.77
SNR (29.4MHz input) 44.5 dB
SNDR (29.4MHz input) 44.2 dB
SFDR (29.4MHz input) 60 dB
ADC core power 5.9mW
Clock power 2.3mW
Input switches (1.8V) 0.3mW
Waldon Figure of Merit 1.07 pJ/step
Thermal Figure of Merit 8.09 fJ/step

http://www.wulff.no/carsten
Papers, thesis, FOM source data, CBSC modeling, pipelined

schematics…
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ADC Techniques For The Nanoscale Era

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ADC Techniques For The Nanoscale Era

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ADC techniques for the nanoscale era

10000 Linear Settling FOM limit

Effective Number of Bits

Things to worry about in nanoscale

Proceedings of the IEEE, october 2009

• Most nanoscale processes has a power supply of 1-­‐1.2V

• Wide swing current mirrors (use everywhere)

• Output resistance of nanoscale transistors is very poor. Don’t

Lewyn, Norchip 2009

New features in sub 100nm technologies:

connected transistors) and the $%&&

transistors they bias far from well

• Absolute minimum 1.5um !"# !"# !"#

• Recommended > 2um $%&&

• Stress is acCvely used in nanoscale transistors to control

• Use larger than minimum (from DRM) length of diﬀusion

DDB: Time dependent dielectric breakdown - Essential for analog design

Things to watch out for:

,/0/0 ,/0/0 !"# ,/0/0 !"# ,/0/0 ,/0/0 !"#' ,/0/0

!$# ,/0,0 !$# ,/0,0

,/0'0,)1 ,/0'0,)1 !$% ,/0,0

!"% ,/0/0 ,/0/0 ,/0/0 ,/0,0

Things to watch out for:

$%&%& $%&%& $%&%& $%&%&

$%&)$& $%&)$& $%&%& $%&)$& $%&)$&

• Also called the

• If mismatch is criCcal add

!"# -)+,+ -)+,+ -)+,+ -)+,+ !"#

Transistor layout rules

• Extremely uniform poly

Carsten Wulff1, Trond Ytterdal2

• What are comparator based switched capacitor circuits?

• How was our ADC implemented?

• What was the measured performance of our ADC?

28 © Carsten Wulff September 10

ISSCC 2006 / SESSION 12 / NYQUIST ADCs / 12.4

The CBSC concept is general and can be applied t

30 © Carsten Wulff September 10

Increased Speed (60MHz)

Resolution not as high as wanted (7.05-bit)

31 © Carsten Wulff September 10

!" #$!%& +,$-,$*2#*#'3-0"1

32 © Carsten Wulff September 10

33 © Carsten Wulff September 10

34 © Carsten Wulff September 10

35 © Carsten Wulff September 10

37 © Carsten Wulff September 10

38 © Carsten Wulff September 10

Default values (set before producCon) With calibraCon

39 © Carsten Wulff September 10

40 © Carsten Wulff September 10

41 © Carsten Wulff September 10

Papers, thesis, FOM source data, CBSC modeling, pipelined

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• Most nanoscale processes has a power supply of 1-‐1.2V

!" #$!%& +,$-,$2##'3-0"1