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Description
The CXD1261AR is an IC which generates the 64 pin LQFP (PIastic)
sync signals and timing signals required for a
camera system that uses the monochrome CCD
image sensor (760H) such as the ICX038/039 and
ICX058/059.
Features
• Compatible with monochrome (EIA/CCIR) systems
• Built-in electronic shutter function
• Built-in driver for the horizontal (H) clock
• Built-in SG and TG functions
Applications
CCD camera systems
Structure
Silicon gate CMOS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95735B7Y-PS
CXD1261AR
Pin Configuration
PBLK
CLP3
CLP4
CLP1
TST7
CLP2
TST8
TST4
TST5
TST6
TST9
SHD
SHP
VDD
VSS
HR
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VR/FLD 49 32 VSS
HTSG 50 31 XV4
VDD 51 30 XSG2
EXT 52 29 XV3
VSS 53 28 XSG1
TST10 54 27 XV1
TST11 55 26 XV2
VDD 56 25 XSUB
TST12 57 24 VDD
TST13 58 23 RG
VSS 59 22 VSS
TST14 60 21 TST3
TST15 61 20 H2
TST16 62 19 TST2
CBLK 63 18 H1
SYNC 64 17 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CKIN
D1
TST1
OSCI
D2
HD
VSS
TRIG
OSCO
ED2
VD
ED1
ED0
PS
ENB
CL
ED0 13 H
ED1 14 H Shutter speed
ED2 15 H
PS 16 H Serial input Parallel input
EXT 52 L Internal External
TST1 6 — Normally High
TST13 58 — Normally Low
Note) Normally open for TST except as shown in the above table.
∗ During frame accumulation (readout), low-speed shutter does not operate normally.
–2–
CXD1261AR
Pin Description
Pin
Symbol I/O Description
No.
1 HD O Horizontal drive pulse
2 VD O Vertical drive pulse
3 CL O CKIN 2 frequency divided output (EIA: 14.318MHz, CCIR: 14.1875MHz)
4 D1 I Mode switching; low: EIA; high: CCIR (with pull-down resistor)
5 D2 I Mode switching; low: field readout; high: frame readout∗ (with pull-down resistor)
6 TST1 I Test input, fixed to high
7 TRIG I Shutter speed setting pulse (with pull-up resistor)
8 VSS — GND
9 OSCI I Oscillating cell input
10 OSCO O Oscillating cell output
11 CKIN I Clock input (EIA: 28.636MHz, CCIR: 28.375MHz)
12 ENB I Shutter switching; low: normal; high: shutter (with pull-up resistor)
13 ED0 I Shutter speed control (with pull-up resistor)
14 ED1 I Shutter speed control (with pull-up resistor)
15 ED2 I Shutter speed control (with pull-up resistor)
16 PS I Shutter speed setting method switching; low: serial; high: parallel (with pull-up resistor)
17 VDD — Power supply
18 H1 O Horizontal register drive clock
19 TST2 I Test input, normally open (with pull-down resistor)
20 H2 O Horizontal register drive clock
21 TST3 I Test input, normally open (with pull-down resistor)
22 VSS — GND
23 RG O Reset gate pulse
24 VDD — Power supply
25 XSUB O Discharge pulse
26 XV2 O Vertical register drive clock
27 XV1 O Vertical register drive clock
28 XSG1 O Sensor charge readout pulse
29 XV3 O Vertical register drive clock
30 XSG2 O Sensor charge readout pulse
31 XV4 O Vertical register drive clock
32 VSS — GND
∗ The CCD image sensor characteristics are guaranteed for field accumulation operation.
–3–
CXD1261AR
Pin
Symbol I/O Description
No.
33 SHP O Precharge level sample-and-hold pulse
34 SHD O Data sample-and-hold pulse
35 TST4 O Test output, normally open
36 TST5 O Test output, normally open
37 TST6 O Test output, normally open
38 TST7 O Test output, normally open
39 TST8 O Test output, normally open
40 VSS — GND
41 CLP1 O Clamp pulse
42 CLP2 O Clamp pulse
43 CLP3 O Clamp pulse
44 CLP4 O Clamp pulse
45 PBLK O Blanking cleaning pulse
46 TST9 O Test output, normally open
47 VDD — Power supply
48 HR I H reset pulse
49 VR/FLD I V reset pulse (FLD output when EXT = low)
HTSG input; low: XSG1, 2 on; high: off (valid only when EXT = low)
50 HTSG I
Fixed to low when EXT = high
51 VDD — Power supply
52 EXT I Sync mode switching; low: internal; high: external sync (with pull-down resistor)
53 VSS — GND
54 TST10 I Test input, normally open (with pull-down resistor)
55 TST11 O Test output, normally open
56 VDD — Power supply
57 TST12 O Test output, normally open
58 TST13 I Test input, fixed to low
59 VSS — GND
60 TST14 O Test output, normally open
61 TST15 O Test output, normally open
62 TST16 O Test output, normally open
63 CBLK O Composite blanking pulse
64 SYNC O Composite sync pulse
–4–
CXD1261AR
Block Diagram
CL
63 CBLK
64 SYNC
1 HD
H Counter Decoder
1/910 or 1/908 2 VD
Pulse
Generator
V Counter 45 PBLK
Decoder
1/525 or 1/625
41 CLP1
EXT 52 42 CLP2
HR 48 43 CLP3
Reset
VR/FLD 49 Generator
HTSG 50
HTSG
FLD
27 XV1
26 XV2
XSUB
ENB 12 29 XV3
PS 16 31 XV4
ED0 13 28 XSG1
ED1 14 30 XSG2
Shutter Control
ED2 15
25 XSUB
TRIG 7
OSCI 9
OSCO 10 23 RG
18 H1
CKIN 11 20 H2
33 SHP
34 SHD
CL High-speed Pulse
Generator
1/2
CL 3
D1 4
Mode
Setting
D2 5
–5–
CXD1261AR
Electrical Characteristics
1) DC characteristics (VDD = 5V ± 0.25V, Topr = –20 to +75°C)
Item Symbol Conditions Min. Typ. Max. Unit
Supply voltage VDD 4.75 5.0 5.25 V
VIH1 0.7VDD V
Input voltage
VIL1 0.3VDD V
VOH1 IOH = –2mA VDD – 0.5 V
Output voltage 1 ∗1
VOL1 IOL = 4mA 0.4 V
VOH2 IOH = –4mA VDD – 0.5 V
Output voltage 2 ∗2
VOL2 IOL = 8mA 0.4 V
VOH3 IOH = –8mA VDD – 0.5 V
Output voltage 3 ∗3
VOL3 IOL = 8mA 0.4 V
VOH4 IOH = –2mA VDD/2 V
Output voltage 4 ∗4
VOL4 IOL = 2mA VDD/2 V
Feedback resistor RFB VIN = VSS or VDD 500K 2M 5M Ω
Pull-up resistor RPU VIL = 0V 40K 100K 250K Ω
Pull-down resistor RPD VIH = VDD 40K 100K 250K Ω
Note) ∗1 CLP1, CLP2, CLP3, CLP4, PBLK, CBLK, SYNC, VR, HD, VD, XSUB, XSG1, XSG2, XV1, XV2,
XV3, XV4
∗2 CL, RG, SHP, SHD
∗3 H1, H2
∗4 OSCO
–6–
CXD1261AR
H Reset (HR)
The reset is performed at the first falling edge of the reset pulse that was input; resets are not performed at
subsequent edges as long as they do not deviate by two clock pulses (0.14µs) or more.
The minimum reset pulse width is 0.35µs. In addition, HD immediately after a reset can not be guaranteed.
The position at which the reset is performed is 2.31µs advanced after the H reset input.
H reset input
0.35µs or more
HD output
2.31µs
V Reset (VR)
The falling edge of V reset pulse that was input is field identified by the phase difference with the internal signal
(field judge pulse) defined by the falling edge of HD. And VD is reset in phase with V reset pulse.
When field judge pulse is low and V reset pulse falls,
EIA: VD falling edge after 262.5H is the relation between HD and VD of EVEN field.
CCIR: VD falling edge after 313.5H is the relation between HD and VD of ODD field.
Also, when field judge pulse is high and V reset pulse falls,
EIA: VD falling edge after 262.5H is the relation between HD and VD of ODD field.
CCIR: VD falling edge after 313.5H is the relation between HD and VD of EVEN field.
The minimum reset pulse width is 64µs.
Field
judge
pulse
64µs or more
VR input
VD timing is genarated after
262.5H with this VR timing
VD output
(EIA)
VD timing is genarated after
313.5H with this VR timing
1HD 1HD
VD output
(CCIR)
–7–
CXD1261AR
Electronic Shutter Description (During frame accumulation, low-speed shutter does not operate normally.)
The XSUB pulse timing changes according to the electronic shutter control described below. In addition, the
ENB pin controls whether the XSUB pulse is output or not; this control has priority.
VD
HD
XSG1
TRIG
XSUB
Shutter speed
The shutter speed is determined by sampling the XSUB pulse during the interval between the falling edge of
XSG1 and the falling edge of TRIG, and then stopping the XSUB pulse during the interval between the falling
edge of TRIG and the next falling edge of XSG1.
When using the TRIG pin to control the shutter speed, in order to broaden the control range it is necessary to
use the ED0, 1, and 2 pins (described later) to set the shutter speed to 1/10000.
2. Normal shutter
–8–
CXD1261AR
ED1 (CLK)
ED0 (STB)
The data on ED2 is latched in the register at the rising edge of ED1 and is then taken in internally while ED0 is
low.
–9–
CXD1261AR
ED2
tS2 th2
ED1
tS1 tS0
ED0
tW0
– 10 –
Timing Chart (EIA)
HD
VD
SYNC
CBLK
FLD
– 11 –
HD
VD
SYNC
CBLK
FLD
CXD1261AR
Timing Chart (CCIR)
ODD EVEN
FIELD FIELD
HD
VD
SYNC
CBLK
FLD
EVEN ODD
– 12 –
FIELD FIELD
HD
VD
SYNC
CBLK
FLD
CXD1261AR
CXD1261AR
0 91 910
HD
21
HSYNC
S 56 476 511
Y
N EQ
C 406 861
VSYNC
154
CBLK
VD
FLD
0 91 908
HD
21
HSYNC
S 56 475 510
Y
N EQ
C 405 859
VSYNC
167
CBLK
VD
FLD
– 13 –
Timing Chart (EIA vertical direction)
ODD Field
FLD
CBLK/VD
HD
XSG1
XSG2
XV1
XV2
FIELD
XV3
XV4
– 14 –
XV1
XV2
FRAME
XV3
XV4
PBLK
CLP1
CLP2
CLP3
CLP4
CXD1261AR
Timing Chart (EIA vertical direction)
EVEN Field
FLD
CBLK/VD
HD
XSG1
XSG2
XV1
XV2
FIELD
XV3
XV4
– 15 –
XV1
XV2
FRAME
XV3
XV4
PBLK
CLP1
CLP2
CLP3
CLP4
CXD1261AR
Timing Chart (CCIR vertical direction)
ODD Field
FLD
CBLK/VD
HD
XSG1
XSG2
XV1
XV2
FIELD
XV3
XV4
– 16 –
XV1
XV2
FRAME
XV3
XV4
PBLK
CLP1
CLP2
CLP3
CLP4
CXD1261AR
Timing Chart (CCIR vertical direction)
EVEN Field
FLD
CBLK/VD
HD
XSG1
XSG2
XV1
XV2
FIELD
XV3
XV4
– 17 –
XV1
XV2
FRAME
XV3
XV4
PBLK
CLP1
CLP2
CLP3
CLP4
CXD1261AR
Timing Chart (EIA horizontal direction)
HD
CK
CL
H1
H2
RG
SHP
SHD
XV1
– 18 –
XV2
XV3
XV4
XSUB
CLP1
CLP2
CLP3
CLP4
PBLK
HD
CK
CL
H1
H2
RG
SHP
SHD
XV1
XV2
– 19 –
XV3
XV4
XSUB
CLP1
CLP2
CLP3
CLP4
PBLK
HD
ODD XV1
XV2
XV3
XV4
578 3
FIELD
READOUT
36 36 36
EVEN XV1
XV2
XV3
XV4
XSG1
XSG2
– 20 –
22 36
ODD XV1
XV2
XV3
XV4
36
FRAME
READOUT 3 33
EVEN XV1
XV2
XV3
XV4
36
3 Unit: clock pulses (1ck = 69.84ns)
CXD1261AR
Readout Timing Chart (CCIR)
HD
ODD XV1
XV2
XV3
XV4
589 3
FIELD
READOUT
36 36 36
EVEN XV1
XV2
XV3
XV4
XSG1
XSG2
– 21 –
22 36
ODD XV1
XV2
XV3
XV4
36
FRAME 3 33
READOUT
EVEN XV1
XV2
XV3
XV4
36
3 Unit: clock pulses (1ck = 70.48ns)
CXD1261AR
CXD1261AR
CKIN
CL
H1
H2
RG
SHP
SHD
Application Circuit
Signal processing
48 33
49 32 CCD image sensor
V Driver
CXD1261AR
64 17
1 16
Shutter control
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 22 –
CXD1261AR
12.0 ± 0.2
∗ 10.0 ± 0.1
48 33
49 32
(11.0)
0.5 ± 0.2
A
64 17
(0.22)
1 16
+ 0.08 + 0.05
0.5
0.18 – 0.03 0.127 – 0.02
0.13 M + 0.2
1.5 – 0.1
0.1
0.1 ± 0.1
0.5 ± 0.2
0° to 10°
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN
– 23 –