Ece210 CP - Even 16-17

E.C.E.
Department Vision: To become an internationally leading Centre of higher learning

and research in the domain of Electronics and Communication Engineering
ECE210 / Digital Design using HDL / 2016-17 / Even Semester/ B.Tech. E.C.E. / II Year
/ IV Semester
SYLLABUS
L T P C
ECE210 Digital Design using HDL (Verilog)
3 1 0 4
I NUMBER SYSTEMS, CODES, DIGITAL IC’s
Digital Logic – The Basic Gates, Universal Logic Gates, AND-OR-Invert Gates, Positive and
Negative Logic, Introduction to HDL, HDL Implementation Methods, Digital IC Families and
Interfacing, Number Systems and Codes
II COMBINATIONAL CIRCUITS
Boolean Laws and Theorems, Sum-of-Products, Product-of-Sum, K-Map, Data Processing
Circuits: Multiplexers, De-multiplexers, 1-of-16 decoder, BCD-Decimal Decoder, Seven segment
decoders, Encoders, Parity generators and checkers, Magnitude Comparators, Verilog
implementation of data processing circuits, Arithmetic circuits: Binary addition, Binary
subtraction, Unsigned binary numbers, Sign-Magnitude numbers, 2’s Complement representation,
2’s complement arithmetic, arithmetic building blocks, adder- subtractors, Verilog
implementation of Arithmetic Circuits
III SEQUENTIAL CIRCUITS
Flip-flops Gated Flip-Flops, Edge triggered Flip-Flops, Flip-Flop timing, JK Master-Slave Flip-
Flop, Various representation of Flip-flops, Analysis of Sequential circuits, Verilog
implementation Registers SISO, SIPO, PISO, PIPO, Applications of shift registers, Verilog
implementation, Counters Asynchronous counters, Synchronous counters, Changing the counter
modulus, Decade counters, Counter design as a synthesis problem, Verilog implementation
IV SYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN
Model selection, state transition diagram, state synthesis table, design equations and circuit
diagram, Algorithmic state machine, state reduction technique
V ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN
Analysis of Asynchronous Sequential Circuit, Problem with Asynchronous Sequential Circuit,
Design of Asynchronous Sequential Circuit, FSM implementation in HDL, Memory and its types
TEXT BOOK
1. Donald Leach, Albert Malvino, Goutam Saha, Digital Principles and Applications,
TMH, 7th Edition, 2010
REFERENCES
1. John F. Wakerly, Digital Design – Principles and Practices, Pearson India, 4th Edition,
2012
2. M. Morris Mano, Digital Design, Pearson India, 5th Edition, 2013
3. Frank Vahid, Digital Design with RTL Design, Verilog and VHDL, Wiley India, 2nd
Edition, 2010
4. Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, PHI, 2010
WEIGHTAGE:
Sessional Examinations Assessments End Semester Examination
40% 10% 50%
E.C.E. Department Mission:

 To provide quality education in the domain of Electronics and Communication
Engineering through updated curriculum, effective teaching learning process, best of breed
laboratory facilities and collaborative ventures with the industries.
 To inculcate innovative skills, research aptitude, team-work, ethical practices among
students so as to meet expectations of the industry as well as society.
Page 1 of 96
E.C.E. Department Vision: To become an internationally leading Centre of higher learning
/ IV Semester
KALASALINGAM UNIVERSITY
(Kalasalingam Academy of Research and Education)
Krishnankoil
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
COURSE INFORMATION SHEET
Course Name / Code Digital Design using HDL – ECE210

Degree / Branch B.Tech., E.C.E.
Semester / Section IV/ A, B, C, D
Course Credit 4 (3-1-0)
Course Category Programme Core – Theory
Mr. K. Jeya Prakash
Mr. K. Pandiaraj
Course Instructors
Mr. G. Karthy
Mr. G. Ramesh
Course Coordinator Mr. K. Jeya Prakash
Module VLSI and Embedded Systems Design
Module Coordinator Mr C. Ganesh Kumar
Programme Coordinator Mr. K. Jeya Prakash
Academic Year Even Semester / 2016-17
1. Pre-requisite: ECE201, ECE205, ECE284
2. Course Description: This course covers combinational and sequential logic circuits
using Verilog Hardware Description Language (Verilog HDL). Topics include number
systems, Boolean algebra, logic families, memory devices and other related topics.
Upon completion, students should be able to construct, analyse, design and synthesis
of digital hardware with hardware description language and troubleshoot digital circuits
using appropriate techniques and test equipment
3. Career Opportunities: A core course required for an electronics engineering to get

placed in any organisation.
4. Course Objectives:
1. To familiarize the students with the analysis, design and implementation of
digital circuits using HDL.

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/ IV Semester
5. Course Outcomes:
At the end of the course,
1. The student will be able to apply the fundamentals of converting one number system
to another
2. The student will be able to apply Boolean algebra theorems and techniques to
simplify logic functions
3. The student will be able to apply the knowledge of logic gates to build
combinational and sequential circuits
4. The student will be able to use typical design techniques for asynchronous and
synchronous sequential circuits
5. The student will be able to demonstrate the knowledge of the nomenclature and
technology in the area of memory devices, FPGA architecture and logic families
6. The student will be able to write program for combinational and sequential circuits
using HDL
6. B.Tech. E.C.E. Programme Educational Objectives:

After few years of graduation, the student will be able to
PEO1: Technical Proficiency:
Succeed in obtaining employment appropriate to their interests, education and will
become productive and valued engineers within their companies
PEO2: Professional Growth:
Continue to develop professionally through life-long learning, higher education, and
other creative pursuits in their areas of expertise or interest
PEO3: Management Skills:
Exercise leadership (management) qualities in a responsive, ethical, and innovative
manner
7. B.Tech. E.C.E. Programme Outcomes:

At the end of the programme, the students will be able to:
1. Apply knowledge of Mathematics, Science, Engineering fundamentals and
specialisation in Electronics and Communication Engineering to the conceptualisation
of Engineering models
2. Identify, formulate and solve complex problems in the domains of analog/digital
electronics, signal processing and communication engineering, reaching substantiated
conclusions using first principles of Mathematics and Engineering Sciences.
3. Design/develop Microprocessor, Microcontroller based systems, Communication and
Networking systems, Algorithms for signal processing and VLSI circuit components to

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/ IV Semester
meet desired specifications with realistic constraints such as manufacturability and
sustainability.
4. Design and conduct experiments in analog/digital systems, signal processing and
communication and networking systems, analyse and interpret data, and synthesise
information to provide valid conclusions using simulation techniques and/or numerical
methods, graphics.
5. Select and apply necessary engineering instruments, equipment’s, like Digital Storage
Oscilloscope, Microprocessors and Microcontrollers, DSP and FPGA kits, and modern
CAD tools, for Digital Signal Processing, Communication Engineering, Networking
and VLSI Engineering practices with an understanding of their limitations.
6. Apply reasoning informed by the contextual knowledge to assess societal, safety, legal
and cultural issues, and the consequent responsibilities relevant to the professional
engineering practice.
7. Demonstrate the knowledge of contemporary issues in the field of Electronics and
Communication Engineering.
8. Commit to professional ethics and responsibilities and norms of engineering practice.
9. Work effectively as an individual, and also as a member or leader in multicultural and
multidisciplinary teams.
10. Effectively communicate about their field of expertise on their activities, with their peer
and society at large, such as, being able to comprehend and write effective reports and
design documentation, make effective presentations.
11. Manage projects by applying gained knowledge on Engineering and Management
principles.
12. Adapt themselves completely to the demands of the Electronics and Communication
related Engineering by life-long learning
8. B.Tech. E.C.E. Programme Specific Outcomes:

At the end of the programme, the students will be able to:
1. Able to apply the fundamental knowledge of mathematics, basic science and basic
engineering to identify, formulate, research and solve electronics and communication
engineering problems in the areas of Analog and Digital Electronics, Signal processing,
VLSI, Embedded systems, Communication Engineering and Network Engineering
2. Able to apply the knowledge in Electronics and Communication Engineering to the
conceptualisation of Engineering models in various areas, like Analog and Digital
Electronics, Signal processing, VLSI, Embedded systems, Communication
Engineering and Network Engineering

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/ IV Semester
3. Able to analyse and design complex Electronics and Communication Engineering
problems using latest hardware and software tools, along with analytical skills in an
effective and efficient way
4. Able to apply ethical issues, social environmental impact and managerial skills to
communicate the engineering activities effectively to engineering community and
society in large to have a successful career
9. CO, PO and PSO Mapping:

CO vs. PO PSO
PO,
PSO 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4
ECE210             
CO1 H H
CO2 H H H L
CO3 M M H M L L L H M H L L
CO4 M M H M L L L H M H L L
CO5 H L M L M
CO6 M M M H M M M M
10. COs, Teaching Methodologies and Assessment Tools:

Content Assessment Tools
Bloom’s
CO Delivery
Level Direct Indirect
Methodology
1. Class Lecture 1. SE–I – 30%
Course
CO1 2. Flipped Class Remember 2. END SEM. – 50%
Survey
3. Tutorial 3. QUIZ – 20%
1. SE–I – 10%
1. Class Lectures
2. SE–II – 20% Course
CO2 2. Flipped Class Understand
3. END SEM. – 50% Survey
3. Tutorial
4. Assignments – 20%
1. Class Lectures
1. SE–II – 10%
2. Flipped Class
2. SE–III – 20% Course
CO3 3. Tutorial Apply
3. END SEM. – 30% Survey
4. Laboratory
4. Design Report – 40%
Sessions
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/ IV Semester
Content Assessment Tools
Bloom’s
CO Delivery
Level Direct Indirect
Methodology
1. Flipped Class
2. Class Lectures 1. SE–III – 30%
2. END SEM. – 30% Course
CO4 3. Laboratory Apply
Survey
Sessions 3. Design Report – 40%
4. Tutorial
1. SE–I – 10%
1. Flipped Class 2. SE–III – 30% Course
CO5 Understand
2. Class Lectures 3. END SEM. – 40% Survey
4. Quiz – 20%
1. SE–I – 10%
1. Flipped Class
2. SE–II – 10%
2. Class Lectures Course
CO6 Apply 3. SE–III – 10%
3. Laboratory Survey
4. END SEM. – 30%
Sessions
5. Report – 40%
11. Books:
Sl. Name of the book Author Publisher / Year
Digital Principles and Donald Leach, 7th Edition/ 2010
TEXT
1. Applications Albert Malvino,

Goutam Saha
Digital Design – Principles
1.
and Practices John F. Wakerly 4th Edition/ 2008
REFERENCE BOOKS
2. Digital Design M. Morris Mano 5th Edition/ 2013

Fundamentals of Digital Stephen Brown,
3.
Logic with VHDL Design Zvonko Vranesic 3rd Edition/ 2012
Digital Design with RTL
4.
Design, Verilog and VHDL Frank Vahid 2nd Edition
Verilog HDL: A Guide to
5. Digital Design and
Synthesis Samir Palnitkar 2010
12. Web Resources:

Sl. Units Website
I to V
1.
(NPTEL)
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/ IV Semester
Sl. Units Website
2. I
3. I http://www.ni.com/getting-started/labview-basics/environment
4. II http://www.ni.com/getting-started/labview-basics/dataflow
5. III http://www.ni.com/getting-started/labview-basics/execution-structures
6. III http://www.ni.com/getting-started/labview-basics/data-structures
http://www.lammertbies.nl/comm/info/RS-485.html
7. IV http://www.ni.com/white-paper/3536/en/
http://www.ni.com/white-paper/9401/en/
8. IV http://www.arcelect.com/rs232.htm
9. IV http://www.hit.bme.hu/~papay/edu/GPIB/tutor.htm
http://people.etf.unsa.ba/~asalihbegovic/Special%20measurement%20
10. IV, V
methods.html
11. V http://www.hardwarebook.info/PCI
12. V http://www.ni.com/tutorial/2804/en/
http://www.ni.com/tutorial/3702/en/
13. V
http://www.ni.com/ivi/
13. Web links for similar courses offered at other Universities:

Name of
Sl
Course Title the Website
.
University
1. VIRTUAL Alexandru http://www.uaic.ro/wp-
INSTRUMENTATIO Ioan Cuza content/uploads/2013/12/VirtualInstrument
N University ation.pdf
of Iaşi
2. VIRTUAL Alma Mater http://www.engineeringarchitecture.unibo.i
INSTRUMENTATIO Studiorum, t/en/programmes/course-unit-
N LABORATORY Universita catalogue/course-unit/2015/376395
Di Bologna.
14. Online Courses / Certification Courses:

Sl. Course Link Duration
http://www.vlab.co.in/ba_nptel_labs.php?
id=1
1. NPTEL Video Lectures -
http://www.nptelvideos.in/2012/11/indust
rial-automation-and-control.html

Page 7 of 96
/ IV Semester

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/ IV Semester
15. Lesson Plan:
ABBREVIATION TEACHING METHOD
L Class Room Lecture
EL Smart Class Room Lecture (Multimedia)
S Simulations
FC Flipped class
LS Laboratory Sessions
GL Guest Lecture
# of
Sl. Hours Teaching
No. Topic (Cum.) Method(s) Book
Orientation; discussion of course goals and
expected outcomes; discussion of course
1. policies, grading system 1 (1)
I NUMBER SYSTEMS, CODES, DIGITAL IC’s
Digital Logic – The Basic Gates, Universal
Logic Gates, AND-OR-Invert Gates, Positive
2. and Negative Logic 1 (2) L T1
Introduction to HDL, HDL Implementation
3. Methods, Digital IC Families and Interfacing 2 (4) L, P T1
4. Number Systems and Codes 4 (8) L, EL, T T1
5. Assessment of CO1, CO6 1 (9) ---
II COMBINATIONAL CIRCUITS
6. Boolean Laws and Theorems 1 (10) L, T T1
7. Sum-of-Products, Product-of-Sum 3 (13) L, T T1
8. K-Map, Quine-McClusky Method 4 (17) L, T T1
Data Processing Circuits: Multiplexers, De-
multiplexers, 1-of-16 decoder, BCD-Decimal
Decoder, Seven segment decoders, Encoders,
Parity generators and checkers, Magnitude
Comparators, HDL implementation of data
9. processing circuits 4 (22) L, EL, P T1
Arithmetic circuits: Binary addition, Binary
subtraction, Unsigned binary numbers, Sign-
Magnitude numbers, 2’s Complement
representation, 2’s complement arithmetic,
arithmetic building blocks, adder- subtractors,
Binary multiplication and division, HDL
10. implementation of Arithmetic Circuits 3 (25) L, EL, P T1
11. Assessment of CO2, CO3, CO6 1 (26) ----
III SEQUENTIAL CIRCUITS
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/ IV Semester
# of
Sl. Hours Teaching
No. Topic (Cum.) Method(s) Book
Flip-flops Gated Flip-Flops, Edge triggered
Flip-Flops, Flip-Flop timing, JK Master-Slave
Flip-Flop, Switch Contact Bounce circuit,
Various representation of Flip-flops, Analysis of
12. Sequential circuits, HDL implementation 5 (31) L, P T1
Registers SISO, SIPO, PISO, PIPO,
Applications of shift registers, HDL
13. implementation 3 (34) L, EL T1
Counters Asynchronous counters, Synchronous
counters, Changing the counter modulus,
Decade counters, Counter design as a synthesis
14. problem, HDL implementation 3 (37) L, T T1
15. Assessment of CO3, CO6 1 (38) ---
IV SYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN
Model selection, state transition diagram, state
synthesis table, design equations and circuit
16. diagram 5 (43) L, T T1
Algorithmic state machine, state reduction
17. technique 4 (47) L, T T1
V ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN
18. Analysis of Asynchronous Sequential Circuit 2 (49) L, T T1
19. Problem with Asynchronous Sequential Circuit 1 (50) L T1
20. Design of Asynchronous Sequential Circuit 2 (52) L, T T1
21. FSM implementation in HDL 2 (54) L, T, P T1
22. Memory and its types 1 (55) EL T1
23. FPGA Architecture 2 (57) EL T1
24. Assessment of CO4, CO5, CO6 2 (59) ---
25. Exit Survey, Review / Revision 1 (60) ---
# OF CUM.
SL. TOPIC NAME REF. PAGE METHOD
HOURS HOURS
Introduction -- -- 1 1 --
I REVIEW OF VIRTUAL INSTRUMENTATION
Historical perspective
1. T1 1 – 10 1 2 L, EL
of VI
Advantages of VI, T1,
2. block diagram of VI 20 - 35 1 3 L, EL
R3
Page 10 of 96
/ IV Semester
# OF CUM.
HOURS HOURS
Architecture of a
3. virtual T1 1 L, EL
instrumentation
Introduction to T1,
4. LabVIEW 2009 2 9 FC
R1
Assessment of CO1 1 10 --
II DATA – FLOW TECHNIQUES
Graphical
5. T1, 15 - 17 2 12 L, EL
programming
Data flow in G- T1,
6. Programming 35 - 38 1 13 FC, EL
R5
Comparison with T1,
7. conventional 17 1 14 EL
R5
programming
III VI PROGRAMMING TECHNIQUES
Development of
8. simple VIs and sub- T1 50 – 57 2 18 FC, LS
VIs,
For loop, while loop,
9. Shift register, T1 65 – 76 3 21 EL, LS
feedback nodes
Case structures,
10. sequence structures T1 160 -165 2 23 EL, LS
formula nodes,
Single and Multi-
dimensional array &
11. its functions – T1 91 – 98 4 27 EL, LS
Creating clusters,
cluster function, error
handling functions
Waveform charts,
waveform graphs, XY 131 –
12. graphs, mechanical T1 2 29 FC, LS
136
action of Boolean
switches
Creating string, string 194 –
13. functions, File I/Os, T1 203, 204 2 31 EL, LS
Express Vis – 207

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/ IV Semester
# OF CUM.
HOURS HOURS
14. Declaring local, T1 77 – 81 1 32 EL, LS
global variables
IV DATA ACQUISITION AND INSTRUMENT INTERFACE
Analog to Digital
conversion, Digital to 265 –
15. Analog Conversion, T1 2 37 EL, GL
267,268
Digital I/O, Counters,
Timers
PC hardware T1,
16. structure, timing, 260 1 38 EL
R6
interrupts, DMA
Software and
17. hardware installation, T1 226 -228 1 39 FC, EL
Current loop
18. RS232/RS485 R9 - 1 40 GL
GPIB, USB, PCMCIA T1,
19. 224 1 41 GL
R10
V ANALYSIS TOOLS AND APPLICATION
Control and
20. simulation toolkit, T1 364 2 44 S, LS
system identification
toolkit
Overview of VISA T1, 230 –
21. and IVI 1 45 FC
R14 232
Image acquisition a 312 -
22. processing T1 1 46 LS
317
23. VI applications in R13 - 1 47 LS
various fields
24. Real time application R13 - 1 48 LS
development using VI
Assessment of CO5 3 51
--
Course Survey and Discussion 1 52
16. Assessment Topics:

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/ IV Semester
Sl. Assessment Topics Submission Date
LabVIEW Basics – 30th December
1. Online Quiz
Architecture 2016
Data flow in G-
2. Written Assignment 13th January 2016
Programming
Declaring local, global
3. Experiment in LabVIEW 30th January 2016
variables, File I/O
RS232/RS485, GPIB, USB, 10th February
4. Written Assignment PCMCIA 2016
5. Written Assignment VISA and IVI 6th March 2016
Real time Application
6. Experiment in LabVIEW (Simulation) 20th March 2016
17. Exam Portions:

Sl. Test / Exam Topic No(s). Date
1. Unit test – 1 1, 2 and 3 th
5 January 2016
2. Sessional Examination – I 1 to 5 As per Academic calendar
3. Unit test – 2 6 and 7 17th February 2016
4. Sessional Examination – II 6 to 9 As per Academic calendar
5. Unit test – 3 10, 11 and 12 27th March 2016
6. Sessional Examination – III 10 to 15 As per Academic calendar
7. End Semester Examination 1 to 16 As per Academic calendar
18. Topic Beyond Syllabus: Signal Processing and Analysis LabVIEW Tool; GSD
Applications Using LabVIEW
19. Flipped Class Topics:
Sl. Topic No(s). Streaming URL
https://eceklu.sharepoint.com/portals/hub/_layo
uts/15/PointPublishing.aspx?app=video&p=p&c
1. Introduction to LabVIEW hid=29f2a105-2213-4b13-8b3d-
641bdf274bc7&vid=7a22937f-b10a-4fe4-b0a2-
a4a776057c00
https://eceklu.sharepoint.com/portals/hub/_la
2. Arrays in LabVIEW youts/15/PointPublishing.aspx?app=video&p
=p&chid=29f2a105-2213-4b13-8b3d-

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/ IV Semester
641bdf274bc7&vid=a2b291d6-add8-4297-
b3dc-f012ff51a42d
https://eceklu.sharepoint.com/portals/hub/_layo
uts/15/PointPublishing.aspx?app=video&p=p&c
VI applications & Design
3. hid=29f2a105-2213-4b13-8b3d-
Patterns
641bdf274bc7&vid=b54aac59-b101-4438-
95c5-8580e5150ec3
Course Coordinator / EIE315 Module Coordinator /

Signals and Systems Module
Programme Coordinator / B.Tech. E.C.E. Head of the Department / E.C.E.

Page 14 of 96
/ IV Semester Concepts: lecture 0
I – NUMBER SYSTEMS, CODES, DIGITAL IC’s
CONCEPT MAP
continuous
Analogue circuitry
time and amplitude
Implemented as analogue
Process,
Electronic Systems Store Signals
display
Implemented as digital
Digital circuitry discrete

time and amplitude
has
Organised as
has
Technical
History Design Hierarchy
Advantages
Clarity,
Boole System
Electrical performance,
Module
Complex building
Shannon Logic
blocks,
Gate
Reliabilty,
CMOS Transistor
Programmability

Page 15 of 96
and research in the domain of Electronics and Communication Engineering Concepts: lecture 3
/ IV Semester
Values Operations variables

0,1 + . ' a,b,c, ….
Define the
physically
represented by operations
lead directly to
gates
form + ↔ .
axioms dual
by 1 ↔ 0
assemble into
are used to prove
Logic
circuit
special
theorems case De Morgan
described by
are used for used to
Boolean
equation
form
simplifications
complement
also described by
Truth
table

Page 16 of 96
/ IV Semester Concepts: lecture 1
Number system Has

value power series
base r
example example
X2
Remove integer
Other
Converts codes
fraction
to
÷ 10 Converts
integer
Take remainders to use
Decimal Binary
base 10 base 2
Converts Evaluate integer

to
power series
Binary
Converts
coefficients fraction
to
supports
Evaluate
power series
Converts
to
Binary
Coded
integer
decimal
integer
1010 power
Binary arithmetic
series
Converts
to
÷ 1010
Take remainders
Is needed
for

Page 17 of 96
/ IV Semester

Page 18 of 96
/ IV Semester
Boolean Truth
Represent by Generalises to
functions table
All possible
Represent by Convert to
functions
Generalise to
NAND Leads Sum of Sum of Generalises to Leads to

implementation to products minterms
Simplify to
Programmable
Manipulate to
logic
Generalise to
NOR Leads Product of Product of

implementation to sums maxterms
Simplify to

Page 19 of 96
/ IV Semester
Characterised
K Map
by Representation Taking the formal
route
leads directly to
Adjacency
properties
support
Function Prime
simplification implicants
In the form
In the form identify
Essential
Sum of
Product of sums Prime
products
implicants
Can incorporate select
Function
Don’t cares
cover

Page 20 of 96
Concepts: lecture 6

/ IV Semester
CMOS
comprises comprises
technology
P-channel N-channel
device device
use to build CMOS use to build

Circuits
basic digital basic digital
The most basic being
NAND NOR
Inverter
gate gate
also has
also has
comprises has comprises
N’s in series Good electrical N’s in parallel

P’s in parallel properties P’s in series
also features
shapes shapes
General
gate

Page 21 of 96
/ IV Semester
QUESTION BANK
Bloom’s
Taxonomy
No. Question Level
PART A QUESTIONS
1. Find the hexadecimal equivalent of the decimal number 256. Apply
2. Find the octal equivalent of the decimal number 64. Apply
3. What is meant by weighted and non-weighted coding? Knowledge
4. Convert A3BH and 2F3H into binary and octal respectively. Apply
5. Find the decimal equivalent of (123)8. Apply
6. Find the octal equivalent of the hexadecimal number AB.CD Apply
7. Encode the ten decimal digits in the 2 out of 5 code. Apply
8. Show that the Excess–3 code is self –complementing. Comprehension
9. Find the hexadecimal equivalent of the octal number 153.4. Apply
10. Find the decimal equivalent of (346)7. Apply
A hexadecimal counter capable of counting up to at least
(10,000)10 is to be constructed. What is the minimum number
11. of hexadecimal digits that the counter must have? Analysis
12. Convert the decimal number 214 to hexadecimal. Apply
Give an example of a switching function that contains only
13. cyclic prime implicant. Knowledge
How will you use a 4 input NAND gate as a 2 input NAND
14. gate? Analysis
15. How will you use a 4 input NOR gate as a 2 input NOR gate? Analysis
What happens when all the gates in a two level, AND-OR, gate
16. network, are replaced by NOR gates? Analysis
17. What is meant by multilevel gates networks? Knowledge
18. Show that the NAND gate is a universal building block. Comprehension
19. Distinguish between positive logic and negative logic. Comprehension
Implement AND gate, EX-OR gate and OR gate using universal
20. gates. Apply
21. Prove that positive logic NAND is negative NOR logic. Comprehension
22. What is a totem output? Knowledge
23. What is the significance of high impedance in tri-stage gates? Comprehension
24. What are the different data types in Verilog HDL? Knowledge
25. What is a test bench? What is its relevance in Verilog? Knowledge
26. Give the classification of logic families. Comprehension
27. State advantages and disadvantages of each logic family. Comprehension
28. What is module? Write the syntax for module? Knowledge
29. What is Net? Give an example in Verilog. Comprehension
30. What is register? Give an example in Verilog. Comprehension
Page 22 of 96
/ IV Semester
Bloom’s
Taxonomy
No. Question Level
What is a continuous assignment? Write the syntax for
31. continuous assignments Comprehension
32. What is concatenation operator? Knowledge
33. Write the syntax of initial statement. Knowledge
34. Write the syntax for always statement. Knowledge
35. Write the syntax for if and case statement in Verilog HDL Knowledge
36. What is the difference between === and ==? Comprehension
37. State port connection rules. Knowledge
PART B QUESTIONS
Draw the circuit diagram of a 2 input TTL NAND gate. Draw its
transfer characteristics and explain its operation. (Mumbai Univ.
38. 2007, 2006, 2009, 2010) Analysis
Explain voltage parameters of a TTL family. Also explain the
current sinking and sourcing when two standard TTL gates are
39. connected. (Mumbai Univ. 2008) Comprehension
Obtain Hamming code for '1011' data for even parity. Why is
Hamming code called error correcting code? Justify. (Mumbai
40. Univ. 2009) Apply
Construct Hamming code for BCD 0110. Use even parity.
41. (Mumbai Univ. 2009) Apply
With respect to a logic family define the following terms;
1) Fan-out 2) Noise Margin 3) Propagation delay 4) Voltage
parameters 5) Current Parameters. Give the typical values for the
42. terms for CMOS family. (Mumbai Univ. 2008, 2009, 2010) Comprehension
Explain with example self-complementing codes. (Mumbai Univ.
43. 2009) Analysis
Explain what tristate gate is. Draw the symbol, truth table and
44. circuit diagram of the same. (Mumbai Univ. 2006) Comprehension
45. Convert BCD numbers to excess-3 codes. (Mumbai Univ. 2010) Apply
Draw a circuit diagram of a CMOS inverter. Draw its transfer
46. characteristic and explain its operation. (Mumbai 2011) Analysis
Write notes on Interfacing TTL and CMOS logic families.
47. (Mumbai 2011) Apply
Generate a 7 bit even parity hamming code for" 1010". (Mumbai
What are reflective codes? Give suitable example and explain.
49. (Mumbai 2008) Comprehension
Explain Top-down Design methodology with example? (JNTU
50. 2009) Comprehension
51. Write notes on operators in Verilog. (JNTU 2009) Comprehension
Page 23 of 96
/ IV Semester
Bloom’s
Taxonomy
No. Question Level
Explain how you will construct an (n+1) bit Gray code from an n
52. bit Gray code Analysis
53. Show that the Excess–3 code is self –complementing. Comprehension
Explain the following logic families in detail.
54. a) RTL, b) DTL, and c) TTL Comprehension
Explain in detail about Emitter coupled logic and Integrated
55. injection logic. Comprehension
56. Give the comparison of performance of various logic families. Comprehension
57. Explain in detail about schottky and clamped TTL logic. Comprehension
58. Explain error detection and error correction codes. Comprehension
59. Explain the parameters used to characterise logic families. Comprehension
60. Draw the VLSI design flow. Explain it. Comprehension
61. Explain the different types of modelling in Verilog. Comprehension
COMPETITIVE EXAMINATIONS QUESTIONS
62.
63. (GATE 2014)

Page 24 of 96
/ IV Semester
Bloom’s
Taxonomy
No. Question Level
64. (GATE 2014)

Page 25 of 96
/ IV Semester
Bloom’s
Taxonomy
No. Question Level
65. (GATE 2007)
66. (GATE 2010)

Page 26 of 96
/ IV Semester
Bloom’s
Taxonomy
No. Question Level
67. (BSNL JTO 2009)
68. (BSNL JTO 2009)
69. (IES 2013)
70. (IES 2013)
71. (IES 2013)

Page 27 of 96
/ IV Semester
Bloom’s
Taxonomy
No. Question Level
72. (IES 2013)
73. (IES 2013)
74. (IES 2013)
75. (IES 2012)

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/ IV Semester
Bloom’s
Taxonomy
No. Question Level
76. (IES 2012)
77. (IES 2012)
78. (IES 2012)

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/ IV Semester
Bloom’s
Taxonomy
No. Question Level
79. (IES 2012)
(IES
80. 2012)
81. (IES 2011)

Page 30 of 96
/ IV Semester
Bloom’s
Taxonomy
No. Question Level
82. (IES 2011)
83. (IES 2011)

Page 31 of 96
/ IV Semester
Bloom’s
Taxonomy
No. Question Level
84. (IES 2011)
85. (IES 2011)

Page 32 of 96
/ IV Semester
Bloom’s
Taxonomy
No. Question Level
86. (IES 2011)
(ISRO
87. 2012)
88. (ISRO 2010)
89. (ISRO 2010)

Page 33 of 96
/ IV Semester
Bloom’s
Taxonomy
No. Question Level
90. (ISRO 2010)
91. (TANCET)

Page 34 of 96
/ IV Semester
CONCEPT MAP
II – Combinational Circuits
Concepts: lecture 2
Arithmetic
value
may convert directly to
Signed Sign &

2's complement represent by represent by
numbers magnitude
define
add
subtract
2's comp
Regular addition
& 2N - X
Ignore ms carry
add
if outside
Implemented by
range
Invert bits
overflow &
Add 1

Page 35 of 96
/ IV Semester
Question Bank
Bloom’s
No Taxonomy
. Question Level
PART A QUESTIONS
Give an example of a switching function that contains only cyclic
1. prime implicant. Apply
Give an example of a switching function that for which the MSP
2. from is not unique. Apply
3. Express x+yz as the sum of Minterms Apply
4. Find the value of X = A B C (A+D) if A=0; B=1; C=1 and D=1 Apply
5. What are ‘Minterms’ and ‘Maxterms’? Knowledge
Comprehensi
6. State and prove Demorgan’s theorem. on
7. Find the complement of x+yz Apply
Comprehensi
8. State and prove Consensus theorem. on
What theorem is used when two terms in adjacent squares of K map
9. are combined? Analysis
Comprehensi
10. Show that the NAND connection is not associative. on
List the truth table of the function: Comprehensi
11. F = x y + x y’ + y ’z on
Relate Carry Generate, Carry Propagate, Sum and Carry-Out of a
12. Carry Look-Ahead Adder. (Anna Univ.) Analysis
Design a half-subtractor combinational circuit to produce outputs
13. Borrow and Difference. (Anna Univ.) Synthesis
14. Write the Verilog model of a full-subtractor circuit. (Anna Univ.) Synthesis
15. Draw the structure of 8:1 decoder. Apply
16. Solve using 2’s Complement Method: 26-18 Apply
17. Divide 11011 by 11. Apply
18. Design a single bit comparator to compare two words A and B. Synthesis
(Anna
19. Univ.) Apply
(Anna
20. Univ.) Apply
21. Draw the logic diagram of a serial adder. (Anna Univ.) Synthesis
22. Design a three bit even parity generator. (Anna Univ.) Synthesis
23. Design a three input AND gate using Verilog. (Anna Univ.) Synthesis
24. What are Don’t Care Terms? (Anna Univ.) Knowledge
Page 36 of 96
/ IV Semester
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No Taxonomy
. Question Level
25. Draw the logic diagram of 4:1 MUX (Anna Univ.) Synthesis
26. State Distributive Law. (Anna Univ.) Knowledge
27. What is Prime Implicant? (Anna Univ.) Knowledge
Comprehensi
28. Enumerate some of the combinational circuits. (Anna Univ.) on
Comprehensi
29. List out various applications of Multiplexer. (Anna Univ.) on
PART B QUESTIONS
30. Prove that (x1+x2).(x1’. x3’+x3) (x2’ + x1.x3) =x1’x2. Apply
Simplify using K-map to obtain a minimum POS expression:
(A’ + B’+C+D) (A+B’+C+D) (A+B+C+D’) (A+B+C’+D’)
31. (A’+B+C’+D’) (A+B+C’+D) Apply
Reduce the following equation using Quine McClucky method of
32. minimization F (A,B,C,D) = _m(0,1,3,4,5,7,10,13,14,15) Apply
Comprehensi
33. State and Prove idempotent laws of Boolean algebra. on
34. Using a K-Map ,Find the MSP from of F= _(0,4,8,12,3,7,11,15) +_d(5) Apply
With the help of a suitable example, explain the meaning of a
35. redundant prime implicant. Analysis
36. Using a K-Map, Find the MSP form of F= _ (0-3, 12-15) + _d (7, 11) Apply
Simplify the following using the Quine – McClusky minimization
technique D = f(a,b,c,d) = _ (0,1,2,3,6,7,8,9,14,15).Does Quine –
McClusky take care of don’t care conditions? In the above problem,
will you consider any don’t care conditions? Justify your answer. List
also the prime implicant and essential prime implicant for the above
37. case Evaluate
38. Determine the MSP and MPS focus of F= _ (0, 2, 6, 8, 10, 12, 14, 15) Apply
Determine the MSP form of the Switching function F = _ (
39. 0,1,4,5,6,11,14,15,16,17,20- 22,30,32,33,36,37,48,49,52,53,56,63) Apply
40. Find the Minterm expansion of f(a,b,c,d) = a’(b’+d) + acd’ Apply
Simplify the following Boolean function by using the Tabulation
41. Method F= _ (0, 1, 2, 8, 10, 11, 14, 15) Apply
Find the MSP representation for F(A,B,C,D,E) =
_m(1,4,6,10,20,22,24,26) + _d (0,11,16,27) using K-Map method.
42. Draw the circuit of the minimal expression using only NAND gates Apply
43. Implement Y = (A+C) (A+D’) ( A+B+C’) using NOR gates only. Apply
Show that the NAND operation is not distributive over the AND
44. operation. Analysis
Find a network of AND and OR gate to realize f(a,b,c,d) = _ m
45. (1,5,6,10,13,14). Apply

Page 37 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
What are the advantages of using tabulation method? Determine the
prime implicant of the following function using tabulation method F(
46. W,X,Y,Z) = _(1,4,6,7,8,9,10,11,15). Apply
Design a 4 bit magnitude comparator to compare two 4 bit number and
47. implement it in Verilog. Synthesis
Construct a combinational circuit to convert given binary coded
decimal number into an Excess 3 code for example when the input to
48. the gate is 0110 then the circuit should generate output as 1001. Synthesis
Design a combinational logic circuit whose outputs are F1 = a’bc +
49. ab’c and F2 = a’ + b’c + bc’ Apply
Draw the logic diagram of a *-bit 7483 adder. Using a single 7483,
50. Draw the logic diagram of a 4 bit adder/subtractor. Apply
Comprehensi
51. Distinguish between Boolean addition and Binary addition. on
Realize a BCD to Excess 3 code conversion circuit starting from its
52. truth table and implement it in Verilog. Synthesis
Design a combinational circuit which accepts 3 bit binary number and
53. converts its equivalent excess 3 codes. Synthesis
Derive the simplest possible expression for driving segment “a”
through ‘g’ in an 8421 BCD to seven segment decoder for decimal
digits 0 through 9 .Output should be active high. Implement an
54. equivalent in Verilog. Synthesis
Write the HDL description of the circuit specified by the following
Boolean function
Y= (A+B+C) (A’+B’+C’)
F= (AB’ + A’B) (CD’+C’D)
Z = ABC + AB’ + A (D+B)
55. T= [(A+B} {B’+C’+D’)] Apply
Design 16 bit adder using 4 7483 ICs. Implement an equivalent in
56. Verilog. Synthesis
57. Model a 4 bit binary multiplier using Verilog HDL. Synthesis
58. Model a 4 bit linear feedback shift register using Verilog HDL. Synthesis
Design a full adder using half adder.
Design and implement a full adder using Verilog HDL.
a) gate level modelling
59. b) structural modelling( using half adder) (Anna Univ.) Synthesis
Simplify the given Boolean function F(A,B,C,D) =
60. ∑m(0,1,2,8,10,11,14,15) using Quine Mc Clusky algorithm. Apply
61. Write the Verilog code for a 2:4 decoder circuit. Synthesis

Page 38 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
Realise the functions f1(x,y,z) = ∑m(1,2,4,5) and f2(x,y,z) = ∑m(1,5,7)
62. using MUX. Apply
Design and implement 16:1 Multiplexer using two 8:1 MUX in
63. Verilog HDL. Synthesis
64. (Anna Univ.) Apply

Design a combinational circuit that generates 9’s complement of a
67. BCD digit. Model it in Verilog. Synthesis
68. Explain the operation of Carry Look-Ahead Adder with neat diagram. Analysis
Design a combinational circuit that produces the product of 2 binary
numbers
69. A = (A1 A0) x B = (B2 B1 B0). Model it in Verilog. Synthesis
Simplify the following expression using Boolean theorems
- -
70. (AB+C+D) (C+D) (C+D+E) (Mumbai Univ. 2008) Apply
Draw a Karnaugh Mapfor the given circuit:

Implement the following function using NAND gates only
72. F= Σm(l, 2, 4,7, 11, 13) + d (9, 15) (Mumbai Univ. 2008) Apply

Page 39 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
Design a combinational Circuit for controlling panel light of satellite
control room. The Light should go ON if :-
 The pressure in fuel and oxidizer tank is equal to or above the
required
minimum and there are 10 minutes or less for the satellite to lift off.
Or
 The pressure in fuel tank is below the required minimum but
there are more than 10 minutes for the satellite to lift off.
Or
 The pressure in oxidizer tank is below the required minimum
but there
are more than 10 minutes for the satellite to lift off.
73. Model the same in Verilog. (Mumbai Univ. 2008) Synthesis
74. Design a 4: 1MUXwith active high enable input using NORgates only. Synthesis
Using Quine McCluskey Simplification Method simplify
75. F=Σm(I,3, 13, 15)+ Σd(8,9, to, 11) (Mumbai Univ. 2008) Apply
Design a 4-bit even parity generator and checker. Implement using one
76. 8:1 MUXeach. Model the same using Verilog. (Mumbai Univ. 2008) Synthesis
Design a 1 digit BCD adder using IC 7483 and explain the operation
for
77. (0101) BCD + (l001) BCD (Mumbai Univ. 2008, 2007, 2011, 2006) Analysis
Find'the static hazard in the given circuit and modify it to eliminate the
hazard-
78. (Mumbai 2008) Analysis
79. (Mumbai Univ. 2007) Analysis

Page 40 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
Simplify the following function using Quine McCluskey method :-
F(A. B, C, D. E) = Σm (0,1,9,11,24,29,31) + Σd( 8,15,30). Model the
81. same using Verilog HDL. (Mumbai Univ. 2007) Apply
Implement the function using only one 4 : 1 mux and gates:
F(A. B. C, D) = Σm (0, 2, 3, 6, 8, 9, 11. 13). (Mumbai Univ. 2007,
82. 2011) Apply
Implement the following functions using active low decoder :-
(i) F(A, B) = Σm (0, 1, 3) ,
(ii) F(A, B) = ΠM (0, 2. 3) (Do not convert to SOP form). (Mumbai
83. Univ. 2007, 2011) Apply
Write short notes on 74180 parity generator and checker IC. (Mumbai Comprehensi
84. Univ. 2007) on
Find static hazards in the circuit given below and modify the circuit to
eliminate the hazard.
(Mumbai
85. Univ. 2011) Analysis
86. Write a Verilog Program for active 3:8 decoder. (Mumbai Univ. 2011) Synthesis
Write a Verilog code for an 8 - to - 3 priority encoder using conditional
87. signal assignment. (Mumbai Univ. 2011) Synthesis
Explain working of comparator IC 7485 and implement 10 bit
88. comparator using same IC. (Mumbai 2011) Synthesis
90. (Mumbai Univ. 2010) Analysis

Page 41 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
Perform the following functions:
1101.11 x 101.10001
91. 10000111 / 1101 (Mumbai Univ. 2006) Apply
93. Apply
Explain the working of IC7485 4-bit comparator and hence implement
94. a 5-bit comparator using the same IC. Synthesis

Page 42 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
A lawn sprinkling system is controlled automatically by certain
combination of the following variables:
Season ( S = 1 if summer;0, otherwise)
Temperature (T = 1, if high; 0, if low)
Atmospheric humidity ( H = 1, if high; 0, if low)
Moisture content of the soil ( M = 1, if high; 0, if low)
The sprinkler is turned ON under any of the following circumstances:
. (i) The moisture.contentis low in winter
(ii) The temperature is high and moisture content is low in summer
(Hi) The temperature is high and humidity is high in summer
(iv) The temperature is low and moisture content is low in summer
(v) The temperature is high and humidity is low.
96. Model the same in Verilog. (Mumbai Univ. 2009) Synthesis
Implement the function using single IC 74151 and some gates
F = Σm (1,2.4,10,14,17.19.23.25.26.28,29.30;31) (Mumbai Univ.
97. 2009) Synthesis
Using k-map simplify the following function and implement it as a
SOP and as a POS f = Σ m (0, 4, 5, 6, 8, 12, 13, 14) (Mumbai Univ.
98. 2009) Apply
There are four adjacent parking slot in a company. Each slot is
equipped 10
with a special sensor whose output is asserted low when c~r is
occupying
a slot, otherwise the sensor's output is high. Design and draw.
Schematic
for a system, which will generate a low output if and only if there are
two
or more than two adjacent slots vaccarit. Model the same in Verilog.
99. (Mumbai Univ. 2009) Synthesis
Implement f = Π m(O, 1, 4, 5, 7) using 4 : 1 multiplexer. (Mumbai
Implement 9-bit odd parity checker circuit using IC = 74180. (Mumbai
101. Univ. 2009) Synthesis
Explain comparator chip IC 7485. Design 12-bit comparator circuit
using 10
102. three '7485' ICs. (Mumbai Univ. 2009) Synthesis
Design a 1to4 demultiplexer module by using 2 to 4 decoder? Write
103. the Verilog Code for 1:4 De-Mux using 2:4 decoder. (JNTU 2009) Synthesis
Design a Verilog module for a BCD adder module at the data flow
104. level. (JNTU 2009) Synthesis

Page 43 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
Design a module to generate 2s complement of a 4 bit number? Write
105. the Verilog Code for the same. (JNTU 2009) Synthesis
Draw thelogic diagram of 2bit by 2bit multiplier. Explain its operation.
106. (Anna Univ.) Analysis
107. Explain the operation of a BCD Adder. (Anna Univ.) Analysis
Design a 4 bit parallel adder/subtractor. Model it in Verilog. (Anna
108. Univ.) Synthesis
Design a 4bit Magnitude Comparator and explain its operation. (Anna
109. Univ.) Evaluation
Comprehensi
110. Write short notes on don’t care conditions. (Anna Univ.) on
111. Explain about NAND and NOR implementations. (Anna Univ.) Analysis
Draw the logic diagram of BCD — Decimal decoder and explain its
112. operations. (Anna Univ.) Evaluation
113. Compare and contrast Multiplexer and Encoder. Analysis
114. Implement full adder using 1:8 De-Multiplexer. Synthesis
115. Make a 32:1 mux using 16:1 mux. Model the same in Verilog. Synthesis
116. Write notes on priority encoders. Analysis
117. Apply
118. Apply
119. Apply
120. (GATE 2014)

Page 44 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
121. (GATE 2014)
122. (GATE 2014)
123. (GATE 2013)

Page 45 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
124. (GATE 2014)
125. (GATE 2014)
126. (GATE 2012)
(GATE
127. 2012)

Page 46 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
128. (GATE 2014)
129. (GATE 2014)

Page 47 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
130. (GATE 2014)
131. (GATE 2007)
132. (GATE 2007)

Page 48 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
133. (GATE 2007)
(GATE
134. 2007)
135. (GATE 2008)

Page 49 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
136. (GATE 2008)
137. (GATE 2009)
138. (GATE 2009)

Page 50 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
139. (GATE 2010)
140. (GATE 2010)
141. (BSNL JTO 2009)

Page 51 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
142. (BSNL JTO 2009)
143. (BSNL JTO 2009)
144. (BSNL JTO 2009)
145. (BSNL JTO 2009)

Page 52 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
146. (BSNL JTO 2009)
147. (BSNL JTO 2007)
148. (IES 2013)

Page 53 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
149. (IES 2013)
150. (IES 2013)
151. (IES 2013)
152. (IES 2013)

Page 54 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
153. (IES 2013)
154. (IES 2013)
155. (IES 2013)

Page 55 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
156. (IES 2013)
157. (IES 2013)
158. (IES 2012)
159. (IES 2012)

Page 56 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
160. (IES 2012)
161. (IES 2012)
162. (IES 2012)

Page 57 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
163. (IES 2012)
164. (IES 2012)
165. (IES 2012)
166. (IES 2012)
(IES
167. 2011)

Page 58 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
(IES
168. 2011)
169. (IES 2012)
170. (IES 2011)
171. (IES 2011)

Page 59 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
172. (IES 2011)
173. (IES 2011)
174. (ISRO 2013)

Page 60 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
175. (ISRO 2013)
176. (ISRO 2013)
177. (ISRO 2012)

Page 61 of 96
/ IV Semester
III – SEQUENTIAL CIRCUITS

CONCEPT MAP
QUESTION BANK
Bloom’s
No Taxonomy
. Question Level
PART A QUESTIONS
178. Derive the characteristic equation of all the flip-flops. Comprehension
179. Distinguish between combinational and sequential logic circuits. Comprehension
180. What are the various types of triggering of flip-flops? Knowledge
181. What is race round condition? How it is avoided? Analysis
182. List the functions of asynchronous inputs Comprehension
183. Define Master slave flip flop. Knowledge
Page 62 of 96
/ IV Semester
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No Taxonomy
. Question Level
184. Define Counter. Knowledge
185. What is the primary disadvantage of an asynchronous counter? Comprehension
How synchronous counters differ from asynchronous (ripple)
186. counters? Comprehension
187. Write a short note on counter applications. Comprehension
188. When is a counter said to suffer from lock out? Analysis
What is the minimum number of flip flops needed to build a
189. counter of modulus 8? Analysis
190. State the relative merits of series and parallel counters. Comprehension
191. What is mean by the term ‘edge triggered’? Knowledge
192. What is mean by the term ‘level triggered’? Knowledge
193. What is lockout? How it is avoided? Analysis
194. List the applications of shift registers. Comprehension
195. How many flip –flops are needed to build an 8 bit shift register? Analysis
196. List the basic types of shift registers in terms of data movement. Comprehension
197. Write a short note on PRBS generator. Comprehension
198. Give the HDL dataflow description for all flip-flops. Synthesis
How do you eliminate race condition in JK flip-flop? (Anna
199. Univ.) Analysis
Design a 3 bit ring counter and find the mod of the designed
200. counter. (Anna Univ.) Synthesis
201. Differentiate latch and flip-flop. Comprehension
PART B QUESTIONS
202. Give the all three HDL models for all flip-flops. Synthesis
What is race around condition? How is it avoided? (b) Draw the
schematic diagram of Master slave JK FF and input and output
203. waveforms. Discuss how it prevents race around condition Analysis
204. Convert a flip-flop into other forms of flip-flops. Comprehension
Explain the operation of JK and clocked JK flip-flops with suitable
205. diagrams. Analysis
Design and explain the working of a synchronous mod–3 counter.
206. Model the same in Verilog. Synthesis
Design and explain the working of a synchronous mod–7 counter.
207. Model the same in Verilog. Synthesis
Design a synchronous counter with states 0, 1, 2, 3, 0, 1 ………….
208. Using JK FF. Model the same using Verilog. Synthesis
Using SR flip flops, design a parallel counter which counts in the
209. sequence 000,111, 101, 110, 001,010,000 …………. Synthesis
Using JK flip flops, design a parallel counter which counts in the
210. sequence 000, 111, 101, 110, 001,010,000 ………… Synthesis
Page 63 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
Discuss a decade counter and its working principle. Model the
211. same in Verilog. Synthesis
Draw an asynchronous 4 bit up-down counter and explain its
212. working. Model the same in Verilog. Synthesis
Design a modulo-5 synchronous counter using JK FF and
213. implement it. Construct its timing diagram Synthesis
Explain the operation of universal shift register with neat diagram.
214. (Anna Univ.) Analysis
215. With a neat diagram, explain BCD counter. (Anna Univ.) Analysis
Design a synchronous 4 bit up-down counter and explain its
216. working. Model the same in Verilog. (Mumbai Univ. 2008) Synthesis
Design a MOD 6 asynchronous counter and explain glitch
217. problem. (Mumbai Univ. 2008) Synthesis
Generate "101" sequence by using shift register in SISO mode.
218. Draw timing diagram. (Mumbai Univ. 2008) Synthesis
(Mumbai
Write the truth table, characteristic equation, state table, excitation
table for all flip-flops. Draw the logic diagram of all flip-flops.
220. Explain their working. Analysis
Construct a twisted ring counter using IC 74194 and draw the
output
221. waveforms. (Mumbai Univ. 2009) Synthesis
Draw the diagram and working of (i) Ring Counter and (ii) Twisted
222. Ring Counter. Analysis
Explain and draw MOD -10 asynchronous counter using T- FF.
Draw output waveforms and show where glitches occur. (Mumbai
Design mod-10 asynchronous counter using J-K flip-flop.
224. (Mumbai Univ. 2009) Synthesis
Explain lockout condition in counter with example. (Mumbai
225. Univ. 2009) Analysis
Page 64 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
226. Design a 4 bit bi-direction shift register. (Anna Univ.) Synthesis
Design a 4 bit asynchronous ripple counte. Explain its working.
227. (Anna Univ.) Synthesis
228. Explain SISO, SIPO, PISO, PIPO registers with neat diagrams. Analysis
229. Explain about triggering of flip-flops. (Anna Univ.) Comprehension
230. (GATE 2014)
231. (GATE 2014)

Page 65 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
232. (GATE 2014)

Page 66 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
233. (GATE 2014)
234. (GATE 2012)
235. (GATE 2014)

Page 67 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
236. (GATE 2007)
(GATE
237. 2007)

Page 68 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
238. (GATE 2008)

Page 69 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
239. (GATE 2008)
240. (GATE 2009)

Page 70 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
241. (GATE 2009)
242. (GATE 2010)
243. (BSNL JTO 2009)

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/ IV Semester
Bloom’s
No Taxonomy
. Question Level
244. (BSNL JTO 2009)
245. (BSNL JTO 2007)
(BSNL
246. JTO 2007)

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/ IV Semester
Bloom’s
No Taxonomy
. Question Level
247. (IES 2013)
248. (IES 2013)
249. (IES 2012)

Page 73 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
250. (IES 2012)
251. (IES 2012)
252. (IES 2012)

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/ IV Semester
Bloom’s
No Taxonomy
. Question Level
253. (IES 2012)
254. (IES 2012)
255. (IES 2012)

Page 75 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
256. (IES 2011)
257. (IES 2011)
258. (IES 2011)

Page 76 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
259. (IES 2011)
260. (ISRO 2013)
261. (ISRO 2013)
262. (ISRO 2013)

Page 77 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
263. (ISRO 2013)
264. (ISRO 2010)
265. (ISRO 2010)

Page 78 of 96
/ IV Semester
IV – Synchronous Sequential Circuits
CONCEPT MAP
QUESTION BANK
Bloom’s
No Taxonomy
. Question Level
PART A QUESTIONS
266. Derive the characteristic equation of all flip-flops. Comprehension
Write the state equations, state table, and excitation table for all
267. flip-flops. Comprehension
268. What is state diagram? Knowledge
269. Write about decision box. Comprehension
270. Write about state box. Comprehension
271. Write about conditional box. Comprehension
272. Define Mealy machine Knowledge
273. Draw the timing diagram of ASM Knowledge
274. Define Moore Machine. Knowledge
275. What are the two models of sequential circuit design? Knowledge

Page 79 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
Draw the block diagram for Mealy and Moore model of clocked
276. synchronous sequential network. Knowledge
277. What are the basic three components of ASM charts? Knowledge
278. Compare Mealy and Moore Machine. Comprehension
279. Why do essential hazards occur? Can it be detected? Justify Analysis
280. Write down the rules to be followed for drawing an ASM chart. Comprehension
281. Draw the structure of a clocked synchronous sequential network. Knowledge
282. Define state reduction algorithm. Knowledge
283. List out the differences between excitation table and truth table. Comprehension
Discuss the relationship between state diagram and ASM chart
284. with Mealy and Moore sequential network. Comprehension
285. Differentiate critical races from non-critical races. Comprehension
286. Define Metastability. Knowledge
PART B QUESTIONS
Design the sequence detector that detects the following
287. overlapping sequence “10110”. Implement in Verilog HDL. Synthesis
Design the sequence detector that detects the following non
Design the Sequence detector that detects that detects the following
non overlapping sequence “100111” using ASM realization.
289. Implement in Verilog HDL. Synthesis
Design the sequence detector that detects the following non
Design a sequence detector that produces an output 1 whenever the
overlapping sequence 101101 is detected using ASM. Implement
291. in Verilog HDL. Synthesis
Design sequence detector that produces an output 1 whenever the
non-overlapping sequence 1011 is detected. Implement in Verilog
292. HDL. Synthesis
Design a serial binary adder using D flip-flop. Implement in
293. Verilog HDL. Synthesis
294. Draw the state diagram for serial adder. Apply
Construct an ASM chart for a synchronous sequential network that
is to recognize the input sequence of pairs X1, X2 = 01,01,11,00
295. and explain the each step. Apply
Analyse the circuit described by the following equation
J1=y K1= y+x/Q
J2=x/q1+xyq1 K2=x/y+yq1
Z1=q1/q2 Z2=q1+q2
296. Q1+=y/q1+/x/yq1+/yq1q2 Analysis

Page 80 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
Design a sequence detector which detects the 1001/1111
297. sequences. Implement in Verilog HDL. Synthesis
Explain the design of iterative clocked synchronous sequential
298. networks. Comprehension
Summarize the design procedure for synchronous sequential
299. circuit. Comprehension

Explain the steps involved in the reduction of state table. (Anna
301. Univ.) Comprehension
302. Write about static hazards. (Mumbai Univ. 2008) Comprehension
303. Explain the term “metastability”, its causes and effects. Comprehension
Design a sequence detector which detects the sequence “01110”
using D Flip-Flops (one bit overlapping). Implement in Verilog
304. HDL. (Anna Univ.) Synthesis
Design a counter to count the sequence 0, 1, 2, 4, 5, 6 using SR
305. FFs. Implement in Verilog HDL. (Anna Univ.) Synthesis
Design and implement a serial binary adder as a Mealy network.
306. Implement in Verilog HDL. Synthesis

Page 81 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
Explain state table reduction and state assignment technique using
the state table given below.
Next State Output (z)
Present
Input (x) Input (x)
State
X =0 X=1 X=0 X=1
*A A B 0 0
B D C 0 1
C F E 0 0
D D F 0 0
E B G 0 0
F G C 0 1
G A F 0 0
307. Apply
308. Draw the ASM chart for a MOD 8 UP/DOWN counter. Apply
Design a clocked synchronous sequential circuit which detects the
309. following sequence 0110/1001. Synthesis
310. Synthesis
Model a Traffic Light Controller using Verilog machines with help
311. of state diagrams. Synthesis
Implement a Vending Machine Controller using Verilog with help
312. of state equations/diagrams. Synthesis
313. Implement a FIFO using Verilog with the help of state diagrams. Synthesis
314. Explain the designing process of synchronous counters. Comprehension

Page 82 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
315. (GATE 2014)
316. (GATE 2012)

Page 83 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
317. (GATE 2012)
318. (BSNL JTO 2009)

Page 84 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
319. (IES 2013)
(IES
320. 2013)

Page 85 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
(IES
321. 2011)
322. (IES 2011)

Page 86 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
323. (ISRO 2012)

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/ IV Semester
V – Asynchronous Sequential Circuit Design

CONCEPT MAP
Bloom’s
No Taxonomy
. Question Level
PART A QUESTIONS
324. How does ROM retain information? Comprehension
Page 88 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
325. Give the classification of memories. Comprehension
326. Which memory is called volatile? Why? Comprehension
327. Write a short note on memory decoding Comprehension
328. What is a memory cycle? Comprehension
329. Whether ROM is classified as a non volatile storage device? Why? Comprehension
330. What is meant by memory expansion? Mention its limits. Comprehension
331. What is PAL? How it differs from PROM and PLA? Comprehension
332. Compare static RAMs and dynamic RAMs. Comprehension
333. Mention two types of Erasable PROM Knowledge
334. What is refreshing? How it is done? Comprehension
335. List the basic types of programmable logic devices. Comprehension
336. Define PLDs. Knowledge
337. What is meant by Race? Knowledge
338. What is meant by race condition in digital circuit? Knowledge
339. Define the critical rate and non-critical rate Knowledge
340. What are races and cycles? Knowledge
What are the steps for the analysis of asynchronous sequential
341. circuit Comprehension
What are the steps for the design of asynchronous sequential
342. circuit? Comprehension
343. What are Hazards? Knowledge
344. What is a static 1 hazard? Knowledge
345. What is a static 0 hazard? Knowledge
346. What is dynamic hazard? Knowledge
347. Differentiate static and dynamic hazards. Comprehension
How critical races can be avoided in asynchronous sequential
348. circuits? Analysis
349. What is the cause for essential hazards? Analysis
Distinguish between fundamental mode and pulse mode operation
350. of asynchronous sequential circuits. (Anna Univ.) Comprehension
351. What is the significance of state assignment? Comprehension
352. Differentiate critical races from non-critical races. (Anna Univ.) Comprehension
353. Implement a 2bit multiplier using ROM. (Anna Univ.) Apply
354. What is access time and cycle time of a memory? (Anna Univ.) Knowledge
Draw the logic diagram of static RAM cell and bipolar RAM cell.
356. Distinguish between flow chart and ASM chart. Comprehension
PART B QUESTIONS

Page 89 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
Design a combinational circuit using a ROM that accepts a 3- bit
number and Generates an output binary number equal to the square
357. of the given input number. Synthesis
Design a switching circuit that converts a 4 bit binary code into a
358. 4 bit Gray code using ROM array. Synthesis
Explain brief about read and write operation with timing
359. waveform. (Anna Univ.) Comprehension
360. Describe the RAM organization. Comprehension
361. Describe the ROM organization. Comprehension
362. Explain about the classification of memories Comprehension
363. Write short notes on – PROM, EPROM, EEPROM, and EAPROM. Comprehension
364. Explain the principle of operation of bipolar RAM cell. Comprehension
365. Write note on MOSFET RAM cell. Comprehension
366. Write note on Dynamic RAM cell. Comprehension
367. Write notes on PLA, PAL, FPGA, CPLDs. Comprehension
368. Describe about the architecture of PLD’s. Comprehension
Draw a neat sketch showing implementation of Z1 = ab’d’e +
a’b’c’e’ + bc + de; Z2 = a’c’e, Z3 = bc +de+c’d’e’+bd and Z4 =
369. a’c’e +ce using a 5*8*4 PLA. Synthesis
Implement the functions, f1(x,y,z) = ∑m(1,2,3,7) and f2(x,y,z) =
370. ∑m(0,1,2,6) using 3X4X2 PLA ( true/compliment method). Synthesis
Write short notes on (a) Shared row state assignment (b) One hot
371. state assignment Comprehension
Describe how to detect and eliminate hazards from an
372. asynchronous network. Analysis
Summarize the design procedure for asynchronous sequential
373. circuit. Comprehension
374. Discuss on Hazards and races. Comprehension
How will you minimize the number of rows in the primitive state
375. table of an incompletely specified sequential machine? Comprehension
State the restrictions on the pulse width in a pulse mode
376. asynchronous sequential machine Comprehension
377. Describe cycles in asynchronous sequential circuits Comprehension
Explain with neat diagram of different hazards and write the
378. various hazard elimination methods. Comprehension
Give hazard – free realization for the following Boolean function
379. f(A,B,C,D) = _M(0,2,6,7,8,10,12). Synthesis

Page 90 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
Obtain the primitive flow table for an asynchronous circuit that has
two inputs x,y and one output Z. An output z =1 is to occur only
during the input state xy = 01 and then if the only if the input state
380. xy =01 is preceded by the input sequence. Synthesis
Analyse the asynchronous sequential network, by forming the
excitation table, transition table, flow table and flow diagram.
D0=xy1y2+/y2/xy0
D1=/x/y0y2+xy0y2+xy1/y2
381. D2=x/y1+xy1/y2+y0/y1/y2 Z=xy0y2 Analysis
Analyse the asynchronous sequential circuit has 2 internal states
and one output. The excitation and the output functions describing
the circuits are ,
Y1=x1x2+x1/y2+/x2y1
382. Y2=x2+x1/y1y2+/x1y1 Z=x2+y1 Analysis
An asynchronous sequential circuit is described by the following
excitation and output function
Y=x1x2+(x1+x2)y
383. Z=y, describe the behaviour of the circuit. Analysis
Design an asynchronous sequential circuit with 2 inputs X and Y
and with one output Z. Wherever Y is 1, input X is transferred to Z
.When Y is 0; the output does not change for any change in X. Use
384. SR latch for implementation of the circuit Synthesis
Develop the state diagram and primitive flow table for a logic
system that has 2 inputs, x and y and an output z. And reduce
primitive flow table. The behavior of the circuit is stated as follows.
Initially x=y=0. Whenever x=1 and y = 0 then z=1, whenever x =
0 and y = 1 then z = 0.When x=y=0 or x=y=1 no change in z ot
remains in the previous state. The logic system has edge triggered
inputs without having a clock .the logic system changes state on
the rising edges of the 2 inputs. Static input values are not to have
385. any effect in changing the Z output Synthesis
Design an asynchronous sequential circuit with two inputs X and
Y and with one output Z. Whenever Y is 1, input X is transferred
386. to Z.When Y is 0,the output does not change for any change in X. Synthesis
A pulse mode asynchronous machine has two inputs. It produces
an output whenever two consecutive pulses occur on one input line
only .The output remains at ‘1’ until a pulse has occurred on the
387. other input line. Draw the state table for the machine. Apply

Page 91 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
Construct the state diagram and primitive flow table for an
asynchronous network that has two inputs and one output. The
input sequence X1X2 = 00,01,11 causes the output to become
1.The next input change then causes the output to return to 0.No
388. other inputs will produce a 1 output Apply
Design an asynchronous sequential circuit with two inputs x1 and
x2 and one output z. Initially both the inputs are equal to zero.
When x1 or x2 becomes 1 the output z becomes 1. When the second
input also becomes 1, the output changes to 0. The output stays at
389. 0 until the circuit goes back to the initial state. Synthesis

Implement a 3 bit binary UP/DOWN counter using PAL devices.
Implement binary to Gray code converter using PROM devices.
Write short notes on memory decoding and memory expansion.
395. (Anna Univ.) Comprehension
Design a hazard free asynchronous circuit that changes state
396. whenver input goes from logic 1 to logic 0. (Anna Univ.) Synthesis
397. Design and explain 32x8 ROM. (Anna Univ.) Analysis

Page 92 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
(Anna
398. Univ.) Apply
399. Implement a full adder using PLA. Synthesis
Compare SRAM and DRAM in terms of cost, size, packaging
400. density, speed and technology. Comprehension
401. Explain the difference between EPROM and PROM. Comprehension

Page 93 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
402. (GATE 2013)

Page 94 of 96
/ IV Semester
Bloom’s
No Taxonomy
. Question Level
403. (IES 2013)
404. (IES 2012)
405. (IES 2012)

Page 95 of 96
/ IV Semester
Module Coordinator / VLSI

Course Coordinator / ECE210 and Embedded Design
Head of the Department /

Programme Coordinator / B.Tech. E.C.E. E.C.E.

Page 96 of 96

Ece210 CP - Even 16-17

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E.C.E.

Department Vision: To become an internationally leading Centre of higher learning

E.C.E. Department Mission:

COURSE INFORMATION SHEET

Course Name / Code Digital Design using HDL – ECE210

1. Pre-requisite: ECE201, ECE205, ECE284

3. Career Opportunities: A core course required for an electronics engineering to get

E.C.E. Department Mission:

6. B.Tech. E.C.E. Programme Educational Objectives:

7. B.Tech. E.C.E. Programme Outcomes:

E.C.E. Department Mission:

8. B.Tech. E.C.E. Programme Specific Outcomes:

E.C.E. Department Mission:

9. CO, PO and PSO Mapping:

10. COs, Teaching Methodologies and Assessment Tools:

1. Applications Albert Malvino,

2. Digital Design M. Morris Mano 5th Edition/ 2013

12. Web Resources:

13. Web links for similar courses offered at other Universities:

14. Online Courses / Certification Courses:

E.C.E. Department Mission:

E.C.E. Department Mission:

E.C.E. Department Mission:

16. Assessment Topics:

E.C.E. Department Mission:

17. Exam Portions:

E.C.E. Department Mission:

Course Coordinator / EIE315 Module Coordinator /

Programme Coordinator / B.Tech. E.C.E. Head of the Department / E.C.E.

E.C.E. Department Mission:

Digital circuitry discrete

E.C.E. Department Mission:

Values Operations variables

are used to prove

are used for used to

E.C.E. Department Mission:

Number system Has

Converts Evaluate integer

E.C.E. Department Mission:

E.C.E. Department Mission:

NAND Leads Sum of Sum of Generalises to Leads to

NOR Leads Product of Product of

E.C.E. Department Mission:

Can incorporate select

E.C.E. Department Mission:

E.C.E. Department Vision: To become an internationally leading Centre of higher learning

use to build CMOS use to build

basic digital basic digital

The most basic being

N’s in series Good electrical N’s in parallel

E.C.E. Department Mission:

63. (GATE 2014)

E.C.E. Department Mission:

64. (GATE 2014)

E.C.E. Department Mission:

65. (GATE 2007)

66. (GATE 2010)

E.C.E. Department Mission:

67. (BSNL JTO 2009)

68. (BSNL JTO 2009)

69. (IES 2013)

70. (IES 2013)

71. (IES 2013)