A DC-50 GHz SPDT Switch with Maximum

Insertion Loss of 1.9 dB in a Commercial 0.13-ȝm

SOI Technology
Bo Yu1, Kaixue Ma2, Fanyi Meng1, Wanlan Yang1 Kiat Seng Yeo3, Shaoqiang Zhang4, Raj Verma
1
School of EEE, NTU, Singapore Purakh4
2 3
School of Physical Electronics, UESTC, Chengdu, China Singapore University of Technology and Design, Singapore
1 4
yubo0002@e.ntu.edu.sg, 2kxma@ieee.sg Technology Development, GLOBALFOUNDRIES
Singapore, Singapore
3
kiatseng_yeo@sutd.edu.sg

Abstract— In this paper, a low insertion loss, high isolation, ultra

wideband (DC to 50 GHz) single-pole double-throw (SPDT)
switch using 0.13 ȝm SOI technology is presented. The switch is
designed by using a series-shunt configuration with input and
output matching networks. The channel length and gate bias
impacts on switch performance are studied. It is found that the
transistor channel length has dominant effects on both the
insertion loss and isolation. The measured insertion loss of the
SPDT with 0.13 ȝm channel length transistor is less than 1.9 dB
up to 50 GHz, while the isolation is better than 27 dB. Measured
P1dB for SPDT switch is larger than 12 dBm. The active chip
(a)
area of designed SPDT switch is only 0.21 x 0.19 mm2.

Keywords- SPDT, switch, ultra wideband, NMOS transistor,

channel length, gate bias effect, SOI process

I. INTRODUCTION
RF switches are widely used in modern communication
systems. The ability of switches to operate over wide
bandwidth is becoming increasingly important to enable
wideband or multi-band systems on chip. While design high
performance switches including lower insertion loss, higher
isolation and power handling capability over an ultra-wide
bandwidth from DC to cross millimeter-wave boundary still
remains quite challenging.
Millimeter-wave wideband SPDT switches have been
designed by various processes and technology nodes
previously, including 90 nm bulk CMOS, 0.18 ȝm/ 45 nm SOI,
0.1 ȝm HEMT, and 0.18 ȝm SiGe BiCMOS [1]-[5], etc. In
recent years, by using high resistivity (HR) substrate, SOI
technology has been started to penetrate in the switch market,
thanks to SOI reduced parasitic capacitance and substrate loss.
In this paper, we present 0.13ȝm HR-SOI based SPDT
switch design and the investigation about the gate bias and
channel length effects on switch performance. Compared with
the state of the arts, the designed switch achieves the lowest
insertion loss (< 0.9 dB at 30 GHz, < 1.9 dB at 50 GHz) over
DC to 50 GHz.
(b)
Figure 1. (a) Schematic of the SPDT switch, and (b) equivalent L-C-L
T-matching network model
II. WIDEBAND SOI SWITCH DESIGN
2.5 V body-tied SOI NMOS, with nominal channel length,
Lg = 0.2 ȝm, is used for switch design, the designed SPDT
switches are based on series-shunt with input and output
matching network topology to achieve wideband operation.
On-chip series inductors are used and act as a L-C-L T-
matching circuit using the off-state capacitance of the shunt
NMOS as shunt capacitor C. The final topology for SPDT
switch and equivalent L-C-L T-matching network model are
shown in Fig. 1.
Transistor width are optimized for this design, series
transistors M1 and M3, with total width 75 ȝm, shunt transistors
M2 and M4, with total width 100 ȝm, series inductors, 130 pH
for both L1 and L2, are designed for the SPDT switch. A gate
resistor, Rg = 50 kȍ is used for each transistor for AC floating
to prevent signal leakage and gate oxide breakdown.
This SPDT switch only occupies a small chip area of 0.21 x
0.19 mm2. A same SPDT layout but with shorter channel

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length (Lg = 0.13 ȝm) is also designed to investigate the testing support and Mr. Ye Wanxin, Mr. Kumar, Mr. Han
channel length effect on ultra wideband switch performance. Jiangan NTU, for technical discussions.

III. MEASUREMENT RESULT

The fabricated SPDT is shown in Fig. 2. Measured S-
parameters of both Lg = 0.2 ȝm and Lg = 0.13 ȝm NMOS
switches are shown in Fig.3, under both 2.5 V and 3.3 V gate
bias. Measured insertion loss/isolation of Lg = 0.2 ȝm SPDT
switch under 2.5 V bias is better than 2.1 dB/26 dB from DC to
50 GHz, measured insertion loss/isolation of Lg = 0.13 ȝm
under 3.3 V is better than 1.9 dB/27 dB from DC to 50 GHz.
Insertion loss/isolation of Lg = 0.13 ȝm show about 0.3 dB/2
dB improvement compared to Lg = 0.2 ȝm under same gate
bias, while for same gate length, insertion loss/isolation under
3.3 V bias are 0.1dB/1 dB better than under 2.5 V. (a)

Figure 2. Photography of the SPDT switch

Measured P1dB for Lg = 0.2 ȝm and Lg = 0.13 ȝm switches
are around 14 dBm and 12 dBm at different frequencies from
DC to 30 GHz, respectively.
IV. CONCLUSION
DC-50 GHz SPDT switches have been introduced, a
comparison of wideband switches are given in Table I. The
developed switches exhibit excellent performance at an ultra-
wide frequency band. This is achieved by optimizing the size
of both series and shunt transistors, the matching inductors, and
interconnect layout. Further improvement of both insertion
loss/isolation can be achieved by using reduced channel length
NMOS and applying higher gate bias. The SPDT switches
show outstanding performance to be cost-effectively integrated
into ultra-wideband applications.
ACKNOWLEDGMENT
This program is supported by Singapore Economic
Development Board and GLOBALFOUNDRIES Singapore.
The authors would like to thank IC Design II Lab NTU for
(b)
Figure 3. Measured (a) insertion, ( b) isolation of SPDT switches
REFERENCES
[1] H.-Y. Chang and C.-Y. Chan, “A low loss high isolation DC–60 GHz
SPDT traveling-wave switch with a body bias technique in 90 nm
CMOS process,” IEEE Microw. Wireless Compon. Lett., vol. 20, no.2,
pp. 82–84, Feb. 2010.
[2] M. Parlak and J.F. Buckwalter, “A 2.5-dB Insertion Loss, DC-60 GHz
CMOS SPDT Switch in 45-nm SOI,” Compound Semiconductor
Integrated Circuit Symposium (CSICS), pp. 1-4, Oct. 2011.
[3] K.-Y. Lin, W.-H. Tu, P.-Y. Chen, H.-Y. Chang, H. Wang, and R.-B.
Wu, “Millimeter-wave MMIC passive HEMT switches using traveling-
wave concept,” IEEE trans. Microwave Theory and Tech., vol. 52, no. 8,
Aug. 2004, pp. 1798-1808
[4] S. Mau, K. Ma, and K. S. Yeo, “A DC to 30 GHz ultra-wideband CMOS
T/R switch,” Microw. Opt. Technol. Lett., vol. 53, pp.2072–2075, Sep.
2011.
[5] A. S. Cardoso, P. Saha, P. S. Chakraborty, D. M. Fleischhauer, and J. D.
Cressler. "Low-loss, wideband SPDT switches and switched-line phase
shifter in 180-nm RF CMOS on SOI technology", RWS Page(s): 199 -
201,2014

TABLE I. TABLE TYPE STYLES COMPARISON OF WIDEBAND SWITCHES

BW IL ISO Input P1dB Chip Size
Ref. Tech. Type Topology
(GHz) (dB) (dB) (dBm) (mm2)
[1] 90 nm CMOS SPDT DC-60 <3 > 48 17 0.68 x 0.87 traveling-wave concept
[2] 45 nm SOI SPDT DC-60 2.5 > 25 7.1 0.18×0.22 Series-shunt, low-resistivity substrate.
[3] 0.1 ȝm HEMT SPDT 15-80 < 3.6 > 25 NA 1.5 x 1.5 traveling-wave concept
[4] 0.18 ȝm SiGe SPDT DC-30 1.5 – 3.3 > 20 23 0.025 series-shunt, with matching network
[5] 0.18 ȝm SOI SPDT DC-40 <5 > 17 15 0.28 x 0.09 series-shunt, with matching network
This < 1.9 at 50 GHz series-shunt, with matching network, (> 1 kȍ–
0.13ȝm SOI SPDT DC-50 > 27 12 0.21 x 0.19
work < 0.9 at 30 GHz cm) substrate

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