1.

INTRODUCTION

Skilled navigation in mobile robotics usually requires solving two problems

pertaining to the knowledge of the position of the robot, and to a motion control strategy.
When no prior knowledge of the environment is available, the problem becomes even more
challenging, since the robot has to build a map of its surroundings as it moves. These three
tasks ought to be solved in conjunction due to their interdependency. The present
manuscript proposes a novel mobile robot navigation technique using a customized RFID
reader with two receiving antennas mounted on the robot and a number of standard RFID
tags attached in the robot’s environment to define its path. In here, we show that using the
RF signal from the RFID tags as an analog feedback signals can be a promising strategy to
navigate a mobile robot within an unknown or uncertain indoor environment. This method
is computationally simpler and more cost-effective than many of its counterparts in the
state of the art. It is also modular and easy to implement since it is independent of the
robot’s architecture and its workspace. A set of numerical computer simulations are
provided to illustrate the effectiveness of the proposed scheme

Fig 1.1 Diagram Of Transmitter And Receiver

Radio Frequency Identification (RFID) is evolving as a major technology enabler

for identifying and tracking goods and assets around the world. It can help hospitals locate
expensive equipment more quickly to improve patient care, pharmaceutical companies to

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reduce counterfeiting and logistics providers to improve the management of moveable
assets. It also promises to enable new efficiencies in the supply chain by tracking goods
from the point of manufacture through to the retail point of sale (POS).

RFID is used for reading the physical tags on single products, cases, pallets, or re-
usable containers which emit radio signals to be picked up by reader devices. The complete
RFID picture combines the technology of the tags and readers with access to global
standardized databases. Tags contain a unique identification number called an Electronic
Product Code (EPC), and potentially additional information of interest to manufacturers,
healthcare organizations, military organizations or others that need to track the physical
location of goods or equipment. RFID can be read at a small distance with no overt
physical action required to scan the tag.
This project is developed to build a security system for a home/office to prevent
unauthorized persons to enter into the important room/chamber by controlling radio
frequency identification by checking a suitable RFID card. The RFID tag gives the unique
ID whenever it reads the card information. This ID information is send to the micro
controller to check the correct card to take a security action. If the card ID matches with the
original information, it allows entering into the gate, if not gives the buzzer as an indication
of unauthorized person tried to enter into the gate

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BLOCKDIAGRAM

FIG 1.2 BLOCK DIAGRAM OF MOBILE ROBOT NAVIGATION

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 2 .WORKING PRINCIPLE

• In this project will see how the robot is used in day-to-day life.
• Microcontroller is attached to robot which is having 2 wheels .wheels are connected
to shaft of DC motor. DC motors contains drivers through which is it accessed.
• Robot contains minimum of 2 motors compulsory so as to provide direction .
• The RFID reader which is present in the block diagram always try to read data
present on the RFID tag, and is send through a microcontroller by using a voltage level translator
that is MAX232.
• The voltage levels are different from RFID to AVR controller, so for the conversion
of levels we use MAX232 as LEVEL TRANSLATOR.
• Now for ROBOT and RFID there is a L293D IC because we can’t directly access
the motor and microcontroller
• In RFID there is one coil and one chip present, by inducing the magnetic flux, emf
is generated then the power through the IC will be on then it can detect the number present on the
RFID tag and send it to the reader and the reader detects the number and send to microcontroller
using MAX232.
• Whenever we want to perform a task the authorized person keeps the RFID Tag on
the RFID Reader it reads the and checks whether it is a VALID or INVALID card, if the card
belongs to the authorized person (if it is a valid one) then it will allow for further operations i.e., it
will send the information to the controller and controller will reads the data.
• The data is received from particular reader, based on the technology used and is
compared with pre-stored values.
• For observing the number on the RFID tag we use a LCD display in our project.
• We connect a power supply to acess motor, controller and LCD.

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 3. MICROCONTROLLER

The microcontroller here we are using is AVR (ADVANCED VIRTUAL

RISC ARCHIECTURE).The features of this microcontroller are discussed in detail.

3.1 ATMEGA32 MICROCONTROLLER ARCHITECTURE

• High-performance, Low-power AVR 8-bit Microcontroller
• Advanced RISC Architecture
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
• Non-volatile Program and Data Memories
– 32K Bytes of In-System Self-Programmable Flash
– Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
– In-System Programming by On-chip Boot Program
– True Read-While-Write Operation
– 1024 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 2K Byte Internal SRAM
– Programming Lock for Software Security
• JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

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• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and
Capture Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels in TQFP Package Only
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Programmable Watchdog Timer with Separate On-chip Oscillator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down,
Standby and Extended Standby
• I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
• Operating Voltages
– 4.5 - 5.5V for ATmega32
• Speed Grades
– 0 - 8 MHz for ATmega32L
– 0 - 16 MHz for ATmega32
• Power Consumption at 1 MHz, 3V, 25°C for ATmega32L
– Active: 1.1 mA

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 – Idle Mode: 0.35 mA
3.2 PIN CONFIGURATION:

FIG: 3.2 PIN DIAGRAM ATMEGA32

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BLOCK DIAGRAM

Fig 3.2 Block Diagram

FIG 3.2.1 Block Diagram of ATMEGA32

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OVERVIEW:
The ATmega32 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega32 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general purpose working
registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed in one
clock cycle. The resulting architecture is more code efficient while achieving throughputs
up to ten times faster than conventional CISC microcontrollers.

The ATmega32 provides the following features: 32K bytes of In-System

Programmable Flash Program memory with Read-While-Write capabilities, 1024 bytes
EEPROM, 2K byte SRAM, 32 general purpose I/O lines, 32 general purpose working
registers, a JTAG interface for Boundary-scan, On-chip Debugging support and
programming, three flexible Timer/Counters with compare modes, Internal and External
Interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, an 8-
channel, 10-bit ADC with optional differential input stage with programmable gain (TQFP
package only), a programmable Watchdog Timer with Internal Oscillator, an SPI serial
port, and six software selectable power saving modes. The Idle mode stops the CPU while
allowing the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters, SPI
port, and interrupt system to continue functioning. The Power-down mode saves the
register contents but freezes the Oscillator, disabling all other chip functions until the next
External Interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer
continues to run, allowing the user to maintain a timer base while the rest of the device is
sleeping.
The ADC Noise Reduction mode stops the CPU and all I/O modules except
Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In

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Standby mode, the crystal/resonator Oscillator is running while the rest of the device is
sleeping. This allows very fast start-up combined with low-power consumption. In
Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to
run.
The device is manufactured using Atmel’s high density nonvolatile memory
technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-
system through an SPI serial interface, by a conventional nonvolatile memory programmer,
or by an On-chip Boot program running on the AVR core. The boot program can use any
interface to download the application program in the Application Flash memory. Software
in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU
with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega32 is a
powerful microcontroller that provides a highly-flexible and cost-effective solution to
many embedded control applications.

PIN DESCRIPTIONS
VCC Digital supply voltage.
GND Ground.

Port A (PA7-PA0) Port A serves as the analog inputs to the A/D Converter. Port A
also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port A output buffers
have symmetrical drive characteristics with both high sink and source capability. When
pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current
if the internal pull-up resistors are activated. The PortA pins are tri-stated when a reset
condition becomes active, even if the clock is not running.

Port B (PB7-PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors
(selected for each bit). The Port B output buffers have symmetrical drive characteristics

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with both high sink and source capability. As inputs, Port B pins that are externally pulled
low will source current if the pull-up resistors are activated.

Port C (PC7-PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up
resistors (selected for each bit). The Port C output buffers have symmetrical drive
characteristics with both high sink and source capability. As inputs, Port C pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port C
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port C also serves the functions of the JTAG interface and other special features of the
ATmega32

Port D (PD7-PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up
resistors (selected for each bit). The Port D output buffers have symmetrical drive
characteristics with both high sink and source capability. As inputs, Port D pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port D
pins are tri-stated when a reset condition becomes active, even if the clock is not running
Port D also serves the functions of various special features of the ATmega32.

RESET Reset Input. A low level on this pin for longer than the minimum
pulse
length will generate a reset, even if the clock is not running.
XTAL1 Input to the inverting Oscillator amplifier and input to the internal
clock
operating circuit.
XTAL2 Output from the inverting Oscillator amplifier.

Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier
which can be configured for use as an On-chip Oscillator, as shown in Figure 12. Either a
quartz crystal or a ceramic resonator may be used. The CKOPT Fuse selects between two

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different Oscillator amplifier modes. When CKOPT is programmed, the Oscillator output
will oscillate will a full rail-to-rail swing on the output. This mode is suitable when
operating in a very noisy environment or when the output from XTAL2 drives a second
clock buffer. This mode has a wide frequency range. When CKOPT is unprogrammed, the
Oscillator has a smaller output swing. This reduces power consumption considerably. This
mode has a limited frequency range and it cannot be used to drive other clock buffers.
For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and
16 MHz with CKOPT programmed. C1 and C2 should always be equal for both crystals
and resonators. The optimal value of the capacitors depends on the crystal or resonator in
use, the amount of stray capacitance, and the electromagnetic noise of the environment.
Some initial guidelines for choosing capacitors for use with crystals are given in Table
below. For ceramic resonators, the capacitor values given by the manufacturer should be
used.

Fig: 3.2.2 Crystal Oscillator Connections

The Oscillator can operate in three different modes, each optimized for a specific
frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in table
below.
Table: 3.1

AVCC AVCC is the supply voltage pin for Port A and the A/D Converter. It
should be externally connected to VCC, even if the ADC is not

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 used. If the ADC is used, it should be connected to VCC through a
low-pass filter.
AREF AREF is the analog reference pin for the A/D Converter.

3.3 AVR CPU CORE:

Introduction
This section discusses the AVR core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able to
access memories, perform calculations, control peripherals, and handle interrupts.

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 Fig: 3.3 Block Diagram of THE AVR MCU Architecture
Architectural Overview

In order to maximize performance and parallelism, the AVR uses a Harvard architecture –
with separate memories and buses for program and data. Instructions in the program
memory are executed with a single level pipelining. While one instruction is being
executed, the next instruction is pre-fetched from the program memory. This concept

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enables instructions to be executed in every clock cycle. The program memory is In-
System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers
with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit
(ALU) operation. In a typical ALU operation, two operands are output from the Register
File, the operation is executed, and the result is stored back in the Register File – in one
clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers
for Data Space addressing – enabling efficient address calculations. One of the address
pointers can also be used as an address pointer for look up tables in Flash Program
memory. These added function registers are the 16-bit X-, Y-, and Z-register,
described later in this section.

The ALU supports arithmetic and logic operations between registers or between a
constant and a register. Single register operations can also be executed in the ALU. After
an arithmetic operation, the Status Register is updated to reflect information about the
result of the operation.

Program flow is provided by conditional and unconditional jump and call

instructions, able to directly address the whole address space. Most AVR instructions have
a single 16-bit word format. Every program memory address contains a 16- or 32-bit
instruction.

Program Flash memory space is divided in two sections, the Boot program section
and the Application Program section. Both sections have dedicated Lock bits for write and
read/write protection. The SPM instruction that writes into the Application Flash memory
section must reside in the Boot Program section.

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 During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the Stack. The Stack is effectively allocated in the general data SRAM, and
consequently the Stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines or
interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The
data SRAM can easily be accessed through the five different addressing modes supported
in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory
maps. A flexible interrupt module has its control registers in the I/O space with an
additional global interrupt enable bit in the Status Register. All interrupts have a separate
interrupt vector in the interrupt vector table. The interrupts have priority in accordance with
their interrupt vector position. The lower the interrupt vector address, the higher the
priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as
Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly,
or as the Data Space locations following those of the Register File.

ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32
general purpose working registers. Within a single clock cycle, arithmetic operations
between general purpose registers or between a register and an immediate are executed.
The ALU operations are divided into three main categories – arithmetic, logical, and bit-
functions. Some implementations of the architecture also provide a powerful multiplier
supporting both signed/unsigned multiplication and fractional format. See the “Instruction
Set” section for a detailed description.

Status Register
The Status Register contains information about the result of the most recently
executed arithmetic instruction. This information can be used for altering program flow in

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order to perform conditional operations. Note that the Status Register is updated after all
ALU operations, as specified in the Instruction Set Reference. This will in many cases
remove the need for using the dedicated compare instructions, resulting in faster and more
compact code. The Status Register is not automatically stored when entering an interrupt
routine and restored when returning from an interrupt. This must be handled by software.
The AVR Status Register – SREG – is defined as:

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The
individual interrupt enable control is then performed in separate control registers. If the
Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent
of the individual interrupt enable settings.. The I bit can also be set and cleared by the
application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as
source or destination for the operated bit. A bit from a register in the Register File can be
copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in
the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a half carry in some arithmetic operations. Half
Carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed
information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

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 The S-bit is always an exclusive or between the Negative Flag N and the Two’s
Complement Overflow Flag V. See the “Instruction Set Description” for detailed
information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetic’s.
See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation.
See the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.

General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In
order to achieve the required performance and flexibility, the following input/output
schemes are supported by the Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input

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 Fig: 3.3.1 AVR CPU General Purpose Working Registers

. As shown in Figure, each register is also assigned a data memory address,

mapping them directly into the first 32 locations of the user Data Space. Although not
being physically implemented as SRAM locations, this memory organization provides
great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set
to index any register in the file.
The X-register, Y-register and Z-register
The registers R26..R31 have some added functions to their general purpose usage.
These registers are 16-bit address pointers for indirect addressing of the Data Space. The
three indirect address registers X, Y, and Z are defined as described in Figure below.

Fig: 3.3.2 X-, Y-, Z- Registers

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Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and
for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register
always points to the top of the Stack. Note that the Stack is implemented as growing from
higher memory locations to lower memory locations. This implies that a Stack PUSH
command decreases the Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and
Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack
Pointer must be set to point above $60. The Stack Pointer is decremented by one when data
is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the
return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer
is incremented by one when data is popped from the Stack with the POP instruction, and it
is incremented by two when data is popped from the Stack with return from subroutine
RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number
of bits actually used is implementation dependent. Note that the data space in some
implementations of the AVR architecture is so small that only SPL is needed. In this case,
the SPH Register will not be present.

Instruction Execution Timing

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 This section describes the general access timing concepts for instruction execution.
The AVR CPU is driven by the CPU clock clk CPU, directly generated from the selected
clock source for the chip. No internal clock division is used. Figure shows the parallel
instruction fetches and instruction executions enabled by the Harvard architecture and the
fast-access Register File concept. This is the basic pipelining concept to obtain up to 1
MIPS per MHz with the corresponding unique results for functions per cost, functions per
clocks, and functions per power-unit.

Fig: 3.3.3 parallel instruction fetches and instruction executions enabled by the
Harvard architecture

Below figure shows the internal timing concept for the Register File. In a single
clock cycle an ALU operation using two register operands is executed, and the result is
stored back to the destination register.

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 Fig: 3.3.4 Internal Timing Concepts for the Register File

Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the
separate reset vector each have a separate program vector in the program memory space.
All interrupts are assigned individual enable bits which must be written logic one together
with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
Depending on the Program Counter value, interrupts may be automatically disabled when
Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software
security. See the section “Memory Programming” on page 254 for details.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all
interrupts are disabled. The user software can write logic one to the I-bit to enable nested
interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is
automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event
that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the
actual Interrupt Vector in order to execute the interrupt handling routine, and hardware
clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a
logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the
corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered
until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more
interrupt conditions occur while the Global Interrupt Enable bit is cleared, the
corresponding Interrupt Flag(s) will be set and remembered until the global interrupt enable
bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is
present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition
disappears before the interrupt is enabled, the interrupt will not be triggered

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When the AVR exits from an interrupt, it will always return to the main program and
execute one more instruction before any pending interrupt is served. Note that the Status
Register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be
immediately disabled. No interrupt will be executed after the CLI instruction, even if it
occurs simultaneously with the CLI instruction. The following example shows how this can
be used to avoid interrupts during the timed EEPROM write sequence

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock
cycles minimum. After four clock cycles the program vector address for the actual interrupt
handling routine is executed. During this four clock cycle period, the Program Counter is
pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump
takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction,
this instruction is completed before the interrupt is served. If an interrupt occurs when the
MCU is in sleep mode, the interrupt execution response time is increased by four clock
cycles. This increase comes in addition to the start-up time from the selected sleep mode. A
return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer
is incremented by two, and the I-bit in SREG is set.
3.4 I/O PORTS

Introduction
All AVR ports have true Read-Modify-Write functionality when used as general
digital I/O ports. This means that the direction of one port pin can be changed without
unintentionally changing the direction of any other pin with the SBI and CBI instructions.
The same applies when changing drive value (if configured as output) or enabling/disabling
of pull-up resistors (if configured as input). Each output buffer has symmetrical drive
characteristics with both high sink and source capability. The pin driver is strong enough to

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drive LED displays directly. All port pins have individually selectable pull-up resistors
with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC
and Ground.

Figure: 3.4 I/O Pin Equivalent Schematic

All registers and bit references in this section are written in general form. A lower
case “x” represents the numbering letter for the port, and a lower case “n” represents the bit
number. However, when using the register or bit defines in a program, the precise form
must be used. i.e., PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn.
Three I/O memory address locations are allocated for each port, one each for the Data
Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The
Port Input Pins I/O location is read only, while the Data Register and the Data Direction
Register are read/write. In addition, the Pull-up Disable – PUD bit in SFIOR disables the
pull-up function for all pins in all ports when set.

Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure shows a
functional description of one I/O-port pin, here generically called Pxn.

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 Figure: 3.4.1 General Digital I/O
Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown
in “Register Description for I/O Ports” , the DDxn bits are accessed at the DDRx I/O
address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O
address.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-
up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic
zero or the pin has to be configured as an output pin. The port pins are tri-stated when a
reset condition becomes active, even if no clocks are running.

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high
({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn,
PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the
pull-up enabled state is fully acceptable, as a high-impudent environment will not notice
the difference between a strong high driver and a pull-up. If this is not the case, the PUD
bit in the SFIOR Register can be set to disable all pull-ups in all ports.

Digital Input Enable and Sleep Modes

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 As shown in Figure 3.10, the digital input signal can be clamped to ground at the
input of the Schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU
Sleep Controller in Power-down mode, Power-save mode, Standby mode, and Extended
Standby mode to avoid high power consumption if some input signals are left floating, or
have an analog signal level close to VCC/2.

SLEEP is overridden for port pins enabled as External Interrupt pins. If the External
Interrupt Request is not enabled, SLEEP is active also for these pins. SLEEP is also
Over ridden by various other alternate functions as described in “Alternate Port Functions”

If a logic high level (“one”) is present on an Asynchronous External Interrupt pin

configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while
the External Interrupt is not enabled, the corresponding External Interrupt Flag will be set
when resuming from the above mentioned sleep modes, as the clamping in these sleep
modes produces the requested logic change.

Unconnected pins
If some pins are unused, it is recommended to ensure that these pins have a defined
level. Even though most of the digital inputs are disabled in the deep sleep modes as
described above, floating inputs should be avoided to reduce current consumption in all
other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the
internal pullup. Connecting unused pins directly to VCC or GND is not recommended,
since this may cause excessive currents if the pin is accidentally configured as an output.

Alternate Port Functions

Most port pins have alternate functions in addition to being General Digital
I/Os. Figure 26 shows how the port pin control signals from the simplified Figure 23 can be
overridden by alternate functions. The overriding signals may not be present in all port
pins, but the figure serves as a generic description applicable

26
 The following subsections shortly describe the alternate functions for each port, and
relate the overriding signals to the alternate function. Refer to the alternate function
description for further details.

Special Function I/O Register – SFIOR

• Bit 2 – PUD: Pull-up disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn
and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
See “Configuring the Pin”

Alternate Functions Of Port A

Port A has an alternate function as analog input for the ADC as shown in Table 22.
If some Port A pins are configured as outputs, it is essential that these do not switch when a
conversion is in progress. This might corrupt the result of the conversion.

Table: 3.4 Port A Pins Alternate Function

Alternate Functions of Port B

27
Table: 3.5 Port B Pins Alternate Functions

• SCK – Port B, Bit 7

SCK: Master Clock output, Slave Clock input pin for SPI. When the SPI is enabled
as a Slave, this pin is configured as an input regardless of the setting of DDB7. When the
SPI is enabled as a Master, the data direction of this pin is controlled by DDB7. When the
pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB7
bit.
• MISO – Port B, Bit 6
MISO: Master Data input, Slave Data output pin for SPI. When the SPI is enabled
as a Master, this pin is configured as an input regardless of the setting of DDB6. When the
SPI is enabled as a Slave, the data direction of this pin is controlled by DDB6.

• MOSI – Port B, Bit 5

MOSI: SPI Master Data output, Slave Data input for SPI. When the SPI is enabled
as a Slave, this pin is configured as an input regardless of the setting of DDB5. When the
SPI is enabled as a Master, the data direction of this pin is controlled by DDB5. When the
pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB5
bit.

• SS – Port B, Bit 4
SS: Slave Select input. When the SPI is enabled as a Slave, this pin is configured as
an input regardless of the setting of DDB4. As a Slave, the SPI is activated when this pin is

28
driven low. When the SPI is enabled as a Master, the data direction of this pin is controlled
by DDB4. When the pin is forced by the SPI to be an input, the pull-up can still be
controlled by the PORTB4 bit.

• AIN1/OC0 – Port B, Bit 3

AIN1, Analog Comparator Negative Input. Configure the port pin as input with the
internal pull-up switched off to avoid the digital port function from interfering with the
function of the analog comparator. OC0, Output Compare Match output: The PB3 pin can
serve as an external output for the Timer/Counter0 Compare Match. The PB3 pin has to be
configured as an output (DDB3 set (one)) to serve this function. The OC0 pin is also the
output pin for the PWM mode timer function.

• AIN0/INT2 – Port B, Bit 2

AIN0, Analog Comparator Positive input. Configure the port pin as input with the
internal pull-up switched off to avoid the digital port function from interfering with the
function of the Analog Comparator. INT2, External Interrupt Source 2: The PB2 pin can
serve as an external interrupt source to the MCU.

• T1 – Port B, Bit 1
T1, Timer/Counter1 Counter Source.
• T0/XCK – Port B, Bit 0
T0, Timer/Counter0 Counter Source.
XCK, USART External Clock. The Data Direction Register (DDB0) controls whether the
clock is output (DDB0 set) or input (DDB0 cleared). The XCK pin is active only when the
USART operates in Synchronous mode.

Alternate Functions of Port C

The Port C pins with alternate functions are shown in Table 3.9. If the JTAG interface is
enabled, the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be
activated even if a reset occurs.

29
Table: 3.6 Port C Pins Alternate Functions

• TOSC2 – Port C, Bit 7

TOSC2, Timer Oscillator pin 2: When the AS2 bit in ASSR is set (one) to enable
asynchronous clocking of Timer/Counter2, pin PC7 is disconnected from the port, and
becomes the inverting output of the Oscillator amplifier. In this mode, a Crystal Oscillator
is connected to this pin, and the pin cannot be used as an I/O pin.

• TOSC1 – Port C, Bit 6

TOSC1, Timer Oscillator pin 1: When the AS2 bit in ASSR is set (one) to enable
asynchronous clocking of Timer/Counter2, pin PC6 is disconnected from the port, and
becomes the input of the inverting Oscillator amplifier. In this mode, a Crystal Oscillator is
connected to this pin, and the pin cannot be used as an I/O pin
• TDI – Port C, Bit 5
TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or
Data Register (scan chains). When the JTAG interface is enabled, this pin cannot be used
as an I/O pin.
• TDO – Port C, Bit 4

30
TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register.
When the JTAG interface is enabled, this pin cannot be used as an I/O pin.
The TD0 pin is tri-stated unless TAP states that shifts out data are entered.
• TMS – Port C, Bit 3
TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller
state machine. When the JTAG interface is enabled, this pin cannot be used as an I/O pin.
• TCK – Port C, Bit 2
TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG
interface is enabled, this pin cannot be used as an I/O pin.
• SDA – Port C, Bit 1
SDA, Two-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to
enable the Two-wire Serial Interface, pin PC1 is disconnected from the port and becomes
the Serial Data I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter
on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by
an open drain driver with slew-rate limitation. When this pin is used by the Two-wire
Serial Interface, the pull-up can still be controlled by the PORTC1 bit.

• SCL – Port C, Bit 0

SCL, Two-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to
enable the Two-wire Serial Interface, pin PC0 is disconnected from the port and becomes
the Serial Clock I/O pin for the Two-wire Serial Interface. In this mode, there is a spike
filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is
driven by an open drain driver with slew-rate limitation. When this pin is used by the Two-
wire Serial Interface, the pull-up can still be controlled by the PORTC0 bit.
Note: 1. When enabled, the Two-wire Serial Interface enables slew-rate controls on
the output pins PC0 and PC1. This is not shown in the figure. In addition, spike filters are
connected between the AIO outputs shown in the port figure and the digital logic of the
TWI module.

Alternate Functions of Port D

The Port D pins with alternate functions are shown in Table 3.12.

31
Table: 3.7 Port D Pins Alternate Functions

The alternate pin configuration is as follows:

• OC2 – Port D, Bit 7

OC2, Timer/Counter2 Output Compare Match output: The PD7 pin can serve as an
external output for the Timer/Counter2 Output Compare. The pin has to be configured
as an output (DDD7 set (one)) to serve this function. The OC2 pin is also the output pin for
the PWM mode timer function.

• ICP1 – Port D, Bit 6

ICP1 – Input Capture Pin: The PD6 pin can act as an Input Capture pin for
Timer/Counter1.

• OC1A – Port D, Bit 5

OC1A, Output Compare Match A output: The PD5 pin can serve as an external
output for the Timer/Counter1 Output Compare A. The OC1A pin is also the output pin for
the PWM mode timer function.

• OC1B – Port D, Bit 4

32
 OC1B, Output Compare Match B output: The PD4 pin can serve as an external
output for the Timer/Counter1 Output Compare B. The pin has to be configured as an
output to serve this function.

• INT1 – Port D, Bit 3

INT1, External Interrupt Source 1: The PD3 pin can serve as an external interrupt
source.

• INT0 – Port D, Bit 2

INT0, External Interrupt Source 0: The PD2 pin can serve as an external interrupt
source.

• TXD – Port D, Bit 1

TXD, Transmit Data (Data output pin for the USART). When the USART
Transmitter is enabled, this pin is configured as an output regardless of the value of DDD1.

• RXD – Port D, Bit 0

RXD, Receive Data (Data input pin for the USART). When the USART Receiver is
enabled this pin is configured as an input regardless of the value of DDD0. When the
USART forces this pin to be an input, the pull-up can still be controlled by the PORTD0
bit.
3.5 USART

The Universal Synchronous and Asynchronous serial Receiver and Transmitter

(USART) is a highly flexible serial communication device. The main features are:

• Full Duplex Operation (Independent Serial Receive and Transmit Registers)

• Asynchronous or Synchronous Operation
• Master or Slave Clocked Synchronous Operation
• High Resolution Baud Rate Generator
• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

33
• Odd or Even Parity Generation and Parity Check Supported by Hardware
• Data OverRun Detection
• Framing Error Detection
• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
• Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX
Complete
• Multi-processor Communication Mode
• Double Speed Asynchronous Communication Mode.

Overview
A simplified block diagram of the USART transmitter is shown in CPU
accessible I/O .The dashed boxes in the block diagram separate the three main parts of the
USART (listed from the top): Clock Generator, Transmitter and Receiver. Control
Registers are shared by all units. The clock generation logic consists of synchronization
logic for external clock input used by synchronous slave operation, and the baud rate
generator.

34
 Fig 3.5 Block Diagram Of Usart
.
The XCK (Transfer Clock) pin is only used by Synchronous Transfer mode. The
Transmitter consists of a single write buffer, a serial Shift Register, parity generator and
control logic for handling different serial frame formats.
The write buffer allows a continuous transfer of data without any delay between
frames. The Receiver is the most complex part of the USART module due to its clock and
data recovery units. The recovery units are used for asynchronous data reception.
In addition to the recovery units, the receiver includes a parity checker, control
logic, a Shift Register and a two level receive buffer (UDR). The receiver supports the
same frame formats as the transmitter, and can detect frame error, data overrun and parity
errors.

35
AVR USART vs. AVR UART – Compatibility
The USART is fully compatible with the AVR UART regarding:
• Bit locations inside all USART Registers
• Baud Rate Generation
• Transmitter Operation
• Transmit Buffer Functionality
• Receiver Operation
However, the receive buffering has two improvements that will affect the
compatibility in some special cases:
• A second Buffer Register has been added. The two Buffer Registers operate as a
circular FIFO buffer. Therefore the UDR must only be read once for each incoming data!
More important is the fact that the Error Flags (FE and DOR) and the 9th data bit (RXB8)
are buffered with the data in the receive buffer. Therefore the status bits must always be
read before the UDR Register is read. Otherwise the error status will be lost since the
buffer state is lost.
• The receiver Shift Register can now act as a third buffer level. This is done by
allowing the received data to remain in the serial Shift Register (see Figure 69) if the
Buffer Registers are full, until a new start bit is detected. The USART is therefore more
resistant to Data OverRun (DOR) error conditions.
The following control bits have changed name, but have same functionality and
register location:
• CHR9 is changed to UCSZ2
• OR is changed to DOR

Clock Generation
The clock generation logic generates the base clock for the Transmitter and
Receiver. The USART supports four modes of clock operation: Normal Asynchronous,
Double Speed Asynchronous, Master Synchronous and Slave Synchronous mode. The
UMSEL bit in USART Control and Status Register C (UCSRC) selects between
asynchronous and synchronous operation.

36
Double Speed Operation (U2X)
The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit
only has effect for the asynchronous operation. Set this bit to zero when using synchronous
operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8,
effectively doubling the transfer rate for asynchronous communication. Note however that
the receiver will in this case only use half the number of samples (reduced from 16 to 8) for
data sampling and clock recovery, and therefore a more accurate baud rate setting and
system clock are required when this mode is used. For the Transmitter, there are no
downsides.

External Clock
External clocking is used by the synchronous slave modes of operation. The
description in this section refers to for details.
External clock input from the XCK pin is sampled by a synchronization register to
minimize the chance of meta-stability. The output from the synchronization register must
then pass through an edge detector before it can be used by the Transmitter and receiver.
This process introduces a two CPU clock period delay and therefore the maximum
external XCK clock frequency is limited by the following equation:

Synchronous Clock Operation

When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either
clock input (Slave) or clock output (Master). The dependency between the clock edges and
data sampling or data change is the same. The basic principle is that data input (on RxD) is
sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed.
The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and
which is used for data change. As Figure 71 shows, when UCPOL is zero the data will be
changed at rising XCK edge and sampled at falling XCK edge. If UCPOL is set, the data
will be changed at falling XCK edge and sampled at rising XCK edge.

37
USART REGISTER DESCRIPTION
USART I/O Data Register – UDR

The USART Transmit Data Buffer Register and USART Receive Data Buffer
Registers share the same I/O address referred to as USART Data Register or UDR. The
Transmit Data Buffer Register (TXB) will be the destination for data written to the UDR
Register location. Reading the UDR Register location will return the contents of the
Receive Data Buffer Register (RXB).
The transmit buffer can only be written when the UDRE Flag in the UCSRA
Register is set. Data written to UDR when the UDRE Flag is not set, will be ignored by the
USART Transmitter. When data is written to the transmit buffer, and the Transmitter is
enabled, the Transmitter will load the data into the transmit Shift Register when the Shift
Register is empty. Then the data will be serially transmitted on the TxD pin. The receive
buffer consists of a two level FIFO. The FIFO will change its state whenever the receive
buffer is accessed. Due to this behavior of the receive buffer, do not use read modify write
instructions (SBI and CBI) on this location. Be careful when using bit test instructions
(SBIC and SBIS), since these also will change the state of the FIFO.

USART Control and Status Register A – UCSRA

• Bit 7 – RXC: USART Receive Complete

This flag bit is set when there are unread data in the receive buffer and cleared
when the receive buffer is empty (i.e., does not contain any unread data). If the receiver is
disabled, the receive buffer will be flushed and consequently the RXC bit will become

38
zero. The RXC Flag can be used to generate a Receive Complete interrupt (see description
of the RXCIE bit).
• Bit 6 – TXC: USART Transmit Complete
This flag bit is set when the entire frame in the transmit Shift Register has been
shifted out and there are no new data currently present in the transmit buffer (UDR). The
TXC Flag bit is automatically cleared when a transmit complete interrupt is executed, or it
can be cleared by writing a one to its bit location.
• Bit 5 – UDRE: USART Data Register Empty
The UDRE Flag indicates if the transmit buffer (UDR) is ready to receive new data.
If UDRE is one, the buffer is empty, and therefore ready to be written. The UDRE Flag can
generate a Data Register empty Interrupt (see description of the UDRIE bit).
UDRE is set after a reset to indicate that the transmitter is ready.
• Bit 4 – FE: Frame Error
This bit is set if the next character in the receive buffer had a Frame Error when
received. i.e., when the first stop bit of the next character in the receive buffer is zero. This
bit is valid until the receive buffer (UDR) is read. The FE bit is zero when the stop bit of
received data is one. Always set this bit to zero when writing to UCSRA.
• Bit 3 – DOR: Data OverRun
This bit is set if a Data OverRun condition is detected. A Data OverRun occurs
when the receive buffer is full (two characters), it is a new character waiting in the receive
Shift Register, and a new start bit is detected. This bit is valid until the receive buffer
(UDR) is read. Always set this bit to zero when writing to UCSRA.
• Bit 2 – PE: Parity Error
This bit is set if the next character in the receive buffer had a Parity Error when
received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid
until the receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA
• Bit 1 – U2X: Double the USART Transmission Speed
This bit only has effect for the asynchronous operation. Write this bit to zero when
using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate
divider from 16 to 8 effectively doubling the transfer rate for asynchronous
communication.

39
• Bit 0 – MPCM: Multi-processor Communication Mode
This bit enables the Multi-processor Communication mode. When the MPCM bit is
written to one, all the incoming frames received by the USART receiver that do not contain
address information will be ignored. The transmitter is unaffected by the MPCM setting.
For more detailed information.

USART Control and Status Register B – UCSRB

• Bit 7 – RXCIE: RX Complete Interrupt Enable

Writing this bit to one enables interrupt on the RXC Flag. A USART Receive
Complete Interrupt will be generated only if the RXCIE bit is written to one, the Global
Interrupt Flag in SREG is written to one and the RXC bit in UCSRA is set.
• Bit 6 – TXCIE: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXC Flag. A USART Transmit
Complete Interrupt will be generated only if the TXCIE bit is written to one, the Global
Interrupt Flag in SREG is written to one and the TXC bit in UCSRA is set.
• Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDRE Flag. A Data Register Empty
Interrupt will be generated only if the UDRIE bit is written to one, the Global Interrupt
Flag in SREG is written to one and the UDRE bit in UCSRA is set.

• Bit 4 – RXEN: Receiver Enable

Writing this bit to one enables the USART Receiver. The Receiver will override
normal port operation for the RxD pin when enabled. Disabling the Receiver will flush the
receive buffer invalidating the FE, DOR, and PE Flags.

40
• Bit 3 – TXEN: Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will
override normal port operation for the TxD pin when enabled. when the transmit Shift
Register and transmit Buffer Register do not contain data to be transmitted. When disabled,
the transmitter will no longer override the TxD port.
• Bit 2 – UCSZ2: Character Size
The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data
bits (Character Size) in a frame the receiver and transmitter use.
• Bit 1 – RXB8: Receive Data Bit 8
RXB8 is the ninth data bit of the received character when operating with serial
frames with nine data bits. Must be read before reading the low bits from UDR.
• Bit 0 – TXB8: Transmit Data Bit 8
TXB8 is the ninth data bit in the character to be transmitted when operating with
serial frames with nine data bits. Must be written before writing the low bits to UDR.

USART Control and Status Register C – UCSRC

• Bit 7 – URSEL: Register Select

This bit selects between accessing the UCSRC or the UBRRH Register. It is read as
one when reading UCSRC. The URSEL must be one when writing the UCSRC.
• Bit 6 – UMSEL: USART Mode Select
This bit selects between Asynchronous and Synchronous mode of operation.

• Bit 5:4 – UPM1:0: Parity Mode

41
 These bits enable and set type of parity generation and check. If enabled, the
transmitter will automatically generate and send the parity of the transmitted data bits
within each frame. The Receiver will generate a parity value for the incoming data and
compare it to the UPM0 setting. If a mismatch is detected, the PE Flag in UCSRA will be
set.

• Bit 3 – USBS: Stop Bit Select

This bit selects the number of Stop Bits to be inserted by the Transmitter. The
Receiver ignores this setting.

• Bit 2:1 – UCSZ1:0: Character Size

The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data
bits (Character Size) in a frame the Receiver and Transmitter use.
• Bit 0 – UCPOL: Clock Polarity
This bit is used for Synchronous mode only. Write this bit to zero when
Asynchronous mode is used. The UCPOL bit sets the relationship between data output
change and data input sample, and the synchronous clock (XCK).

42
 4. RFID

 Radio Frequency Identification (RFID) is a silicon chip-based transponder that

communicates via radio waves. Radio Frequency Identification is a technology which uses
tags as a component in an integrated supply chain solution set that will evolve over the next
several years. RFID tags contain a chip which holds an electronic product code (EPC)
number that points to additional data detailing the contents of the package.
 Applications are evolving to comply with shipping products to automatically processing
transactions based on RFID technology.

4.1 Operating principles of RFID systems

There is a huge variety of different operating principles for RFID systems. The picture
below provides a short survey of known operation principles (The numbers refer to the
relating chapters in the book).

The most important principles - ‘inductive coupling’ and ‘backscatter coupling’ are
described more detailed below.

Inductive Coupling (3.2.1)

An inductively coupled transponder comprises of an electronic data carrying device,

usually a single microchip and a large area coil that functions as an antenna.

Inductively coupled transponders are almost always operated passively. This means that all
the energy needed for the operation of the microchip has to be provided by the reader. For
this purpose, the reader's antenna coil generates a strong, high frequency electro-magnetic
field, which penetrates the cross -section of the coil area and the area around the coil.
Because the wavelength of the frequency range used (< 135 kHz: 2400 m, 13.56 MHz: 22.1

43
m) is several times greater than the distance between the reader's antenna and the
transponder, the electro-magnetic field may be treated as a simple magnetic alternating
field with regard to the distance between transponder and antenna .

A small part of the emitted field penetrates the antenna coil of the transponder, which is
some distance away from the coil of the reader. By induction, a voltage Ui is generated in
the transponder's antenna coil. This voltage is rectified and serves as the power supply for
the data carrying device (microchip). A capacitor C1 is connected in parallel with the
reader's antenna coil, the capacitance of which is selected such that it combines with the
coil inductance of the antenna coil to form a parallel resonant circuit, with a resonant
frequency that corresponds with the transmission frequency of the reader. Very high
currents are generated in the antenna coil of the reader by resonance step-up in the parallel
resonant circuit, which can be used to generate the required field strengths for the operation
of the remote transponder.

The antenna coil of the transponder and the capacitor C1 to form a resonant circuit tuned to
the transmission frequency of the reader. The voltage U at the transponder coil reaches a
maximum due to resonance step-up in the parallel resonant circuit.

Fig. 4.1 Block digram of RFID interfacing

As described above, inductively coupled systems are based upon a transformer-type

coupling between the primary coil in the reader and the secondary coil in the

44
transponder. This is true when the distance between the coils does not exceed 0.16 , so that
the transponder is located in the near field of the transmitter antenna .

If a resonant transponder (i.e. the self-resonant frequency of the transponder corresponds

with the transmission frequency of the reader) is placed within the magnetic alternating
field of the reader's antenna, then this draws energy from the magnetic field. This
additional power consumption can be measured as voltage drop at the internal resistance in
the reader antennae through the supply current to the reader's antenna. The switching on
and off of a load resistance at the transponder's antenna therefore effects voltage changes at
the reader's antenna and thus has the effect of an amplitude modulation of the antenna
voltage by the remote transponder. If the switching on and off of the load resistor is
controlled by data, then this data can be transferred from the transponder to the reader. This
type of data transfer is called load modulation.

To reclaim the data in the reader, the voltage measured at the reader's antenna is rectified.
This represents the demodulation of an amplitude modulated signal. An example circuit is
shown in the chapter "Reader – Low Cost Layout".

Fig4.2 sample circuit of the power supply and load modulator in a transponder

Picture above: If the additional load resistor in the transponder is switched on and off at a
very high elementary frequency fH, then two spectral lines are created at a distance

45
of f H around the transmission frequency of the reader, and these can be easily detected
(however fH must be less than fREADER). In the terminology of radio technology the new
elementary frequency is called a subcarrier. Data transfer is by the ASK, FSK or PSK
modulation of the subcarrier in time with the data flow. This represents an amplitude
modulation of the subcarrier.

Backscatter Coupling (3.2.2)

We know from the field of RADAR technology that electromagnetic waves are reflected by
objects with dimensions greater than around half the wavelength of the wave. The
efficiency with which an object reflects electromagnetic waves is described by
its reflection cross-section.Objects that are in resonance with the wave front that hits them,
as is the case for antenna at the appropriate frequency for example, have a particularly large
reflection cross-section.

Fig 4.3 Operation principle of a backscatter transüonder

Power P1 is emitted from the reader's antenna, a small proportion of which (free space
attenuation) reaches the transponder's antenna. The power P1' is supplied to the antenna
connections as HF voltage and after rectification by the diodes D1 and D2 this can be used
as turn on voltage for the deactivation or activation of the power saving "power-down"
mode. The diodes used here are low barrier Schottky diodes, which have a particularly low
threshold voltage. The voltage obtained may also be sufficient to serve as a power supply
for short ranges.

46
A proportion of the incoming power P1' is reflected by the antenna and returned as power
P2. The reflection characteristics of the antenna can be influenced by altering the load
connected to the antenna. In order to transmit data from the transponder to the reader, a
load resistor RL connected in parallel with the antenna is switched on and off in time with
the data stream to be transmitted. The amplitude of the power P2 reflected from the
transponder can thus be modulated

The power P2 reflected from the transponder is radiated into free space. A small proportion
of this) is picked up by the reader's antenna. The reflected signal therefore travels into the
antenna connection of the reader in the "backwards direction" and can be decoupled using a
directional coupler and transferred to the receiver input of a reader. The "forward" signal
of the transmitter, which is stronger by powers of ten, is to a large degree suppressed by the
directional coupler.

Frequency Ranges

Because RFID systems generate and radiate electromagnetic waves, they are justifiably
classified as radio systems. The function of other radio services must under no
circumstances be disrupted or impaired by the operation of RFID systems. It is particularly
important to ensure that RFID systems do not interfere with nearby radio and television,
mobile radio services (police, security services, industry), marine and aeronautical radio
services and mobile telephones.

The need to exercise care with regard to other radio services significantly restricts the range
of suitable operating frequencies available to an RFID system. For this reason, it is usually
only possible to use frequency ranges that have been reserved specifically for industrial,
scientific or medical applications or for short range devices. These are the frequencies
classified worldwide as ISM frequency ranges (Industrial-Scientific-Medical) or SRD
frequency ranges, and they can also be used for RFID applications.

47
 frequency ranges for RFID-Systems
frequency comment allowed fieldstrength /
range transmission power
< 135 kHz low frequency, inductive coupling 72 dBµA/m max
3.155 ... EAS 13.5 dBµA/m
3.400 MHz
6.765 .. medium frequency (ISM), inductive coupling 42 dBµA/m
6.795 MHz
7.400 .. medium frequency, used for EAS (electronic 9 dBµA/m
8.800 MHz article surveilance) only
13.553 .. medium frequency (13.56 MHz, ISM), inductive 60(!) dBµA/m
13.567 coupling, wide spread usage for contactless
MHz smartcards (ISO 14443, MIFARE, LEGIC, ...),
smartlabels (ISO 15693, Tag-It, I-Code, ...) and
item management (ISO 18000-3).
26.957 .. medium frequency (ISM), inductive coupling, 42 dBµA/m
27.283 special applications only
MHz
433 MHz UHF (ISM), backscatter coupling, rarely used for 10 .. 100 mW
RFID
865 .. 868 UHF (RFID only), Listen before talk 100 mW ERP
MHz Europe only
865.6 .. UHF (RFID only), Listen before talk 2W ERP (=3.8W
867.6 MHz EIRP)
Europe only

Table: 4.1 Frequency ranges used for RFID-systems (August 2006)

5 .SERIAL COMMUNICATION

INTRODUCTION:

48
 The Serial Port is harder to interface than the Parallel Port. In most cases, any
device you connect to the serial port will need the serial transmission converted back to
parallel so that it can be used. This can be done using a UART. On the software side of
things, there are many more registers that you have to attend to than on a Standard Parallel
Port. (SPP) So what are the advantages of using serial data transfer rather than parallel?

1. Serial Cables can be longer than Parallel cables. The serial port transmits a '1' as
-3 to -25 volts and a '0' as +3 to +25 volts where as a parallel port transmits a '0' as 0v and a
'1' as 5v. Therefore the serial port can have a maximum swing of 50V compared to the
parallel port which has a maximum swing of 5 Volts. Therefore cable loss is not going to
be as much of a problem for serial cables as they are for parallel.

2. You don't need as many wires as parallel transmission. If your device needs to be
mounted a far distance away from the computer then 3 core cable (Null Modem
Configuration) is going to be a lot cheaper that running 19 or 25 core cable. However you
must take into account the cost of the interfacing at each end.

3. Infra Red devices have proven quite popular recently. You may have seen many
electronic diaries and palmtop computers which have infra red capabilities build in.
However could you imagine transmitting 8 bits of data at the one time across the room and
being able to (from the devices point of view) decipher which bits are which? Therefore
serial transmission is used where one bit is sent at a time. IrDA-1 (The first infra red
specifications) was capable of 115.2k baud and was interfaced into a UART. The pulse
length however was cut down to 3/16th of a RS232 bit length to conserve power
considering these devices are mainly used on diaries, laptops and palmtops.

4. Microcontroller's have also proven to be quite popular recently. Many of these

have in built SCI (Serial Communications Interfaces) which can be used to talk to the
outside world. Serial Communication reduces the pin count of these MPU's. Only two pins
are commonly used, Transmit Data (TXD) and Receive Data (RXD) compared with at least
8 pins if you use an 8 bit Parallel method (You may also require a Strobe)

49
 Information being transferred between data processing equipment and peripherals is
in the form of digital data which is transmitted in either a serial or parallel mode. Parallel
communications are used mainly for connections between test instruments or computers
and printers, while serial is often used between computers and other peripherals. Serial
transmission involves the sending of data one bit at a time, over a single communications
line. In contrast, parallel communications require at least as many lines as there are bits in a
word being transmitted (for an 8-bit word, a minimum of 8 lines are needed). Serial
transmission is beneficial for long distance communications, whereas parallel is designed
for short distances or when very high transmission rates are required.

5.1.2. RS-232 STANDARDS

One of the advantages of a serial system is that it lends itself to transmission over
telephone lines. The serial digital data can be converted by modem, placed onto a standard
voice-grade telephone line, and converted back to serial digital data at the receiving end of
the line by another modem. Officially, RS-232 is defined as the “Interface between data
terminal equipment and data communications equipment using serial binary data
exchange.” This definition defines data terminal equipment (DTE) as the computer, while
data communications equipment (DCE) is the modem. A modem cable has pin-to-pin
connections, and is designed to connect a DTE device to a DCE device.
In addition to communications between computer equipment over telephone lines,
RS-232 is now widely used for direct connections between data acquisition devices and
computer systems. As in the definition of RS-232, the computer is data transmission
equipment (DTE). However, many interface products are not data communications
equipment (DCE). Null modem cables are designed for this situation; rather than having
the pin- to-pin connections of modem cables, null modem cables have different internal
wiring to allow DTE devices to communicate with one another.
RS-232 cables are commonly available with 4, 9 or 25-pin wiring. The 25-pin cable
connects every pin; the 9-pin cables do not include many of the uncommonly used
connections; 4-pin cables provide the bare minimum connections, and have jumpers to
provide “handshaking” for those devices that require it. These jumpers connect pins 4, 5

50
and 8, and also pins 6 and 20. The advent of the IBM PC AT has created a new wrinkle in
RS-232 communications. Rather than having the standard 25-pin connector, this computer
and many new expansion boards for PC’s feature a 9-pin serial port. To connect this port to
a standard 25- pin port, a 9-to-25-pin adaptor cable can be utilized, or the user can create
his own cable specifically for that purpose. Selecting a Cable The major consideration in
choosing an RS-232 cable is what devices are to be connected? First, are you connecting
two DTE devices (null modem cable) or a DTE device to a DCE device (modem cable)?
Second, what connectors are required on each end, male or female, 25-pin or 9-pin (AT
style)? Usually, it is recommended that the user obtain the two devices to be connected, and
then determine which cable is required.
5.1.3. HARDWARE PROPERTIES

Devices which use serial cables for their communication are split into two
categories. These are DCE (Data Communications Equipment) and DTE (Data Terminal
Equipment.) Data Communications Equipment are devices such as your modem, TA
adapter, plotter etc while Data Terminal Equipment is your Computer or Terminal.

The electrical specifications of the serial port are contained in the EIA (Electronics
Industry Association) RS232C standard. It states many parameters such as -

1. A "Space" (logic 0) will be between +3 and +25 Volts.

2. A "Mark" (Logic 1) will be between -3 and -25 Volts.
3. The region between +3 and -3 volts is undefined.
4. An open circuit voltage should never exceed 25 volts. (In
Reference to GND)
5. A short circuit current should not exceed 500mA. The driver
should be able to handle this without damage. (Take note of
this one!)

Above is no where near a complete list of the EIA standard. Line Capacitance,
Maximum Baud Rates etc are also included. For more information please consult the EIA
RS232-C standard. It is interesting to note however, that the RS232C standard specifies a
maximum baud rate of 20,000 BPS!, which is rather slow by today's standards. A new
standard, RS-232D has been recently released.

51
 Serial Ports come in two "sizes", there are the D-Type 25 pin connector and the D-
Type 9 pin connector both of which are male on the back of the PC, thus you will require a
female connector on your device. Below is a table of pin connections for the 9 pin and 25
pin D-Type connectors. Serial Pin outs (D9Connector

Table 5.1 DB9 Pin Connectors

D-Type-
9 Abbreviation Full Name
Pin No.
Transmit
Pin 3 TD
Data
Pin 2 RD Receive Data
Request To
Pin 7 RTS
Send
Clear To
Pin 8 CTS
Send
Data Set
Pin 6 DSR
Ready
Signal
Pin 5 SG
Ground
Pin 1 CD Carrier Detect
Data
Pin 4 DTR Terminal
Ready
Ring
Pin 9 RI
Indicator

52
 Fig 5.1: DB9 PIN &DB 25 PIN configurations

Abbreviation Full
Function
Name
TD Transmit
Serial Data Output (TXD)
Data

53
 RD Receive
Serial Data Input (RXD)
Data
CTS Clear to This line indicates that the
Send Modem is ready to exchange
data.
DCD Data When the modem detects a
Carrier "Carrier" from the modem at the
Detect other end of the phone line, this
Line becomes active.
DSR Data Set This tells the UART that the
Ready modem is ready to establish a
link.
DTR Data This is the opposite to DSR. This
Terminal tells the Modem that the UART
Ready is ready to link.
RTS Request This line informs the Modem
To Send that the UART is ready to
exchange data.
RI Ring Goes active when modem detects
Indicator a ringing signal

Table 5.1.1 :DB9 pin functionality

5.1.4 DATA TRANSFER

SYNCHRONOUS DATA TRANSFER

In program-to-program communication, synchronous communication requires that

each end of an exchange of communication respond in turn without initiating a new
communication. A typical activity that might use a synchronous protocol would be a
transmission of files from one point to another. As each transmission is received, a
response is returned indicating success or the need to resend.

54
ASYNCHRONOUS DATA TRANSFER

The term asynchronous is usually used to describe communications in which data

can be transmitted intermittently rather than in a steady stream. For example, a telephone
conversation is asynchronous because both parties can talk whenever they like. If the
communication were synchronous, each party would be required to wait a specified interval
before speaking. The difficulty with asynchronous communications is that the receiver
must have a way to distinguish between valid data and noise. In computer communications,
this is usually accomplished through a special start bit and stop bit at the beginning and end
of each piece of data. For this reason, asynchronous communication is sometimes called
start-stop transmission.

5.2 LINE DRIVER

The MAX220–MAX249 family of line drivers/receivers is intended for all

EIA/TIA-232E and V.28/V.24 communications interfaces, particularly applications where
±12V is not available. These parts are especially useful in battery-powered systems, since
their low-power shutdown mode reduces power dissipation to less than 5μW. The
MAX225, MAX233, MAX235, and MAX245/MAX246/MAX247 use no external
components and are recommended for applications where printed circuit board space is
critical.

55
 Fig 5.2: Internal Diagram of MAX232

The MAX220–MAX249 contain four sections: dual charge-pump DC-DC voltage

converters, RS-232 drivers, RS-232 receivers, and receiver and transmitter enable control
inputs.

Dual Charge-Pump Voltage Converter

The MAX220–MAX249 has two internal charge-pumps that convert +5V to ±10V
(unloaded) for RS-232 driver operation. The first converter uses capacitor C1 to double the
+5V input to +10V on C3 at the V+ output. The second converter uses capacitor C2 to
invert +10V to -10V on C4 at the V- output. A small amount of power may be drawn from
the +10V (V+) and -10V (V-) outputs to power external circuitry except on the MAX225
and MAX245–MAX247, where these pins are not available. V+ and V- are not regulated,
so the output voltage drops with increasing load current. Do not load V+ and V- to a point
that violates the minimum ±5V EIA/TIA-232E driver output voltage when sourcing current

56
from V+ and V- to external circuitry. When using the shutdown feature in the MAX222,
MAX225, MAX230, MAX235, MAX236, MAX240, MAX241, and MAX245–MAX249,
avoid using V+ and Vto power external circuitry. When these parts are shut down, V- falls
to 0V, and V+ falls to +5V. For applications where a +10V external supply is applied to the
V+ pin (instead of using the internal charge pump to generate +10V), the C1 capacitor must
not be installed and the SHDN pin must be tied to VCC. This is because V+ is internally
connected to VCC in shutdown mode.

RS-232 DRIVERS:
The typical driver output voltage swing is ±8V when loaded with a nominal 5kΩ
RS-232 receiver and VCC = +5V. Output swing is guaranteed to meet the EIA/TIA- 232E
and V.28 specification, which calls for ±5V minimum driver output levels under worst-case
conditions. These include a minimum 3kΩ load, VCC = +4.5V, and maximum operating
temperature. Unloaded driver output voltage ranges from (V+ -1.3V) to (V- +0.5V).

Input thresholds are both TTL and CMOS compatible. The inputs of unused drivers
can be left unconnected since 400kΩ input pull-up resistors to VCC are built in (except for
the MAX220). The pull-up resistors force the outputs of unused drivers low because all
drivers invert. The internal input pull-up resistors typically source 12μA, except in
shutdown mode where the pull-ups are disabled. Driver outputs turn off and enter a high-
impedance state—where leakage current is typically

Microamperes (maximum 25μA) when in shutdown mode, in three-state mode, or

when device power is removed. Outputs can be driven to ±15V. The power supply current
typically drops to 8μA in shutdown mode. The MAX220 does not have pull-up resistors to
force the outputs of the unused drivers low. Connect unused inputs to GND or VCC.

The MAX239 has a receiver three-state control line, and the MAX223, MAX225,
MAX235, MAX236, MAX240, and MAX241 have both a receiver three-state control line
and a low-power shutdown control. Table 2 shows the effects of the shutdown control and
receiver three state controls on the receiver outputs.

57
Receiver and Transmitter Enable Control Inputs
The MAX225 and MAX245–MAX249 feature transmitter and receiver enable
controls. The receivers have three modes of operation: full-speed receive (normal active)
‚ three-state (disabled) ‚ and low power receive (enabled receivers continue to function at
lower data rates). The receiver enables inputs control the full-speed receive and three-state
modes. The transmitter enable inputs also control the shutdown mode. The device enters
shutdown mode when all transmitters are disabled. Enabled receivers function in the low-
power receive mode when in shutdown.
The control states. The MAX244 has no control pins and is not included in these
tables. The MAX246 has ten receivers and eight drivers with two control pins, each
controlling one side of the device. A logic high at the A-side control input (ENA) causes
the four A-side receivers and drivers to go into a three-state mode. Similarly, the B-side
control input (ENB) causes the four B-side drivers and receivers to go into a three-state
mode. As in the MAX245, one aside and one B-side receiver (RA5 and RB5) remain active
at all times.
The MAX247 provides nine receivers and eight drivers with four control pins. The
ENRA and ENRB receiver enable inputs each control four receiver outputs.The MAX249
provides ten receivers and six drivers with four control pins. The ENRA and ENRB
receiver enable inputs each control five receiver outputs. The device enters shutdown mode
and transmitters go into a three-state mode with logic high on both ENTA and ENTB. In
shutdown mode, active receivers operate in a low-power receive mode at data rates up to
20kbits/sec.

APPLICATIONS:
• Portable Computers
• Low-Power Modems
• Interface Translation
• Battery-Powered RS-232 Systems
• Multi drop RS-232 Networks

6. LCDMODULE

58
 A liquid crystal is a material (normally organic for LCDs) that will flow like a liquid but
whose molecular structure has some properties normally associated with solids. The Liquid
Crystal Display (LCD) is a low power device. The power requirement is typically in the
order of microwatts for the LCD. However, an LCD requires an external or internal light
source. It is limited to a temperature range of about 0C to 60C and lifetime is an area of
concern, because LCDs can chemically degrade.
There are two major types of LCDs which are:
Dynamic-scattering LCDs and
Field-effect LCDs
Field-effect LCDs are normally used in such applications where source of energy is
a prime factor (e.g., watches, portable instrumentation etc.).They absorb considerably less
power than the light-scattering type. However, the cost for field-effect units is typically
higher, and their height is limited to 2 inches. On the other hand, light-scattering units are
available up to 8 inches in height. Field-effect LCD is used in the project for displaying the
appropriate information
The turn-on and turn-off time is an important consideration in all displays. The
response time of LCDs is in the range of 100 to 300ms.The lifetime of LCDs is steadily
increasing beyond 10,000+hours limit. Since the color generated by LCD units is
dependent on the source of illumination, there is a wide range of color choice.
LCD Modules can present textual information to user. It’s like a cheap “monitor”
that you can hook in all of your gadgets. They come in various types. The most popular one
can display 2 lines of 16 characters. These can be easily interfaced to microcontrollers
The modules have 16 PIN’S for interfacing. The details of the pins are:

Table: 6.1

59
 NO NAME
1 VSS (GND supply)
2 VCC (+5V supply)
3 VEE (contrast adjust)
4 RS
5 R/W
6 E
7 DBO
8 DB1
9 DB2
10 DB3
11 DB4
12 DB5
13 DB6
14 DB7
15 LED (+)
16 LED (-)

Hardware Diagram:

Fig: 6.1 16 x 2 Char LCD

RS (Command / Data):
This bit is to specify whether received byte is command or data. So that LCD can recognize
the operation to be performed based on the bit status.
RS = 0 => Command
RS = 1 => Data

RW (Read / Write): A K D7
60
RW bit is to specify whether controller wants READ from LCD or WRITE to LCD. The
READ operation here is just ACK bit to know whether LCD is free or not.
RW = 0 => Write
RW = 1 => Read

EN (Enable LCD):
EN bit is to ENABLE or DISABLE the LCD. Whenever controller wants to write
something into LCD or READ acknowledgment from LCD it needs to enable the LCD.
EN = 0 => High Impedance
EN = 1 => Low Impedance

ACK (LCD Ready):

ACK bit is to acknowledge the MCU that LCD is free so that it can send new command
or data to be stored in its internal Ram locations
ACK = 1 => Not ACK
ACK = 0 => ACK

7. MOTORS

Microcontroller provides 10 milli amps current from each port. This current is not
sufficient to drive the motors so an H- bridge driver circuit is required for driving the
motor which amplifies the current up to 1A. So in L293D driver IC internally four H-
bridge drivers are provided for four channels. Each channel provides max 1A current so it

61
can drive four dc motors in one direction. This L293D driver IC is interfaced with port 1
of microcontroller. For bidirectional controlling of dc motors forward and backward two
channels are connected to one motor and other two channels to another motor. By
changing the polarities of dc motor it can move in forward and backward.

L293D MOTOR DRIVER

Description: A DC Motor Object is a Hardware Object that uses three digital I/O
lines to control the direction, speed, and braking of a DC Motor by communicating with
an H-Bridge circuit which handles the voltage and current requirements of the DC Motor
it is connected to. The H-Bridge that the DC Motor Object is designed to work with has 2
drive inputs and a PWM input. The L293 and L298 H-Bridges are configured in this
way.
The DC Motor Object is capable of driving a DC Motor at 255 different speeds, in
forward or reverse plus free spinning, active braking, and friction braking modes. The
speed at which the motor spins is specified by a single value which can be configured to
have a range of 0 to 255 or -128 to +127.
When the speed value is configured with a range of -128 to +127, the speed value
is then also used to specify the direction that the motor turns. When this value is 0, the
motor is at free-spinning rest. When the value is a positive number from 1 to 127, the
motor turns forward at the speed indicated by the value. The higher the value, the faster
the motor turns. When the value is a negative number from -1 to -128, the motor turns
backwards at the speed indicated by the value. The lower the number, the faster the
motor turns in reverse.
When the speed value is configured with a range of 0 to 255, the motor turns in a
direction specified by a direction value at the rate specified by the speed value. When this
value is 0, the motor is at free-spinning rest.
When the value is 1 to 255, the motor turns forward at the speed indicated by the
value. The higher the value, the faster the motor turns. The physical direction that the
motor will turn can be set to: forward turns clockwise and reverse turns counter-
clockwise or forward turns counter-clockwise and reverse turns clockwise. A brake value

62
is used to apply brakes and when this value is set to 1, the speed value is ignored and the
motor will quickly stop. The method used to stop the motor is active braking. The
maximum number of DC Motor Objects that can be dimensioned in a single application
program is 2, limited only be the number of PWM channels are available.

H BRIDGE CIRCUIT

Fig 7.1 Circuit Diagram Of H-Bridge Circuit

Operation:
The DC Motor Object monitors the Value and the Brake properties, and
based on their numeric values controls the direction, speed, and braking of a DC Motor by
outputting control signals to a H-Bridge motor driver circuit such as the L293D. To
control the speed of the motor, a Pulse-Width-Modulated (PWM) clock cycle is outputted
on the I/O line specified by the IOLineP property.

63
 The direction that the motor spins is controlled by setting one of the
control lines specified by IOLine1 and IOLine2 properties to 1 while setting the other to
0. Whether or not the brakes are applied is controlled by outputting the same value to both
of the control lines specified by IOLine1 and IOLine2 properties. The L293D H-Bridge
monitors the state of all three of these control lines and controls the DC motor
accordingly.
In normal operation, a 0 in the Value property will cause the PWM line to
output 0 Volts, causing the motor to be at a full stop. If the Value property is greater than
0, then the Pulse-Width of the PWM output is set to correspond to the Value property, the
Direction property is set to 0, the I/O line specified by the IOLine1 property is set to 5
Volts and the I/O line specified by the IOLine2 property is set to 0 Volts.
This will cause the DC Motor to go backwards at a speed specified by the
Value property. The lower the number (down to negative 128), the faster the motor will
turn in reverse. If the Unsigned property is set to 1, then the operation is modified so that
the Value property is always expected to be a positive value. In this case, the application
program is expected to set the value of the Direction property, and the control lines
specified by the IOLine1 and IOLine2 properties are set according to the value that the
Direction property was set to.
The actual direction that the DC Motor spins when going in the "forward"
direction can be reversed by setting the Invert Out property to 1. When the Brake property
is set to 1, both of the control lines specified by the IOLine1 and IOLine2 properties are
set to the value specified by the InvertOutB property and the PWM output is set to the
value specified by the Mode property. The required state of the PWM while braking is on
depends on the control circuit that is used.
If the motor is being driven by an L293D H-Bridge, then setting both the control
lines to the same value will cause the Motor to generate power back into itself, effectively
driving the motor back the other way which causes the motor to come to an abrupt stop.
In this case, the Mode property need to be 1 which will set the PWM line to 5 Volts so
that the motor will remain on to allow the braking power to be applied.

64
 However, if the Brake line is connected to a mechanical braking system, then the
Mode property needs to be 0 which will set the PWM line to 0 Volts so that the Motor
will shut off when the mechanical brake is applied.

The combination of the period and the pre scale properties specify the PWM clock
cycle's frequency. The pre scale property specifies how many times a 5-Mhz clock is
divided. This scaled down 5-Mhz clock is used to increment a Period-Duration Counter.
A full PWM clock cycle has been reached when the Period-Duration Counter reaches the
value specified by the period property. The pre scale property can be set to divide the 5-
Mhz clock by 1, 4, or 16, giving frequencies of 5-Mhz, 1.25-Mhz, and 312.5-Khz. The
period property can be set to any value from 1 to 255. This results in 765 possible
frequencies.

The period property also dictates the resolution of the PWM pulse. If the period
property Is set to 255 then the value property's range is 0 - 255. Likewise, if the period
property is set to 10, then the value property's effective range is 0 - 10, because any value
above 10 will never be reached by the Period-Duration Counter.

The L293D H-Bridge is a dual H-Bridge and each one of its H-Bridges is a set of
2 push-pull drivers that use a total of 3 I/O lines. IOLine1 and IOLine2 can be any 2 I/O
lines of the OOPic's 31 I/O lines. IOLineP can be I/O line 17 or 18. The L293D H-

65
Bridge requires a power supply that is capable of handling enough current to dive the
attached DC motor.

Fig 7.2 Block diagram of L-293D & DC Motor

8. POWERSUPPLY

BLOCK DIAGRAM

66
 Fig 8.1 Block Diagram of Power Supply

INDIVIDUAL UNIT DESCRIPTION:

STEP DOWN TRANSFORMER:

When AC is applied to the primary winding of the power transformer it can either
be stepped down or up depending on the value of DC needed. In our circuit the transformer
of 230v/15-0-15v is used to perform the step down operation where a 230V AC appears as
15V AC across the secondary winding. One alteration of input causes the top of the
transformer to be positive and the bottom negative. The next alteration will temporarily
cause the reverse. The current rating of the transformer used in our project is 2A. Apart
from stepping down AC voltages, it gives isolation between the power source and power
supply circuitries.

RECTIFIER UNIT:

In the power supply unit, rectification is normally achieved using a solid state
diode. Diode has the property that will let the electron flow easily in one direction at proper

67
biasing condition. As AC is applied to the diode, electrons only flow when the anode and
cathode is negative. Reversing the polarity of voltage will not permit electron flow.

A commonly used circuit for supplying large amounts of DC power is the bridge rectifier.
A bridge rectifier of four diodes (4*IN4007) are used to achieve full wave rectification.
Two diodes will conduct during the negative cycle and the other two will conduct during
the positive half cycle. The DC voltage appearing across the output terminals of the bridge
rectifier will be somewhat less than 90% of the applied rms value. Normally one alteration
of the input voltage will reverse the polarities. Opposite ends of the transformer will
therefore always be 180 deg out of phase with each other.
For a positive cycle, two diodes are connected to the positive voltage at the top
winding and only one diode conducts. At the same time one of the other two diodes
conducts for the negative voltage that is applied from the bottom winding due to the
forward bias for that diode. In this circuit due to positive half cycleD1 & D2 will conduct
to give 10.8v pulsating DC. The DC output has a ripple frequency of 100Hz. Since each
altercation produces a resulting output pulse, frequency = 2*50 Hz. The output obtained is
not a pure DC and therefore filtration has to be done.

FILTERING UNIT

Filter circuits which are usually capacitors acting as a surge arrester always follow the
rectifier unit. This capacitor is also called as a decoupling capacitor or a bypassing
capacitor, is used not only to ‘short’ the ripple with frequency of 120Hz to ground but also
to leave the frequency of the DC to appear at the output. A load resistor R1 is connected so
that a reference to the ground is maintained. C1R1 is for bypassing ripples.

VOLTAGE REGULATORS:

The voltage regulators play an important role in any power supply unit. The
primary purpose of a regulator is to aid the rectifier and filter circuit in providing a constant

68
 DC voltage to the device. Power supplies without regulators have an inherent problem of
changing DC voltage values due to variations in the load or due to fluctuations in the AC
liner voltage. With a regulator connected to the DC output, the voltage can be maintained
within a close tolerant region of the desired output. IC7812 and 7912 is used in this project
for providing +12v and –12v DC supply.

Fig 8.2 Common Terminal with mounting base

A variable regulated power supply, also called a variable bench power supply, is one where
you can continuously adjust the output voltage to your requirements. Varying the output of
the power supply is the recommended way to test a project after having double checked
parts placement against circuit drawings and the parts placement guide.

CIRCUIT DIAGRAM

69
 Fig 8.3 Circuit diagram of power supply

CIRCUIT DESCRIPTION

The +5 volt power supply is based on the commercial 7805 voltage regulator
IC. This IC contains all the circuitry needed to accept any input voltage from 8 to 18
volts and produce a steady +5 volt output, accurate to within 5% (0.25 volt). It also
contains current-limiting circuitry and thermal overload protection, so that the IC won't
be damaged in case of excessive load current; it will reduce its output voltage instead.

The 1000µf capacitor serves as a "reservoir" which maintains a

reasonable input voltage to the 7805 throughout the entire cycle of the ac line
voltage. The two rectifier diodes keep recharging the reservoir capacitor on alternate
half-cycles of the line voltage, and the capacitor is quite capable of sustaining any
reasonable load in between charging pulses.

The 10µf and .01µf capacitors serve to help keep the power supply
output voltage constant when load conditions change. The electrolytic capacitor
smooth’s out any long-term or low frequency variations. However, at high
frequencies this capacitor is not very efficient. Therefore, the .01µf is included to
bypass high-frequency changes, such as digital IC switching effects, to ground.

70
 The LED and its series resistor serve as a pilot light to indicate when
the power supply is on. I like to use a miniature LED here, so it will serve that
function without being obtrusive or distracting while I'm performing an experiment. I
also use this LED to tell me when the reservoir capacitor is completely discharged
after power is turned off. Then I know it's safe to remove or install components for
the next experiment.

TESTING:

Set your voltmeter to measure voltages up to 20 volts, and connect the

black (Common or Ground) lead to the negative lead of the 1000µf capacitor.
Connect the red lead to the upper end of the 0.3" red jumper wire. Turn on your
voltmeter, and then turn on power to your transformer and power supply circuit.

You should measure a steady +5 volts (+4.75 to +5.25) here, at the

power supply output, and the red pilot LED should turn on. If you get these results,
move your redvoltmeter lead to the positive lead of the 1000µf reservoir capacitor.
You should see about +17 volts here, possibly higher.

If you get the correct results, turn off your power supply and voltmeter, and
skip down to the Discussion below. If your results are different, quickly note the
results you did obtain; then turn power off and look through the following
troubleshooting chart.

Output voltage is steady at +5, but LED remains off.

LED is reversed. Remove it and re-insert it in the opposite direction. Then try
the power supply again.

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 Resistor is the wrong value or connected incorrectly. Make sure it is a 1K
resistor (brown-black-red) and is connected from the lower end of the red jumper to
the left (anode) end of the LED. Then try the power supply again.

Output voltage rises to +5 volts, but then declines steadily.

One or both electrolytic capacitors is reversed. The reversed one will be warm
or hot to the touch. If you leave power on too long, it will explode and leave a large
mess to be cleaned up. Check and correct capacitor orientation, and then try the
power supply again.

Output voltage is negative.

Your main rectifier diodes are installed backwards. Refer back to the assembly
diagram and install them correctly. Output voltage is incorrect. 7805 voltage regulator is
installed incorrectly or is defective. Verify correct installation and replace if necessary.
Once you are sure that your power supply is working correctly in all respects, turn off
power to your circuit and your voltmeter. Then move down to the concluding discussion
below.

PARTS LIST

U1- 7805 three terminal +5V Voltage regulator

D1- DB102 bridge diode
D2- 1N4001 silicon rectifier diode
C1- 1000uF, 25V, electrolytic capacitor
C2- 10uF, 16V, electrolytic capacitor
C3- 0.1uF disc ceramic capacitor
T1- transformer 220V primary 7.5V secondary 500mA

9. SOFTWARE MODULES

TYPES OF MODULES:
• CVAVR IDE TOOL

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 • ISP PROGRAMMER
• EMDEDDED C PROGRAMMING

IN-SYSTEM PROGRAMMER

It is the ability of some programmable logic devices, micro controllers, and other
programmable electronic chips to be programmed while installed in a complete system,
rather than requiring the chip to be programmed prior to installing it into the system.

The primary advantage of this feature is that it allows manufacturers of electronic

devices to integrate programming and testing into a single production phase, rather than
requiring a separate programming stage prior to assembling the system. This may allow
manufacturers to program the chips in their own system's production line instead of buying
preprogrammed chips from a manufacturer or distributor, making it feasible to apply code
or design changes in the middle of a production run.

Typically, chips supporting ISP have internal circuitry to generate any necessary
programming voltage from the system's normal supply voltage, and communicate with the
programmer via a serial protocol. Most programmable logic devices use a variant of
the JTAG protocol for ISP, in order to facilitate easier integration with automated testing
procedures. Other devices usually use proprietary protocols or protocols defined by older
standards. In systems complex enough to require moderately large glue logic, designers
may implement a JTAG-controlled programming subsystem for non-JTAG devices such
as flash memory and microcontrollers, allowing the entire programming and test procedure
to be accomplished under the control of a single protocol.

EMBEDDED C PROGRAMMING:

High-level language programming has long been in use for embedded-systems

development. However, assembly programming still prevails, particularly for digital-signal

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processor (DSP) based systems. DSPs are often programmed in assembly language by
programmers who know the processor architecture inside out. The key motivation for this
practice is performance, despite the disadvantages of assembly programming when
compared to high-level language programming.

If the video decoding takes 80 percent of the CPU-cycle budget instead of 90

percent, for instance, there are twice as many cycles available for audio processing. This
coupling of performance to end-user features is characteristic of many of the real-time
applications in which DSP processors are applied.

Embedded C is not part of the C language as such. Rather, it is a C language

extension that is the subject of a technical report by the ISO working group named
"Extensions for the Programming Language C to Support Embedded Processors" [3]. It
aims to provide portability and access to common performance-increasing features of
processors used in the domain of DSP and embedded processing. The Embedded C
specification for fixed-point, named address spaces, and named registers gives the
programmer direct access to features in the target processor, thereby significantly
improving the performance of applications.

The hardware I/O extension is a portability feature of Embedded C. Its goal is to

allow easy porting of device-driver code between systems. In this article, we focus on the
performance-improving features of Embedded C.

DSPs have a highly specialized architecture to achieve the performance

requirements for signal processing applications within the limits of cost and power
consumption set for consumer applications. Unlike a conventional Load-Store (RISC)
architecture, DSPs have a data path with memory-access units that directly feed into the
arithmetic units. Address registers are taken out of the general-purpose register file and
placed next to the memory units in a separate register file.

A further specialization of the data path is the coupling of multiplication and

addition to form a single cycle Multiply-accumulate unit (MAC). It is combined with

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special-purpose accumulator registers, which are separate from the general-purpose
registers.

Data memory is segmented and placed close to the MAC to achieve the high
bandwidths required to keep up with the streamlined data path. Limits are often placed on
the extent of memory-addressing operations. The localization of resources in the data path
saves many data movements that typically take place in Load-Store architecture.

The most important, common arithmetic extension to DSP architectures is the

handling of saturated fixed-point operations by the arithmetic unit. Fixed-point arithmetic
can be implemented with little additional cost over integer arithmetic. Automatic saturation
(or clipping) significantly reduces the number of control-flow instructions needed for
checking overflow explicitly in the program.

DSP architectures are not easy to program optimally, either by hand or with
compilers. Manual assembly programming is awkward because of the none orthogonally of
the architecture and arbitrary restrictions that can be in place. Modern compilers can deal
with none orthogonally reasonably well, but are not good at exploiting the special features
that DSP processors have in place.

Current state-of-the-art embedded applications (mobile phones, for example) are

implemented using two processors. One processor is a low-power RISC processor that
takes care of all control processing, user interaction, and display management. It is
programmed in a high-level language using an SDK that includes a compiler. The other
processor is a DSP, which takes care of all of the signal processing. The signal-processing
algorithms are typically hand-coded in assembly.

Changes in technological and economic requirements make it more expensive to

continue programming DSPs in assembly. Staying with the mobile phone as an example,
the signal-processing algorithms required become increasingly complex. Features such as
stronger error correction and encryption must be added. Communication protocols become
more sophisticated and require much more code to implement. In certain markets, multiple
protocol stacks are implemented to be compatible with multiple service providers. In

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addition, backward compatibility with older protocols is needed to stay synchronized with
provider networks that are in a slow process of upgrading.

On the economic side, time-to-market for new technology puts increasing pressure
on design time. In 2004, the number of mobile phones sold worldwide is in the order of 500
million. In the western world, the time-to-replacement for mobile phones is between one
and two years, and is driven by new features and fashion.

Assembly programming has no place in this world. Assembly code has limited
support for data types and generally no support for data structures. When assembly code is
used, this lack of abstraction becomes a design restriction that impacts not only the
interface to the assembly code but often the application as a whole.

Assembly programs are difficult to maintain and make a company dependent on a

few specialists. By definition, assembly programs are non portable. Legacy code makes it
extremely expensive to switch to a new technology. These dependencies make a company
vulnerable to employee and supplier chain changes.

Today, most embedded processors are offered with C compilers. Despite this,
programming DSPs is still done in assembly for the signal processing parts or, at best, by
using assembly-written libraries supplied by manufacturers. The key reason for this is that
although the architecture is well matched to the requirements of the signal-processing
application, there is no way to express the algorithms efficiently and in a natural way in
Standard C. Saturated arithmetic.

For example, is required in many algorithms and is supplied as a primitive in many

DSPs. However, there is no such primitive in Standard C. To express saturated arithmetic
in C requires comparisons, conditional statements, and correcting assignments. Instead of
using a primitive, the operation is spread over a number of statements that are difficult to
recognize as a single primitive by a compiler.

DESIGN WINDOW OF AVRSTUDIO4

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Fig 9.1 Design Window of AVRSTUDIO4

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