Kevin Shah

(480) 326-5047 | linkedin.com/in/kvshah95 | 1275 E University DR, Unit 413, Tempe, AZ 85281 | kvshah95@gmail.com

EDUCATION
Master of Science - Computer Engineering (Electrical Engineering) Current GPA 3.87/4.0 Expected December 2018
Arizona State University, Tempe, AZ.
Courses: Constructionist Approach to Microprocessor Design, Hardware acceleration and FPGA Computing, VLSI Design, Digital
Systems and Circuits, Embedded Operating system internals
Bachelor of Technology, Information and Communication Technology Cumulative GPA 3.56/4.0 May 2017
Ahmedabad University, Ahmedabad, India | ECE Topper of the Batch 2017
Courses: Multiple VLSI Design Courses, Embedded Systems Design, Computer Architecture and Organisation, Analog and Digital
Communication, Digital Signal Processing, Object Oriented Programing, Operating Systems, Internet of Things, Machine Learning.
TECHNICAL SKILLS
Hardware Descriptive and Verification Languages: SystemVerilog, Verilog, UVM, SystemC.
EDA tools: Cadence v6 (Synopsys 32nm PDK, Hercules), StarRRC, Encounter (Automatic Place and Route), Primetime.
Scripting Languages: Shell, Bash, Python, Perl, tcl.
Architectures and Operating Systems: RISC-V, MIPS, Unix, gem5, llvm (Beginner), Cuda, ARM Cortex-A15, Arduino, Raspberry Pi
Languages/ Simulators: C, C++, Java, Assembly, LabVIEW, MATLAB, Genesis 2, Embedded C, HSPICE, Altera ModelSim.
PROFESSIONAL EXPERIENCE
Design Verification Intern (WiFi SoC DV Team) May 2018 - Present
Qualcomm, San Jose, CA
• Developed Retention flops UVM Verification IP from scratch | Intensive use of IPC and fine-grained process control.
• IP implicitly checks for different power domains by loading and retaining values from an associative array.
• Designed such that it can force/release value to explicitly check the flops | debugging using Verdi fsdb.
• Python scripting for generating the flop list after UPF simulation on the fly and the agent can be attached to any project.
• Designed Assertions and constraint random UVM tests for RF ADC/DAC modules (cleared 2 bugs).
RTL Design Intern (DCTD Team) Jan 2017 - May 2017
Space Application Center, Indian Space Research Organization (ISRO), Ahmedabad, GJ
• Designed MSS satellite modem for various modulation scheme including CDMA, multi-user in MATLAB and systemverilog.
• Realized Costas loop, Early late gate synchronizer, FIR low pass filters and NCO and verified with Digital Oscilloscope.
• Verified the design with SystemVerilog and implemented on Cyclone 5 SoC FPGA (14-bit ADC for signal generation).
ACADEMIC PROJECTS
64-bit RISC-V Microarchitecture Design Implementation (with Vector Extension) Fall 2017 - Present
• Designed SystemVerilog modules for ALU, Bidding Arbiter, vector add, Booth8 multiplier and essentials on genesis2
• 1.2 IPC multiple issue Pipelined RISC-V CPU implemented from RTL to GDS (7 nm PDK) after constrained-random tests
• extensive Perl scripting used for automation for flexible parameterized design and functional coverage verification
• Complete verification with data dependencies through assembler design and generating golden reference for memories
RTL to GDS II of Convolution neural network in Cadence Encounter (ASAP7 7nm PDK) Spring 2018
• Design and verification of CNN max-pooling engine using SystemVerilog, synthesized netlist using DC compiler.
• Automatic Place and Route using Cadence Encounter and Primetime Synopsys tool as a gate-level static timing analyzer.
• Post Synthesis and Post APR timing Verification done using Primetime.
Hardware Accelerator Design for Convolutional Neural Network (CNN) Spring 2018
• Vivado HLS tool used to define 10 weighted layers of CNN and trained to recognize handwritten digits
• Zynq SoC used for implementation as DMA controller required with 4 channels controlled by AXI-Lite
• loop unrolling and interleaving for increasing throughput (32.6%) and reducing energy (23.9%)
VLSI Subsystems Design and Characterization Fall 2017
• Verilog and physical design of different adders/multipliers (Baugh wooly/carry-skip etc), scan chain/SRAM and MIPS uP
• Built by creating a custom library and characterized in terms of power and propagation delay for probabilistic model
EXTRACURRICULAR ACTIVITIES
● Graduate/Teaching Assistant for courses - HDL/VLSI/Computer Organization/Digital Design/Mechatronics
● Technical Committee Member and VLSI-SIG Head, IEEE Student Branch of Ahmedabad University
● Certification course on Machine Learning (Stanford University), Computer Architecture (Princeton University)