Testing (selected from Chapters
4, 5, 7, and 10)
■ Fault models.
■ Testing of combinational circuits.
■ Testing of sequential circuits.
Revised by SG: January 18, 2004
Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
Testing and faults
■ Fault model:
– possible locations of faults;
– I/O behavior produced by the fault.
■ Good news: if we have a fault model, we
can test the network for every possible
instantiation of that type of fault.
■ Bad news: it is difficult to enumerate all
types of manufacturing faults.
Revised by SG: January 18, 2004
Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
Manufacturing testing
■ Errors are introduced during manufacturing.
■ Testing verifies that chip corresponds to
design.
■ Varieties of testing:
– functional testing;
– performance testing (binning chips by speed).
■ Testing also weeds out infant mortality.
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Stuck-at-0/1 faults
■ Stuck-at-0/1: logic gate output is always
stuck at 0 or 1, independent of input values.
■ Correspondence to manufacturing defects
depends on logic family.
■ Experiments show that 100% stuck-at-0/1
fault coverage corresponds to high overall
fault coverage.
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 Testing procedure Stuck-at faults in gates

■ Testing procedure: a b OK SA0 SA1 a b OK SA0 SA1

– set gate inputs; 0 0 1 0 1 0 0 1 0 1
– observe gate output; 0 1 1 0 1 0 1 0 0 1
– compare fault-free and observed gate output. 1 0 1 0 1 1 0 0 0 1
■ Test vector: set of gate inputs applied to a 1 1 0 0 1 1 1 0 0 1
system.
NAND NOR

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Testing single gates Testing combinational networks

■ Three ways to test NAND for stuck-at-0, ■ 100% coverage: test every gate for
only one way to test it for stuck-at-1. – stuck-at-0;
■ Three ways to test NOR for stuck-at-1, only – stuck-at-1.
one way to test it for stuck-at-0. ■ Assume that there is only one faulty gate
per network.
■ Most networks require more than one test
vector to test all gates.

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 Multiple test example
Revised by SG: January 18, 2004
Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
Combinational network testing
Two parts to testing:
– controlling the inputs of (possibly interior)
gates;
– observing the outputs of (possibly interior)
gates.
Revised by SG: January 18, 2004
Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
Example
■ Can test both NANDs for stuck-at-0
simultaneously (abc = 000).
■ Cannot test both NANDs for stuck-at-1
simultaneously due to inverter. Must use
two vectors.
■ Each extra vector means longer testing time,
longer tester occupation, higher costs.
■ Must also test inverter.
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Test generation (Chapter 10)
■ Automatic test pattern generation (ATPG)
generates a set of test vectors for a Boolean
network (combinational ATPG) or
sequential machine (sequential ATPG).
■ D notation allows to quickly denote fault:
– D value on a node means that the signal is 0 in
good and 1 in faulty circuit at that point.
– D’ value is the opposite: 1 in good, 0 in faulty.
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 PODEM (path-oriented
decision making) algorithm Fault propagation example
■ Goal: propagate D (or D’) value to primary
outputs.
■ PODEM performs combinational test start step 1
generation. Uses implicit enumeration.
■ Uses five values: 0, 1, D, D’, and X. Start
all values at X.
■ In worst case, must examine all possible
inputs, but can be implemented to run
quickly.
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Fault propagation example,

cont’d Combinational testing example

step 2 step 3

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 Testing procedure Testing procedure, cont’d
■ Goal: test gate D for stuck-at-0 fault. ■ Observe the fault at a primary output:
■ First step: justify 0 values on gate inputs. – o1 gives different values if D is true/faulty.
■ Work backward from gate to primary
■ Work forward and backward:
inputs: – F’s other input must be 0 to detect true/fault.
– Justify 0 at E’s output.
– w1 = 0 (A output = 0);
– Final result: i5 = 1; i6 = i7 = 0; i8 = don’t care.
– i1 = i2 = 1.
■ In general, may have to propagate fault
■ Similarly: through multiple levels of logic to primary
– i3 = i4 = 1. outputs.
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Fault masking Redundancy example

Redundant logic can mask faults: ■ Testing NOR for SA0 requires setting both
inputs to 0.
■ Network topology ensures that one NOR
a SA1
SA0
input will always be 1.
b ■ Function reduces to 0:
– f = ((ab)’ + b)’ = (a’ + b’ + b)’ = 0.

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 Redundancies and testing Stuck-at-open/closed model

■ Redundant logic cannot be controlled. ■ Models transistors always on/off.

■ Observations requiring control of redundant
logic may not be possible.
■ Redundant logic should be minimized to
eliminate redundancy. Redundancies can
introduce delay faults and other problems.

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Stuck-open behavior Fault models in practice

■ If t1 is stuck-open (switch cannot be closed), ■ In spite of the existence of many fault

there can be no path from VDD to output models, the only fault model that is used in
capacitance. So, stuck-open is equivalent to practice is the stuck-at model due to its
stuck-at-0 in this case. simplicity.
■ If t2 is stuck-open, the output can be ■ Many test vectors that are developed for the
discharged when a=1, but not when b=1. stuck-at model also detect other type of
defects.

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 Delay fault Sequential testing

■ Delay falls outside acceptable limits:
– gate delay fault assumes that all delays are
lumped into one gate;
– path delay fault models delay problems along
path through network.
■ Delay problems reduce yield:
– performance problems;
– functional problems in some types of circuits.
Revised by SG: January 18, 2004
Modern VLSI Design 3e: Testing (from Chapters 4, 5, 7 & 10)
■ Much harder than combinational testing—
can’t set memory element values directly.
■ Must apply sequences to put machine in
proper state for test, be able to observe
value of test.
■ Or, one must use design-for-testability
techniques: add a scan path.
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Scan flip-flop Scan chain

D D
D Q/scan_out Q/scan_out
0
1 Q/scan_out scan_in scan_in
scan_in D Q
■ Normal flip-flop scan_mode φ scan_mode φ
behavior when
scan_mode = 0.
scan_mode φ ■ Connect successive scan_outs to scan_ins.
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 Scan-based testing (1) Scan-based testing (2)

■ When all flip-flops have been incorporated Primary inputs

Primary outputs
in a scan chain, they become part of a shift ■ The response Combinational
register. can be shifted logic

■ In scan mode, any desired pattern can be

out and
shifted in. analyzed.
■ By disabling scan mode for one clock cycle
the combinational circuit response to the
pattern can be captured in the flip-flops. memory

chip scan_in chip scan_out

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Partial scan Boundary scan (Chapter 7)

■ Full scan is expensive—must roll out and ■ Boundary scan is a technique for testing
roll in state many times during a set of tests. chips on boards. Pads on chips are arranged
■ Partial scan selects some registers for into a scan chain that can be used to observe
scanability. and control pins of all chips.
■ Requires analysis to choose which registers ■ Requires some control circuitry on pads
are best for scan. along with an on-chip controller and
boundary-scan-mode control pins.

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