Verilog Behavioral Program for Counters

UP COUNTER (4 BIT):

module upcount(clk,clr,q);
input clk,clr;
output [3:0]q;
reg [3:0]tmp;
always@(posedge clk or posedge clr)
begin
if(clr)
tmp<=4'b0000;
else
tmp<=tmp+1'b1;
end
assign q=tmp;
endmodule
DOWN COUNTER (4 BIT) :

module downcount(clk,clr,q);
input clk,clr;
output [3:0]q;
reg [3:0]tmp;
always@(posedge clk or posedge clr)
begin
if(clr)
tmp<=4'b1111;
else
tmp<=tmp-1'b1;
end
assign q=tmp;
end module

4 BIT COUNTER:

module fourbitcounter(clk,reset,out);
input clk,reset;
output reg [3:0] out;
always@(posedge reset or negedge clk)
begin
if(reset)
out<=0;
else
out<=out+1'b1;
end
end module

8 BIT COUNTER:

module eightbitcounter(clk,reset,q);
input clk,reset;
output [7:0] q;
wire [3:0] u;
wire [3:0] v;
fourbitcounter f0(clk,reset,u);
fourbitcounter f1(u[3],reset,v);
assign q[3:0]=u;
assign q[7:4]=v;
end module
16 BIT COUNTER

module sixteenbitcounter(clk,reset,a);
input clk,reset;
output [15:0] a;
wire [7:0] s;
wire [7:0] t;
eightbitcounter e0(clk,reset,s);
eightbitcounter e1(s[7],reset,t);
assign a[7:0]=s;
assign a[15:8]=t;
end module
32 BIT COUNTER:

module thirtytwobitccounter(clk,reset,d);
input clk,reset;
output [31:0] d;
wire [15:0] e;
wire [15:0] f;
sixteenbitcounter s0(clk,reset,e);
sixteenbitcounter s1(e[15],reset,f);
assign d[15:0]=e;
assign d[31:16]=f;
endmodule
64 BIT COUNTER:

module sixtyfourbitcounter(clk,reset,g);
input clk,reset;
output [63:0] g;
wire [31:0] h;
wire [31:0] i;
thirtytwobitccounter t0(clk,reset,h);
thirtytwobitccounter t1(h[31],reset,i);
assign g[31:0]=h;
assign g[63:32]=i;
endmodule
128 BIT COUNTER:

module counter_128bit(clk,reset,z);
input clk,reset;
output [127:0] z;
wire [63:0] x;
wire [63:0] y;
sixtyfourbitcounter s0(clk,reset,x);
sixtyfourbitcounter s1(x[63],reset,y);
assign z[63:0]=x;
assign z[127:64]=y;
endmodule

Verilog Behavioral Program for Flip Flops

SR FLIP FLOP :

module srflipflop(clk,S,R,Qnew,Qprev);
input clk,S,R;
output reg Qnew,Qprev=0;
always@(posedge clk)
begin
if(~S&~R)
Qnew<=Qprev;
else if(S&~R)
Qnew<=1;
else if(~S&R)
Qnew<=0;
end
endmodule

D FLIP FLOP :

module dflipflop(D,clk,clr,Q);
input D,clk,clr;
output reg Q=0;
always@(posedge clk or posedge clr)
begin
if(clr)
Q<=0;
else
Q<=D;
end
end module

JK FLIP FLOP :

module jkflipflop(clk,J,K,Q);
input clk,J,K;
output reg Q=0;
always@(negedge clk)
begin
if(J&(~K))
Q<=1;
else if((~J)&K)
Q<=0;
else if (J&K)
Q<=~Q;
 end
end module
T FLIP FLOP :

module tflipflop(clk,T,Q);
input clk,T;
output reg Q=0;
always@(negedge clk)
begin
if(T)
Q<=~Q;
end
end module
Verilog Behavioral Program for Magnitude Comparator
MAGNITUDE COMPARATOR (4 BIT) :

module comp(a,b,equal,greater,lower);
output equal;
reg equal;
output greater;
reg greater;
output reg lower;
input [3:0] a,b;
wire [3:0]a;
always@(a or b)
begin
if(a<b)
begin
equal=0;
lower=1;
greater=0;
end
else if(a==b)
begin
equal=1;
lower=0;
greater=0;
end else
begin
equal=0;
lower=0;
greater=1;
end
end
end module

Verilog Behavioral Program for Data Converters

BINARY - TO - GRAY CONVERTER (4 BIT) :

module binarytogray(a,b);
input[3:0]a;
outputreg [3:0]b;
always@(a)
begin
b[3]<=a[3];
b[2]<=a[3]^a[2];
b[1]<=a[2]^a[1];
b[0]<=a[1]^a[0];
end
end module

GRAY TO BINARY CONVERTER (4 BIT) :

module graytobinary(g,b);
input [3:0] g;
output reg [3:0] b;
always@(g)
begin
b[3]<=g[3];
b[2]<=b[3]^g[2];
b[1]<=b[2]^g[1];
b[0]<=b[1]^g[0];
end
end module

Verilog Behavioral Program for Multiplexers

8X1 MULTIPLEXER :

module eight_to_onemux(s,p,q);
input[2:0]s;
input[7:0]p;
output q;
reg q;
always@(s or p)
begin
case(s)
3'b000:q=p[0];
3'b001:q=p[1];
3'b010:q=p[2];
3'b011:q=p[3];
3'b100:q=p[4];
3'b101:q=p[5];
3'b110:q=p[6];
3'b111:q=p[7];
endcase
end
endmodule

16X1 MULTIPLEXER :
module multiplexer(s,p,q);
input[3:0]s;
input[15:0]p;
output q;
reg q;
always@(s or p)
begin
case(s)
4'b0000:q=p[0];
4'b0001:q=p[1];
4'b0010:q=p[2];
4'b0011:q=p[3];
4'b0100:q=p[4];
4'b0101:q=p[5];
4'b0110:q=p[6];
4'b0111:q=p[7];
4'b1000:q=p[8];
4'b1001:q=p[9];
4'b1010:q=p[10];
4'b1011:q=p[11];
4'b1100:q=p[12];
4'b1101:q=p[13];
4'b1110:q=p[14];
4'b1111:q=p[15];
endcase
end
endmodule

Verilog Behavioral Program for Decoder

2 X 4 DECODER :

module decoder(a,en,y);
input [1:0] a;
input en;
output reg [3:0] y;
always@(a or en)
begin
if(!en)
y<=4'b0000;
else
case(a)
2'b00:y<=4'b0001;
2'b01:y<=4'b0010;
2'b10:y<=4'b0100;
2'b11:y<=4'b1000;
endcase
end
endmodule
Verilog Behavioral Program for Encoder (with and
without priority)
8 X 3 ENCODER WITHOUT PRIORITY:
module encwtoutprio(a,en,y);
input [7:0] a;
input en;
output reg [2:0] y;
always@(a or en)
begin
if(!en)
y<=1'b0;
else
case(a)
8'b00000001:y<=3'b000;
8'b00000010:y<=3'b001;
8'b00000100:y<=3'b010;
8'b00001000:y<=3'b011;
8'b00010000:y<=3'b100;
8'b00100000:y<=3'b101;
8'b01000000:y<=3'b110;
8'b10000000:y<=3'b111;
endcase
end
endmodule
8 X 3 PRIORITY ENCODER :
module priorityencoder(a,en,y);
input [7:0] a;
input en;
output reg [2:0] y;
always@(a or en)
begin
if(!en)
y<=1'b0;
else
casex(a)
8'b00000001:y<=3'b000;
8'b0000001x:y<=3'b001;
 8'b000001xx:y<=3'b010;
8'b00001xxx:y<=3'b011;
8'b0001xxxx:y<=3'b100;
8'b001xxxxx:y<=3'b101;
8'b01xxxxxx:y<=3'b110;
8'b1xxxxxxx:y<=3'b111;
Endcase
end
endmodule

Verilog behavioral program for Half Adder and Full Adder

HALF ADDER:
module halfadder(en,a,sum,carry);
input [1:0] a;
input en;
output reg sum,carry;
always@(en or a)
begin
if(!en)
begin
sum<=0;
carry<=0;
end
else
case(a)
2'b00:
begin
sum<=0;
carry<=0;
end
2'b01:
begin
sum<=1;
carry<=0;
end
2'b10:
begin
sum<=1;
carry<=0;
end
default:
begin
sum<=0;
carry<=1;
end
endcase
end
Endmodule
FULL ADDER:
module fulladder(a,b,cin,en,sum,cout);
input a,b,cin,en;
output reg sum,cout;
reg t1,t2,t3;
always@(a or b or cin or en)
begin
if(!en)
begin
sum<=0;
cout<=0;
end
 else
begin
sum<=(a^b)^cin;
t1<=a&b;
t2<=a&cin;
t3<=b&cin;
cout<=(t1|t2)|t3;
end
end
endmodule

Verilog Behavioral Programs for logic gates

implementation
AND GATE :

module andgate(a,b);
input [1:0] a;
output reg b;
always@(a)
begin
case(a)
2'b11:b=1'b1;
default:b=1'b0;
endcase
end
endmodule

OR GATE :

module orgate(a,b);
 input [1:0] a;
output reg b;
always@(a)
begin
case(a)
2'b00:b=1'b0;
default:b=1'b1;
endcase
end
endmodule

NOT GATE :

module notgate(a,b);
input a;
output reg b;
always@(a)
begin
case(a)
1'b0:b=1'b1;
default:b=1'b0;
endcase
end
endmodule

NAND GATE :

module nandgate(a,b);
input [1:0] a;
output reg b;
 always@(a)
begin
case(a)
2'b00:b=1'b1;
default:b=1'b0;
endcase
end
endmodule

NOR GATE :
module norgate(a,b);
input [1:0] a;
output reg b;
always@(a)
begin
case(a)
2'b00:b=1'b1;
default:b=1'b0;
endcase
end
endmodul

XOR GATE :
module xorgate(a,b);
input [1:0] a;
output reg b;
always@(a)
begin
case(a)
2'b00:b=1'b0;
2'b11:b=1'b0;
 default:b=1'b1;
endcase
end
endmodule

XNOR GATE :
module xnorgate(a,b);
input [1:0] a;
output reg b;
always@(a)
begin
case(a)
2'b00:b=1'b1;
2'b11:b=1'b1;
default:b=1'b0;
endcase
end
endmodule