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8/10-bit resolution.
ECE/CS 5780/6780: Embedded System Design 7 µs, 10-bit single conversion time.
Programmable sample time.
Scott R. Little External trigger control.
Lecture 23: Integrated ADC Configuration Conversion completion interrupt generation.
8 analog input channels via an analog input multiplexer.
Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
1-8 sequence lengths for conversion.
8.1.2.2 MCU Operating Modes Continuous conversion mode.
• Stop Mode
Entering stop mode causes all clocks to halt and thus the system is placed in a minimum power
standby mode. This aborts any conversion sequence in progress. During recovery from stop mode,
there must be a minimum delay for the stop recovery time, tSR, before initiating a new ATD
conversion sequence.
• Wait Mode
Scott R. Little (Lecture 23: ADC
Entering waitConfig) ECE/CS
mode the ATD conversion 5780/6780
either continues or aborts for low power depending on the 1 / 20 Scott R. Little (Lecture 23: ADC Config) ECE/CS 5780/6780 2 / 20
logical value of the AWAIT bit.
• Freeze Mode
In freeze mode the ATD10B8C will behave according to the logical values of the FRZ1 and FRZ0
bits. This is useful for debugging and emulation.
ADC 8.1.3
Block Diagram
Block Diagram External Input Pin Descriptions
Figure 8-1 is a block diagram of the ATD.
ATD10B8C
mode.11 1ATD
Power down ATD
halts
Interrupt
Normal the ADC when the MCU enters Wait mode.
will be requested whenever ASCIF = 1 is set.
ATD functionality
1 is one (FIFO mode)1the conversion counter is not reset
If this bit High
at thelevel
beginning or ending of a conversion
sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning
06 ATD
ATD Sequence Complete
Fast Flag Clear All Interrupt Flag — If ASCIE = 1 the ASCIF flag equals the SCF flag (see conversion sequence, the result register counter will wrap around when it reaches the end of the result register
ASCIE:
ASCIF
AFFC 0ATD
Section
0 ATD
0 No
disables
8.3.2.7,
flag clearing interrupts.
“ATDoperates
Status Register
normally0(read the 1
(ATDSTAT0)”), enables
status else ASCIF
register interrupts.
reads
ATDSTAT1 zero. Writes
before havethe
reading Interrupts
no effect.register to
result
file. The conversion counter value (CC2-0 in ATDSTAT0) can be used to determine where in the result register
clear theinterrupt
associateoccurred
CCF flag).
occur 11when ATD
ASCIF
sequence
Changes all ATDcomplete
is setpending
interrupt
conversion complete to flags1.
to a fast clear sequence. Any access to a result register will cause file, the current conversion result will be placed.
conversion
6–3 ConversionisSequence
put into Length —theThese next
bits controlresult
the number register insequence.
of conversions per order. The
Table 8-4 showsorder
S8C, S4C, all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Field Description
Table 8-5. ATD Behavior in Freeze Mode (Breakpoint)
wraps
S2C, around. Intended usage is with continuous conversion or
S1C Family.
FRZ1 FRZ0 Behavior in Freeze Mode
6–3 Conversion Sequence Length — These bits control the number of conversions per sequence. Table 8-4
triggered conversion.
S8C, S4C, all combinations. At reset,0 S4C is set 0to 1 (sequence length Continueis 4). This is to maintain software continuity t
conversion
FRIZ[1:0]: Determines how the ADC will respond in debug mode S2C, S1C Family. 0 1 Reserved
1 0 Finish current conversion, then freeze
when a breakpoint is encountered. 1 1 Freeze Immediately
R
SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0
W Table 8-7. Sample Time Select
Reset 0 0 0 0 0 1 0 1
SMP1 SMP0 Length of 2nd Phase of Sample Time
Figure 8-7. ATD Control Register 4 (ATDCTL4) Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
0 0 2 A/D conversion clock periods
Read: Anytime
SRES8: 0 is 10-bit resolution and 1 is 8-bit resolution. 0 1
Table 4 A/D
8-10. Available Result conversion
Data Formats clock periods
Write: Anytime 1 0 8 A/D conversion clock
Result Data periods
Formats
SMP[1:0]: Two bits select the length of the second phase of the SRES8
1
DJM
1
DSGN
Description and Bus Bit Mapping
16 A/D conversion clock periods
Table 8-6. ATDCTL4 Field Descriptions
sample time in units of ADC conversion cycles. A longer time 1
1
0
0
0
1
8-bit / left justified / unsigned — bits 8–15
8-bit / left justified / signed — bits 8–15
Field Description 1 1 X 8-bit / right justified / unsigned — bits 0–7
improves the accuracy of the conversion. 0 0 0 10-bit / left justified / unsigned — bits 6–15
7 A/D Resolution Select — This bit selects the resolution of A/D conversion results as either 8 or 10 bits. The A/D 0 0 1 10-bit / left justified / signed — bits 6–15
SRES8PRS[4:0]:
converter hasFive bitsofselect
an accuracy the frequency
10 bits; however, if low resolution isof thetheADC
required, conversion
conversion can be speeded up 0 1 X 10-bit / right justified / unsigned — bits 0–9
by selecting 8-bit resolution. Eclk
clock frequency
0 10-bit resolution using the equation: ADCclock = PRS+1 * 0.5. 234 MC9S12C-Family
Table 8-11. Left Justified, Signed,/ and
MC9S12GC-Family
Unsigned ATD Output Codes. Freescale Semiconductor
1 8-bit resolution
6–5
Maximum conversion frequency is 2 MHz and minimum
Sample Time Select — These two bits select the length of the second phase of the sample time in units of ATD
Input Signal Signed
Rev 01.23
Unsigned Signed Unsigned
VRL = 0 Volts 8-Bit 8-Bit 10-Bit 10-Bit
conversion
SMP[1:0] frequency
conversion clock isthe500
cycles. Note that kHz. clock period is itself a function of the prescaler value (bits
ATD conversion VRH = 5.12 Volts Codes Codes Codes Codes
PRS4-0). The sample time consists of two phases. The first phase is two ATD conversion clock cycles long and
5.120 Volts 7F FF 7FC0 FFC0
transfers
Scott R. Little (Lecture 23:the
ADCsample quickly (via the buffer
Config) ECE/CS amplifier)
5780/6780onto the A/D machine’s storage node. The second 9phase
/ 20 Scott R. Little (Lecture 23: ADC Config) ECE/CS 5780/6780 10 / 20
5.100 7F FF 7F00 FF00
attaches the external analog signal directly to the storage node for final charging and high accuracy. Table 8-7 5.080 7E FE 7E00 FE00
lists the lengths available for the second sample phase.
Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 2.580 01 81 0100 8100
4–0 ATD Clock Prescaler — These 5 bits are the binary value prescaler value PRS. The ATD conversion clock 2.560 00 80 0000 8000
PRS[4:0} frequency is calculated as follows: 2.540 FF 7F FF00 7F00
8.3.2.6 ATD Control Register 5 (ATDCTL5)
[ BusClock ]
ATDCTL5 Part 1 ATDclock = ------------------------------ × 0.5
This register selects the type of [conversion
PRS + 1 ] sequence and the analog input channels sampled. Writes to this
register will abort current conversion sequence and start a new conversion sequence.
ATDCTL5 Part 2 0.020
0.000
81
80
01
00
8100
8000
0100
0000
Note: The maximum ATD conversion clock frequency is half the Bus Clock. The default (after reset) prescaler
value is 5 which results in a default ATD conversion clock frequency that is Bus Clock divided by 12.
Module Base + 0x0005 Table 8-12. Analog Input Channel Select Coding
Table 8-8 illustrates the divide-by operation and the appropriate range of the Bus Clock.
7 6 5 4 3 2 1 0 CC CB CA Analog Input Channel
R 0 0 0 0 AN0
DJM DSGN SCAN
Table 8-7.MULT
Sample Time Select CC CB CA
W 0 0 1 AN1
Reset 0 SMP1 0 SMP0
0 0 Length of0 2nd Phase0of Sample Time
0 0 0 1 0 AN2
0 1 1 AN3
0= Unimplemented or0Reserved 2 A/D conversion clock periods
1 0 0 AN4
0 Figure 8-8.
1 ATD Control Register
4 A/D5conversion
(ATDCTL5)clock periods
1 0 1 AN5
7 6 5 4 3 2 1 0
Write: Anytime Module Base + 0x0009 This read-only register contains the Conversion Complete Flags.
7 6 5 4 3 2 1 0
Module Base + 0x000B
R U UTable 8-14.
U ATDTEST1
U FieldUDescriptions
U U
SC 7 6 5 4 3 2 1 0
W
Field Description R CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
Reset 0 0 0 0 0 0 0 0
W
0 Special Channel Conversion Bitor—
= Unimplemented If this bit is set, then special channel conversion can be selected using CC,
Reserved
Reset 0 0 0 0 0 0 0 0
SC CB, and CA of ATDCTL5. Table 8-15 lists the coding.
238 FigureMC9S12C-Family
8-11. ATD Test/Register 1 (ATDTEST1)
MC9S12GC-Family Freescale Semiconductor
0 Special channel conversions disabled = Unimplemented or Reserved
Rev 01.23
SC: Setting this bit allows a special conversion channel to be
1 Special
Read: channel
Anytime, conversions
returns enabled
unpredictable values for Bit 7 and Bit 6 Figure 8-12. ATD Status Register 1 (ATDSTAT1)
Note: Always write remaining bits of ATDTEST1 (Bit7 to Bit1) zero when writing SC bit. Not doing so might result
Write: Anytime
used. The special channel is selected via the CA, CB, and CC
in unpredictable ATD behavior. Read: Anytime
Table 8-14. ATDTEST1 Field Descriptions
bits. CCF[7:0]: A conversion complete flag is set at the end of each
Write: Anytime, no effect
Field Description Table 8-16. ATDSTAT1 Field Descriptions
0
Table 8-15. Special Channel Select Coding
Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using CC,
conversion in a conversion sequence. For example, CCF0 is set
Field Description
SC
SC
CB, and CA of ATDCTL5. Table 8-15 lists the coding.
0 Special CC CB
channel conversions CA
disabled Analog Input Channel
after
7–0
the first conversion when the data in ATDDR0 is available,
Conversion Complete Flag x (x = 7, 6, 5, 4, 3, 2, 1, 0) — A conversion complete flag is set at the end of each
1 Special channel conversions enabled
1Note: Always0 write remaining
X bits ofXATDTEST1 (Bit7 to Bit1) zero when Reserved
writing SC bit. Not doing so might result etc. AalsoCCF#
CCF[7:0] conversion in a flag is cleared when
conversion sequence. The flags are a new
associated conversion
with the conversion position in a sequence
sequence (and
the result register number). Therefore, CCF0 is set when the first conversion in a sequence is complete and
is
in unpredictable ATD behavior.
1 1 0 0 VRH started, if AFFC = 0 (ATDCTL2) and a read of ATDSTAT1
the result is available in result register ATDDR0; CCF1 is set when the second conversion in a sequence is
complete and the result is available in ATDDR1, and so forth. A flag CCFx (x = 7, 6, 5, 4, 3, 2, 1, 0) is cleared
is
when one of the following occurs:
1 1 0
Table 8-15.1Special Channel Select Coding
VRL followed byWriteatoread
A) ATDCTL5of (a newresult
conversionregister ATDDR#, or AFFC = 1 and
sequence is started)
1 1 1 0CA (V +V )/2 B) If AFFC = 0 and read of ATDSTAT1 followed by read of result register ATDDRx
SC CC CB RH
Analog Input RL
Channel a read ofC)aIf AFFC result= 1 andregister ATDDR#.
read of result register ATDDRx
1 11 0 1 X 1X Reserved
Reserved 0 Conversion number x not completed
1 Conversion number x has completed, result ready in ATDDRx
1 1 0 0 VRH
1 Config)
Scott R. Little (Lecture 23: ADC 1 0 1
ECE/CS 5780/6780 VRL 15 / 20 Scott R. Little (Lecture 23: ADC Config) ECE/CS 5780/6780 16 / 20
1 1 1 0 (VRH+VRL) / 2
1 1 1 1 Reserved
ATDDIEN ATDDR#H/ATDDR#L Left Justified
Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
Module Base + 0x0010 = ATDDR0H, 0x0012 = ATDDR1H, 0x0014 = ATDDR2H, 0x0016 = ATDDR3H
8.3.2.11 ATD Input Enable Register (ATDDIEN) 0x0018 = ATDDR4H, 0x001A = ATDDR5H, 0x001C = ATDDR6H, 0x001E = ATDDR7H
7 6 5 4 3 2 1 0
Module Base + 0x000D
R BIT 9 MSB BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 10-bit data
7 6 5 4 3 2 1 0
W BIT 7 MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 8-bit data
R
IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 Reset 0 0 0 0 0 0 0 0
W
Figure 8-15. Left Justified, ATD Conversion Result Register, High Byte (ATDDRxH)
Reset 0 0 0 0 0 0 0 0
Figure 8-13. ATD Input Enable Register (ATDDIEN) Module Base + 0x0011 = ATDDR0L, 0x0013 = ATDDR1L, 0x0015 = ATDDR2L, 0x0017 = ATDDR3L
0x0019 = ATDDR4L, 0x001B = ATDDR5L, 0x001D = ATDDR6L, 0x001F = ATDDR7L
Read:
Chapter Anytime
8 Analog-to-Digital Converter (ATD10B8C) Block Description
7 6 5 4 3 2 1 0
8.3.2.13.2 Right Justified Result Data R BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 10-bit data
Module Base + 0x0010 = ATDDR0H, 0x0012 = ATDDR1H, 0x0014 = ATDDR2H, 0x0016 = ATDDR3H W BIT 7 MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 8-bit data
Reset 0 0 0 0 0 0 0 0
Configure the number of conversions via ATDCTL3.
Figure 8-17. Right Justified, ATD Conversion Result Register, High Byte (ATDDRxH) Configure resolution, sampling time, and ADC clock speed via
Module Base + 0x0011 = ATDDR0L, 0x0013 = ATDDR1L, 0x0015 = ATDDR2L, 0x0017 = ATDDR3L ATDCTL4.
0x0019 = ATDDR4L, 0x001B = ATDDR5L, 0x001D = ATDDR6L, 0x001F = ATDDR7L 244 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
7 6 5 4 3 2 1 0
Configure the starting channel, single/multiple channel,
Rev 01.23
Reset 0 0 0 0 0 0 0 0
ATDCTL5. Writing to ATDCTL5 should happen last as it starts
Figure 8-18. Right Justified, ATD Conversion Result Register, Low Byte (ATDDRxL) the conversion.
Scott R. Little (Lecture 23: ADC Config) ECE/CS 5780/6780 19 / 20 Scott R. Little (Lecture 23: ADC Config) ECE/CS 5780/6780 20 / 20
244 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.23