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ADC Description

8/10-bit resolution.
ECE/CS 5780/6780: Embedded System Design 7 µs, 10-bit single conversion time.
Programmable sample time.
Scott R. Little External trigger control.
Lecture 23: Integrated ADC Configuration Conversion completion interrupt generation.
8 analog input channels via an analog input multiplexer.
Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
1-8 sequence lengths for conversion.
8.1.2.2 MCU Operating Modes Continuous conversion mode.
• Stop Mode
Entering stop mode causes all clocks to halt and thus the system is placed in a minimum power
standby mode. This aborts any conversion sequence in progress. During recovery from stop mode,
there must be a minimum delay for the stop recovery time, tSR, before initiating a new ATD
conversion sequence.
• Wait Mode
Scott R. Little (Lecture 23: ADC
Entering waitConfig) ECE/CS
mode the ATD conversion 5780/6780
either continues or aborts for low power depending on the 1 / 20 Scott R. Little (Lecture 23: ADC Config) ECE/CS 5780/6780 2 / 20
logical value of the AWAIT bit.
• Freeze Mode
In freeze mode the ATD10B8C will behave according to the logical values of the FRZ1 and FRZ0
bits. This is useful for debugging and emulation.

ADC 8.1.3
Block Diagram
Block Diagram External Input Pin Descriptions
Figure 8-1 is a block diagram of the ATD.

ATD10B8C

BUS CLOCK CLOCK ATD CLOCK


PRESCALER

CONVERSION MODE AND TIMING CONTROL


COMPLETE INTERRUPT
PAD0-PAD6: Serve as the analog input for channel #. They
RESULTS
VRH
VRL
SUCCESSIVE
APPROXIMATION
ATD 0
ATD 1
ATD 2
can also be configured for digital GPIO.
REGISTER (SAR) ATD 3
VDDA ATD 4
VSSA
AND DAC ATD 5
ATD 6
ATD 7
PAD7: Serves as the analog input for channel 7. It can also be
AN7 / PAD7
AN6 / PAD6 configured to provide an external trigger for the ADC or be used
+
AN5 / PAD5
AN4 / PAD4
1
SAMPLE & HOLD as digital GPIO.
1 –
AN3 / PAD3
AN2 / PAD2 COMPARATOR VRH , VRL : The high and low reference voltages for the ADC.
AN1 / PAD1
AN0 / PAD0
ANALOG ATD INPUT ENABLE REGISTER
VDDA , VSSA : Power supplies for the ADC analog circuits.
MUX

PORT AD DATA REGISTER

Figure 8-1. ATD10B8C Block Diagram

MC9S12C Family Reference Manual pg. 224


Scott R. Little (Lecture 23: ADC Config) ECE/CS 5780/6780 3 / 20 Scott R. Little (Lecture 23: ADC Config) ECE/CS 5780/6780 4 / 20
224 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.23
Field Description
Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description

8.3.2.3 ATD Control Register 2 (ATDCTL2)


1 ATD Sequence Complete Interrupt Enable
ASCIE 0 ATD Sequence Complete interrupt requests are disabled.
ATDCTL2 Part
This register controls 1 interrupt, and external trigger. Writes to this register will abort current
power down,
conversion sequence but will not start a new sequence.
ATDCTL2 Part 2
1 ATD Interrupt will be requested whenever ASCIF = 1 is set.
Module Base + 0x0002
0 ATD Sequence Complete Interrupt Flag — If ASCIE = 1 the ASCIF flag equals the SCF flag (see
7 6 5 4 3 2 1 0
ASCIF Section 8.3.2.7, “ATD Status Register 0 (ATDSTAT0)”), else ASCIF reads zero. Writes have no effect.
R ASCIF 0 No ATD interrupt occurred
W
ADPU AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE
1 ATD sequence complete interrupt pending
Reset 0 0 0 0 0 0 0 0
ETRIGE: 1 enables an external trigger to start ADC conversion.
= Unimplemented or Reserved Channel 7 is not available in external trigger mode.
Figure 8-5. ATD Control Register 2 (ATDCTL2) Table 8-2. External Trigger Configurations
ADPU: 1 enables ADC and 0 disables ADC.
Read: Anytime
ETRIGLE ETRIGP
Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
External Trigger Sensitivity
Write: Anytime
AFFC: 1 enables fast clear which results in any access to a result
Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description Table 8-3. ATDCTL3 Field Descriptions (continued)
Table 8-1. ATDCTL2 Field Descriptions 0 0 Falling edge
register causingTable the8-1.associated
ATDCTL2 Field Descriptions
CCF flag to clear. 0 is normal
Description (continued) Field Description
Field
0 1 Rising edge
operation.
7
Field ATD Power Down — This bit provides on/off control over the ATD10B8C block allowing reduced MCU power
Description 2 Result Register FIFO Mode — If this bit is zero (non-FIFO mode), the A/D conversion results map into the result
ADPU consumption. Because analog electronic is turned off when powered down, the ATD requires a recovery time FIFO 1
registers 0
based on the conversion Low
sequence; the result of the first level appears in the first result register,
conversion
AWAI:
1
ASCIE
ATD0 Sequence
period
00 ATD
enables
after ADPU
Sequence
Completethe
bit is ADC
Interrupt
enabled. Enable to run even when the MCU is in Wait
Complete interrupt requests are disabled.
the second result in the second result register, and so on.

mode.11 1ATD
Power down ATD
halts
Interrupt
Normal the ADC when the MCU enters Wait mode.
will be requested whenever ASCIF = 1 is set.
ATD functionality
1 is one (FIFO mode)1the conversion counter is not reset
If this bit High
at thelevel
beginning or ending of a conversion
sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning
06 ATD
ATD Sequence Complete
Fast Flag Clear All Interrupt Flag — If ASCIE = 1 the ASCIF flag equals the SCF flag (see conversion sequence, the result register counter will wrap around when it reaches the end of the result register
ASCIE:
ASCIF
AFFC 0ATD
Section
0 ATD
0 No
disables
8.3.2.7,
flag clearing interrupts.
“ATDoperates
Status Register
normally0(read the 1
(ATDSTAT0)”), enables
status else ASCIF
register interrupts.
reads
ATDSTAT1 zero. Writes
before havethe
reading Interrupts
no effect.register to
result
file. The conversion counter value (CC2-0 in ATDSTAT0) can be used to determine where in the result register
clear theinterrupt
associateoccurred
CCF flag).
occur 11when ATD
ASCIF
sequence
Changes all ATDcomplete
is setpending
interrupt
conversion complete to flags1.
to a fast clear sequence. Any access to a result register will cause file, the current conversion result will be placed.

8.3.2.4 ATD Control Register 3 (ATDCTL3)


the associate CCF flag to clear automatically. Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the
ASCIF:
5 ATDIf ASCIE
Power Down in Wait =Mode1 —the WhenASCIF flagthisequals
entering Wait Mode
Table 8-2. External Trigger Configurations
thecontrol
bit provides on/off SCF over the ATD10B8C conversion counter even if FIFO=1. So the first result of a new conversion sequence, started by writing to
ATDCTL5, will always be place in the first result register (ATDDDR0). Intended usage of FIFO mode is continuos
AWAI block allowing reduced MCU power. Because analog electronic is turned off when powered down, the ATD
(ATDSTAT0[7])requires a recovery flag ETRIGP
time
ETRIGLE
period
0 ATD continues to run in Wait mode
else ASCIF
after exit from Wait mode.
External=Trigger
0. Sensitivity This register controls theWhich conversion
conversion (SCAN=1) or triggered
sequence conversion
length, (ETRIG=1).
FIFO for results registers and behavior in F
1 23:
Halt ADC
conversion 0 power down
and 0 ATD during Wait mode Falling edge result registers hold valid data can be tracked using the conversion complete flags. Fast flag clear mode
Scott R. Little (Lecture Config)
After exiting Wait0mode with an interrupt
1
ECE/CS 5780/6780
conversion will resume. But
Rising edge due to the recovery time the result of Mode.
this Writes
5 / 20
to this register
Scott R. Little (Lecture
may or maywill notabort
23: ADC useful current
beConfig) in a particularconversion
ECE/CS to tracksequence
5780/6780
application valid data. but will not start a6 /new 20
seque
conversion should be ignored. 0 Conversion results are placed in the corresponding result register up to the selected sequence length.
1 0 Low level 1 Conversion results are placed in consecutive result registers (wrap around at end).
4 External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See
ETRIGLE 1
Table 8-2 for details. 1 High level
Module Base + 0x0003
1–0 Background Debug Freeze Enable — When debugging an application, it is useful in many cases to have the
3 External Trigger Polarity — This bit controls the polarity of the external trigger signal. See Table 8-2 for details. FRIZ[1:0] ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond
ETRIGP to a breakpoint as shown in Table 8-5. Leakage onto the storage node and comparator reference capacitors may
ATDCTL3
8.3.2.4 ATD Part
2 1 3 (ATDCTL3)
Control Register
ETRIGE
External Trigger Mode Enable — This bit enables the external trigger on ATD channel 7. The external trigger
allows to synchronize sample and ATD conversions processes with external events.
7
ATDCTL3 Part 2 6 5 4 3 2
compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period.
1

This register 0controls the conversion


Disable external trigger sequence length, FIFO for results registers and behavior in Freeze R 0
Mode. Writes1 to Enable external trigger
this register will abort current conversion sequence but will not start a new sequence. S8C S4C S2C
Table 8-4. Conversion Sequence Length Coding
S1C FIFO FRZ1 F
Note: The conversion results for the external trigger ATD channel 7 have no meaning while external trigger mode
is enabled.
W
Module Base + 0x0003
Number of Conversions per
S8C S4C S2C S1C
7 6 5 4 3 2 1 0 Reset 0 0 1 0 0 Sequence 0 0
R 0 0 0 0 0 8
S8C S4C S2C S1C FIFO FRZ1 FRZ0
W = Unimplemented
0
or0Reserved0 1 1
Reset 0 0 1 0 0 0 0 0 0 0 1 2 0
Freescale Semiconductor= Unimplemented or
MC9S12C-Family
Reserved / MC9S12GC-Family 231
Figure 8-6. ATD Control Register 3 (ATDCTL3)
0 0 1 1 3
Rev 01.23
Figure 8-6. ATD Control Register 3 (ATDCTL3) 0 1 0 0 4
Read: Anytime 0 1 0 1 5
Read: Anytime
0 1 1 0
6
S8C, S4C, S2C, S1C: Set the number of conversions/sequence.
Write: Anytime Write: Anytime 0 1 1 1 7
Table 8-3. ATDCTL3 Field Descriptions
FIFO:
Field
0 is normal operation. 1 enables
Description
FIFO mode where each 1
Table X
8-3. ATDCTL3
X X
Field Descriptions 8

conversion
6–3 ConversionisSequence
put into Length —theThese next
bits controlresult
the number register insequence.
of conversions per order. The
Table 8-4 showsorder
S8C, S4C, all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Field Description
Table 8-5. ATD Behavior in Freeze Mode (Breakpoint)
wraps
S2C, around. Intended usage is with continuous conversion or
S1C Family.
FRZ1 FRZ0 Behavior in Freeze Mode
6–3 Conversion Sequence Length — These bits control the number of conversions per sequence. Table 8-4
triggered conversion.
S8C, S4C, all combinations. At reset,0 S4C is set 0to 1 (sequence length Continueis 4). This is to maintain software continuity t
conversion

FRIZ[1:0]: Determines how the ADC will respond in debug mode S2C, S1C Family. 0 1 Reserved
1 0 Finish current conversion, then freeze
when a breakpoint is encountered. 1 1 Freeze Immediately

232 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor


Scott R. Little (Lecture 23: ADC Config) Rev 01.23
ECE/CS 5780/6780 7 / 20 Scott R. Little (Lecture 23: ADC Config) ECE/CS 5780/6780 8 / 20
PRS4-0). The sample time consists of two phases. The first phase is two ATD conversion clock cycles long and
transfers the sample quickly (via the buffer amplifier) onto the A/D machine’s storage node. The second phase
attaches the external analog signal directly to the storage node for final charging and high accuracy. Table 8-7
Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
lists the lengths available for the second sample phase.
8.3.2.5 ATD Control Register 4 (ATDCTL4) 4–0 ATD Clock Prescaler — These 5 bits are the binary value prescaler value PRS. The ATD conversion clock
ATDCTL4 Part 1
This register selects the conversion clock frequency, the length of the second phase of the sample time and
ATDCTL4
PRS[4:0} Part
frequency is calculated 2
as follows:
[ BusClock ]
the resolution of the A/D conversion (i.e.: 8-bits or 10-bits). Writes to this register will abort current ATDclock = ------------------------------ × 0.5
[ PRS + 1 ]
conversion sequence but will not start a new sequence.
Note: The maximum ATD conversion clock frequency is half the Bus Clock. The default (after reset) prescaler
Module Base + 0x0004 value is 5 which results in a default ATD conversion clock frequency that is Bus Clock divided by 12.
Table 8-8 illustrates the divide-by operation and the appropriate range of the Bus Clock.
7 6 5 4 3 2 1 0

R
SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0
W Table 8-7. Sample Time Select
Reset 0 0 0 0 0 1 0 1
SMP1 SMP0 Length of 2nd Phase of Sample Time
Figure 8-7. ATD Control Register 4 (ATDCTL4) Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
0 0 2 A/D conversion clock periods
Read: Anytime
SRES8: 0 is 10-bit resolution and 1 is 8-bit resolution. 0 1
Table 4 A/D
8-10. Available Result conversion
Data Formats clock periods
Write: Anytime 1 0 8 A/D conversion clock
Result Data periods
Formats
SMP[1:0]: Two bits select the length of the second phase of the SRES8
1
DJM
1
DSGN
Description and Bus Bit Mapping
16 A/D conversion clock periods
Table 8-6. ATDCTL4 Field Descriptions
sample time in units of ADC conversion cycles. A longer time 1
1
0
0
0
1
8-bit / left justified / unsigned — bits 8–15
8-bit / left justified / signed — bits 8–15
Field Description 1 1 X 8-bit / right justified / unsigned — bits 0–7
improves the accuracy of the conversion. 0 0 0 10-bit / left justified / unsigned — bits 6–15
7 A/D Resolution Select — This bit selects the resolution of A/D conversion results as either 8 or 10 bits. The A/D 0 0 1 10-bit / left justified / signed — bits 6–15
SRES8PRS[4:0]:
converter hasFive bitsofselect
an accuracy the frequency
10 bits; however, if low resolution isof thetheADC
required, conversion
conversion can be speeded up 0 1 X 10-bit / right justified / unsigned — bits 0–9
by selecting 8-bit resolution. Eclk
clock frequency
0 10-bit resolution using the equation: ADCclock = PRS+1 * 0.5. 234 MC9S12C-Family
Table 8-11. Left Justified, Signed,/ and
MC9S12GC-Family
Unsigned ATD Output Codes. Freescale Semiconductor
1 8-bit resolution
6–5
Maximum conversion frequency is 2 MHz and minimum
Sample Time Select — These two bits select the length of the second phase of the sample time in units of ATD
Input Signal Signed
Rev 01.23
Unsigned Signed Unsigned
VRL = 0 Volts 8-Bit 8-Bit 10-Bit 10-Bit
conversion
SMP[1:0] frequency
conversion clock isthe500
cycles. Note that kHz. clock period is itself a function of the prescaler value (bits
ATD conversion VRH = 5.12 Volts Codes Codes Codes Codes
PRS4-0). The sample time consists of two phases. The first phase is two ATD conversion clock cycles long and
5.120 Volts 7F FF 7FC0 FFC0
transfers
Scott R. Little (Lecture 23:the
ADCsample quickly (via the buffer
Config) ECE/CS amplifier)
5780/6780onto the A/D machine’s storage node. The second 9phase
/ 20 Scott R. Little (Lecture 23: ADC Config) ECE/CS 5780/6780 10 / 20
5.100 7F FF 7F00 FF00
attaches the external analog signal directly to the storage node for final charging and high accuracy. Table 8-7 5.080 7E FE 7E00 FE00
lists the lengths available for the second sample phase.
Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 2.580 01 81 0100 8100
4–0 ATD Clock Prescaler — These 5 bits are the binary value prescaler value PRS. The ATD conversion clock 2.560 00 80 0000 8000
PRS[4:0} frequency is calculated as follows: 2.540 FF 7F FF00 7F00
8.3.2.6 ATD Control Register 5 (ATDCTL5)
[ BusClock ]
ATDCTL5 Part 1 ATDclock = ------------------------------ × 0.5
This register selects the type of [conversion
PRS + 1 ] sequence and the analog input channels sampled. Writes to this
register will abort current conversion sequence and start a new conversion sequence.
ATDCTL5 Part 2 0.020
0.000
81
80
01
00
8100
8000
0100
0000
Note: The maximum ATD conversion clock frequency is half the Bus Clock. The default (after reset) prescaler
value is 5 which results in a default ATD conversion clock frequency that is Bus Clock divided by 12.
Module Base + 0x0005 Table 8-12. Analog Input Channel Select Coding
Table 8-8 illustrates the divide-by operation and the appropriate range of the Bus Clock.
7 6 5 4 3 2 1 0 CC CB CA Analog Input Channel
R 0 0 0 0 AN0
DJM DSGN SCAN
Table 8-7.MULT
Sample Time Select CC CB CA
W 0 0 1 AN1
Reset 0 SMP1 0 SMP0
0 0 Length of0 2nd Phase0of Sample Time
0 0 0 1 0 AN2
0 1 1 AN3
0= Unimplemented or0Reserved 2 A/D conversion clock periods
1 0 0 AN4
0 Figure 8-8.
1 ATD Control Register
4 A/D5conversion
(ATDCTL5)clock periods
1 0 1 AN5

DJM: 0 is 1left justified


Read: Anytime 0
data and 81A/Disconversionright clock periods
justified data. 1 1 0 AN6
1 1 16 A/D conversion clock periods 1 1 1 AN7
Write: Anytime
DSGN: 0 is unsigned data and 1 is signed data. Signed data is
Table 8-9. ATDCTL5 Field Descriptions
not
Field
available with right justification. Description MULT: When 0 the ADC samples only from the input specified
Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
SCAN:
7 0 is
Result single
Register conversion
Data Justification and justification
— This bit controls 1 is continuous
of conversion data in conversion.
the result registers.
by the channel selection code (CC,CB,CA). When 1 the ADC
DJM See Section 8.3.2.13, “ATD Conversion Result Registers (ATDDRHx/ATDDRLx)” for details.
234 0 Left justified data Table 8-10.
in the result Available Result
registers
MC9S12C-Family Data Formats
/ MC9S12GC-Family Freescale Semiconductor
1 Right justified data in the result registers
Rev 01.23
samples across channels. The number of channels sampled is set
6 Result Register Data Signed or Unsigned Representation — This bitResult selects between signed and unsigned
Data Formats
SRES8conversion data
DSGN DJM
representation in theDSGNresult registers. Signed data is represented as 2’s complement. Signed
Description and Bus Bit Mapping
by the S#C bits. The first channel examined is set by the
data is not available in right justification. See Section 8.3.2.13, “ATD Conversion Result Registers
1 (ATDDRHx/ATDDRLx)”0 for details. 0 8-bit / left justified / unsigned — bits 8–15 channel selection code. Subsequent channels selected are
1 0 Unsigned data0representation in the1 result registers 8-bit / left justified / signed — bits 8–15
1 Signed data representation in the result registers
1 1 X 8-bit / right justified / unsigned — bits 0–7 determined by incrementing the channel selection code.
Table 8-10 summarizes the result data formats available and how they are set up using the control bits.
0 0 0 10-bit / left justified / unsigned — bits 6–15
Table 8-11 illustrates
0 0 the difference between
1 the signed and unsigned,
10-bit left justified
/ left justified output codes
/ signed — bitsfor6–15
an input CC, Semiconductor
Freescale CB, CA: SelectsMC9S12C-Family
the analog channel to be sampled or 237
/ MC9S12GC-Family
signal range between 0 and 5.12 Volts. Rev 01.23
0 1 X 10-bit / right justified / unsigned — bits 0–9
5 Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed sampled first.
SCAN continuously or only once.
Scott R. Little (Lecture 23: ADC Config) ECE/CS 5780/6780 11 / 20 Scott R. Little (Lecture 23: ADC Config) ECE/CS 5780/6780 12 / 20
0 Single conversion sequence
1 Table 8-11.
Continuous Left Justified,
conversion sequences Signed,
(scan mode)and Unsigned ATD Output Codes.
4 Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the specified
Input Signal
MULT analog input channel Signed
for an entire conversionUnsigned Signed
sequence. The analog channel Unsigned
is selected by channel selection
V = 0 code
RL Volts(control bits CC/CB/CA
8-Bit located in ATDCTL5). When MULT is 1, the
8-Bit ATD sequence controller
10-Bit samples
10-Bit
Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description

8.3.2.7 ATD Status Register 0 (ATDSTAT0)


ATDSTAT0
This read-only registerPart
contains the1sequence complete flag, overrun flags for external trigger and FIFO
mode, and the conversion counter.
ATDSTAT0 Part 2
Module Base + 0x0006

7 6 5 4 3 2 1 0

R 0 0 CC2 CC1 CC0


SCF ETORF FIFOR
W

Reset 0 0 0 0 0 0 0 0 FIFOR: Indicates that a result register has been written to


= Unimplemented or Reserved before its associated conversion complete flag (CCF#) has been
Figure 8-9. ATD Status Register 0 (ATDSTAT0)
cleared. This is useful in FIFO mode to indicate that result
SCF: The flag is set when a conversion sequence completes. If
Read: Anytime
registers are out of sync with input channels. The flag is cleared
Write: Anytime (no effect
continuous on (CC2, CC1,isCC0))
conversion being performed the flag is set after
Table 8-13. ATDSTAT0 Field Descriptions
when a 1 is written to FIFOR or a new conversion sequence is
each conversion completes. The flag is cleared when a 1 is started.
Field Description
written
Chapter 8 Analog-to-Digital to SCF,
Converter a new
(ATD10B8C) Blockconversion
Description sequence is started, or if AFFC
7 Sequence Complete Flag — This flag is set upon completion of a conversion sequence. If conversion
CC[2:0]: Represent the binary value of the conversion counter
=SCF1 (ATDCTL2)
sequences are continuously performed (SCAN = 1), the flag is set after each one is completed. This flag is
and a result register is read.
8.3.2.9 ATD Test Register
A) Write “1” to SCF1 (ATDTEST1)
cleared when one of the following occurs:
which points to the result register that will receive the result of
ETORF: B)The Write toexternal
ATDCTL5 (a newtrigger overrun
conversion sequence is started)flag is set when
This register contains the C)SC bit used
If AFFC=1 to ofenable
and read special channel conversions.
a result register the current conversion.
ETRIGLE=0 (ATDCTL2)
0 Conversion sequence not completed and additional active edges are
1 Conversion sequence has completed
detected
Module Base + 0x00095 while
External a conversion
Trigger Overrun Flag — While in edgeis trigger
in progress.
mode (ETRIGLE =The flagactive
0), if additional is edges
cleared
are
ETORF detected while a conversion sequence is in process the overrun flag is set. This flag is cleared when one of the
when
7 a 1
followingis written
6 occurs: 5 to ETORF, 4 a conversion
3 sequence
2 is 1 0
A) Write “1” to ETORF
R Uaborted, B) or
UWrite a tonew
ATDCTL2,conversion
UATDCTL3 or ATDCTL4 U sequence
(a conversionU is started.
sequence U
is aborted) U
C) Write to ATDCTL5 (a new conversion sequence is started) SC
W 0 23:
Scott R. Little (Lecture No External trigger over run error has
ADC Config) occurred
ECE/CS 5780/6780 13 / 20 Scott R. Little (Lecture 23: ADC Config) ECE/CS 5780/6780 14 / 20
1 External trigger over run error has occurred
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Chapter 8 Analog-to-Digital or Reserved
Converter (ATD10B8C) Block Description

ATD TestFigure 8-11. ATD Test Register 1 (ATDTEST1)


ATDTEST1
8.3.2.9 Register 1 (ATDTEST1)
ATDSTAT1 Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description

Read: Anytime, returns unpredictable values for Bit 7 and Bit 6


This register contains the SC bit used to enable special channel conversions. 8.3.2.10 ATD Status Register 1 (ATDSTAT1)

Write: Anytime Module Base + 0x0009 This read-only register contains the Conversion Complete Flags.
7 6 5 4 3 2 1 0
Module Base + 0x000B
R U UTable 8-14.
U ATDTEST1
U FieldUDescriptions
U U
SC 7 6 5 4 3 2 1 0
W
Field Description R CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
Reset 0 0 0 0 0 0 0 0
W
0 Special Channel Conversion Bitor—
= Unimplemented If this bit is set, then special channel conversion can be selected using CC,
Reserved
Reset 0 0 0 0 0 0 0 0
SC CB, and CA of ATDCTL5. Table 8-15 lists the coding.
238 FigureMC9S12C-Family
8-11. ATD Test/Register 1 (ATDTEST1)
MC9S12GC-Family Freescale Semiconductor
0 Special channel conversions disabled = Unimplemented or Reserved
Rev 01.23
SC: Setting this bit allows a special conversion channel to be
1 Special
Read: channel
Anytime, conversions
returns enabled
unpredictable values for Bit 7 and Bit 6 Figure 8-12. ATD Status Register 1 (ATDSTAT1)
Note: Always write remaining bits of ATDTEST1 (Bit7 to Bit1) zero when writing SC bit. Not doing so might result
Write: Anytime
used. The special channel is selected via the CA, CB, and CC
in unpredictable ATD behavior. Read: Anytime
Table 8-14. ATDTEST1 Field Descriptions
bits. CCF[7:0]: A conversion complete flag is set at the end of each
Write: Anytime, no effect
Field Description Table 8-16. ATDSTAT1 Field Descriptions
0
Table 8-15. Special Channel Select Coding
Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using CC,
conversion in a conversion sequence. For example, CCF0 is set
Field Description
SC
SC
CB, and CA of ATDCTL5. Table 8-15 lists the coding.
0 Special CC CB
channel conversions CA
disabled Analog Input Channel
after
7–0
the first conversion when the data in ATDDR0 is available,
Conversion Complete Flag x (x = 7, 6, 5, 4, 3, 2, 1, 0) — A conversion complete flag is set at the end of each
1 Special channel conversions enabled
1Note: Always0 write remaining
X bits ofXATDTEST1 (Bit7 to Bit1) zero when Reserved
writing SC bit. Not doing so might result etc. AalsoCCF#
CCF[7:0] conversion in a flag is cleared when
conversion sequence. The flags are a new
associated conversion
with the conversion position in a sequence
sequence (and
the result register number). Therefore, CCF0 is set when the first conversion in a sequence is complete and
is
in unpredictable ATD behavior.
1 1 0 0 VRH started, if AFFC = 0 (ATDCTL2) and a read of ATDSTAT1
the result is available in result register ATDDR0; CCF1 is set when the second conversion in a sequence is
complete and the result is available in ATDDR1, and so forth. A flag CCFx (x = 7, 6, 5, 4, 3, 2, 1, 0) is cleared
is
when one of the following occurs:
1 1 0
Table 8-15.1Special Channel Select Coding
VRL followed byWriteatoread
A) ATDCTL5of (a newresult
conversionregister ATDDR#, or AFFC = 1 and
sequence is started)
1 1 1 0CA (V +V )/2 B) If AFFC = 0 and read of ATDSTAT1 followed by read of result register ATDDRx
SC CC CB RH
Analog Input RL
Channel a read ofC)aIf AFFC result= 1 andregister ATDDR#.
read of result register ATDDRx
1 11 0 1 X 1X Reserved
Reserved 0 Conversion number x not completed
1 Conversion number x has completed, result ready in ATDDRx
1 1 0 0 VRH
1 Config)
Scott R. Little (Lecture 23: ADC 1 0 1
ECE/CS 5780/6780 VRL 15 / 20 Scott R. Little (Lecture 23: ADC Config) ECE/CS 5780/6780 16 / 20
1 1 1 0 (VRH+VRL) / 2
1 1 1 1 Reserved
ATDDIEN ATDDR#H/ATDDR#L Left Justified
Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description

8.3.2.13.1 Left Justified Result Data


Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description

Module Base + 0x0010 = ATDDR0H, 0x0012 = ATDDR1H, 0x0014 = ATDDR2H, 0x0016 = ATDDR3H
8.3.2.11 ATD Input Enable Register (ATDDIEN) 0x0018 = ATDDR4H, 0x001A = ATDDR5H, 0x001C = ATDDR6H, 0x001E = ATDDR7H

7 6 5 4 3 2 1 0
Module Base + 0x000D
R BIT 9 MSB BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 10-bit data
7 6 5 4 3 2 1 0
W BIT 7 MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 8-bit data
R
IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 Reset 0 0 0 0 0 0 0 0
W
Figure 8-15. Left Justified, ATD Conversion Result Register, High Byte (ATDDRxH)
Reset 0 0 0 0 0 0 0 0

Figure 8-13. ATD Input Enable Register (ATDDIEN) Module Base + 0x0011 = ATDDR0L, 0x0013 = ATDDR1L, 0x0015 = ATDDR2L, 0x0017 = ATDDR3L
0x0019 = ATDDR4L, 0x001B = ATDDR5L, 0x001D = ATDDR6L, 0x001F = ATDDR7L
Read:
Chapter Anytime
8 Analog-to-Digital Converter (ATD10B8C) Block Description

IEN[7:0]: When IEN# is 0 digital input is disabled on PTAD#.


Write: AnytimeLeft Justified Result Data
8.3.2.13.1 R
7 6 5 4 3 2 1 0

BIT 1 BIT 0 0 0 0 0 0 0 10-bit data


When IEN# is 1 digital Table 8-17.input
ATDDIEN is enabled
Field Descriptionson PTAD#.
Module Base + 0x0010 = ATDDR0H, 0x0012 = ATDDR1H, 0x0014 = ATDDR2H, 0x0016 = ATDDR3H W U U 0 0 0 0 0 0 8-bit data

Field 0x0018 = ATDDR4H, 0x001A = ATDDR5H, 0x001C = ATDDR6H, 0x001E = ATDDR7H


Description Reset 0 0 0 0 0 0 0 0
7–0 ATD
7 Digital Input
6 Enable on 5 channel x4(x = 7, 6, 5, 4,3 3, 2, 1, 0) —
2 This bit controls
1 the digital
0 input buffer from Figure 8-16. Left Justified, ATD Conversion Result Register, Low Byte (ATDDRxL)
IEN[7:0]
R the analog input pin (ANx) to PTADx data register.
BIT 09 MSB BIT 8input buffer
Disable digital BIT 7to PTADxBIT 6 BIT 5 BIT 4 BIT 3 BIT 2 10-bit data
W BIT 17 MSB BIT 6input buffer
Enable digital BIT to
5 PTADx.BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 8-bit data
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while 8.3.2.13.2 Right Justified Result Data
Reset 0 0 0 0 0 0 0 0
simultaneously using it as an analog port, there is potentially increased power consumption because the
Figuredigital
8-15.input
Leftbuffer maybeATD
Justified, in theConversion
linear region.Result Register, High Byte (ATDDRxH) Module Base + 0x0010 = ATDDR0H, 0x0012 = ATDDR1H, 0x0014 = ATDDR2H, 0x0016 = ATDDR3H
0x0018 = ATDDR4H, 0x001A = ATDDR5H, 0x001C = ATDDR6H, 0x001E = ATDDR7H
Module(Lecture
Scott R. Little Base + 0x0011 = ATDDR0L,
23: ADC Config) 0x0013 = ATDDR1L,
ECE/CS0x0015 = ATDDR2L, 0x0017 = ATDDR3L
5780/6780 17 / 20 Scott R. Little (Lecture723: ADC Config)
6 5 ECE/CS
4 5780/6780
3 2 1 0 18 / 20
0x0019 = ATDDR4L, 0x001B = ATDDR5L, 0x001D = ATDDR6L, 0x001F = ATDDR7L
R 0 0 0 0 0 0 BIT 9 MSB BIT 8 10-bit data
7 6 5 4 3 2 1 0
W 0 0 0 0 0 0 0 0 8-bit data
R BIT 1 BIT 0 0 0 0 0 0 0 10-bit data Reset 0 0 0 0 0 0 0 0
W U U 0 0 0 0 0 0 8-bit data
Figure 8-17. Right Justified, ATD Conversion Result Register, High Byte (ATDDRxH)
ATDDR#H/ATDDR#L Right Justified
Reset 0 0 0 0 0 0 0 0 Setting up and starting an ADC conversion
Figure 8-16. Left Justified, ATD Conversion Result Register, Low Byte (ATDDRxL) Module Base + 0x0011 = ATDDR0L, 0x0013 = ATDDR1L, 0x0015 = ATDDR2L, 0x0017 = ATDDR3L
0x0019 = ATDDR4L, 0x001B = ATDDR5L, 0x001D = ATDDR6L, 0x001F = ATDDR7L

7 6 5 4 3 2 1 0
8.3.2.13.2 Right Justified Result Data R BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 10-bit data

Module Base + 0x0010 = ATDDR0H, 0x0012 = ATDDR1H, 0x0014 = ATDDR2H, 0x0016 = ATDDR3H W BIT 7 MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 8-bit data

0x0018 = ATDDR4H, 0x001A = ATDDR5H, 0x001C = ATDDR6H, 0x001E = ATDDR7H Power


Reset up the0 ADC 0(ADPU
0 0 = 1) 0 and other
0 ATDCTL2
0 0 settings.
7 6 5 4 3 2 1 0 Figure 8-18. Right Justified, ATD Conversion Result Register, Low Byte (ATDDRxL)
R 0 0 0 0 0 0 BIT 9 MSB BIT 8 10-bit data
Wait for the ADC recovery time.
W 0 0 0 0 0 0 0 0 8-bit data

Reset 0 0 0 0 0 0 0 0
Configure the number of conversions via ATDCTL3.
Figure 8-17. Right Justified, ATD Conversion Result Register, High Byte (ATDDRxH) Configure resolution, sampling time, and ADC clock speed via
Module Base + 0x0011 = ATDDR0L, 0x0013 = ATDDR1L, 0x0015 = ATDDR2L, 0x0017 = ATDDR3L ATDCTL4.
0x0019 = ATDDR4L, 0x001B = ATDDR5L, 0x001D = ATDDR6L, 0x001F = ATDDR7L 244 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
7 6 5 4 3 2 1 0
Configure the starting channel, single/multiple channel,
Rev 01.23

242 R BIT 7 BIT 6 BIT MC9S12C-Family


5 BIT 4 / MC9S12GC-Family
BIT 3 BIT 2 BIT 1 Freescale
BIT 0 Semiconductor
10-bit data continuous or single sequence and result data format via
W BIT 7 MSB BIT 6 BIT 5 BIT 4Rev 01.23
BIT 3 BIT 2 BIT 1 BIT 0 8-bit data

Reset 0 0 0 0 0 0 0 0
ATDCTL5. Writing to ATDCTL5 should happen last as it starts
Figure 8-18. Right Justified, ATD Conversion Result Register, Low Byte (ATDDRxL) the conversion.

Scott R. Little (Lecture 23: ADC Config) ECE/CS 5780/6780 19 / 20 Scott R. Little (Lecture 23: ADC Config) ECE/CS 5780/6780 20 / 20
244 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.23

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