2011 International Conference on Computer Applications and Industrial Electronics (ICCAIE 2011)

Design of Proportional Integral Derivative (PID)

Controller for Impedance-Source Inverter

B.Y. Husodo1,2 and S.M. Ayob1

1
Department of Energy Conversion Engineering
Faculty of Electrical Engineering
Universiti Teknologi Malaysia
Johor bahru, Malaysia
2
Department of Electrical Engineering
Faculty of Engineering
Universitas Mercu Buana
Jakarta, Indonesia

Abstract—This paper presents the design of voltage mode
control for impedance-source inverter using Proportional
Integral Derivative (PID) controller. The proposed controller
controls the output AC voltage by regulating the DC-link
voltage at the input side. Mathematical model of the inverter is
developed and the control parameters are design via Bode plot.
Simulation under source and load disturbances is carried out
to validate the design. From the results, it was shown that the
proposed controller is capable to regulate the AC output
voltage well.
Keywords; impedance-source inverter, proportional integral
derivative controller, voltage mode controller
I. INTRODUCTION
Conventional Voltage Source Inverter (VSI) is a
common circuit topology used in converting DC power to
AC power. However, it can only produce output AC voltage
lower than the input. This is the main drawback for the VSI.
As compared to VSI, impedance-source inverter (ZSI) is a
relatively new topology. The main feature of ZSI is that it
can boost up its output voltage higher than the input in one
stage DC-AC power conversion. Hence, a compact and
high efficiency power converter is obtained. In addition, the
reliability is improved due to the insertion of shoot-through
interval [1]. The structure of the ZSI is depicted in Fig. 1.
Numerous control techniques have been proposed for
controlling ZSI. In [2-4], the DC-link voltage is indirectly
controlled by the capacitor voltage (Vc) of the impedance
network. The capacitor voltage can be kept constant at a
desired value through the selection of proper shoot-through
duty ratio [2] and Kp and Ki parameters [3, 4] by the
controllers. However, when the inverter experiences a step
change of input voltage, the DC-link voltage changes though
Vc keeps constant and tends to become uncontrollable. This
will result in distortion in the inverter’s output voltage. The
other work proposed in [5] used a PID controller to maintain
the peak DC-link voltage directly through direct
measurement. It requires additional circuitry for peak
detection of the DC-link voltage. Hence the control becomes
more complex. In [6], a method for controlling the output
voltage of Z-Source Converter (ZSC) is proposed. The
output voltage, which is the DC-link voltage, is estimated by
the measurement of the input voltage (Vin) and Vc. Two types
of controller, voltage mode and current programmed mode,
are designed based on the above method. In [7], the design
procedure proposed in [6] is utilized to design voltage mode
and current mode control for a high-performance z-source
inverter.
This paper presents the design of voltage mode control
for a conventional z-source inverter using PID controller.
The controller regulates the AC output by controlling the
DC-link voltage at the input side. The Kp, Ki, and Kd
parameters of the PID are calculated using Sisotool, a tool in
Matlab/Simulink for controller design. The PWM pulses
needed for triggering the inverter’s switches are generated
using modulation method presented in [2]. Through this
paper, it is shown that the controller is capable to maintain
the DC-link voltage during source and load disturbance.
Figure 1. Z-source inverter structure
II. Z-SOURCE INVERTER OPERATION
In the operation of ZSI, the third state called shoot-through
state exists together with the null states and the active states.
Shoot-through state is a condition where both switches of an
inverter leg in PWM inverter conduct simultaneously, which
is prohibited in traditional VSI’s since may cause a short
circuit condition that could destroy the inverter. Thus, there
are two conditions in the operation of ZSI, the shoot-through

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state and the non shoot-through state. With symmetric z- III. CONTROLLER DESIGN
source network, i.e. L1 = L2 = L and C1= C2 = C, the inverter The complete system configuration for ZSI connected to
side of z-source network can treated by an equivalent current a three phase load is shown in Fig. 3. The average output
source with a finite current during non shoot through state voltage of ZSI depends on the DC-link voltage and the
and a zero current during shoot through state. The equivalent modulation index. The control strategy is to control the ZSI
circuit of the two conditions can be seen in Fig. 2(a) and (b) from the DC side only. The modulation index is adjusted
respectively [1, 8]. From Fig. 2, the voltage across z-source
using the relationship m + do = 1 . The DC-link voltage, Vdc,
capacitor is
is taken as the control target and the control algorithm is
⎛ ⎛T ⎞ ⎞ shown in Fig. 4. The control (duty ratio) to peak DC-link
⎛ Tsh ⎞ ⎜ 1 − ⎜ sh T ⎟ ⎟ voltage transfer function can be expressed as (4) [7]. Using
Vc = ⎜⎜ ⎟Vin = ⎜ ⎝ ⎠ ⎟ 1 − do V (1)
⎟ in parameters listed in Table I, the transfer function can be
⎝ Tns − Tsh ⎠ ⎜ ⎛ Tsh ⎞ ⎟ 1 − 2d o
⎜ 1 − 2⎜ T ⎟ ⎟ rewritten as
⎝ ⎝ ⎠⎠
2.06 x10−7 s 2 + 216 s + 32920
Peak DC-link voltage across the inverter bridge is given by Gvdpd = (5)
5.4 x10− 8 s 3 + 8.23 x10− 6 s 2 + 0.0948s + 14.34
Vˆdc = 2Vc − Vin = BVin (2)
The magnitude and phase asymptotes of the ZSI’s loop gain
The output peak phase voltage is defined as without compensator is sketched in Fig. 5. The phase
margin is 0.003280. It is inadequately too small for power
mVˆdc m( BVin ) ⎛ mVin ⎞ converter application which usually needs 400 – 600 phase
vˆac = = = B⎜ ⎟ (3) margin. A controller is needed to increase the phase margin.
2 2 ⎝ 2 ⎠ Initially, PI controller is designed for controlling the DC-link
Tsh : shoot-through period voltage. In this study, the crossover frequency, fc is taken to
be one-tenth of the switching frequency or less. Fig. 6 shows
Tns : non-shoot-through period the magnitude and phase asymptote of the loop gain
compensated by PI controller using various frequencies that
T : switching period are lower than fc. From Fig. 6, it can be seen that PI
controller is inadequate to improve the phase margin.
m : modulation index
A PID controller is then designed. The final PID transfer
d o : shoot-through duty ratio function is obtained and given by
Vin : inverter’s DC input voltage ( s + 1000)(s + 1000)
Gc ( s ) = 6.107 (6)
s ( s + 30200)
The magnitude and phase asymptote of the system
compensated by this PID controller is depicted in Fig. 7. It is
observed from Fig. 7 that using PID controller, the phase
margin increases to 47.10 at crossover frequency 471 Hz,
somewhat adequate to ensure stable operation under
disturbances.

(a)

(b)

Figure 2. Equivalent circuit of z-source inverter (a) Non-shoot-through

state (b) Shoot-through state Figure 3. Voltage mode control of z-source inverter using PID
controller

122
 (−2 I L + I l ) Ll Ls 2 + {(−2 I L + I l ) Rl L + (1 − d o )(2Vc − Vin ) L + (1 − 2d o )(2Vc − Vin ) Ll ]s + (1 − 2d o )(2Vc − Vin ) Rl
Gvdpd = 2
Ll LCs 3 + Rl LCs 2 + [2 L(1 − d o ) 2 + Ll (2d o − 1) 2 ]s + Rl ( 2d o − 1) 2 (4)

Bode Diagram
From: In1 To: Transfer Fcn
TABLE I SIMULATION PARAMETERS 150

100

Vin (V) 500

Magnitude (dB)
50

L (μH) 500 0

-50
C (μF) 500
-100
Do 0.17
-150
0
Rl (Ω) 32.92
-45
Ll (mH) 216

Phase (deg)
-90
fs (kHz) 10
-135

-180

-225
-2 -1 0 1 2 3 4 5 6
10 10 10 10 Frequency
10 (Hz) 10 10 10 10

Figure 6. Bode diagram of ZSI transfer function compensated with PI

Open-Loop Bode Editor for Open Loop 1 (OL1)

100

50
Magnitude (dB)

Figure 4. Control algorithm of z-source peak DC-link voltage

0

-50 G.M.: Inf

I. SIMULATION RESULTS AND DISCUSSIONS Freq: NaN
Stable loop

The simulation for the ZSI system is carried out using -100
90
Matlab/Simulink software. The DC-link voltage of the ZSI is P.M.: 47.1 deg
Freq: 471 Hz
required to be maintained at 757 V to produce RMS line 0
Phase (deg)

output voltage of 385 V. The performance of the designed

voltage mode controller is tested during source and load -90
disturbances.
Bode Diagram
-180
0 1 2 3 4 5
From: In1 To: Transfer Fcn 10 10 10 10 10 10
100 Frequency (Hz)

50 Figure 7. Bode diagram of ZSI transfer function compensated with

Magnitude (dB)

PID
0

-50
A. Performance of the Controller Under No Disturbance
-100 Inverter output voltage, output current, DC-link voltage
0
and inductor current at steady state under no disturbance are
-45 presented in Fig. 8(a). As can be seen in Fig. 8(b), the DC-
link voltage is 757 V. This result shows that the controller
Phase (deg)

-90
can successfully track the reference. Although ripples are
-135 observed in the DC-link voltage, they are very small and
insignificant to the control performances. The DC-link
-180
10
1 2
10 Frequency (Hz) 10
3
10
4 voltage ripples is observed as 0.5%.

Figure 5. Bode diagram of ZSI transfer function without compensation

123
 1000
500
Vabc

Vabc
0 0
-500
-1000
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2 0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2
100
100
Iabc

Iabc
0
-100
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2 -100
1000 0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2
2000
Vdc

500

Vdc
1000
0
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2 0
100 0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2

50 0.2
IL

Do
0.1
0
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2
0
t 0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2
t
(a)
Figure 9. Dynamic response of the ZSI when subjected to 20% input
1000 voltage increase

950
500

Vabc
0
900
-500
850 0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2
757 V 100
Vdc

800
Iabc

750 -100
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2
700 2000
Vdc

1000
650
0
600 0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2
t 0.3
Do

0.2
(b)
Figure 8 (a) Steady-state response of ZSI under no disturbances (b) 0.1
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2
Zoomed image of the DC-link voltage t

Figure 10. Dynamic response of the ZSI under 20% input voltage drop
B. Performance of the Controller Under Source
Disturbance
When the input voltage changes 20% from 500 to 600 V, 500
the corresponding simulation results are presented in Fig. 9.
Vabc

0
The figure shows how the converter changes the duty ratio in -500
order for the ZSI to have required DC-link voltage. This duty 0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2
ratio regulation keeps the output voltages and output currents 200

unchanged at the required value.

Iabc

0
-200
Fig. 10 shows simulation results when the inverter is 0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2
subjected to the input voltage drop from 500 to 400 V (20%). 2000

Again, the output voltage and the output current can be

Vdc

1000
maintained as well as the DC-link voltage due to duty ratio
0
regulation carried out by the controller. 0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2

0.3
C. Performance of the Controller Under Load Disturbance
Do

0.2
The simulation results of the ZSI during sudden heavy load 0.1
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2
change are presented in Fig.11. The load changes from 30 t
kW to 90 kW. It is observed that the output current increases
due to load increase. The duty ratio changes slightly higher Figure 11. Dynamic response of the ZSI under heavy load disturbance
to maintain the DC-link and output voltage of the ZSI.

124
 II. CONCLUSION
This paper presents the design of voltage mode
Proportional Integral Derivative (PID) controller for
Impedance-source inverter. The proposed controller
regulates the output AC voltage by regulating the DC-link
voltage at the input side. Mathematical model has been
derived and the control parameters are designed via Bode
plot. Simulation under source and load disturbances has
been carried out and the results show that the design is
validated.
ACKNOWLEDGMENT
This paper has been supported by Ministry of Higher
Education Malaysia (MOHE) and Universiti Teknologi
Malaysia under Fundamental Research Grant Scheme
(FRGS) (Vot. No: 78685)
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