GEH-6721 Vol II

GE Energy GEH-6721L
Mark* VIe Control Vol. II

System Hardware Guide
System Guide
SIZE DWG N
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ORMAT.
Disclaimer
These instructions do not purport to cover all details or variations in equipment, nor to provide for every possible contingency
to be met during installation, operation, and maintenance. The information is supplied for informational purposes only, and
GE makes no warranty as to the accuracy of the information included herein. Changes, modifications, and/or improvements to
equipment and specifications are made periodically and these changes may or may not be reflected herein. It is understood
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Revised: 100223
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Contents
Mark VIe Controllers (UCCx and UCSx) ........................................................................ 1-1
UCCx Controller ............................................................................................................................... 1-1
Installation ................................................................................................................................ 1-1
Operation .................................................................................................................................. 1-2
Configuration ............................................................................................................................. 1-2
Controller Battery ....................................................................................................................... 1-3
Cooling Fan ............................................................................................................................... 1-5
EPMC ...................................................................................................................................... 1-5
UCCA Processor ........................................................................................................................ 1-6
UCCC Processor......................................................................................................................... 1-9
CPCI Control Module....................................................................................................................... 1-12
Installation .............................................................................................................................. 1-12
Operation ................................................................................................................................ 1-13
Specifications........................................................................................................................... 1-14
CPCI Component Replacement ................................................................................................... 1-14
Power Supply(s) .............................................................................................................................. 1-16
Installation .............................................................................................................................. 1-16
Operation ................................................................................................................................ 1-17
Specifications........................................................................................................................... 1-17
Power Supply Replacement ........................................................................................................ 1-18
UCSx Controller ............................................................................................................................. 1-19
Installation .............................................................................................................................. 1-20
Operation ................................................................................................................................ 1-21
UCSA Specifications ................................................................................................................. 1-24
Configuration ........................................................................................................................... 1-25
PAIC Analog Input/Output Module................................................................................. 2-1
Analog Input/Output (PAIC) ................................................................................................................ 2-1
Functional Description ................................................................................................................. 2-1
Installation ................................................................................................................................ 2-3
Operation .................................................................................................................................. 2-4
Specifications........................................................................................................................... 2-13
Diagnostics.............................................................................................................................. 2-14
Configuration ........................................................................................................................... 2-15
TBAI Analog Input/Output................................................................................................................ 2-18
Functional Description ............................................................................................................... 2-18
Installation .............................................................................................................................. 2-19
Operation ................................................................................................................................ 2-21
Specifications........................................................................................................................... 2-23
Diagnostics.............................................................................................................................. 2-23
Configuration ........................................................................................................................... 2-23
STAI Simplex Analog Input............................................................................................................... 2-24
Installation .............................................................................................................................. 2-25
Operation ................................................................................................................................ 2-27
Specifications........................................................................................................................... 2-28
Diagnostics.............................................................................................................................. 2-28
Configuration ........................................................................................................................... 2-28
SAII Simplex Isolated Analog Input .................................................................................................... 2-29
Installation .............................................................................................................................. 2-29
Operation ................................................................................................................................ 2-34
Specifications........................................................................................................................... 2-36
Diagnostics.............................................................................................................................. 2-36
Configuration ........................................................................................................................... 2-37
PAMB Acoustic Monitoring Input Module..................................................................... 3-1
Acoustic Monitoring Input (PAMB) ......................................................................................................3-1
Functional Description .................................................................................................................3-1
Installation ................................................................................................................................3-3
Operation ..................................................................................................................................3-4
Specifications........................................................................................................................... 3-10
Diagnostics.............................................................................................................................. 3-10
Configuration ........................................................................................................................... 3-11
SAMB Acoustic Monitoring Input ...................................................................................................... 3-15
Installation .............................................................................................................................. 3-15
Operation ................................................................................................................................ 3-18
Specifications........................................................................................................................... 3-19
Diagnostics.............................................................................................................................. 3-19
PAMC Acoustic Monitoring Input Module..................................................................... 4-1
Acoustic Monitoring Input (PAMC) ......................................................................................................4-1
Installation ................................................................................................................................4-3
Operation ..................................................................................................................................4-7
Specifications........................................................................................................................... 4-17
Diagnostics.............................................................................................................................. 4-17
Configuration ........................................................................................................................... 4-18
SAMB Acoustic Monitoring Input ...................................................................................................... 4-24
Installation .............................................................................................................................. 4-24
Operation ................................................................................................................................ 4-27
Specifications........................................................................................................................... 4-28
Diagnostics.............................................................................................................................. 4-28
PAOC Analog Output Module......................................................................................... 5-1
Analog Output (PAOC).......................................................................................................................5-1
Installation ................................................................................................................................5-2
Operation ..................................................................................................................................5-3
Specifications.............................................................................................................................5-9
Diagnostics.............................................................................................................................. 5-10
Configuration ........................................................................................................................... 5-11
TBAO Analog Output ...................................................................................................................... 5-12
Installation .............................................................................................................................. 5-13
Operation ................................................................................................................................ 5-14
Specifications........................................................................................................................... 5-16
Diagnostics.............................................................................................................................. 5-16
Configuration ........................................................................................................................... 5-16
STAO Simplex Analog Output ........................................................................................................... 5-17
Installation .............................................................................................................................. 5-17
Operation ................................................................................................................................ 5-19
Specifications........................................................................................................................... 5-19
Diagnostics.............................................................................................................................. 5-20
Configuration ........................................................................................................................... 5-20
PCAA Core Analog Module ............................................................................................ 6-1
Core Analog Module (PCAA) ..............................................................................................................6-1
Installation ................................................................................................................................6-4
Wiring ...................................................................................................................................... 6-5
Operation .................................................................................................................................. 6-8
Specifications........................................................................................................................... 6-35
Diagnostics.............................................................................................................................. 6-36
Configuration ........................................................................................................................... 6-37
TCAT Core Analog Terminal Board .................................................................................................... 6-40
Installation .............................................................................................................................. 6-42
Operation ................................................................................................................................ 6-45
Specifications........................................................................................................................... 6-45
Diagnostics.............................................................................................................................. 6-46
Configuration ........................................................................................................................... 6-46
JGPA Ground and Power Board.......................................................................................................... 6-47
Installation .............................................................................................................................. 6-48
Operation ................................................................................................................................ 6-48
Specifications........................................................................................................................... 6-49
Diagnostics.............................................................................................................................. 6-49
Configuration ........................................................................................................................... 6-49
PCLA Core Analog Module - Aero ................................................................................. 7-1
Core Analog I/O for Aero (PCLA) ........................................................................................................ 7-1
Installation ................................................................................................................................ 7-5
Operation .................................................................................................................................. 7-6
Specifications........................................................................................................................... 7-17
Diagnostics.............................................................................................................................. 7-19
Configuration ........................................................................................................................... 7-20
SCLS Core Analog Terminal Board .................................................................................................... 7-25
Installation .............................................................................................................................. 7-27
Operation ................................................................................................................................ 7-29
SCLS Specifications .................................................................................................................. 7-35
Diagnostics.............................................................................................................................. 7-36
SCLS Configuration .................................................................................................................. 7-37
SCLT Core Analog Terminal Board..................................................................................................... 7-38
Installation .............................................................................................................................. 7-40
Operation ................................................................................................................................ 7-42
SCLT Specifications .................................................................................................................. 7-44
Diagnostics.............................................................................................................................. 7-45
PCNO CANopen Master Gateway Module..................................................................... 8-1
CANopen Master Gateway (PCNO) ...................................................................................................... 8-1
Installation ................................................................................................................................ 8-3
Operation .................................................................................................................................. 8-4
Specifications............................................................................................................................. 8-9
Diagnostics................................................................................................................................ 8-9
PDIA Discrete Input Module ........................................................................................... 9-1
Discrete Input (PDIA) ........................................................................................................................ 9-1
Installation ................................................................................................................................ 9-3
Operation .................................................................................................................................. 9-4
Specifications............................................................................................................................. 9-8
Diagnostics................................................................................................................................ 9-8
Configuration ............................................................................................................................. 9-9
TBCI Contact Input with Group Isolation ............................................................................................. 9-10
Installation .............................................................................................................................. 9-11
Operation ................................................................................................................................ 9-13
Specifications........................................................................................................................... 9-14
Diagnostics.............................................................................................................................. 9-15
Configuration ........................................................................................................................... 9-15
TICI Contact Input with Point Isolation ............................................................................................... 9-16
Installation .............................................................................................................................. 9-17
Operation ................................................................................................................................ 9-18
Specifications........................................................................................................................... 9-20
Diagnostics.............................................................................................................................. 9-20
Configuration ........................................................................................................................... 9-20
STCI Simplex Contact Input .............................................................................................................. 9-21
Installation .............................................................................................................................. 9-22
Operation ................................................................................................................................ 9-23
Specifications........................................................................................................................... 9-24
Diagnostics.............................................................................................................................. 9-24
Configuration ........................................................................................................................... 9-24
PDII Isolated Discrete Input Module ............................................................................ 10-1
Isolated Discrete Input (PDII) ............................................................................................................ 10-1
Installation .............................................................................................................................. 10-3
Operation ................................................................................................................................ 10-4
Specifications........................................................................................................................... 10-8
Diagnostics.............................................................................................................................. 10-9
Configuration ......................................................................................................................... 10-10
SDII Simplex Contact Input with Point Isolation.................................................................................. 10-12
Functional Description ............................................................................................................. 10-12
Installation ............................................................................................................................ 10-15
Operation .............................................................................................................................. 10-24
Specifications......................................................................................................................... 10-37
PDIO Discrete Input/Output Module ............................................................................ 11-1
Discrete Input/Output (PDIO) ............................................................................................................ 11-1
Installation .............................................................................................................................. 11-3
Operation ................................................................................................................................ 11-4
Specifications........................................................................................................................... 11-9
Diagnostics.............................................................................................................................. 11-9
Configuration ......................................................................................................................... 11-10
TDBS Simplex Discrete Input/Output.................................................................................................11-11
Functional Description ..............................................................................................................11-11
Installation ............................................................................................................................ 11-12
Operation .............................................................................................................................. 11-16
Specifications......................................................................................................................... 11-20
Diagnostics............................................................................................................................ 11-21
Configuration ......................................................................................................................... 11-21
TDBT Discrete Input/Output ........................................................................................................... 11-22
Installation ............................................................................................................................ 11-23
Operation .............................................................................................................................. 11-26
Specifications......................................................................................................................... 11-29
Diagnostics............................................................................................................................ 11-30
Configuration ......................................................................................................................... 11-30
PDOA Discrete Output Module .................................................................................... 12-1
Discrete Output (PDOA) ................................................................................................................... 12-1
Installation .............................................................................................................................. 12-2
Operation ................................................................................................................................ 12-3
Specifications........................................................................................................................... 12-7
Diagnostics.............................................................................................................................. 12-7
Configuration ........................................................................................................................... 12-8
TRLYH1B Relay Output with Coil Sensing ........................................................................................ 12-10
Installation ............................................................................................................................ 12-11
Operation .............................................................................................................................. 12-13
Specifications......................................................................................................................... 12-16
Diagnostics............................................................................................................................ 12-17
Configuration ......................................................................................................................... 12-17
TRLYH1C Relay Output with Contact Sensing ................................................................................... 12-18
Installation ............................................................................................................................ 12-20
Operation .............................................................................................................................. 12-21
Specifications......................................................................................................................... 12-23
Diagnostics............................................................................................................................ 12-24
Configuration ......................................................................................................................... 12-24
TRLYH1D Relay Output with Solenoid Integrity Sensing ..................................................................... 12-25
Installation ............................................................................................................................ 12-27
Operation .............................................................................................................................. 12-28
Specifications......................................................................................................................... 12-30
Diagnostics............................................................................................................................ 12-30
Configuration ......................................................................................................................... 12-31
TRLYH1E Solid-State Relay Output ................................................................................................. 12-31
Installation ............................................................................................................................ 12-33
Operation .............................................................................................................................. 12-34
Specifications......................................................................................................................... 12-37
Diagnostics............................................................................................................................ 12-38
Configuration ......................................................................................................................... 12-38
TRLYH1F Relay Output with TMR Contact Voting ............................................................................. 12-39
Installation ............................................................................................................................ 12-41
Operation .............................................................................................................................. 12-44
Specifications......................................................................................................................... 12-48
Diagnostics............................................................................................................................ 12-49
Configuration ......................................................................................................................... 12-49
SRLY Simplex Relay Output ........................................................................................................... 12-50
Installation ............................................................................................................................ 12-51
Operation .............................................................................................................................. 12-54
Specification .......................................................................................................................... 12-58
Diagnostics............................................................................................................................ 12-59
Configuration ......................................................................................................................... 12-59
PEFV Electric Fuel Valve Gateway .............................................................................. 13-1
Electrical Fuel Valve Gateway (PEFV) ................................................................................................ 13-1
Installation .............................................................................................................................. 13-2
Operation ................................................................................................................................ 13-3
Specifications........................................................................................................................... 13-6
Configuration ........................................................................................................................... 13-7
PGEN Turbine Generator Monitor Module .................................................................. 14-1
Turbine Generator Monitor (PGEN) .................................................................................................... 14-1
Installation .............................................................................................................................. 14-3
Operation ................................................................................................................................ 14-4
Specifications........................................................................................................................... 14-9
Diagnostics............................................................................................................................ 14-10
Configuration ......................................................................................................................... 14-11
TGNA Turbine-Generator ............................................................................................................... 14-17
Installation ............................................................................................................................ 14-19
Operation .............................................................................................................................. 14-22
Specifications......................................................................................................................... 14-22
Diagnostics............................................................................................................................ 14-23
Configuration ......................................................................................................................... 14-23
PHRA HART Enabled Analog I/O Module.................................................................... 15-1
HART Enabled Analog Input/Output (PHRA) ....................................................................................... 15-1
Installation .............................................................................................................................. 15-2
Operation ................................................................................................................................ 15-3
Specifications........................................................................................................................... 15-9
Diagnostics............................................................................................................................ 15-10
Configuration ......................................................................................................................... 15-11
SHRA HART Enabled Analog Input/Output ....................................................................................... 15-16
Installation ............................................................................................................................ 15-17
Operation .............................................................................................................................. 15-19
Specifications......................................................................................................................... 15-20
Diagnostics............................................................................................................................ 15-20
Configuration ......................................................................................................................... 15-20
PPRA Emergency Turbine Protection ......................................................................... 16-1
Emergency Turbine Protection (PPRA) ................................................................................................ 16-1
Installation .............................................................................................................................. 16-3
Operation ................................................................................................................................ 16-4
Specifications......................................................................................................................... 16-25
Diagnostics............................................................................................................................ 16-25
Configuration ......................................................................................................................... 16-26
TREA/WREA Turbine Emergency Trip ............................................................................................. 16-31
Installation ............................................................................................................................ 16-34
Operation .............................................................................................................................. 16-39
Specifications......................................................................................................................... 16-43
Diagnostics............................................................................................................................ 16-44
Configuration ......................................................................................................................... 16-44
PPRF PROFIBUS Master Gateway............................................................................... 17-1
PROFIBUS Master Gateway (PPRF)................................................................................................... 17-1
Installation .............................................................................................................................. 17-3
Operation ................................................................................................................................ 17-4
Specifications........................................................................................................................... 17-7
Diagnostics.............................................................................................................................. 17-8
Configuration ......................................................................................................................... 17-11
PPRO Backup Turbine Protection Module.................................................................. 18-1
Turbine Protection (PPRO)................................................................................................................ 18-1
Installation .............................................................................................................................. 18-5
Operation ................................................................................................................................ 18-6
Specifications......................................................................................................................... 18-28
Diagnostics............................................................................................................................ 18-29
Configuration ......................................................................................................................... 18-30
TPROH#C Emergency Protection ..................................................................................................... 18-36
Installation ............................................................................................................................ 18-37
Operation .............................................................................................................................. 18-40
Specification .......................................................................................................................... 18-42
Diagnostics............................................................................................................................ 18-42
Configuration ......................................................................................................................... 18-42
TREA Turbine Emergency Trip........................................................................................................ 18-43
Installation ............................................................................................................................ 18-45
Operation .............................................................................................................................. 18-48
Specifications......................................................................................................................... 18-51
Diagnostics............................................................................................................................ 18-52
Configuration ......................................................................................................................... 18-52
TREG Turbine Emergency Trip........................................................................................................ 18-53
Installation ............................................................................................................................ 18-56
Operation .............................................................................................................................. 18-57
Specifications......................................................................................................................... 18-59
Diagnostics............................................................................................................................ 18-60
Configuration ......................................................................................................................... 18-60
TREL Turbine Emergency Trip ........................................................................................................ 18-61
Installation ............................................................................................................................ 18-62
Operation .............................................................................................................................. 18-63
Specifications......................................................................................................................... 18-65
Diagnostics............................................................................................................................ 18-65
Configuration ......................................................................................................................... 18-65
TRES Turbine Emergency Trip ........................................................................................................ 18-66
Installation ............................................................................................................................ 18-67
Operation .............................................................................................................................. 18-68
Specifications......................................................................................................................... 18-70
Diagnostics............................................................................................................................ 18-70
Configuration ......................................................................................................................... 18-70
SPRO Emergency Protection ........................................................................................................... 18-71
Installation ............................................................................................................................ 18-73
Operation .............................................................................................................................. 18-74
Specifications......................................................................................................................... 18-76
Diagnostics............................................................................................................................ 18-76
Configuration ......................................................................................................................... 18-76
PRTD Input Module ....................................................................................................... 19-1
RTD Input (PRTD) .......................................................................................................................... 19-1
Installation .............................................................................................................................. 19-3
Operation ................................................................................................................................ 19-4
Diagnostics.............................................................................................................................. 19-9
Configuration ......................................................................................................................... 19-10
TRTD RTD Input .......................................................................................................................... 19-12
Installation ............................................................................................................................ 19-13
Operation .............................................................................................................................. 19-15
Specifications......................................................................................................................... 19-17
Diagnostics............................................................................................................................ 19-18
Configuration ......................................................................................................................... 19-19
SRTD Simplex RTD Input............................................................................................................... 19-19
Installation ............................................................................................................................ 19-19
Operation .............................................................................................................................. 19-21
Specifications......................................................................................................................... 19-22
Diagnostics............................................................................................................................ 19-24
Configuration ......................................................................................................................... 19-24
PSCA Serial Communication I/O Module .................................................................... 20-1
Serial Communication Input/Output (PSCA)......................................................................................... 20-1
Installation .............................................................................................................................. 20-2
Operation ................................................................................................................................ 20-3
Specifications......................................................................................................................... 20-10
Diagnostics............................................................................................................................ 20-10
SSCA Simplex Serial Communication Input/Output ............................................................................. 20-11
Installation ............................................................................................................................ 20-11
Operation .............................................................................................................................. 20-12
Specifications......................................................................................................................... 20-13
Diagnostics............................................................................................................................ 20-14
Configuration ......................................................................................................................... 20-14
DPWA Transducer Power Distribution............................................................................................... 20-15
Installation ............................................................................................................................ 20-16
Operation .............................................................................................................................. 20-17
Specifications......................................................................................................................... 20-18
Diagnostics............................................................................................................................ 20-18
Configuration ......................................................................................................................... 20-18
XDSA Transducer Interface............................................................................................................. 20-19
Installation ............................................................................................................................ 20-19
Operation .............................................................................................................................. 20-23
Specifications......................................................................................................................... 20-24
Diagnostics............................................................................................................................ 20-24
Configuration ......................................................................................................................... 20-24
PSVO Servo Control Module ........................................................................................ 21-1
Servo Control (PSVO)...................................................................................................................... 21-1
Installation .............................................................................................................................. 21-2
Operation ................................................................................................................................ 21-3
Specifications........................................................................................................................... 21-8
Diagnostics.............................................................................................................................. 21-9
Configuration ......................................................................................................................... 21-10
TSVC Servo Input/Output ............................................................................................................... 21-24
Installation ............................................................................................................................ 21-25
Operation .............................................................................................................................. 21-26
Specifications......................................................................................................................... 21-30
Diagnostics............................................................................................................................ 21-31
Configuration ......................................................................................................................... 21-31
PSVP Servo Control - Steam ........................................................................................ 22-1
Servo Control - Steam (PSVO)........................................................................................................... 22-1
Installation .............................................................................................................................. 22-3
Operation ................................................................................................................................ 22-4
Specifications......................................................................................................................... 22-15
Diagnostics............................................................................................................................ 22-16
Configuration ......................................................................................................................... 22-17
SSVP Servo Input/Output................................................................................................................ 22-42
Installation ............................................................................................................................ 22-44
Operation .............................................................................................................................. 22-45
Specifications......................................................................................................................... 22-49
Diagnostics............................................................................................................................ 22-49
Configuration ......................................................................................................................... 22-50
PTCC Thermocouple Input Module ............................................................................. 23-1
Thermocouple Input (PTCC) ............................................................................................................. 23-1
Installation .............................................................................................................................. 23-3
Operation ................................................................................................................................ 23-4
Specifications......................................................................................................................... 23-10
Diagnostics............................................................................................................................ 23-11
Configuration ......................................................................................................................... 23-12
TBTC Thermocouple Input.............................................................................................................. 23-15
Installation ............................................................................................................................ 23-16
Operation .............................................................................................................................. 23-17
Specifications......................................................................................................................... 23-20
Diagnostics............................................................................................................................ 23-20
Configuration ......................................................................................................................... 23-20
STTC Simplex Thermocouple Input .................................................................................................. 23-21
Installation ............................................................................................................................ 23-22
Operation .............................................................................................................................. 23-23
Specifications......................................................................................................................... 23-24
Diagnostics............................................................................................................................ 23-24
Configuration ......................................................................................................................... 23-24
PTUR Turbine Specific Primary Trip ........................................................................... 24-1
Primary Turbine Specific Primary Trip (PTUR) ..................................................................................... 24-1
Installation .............................................................................................................................. 24-3
Operation ................................................................................................................................ 24-4
Specifications......................................................................................................................... 24-26
Diagnostics............................................................................................................................ 24-27
Configuration ......................................................................................................................... 24-28
TTUR_1C Primary Turbine Protection Input....................................................................................... 24-34
Installation ............................................................................................................................ 24-37
Operation .............................................................................................................................. 24-38
Specifications......................................................................................................................... 24-40
Diagnostics............................................................................................................................ 24-41
Configuration ......................................................................................................................... 24-41
TRPG Turbine Primary Trip ............................................................................................................ 24-42
Installation ............................................................................................................................ 24-44
Operation .............................................................................................................................. 24-45
Specifications......................................................................................................................... 24-46
Diagnostics............................................................................................................................ 24-46
Configuration ......................................................................................................................... 24-46
TRPA Turbine Primary Trip............................................................................................................. 24-47
Installation ............................................................................................................................ 24-48
Operation .............................................................................................................................. 24-52
Specifications......................................................................................................................... 24-57
Diagnostics............................................................................................................................ 24-58
Configuration ......................................................................................................................... 24-58
TRPL Turbine Primary Trip............................................................................................................. 24-59
Installation ............................................................................................................................ 24-60
Operation .............................................................................................................................. 24-61
Specifications......................................................................................................................... 24-63
Diagnostics............................................................................................................................ 24-63
Configuration ......................................................................................................................... 24-63
TRPS Turbine Primary Trip ............................................................................................................. 24-64
Installation ............................................................................................................................ 24-65
Operation .............................................................................................................................. 24-66
Specifications......................................................................................................................... 24-68
Diagnostics............................................................................................................................ 24-68
Configuration ......................................................................................................................... 24-68
STUR Simplex Primary Turbine Protection Input ................................................................................ 24-69
Installation ............................................................................................................................ 24-70
Operation .............................................................................................................................. 24-72
Specifications......................................................................................................................... 24-77
Diagnostics............................................................................................................................ 24-78
Configuration ......................................................................................................................... 24-78
PVIB Vibration Monitor Module.................................................................................... 25-1
Vibration Monitor (PVIB) ................................................................................................................. 25-1
Installation .............................................................................................................................. 25-2
Operation ................................................................................................................................ 25-3
Specifications......................................................................................................................... 25-21
Diagnostics............................................................................................................................ 25-22
Configuration ......................................................................................................................... 25-23
TVBA Vibration Input.................................................................................................................... 25-28
Installation ............................................................................................................................ 25-29
Operation .............................................................................................................................. 25-32
Specifications......................................................................................................................... 25-34
Diagnostics............................................................................................................................ 25-35
Configuration ......................................................................................................................... 25-35
PDM Power Distribution Modules ............................................................................... 26-1
Power Distribution Modules (PDM) .................................................................................................... 26-1
Operation ................................................................................................................................ 26-3
PPDA Power Distribution System Feedback ....................................................................................... 26-13
Installation ............................................................................................................................ 26-14
Operation .............................................................................................................................. 26-16
Diagnostics............................................................................................................................ 26-19
Configuration ......................................................................................................................... 26-19
DS2020DACAG2 ac-dc Power Conversion ........................................................................................ 26-23
Installation ............................................................................................................................ 26-23
Operation .............................................................................................................................. 26-26
Specifications......................................................................................................................... 26-27
Diagnostics............................................................................................................................ 26-27
Configuration ......................................................................................................................... 26-27
JPDA Local ac Power Distribution.................................................................................................... 26-28
Installation ............................................................................................................................ 26-29
Operation .............................................................................................................................. 26-30
Specifications......................................................................................................................... 26-31
Diagnostics............................................................................................................................ 26-31
Configuration ......................................................................................................................... 26-31
JPDB Ac Power Distribution ........................................................................................................... 26-32
Installation ............................................................................................................................ 26-33
Operation .............................................................................................................................. 26-34
I/O Characteristics .................................................................................................................. 26-38
Specifications......................................................................................................................... 26-39
Diagnostics............................................................................................................................ 26-39
Configuration ......................................................................................................................... 26-39
JPDC Power Distribution Module ..................................................................................................... 26-40
Installation ............................................................................................................................ 26-40
Operation .............................................................................................................................. 26-42
Specifications......................................................................................................................... 26-46
Diagnostics............................................................................................................................ 26-47
Configuration ......................................................................................................................... 26-48
Handling Precautions............................................................................................................... 26-49
JPDD Dc Power Distribution ........................................................................................................... 26-50
Installation ............................................................................................................................ 26-51
Operation .............................................................................................................................. 26-52
Specifications......................................................................................................................... 26-53
Diagnostics............................................................................................................................ 26-53
Configuration ......................................................................................................................... 26-53
JPDE Dc Battery Power Distribution ................................................................................................. 26-54
Installation ............................................................................................................................ 26-54
Operation .............................................................................................................................. 26-55
Specifications......................................................................................................................... 26-57
Diagnostics............................................................................................................................ 26-57
Configuration ......................................................................................................................... 26-57
JPDF 125 V Power Distribution ....................................................................................................... 26-58
Installation ............................................................................................................................ 26-59
Operation .............................................................................................................................. 26-60
Specifications......................................................................................................................... 26-64
Diagnostics............................................................................................................................ 26-64
Configuration ......................................................................................................................... 26-64
JPDH High Density Power Distribution ............................................................................................. 26-65
Installation ............................................................................................................................ 26-66
Operation .............................................................................................................................. 26-67
Specifications......................................................................................................................... 26-68
Diagnostics............................................................................................................................ 26-68
Configuration ......................................................................................................................... 26-68
JPDL Local Pack Dc Power Distribution ............................................................................................ 26-69
Installation ............................................................................................................................ 26-69
Operation .............................................................................................................................. 26-70
Specifications......................................................................................................................... 26-71
Diagnostics............................................................................................................................ 26-71
Configuration ......................................................................................................................... 26-71
JPDM Power Distribution ............................................................................................................... 26-72
Installation ............................................................................................................................ 26-72
Operation .............................................................................................................................. 26-74
Specifications......................................................................................................................... 26-76
Diagnostics............................................................................................................................ 26-77
Configuration ......................................................................................................................... 26-77
JPDP Local Power Distribution ........................................................................................................ 26-78
Installation ............................................................................................................................ 26-78
Operation .............................................................................................................................. 26-79
Specifications......................................................................................................................... 26-80
Diagnostics............................................................................................................................ 26-80
Configuration ......................................................................................................................... 26-80
JPDS 28 V Power Distribution ......................................................................................................... 26-81
Installation ............................................................................................................................ 26-81
Operation .............................................................................................................................. 26-83
Specifications......................................................................................................................... 26-85
Diagnostics............................................................................................................................ 26-85
Configuration ......................................................................................................................... 26-85
JGND Shield Ground ..................................................................................................................... 26-86
Installation ............................................................................................................................ 26-86
Operation .............................................................................................................................. 26-88
Specifications......................................................................................................................... 26-88
Diagnostics............................................................................................................................ 26-88
Configuration ......................................................................................................................... 26-88
Vendor Manufactured Control Power Supplies .................................................................................... 26-89
Operation .............................................................................................................................. 26-90
PSFD Flame Detector Power Supply ................................................................................................26-101
Functional Description ............................................................................................................26-101
Installation ...........................................................................................................................26-102
Operation .............................................................................................................................26-103
Specifications........................................................................................................................26-104
Diagnostics...........................................................................................................................26-105
Configuration ........................................................................................................................26-105
Replacement/Warranty ................................................................................................. 27-1
Replacement................................................................................................................................... 27-1
Handling Precautions................................................................................................................. 27-1
Replacement Procedures ............................................................................................................ 27-2
Replacing Controller Components................................................................................................ 27-7
Renewal Warranty ........................................................................................................................... 27-8
How to Order a Board................................................................................................................ 27-8
Notes
Mark VIe Controllers (UCCx and UCSx)
Mark* VIe controllers are based on two different types of architecture. The
UCCx controller is based on CompactPCI® (CPCI) single board computers. The
UCSx controller is a series of stand-alone Modules.
UCCx Controller
The I/O networks are private The UCCx controllers are a family of CompactPCI® (CPCI), 6U high, single-board
special purpose Ethernet that computers that runs the application code. The controller mounts in a CPCI enclosure,
support only the I/O packs and communicates with the I/O packs through onboard I/O network interfaces. The
and the controllers. controller operating system (OS) is QNX® Neutrino®, a real-time, multitasking OS
designed for high-speed, high-reliability industrial applications. Five communication
ports provide links to I/O, operator, and engineering interfaces as follows:
• Ethernet connection for the Unit Data Highway (UDH) for communication
with HMIs, and other control equipment
• Ethernet connection for the R, S, and T I/O network
• RS-232C connection for setup using the COM1 port
Installation
If the slot 1 controller is The controller module contains (at a minimum) a controller and a four-slot CPCI rack with
removed, the other controllers either one or two power supplies. The primary controller must be placed in the left-most
will stop operating. slot (slot 1). A second, third, and fourth controller can be placed in a single rack.
The CMOS battery is disconnected using a processor board jumper during storage
to extend the life of the battery. When installing the board, the battery jumper must
be reinstalled. Refer to the specific UCCx module drawing for jumper location. The
battery supplies power to the CMOS RAM settings and the internal date and real-time
clock. There is no need to set CMOS settings since the settings are defaulted to the
proper values through the BIOS. Only the real-time clock must be reset. The initial date
and time can be set using a system NTP server or ToolboxST application.
If the board is the system board (slot 1 board) and other boards are in the rack,
ejection of the system board will cause the other boards to stop operating. It is
recommended that power be removed from the rack when replacing any board in the
rack. Rack power can be removed by one of the following methods.
• In a single power supply unit, a switch is provided to disable the power supply outputs.
• In a dual power supply unit, both power supplies can be safely ejected to remove power.
• Unplug the bulk power input Mate-N-Lok® connector(s) on the
bottom of the CPCI enclosure.
• Use a remote disconnect switch.
GEH-6721L Mark VIe Controllers (UCCx and UCSx) System Guide 1-1
Unlike the Mark VI VME boards that provided only ejectors, the UCCx module has
injectors/ejectors at the bottom and top of the module. Before sliding the board in
the rack, the top ejector should be tilted up and the bottom ejector should be tilted
down. When the connector on the backside of the board connects with the backplane
connector, the injectors should be used to fully insert the board. This is done by
pushing down on the top injector and pulling up on the bottom ejector. Remember to
finish the installation by tightening the top and bottom injector/ejector screws. This
provides mechanical security as well as a chassis ground connection.
Note Failing to lock the injectors will prevent the controller from booting. When
extracting the board, perform the insertion process in reverse. See the next section
on configuration before connecting the Ethernet cables. If a previous application is
loaded in the module, mis-operation can occur if the Ethernet addresses collide with
other operating equipment.
Operation
Control software can be The controller is loaded with software specific to its application, which includes
modified online without but is not limited to steam, gas, and land-marine aeroderivative (LM), or
requiring a restart. balance-of-plant (BOP) products. It can run rungs or blocks. The IEEE® 1588
protocol is used through the R, S, and T IONets to synchronize the clock of the
I/O packs and controllers to within ±100 micro seconds.
External data is transferred to and from the control system database in the
controller over the R, S, and T IONets.
In a simplex system, this includes process inputs/outputs to the I/O packs.
In a dual system:
• Process inputs/outputs to the I/O packs

• Internal state values and initialization information from the designated controller
• Status and synchronization information from both controllers
In a triple modular redundant (TMR) system:

• Internal state values from for voting and status and synchronization
information from all three controllers
• Initialization information from the designated controller
Configuration
The controller must be configured with a TCP/IP address prior to connecting to the UDH
Ethernet. This is achieved through the ToolboxST* application and the COM1 serial port.
1-2 Mark* VIe Control Vol. II System Hardware Guide

Controller Battery
The UCCx uses a lithium battery to supply power to the CMOS (which contains the
BIOS settings for the CPU board) and the real-time clock when the controller is not
on. Default CMOS settings are also stored in flash memory, so when the battery
reaches end-of-life, only the real-time clock functions are lost.
The lithium battery for the UCCx has a service life of 10 years. The battery is
disabled in stock and can be disabled when storing a controller. If the controller is
stored with the battery disabled, its life expectancy is 10 years, minus the time the
controller has been in service. If the controller is stored with the battery enabled,
the life expectancy drops to seven years minus the time the controller has been in
service. An expired battery can be replaced on the controller board.
¾ To replace the controller battery

1. Power down the CPCI rack. If the rack has a single power supply (version P1),
turn off the power switch located on the panel above the power supply.
2. Loosen the screws at the top and bottom of the controller.
3. Press down on the top ejector tab and pull up on the bottom ejector tab to disconnect
the controller from the backplane. Carefully pull the controller out of the CPCI rack.
4. Locate the battery near the top, inboard side of the controller.
5. Loosen the screw on the tab holding the battery and move it out of the way.
6. Slide the expired battery out of its enclosure, making note that the positive
(+) side faces away from the controller.
7. Insert the new battery. Reposition the holding tab and tighten the screw.
8. Slide the controller back into the CPCI rack and secure it in place.
9. Use the ToolboxST application to reset the real-time clock.
B attery
210 E 207 E209 E
1 206 E
E
+ +
P 11 P 12
J3
J2 +
J1
DS 3
DS 4
+ +
2
12
E
11
2E
UCCx Controller Battery

Cooling Fan
A cooling fan is located in a tray at the bottom of the CPCI rack. The cooling fan can
fail, causing temperatures to rise to a level that will damage the controllers and power
supplies. The cooling fan can be replaced without removing power to the rack.
Note The controller automatically monitors the CPU core temperature and can be
configured to continue to run, or to reboot the controller into a low power failure state.
See the help for the TEMP_STATUS function block for details.
¾ To replace the cooling fan

1. Loosen the two screws at the top of the door located at the bottom of CPCI rack.
2. Open the door and slide the old cooling fan out of the rack. There are no cables
to remove. The fan assembly plugs directly into the backplane.
3. Insert a new cooling fan into the guides in the compartment and push in firmly. If
the fan is not completely in place, the compartment door will not close.
4. Close the door and tighten the two screws at the top.
Cooling fan
compartment
Screws
Replacing CPCI Cooling Fan
EPMC
The CPCI controllers support a single PCI Mezzanine Card (PMC)
daughterboard called the IS200EPMC.
The IS200EPMC contains specific controller hardware functions as follows:
• Power supply monitoring

• Flash backed SRAM
• IONet Ethernets
• Ethernet physical layer packet snooping for precision time synchronization
The EPMC board plugs onto one of the PMC sites and communicates to the
processor board through the PCI bus. The PCI interface on the EPMC is PCI Rev
2.2 compliant and supports both 3.3 V and 5 V signal levels.
UCCA Processor
™
The IS215UCCAH3 is a single-slot board using a 650 MHz Intel® Celeron processor.
A 10BaseT/100BaseTX (RJ-45) Ethernet port provides connectivity to the Unit Data
Highway (UDH). There are two PCI Mezzanine Card (PMC) sites and a watchdog
timer. The processor board is the compute engine of the Mark VIe controller. The
IS215UCCAM03 is a module assembly that includes the IS215UCCAH3 combined
with 128 MB of flash memory, 128 MB of DRAM, and the IS200EPMC.
M
E
Z
Z
A
N
I
N
E
C
A
R
D
STAT LED (Reserved ) M STAT ON

ON LED
E
Z Green = controller online and
Z 3
running application code
A
IONet 3 ETHERNET T N 3
IONet Ethernet LEDs
2
I Green = 100 Base TX and full duplex
IONet 2 ETHERNET S N
IONet 1 ETHERNET R E
2
Blinking = Activity
1
C
OT LED (Reserved ) A O
1
T
R
Diag LED D DIAG DC
DC LED
Solid Red = Diagnostic available Green = Designated Controller
L
A UDH ETHERNET (UDH )
UDH Ethernet Status LEDs N
Active (Blinking = Active ) Primary Ethernet port for Unit Data
Speed (Yellow = 10 BaseT ) C Highway communication (ToolboxST )
O
( Green = 100 BaseTX ) M
1:2 COM 2 RS- 232 C Port Reserved
COM 1 RS232 C Port for
RST
Initial controller setup
S Status LEDs
System : When off , CPU is ready
IDE : Flash disk activity
Power : Lights when power is applied
+ Reset : Lights during reset condition
UCCA Front View

UCCAM03 Specifications
Item Specification
Microprocessor Intel Ultra Low Voltage Celeron 650 MHz (8.3 Watts Max.)
Memory 128 MB DDR SDRAM through one SODIMM
128 MB Compact Flash Module
256 KB L2 cache
Flash-backed SRAM - 8K allocated as NVRAM for controller functions
Operating System QNX Neutrino
Programming Control block language with analog and discrete blocks; Boolean logic
represented in relay ladder diagram format. Supported data types include:
Boolean
16-bit signed integer
16-bit unsigned integer
32-bit floating point
64-bit long floating point
Primary Ethernet interface (one port) TCP/IP protocol used for communication between controller and toolbox
TCP/IP protocol used for alarm communication to HMIs
EGD protocol for application variable communication with CIMPLICITY® HMI and
Series 90-70 PLCs
Ethernet Modbus® protocol supported for communication between controller
and third-party DCS
EPMC Ethernet Interface (three ports) Twisted pair 10BaseT/100BaseTX, RJ-45 connectors:
TCP/IP protocols used to communicate between controllers and I/O packs
COM ports Two micro-miniature 9-pin D connectors:
COM1 Reserved for diagnostics, 9600 baud, 8 data bits, no parity, 1 stop bit
COM2 Not used
For cabling use either:
a standard 4 pair UTP cable (e.g. Ethernet cable) joined with a PC null modem
connector (GE part #342A4931ABP1) and a controller connector (GE part
#342A4931ABP2) or a miniature D shell, null modem serial cable (GE part
#336A3582P1), connected with a micro-miniature pigtail (GE part #336A4929G1)
Environmental Specifications Temperature: Operating 0 to 60°C (32 to +140 ºF)
Temperature: Storage -40 to +85°C (-40 to +185 ºF)
Humidity: 5 to 95% non-condensing
Altitude: Operating 0 to 10,000 ft. (3,000 m)
Altitude: Storage 0 to 40,000 ft (12,000 m)
Power requirements +3.3 V dc, 3.5 A typical, 4.25 A maximum
+5 V dc, 150 mA typical, 300 mA maximum
UCCA Configuration
Airflow requirements as measured at the output side of

the heat sink must be greater than 400LFM to prevent
overheating and potential damage to the board.
Caution
CPU BOARD JUMPER SETTINGS
JUMPER NAME JUMPER FUNCTION JUMPER POSITION

JUMPER E206 CUSTOMER TO REPOSITION
JUMPER E206 SETTING E1 PASSWORD CLEAR 1-2
AS SHIPPED
TO ENABLE BATTERY E206 E204 ITP NO JUMPERS
E206
E206 BATTERY ENABLE 1 – 2 ***

E210, E211 FACTORY RESERVED
E212 DO NOT USE
E209 WATCHDOG TIMER 1–2
RESET ENABLE
E207 IGNORE CPCI 1-2
RESET
NO JUMPER E207 E209

E1
E210
JUMPER SYMBOL
0E2
1 0 7E2
9E2 0
E1
6E2
0
P11 P12
J3
J2
BACK
FRONT
J1
DS3
DS4
E212
E211
E212
E211
NO JUMPER
UCCA Controller Jumper Settings

UCCC Processor
The IS215UCCCH4 is a single-slot CPCI controller board containing a 1.6
GHz Pentium® M processor. Two 10/100/1000BaseTX Ethernet ports provide
connectivity to the UDH and an optional Ethernet network. The IS215UCCCM04
is a module assembly that includes the IS215UCCCH4 combined with 128 MB
of flash memory, 256 MB of DRAM, and the IS200EPMC.
UCCC Front View
UCCCM04 Specifications
Item Specification
Microprocessor Intel Pentium M processor 1.6 GHz
Memory 256 MB DDR SDRAM through one SODIMM
128 MB Compact Flash Module
256 KB L2 cache
Programming Control block language with analog and discrete blocks; Boolean logic represented
in relay ladder diagram format. Supported data types include:
Boolean
Primary Ethernet Interface (2) Twisted pair 10BaseT/100BaseTX, RJ-45 connectors:
TCP/IP protocol used for communication between controller and toolbox
EGD protocol for application variable communication with CIMPLICITY HMI and
Series 90-70 PLCs
Ethernet Modbus protocol supported for communication between controller and
third party DCS
EPMC Ethernet Interface (3 ports) Twisted pair 10BaseT/100BaseTX, RJ-45 connectors:
COM ports One accessible through RJ-45 connector on front panel
For cabling use a standard 4 pair UTP cable (such as, Ethernet cable) joined with
a PC null modem connector (GE part #342A4931ABP1)
Power Requirements +5 V dc (+5%, -3%, 4.5 A (typical), 6.75 maximum)
+3.3 V dc, (+5%, -3%, 1.5 A (typical), 2.0 A maximum)
+12 V dc (+5%, -3%), 50 mA maximum
-12 V dc (+5%, -3%), 50 mA maximum
Environmental Specifications Operating: 0 to +50°C (32 to +122 °F)
Storage: -40 to +85°C (-40 to +185 °F)
Relative humidity: 5% to 95%, no-condensing
Mechanical Specifications Shock: 10 Gs, 16 ms half sine, 6 axis, 10 pulses each
Vibration: 6 Gs rms (20-2000 Hz) random, 0.0185 G2 per Hz

UCCC Configuration
Airflow requirements as measured at the output side of

the heat sink must be greater than 300LFM to prevent
overheating and potential damage to the board.
Caution
UCCC Jumper Location and Settings
CPCI Control Module
The CPCI control module rack provides an enclosure for the controller, an enclosure
for the power supplies(s), and a cooling system. The rack backplane is only used
to connect the power supplies to the controller and cooling fans.
Installation
The CPCI rack is designed to be wall-mounted. Use the following drawing to determine
the placement of the mounting hardware and the enclosure space required.
2.32 cm
(0.80 in) 9.04240 cm
(3.56 in) 23.4188 cm
(9.22 in)
R 0.1 0 24
0.55880 cm
(0.22 in)
37.2110 cm 38.9382 cm
(14.65 in) (15.33 in)
0.50800 cm
(0.20 in)
0.99060 cm
(0.39 in)
9.04240 cm 22.7330 cm
(3.56 in) (8.95 in)
2.32 cm 13.1064 cm
(0.80 in) (5.16 in)
Power supply connector pin definitions

P1 = ac line or dc-
P2 = ac neutral or dc+
P3 = GND
The plug connector is AMP# 350550-7 or equivalent with

receptacle connector AMP#250766-1 or equivalent contacts.
Bulk Input power connector

Operation
Bulk incoming power is supplied to the rack using one or two power connectors. The
CPCI power supply converts the bulk input to ±12 V dc, 5 V dc, and 3.3 V dc. These
voltages are distributed to the controllers and fans through the backplane.
The following rack parts are available.
Catalog # # Power Supplies Ports Power Inputs

336A4940CTP1 1 1
336A4940CTP2 2 2
23.4188 cm 23.4188 cm
(9.22 in) (9.22 in)
34.4454 cm 38.9382 cm
(13.56 in) 34.4454 cm
(15.33 in)
(13.56 in)
13.1064 cm 13.1064 cm
(5.16 in) Right Side View (5.16 in) Right Side View
Front View Front View
23.4188 cm
(9.22 in)
Bottom View Bottom View
Part 1 (Single Power Supply) Part 2 (Dual Power Supply)
The P1 version contains a on/off switch located in the upper right panel. The
switch is connected to the disable outputs pin of the power supply, which turns
off power to the controllers and fans. The P2 version does not have a switch so
power is removed by ejecting the power supplies, disconnecting the incoming
bulk power plugs or using a remote disconnect.
Specifications
Item Specification
Environment Temperature: Operating 0 to +65ºC (+32 to +149 ºF)
Temperature: Storage - 40 to +85ºC (-40 to +185 ºF)
Altitude: Storage 0 to 50,000 ft
Air flow provided 300 linear feet per minute
Codes and Standards UL 508A Safety Standard Industrial Control Equipment
CSA 22.2 No. 14 Industrial Control Equipment Class 1 Division 2
EN 61010-1 Safety of Electrical Equipment, Industrial Machines
IEC 529 Intrusion Protection Codes/NEMA 1/IP 20
CPCI Component Replacement

The following sections provide replacement procedures for the CPCI control module.
¾ To replace the CPCI controller

1. Power down the CPCI rack. If the rack has a single power supply (version
P1), turn off the power switch located on the panel above the power supply.
The power can also be removed by disconnecting the bulk power plug from
the bottom of the rack or by using a remote disconnect.
2. When two power supplies are used (version P2), loosen the top and bottom screw on
each one. Press down the red tab in the black release lever on each power supply.
Press down on the black release lever and pull out to disconnect both power supplies
from the CPCI rack backplane. The power can also be removed by disconnecting the
bulk power plugs from the bottom of the rack or by using a remote disconnect.
3. Loosen the screws at the top and bottom of the controller.
4. Press down on the top ejector tab and pull up on the bottom ejector tab to disconnect
the controller from the backplane. Carefully pull the controller out of the CPCI rack.
5. Carefully slide the new controller module into the CPCI enclosure.
6. Press up on the top injector/ejector tab and push down on the bottom injector/ejector
tab to seat the controller connectors with the receptacles on the backplane.
7. Tighten the screws at the top and bottom of the controller, securing
it in the CPCI enclosure.
8. Power up the controller by turning on the power switch on CPCI enclosure
with a single power supply or pushing in on both power supplies and securing
them on a CPCI enclosure using dual supplies.
9. Configure controller with TCP/IP address prior to connecting the UDH Ethernet
cable. This is done using the ToolboxST application and COM1 serial port.
10. Connect the UDH Ethernet cable to the LAN port. Connect the three IONet
Ethernet cables to the appropriate receptacles.

Main processor board
QNX operating system
UDH Ethernet connections
IONET 100 MB Ethernet
Power supply
on / off switch
Power supply
Cooling fan compartment
CPCI Controller
Power Supply(s)
The CPCI power supply takes the incoming bulk power from the CPCI rack and
creates ±12, 5, and 3.3 V dc. This power is provided to the backplane for use
in the rack, mainly for the controller(s) and cooling fan.
The CPCI rack can hold one or two power supplies. The power supplies plug directly
into the backplane using CPCI 47-pin connector. The power supply(s) are hot swap
compliant and can be safely removed with powering down CPCI rack.
Installation
¾ To remove the CPCI power supply(s)
1. Loosen the two screws holding the power supply in the rack. The bottom screw is
located beneath the black ejection lever at the bottom of the power supply faceplate.
2. Press down on the red tab inside the black ejection lever to release it.
3. Push the black release lever down to unplug the power supply from the backplane.
4. Slide the power supply out of the CPCI rack.
¾ To install a new CPCI power supply(s)

1. Slide the new power supply(s) into CPCI rack. Ensure the front of the power
supply is flush with other components in the enclosure.
2. Push the black ejection lever up. The red tab in the black ejection lever
will snap up when the power supply is fully inserted.
3. Tighten the top and bottom screws.
Black release
lever
Top screw
Red tab
Bottom screw
Replacing CPCI Power Supply

Operation
The power supply is a CPCI Rev 2.11 hot swap compliant 3U power supply using
the standard Positronics® 47-pin connector. Remote sense and active current
share on the +5 and +3.3 V dc outputs along with o-ring FETs allow it to be
used in the dual power supply CPCI rack. The ±12 V dc outputs use regular
o-ring diodes for parallel operation in the dual rack.
The following power supply is supported.
Catalog # Input Voltage

342A4920 20-36 V dc
LEDs
The 20-36 V dc power supply has the following LEDs:
• Power: Solid green if all power supply outputs are OK. The LED
will turn off on any output failure.
• Alarm: Solid red if one or more of the outputs have failed.
Specifications
Item Specification
Environment Temperature: Operating 0 to +65°C (+32 to +149 ºF)
Temperature: Storage -40 to +85°C (-40 to +185 ºF)
Altitude: Storage 0 to 50,000 ft
Vibration: Random vibration 10 Hz to 2 kHz, 3 axis (1 GRMS)
Incoming power 20-36 V dc
Output power 150 W (De-rated for 65 C operation and 10,000 ft altitude)
Over temperature protection System shut down due to excessive internal temperature, automatic reset
Over voltage protection Latch style over-voltage protection
(110% minimum to 130% of V nom)
Overload protection Fully protected against output overload and short circuit. Automatic recovery upon
removal of overload condition
Agency Approvals UL 1950, UL 1950, EN60950 (TUV)
Dielectric withstand voltage Input to output per EN60950 (minimum 1500 V dc)
ESD susceptibility Per EN61000-4-2, level 4 (minimum 8 kV)
Radiated Susceptibility Per EN61000-4-3, level 3 (minimum 10 V/M)
EFT Burst Per EN61000-4-4, level 3 (minimum ±2 kV)
Input Surge Per EN61000-4-5, level 3. (Line to Line minimum 1 kV) (Line to Ground minimum 2 kV)
Conducted Disturbance Per EN61000-4-6, level 2 (maximum 3 V)
Insulation Resistance Input to Output (Nominal 10 M Ω)
Power Supply Replacement
¾ To replace the CPCI power supply(s)
1. Loosen the two screws holding the power supply in the rack. The bottom screw is
located beneath the black ejection lever at the bottom of the power supply faceplate.
2. Press down on the red tab inside the black ejection lever to release it.
3. Push the black release lever down to unplug the power supply from the backplane.
4. Slide the power supply out of the CPCI rack.
5. Slide the new power supply(s) into the CPCI rack. Ensure the front of the power
supply is flush with the other components in the enclosure.
6. Push the black ejection lever up. The red tab in the black ejection lever
will snap up when the power supply is fully inserted.
7. Tighten the top and bottom screws.
Black release
lever
Top screw
Red tab
Bottom screw
Replacing CPCI Power Supply

UCSx Controller
The I/O networks are private The Mark* VIe UCSx controllers are a family of stand-alone computer that runs the
special-purpose Ethernet that application code. The controller mounts in a panel, and communicates with the I/O
support only the I/O packs packs through on-board I/O network interfaces. The controller operating system
and the controllers. (OS) is QNX® Neutrino®, a real time, multitasking OS designed for high-speed,
high-reliability industrial applications. Five communication ports provide links
to I/O, operator, and engineering interfaces are as follows:
• Ethernet connection for the Unit Data Highway (UDH) for communication
with HMIs, and other control equipment
• Ethernet connection for the R, S, and T I/O network
• RS-232C connection for setup using the COM1 port
The stand-alone controllers offer the following advantages over the

Compact PCI and Mark VIe controllers.
• Single module
• Built-in power supply
• No jumper settings required
• No battery
• No fan
• Smaller panel footprint
• Easy access to CompactFlash™
Installation
The controller is contained in a single module that mounts directly to the panel sheet
metal. The following diagram shows the module envelope and mounting dimensions.
28 V DC INPUT POWER
CONNECTOR MICRO-MINI
MATE-N-LOK Note:
1. ALL DIMENSIONS IN INCHES
2. WEIGHT OF ASSEMBLY = 2 LBS
3. UCSA ASSEMBLY TO BE MOUNTED TO
FLASH DISK PANEL AS SHOWN. (VERTICAL AIR FLOW
THROUGH FINS TO BE UNOBSTRUCTED)
.965
1.544
.230 .465
6.305
0.228 1.045
SEE DETAIL A .250
0.450
.339
DETAIL A
SCALE 2/1
8.011
7.563
0.228
SEE DETAIL B
.218
.465
DETAIL B FRONT VIEW
SCALE 2/1 SCALE 3/4
Module Envelope and Mounting Dimensions

Operation
Application software can The controller is loaded with software specific to its application, which includes
be modified online without but is not limited to, steam, gas, wind, hydro, and land-marine aeroderivative
requiring a restart. (LM), or balance of plant (BoP) products. It can run rungs or blocks. The IEEE®
1588 protocol is used through the R, S, and T IONets to synchronize the clock of
the I/O packs and controllers to within ±100 microseconds.
External data is transferred to and from the control system database in the
controller over the R, S, and T IONets.
In a simplex system, this includes process inputs/outputs to the I/O packs.
In a dual system:

• Internal state values and initialization information from the designated controller
• Status and synchronization information from both controllers
In a triple modular redundant (TMR) system:

• Internal state values for voting and status, and synchronization
information from all three controllers
• Initialization information from the designated controller
UCSA Module
The IS220UCSAH1+ Module contains a 667 MHz Power QUICC II Pro Freescale
processor. Two 10/100BaseTX Ethernet ports provide connectivity to the UDH, and three
additional 10/100Base TX Ethernet ports provide connectivity to the IONets.
GE Energy
Link
T/
Act SL3
Link
S/
Act SL2
Link R/
SL1
Act
Power
Boot
OnLine
Flash
DC
Diag
Link
ENET 1
Act
Link
ENET 2
Act
On USB
COM
UCSA Front View

LEDs
The UCSA module has the following LEDs:
• Link displays solid green if the Ethernet PHY on the UCSA has established
a link with an Ethernet switch port.
• Act indicates packet traffic on an Ethernet interface. This LED may blink
if the traffic is low, but is solid green in most systems.
• Power displays solid Green when the internal 5 V supply is up and
regulating. The UCSA converts the incoming 28 V dc to 5 V dc. All other
internal power planes are derived from the 5 V.
• Boot displays solid red or blinking red during the boot process. The
boot blink codes are described below.
− Online displays solid green when the controller is online and
running application code.
− Flash blinks amber when any flash device is being accessed.
− Dc displays solid green when the controller is the designated controller.
− Diag displays solid red when the controller has a diagnostic available. The
diagnostic can be viewed and cleared using the ToolboxST application.
− On displays solid green when the USB is active.
Boot LED Flashing Codes
Refer to GEH-6700, ToolboxST The boot LED is lit continuously during the boot process unless an error is
User Guide for Mark* detected. If an error is detected, the LED flashes at a 1 Hz frequency. The LED,
VIe Control, the section when flashing, is on for 500 ms and off for 500 ms. The LED turns off for three
Downloading to a Controller. seconds. The number of flashes indicates the failed state.
The flashing codes are:
• 1: Failed Serial Presence Detect (SPD) EEPROM.

• 2: Failed to initialize DRAM or DRAM tests failed.
• 3: Failed NOR flash file system check.
• 4: Failed to load FPGA or PCI failed.
• 5: Compact Flash device not found.
• 6: Failed to start IDE driver
• 7: Compact Flash image not valid.
If the CompactFlash image is valid but the runtime firmware has not been loaded,
the boot LED flashes continuously at a 1 Hz rate. Once the firmware is loaded,
the boot LED turns off. If the controller does not go online, use the ToolboxST
application to determine why the controller is blocked. Once an IP address has
been assigned, ToolboxST uses the Ethernet for configuration.
UCSA Specifications
Item Specification
Microprocessor Freescale Power pc (Power QUICC II PRO 667 MHz)
Memory 256 MB DDR SDRAM
CompactFlash size is dependent on the application.
Programming Control block language with analog and discrete blocks; Boolean logic represented
in relay ladder diagram format. Supported data types include:
Boolean
Primary Ethernet Interface (2) Twisted pair 10BaseT/100BaseTX, RJ-45 connectors:
TCP/IP protocol used for communication between controller and toolbox
EGD protocol for application variable communication with CIMPLICITY® HMI and
Series 90-70 PLCs
Ethernet Modbus® protocol supported for communication between controller and
third-party DCS
IONet Ethernet Interface (3 ports) Twisted pair 10BaseT/100BaseTX, RJ-45 connectors:
COM ports One accessible through RJ-45 connector on front panel
For cabling use a standard 4-pair UTP cable (for example, Ethernet cable) joined
with a computer null modem connector (GE part #342A4944P1)
Power Requirements +32 V dc to 18 V dc (12.5 W (typical preliminary), TBD (maximum))
Environmental Specifications Operating: 0 to +65°C (32 to +149 °F)
Storage: -40 to +85°C (-40 to +185 °F)
Relative humidity: 5% to 95%, no-condensing
Weight 2 lbs

Configuration
The controller must be configured with a TCP/IP address prior to connecting to the
UDH Ethernet. This can be achieved using one of the following methods.
• Through the ToolboxST* application and the COM1 serial port. See GEH-6700,
ToolboxST Guide for Mark VIe Control for details. A RJ45 to DB9 adapter is required
along with an Ethernet cable. The adapter part number is 342A4944P1.
• Through the ToolboxST application and a CompactFlash™ programmer. See
GEH-6700, ToolboxST Guide for Mark VIe Control for details. The CompactFlash
programmer can be a PCMCIA adapter or a USB device.
The following drawing shows the pin definition of the UCSx RJ45 to the COM port adapter.
Converter
DB 9
RJ45 Female
1 DCD
GND 1 White/Orange 1 Blue
Red 2 RXD
RTS 2 Orange 2
Brown 3 TXD
GND 3 White/Green 3
UCSA TXD/Sout 4 Blue 4
4 DTR
RJ-45 Black 5 GND
NC 5 White Blue 5 Green
6 DSR
CTS 6 Green 6 Yellow 7 RTS
RXD/Sin 7 White/Brown 7 Orange 8 CTS
NC 8 Brown 8 Grey
9 RI
Once the IP address has been assigned, all ToolboxST configuration is through the
Ethernet. See GEH-6700, ToolboxST Guide for Mark VIe Control for further details.
Notes

PAIC Analog Input/Output Module
Analog Input/Output (PAIC)

Functional Description
The Analog Input/Output (PAIC) pack provides the electrical interface between one
ANALOG/IN OUT
PWR
or two I/O Ethernet networks and an analog input terminal board. The pack contains
a processor board common to all Mark* VIe distributed I/O packs and an acquisition
ATTN
board specific to the analog input function. The pack is capable of handling up to 10
analog inputs, the first eight of which can be configured as ±5 V or ±10 V inputs, or 0-20
LINK mA current loop inputs. The last two inputs may be configured as ±1 mA or 0-20 mA
ENET1
TxRx current inputs. The load terminal resistors for current loop inputs are located on the
terminal board and voltage is sensed across these resistors by the PAIC. The PAICH1
LINK
also includes support for two 0-20 mA current loop outputs. The PAICH2 includes extra
ENA1 ENET2
hardware to support 0-200 mA current on the first output.
TxRx
ENA2
IR PORT
Input to the pack is through dual RJ45 Ethernet connectors and a three-pin power input.
Output is through a DC-37 pin connector that connects directly with the associated
terminal board connector. Visual diagnostics are provided through indicator LEDs.
Note The infrared port is not used.

IS220PAICH1A
GEH-6721L PAIC Analog Input/Output Module System Guide 2-1

PAICH1A
Analog Input BPPB
BPAIH1A Module processor board
board
Single or dual
Ethernet cables
ENET1
TBAI Analog Input
Terminal Board
ENET2
External 28 V dc
power supply
Analog Inputs (10)
Analog Outputs (2) ENET1
ENET2
28 V dc
Three PAIC modules for TMR ENET1

One PAIC module for Simplex
ENET2
No Dual control available
28 V dc
PAIC Block Diagram
Compatibility
PAICH1A is compatible with the analog input terminal board (TBAIHIC), and
the STAI board, but not the DIN rail-mounted DTAI board. The following
table gives details of the compatibility:
Terminal Board TBAIH1C DTAI STAIH1A

Control mode Simplex-yes Dual - no TMR-yes No Simplex-yes
Control mode refers to the number of I/O packs used in a signal path:
• Simplex uses one I/O pack with one or two network connections.
• Dual uses two I/O packs with one or two network connections.
• TMR uses three I/O packs with one network connection on each pack.
While the PAIC will mount on a TBAIH1A or TBAIH1B terminal board the pack will not
realize full accuracy of the analog signals due to circuit differences between the terminal
board revisions. For this reason, the PAIC is only compatible with the H1C version of
TBAI and will report a board compatibility problem with any of the earlier revisions. No
physical damage will result if a PAIC is powered up on an older board in error.

Installation
¾ To install the PAIC pack
1. Securely mount the desired terminal board.
2. Directly plug the PAIC I/O pack into the terminal board connectors.
3. Mechanically secure the packs using the threaded studs adjacent to the Ethernet
ports. The studs slide into a mounting bracket specific to the terminal board type.
The bracket location should be adjusted such that there is no right-angle force
applied to the DC-37 pin connector between the pack and the terminal board. The
adjustment should only be required once in the life of the product.
Note The PAIC mounts directly to a Mark VIe terminal board. Simplex terminal
boards have a single DC-37 pin connector that receives the PAIC. TMR-capable
terminal boards have three DC-37 pin connectors and can be used in simplex mode if
only one PAIC is installed. The PAIC directly supports all of these connections.
4. Plug in one or two Ethernet cables depending on the system configuration. The pack
will operate over either port. If dual connections are used, the standard practice is
to connect ENET1 to the network associated with the R controller.
5. Apply power to the pack by plugging in the connector on the side of the pack. It is not
necessary to remove power from the cable before plugging it in because the I/O pack
has inherent soft-start capability that controls current inrush on power application.
6. Use the ToolboxST* application to configure the I/O pack as necessary.
See also the Auto-Reconfiguration section
If the configuration being downloaded contains I/O

packs with different module IDs than the configuration
currently running, the download may install incorrect
firmware to some I/O packs. If this occurs, make sure the
controller is running the new configuration, restart the
Attention entire system, and then start the ToolboxST Download
Wizard again.

Operation
Processor
The processor board is common to all Mark VIe Ethernet I/O packs
or modules. It contains the following:
• High-speed processor with RAM and flash memory

• Two fully independent 10/100 Ethernet ports with connectors
• Hardware watchdog timer and reset circuit
• Internal temperature sensor
• Status-indication LEDs
• Electronic ID and the ability to read IDs on other boards
• Input power connector with soft start/current limiter
• Local power supplies, including sequencing and monitoring
The processor board connects to an acquisition board specific to the I/O pack or
module function. Upon application of input power, the soft-start circuit ramps up the
voltage available on the processor board. The local power supplies are sequenced
on, and the processor reset is removed. The processor completes self-test routines
and then loads application code specific to the I/O pack or module type from flash
memory. The application code reads board ID information to ensure the correct
matching of application code, acquisition board, and terminal board. With a good match,
the processor attempts to establish Ethernet communications, starting with request
of a network address. The address request uses the industry standard dynamic host
configuration protocol (DHCP) and the unique identification read from the terminal
board. After Ethernet initialization, the processor programs the on-board logic, runs
the application, and enables the acquisition board to begin operation.
The processor application code contains all the logic necessary to allow the I/O pack
to operate from one or two Ethernet inputs. When operated from two Ethernet inputs,
both network paths are active all the time. A failure of either network will not result in
any disturbance to the I/O pack or module operation, and the failure will be indicated
through the working network connection. This arrangement is more tolerant of faults
than a classic hot-backup system where the second port is only used after a primary port
failure is detected. The Ethernet ports on the processor auto-negotiate between 10 MB/s
and 100 MB/s speed, and between half-duplex and full-duplex operation.

Auto-Reconfiguration
The Auto-Reconfiguration The Auto-Reconfiguration feature allows I/O packs to be replaced without the operator
feature first became available having to manually reconfigure each pack or module. If the Auto-Reconfiguration
with the ControlST* V03.05 feature is enabled, when the controller detects an I/O pack booting with a different
software release. configuration, a reconfiguration file is automatically downloaded from the controller
to the I/O pack. This reconfiguration includes the bootload, baseload, firmware, and
parameters. Each I/O pack is updated with the current configuration that matches the
configuration used by the controller, unless it already contains the latest version.
Refer to GEI-100694, While an Auto-Reconfiguration is in progress, the controller will not allow a reboot
ControlST Upgrade until after the Auto-Reconfiguration has finished. Other downloads to the I/O pack
Instructions for more cannot be initiated while it is being Auto-Reconfigured. If an I/O pack is already
information. running, Auto-Reconfiguration only performs diagnostics.
Auto-Reconfiguration is enabled or disabled in the ToolboxST application through the

Component Editor. This allows the operator to manually reconfigure each pack or module
if necessary. The Auto-reconfiguration of terminal boards and controllers is not supported.
If a terminal board is replaced, the I/O pack must be manually reconfigured.
Refer to GEH-6700, Install or replace the I/O pack in accordance with the procedure in the Installation
ToolboxST* for Mark* VIe section. When power is applied, the I/O pack boots up and the Auto-Reconfiguration
Control for more information. process starts. It generates a signal to the controller to indicate it needs an IP address and
configuration. The controller queries the I/O pack to identify existing files to determine
if a reconfiguration is needed. The controller then starts to download the IP address
and reconfiguration files. The controller signals the I/O pack when the download is
complete. The I/O pack reboots, performs a self-diagnostic test, and goes online.
Note When replacing an I/O pack with a new one that has a similar file structure
(a current revision with another current revision) the Auto-Reconfiguration process
takes a relatively short amount of time. When the file structure of the replacement I/O
pack varies from the one being replaced (a current revision with an older revision), the
Auto-Reconfiguration process takes a longer time to complete.

Status LEDs
Processor LEDs
Color Label Description

Green PWR Shows the presence of control power
Green LINK Provided for each Ethernet port to indicate if a valid Ethernet connection is
present
Yellow TxRx Provided for each Ethernet port to indicate when the pack or module is
transmitting or receiving data over the port
Red / Green ATTN Shows I/O pack or module status
LED Status
LED Flashing Pattern Description Software Version

Red LED out There are no detectable problems with the I/O pack or module. All
ATTN
LED solid on A critical fault is present that prevents the I/O pack or module from 3.04 or earlier
operating. There could be hardware failures on the processor or
acquisition boards, or there is not any application code loaded.
4 Hz 50% An alarm condition is present in the pack or module. These alarms
include wrong processor / terminal board combination, terminal
board is missing, or errors in loading the application code.
1.5 Hz 50% The I/O pack or module is not online.
0.5 Hz 50% This is used during factory testing to draw attention to the pack
or module.
Red Solid Booting - prior to reading Dallas ID 3.05 or later
ATTN
4 Hz 50% Diagnostic present
2 Hz 50% Awaiting an IP address
1 Hz 50% No Firmware to load (Program mode)
0.5 Hz 50% Application not loaded
Green Solid BIOS (at power on), but if it remains in this state, the I/O pack or
ATTN module Is not functioning properly and should be replaced.
2 Hz 50% Awaiting Auto-Reconfiguration release
1 Hz 50% In WAIT or STANDBY mode
Two 4 Hz flashes Application online
every 4 sec

Analog Input Hardware
The PAIC accepts input voltage signals from the terminal board for all 10 input channels.
The analog input section consists of an analog multiplexer block, several gain and
scaling selections, and a 16-bit analog-to-digital converter (DAC).
PAIC Analog Input Module
Terminal
M u l ti p le x o r
Board Analog to
Analog Digital
Inputs Converter
16-bit
10-Inputs
Ethernet
Processor
communications
Terminal
Board Digital to
Analog Analog
Linear
Outputs Output Converter
Drive 14-bit
2-Outputs
The inputs can be individually configured as ±5 V or ±10 V scale signals, depending

on the input configuration. The terminal board provides a 250 Ω burden resistor
when configured for current inputs yielding a 5 V signal at 20 mA. These analog
input signals are first passed through a passive, low pass filter network with a pole at
75.15 Hz. Voltage signal feedbacks from the analog output circuits and calibration
voltages are also sensed by the PAIC analog input section.

Analog Output Hardware
The PAIC includes two 0-20 mA analog outputs capable of 18 V compliance running
simplex or TMR. A 14-bit DAC commands a current reference to the current regulator
loop in the PAIC that senses current both in the PAIC pack and on the terminal board. In
TMR mode, the three current regulators in each PAIC share the commanded current loads
among themselves. Analog output status feedbacks for each output include:
• Current reference voltage

• Individual current (output current sourced from within the PAIC)
• Total current (as sensed from the terminal board, summed current in TMR mode)
PAIC Analog Input Pack TBAI Terminal Board Max.

Suicide Load
D/A ENA Relay Noise
Current TMR 800
14-bit Suppr-
From Regulator/ Junction ession ohms
Processor Power Driver
Analog
Current Fdbk Sensing Output
Total Current Sensing

Feedback
Output section of board

Other
modules
DC-37
Connector
Each analog output circuit also includes a normally open mechanical relay to enable or
disable operation of the output. The relay is used to remove a failed output from a TMR
system allowing the remaining two PAICs to create the correct output without interference
from the failed circuit. When the suicide relay is de-activated, the output opens through the
relay, open-circuiting that PAIC's analog output from the customer load that is connected to
the terminal board. The mechanical relay’s second normally open contact is used as a status
to indicate position of the relay to the control and includes visual indication with an LED.
Optional Hardware
The PAIC includes support for additional hardware in the form of an add-on
daughterboard that adds 0-200 mA output capability to the first analog output,
analog output #1. The 200 mA circuit is capable of 9 V compliance and is identical
to the diagram shown with the exception of the P28 power source. Power for the
200 mA circuit is derived from a variable voltage source on the daughterboard
to reduce power dissipation of the linear output transistor.
When configured for 200 mA mode operation, the 20 mA suicide relay is automatically
opened and the 200 mA suicide relay on the optional daughterboard is closed.

ID Line
The processor board and acquisition board within the I/O pack contain electronic ID
parts that are read during power initialization. A similar part located with each terminal
board DC-37 pin connector allows the processor to confirm correct matching of I/O pack
to terminal board and report board revision status to the system level control.
Power Management
The I/O pack includes power management in the 28 V input circuit. The management
function provides soft start to control current inrush during power application. After
applying power, the circuit provides a fast current limit function to prevent a pack or
terminal board failure from propagating back onto the 28 V power system. When power is
present and working properly, the green PWR LED indicator will be lit. After the current
limit function operates, PWR LED will remain unlit until the problem is resolved.
Connectors
The pack contains the following connectors:
• A DC-37 pin connector on the underside of the I/O pack connects directly to
the discrete input terminal board. The connector contains the 24 input signals,
ID signal, relay coil power, and feedback multiplex command.
• An RJ45 Ethernet connector named ENET1 on the side of the pack
is the primary system interface.
• A second RJ45 Ethernet connector named ENET2 on the side of the pack
is the redundant or secondary system interface.
• A 3-pin power connector on the side of the pack is for 28 V dc
power for the pack and terminal board.
Compressor Stall Detection

PAIC firmware includes gas turbine compressor stall detection, executed at 200 Hz. Two
stall algorithms can be selected. Both use the first four analog inputs, scanned at 200 Hz.
One algorithm is for small LM gas turbines and uses two pressure transducers (refer to
the figure, Small (LM) Gas Turbine Compressor Stall Detection Algorithm). The other
algorithm is for heavy-duty gas turbines and uses three pressure transducers (refer to
the figure, Heavy Duty Gas Turbine Compressor Stall Detection Algorithm).
Real-time inputs are separated from the configured parameters for clarity. The parameter
CompStalType selects the type of algorithm required, either two transducers or three. PS3
is the compressor discharge pressure. A drop in this pressure (PS3 drop) indicates possible
compressor stall. The algorithm also calculates the rate of change of discharge pressure,
dPS3dt, and compares these values with configured stall parameters (KPS3 constants).
The compressor stall trip is initiated by PAIC, which sends the signal to the controller
where it is used to initiate a shutdown. The shutdown signal can be used to set
all the fuel shut-off valves (FSOV) through any relay output.

Input VAIC, 200 Hz scan rate *Note: where x, y, represent any two Signal Space
Config of the input circuits 1 thru 4. Inputs
Input, cctx* param.
AnalogInx*
Scaling
Low_Input, Low_Value,
High_Input, High Value 4
Sys Lim Chk #1
SysLim1Enabl, Enabl SysLimit1_x*
4
SysLim1Latch, Latch
SysLim1Type, >=
SysLimit1, xxxx
ResetSys, VCMI, Mstr Sys Lim Chk #2
4 SysLimit2_x*
SysLim2Enabl, Enabl AnalogIny*
SysLim2Latch, Latch
SysLimit1_y*
SysLim2Type, <=
SysLimit2, xxxx SysLimit2_y*
Validation & Stall Detection

CompStalType two_xducer PS3B_Fail
OR PS3A_Fail OR
Input Circuit Selection PS3A PS3B
InputForPS3A eg. AnalogIn2
InputForPS3B PS3A_Fail
eg. AnalogIn4 PS3_Fail
PS3B_Fail AND
PS3A A
|A-B| A
PS3B DeltaFault
B A>B
PressDelta B
PS3Sel Selection Definition
If PS3B_Fail & not PS3A_Fail
SelMode Max then PS3Sel = PS3A;
ElseIf PS3A_Fail & not PS3B_Fail
PS3A then PS3Sel = PS3B;
ElseIf DeltaFault
then PS3Sel = Max (PS3A, PS3B)
PS3B ElseIf SelMode = Avg PS3Sel PressSel
then PS3Sel = Avg (PS3A, PS3B)
PS3A_Fail ElseIf SelMode = Max
then PS3Sel = Max (PS3A, PS3B) d DPS3DTSel
__
Else
PS3B_Fail then PS3SEL = old value of PS3SEL dt PressRateSel
-DPS3DTSel
-1 X
TimeDelay
-DPS3DTSel TD
KPS3_Drop_Mx PS3_Fail
KPS3_Drop_Mn
KPS3_Drop_I A Mid A AND
KPS3_Drop_S A+B A>B
X B B
z-1
stall_timeout
PS3i
PS3Sel X stall_set
KPS3_Delta_S AND S
A
delta_ref CompStall
KPS3_Delta_I A+B MIN Latch
B A R
stall_delta
KPS3_Delta_Mx delta AB AND
B PS3Sel BA-B stall_permissive
CompStalPerm
MasterReset, VCMI, Mstr
Small (LM) Gas Turbine Compressor Stall Detection Algorithm

Input VAIC, 200 Hz scan rate *Note: where x, y, z, represent any
Signal Space
Config. three of the input circuits 1 thru 4. inputs
param. Scaling
Input, cctx* AnalogInx*
Low_Input, Low_Value,
High_Input, High Value 4 Sys Lim Chk #1
SysLim1Enabl, Enabl SysLimit1_x*
4
SysLim1Latch, Latch
SysLim1Type, >=
SysLimit1, xxxx
ResetSys, VCMI, Mstr
Sys Lim Chk #2
4 SysLimit2_x*
SysLim2Enabl, Enabl
AnalogIny*
SysLim2Latch, Latch SysLimit1_y*
SysLim2Type, <=
SysLimit2_y*
SysLimit2, xxxx
AnalogInz*
SysLimit1_z*
SysLimit2_z*
Stall Detection
CompStalType
three_xducer
not used DeltaFault

Input Circuit Selection
InputForPS3A
eg. AnalogIn1
InputForPS3B
eg. AnalogIn2
InputForPS3C
eg. AnalogIn4
PS3C
PS3B MID PS3Sel, or CPD PressSel
PressDelta not used PS3A SEL
d DPS3DTSel
__
SelMode not used dt PressRateSel
-DPS3DTSel
-1 X
TimeDelay
TD
-DPS3DTSel
KPS3_Drop_Mx
KPS3_Drop_Mn
KPS3_Drop_I MID A
A
KPS3_Drop_S A+B A>B
X B B
z-1
stall_timeout
PS3i
PS3Sel X stall_set
KPS3_Delta_S S
A AND CompStall
A+B delta_ref Latch
KPS3_Delta_I MIN stall_
B A
KPS3_Delta_Mx delta R
delta AB PS3i_Hold A
B AND A-B
PS3Sel stall_permissive
B
CompStalPerm
MasterReset, VCMI, Mstr
Heavy Duty Gas Turbine Compressor Stall Detection Algorithm

200
0
B. Delta PS3 drop (PS3 initial - PS3 actual) , DPS3, psid

180 25
0 0
D
Rate of Change of Pressure- dPS3dt, psia/sec

A. KPS3_Drop_S
B. KPS3_Drop_I
C. KPS3_Drop_Mn
140 D. KPS3_Drop_Mx 20
0 0
120 A
0
100 15
0 0
80
0
60 10
0 0
G
40 E
0
20 5
C
0 0
E. KPS3_Delta_S
B
0 F. KPS3_Delta_I
F G. KPS3_Delta_Mx
-200 0
0 100 200 300 400 500 600 700
Initial Compressor Discharge Pressure PS3
Configurable Compressor Stall Detection Parameters
The variables used by the stall detection algorithm are defined as follows:
Variable Variable Description

PS3 Compressor discharge pressure
PS3I Initial PS3
KPS3_Drop_S Slope of line for PS3I versus dPS3dt
KPS3_Drop_I Intercept of line for PS3I versus dPS3dt
KPS3_Drop_Mn Minimum value for PS3I versus dPS3dt
KPS3_Drop_Mx Maximum value for PS3I versus dPS3dt
KPS3_Delta_S Slope of line for PS3I versus Delta PS3 drop
KPS3_Delta_I Intercept of line for PS3I versus Delta PS3 drop
KPS3_Delta_Mx Maximum value for PS3I versus Delta PS3 drop

Specifications
The following table provides information specific to the PAIC.
Item Specification
Number of channels 12 channels per terminal board (10 AI, 2 AO)
Input span 1 - 5 V dc, ±5 V dc, ±10 V dc, or 0-20 mA (Inputs 1-8)
0-20 mA or ±1 mA (Inputs 9-10)
Input converter resolution 16-bit analog-to-digital converter
Scan time Normal scan 5 ms (200 Hz). Note that maximum controller frame rate is 100 Hz.
Measurement accuracy PAIC with TBAI/STAI terminal boards –0.1% of full scale over the full operating temperature
range.
PAIC with SAII terminal board –0.3% of full scale over the full operating temperature range.
Noise suppression on inputs The ten circuits have a hardware filter with single pole down break at 500 rad/sec. A software
filter, using a two pole low pass filter, is configurable for: 0, .75, 1.5 Hz, 3 Hz, 6 Hz, 12 Hz
Common mode rejection Ac common mode rejection 60 dB at 60 Hz, with up to ±5 V common mode voltage.
Dc common mode rejection 80 dB with from -5 to +7 peak V common mode voltage
Common mode voltage range ±5 V (±2 V CMR for the ±10 V inputs)
Output converter 14-bit D/A converter with 0.5% accuracy
Output load 800 Ω for 4-20 mA output
50 Ω for 200 mA output
Power consumption 5.3 W typical, 6.2 W worst case
Compressor stall detection Detection and relay operation within 30 seconds
Physical
Size 8.26 cm high x 4.19 cm wide x 12.1 cm deep (3.25 in x 1.65 in x 4.78 in)
Temperature -30 to +65 ºC (-22 to +149 ºF)
Technology Surface mount

Diagnostics
The I/O pack performs the following self-diagnostic tests:
• A power-up self-test that includes checks of RAM, flash memory, Ethernet

ports, and most of the processor board hardware
• Continuous monitoring of the internal power supplies for correct operation
• A check of the electronic ID information from the terminal board, acquisition board,
and processor board to confirm that the hardware set matches, followed by a check
that the application code loaded from flash memory is correct for the hardware set
• Each analog input has hardware limit checking based on preset (non-configurable)
high and low levels near the end of the operating range. If this limit is
exceeded a logic signal is set and the input is no longer scanned. The logic
signal, L3DIAG_xxxx, refers to the entire board.
• Each input has system limit checking based on configurable high and low
levels. These limits can be used to generate alarms, to enable/disable, and as
latching/non-latching. RESET_SYS resets the out of limits.
• The analog input hardware includes precision reference voltages in each
scan. Measured values are compared against expected values and are used to
confirm health of the analog to digital converter circuits.
• Analog output current is sensed on the terminal board using a small burden
resistor. The I/O pack conditions this signal and compares it to the commanded
current to confirm health of the digital to analog converter circuits.
• The analog output suicide relay is continuously monitored for agreement
between commanded state and feedback indication.
Details of the individual diagnostics are available from the ToolboxST

application. The diagnostic signals can be individually latched, and then reset
with the RESET_DIA signal if they go healthy.

Configuration
Note The following information is extracted from the ToolboxST application and
represents a sample of the configuration information for this board. Refer to the actual
configuration file within the ToolboxST application for specific information.
Parameter Description Choices

Configuration
System Limits Enable or disable system limits Enable, disable
Output Voting Select type of output voting Simplex, TMR
Min_ MA_Input Select minimum current for healthy 4-20 mA input 0 to 21 mA
Max_ MA_Input Select maximum current for healthy 4-20 mA input 0 to 21 mA
CompStalType Select compressor stall algorithm (# of transducers) 0, 2, or 3
InputForPS3A Select analog input circuit for PS3A AnalogIn 1, 2, 3, or 4
InputForPS3B Select analog input circuit for PS3B AnalogIn 1, 2, 3, or 4
InputForPS3C Select analog input circuit for PS3C AnalogIn 1, 2, 3, or 4
SelMode Select mode for excessive difference pressure Maximum, Average
PressDelta Excessive difference pressure threshold 5 to 500
TimeDelay Time delay on stall detection in (msec) 10 to 40
KPS3_Drop_Min Minimum pressure rate 10 to 2000
KPS3_Drop_I Pressure rate intercept 10 to 100
KPS3_Drop_S Pressure rate slope .05 to 10
KPS3_Delta_S Pressure delta slope .05 to 10
KPS3_Delta_I Pressure delta intercept 10 to 100
KPS3_Delta_Mx Pressure delta max 10 to 100
KPS3_Drop_L Threshold pressure rate 10 to 2000
KPS3_Drop_Mx Max pressure rate 10 to 2000
:IS200TBAI Terminal board connected to PAIC Connected, not connected
AnalogIn1 First of 10 Analog Inputs – board point. Point edit (Input FLOAT)
Input Type Current or voltage input type Unused, 4-20 mA, ±5 V, ±10 V
Low_Input Value of current at the low end of scale -10 to +20
Low_Value Value of input in engineering units at low end of scale -3.4082 e + 038 to 3.4028 e + 038
High_Input Value of current at the high end of scale -10 to +20
High_Value Value of input in engineering units at high end of scale -3.4082 e + 038 to 3.4028 e + 038
Input _Filter Bandwidth of input signal filter Unused, 0.75, 1.5 Hz, 3 Hz, 6 Hz, 12 Hz
TMR Diff Limit Difference limit for voted inputs in % of high-low values 0 to 100
Sys Lim 1 Enabl Input fault check Enable, disable
Sys Lim 1 Latch Input fault latch Latch, unlatch
Sys Lim 1 Type Input fault type Greater than or equal Less than or equal
Sys Lim 1 Input limit in engineering units -3.4082 e + 038 to 3.4028 e + 038

Sys Lim 2 Type Input fault type Greater than or equal. Less than or equal
Sys Lim 2 Input limit in Engineering Units -3.4082 e + 038 to 3.4028 e + 038
DiagHighEnab Enable high input limit Enable, disable
DiagLowEnab Enable low input limit Enable, disable
TMR_DiffLimt Diag limit, TMR input vote difference, in percent of 0 to 200 %
(High_Value - Low_Value)
AnalogOut1 First of two analog outputs - board point Point edit (Output FLOAT)
Output_MA Type of output current, mA selection Unused, 0-20 mA, 0-200 mA
Output_State State of the outputs when offline PwrDownMode
Hold Last Value
Output_Value
Output_Value Pre-determined value for the outputs
Low_MA Output mA at low value 0 to 200 mA
Low_Value Output in Engineering Units at low mA -3.4082 e + 038 to 3.4028 e + 038
High_MA Output mA at high value 0 to 200 mA
High_Value Output value in Engineering Units at high mA -3.4082 e + 038 to 3.4028 e + 038
TMR Suicide Suicide for faulty output current, TMR only Enable, disable
TMR SuicLimit Suicide threshold for TMR operation 0 to 200 mA
D/A Err Limit Difference between D/A reference and output, in % for 0 to 200 %
suicide, TMR only
Dither Ampl Dither % current of Scaled Output mA 0 to 10
Dither_Freq Dither rate in Hertz Unused, 12.5, 25.0, 33.33, 50.0, 100.0

Board Points (Signals) Description - Point Edit (Enter Signal Connection) Direction Type
L3DIAG_PAIC Board diagnostic Input BIT
LINK_OK_PAIC Link Diagnostic Input Input BIT
ATTN_PAIC Module Diagnostic Input BIT
IOPackTmpr I/O Pack Temperature Input FLOAT
SysLimit1_1 System Limit 1 Input BIT
: : Input BIT
: : Input BIT
OutSuicide1 Status of Suicide Relay for Output 1 Input BIT
OutSuicide2 Status of Suicide Relay for Output 2 Input BIT
DeltaFault Excessive difference pressure Input BIT
CompStall Compressor Stall Input BIT
Out1MA Feedback, Total Output Current, mA Input FLOAT
: : Input FLOAT
Out2MA Feedback, Total Output Current, mA Input FLOAT
CompPressSel Selected Compressor Press, by Stall Algo. Input FLOAT
PressRate Sel Selected Compressor Press rate, by Stall Algor. Input FLOAT
CompStallPerm Compressor Stall Permissive Output BIT

TBAI Analog Input/Output
The Analog Input/Output (TBAI) terminal board supports 10 analog inputs and 2 outputs.
The 10 analog inputs accommodate two-wire, three-wire, four-wire, or externally powered
transmitters. The analog outputs can be set up for 0-20 mA or 0-200 mA current. Inputs and
outputs have noise suppression circuitry to protect against surge and high frequency noise.
TBAI has three DC-37 pin connectors provided on TBAI for connection to the I/O
processors. Simplex applications are supported using a single connector (JR1).
TMR applications are supported using all three connectors.
In TMR applications, the input signals are fanned to the three connectors for the R, S,
and T controls. TMR outputs combine the current of the three connected output drivers
and determine the total current with a measuring shunt. TBAI then presents the total
current signal to the I/O processors for regulation to the commanded setpoint.
TBAI Input Terminal Board

Control Compatibility
Control System TBAI Functionality

Mark VI control The board works with the VAIC pack and supports simplex and
TMR applications. One or two TBAIs can be connected to the
VAIC. In TMR systems, TBAI is cabled to three VAIC boards.
Mark VIe control The board works with the PAIC I/O pack and supports simplex
and TMR applications. In TMR systems, three PAICs plug
directly into the TBAI.
Mark VIeS control Board revision TBAIS1C is safety certified and required. The
200 mA output option is not supported by YAIC in the Mark
VIeS SIS. The same terminal board can be used for TMR
applications.
Board Revision Mark VI Mark VIe Mark VIeS Comments

IS200VAIC IS220PAIC IS200YAIC
TBAIH1A VAICH1C No No Use TBAIH2C as replacement part
and earlier
TBAIH1B VAICH1C No No Use TBAIH2C as replacement part
and earlier
TBAIH1C VAICH1D Yes, all versions No Current production
and later
TBAIH2C VAICH1C No (lowered No Compatible with early production VAIC
and earlier output with lower output compliance voltage
compliance)
TBAIS1C No Yes, all versions Yes, all versions Safety certified
Installation
Connect the input and output wires directly to two I/O terminal blocks mounted
on the terminal board. Each block is held down with two screws and has
24 terminals accepting up to #12 AWG wires. A shield terminal attachment
point is located adjacent to each terminal block.
TBAI can accommodate the following analog I/O types:
• Analog input, two-wire transmitter

• Analog input, three-wire transmitter
• Analog input, four-wire transmitter
• Analog input, externally powered transmitter
• Analog input, voltage ±5 V, ±10 V dc
• Analog output, 0-20 mA
• Analog output, 0-200 mA

The following figure displays the wiring connections, jumper positions,
and cable connections for TBAI.
Board Jumpers
Analog Input Terminal Board TBAI JT1
Circuit Jumpers
20mA/V dc Open/Ret
x
x 1 Input 1 (24V) Input 1 J1A J1B
Input 1 (20ma) x 2
x 3 Input 1 ( Vdc)
Input 1 (Ret) x 4
Input 2 (20ma) x 6
Input 2 (Ret)
x 7 Input 2 ( Vdc)
x 8
Input 3 (20ma) x 10
x 11 Input 3 ( Vdc)
Input 3 (Ret) x 12
Input 4 (20ma) x 14
x 15 Input 4 ( Vdc)
Input 4 (Ret) x 16
x 17 Input 5 (24V) Input 5 J5A J5B JS1 J ports connections:
Input 5 (20ma) x 18
x 19 Input 5 ( Vdc)
Input 5 (Ret) x 20
Input 6 (20ma) x 22 Plug in I/O Pack for
x 23 Input 6 ( Vdc) Plug
Input 6 (Ret) x 24 MarkinVIe
I/OSystem
pack or
or
x cable(s)
Cable(s) to
to board(s)
Board(s)
for Mark VI
x
Input 7 (20ma) x 26 The number and location
Input 7 (Ret)
x 27 Input 7 ( Vdc)
x 28 depends on the level of
Input 8 (20ma)
x 30 redundancy required.
x 31 Input 8 ( Vdc) 20mA/1 mA Open/Ret
Input 8 (Ret) x 32 JR1
Input 9 (20ma)
x 34
x 35 Input 9 (1ma)
Input 9 (Ret) x 36
Input 10 (20ma)
x 38
Input 10 (Ret)
x 39 Input 10 (1ma)
x 40
PCOM
x 41 PCOM
x 42
x 43 PCOM 20mA/200mA
PCOM x 44
x 45 Output 1 ( Sig) Output 1 J0
Output 1 (Ret) x 46
x 47 Output 2 ( Sig) Output 2 No Jumper (0-20mA)
Output 2 (Ret) x 48
x
Two-wire +24 V dc Three-wire +24 V dc

transmitter transmitter wiring
wiring 4-20mA Voltage input VDC J#A 4-20 mA Voltage input VDC J#A
T
4-20 ma 20 ma 4-20 ma 20 ma
T
Return Return
Open J#B Open J#B
PCOM
Externally powered +24 V dc Four-wire +24 V dc

transmitter wiring transmitter wiring
J#A J#A
4-20 mA Voltage input VDC 5 V dc Voltage input VDC
4-20 ma 20 ma T 4-20 ma 20 ma
+ +
Power
T Return Signal Return
Supply - -
Open J#B Max. common Open J#B
mode voltage Misc return PCOM
is 7.0 V dc to PCOM
PCOM
TBAI Terminal Board Wiring

Operation
TBAI provides a 24 V dc power source for all the transducers. The inputs can be
configured as current or voltage inputs using jumpers (J#A and J#B). One of the two
analog output circuits is 4-20 mA and the other can be configured as 4-20 mA or
0-200 mA. The following table displays the analog I/O capacity of TBAI.
Quantity Analog Input Types Quantity Analog Output Types

8 ±10 V dc, or ±5 V dc, or 4-20 mA 1 0-20 mA or 0-200 mA
2 4-20 mA, or ±1 mA 1 0-20 mA
With the noise suppression and Each 24 V dc power output is rated to deliver 21 mA continuously and is protected
filtering, the input ac CMR is 60 against operation into a short circuit. Transmitters/transducers can be powered
dB, and the dc CMR is 80 dB. by the 24 V dc source in the control system, or can be independently powered.
Jumper JO selects the type of current output. Diagnostics monitor each output
and a suicide relay in the I/O controller disconnects the corresponding output if a
fault cannot be cleared by a command from the processor.
Terminal Board TBAI
8 circuits per I/O CONTROLLER

terminal board
Application Software
SYSTEM Noise
POWERED Suppr-
ession
+24 V dc P28V
Current Limit
+/-5,10 Vdc Vdc J#A

T N
4-20 ma S 20 ma
Return 250 ohms
J#B
Open Return R
PROCESSOR
PCOM
2 circuits per
termination board
A/D D/A
P28V
+24 V dc Current Limit Excitation
1 ma J#A JR1
+/-1 ma N
S 20 ma
4-20 ma 250
ohm 5k ohms
Return
J#B
Return
Open
Current
Regulator/
Two output circuits
Jump select on one Power Supply
circuit only; #2 Circuit 200 ma
is 4-20 ma only
JO
Signal 20 ma
N
S
Return
ID
SCOM
Simplex Analog Inputs and Outputs

In a TMR system, analog inputs fan out to the three I/O packs. The 24 V dc power
to the transducers comes from all three controllers and is diode shared on TBAI.
Each analog current output is fed by currents from all three controllers. The actual
output current is measured with a series resistor, which feeds a voltage back to each
I/O controller. The resulting output is the voted middle value (median) of the three
currents. The following figure displays TBAI in a TMR system.
I/O CONTROLLER
Terminal Board TBAI
8 circuits per Application Software
Terminal board
SYSTEM Noise
POWERED Suppr-
P28V<T>
ession P28VR P28V<S>
+24 V dc Current Limit
+/-5,10 Vdc Vdc J#A

T N
4-20 ma S 20 ma
250 ohms
Return
J#B
Open Return
R
PCOM PROCESSOR
2 circuits per
terminal board A/D D/A
P28VR
+24 Vdc Current Limit Excitation
1 ma J#A JR1
+/-1 ma N
4-20 ma S 20 ma
250
ohm 5k ohms
Return
J#B
Open Return
PCOM S ID Current
T Regulator/
Two output circuits, JO Power Supply
#2 circuit is 4-20 200 ma
mA only
Signal 20 ma
N S JS1
S T
Return
To S PROCESSOR
SCOM
ID
JT1
To T PROCESSOR
ID
Analog Inputs and Outputs, TMR

Specifications
Item Specification
Number of channels 12 channels (10 AI, 2 AO)
Input span, transmitters 1-5 V dc from 4-20 mA current input
Outputs 24 V outputs provide 21 mA each connection
Maximum lead resistance 15 Ω maximum two-way cable resistance, cable length up to 300 m (984 ft)
Output load 500 Ω for 4-20 mA output, TBAIH1B with VAICH1C
800 Ω for 4-20 mA output, TBAIH1C with VAICH1D
800 Ω for 4-20 mA output, TBAIH1C with PAIC
800 Ω for 4-20 mA output, TBAIS1C with YAIC
50 Ω for 200 mA
Physical
Fault detection Monitor total output current
Check connector ID chip for hardware incompatibility
Temperature -30 to 65ºC (-22 to +149 ºF)
Size 10.16 cm wide x 33.02 cm high ( 4.0 in x 13 in)
Diagnostics
Diagnostic tests are made on the terminal board as follows:
• The board provides the voltage drop across a series resistor to indicate
the output current. The I/O processor creates a diagnostic alarm (fault)
if any one of the two outputs goes unhealthy.
• Each cable connector on the terminal board has its own ID device that is
interrogated by the I/O controller. The ID device is a read-only chip coded with
the terminal board serial number, board type, revision number, and the JR, JS, JT
connector location. When this chip is read by the I/O controller and a mismatch
is encountered, a hardware incompatibility fault is created.
Configuration
The terminal board is configured by jumpers. For the location of these jumpers,
refer to the installation diagram. The jumper choices are as follows:
• Jumpers J1A through J8A select either current input or voltage input.
• Jumpers J1B through J8B select whether the return is connected
to common or is left open.
• Jumpers J9A and J10A select either 1 mA or 20 mA input current.
• Jumpers J9B and J10B select whether the return is connected to common or is left open.
• Jumper J0 sets output 1 to either 20 mA or 200 mA.

STAI Simplex Analog Input
The Simplex Analog Input (STAI) terminal board is a compact analog input terminal
board that accepts 10 analog inputs and two analog outputs, and connects to the pack. The
10 analog inputs accommodate two-wire, three-wire, four-wire, or externally powered
transmitters. The two analog outputs are 0-20 mA but one can be jumper configured
to 0-200 mA current. Only a simplex version of the board is available.
High-density Euro-block type terminal blocks are used. An on-board ID chip

identifies the board to the pack for system diagnostic purposes.
Control System STAI Functionality

Mark VIe control PAIC I/O pack works with the STAI. The I/O pack plugs into the
D-type connector and communicates with the controller over
Ethernet. Only simplex systems are supported.
Mark VIeS control Board revisions STAISIA and STAIS2A are safety certified and
work with YAIC. The 200 mA output option is not supported.
Board Revision Mark VIe Mark VIeS Comments

IS220PAIC IS200YAIC
STAIH1A Yes, all versions No Fixed terminals
STAIH2A Yes, all versions No Plug in terminals
STAIS1A Yes, all versions Yes, all versions Fixed terminals, safety certified
STAIS2A Yes, all versions Yes, all versions Plug in terminals, safety certified

Installation
The STAI plus a plastic insulator mounts on a sheet metal carrier that then
mounts on a DIN-rail. Optionally, the STAI plus insulator mounts on a sheet
metal assembly and then bolts directly to a cabinet. There are two types of
Euro-block terminal blocks available as follows:
• STAI_1 has a permanently mounted terminal block with 48 terminals.

• STAI_2 has a right angle header accepting a range of commercially available
pluggable terminal blocks, with a total of 48 terminals.
Typically #18 AWG wires (shielded twisted pair) are used. I/O cable shield
terminal is provided adjacent to the terminal blocks.
The following types of analog inputs and outputs can be accommodated:

• Analog output, 0-20 mA current

Wiring, jumper positions, and cable connections display on the wiring diagram.
STAI Analog Input Terminal Board
E1
Jumpers Circuit Screw Connections Screw Connections Jumpers
Vdc/20mA Open/Return TB1 JP1A DC-37 pin
1 Input 1 (24V) JP1B connector
Input 1 (20mA) 2 with latching
J1A J1B Input 1 3 Input 1 (Vdc)
Input 1 (Return) 4 JP2A
fasteners
5 Input 2 (24V)
J2A J2B Input 2 Input 2 (20mA) 6 JP2B JA1
7 Input 2 (Vdc)
Input 2 (Return) 8
9 Input 3 (24V) JP3A
J3A J3B Input 3 Input 3 (20mA) 10
11 Input 3 (Vdc) JP3B
Input 3 (Return) 12 13 Input 4 (24V) JA1
J4A J4B Input 4 Input 4 (20mA) 14 JP4A
15 Input 4 (Vdc)
Input 4 (Return) 16 JP4B
17 Input 5 (24V) Plug in Pack
Input 5 (20mA) 18
J5A J5B Input 5 19 Input 5 (Vdc) JP5A
Input 6 (20mA) 21 Input 6 (24V)
J6A J6B Input 6 22 or
Input 6 (Return) 23 Input 6 (Vdc) JP6A
24
Input 7 (20mA) 26 25 Input 7 (24V) JP6B
J7A J7B Input 7 27 Input 7 (Vdc) Cable to I/O
Input 7 (Return) 28 JP7A Processor
29 Input 8 (24V)
Input 8 (20mA) 30
J8A J8B Input 8 31 Input 8 (Vdc) JP7B
Input 8 (Return) 32
20mA/1mA 33 Input 9 (24V)
Input 9 (20mA) 34 JP8A
J9A J9B Input 9 35 Input 9 (1mA)
37 Input 10(24V)
J10A J10B Input 10 Input 10(20mA) 38 39 Input 10(1mA) JP9A
Input 10(Return) 40 JP9B
41 PCOM JP0
PCOM 42
43 PCOM JP10A
PCOM 44
45 Output 1 (Signal) JP10B
J0 Output 1 Output 1 (Return) 46
Output 2 (Return) 47 Output 2 (Signal)
No jumper Output 2 48
PCOM
E2
Chassis ground

wiring 4-20mA Voltage input VDC J#A 4-20 mA Voltage input VDC J#A
T
4-20 ma 20 ma 4-20 ma 20 ma
T
Return Return
Open J#B Open J#B
PCOM

J#A
4-20 mA Voltage input VDC J#A 5 V dc Voltage input VDC
4-20 ma 20 ma T 4-20 ma 20 ma
+ +
Power
Supply - -
Open J#B Max. common Open J#B
is 7.0 V dc to PCOM
PCOM
STAI Wiring, Cabling, and Jumper Positions

Operation
24 V dc power is available on the terminal board for all the transmitters (transducers).
There is a choice of current or voltage inputs using jumpers. One of the two
analog output circuits is 4-20 mA, and the other can be jumper configured for
4-20 mA or 0-200 mA. There is only one cable connection, so the terminal board
cannot be used for TMR applications as with TBAI.
The following table displays the analog input/output capacity of the STAI terminal board.

8 ±10 V dc, or ±5 V dc, or 4-20 mA 1 0-20 mA, or 0-200 mA
2 4-20 mA, or ±1 mA 1 0-20 mA
STAI Terminal Board

Specifications
Item Specification
Input span, transmitters 1 - 5 V dc across a precision resistor (usually 250 W)
Maximum lead resistance 15 Ω maximum two-way cable resistance, cable length up to 300 m (984 ft).
Outputs 24 V dc outputs rated at 21 mA each
Load on output currents 800 Ω burden for 4-20 mA output with PAIC pack
50 Ω burden for 200 mA output
Physical
Size 15.9 cm high x 10.2 cm wide (6.25 in. x 4.0 in.)
Temperature -30 to +65ºC (-22 to +149 ºF)
Diagnostics
Configuration
The terminal board is configured by jumpers. For the location of these jumpers,
refer to the installation diagram. The jumper choices are as follows:
• Jumpers J1A through J8A select either current input or voltage input.
• Jumpers J1B through J8B select whether the return is connected
to common or is left open.
• Jumpers J9A and J10A select either 1 mA or 20 mA input current.
• Jumpers J9B and J10B select whether the return is connected to common or is left open.
• Jumper J0 sets output 1 to either 20 mA or 200 mA.

SAII Simplex Isolated Analog Input
The Simplex Analog Input (SAII) terminal board is a compact analog input terminal
board that accepts 10 analog inputs and offers two analog outputs, and connects
to the PAIC. The I/O pack plugs into the D-type connector and communicates
with the controller over Ethernet. The 10 analog inputs accommodate 2-wire,
3-wire, 4-wire, or externally powered transmitters.
Each analog input features point isolation when configured for externally powered
devices. Each analog input has an isolator in the circuit with a rating of 1500 V rms. The
two analog outputs are 0-20 mA but one can be jumper configured to 0-200 mA current
when used with a PAICH2. High-density Euro-block type terminal blocks are used. An
on-board ID chip identifies the SAII to the PAIC for system diagnostic purposes.
Installation
The SAII plus a plastic insulator mounts on a sheet metal carrier that then
mounts on a DIN-rail. Optionally, the SAII plus insulator mounts on a sheet
• SAIIH1 has a permanently mounted terminal block with 48 terminals

• SAIIH2 has a right angle header accepting a range of commercially available
pluggable terminal blocks, with a total of 48 terminals
The Euro-style box terminals on SAII accept conductors with the following characteristics:

Conductor Type Size
Conductor cross section solid min. 0.2 mm²
Conductor cross section solid max. 2.5 mm²
Conductor cross section stranded min. 0.2 mm²
Conductor cross section stranded max. 2.5 mm²
Conductor cross section stranded, with ferrule without plastic sleeve min. 0.25 mm²
Conductor cross section stranded, with ferrule without plastic sleeve max. 2.5 mm²
Conductor cross section stranded, with ferrule with plastic sleeve min. 0.25 mm²
Conductor cross section stranded, with ferrule with plastic sleeve max. 2.5 mm²
Conductor cross section AWG/kcmil min. 24 AWG
Conductor cross section AWG/kcmil max 12 AWG
2 conductors with same cross section, solid min. 0.2 mm²
2 conductors with same cross section, solid max. 1 mm²
2 conductors with same cross section, stranded min. 0.2 mm²
2 conductors with same cross section, stranded max. 1.5 mm²
2 conductors with same cross section, stranded, ferrules without plastic sleeve, min. 0.25 mm²
2 conductors with same cross section, stranded, ferrules without plastic sleeve, max. 1 mm²
2 conductors with same cross section, stranded, TWIN ferrules with plastic sleeve, min. 0.5 mm²
2 conductors with same cross section, stranded, TWIN ferrules with plastic sleeve, max. 1.5 mm²

The following table lists the terminal assignments for the SAII terminal board:
SAII Screw Terminal Assignments

Name Name
1 Input 1 (24 V) 25 Input 7 (24 V)
2 Input 1 (20 mA) 26 Input 7 (20 mA)
3 Input 1 (V dc) 27 Input 7 (V dc)
4 Input 1 (Return) 28 Input 7 (Return)
5 Input 2 (24 V) 29 Input 8 (24 V)
6 Input 2 (20 mA) 30 Input 8 (20 mA)
7 Input 2 (V dc) 31 Input 8 (V dc)
9 Input 3 (24 V) 33 Input 9 (24 V)
10 Input 3 (20 mA) 34 Input 9 (20 mA)
11 Input 3 (V dc) 35 Input 9 (1 mA)
13 Input 4 (24 V) 37 Input 10 (24 V)
14 Input 4 (20 mA) 38 Input 10 (20 mA)
15 Input 4 (V dc) 39 Input 10 (1 mA)
17 Input 5 (24 V) 41 PCOM
18 Input 5 (20 mA) 42 PCOM
19 Input 5 (V dc) 43 PCOM
20 Input 5 (Return) 44 PCOM
21 Input 6 (24 V) 45 Output 1 (Signal)
22 Input 6 (20 mA) 46 Output 1 (Return)
23 Input 6 (V dc) 47 Output 2 (Signal)
24 Input 6 (Return) 48 Output 2 (Return)

The following types of analog inputs and outputs can be accommodated:

Wiring, jumper positions, and cable connections appear on the wiring diagram.
Two-wire +24 V dc I
transmitter S
wiring 4-20mA T Voltage input VDC J#A
O
4-20 ma 20 ma
L
A To PAIC
Return T
O
Open J#B R
Externally powered +24 V dc I

transmitter wiring
S
4-20 mA Voltage input VDC J#A
O
4-20 ma L
+ + 20 ma To PAIC
Power A
T Return T
Supply - -
O
Open J#B R
Three-wire +24 V dc I
transmitter wiring S
4-20 mA Voltage input VDC J#A
O
4-20 ma 20 ma L
T A To PAIC
Return T
O
Open J#B R
PCOM
Four-wire +24 V dc I
transmitter wiring
Voltage input VDC J#A S
5 V dc
O
4-20 ma 20 ma L
T To PAIC
A
Signal Return T
O
Open J#B R
Misc return PCOM
to PCOM
PCOM
SAII Wiring, Cabling, and Jumper Positions

SAII Jumper Details- Input 1-8 Input 9-10
The jumpers for inputs one through eight select between voltage and milliamp
input (JP#A), and grounded or ungrounded operation (JP#B). Inputs 9 and 10
substitute a 1 mA input range for the voltage input option.
SAII Terminal Board

Operation
24 V dc power is available on the terminal board for all the transmitters (transducers).
There is a choice of current or voltage inputs using jumpers. One of the two
analog output circuits is 4-20 mA, and the other can be jumper configured for
4-20 mA or 0-200 mA. There is only one PAIC connection, so the terminal board
cannot be used for TMR applications as with TBAI.
The following table displays the analog input/output capacity of the SAII terminal board.

8 ±10 V dc, or ±5 V dc, or 4-20 mA * 1 0-20 mA, or 0-200 mA
2 4-20 mA, or ±1 mA * 1 0-20 mA
*The input must be within the valid input range and not exceed more than 10% of the full
scale value. For example, in a ±10 V input configuration the input cannot exceed ±11 V.

SAII Terminal Board
Noise
suppr-
ession 8 circuits per board
+24 V dc 1
Current Limit P28V
Voltage In 3 Vdc JP1A
N
4-20 mA 2 S 20mA Isolator
Return 250 ohms
4
JP1B
Return
Open
JA1
41
42
43
44 Pcom
2 circuits per board

PAIC
+24 V dc 33
Current Limit P28V
+/- 1 mA 35 1mA JP9A
N
4-20 mA 34 S 20mA
Isolator
250 5k
Return 36 ohm ohm
JP9B ID
Return
Open
Pcom
200mA
JP11
20mA
Signal 45 Signal
N
Return 46 S Return
2 circuits per board,

1 has 20/200mA jumper
SCOM
SAII Terminal Board

Specifications
Item Specification
Input span, transmitters 1 - 5 V dc across a precision resistor (usually 250 Ω)
Load on output currents 800 Ω burden for 4-20 mA output with PAIC pack
50 Ω burden for 200 mA output
Accuracy Typical accuracy ±0.15%,
Worst case accuracy ±0.3%
PAIC pack with TBAI or STAI terminal board offers full-scale accuracy of 0.1%.
PAIC with SAII terminal board offers full-scale accuracy of 0.3% worst case. Point isolation
introduces an additional 0.2% error to analog inputs and so PAIC/SAII total accuracy is
±0.3% of full scale over the operating temperature range.
Isolation Each analog input is isolated with rating of 1500 V rms
Maximum input range The input must be within the valid input range and not exceed more than 10% of the full
scale value. For example, in a ±10 V input configuration the input cannot exceed ±11 V.
Physical
Temperature -30 to 65ºC (-22 to 149 ºF)
Diagnostics
• The PAIC connector on the terminal board has its own ID device that is

Configuration
Jumpers configure the terminal board. For the location of these jumpers, refer to
the installation diagram. The jumper choices are as follows:
• Jumpers JP1A through JP8A select either current input or voltage input.
• Jumpers JP9A and JP10A select either 1 mA or 20 mA input current.
• Jumpers JP1B through JP10B select whether the return is connected to common or
is left open. When any of the JP1B to JP10B is in place and the return is connected
to common, then that respective channel will not be point isolated.
• Jumper JP11 sets output 1 to either 20 mA or 200 mA when used
with a PAICH2 I/O pack.
Note On the SAII the JP1B through JP10B jumpers that determine the common
connection are a type that provides ample voltage clearance to preserve isolation
voltage rating when they are removed. For convenience, the SAII board provides
storage locations for jumpers that are not providing a path to common.

Notes

PAMB Acoustic Monitoring Input Module
Acoustic Monitoring Input (PAMB)

The Mark* VIe Acoustic Monitoring Input (PAMB) pack supports combustion
dynamics for all frame 6, 7, and 9 gas turbines. The PAMB I/O module includes
the IS215BAPAH1A Analog Processor (BAPA) and the Acoustic Monitoring
(SAMB) terminal board grouped together as an application subassembly, and the
IS215UCCAM06A CompactPCI® (CPCI) processor module.
PAMB accepts dynamic pressure data from SAMB. The analog signal is conditioned to
remove dc bias and amplify ac content (to maximize resolution) before it is digitized by an
analog-to-digital (A/D) converter. A field programmable gate array (FPGA) sequences,
digitizes, and filters the dynamic pressure signals and controls the high-speed serial
link (HSSL) protocol for the Ethernet link between the BAPA and UCCA.
The UCCA, which mounts in a CPCI rack, is a LAN module that serves as the PAMB
processing engine. The UCCA was selected for acoustic monitoring because it provides
the additional processing capacity required for the fast fourier transform (FFT) analysis,
sorting function, proprietary algorithms, sensor diagnostics, and so on.
GEH-6721L PAMB Acoustic Monitoring Input Module System Guide 3-1

Two versions of the Acoustic Monitoring System are offered, as follows:
• Dual Acoustic Monitoring System (323A4747WCP2). SAMB fans all 18 inputs to

each PAMB. PAMB 1 (left) communicates with the UCCA connected to IONet R.
PAMB 2 (right) communicates with the UCCA connected to IONet S. The controller’s
application code votes which PAMB data to use, based on the signal health.
to controllers
Acoustic Acoustic
1
UCCAM06A UCCAM06A
1
Monitoring Monitoring
Charge M M
2
STAT ONL ST AT ONL
E E
Z Z
Converter
3
Z Z
Low-Noise
3
PWR PWR A A
Cable Signal N N
4
ATTN ATTN I I
N N
Amplifier E E
5
Pressure
(CCSA) C C
6
Sensor LINK LINK A A
6
DIAG DC R DIAG DC R
TxRx TxRx D D
7
ENET1 ENET1
9-chan M M
8
STAT ONL
E ST AT ONL
E
Z Z
9
Z Z
9
A A
N N
1
I I
N N
E E
2
1
C C
A A
3
Charge R R
2
DIAG DC DIAG DC
D D
4
Converter
3
L L
Turbine A A
5
Signal ENET1 ENET1 N N
4
Combustor Amplifier 6
C C
5
O O
(max. of 18) Cable M M

7
(CCSA)
6
Twisted RST RST

8
7
S S
&
9
9-chan Shield IS210BAPAH1A IS210BAPAH1A

8
cPCI "R" cPCI "S"

9
IS210SAMB
Mark*VIe Dual PAMB (323A4747WCP2)
Dual Acoustic Monitoring System Overview
• Simplex Acoustic Monitoring System (323A4747WCP1) – Simplex

version of 323A4747WCP2. Controller application code is not
required to vote signals from PAMB.
Acoustic
(open)
1
UCCAM06A
1
Monitoring
Charge M
2
ST AT ONL
E
Z
Converter
3
Z
Low-Noise
3
PWR A
Cable Signal N
4
ATTN I
N To
Amplifier P E
5
Controller
5
Pressure
(CCSA) 1 C
6
LINK A
6
Sensor DIAG DC R
TxRx D
7
ENET1
9-chan M
8
ST AT ONL
E
Z
9
Z
9
A
N
1
I
N
E
2
1
C
A
3
Charge
2
DIAG DC R
D
P
4
Converter
3
L
Turbine 2 A
5
Signal ENET1 N
4
Combustor
6
Amplifier C
5
(max. of 18) Cable M

7
(CCSA)
6
Twisted RST
8
7
S
&
9
9-chan Shield IS210BAPAH1A

8
cPCI "R"
9
IS210SAMB
Mark*VIe Simplex (323A4747WCP1)
Simplex Acoustic Monitoring System Overview

Compatibility
PAMBH1A is compatible with the following acoustic monitoring terminal boards:
Terminal Board SAMBH1A

Control Mode Simplex - Yes Dual - Yes TMR - No
• Dual uses two I/O packs with one network connection.
Simplex PAMB Mounted on SAMB Terminal Board
Installation
A GE field service technician should install the PAMB. Technicians should refer
to Support Central website Acoustic Monitoring Module (PAMB) Installation in
a Mark* VIe Control, for complete installation instructions.
See Installation in the SAMB section of this document for installation instructions
for the SAMB terminal board and dynamic pressure inputs.

Wizard again.

Operation
The PAMB includes the following features.
• Signal conditioning for up to 18 combustion dynamic pressure inputs:

− GE Energy Charge-Converter Signal Amplifier (CCSA) or Piezotronics®
sensors for heavy-duty turbines are supported
− Differential inputs and adjustable gains
− Fast synchronous-sampled A/D with 16x over-sampling
− FPGA pre-processor with finite impulse response (FIR) filters
− Open wire detection
• Analysis capability per channel:
− Windowed FFT analysis
− Rolling average per bin
− 50/60 Hz rejection filters
− Sort function providing peak pressure amplitude for six different frequency bands
− Maximum peak detect for each frequency band
− Average channel peak-to-peak amplitudes per frequency band
− Alarm detection if peak-to-peak amplitude exceeds configurable
level for each frequency band
− List capture for all 18 channels if alarm is detected or user requests capture
− Proprietary functions
Processor
The processor module contains a CPCI processor board (IS200UCCAH1A), an
Ethernet-based IONet communication mezzanine board (IS200EPMCH1A), and one
HSSL Ethernet mezzanine board (IS200EPMCH3A). It contains the following:
• High-speed processor with random access memory (RAM) and flash memory
• Six fully-independent 10/100 Ethernet ports with connectors
• Two universal asynchronous receiver-transmitter (UART) type serial
ports with connectors
• Electronic ID
• Compact flash support
UCCA connects to BAPA through the HSSL interface. The PAMB is designed so that the
UCCA and the BAPA can be located in different locations. Each module can be powered
independently. At power up, the BAPA waits for UCCA to initiate communications.
After communication is established, the application FPGA is programmed.
The processor application code contains the logic to allow PAMB to operate on one or
two IONet inputs. When using two IONet inputs, both network paths are active at all
times. A failure of either network will not disturb I/O pack operation and will be indicated
than a classic hot-backup system in which the second port is only used after a primary
port failure is detected. The Ethernet ports on the processor auto-negotiate between 10
MB/s and 100 MB/s speed, and between half-duplex and full-duplex operation.

Analog Processor
The analog processor includes the following features:
• Eighteen analog signal-conditioning channels

− Differential inputs
− Adjustable gains of 1x, 2x, 4x, and 8x
− Dc bias nulling
− Multiplexer to bypass signal input and apply test signal
− Anti-alias filters to support 5 kHz bandwidth
• Twenty-four A/D input channels
− Six channels per converter
− 16-bit converter
• Application FPGA
− A/D converter control
− D/A converter control
− Eighteen channels of FIR filtering
− Configuration registers
− HSSL control
• Boots FPGA with programmable read-only memory (PROM)
− Bootstrap function
− Tx / Rx mini-MACs
− PHY sync
• PHY0 and PHY1 physical Ethernet layers
• Power supplies
− P28 input
− P15 and N15 outputs
− P5 output
− 3.3 V, 2.5 V, and 1.2 V outputs

Acoustic Monitoring Firmware
The acoustic monitoring firmware supports 18 input channels. The main features are:
• RMS Broadband Calculation – Calculates the broadband root-mean-square

(RMS) energy of the time-domain sampled data in the frequency range of 0 to
5000 Hz. The output is the input of the RMS Scan Average.
• RMS Scan Average – Average multiple scans of broadband RMS values. A scan
is defined by the amount of time-domain sampled combustion data to calculate
a windowed FFT of some defined length. The output is the system input, SIGx
(where x is the channel number), passed to the controller.
• Windowed FFT – Calculates the frequency domain peak-to-peak magnitude
and bin frequency, based on time-domain sampled combustion input data.
The configuration defines the type of FFT window function used, the FFT
length (amount of input data collected for the calculation), and the sample
frequency. The output feeds the Peak-to-Peak Scan Average.
• Peak-to-Peak Scan Average – Provides a frequency domain peak-to-peak
magnitude average per frequency bin, over multiple scans. The configuration
defines the number of scans used in the rolling average calculation. The
output is the input for the Six-Band Sort function.
• Six-Band Sort – Average frequency domain peak-to-peak data is sorted into six
separate frequency bands, as displayed in the following table.
Frequency Bands
Freq Band # Configuration Band Name

1 Low (Low)
2 Middle (Mid)
3 High (High)
4 Low Low (LoLo)
5 Trans (Trns)
6 Screech (Scrch)

The maximum of the average peak-to-peak magnitudes from each frequency band and its
corresponding frequency bin are selected and output as system inputs for the controller.
• Band n Average – Calculates the average peak-to-peak magnitude over all enabled
healthy input channels, based on the output of the Six-Band Sort.
• Band n Maximum – Calculates the maximum peak-to-peak magnitude over
all input channels enabled, based on the Six-Band Sort data. The six frequency
band maximums are output for use by the controller.
• Band n Limit Check – A frequency band limit check based on
the Band n Maximum output data.
RMS Sig1 SIG_1

RMS Scan
Broadband
Avg Sigx SIG_18
Calc
where ch x = 1 - 18
6-Band Sort FrqB1_PkAmp1
FrqB1_PkHz1
Select a maximum
pk-pk amplitude for
each of the 6 FrqBn_PkAmpx
configurable FrqBn_PkHzx S
frequency bands where band n = 1 - 6 I
& ch x = 1 - 18 G
Band n Avg.
FrqB1_AmpAvg N
Average channels 1 A
thru x in Freq. L
Pk-Pk Scan Avg
Band n FrqBn_AmpAvg
FrqB1_AmpMx S
FrqB1_HzMx P
Band n Max. FrqB1_ChMx A
C
Sel max. mag.
FrqBn_AmpMx
E
from the x
FrqBn_HzMx
ch(s) for Freq.
Band n FrqBn_ChMx I
Band n where band n = 1 - 6
Ch 1 Limit N
Check P
Ch 2 FrqB1_LmtSet
U
Windowed
Check T
FFT
Band n S
FrqBn_LmtSet
Max. out
where band n = 1 - 6
Ch x against
where x = 1 - 18 Limit.
Acoustic Monitoring Block Diagram
A/D Compensation
The A/D compensation function eliminates any gain or offset error due to initial
component inconsistency. An auto-calibration function runs each time the module
is reset. The auto-calibration function compares each of the 18 analog channels
against a standard A/D channel. This A/D channel is calibrated using a standard
high-precision voltage reference and the A/D common.

Input Units to Engineering Value Conversion
The Acoustic Monitoring System converts the hardware input units to the engineering
units (EU) needed for the system calculation. For the conversion of mV to psi,
the range is 20 to 600 mV per psi. Four configuration parameters are provided
per channel to define the equation for the transfer function.
Value (EU in counts) = GUnitConversion * Input (millivolts in counts) + Offset
where
GUnitConversion = (High_Value – Low_Value) / (High_Input – Low_Input)
Offset = High_Value - GUnitConversion * High_Input
where High_Value, Low_Value, High_Input + Low Input are the configuration parameters.
A/D Gain Adjust

The configuration parameter, Gain, controls the channel gain in the hardware. This
parameter is defined for each channel. This allows low-level signals to be amplified
to provide better resolution in the A/D conversion hardware. The gain options are
1x, 2x, 4x, and 8x. The channel control writes the gain setup to the FPGA input
amplifier 4x and 2x gain control registers. The signal level calculated by PAMC
firmware does not change with the Gain parameter because the signal is divided by
the gain factor in the firmware, resulting in a net gain of 1 for the signal regardless
of the gain factor used. The maximum expected signal level should not exceed 10 V
(saturation) after the gain is applied as indicated in the following table.
Rules for Selecting Gain Value
Gainx Maximum magnitude of input signal after

dc bias is removed (volts)
1 10
2 5
4 2.5
8 1.25
RMS Calculation and Rolling Average

The RMS calculation function performs an RMS calculation on the ac acoustic
information sampled for a given scan. The RMS is defined as follows:
rms_Chx = SQRT ( (AC_Input(0)**2 + AC_Input(1)**2 + … +

AC_Input(Buffer_Length)**2) / Buffer_Length)
Where x is the channel number.
The rolling average function provides a smoothing function to reduce

the vibration in the signal.

Capture Lists
Two capture lists are available, as follows:
• Trip Capture Lists – This function provides circular buffers that input internally
calculated data, which is selected based on a configuration parameter. The
circular buffers can capture up to 32 scans of information for each of 18
channels. The following internal data can be captured:
• Time-domain sampled input data (in volts)

• Frequency-domain FFT peak-to-peak magnitude (in volts)
• FFT output data with transducer compensation (in volts)
• FFT output data with transducer compensation (in EU)
• Scan-averaged FFT output data with transducer compensation (in EU)
Trip Capture Lists are pre-triggered, meaning for a 32 scan FFT average, data is
scanned 32 times before the triggered event and none after the event. The triggered
event is activated by the signal space input, TripCapReq. Running on the HMI
or OSM computer, AM Gateway software uploads the captured lists and transfers
the data to the Atlanta Remote DLN Tuning Center for analysis.
• User Capture Lists – This function provides circular buffers that are only one
scan in length (compared to the Trip Capture, with 32 scan buffers). The User
Capture buffers can input the same internal data as the Trip Capture buffers. The
AM Gateway software can upload these lists. User capture lists are activated
through the AM Gateway or other compatible applications.
PAMB Acoustic Monitoring Diagnostic Support
Ch x AC sampled data (volts) Capture selected Ch 1 Capture List TripCapList

S data for each
Ch x Windowed FFT data (volts) e channel. Number of Ch 2 Capture List
l data samples Ch 3 Capture List
Ch x FFT w Transducer Compensation (volts)
e determined by the
Ch x FFT w Transducer Compensation (EU) c FFT length and
t number of Scans
averaged. Ch 18 Capture List
Ch x FFT w Trans Comp & Scan Avged (EU)
TripCapReq Start Capturing data

Trip Capture Lists
A User Capture List is also provided but is only 1 Scan deep.
Chan1_Health
Chan2_Health
Channel Health Status
Chan18_Health
L3Diag_VAMB
PAMB Acoustic Monitoring Diagnostic Support

Specifications
Item Specification
Input channels 18 dynamic pressure inputs
Output channels 18 buffered outputs
Gain adjustment options 1x, 2x, 4x, and 8x
Bias – minimum adjust -13.5 ±0.25 V dc
Bias – maximum adjust +13.5 ±0.25 V dc
Input accuracy from terminal point to inputs, SIGx for passband = ≤ 2.0 % of full scale = 10 V dc for Gain = 1x
0 to 5 kHz ≤ 2.0 % of full scale = 5 V dc for Gain = 2x
≤ 2.0 % of full scale = 2.5 V dc for Gain = 4x
Input accuracy (dc + ac) from terminal point to peak-peak signal ≤ 0.5 % of full scale = 10 V dc for Gain = 1x
–space values through FFT analysis for passband = 0 to 3.2 kHz ≤ 0.5 % of full scale = 5 V dc for Gain = 2x
Input accuracy (dc + ac) from terminal point to peak-peak signal-space ≤ 2.0 % of full scale = 10 V dc for Gain = 1x
values through FFT analysis for passband = 3.2 kHz to 5 kHz ≤ 2.0 % of full scale = 5 V dc for Gain = 2x
Input passband frequency 0 to 5 kHz
Diagnostics
The pack performs the following self-diagnostic tests:
• A power-up self test that includes checks of RAM, flash memory, Ethernet
and processor board ID to confirm that the hardware set matches, followed by a check
that the application code loaded from flash memory is correct for the hardware set.
• Each input has sensor limit checking, open circuit detection, dc bias autonulling, and
excessive dc bias detection. Alarms are generated for these diagnostics. Refer to the
tables I/O Pack Alarms and Point Configuration. RESET_SYS resets these alarms.
Details of the individual diagnostics are available in the ToolboxST* application. The
diagnostic signals can be individually reset with RESET_DIA if they go healthy.

Configuration
Module Description (Point Level Configuration) Choices

Parameter
BinReject Defines the number of side bins that will be rejected when the 0 to 6
search function is applied to the FFT results for channels 1 – 18.0
= no bins rejected
Config_Mode Defines the source of the currently active configuration. ToolboxST ToolboxST only
allows only mode toolbox as a selection. The remote gateway
configurator forces mode to tuning configurator without user
control.
E_Bnds_Vis Enables visibility of the parameters associated with the energy 0 to 2147483647
bands processing. This visibility is restricted to authorized GE
personnel and requires the correct code to enable visibility.
FFT_Length Defines the number of samples that will be used in FFT calculation 1024, 2048, 4096, 8192, 16382,
32768
FFT_TF_SelA Boolean that selects the internal test file as the input to all acoustic HW_Input to File
monitoring channels instead of the actual analog input signals
EventLstSel Defines the sample site for the event capture list: Disable to Avg_Out
Disable: list not used
FFT_Out: FFT output scaled in volts
TC_Out: FFT output after transducer compensation
PSI_Out: FFT outputs scaled in PSI
Avg_Out: PSI_Out after averaging filter
Raw_Input: Input time domain data
HiB_Limit Defines the limit for the max peak-peak amplitude signal in the 0 to 50 psi
high frequency band
HiScrchBrkPt Defines the frequency boundary between the high and screech 0 to 3200 Hz
frequency bands
LoLoB_Limit Defines the limit for the max peak-peak amplitude signal in the 0 to 50 psi
low-low frequency band
LowB_Limit Defines the limit for the max peak-peak amplitude signal in the 0 to 50 psi
low frequency band
LowLow_EndPt Defines the ending frequency of the low-low frequency band 0 to 5000 Hz
LowLowStrtPt Defines the starting frequency of the low-low frequency band 0 to 5000 Hz
LowMid_BrkPt Defines the frequency boundary between low and mid frequency 0 to 5000 Hz
bands
Low_StrtPt Defines the starting frequency of the low band 0 to 5000 Hz
MaxVoltCCSA Max sensor volts for a CCSA type sensor -30 to 30 V
MaxVoltCustm Max sensor volts for a custom type sensor -30 to 30 V
MaxVoltPCB Max sensor volts for a PCB type sensor -30 to 30 V
MidB_Limit Defines the limit for the max peak-peak amplitude signal in the 0 to 50 psi
mid frequency band

Parameter
MidHi_BrkPt Defines the frequency boundary between mid and high frequency 0 to 5000 Hz
bands
MinVoltCCSA Minimum sensor volts for a CCSA type sensor -30 to 30 V
MinVoltCustm Minimum sensor volts for a custom type sensor -30 to 30 V
MinVoltPCB Minimum sensor volts for a PCB type sensor -30 to 30 V
NumEventScns Defines the number of scans an event buffer contains 1 to 32 scans
*Note. If the sample location is Raw_Input the max scan allowed
is 1.
OpLstSel Defines sample site for spectrum on demand capture or diagnostic Disable to Avg_Out
list:
Disable: list not used
Raw_Input: input time domain data
PL_Fil_Freq Defines the power line frequency that the notch filter will remove 50 or 60 Hz
from the spectral content of the FFT output
PL_Fil_Tol Power line filter signature tolerance calculated vs theoretical. 0 to 1.0
10% = 0.1.
PL_Fil_Width Defines the bandwidth of the power line notch filter. The bandwidth 0 to 100 Hz
will be ± value centered about the configured power line frequency.
SampleRate Defines the FFT sample rate for all the acoustic monitoring 12,877 Hz only
channels
ScanPrAvgFFT Number of scans per average in acoustic monitoring filtered FFT 1 to 32 scans
output
ScanPrAvgRMS Number of scans per average in the RMS calculation 1 to 32 scans
SearchInAvg(1) – Selects whether the sort function for pk-pk amplitudes uses the No average, Average
SearchInAvg(6) present scan or an average value
Session_Time Scheduled time for temporary configuration mode. This time is 0
forced to zero in the ToolboxST entry. This value is set to the
user-selected time in the temporary gateway remote configurator.
ScrchB_Limit Defines the limit level for the maximum peak-peak amplitude 0 to 50 psi
signal in the screech frequency band
Scrch_EndPt Defines the ending frequency of the screech frequency band 0 to 5000 Hz
T_FilWidth Width (±Hz) of the filter that excludes the transverse frequency 0 to 100 Hz
FFT coefficients and all FFT coefficients designated by this filter
from the screech band search
TMC_Gain(1) – Transducer mounting compensation gain to characterize gain 0 to 10
TMC_Gain(30) response
TMC_Freq(1) – Frequency corresponding to the gain value entered 0 to 5000 Hz
MC_Freq(30)
TrnsB_Limit Defines the limit for the max peak-peak amplitude signal in the 0 to 50 Psi
transverse frequency band

Parameter
Trns_Bnd_Enb Enable calculations associated with the transverse band and Disable, Enable
exclude its FFT coefficients from the screech band
Trns_EndPt Defines the ending frequency of the transverse frequency band 0 to 5000 Hz
Trns_StrtPt Defines the starting frequency of the transverse frequency band 0 to 5000 Hz
WindowSelect Selects windowing function for sampled data for Channel A and B: Rectangular to Flat Top
Rectangular
Hamming
Hanning
Triangular
Blackman
Blackman-Har(ris)
Flat Top
Gain Analog input resolution adjustment to amplify signal before digital 1, 2, 4, 8 V / V
conversion. Gain factor * (maximum signal peak voltage) must be
less than 10 V to prevent saturation.
Bias Dc bias voltage subtracted from the analog signal input for dc bias -11.6 to +11.6 V dc
compensation. Only used when InputUse is custom or file.
Bias_Range Allowable deviation of dc bias used for dc bias diagnostics. Only -30 to 30 V
used when InputUse is custom or file.
Can_Id Combustor can be wired to this terminal board signal. This 1 to 18
normally corresponds to the signal number to avoid confusion;
wire terminal board signal 1 to can 1.
High_Input Defines point 2 X-axis value in mV for SAMB terminal point that is 0 to 9998.8 mV
used to calculate gain and offset for conversion to EU
High_Value Defines point 2 Y-axis value in EU for SAMB terminal point that is 0 to 99999 psi
used to calculate gain and offset for conversion from mV to EU
InputUse Selects the sensor type used on the signal. Unused, CCSA, PCB, Custom, File
If the CCSA in JB1000 is used, set InputUse

and the terminal board jumpers to CCSA
regardless of the transducer manufacturer.
Damage to the CCSA may occur if the PCB
Caution jumper setting is used on the terminal board.
Low_Input Defines point 1 X-axis value in mV for SAMB terminal point that is 0 to 9998.8 mV
used to calculate gain and offset for conversion to EU
Low_Value Defines point 1 Y-axis value in EU for SAMB terminal point that is 0 to 99999 psi
used to calculate gain and offset for the conversion from mV to EU
PL_Fil_En Enables the power line notch filter Disable, Enable
DiagHighEnab Enables high input sensor limit diagnostics Disable, Enable
DiagLowEnab Enables low input sensor limit diagnostics Disable, Enable
BiasNullEnab Enables automatic dc bias nulling Disable, Enable
DiagOCChk Enables open sensor error diagnostic test Disable, Enable
DiagBiasNull Enables excessive dc bias diagnostic test Disable, Enable
DiagSigSat Enables signal saturation diagnostic test Disable, Enable

PAMB Board Points
Board Points (Signals) Description – Point Edit (Enter Signal Connection) Direction Type
L3DIAG_PAMB Board Diagnostic active (non-voted signal) Input BIT
Can1_Health Combustor can 1 signal health Input BIT
: :
Test_Config Card is temporarily remotely configured Input BIT
Test_Mode Signals are from internal test sources, not from terminal Input BIT
board
TripCapList A capture list triggered by TripCapReq is available Input BIT
UserCapList A capture list manually requested by a user is available Input BIT
PambBool_1 General Electric Proprietary Information Input BIT
: :
PambBool_6 General Electric Proprietary Information Input BIT
PambPt_0 General Electric Proprietary Information Input INTEGER
: :
PambPt_317 General Electric Proprietary Information Input INTEGER
Num_Of_Scans Scan (block of FFT data) number of this data (1 – 32) Input INTEGER
Num_Avg_Scns Number of scans (block of FFT data) averaged (1 – 32) Input INTEGER
Session_Tmr Time remaining for remote tuning session Input INTEGER
TripCapReq Request for trip capture buffer collection Input BIT

SAMB Acoustic Monitoring Input
The Mark* VIe Acoustic Monitoring (SAMB) terminal board is a dual terminal board
providing 18 inputs for the Acoustic Monitoring System. SAMB provides two terminal
points per input channel for a maximum of 18 channels on 36 terminals. It also provides
an additional 18 buffered outputs on 36 terminals to connect external instrumentation
for monitoring the ac voltage signal that represents the dynamic pressure signals from
the combustor. SAMB includes passive electromagnetic interference (EMI) filters to
protect against very high frequency noise generated by external sources.
SAMB includes the following features:
• Eighteen signal interface channels for acoustic monitoring, supporting

dedicated-dual configuration
• Channels 1 – 9 are configurable to support PCB Piezotronics® sensors or charge
converter signal amplifier (CCSA) outputs. Sensor power for the PCB sensors
is independent of the sensor power for channels 10 – 18.
• Channels 10 – 18 are configurable to support PCB Piezotronics sensors
or CCSA outputs. Sensor power for the PCB sensors is independent
of the sensor power for channels 1 – 9.
• Eighteen buffered outputs providing ac signal content of the dynamic
pressure signals without dc bias voltage
• Thirty-six Euro-style terminal points for the customer inputs
• Thirty-six Euro-style terminal points for the buffered outputs
• EMI protection for all inputs
• EMI filtered inputs fanned to the A and B slots
Installation
Note A GE field service technician should install the PAMC. Technicians should refer
to Support Central website Acoustic Monitoring Module (PAMC) Installation in a Mark
VIe control, for complete installation instructions.
The figure, SAMB Acoustic Monitoring Terminal Board, shows the functionality of one
of the 18 channels supported by SAMB and PAMC. Connect the CCSA or PCB sensors
and the buffered outputs to the terminal blocks, as described in the table, Terminal
Point Definitions.
Hardware jumpers connect the constant current source to the SIGx line for the PCB
sensors. Each channel has hardware jumper, JPx (where x equals the input number).
The jumper should be in the CCSA position if the GE CCSA for Endevco® sensors or
any other voltage output device is used. The jumper should be in the PCB position
if a PCB sensor or any other current output device is used.

JA1/2 JB1/2
SIGx where x=1-18 SIGx SIGx

P15a 3.6mA
S 221K P24b
CCSA PCB
150K
P28a PCOM
RETx RETx RETx
BUFOUT1 BUFOUT1
BUFOUT18 BUFOUT18
P28A P28B
BAPA(1) BAPA(2)
Voltage
P15X
P15a, P28a & P24b Reg.
assignments per SIGx
PTC P1
x a b Voltage P28A
P24X1 P28X
1–4 X1 X Reg.
5–8 X2 X
9 – 12 Y1 Y
13 – 18 Y2 Y Voltage
P24X2
Reg.
Jumper Configuration for SIGx PTC P2

where x= 1 - 18 Voltage P28B
P24Y1 P28Y
Reg.
JPx pos. for JPx pos. for
PCB selection CCSA selection Voltage
CCSA P24Y2
CCSA Reg.
PCOM
Voltage
P15Y
PCB PCB Reg.
SAMB Acoustic Monitoring Terminal Board

Terminal Channels JPx Position Vendor Vendor Model Vendor I/O
Point (Two-pole) Connection
SIGx 1– 18 CCSA: Disables constant GE Energy Charge CCSA OUT+
RETx current and does not tie Converter Signal Amp OUT-
RETx to PCOM
SIGx 1 – 18 PCB: Enables constant PCB Piezotronics 111A21 102M158 Signal
RETx current and ties RETx to 102A05 102M170 Ground
PCOM 102M43 102M174
Terminal Variable Definitions
Ch. # Variable Signal Description Variable Signal Description

1 1 BUFOUT1 Buffered output, signal 2 SIG1 Dynamic pressure voltage, signal
3 BUFRET1 Buffered output, return 4 RET1 Dynamic pressure voltage, return

Operation
SAMB inputs an ac voltage signal from the CCSA proportional to the dynamic pressure
sensed by the Endevco pressure sensors. SAMB inputs the dynamic pressure directly
from PCB pressure sensors as an ac voltage riding on a dc bias voltage. The terminal
board provides configuration options to support the hardware listed in the figure:
SAMB Connections
Terminal Point Channels JPx Position Vendor Vendor Model Vendor I/O
(Two-pole) Connection
SIGx 1 – 18 CCSA: Disables GE Energy Charge CCSA OUT+
RETx constant current and Converter Signal OUT-
does not tie RETx to Amp
PCOM
SIGx 1 – 18 PCB: Enables PCB Piezotronics 111A21 102M158 Signal
RETx constant current 102A05 102M170 Ground
and ties RETx to 102M43 102M174
PCOM
Each channel provides a constant current source that can be connected to SIGx
(where x is the channel number) for the PCB sensors. The jumper JPx (where x
equals the channel number) is a two-pole jumper that controls the constant current
power supply and whether RETx is tied to the power ground, PCOM. When JPx
is in the CCSA position, the constant current is disabled and RETx is not tied to
PCOM. When JPx is in the PCB position, the constant current is connected to SIGx,
providing approximately 3 mA of current to power the PCB sensor. The RETx line
is tied to PCOM to provide a return path for the constant current.
A high impedance dc bias allows PAMB to detect an open connection

between the charge amplifier (or PCB sensor) and the SAMB terminal board.
Each input circuit has +28 V dc bias only.

Specifications
Item Specification
Power inputs 2 P28 inputs, each with a 2-pin connector
Bias circuit P28 on each channel with < 0.2 % dc error
Dc output gain 1 ±0.5%
Allowable offset on outputs 30 mV ±10%
Output impedance 40 Ω ±50%
Test points 2 with > ±10 V dc range, < 0.5% error tolerance, and = 2.5 mV / count resolution
Physical
Size 14.3 cm high x 23.1 cm wide (5.625 in x 9.1 in)
Cooling Free air convection
Humidity 5 to 95% non-condensing
Diagnostics
The SAMB terminal board has its own ID device, which is interrogated by PAMC.
The board ID is coded into a read-only chip containing the terminal board serial
number, board type, revision number, and the JA4 or JB4 connector location.
This ID is checked as part of the power-up diagnostics.

Notes

PAMC Acoustic Monitoring Input Module
Acoustic Monitoring Input (PAMC)

The Mark* VIe Acoustic Monitoring (PAMC) I/O module supports combustion
dynamics for all frame 6, 7, and 9 gas turbines. The PAMC I/O module includes
the IS215BAPAH1A Analog Processor (BAPA) and the Acoustic Monitoring
(SAMB) terminal board grouped together as an application subassembly, and
the IS220UCSAH1A standalone processor module.
PAMC accepts dynamic pressure data from SAMB. The analog signal is conditioned to
remove dc bias and amplify ac content (to maximize resolution) before it is digitized by an
analog-to-digital (A/D) converter. A field programmable gate array (FPGA) sequences,
digitizes, and filters the dynamic pressure signals and controls the high-speed serial
link (HSSL) protocol for the Ethernet link between the BAPA and UCSA.
The UCSA, which mounts as a standalone module, is a LAN module that serves
as the PAMC processing engine. The UCSA was selected for acoustic monitoring
because it provides the additional processing capacity required for the fast Fourier
transform (FFT) analysis, sorting function, sensor diagnostics, and so on.
Two versions of the Acoustic Monitoring system are offered, as follows:
Dual Acoustic Monitoring System (323A4747WCP4). SAMB fans all 18 inputs

to each BAPA. BAPA 1 (left) communicates with the UCSA connected to IONet R.
BAPA 2 (right) communicates with the UCSA connected to IONet S. The controller’s
application code votes which PAMC data to use, based on the signal health.
GEH-6721L PAMC Acoustic Monitoring Input Module System Guide 4-1

Mark VIe Duplex (two simplex) PAMC (323A4747WCP4)
Simplex Acoustic Monitoring System (323A4747WCP3) – Simplex version of

323A4747WCP3. Controller application code is not required to vote signals from PAMC.
Compatibility
PAMCH1A is compatible with the following acoustic monitoring terminal boards:
Terminal Board SAMBH1A

Control Mode Simplex - Yes Dual - No TMR - No

Installation
The installation procedures in this document only cover the addition of the PAMC
I/O module into a Mark VIe system without using the PAMC signal space inputs. A
qualified GE technician must install the PAMC signal space inputs.
Refer to the section, SAMB Installation to install the SAMB terminal

board and dynamic pressure inputs.

Wizard again.
ToolboxST Procedures
¾ To add a PAMC control I/O pack
1. From the Mark VIe Component Editor, click the Hardware tab.
2. From the Tree View, right-click the Distributed I/O item and select Add
Module. The Add Module Wizard displays.
Select the I/O pack

Redundancy type:
Simplex
.
Select PAMC as
module type.
.
Click Next.

Use the Version drop-down list to select a
module version. Listed module versions
depend on the available compatibility codes.
Click the Release

Notes button to view
additional information
about the currently
selected module
version.
To ensure that hardware

failures are identified
and corrected prior to
controller system
operation, it is highly
recommended that the
Module Required check
box be selected. If it is,
the module must be
present and functioning
for the controller to go
online.
Click Next to
preview
configuration
information.

Click Finish to
add the new
module.

¾ To add a SAMB module
1. From the Component Editor, click the Hardware tab.
From the Tree View,

right-click the Port_S1
item, then select
Attach and SAMB.
2. The Configure Sub-Assembly SAMB dialog box displays.
After sending Build and Download

commands to the controller, click
this button to retrieve the Bar Code.
Note Additional attachments cannot be added to other ports.
3. Enter the TB Connector that the BAPA is plugged into and the Bar Code of the
SAMB. The bar code is located underneath the cover plate over the JB4 connector if
no BAPA is plugged into this connector. If a BAPA is plugged into JB4, remove this
BAPA to view the bar code or use the bar code retrieval method from step two.

Operation
The PAMC includes the following features.
• Signal conditioning for up to 18 combustion dynamic pressure inputs:

− GE Energy Charge-Converter Signal Amplifier (CCSA) or Piezotronics®
sensors for heavy-duty turbines are supported
− Differential inputs and adjustable gains
− Fast synchronous-sampled A/D with 16x over-sampling
− FPGA pre-processor with finite impulse response (FIR) filters
− Open wire detection
• Analysis capability per channel:
− Windowed FFT analysis
− Rolling average per bin
− 50/60 Hz rejection filters
− Sort function providing peak pressure amplitude for six different frequency bands
− Maximum peak detect for each frequency band
− Average channel peak-to-peak amplitudes per frequency band
− Alarm detection if peak-to-peak amplitude exceeds configurable
level for each frequency band
− List capture for all 18 channels if alarm is detected or user requests capture

UCSA Processor
The UCSA processor module contains a processor board (IS200UCSAH1A).
• High-speed processor with random access memory (RAM) and flash memory
• Two fully-independent 10/100 Ethernet ports with connectors Enet1 and Enet2
for connecting to the main controllers' IONet ports.
• Three fully-independent high speed serial link ports with connectors
R/SL1, S/SL2, T/SL3. Only R/SL1 is used in the PAMC for connecting
to a IS210BAPAH1A analog processor board.
• One universal asynchronous receiver-transmitter (UART) type serial
port with RJ-45 connector
• Status-indication LEDs (refer to Status LEDs section)
• Electronic ID
• Compact flash support
UCSA connects to BAPA through the R/SL1 high speed serial link (HSSL) interface. The
PAMC is designed so that the UCSA and the BAPA can be located in different locations
(up to 100 meters of high speed serial link cable length). Each module can be powered
independently. At power up, the BAPA waits for UCSA to initiate communications.
After communication is established, the application FPGA is programmed.
The processor application code contains the logic to allow a UCSA to operate on one or
two IONet inputs. When using two IONet inputs, both network paths are active at all
times. A failure of either network does not disturb I/O pack operation and is indicated
through the working network connection. This arrangement is more tolerant of faults than
a classic hot-backup system in which the second port is only used after a primary port
failure is detected. The Ethernet ports on the UCSA auto-negotiate between 10 MB/s

BAPA Analog Processor
The analog processor includes the following features:
• Eighteen analog signal-conditioning channels

− Differential inputs
− Adjustable gains of 1x, 2x, 4x, and 8x
− Dc bias nulling
− Multiplexer to bypass signal input and apply test signal
− Anti-alias filters to support 5 kHz bandwidth
• Twenty-four A/D input channels
− Six channels per converter
− 16-bit converter
• Application FPGA
− A/D converter control
− D/A converter control
− Eighteen channels of FIR filtering
− Configuration registers
− HSSL control
• Boots FPGA with programmable read-only memory (PROM)
− Bootstrap function
− TX / RX mini-MACs
− PHY sync
• PHY0 and PHY1 physical Ethernet layers
• Power supplies
− P28 input
− P15 and N15 outputs
− P5 output
− 3.3 V, 2.5 V, and 1.2 V outputs



UCSA LEDs
The UCSA module has the following LEDs:
• Power displays solid green when the internal 5 V supply is up and

regulating. The PAMC converts the incoming 28 V dc to 5 V dc. All
other internal supplies are derived from the 5 V.
• Boot displays solid red or blinking red during the boot process. The
boot blink codes are described below.
• Online displays solid green when the PAMC is online and running application code.
• Flash blinks amber when any flash device is being accessed. DC is
not used in the PAMC application.
• Diag displays solid red when the PAMC has a diagnostic available. The diagnostic
can be viewed and cleared using the ToolboxST* application.
• Link displays solid green if the Ethernet hardware interface on the PAMC
has established a link with an Ethernet port.
• Act indicates packet traffic on an Ethernet interface. If traffic is low, this
LED may blink but in most systems, it is on solid.
• On displays solid green when the USB is active.
The boot LED is lit continuously during the boot process unless an error is detected.
If an error is detected, the LED flashes at a 1 Hz frequency. While flashing, the
LED is on for 500 ms and off for 500 ms. The number of flashes indicates the failed
state. After the flashing section, the LED turns off for three seconds.
• 1: Failed Serial Presence Detect (SPD) EEPROM

• 2: Failed to initialize DRAM or DRAM tests failed
• 3: Failed NOR flash file system check
• 4: Failed to load FPGA or PCI failed
• 5: Compact Flash device not found
• 7: Compact Flash image not valid
If the CompactFlash image is valid but the runtime firmware has not
been loaded, the boot LED flashes continuously at a 1 Hz rate. Once the
firmware is loaded, the boot LED turns off.

UCSA Boot LED Flashing Codes
The boot LED is lit continuously during the boot process unless an error is detected.
If an error is detected, the LED flashes at a 1 Hz frequency. While flashing, the
LED is on for 500 ms and off for 500 ms. The number of flashes indicates the failed
state. After the flashing section, the LED turns off for three seconds.
• 1: Failed Serial Presence Detect (SPD) EEPROM

• 2: Failed to initialize DRAM or DRAM tests failed
• 3: Failed NOR flash file system check
• 4: Failed to load FPGA or PCI failed
• 5: Compact Flash device not found
• 7: Compact Flash image not valid
If the CompactFlash image is valid but the runtime firmware has not
been loaded, the boot LED flashes continuously at a 1 Hz rate. Once the
firmware is loaded, the boot LED turns off.
BAPA LEDs
Note To follow the procedure for programming the CompactFlash, refer to GEH-6700,
ToolboxST Guide for Mark VIe Control for details. The CompactFlash programmer can
be a PCMCIA adapter or a USB device.
The BAPA module has the following LEDs:
• PWR displays solid green when 28 volt power is present.

• ATTN will display solid red for about a half second on power applied and will then
go dark. If a valid serial link has been established with the host UCSA, configuration
will be downloaded to the BAPA and then the LED will display solid green.
• Link displays solid green if the high speed serial link interface on the BAPA
has established a proper link with a UCSA serial port.
• Tx/Rx indicates packet traffic on the high speed serial link. This LED
will blink green when this traffic is present.

Acoustic Monitoring Firmware
The acoustic monitoring firmware supports 18 input channels. The main features are:
• RMS Broadband Calculation – Calculates the broadband root-mean-square

(RMS) energy of the time-domain sampled data in the frequency range of 0 to
5000 Hz. The output is the input of the RMS Scan Average.
• RMS Scan Average – Average multiple scans of broadband RMS values. A scan
is defined by the amount of time-domain sampled combustion data to calculate
a windowed FFT of some defined length. The output is the system input, SIGx
(where x is the channel number), passed to the controller.
• Windowed FFT – Calculates the frequency domain peak-to-peak magnitude
and bin frequency, based on time-domain sampled combustion input data.
The configuration defines the type of FFT window function used, the FFT
length (amount of input data collected for the calculation), and the sample
frequency. The output feeds the Peak-to-Peak Scan Average.
• Peak-to-Peak Scan Average – Provides a frequency domain peak-to-peak
magnitude average per frequency bin, over multiple scans. The configuration
defines the number of scans used in the rolling average calculation. The
output is the input for the Six-Band Sort function.
• Six-Band Sort – Average frequency domain peak-to-peak data is sorted into six
separate frequency bands, as displayed in the following table.
Frequency Bands
Freq Band # Configuration Band Name

1 Low (Low)
2 Middle (Mid)
3 High (High)
4 Low Low (LoLo)
5 Trans (Trns)
6 Screech (Scrch)

The maximum of the average peak-to-peak magnitudes from each frequency band and its
corresponding frequency bin are selected and output as system inputs for the controller.
• Band n Average – Calculates the average peak-to-peak magnitude over all enabled
healthy input channels, based on the output of the Six-Band Sort.
• Band n Maximum – Calculates the maximum peak-to-peak magnitude over
all input channels enabled, based on the Six-Band Sort data. The six frequency
band maximums are output for use by the controller.
• Band n Limit Check – A frequency band limit check based on
the Band n Maximum output data.
RMS Sig1 SIG_1

RMS Scan
Broadband
Avg Sigx SIG_18
Calc
where ch x = 1 - 18
6-Band Sort FrqB1_PkAmp1
FrqB1_PkHz1
Select a maximum
pk-pk amplitude for
each of the 6 FrqBn_PkAmpx
configurable FrqBn_PkHzx S
frequency bands where band n = 1 - 6 I
& ch x = 1 - 18 G
Band n Avg.
FrqB1_AmpAvg N
Average channels 1 A
thru x in Freq. L
Pk-Pk Scan Avg
Band n FrqBn_AmpAvg
FrqB1_AmpMx S
FrqB1_HzMx P
Band n Max. FrqB1_ChMx A
C
Sel max. mag.
FrqBn_AmpMx
E
from the x
FrqBn_HzMx
ch(s) for Freq.
Band n FrqBn_ChMx I
Band n where band n = 1 - 6
Ch 1 Limit N
Check P
Ch 2 FrqB1_LmtSet
U
Windowed
Check T
FFT
Band n S
FrqBn_LmtSet
Max. out
where band n = 1 - 6
Ch x against
where x = 1 - 18 Limit.
Acoustic Monitoring Block Diagram
A/D Compensation
The A/D compensation function eliminates any gain or offset error due to initial
component inconsistency. An auto-calibration function runs each time the module
is reset. The auto-calibration function compares each of the 18 analog channels
against a standard A/D channel. This A/D channel is calibrated using a standard
high-precision voltage reference and the A/D common.

Input Units to Engineering Value Conversion
The Acoustic Monitoring System converts the hardware input units to the engineering
units (EU) needed for the system calculation. For the conversion of mV to psi,
the range is 20 to 600 mV per psi. Four configuration parameters are provided
per channel to define the equation for the transfer function.
Value (EU in counts) = GUnitConversion * Input (millivolts in counts) + Offset
where
GUnitConversion = (High_Value – Low_Value) / (High_Input – Low_Input)
Offset = High_Value - GUnitConversion * High_Input
where High_Value, Low_Value, High_Input + Low Input are the configuration parameters.
A/D Gain Adjust

The configuration parameter, Gain, controls the channel gain in the hardware. This
parameter is defined for each channel. This allows low-level signals to be amplified
to provide better resolution in the A/D conversion hardware. The gain options are
1x, 2x, 4x, and 8x. The channel control writes the gain setup to the FPGA input
amplifier 4x and 2x gain control registers. The signal level calculated by PAMC
firmware does not change with the Gain parameter because the signal is divided by
the gain factor in the firmware, resulting in a net gain of 1 for the signal regardless
of the gain factor used. The maximum expected signal level should not exceed 10 V
(saturation) after the gain is applied as indicated in the following table.
Rules for Selecting Gain Value
Gainx Maximum magnitude of input signal after

dc bias is removed (volts)
1 10
2 5
4 2.5
8 1.25
RMS Calculation and Rolling Average

The RMS calculation function performs an RMS calculation on the ac acoustic
information sampled for a given scan. The RMS is defined as follows:
rms_Chx = SQRT ( (AC_Input(0)**2 + AC_Input(1)**2 + … +

AC_Input(Buffer_Length)**2) / Buffer_Length)
Where x is the channel number.
The rolling average function provides a smoothing function to reduce

the vibration in the signal.

Capture Buffers
Two capture buffers are available, as follows:
• Trip Capture Buffers - This function provides capture buffers that input internally
calculated data, which is selected based on a configuration parameter. The capture
buffers can be configured (parameter NumEventScans) to capture up to 32 scans of
information for each of 18 channels. Parameter EventListSel can be used to configure
the trip capture buffer to collect any one of the following internal data:
• Time-domain sampled input data (in volts)
• Frequency-domain FFT peak-to-peak magnitude (in volts)
• FFT output data with transducer compensation (in volts)
• FFT output data with transducer compensation (in EU)
• Scan-averaged FFT output data with transducer compensation (in EU) (default)
Trip Capture Buffers are pre-triggered; meaning for a 32 scan FFT average, data
is scanned 32 times before the triggered event and none after the event. The
triggered event is activated by the signal space input, TripCapReq. Running on
the HMI or OSM computer, AM Gateway software uploads the captured buffers
to the computer on which the Gateway is running.
Ch x AC sampled data (volts) Capture selected Ch 1 Capture Buffer TripCapList

S data for each
Ch x Windowed FFT data (volts) Ch 2 Capture Buffer
e channel. Number
l of data samples Ch 3 Capture Buffer
Ch x FFT w Transducer Compensation (volts) e determined by the
Ch x FFT w Transducer Compensation (EU) c FFT length and
t number of Scans
averaged. Ch 18 Capture Buffer
Ch x FFT w Trans Comp & Scan Avged (EU)
TripCapReq Start Capturing data
Trip Capture Buffers
PAMC Acoustic Monitoring Diagnostic Support
• User Capture Buffers - This function provides capture buffers that are only one
scan in length (compared to the trip capture with up to 32 scans). The user capture
buffers can be configured using parameter OpListSel to collect any of the internal
data listed above for trip capture buffers. The AM Gateway software can upload
these buffers. User capture buffers are activated through the AM Gateway or
other compatible applications. The diagram shown above for trip capture buffers
is the same for user capture buffers except for the trigger source.

Specifications
Item Specification
Gain adjustment options 1x, 2x, 4x, and 8x
Bias - minimum adjust -13.5 ±0.25 V dc
Bias - maximum adjust +13.5 ±0.25 V dc
Input accuracy from terminal point to inputs, SIGx for passband = ≤ 2.0 % of full scale = 10 V dc for Gain = 1x
0 to 5 kHz ≤ 2.0 % of full scale = 5 V dc for Gain = 2x
-space values through FFT analysis for passband = 0 to 3.2 kHz ≤ 0.5 % of full scale = 5 V dc for Gain = 2x
-space values through FFT analysis for passband = 3.2 kHz to 5 ≤ 2.0 % of full scale = 5 V dc for Gain = 2x
kHz ≤ 2.0 % of full scale = 2.5 V dc for Gain = 4x
Input passband frequency 0 to 5 kHz
Diagnostics
• A power-up self test that includes checks of RAM, flash memory, Ethernet
and processor board ID to confirm that the hardware set matches, followed by a check
• Each input has sensor limit checking, open circuit detection, dc bias autonulling,
and excessive dc bias detection. Alarms are generated for these diagnostics.
Refer to the tables I/O Pack Alarms and Point Configuration.
Details of the individual diagnostics are available in the ToolboxST application. I/O
block SYS_OUTPUTS, input RSTDIAG can be used to direct all I/O modules to
clear from the alarm queue all diagnostics in the normal healthy state.

Configuration
Parameter Description (SAMB Level Configuration) Choices

BinReject Defines the number of side bins that are rejected when the 0 to 6 (default: 3)
search function is applied to the FFT results for channels 1 -
18, = no bins rejected
Config_Mode Defines the source of the currently active configuration. Toolbox only
ToolboxST allows only mode Toolbox as a selection.
The remote gateway configurator forces mode to tuning
configurator without user control.
E_Bnds_Vis Enables visibility of the parameters associated with the 0 to 2147483647 (default: 0)
energy bands processing. This visibility is restricted to
authorized GE personnel and requires the correct code to
enable visibility.
FFT_Length Defines the number of samples that are used in FFT 1024, 2048, 4096, 8192, 16382,
calculation 32768 (default: 8192)
FFT_TF_SelA Boolean that selects the internal test file as the input to all HW_Input or File (default: HW.Input)
acoustic monitoring channels instead of the actual analog
input signals
EventLstSel Defines the sample site for the event capture list: Avg_Out, Disable, FFT_Out,
Disable: list not used PSI_Out, Raw_Input, TC_Out
FFT_Out: FFT output scaled in volts (default: Avg_Out)
Raw_Input: Input time domain data
HiB_Limit Defines the limit for the max peak-peak amplitude signal 0 to 50 psi (default: 50)
in the high frequency band
HiScrchBrkPt Defines the frequency boundary between the high and 0 to 5000 Hz (default: 500)
screech frequency bands
LoLoB_Limit Defines the limit for the max peak-peak amplitude signal in 0 to 50 psi (default: 50)
the low-low frequency band
LowB_Limit Defines the limit for the max peak-peak amplitude signal in 0 to 50 psi (default: 50)
the low frequency band
LowLow_EndPt Defines the ending frequency of the low-low frequency band 0 to 5000 Hz (default: 30)
LowLowStrtPt Defines the starting frequency of the low-low frequency band 0 to 5000 Hz (default: 10)
LowMid_BrkPt Defines the frequency boundary between low and mid 0 to 5000 Hz (default: 120)
frequency bands
Low_StrtPt Defines the starting frequency of the low band 0 to 5000 Hz (default: 30)
MaxVoltCCSA Max sensor volts for a CCSA type sensor -30 to 30 V (default: 8.658)
MaxVoltCustm Max sensor volts for a custom type sensor -30 to 30 V (default: 5.29)
MaxVoltPCB Max sensor volts for a PCB type sensor -30 to 30 V (default: 4.75)

MidB_Limit Defines the limit for the max peak-peak amplitude signal in 0 to 50 psi (default: 50)
the mid frequency band
MidHi_BrkPt Defines the frequency boundary between mid and high 0 to 5000 Hz (default: 240)
frequency bands
MinVoltCCSA Minimum sensor volts for a CCSA type sensor -30 to 30 V (default: 8.658)
MinVoltCustm Minimum sensor volts for a custom type sensor -30 to 30 V (default: 5.25)
MinVoltPCB Minimum sensor volts for a PCB type sensor -30 to 30 V (default: -15.25)
NumEventScns Defines the number of scans an event buffer contains 1 to 100 scans (default: 32)
*Note. If the sample location is Raw_Input the max scan
allowed is 1.
OpLstSel Defines sample site for spectrum on demand capture or Avg_Out, Disable, FFT_Out,
diagnostic list: PSI_Out, Raw_Input, TC_Out
Disable: list not used (default: Avg_Out)
Raw_Input: input time domain data
PL_Fil_Freq Defines the power line frequency that the notch filter 50_Hz, 60_Hz
removes from the spectral content of the FFT output (default: 60_Hz)
PL_Fil_Tol Power line filter signature tolerance calculated vs theoretical. 0 to 1.0 (default: 0.1)
10% = 0.1.
PL_Fil_Width Defines the bandwidth of the power line notch filter. The 0 to 100 Hz (default: 0.5)
bandwidth is ± value centered about the configured power
line frequency.
SampleRate Defines the FFT sample rate for all the acoustic monitoring 12,877 Hz only
channels
ScanPrAvgFFT Number of scans per average in acoustic monitoring filtered 1 to 100 scans (default: 48)
FFT output
ScanPrAvgRMS Number of scans per average in the RMS calculation 1 to 32 scans (default: 1)
SearchInAvg(1) – Selects whether the sort function for pk-pk amplitudes uses No average, Average (default:
SearchInAvg(6) the present scan or an average value Average)
Session_Time Scheduled time for temporary configuration mode. This time 0 only
is forced to zero in the ToolboxST entry. This value is set
to the user-selected time in the temporary gateway remote
configurator.
ScrchB_Limit Defines the limit level for the maximum peak-peak amplitude 0 to 50 psi (default: 50)
signal in the screech frequency band
Scrch_EndPt Defines the ending frequency of the screech frequency band 0 to 5000 Hz (default: 3000)
T_FilWidth Width (±Hz) of the filter that excludes the transverse 0 to 100 Hz (default: 40)
frequency FFT coefficients and all FFT coefficients
designated by this filter from the screech band search
TMC_Gain(1) – Transducer mounting compensation gain to characterize 0 to 30 (default: 1)
TMC_Gain(30) gain response

TMC_Freq(1) – Frequency corresponding to the gain value entered 0 to 5000 Hz (default: n*100)
MC_Freq(30)
TrnsB_Limit Defines the limit for the max peak-peak amplitude signal in 0 to 50 Psi (default: 50)
the transverse frequency band
Trns_Bnd_Enb This enables calculations associated with the transverse Disable, Enable
band and excludes its FFT coefficients from the screech (default: Enable)
band. Bands other than the screech are not affected by
this function even if Trns_StrtPt and Trns_EndPt overlap
the other bands.
Trns_EndPt Defines the ending frequency of the transverse frequency 0 to 5000 Hz (default: 1150)
band
Trns_StrtPt Defines the starting frequency of the transverse frequency 0 to 5000 Hz (default: 950)
band
WindowSelect Selects windowing function for sampled data for Channel Rectangular
A and B: Hamming
Hanning
Triangular
Blackman
Blackman-Har(ris)
Flat Top

IS200SAMB Variable Definitions and Configuration
Sigx Analog input x – Card Point Point Edit (Input FLOAT)

Where x = 1 thr
18
Gain Analog input resolution adjustment to amplify signal before 1x, 2x, 4x, 8x (default: 8x)
digital conversion. Gain factor * (maximum signal peak voltage)
must be less than 10 V to prevent saturation.
Bias Dc bias voltage subtracted from the analog signal input for dc -11.67 to 11.67 (default: 0)
bias compensation. Only used when InputUse is custom or file.
Bias_Range Allowable deviation of dc bias used for dc bias diagnostics. 0 to 10 (default: 1)
Only used when InputUse is custom or file.
Can_Id Combustor can be wired to this terminal board signal. This 1 to 18 (default: 11)
normally corresponds to the signal number to avoid confusion;
wire terminal board signal 1 to can 1.
High_Input Defines point 2 X-axis value in mV for SAMB terminal point that -10000 to 10000 (default: 170)
is used to calculate gain and offset for conversion to EU
High_Value Defines point 2 Y-axis value in EU for SAMB terminal point that Any positive real (default: 1)
is used to calculate gain and offset for conversion from mV
to EU
InputUse Selects the sensor type used on the signal. Unused, CCSA, PCB, Custom, File
(default: Unused)
If the CCSA in JB1000 is used, set InputUse
and the terminal board jumpers to CCSA
regardless of the transducer manufacturer.
Damage to the CCSA may occur if the
PCB jumper setting is used on the terminal
Caution board.
Low_Input Defines point 1 X-axis value in mV for SAMB terminal point that -10000 to 10000
is used to calculate gain and offset for conversion to EU
Low_Value Defines point 1 Y-axis value in EU for SAMB terminal point that Any positive real (default: 0)
is used to calculate gain and offset for the conversion from mV
to EU
PL_Fil_En Enables the power line notch filter Disable, Enable (default: Disable)
DiagHighEnab Enables high input sensor limit diagnostics Disable, Enable (default: Enable)
DiagLowEnab Enables low input sensor limit diagnostics Disable, Enable (default: Enable)
BiasNullEnab Enables automatic dc bias nulling Disable, Enable (default: Enable)
DiagOCChk Enables open sensor error diagnostic test Disable, Enable (default: Enable)
DiagBiasNull Enables excessive dc bias diagnostic test Disable, Enable (default: Enable)
DiagSigSat Enables signal saturation diagnostic test Disable, Enable (default: Enable)

IS200SAMB Signal Definitions
L3DIAG_SAMB_R(S or T) Board Diagnostic active (non-voted signal) Input BIT
LINK_OK_SAMB_R(S or T) High speed serial link SL1 is communicating with BAPA Input BIT
ATTN_SAMB SAMB has an active alarm Input BIT
Test_Config PAMC is temporarily remotely configured Input BIT
Test_Mode Signals are from internal test sources, not from terminal board Input BIT
TripCapList A capture buffer triggered by TripCapReq is available Input BIT
UserCapList A capture buffer manually requested by a user is available Input BIT
Num_Of_Scans Scan (block of FFT data) number of this data (1 – 100) Input INTEGER
Num_Avg_Scns Number of scans (block of FFT data) averaged (1 – 100) Input INTEGER
Session_Tmr Time remaining for remote tuning session Input INTEGER
TripCapReq Request for trip capture buffer collection Output BIT
: :
FrqB1_LmtSet All cans, Low Band, Peak amplitude exceeds LowB_Limit Input BIT
FrqB2_LmtSet All cans, Mid Band, Peak amplitude exceeds MidB_Limit Input BIT
FrqB3_LmtSet All cans, Hi Band, Peak amplitude exceeds HiB_Limit Input BIT
FrqB4_LmtSet All cans, LoLo Band, Peak amplitude exceeds LoLoB_Limit Input BIT
FrqB5_LmtSet All cans, Transverse Band, Peak amplitude exceeds TrnsB_Limit Input BIT
FrqB6_LmtSet All cans, Screech Band, Peak amplitude exceeds ScrchB_Limit Input BIT
FrqBn_PkAmpm Peak amplitude detected in band n can m (PSI) Input Float
Where m=1-18 can number
n=1 for low band
n=2 for mid band
n=3 for hi band
n=4 for lolo band
n=5 for transverse band
n=6 for screech band
FrqBn_PkHzm Peak frequency for the peak amplitude FrqBn_PkAmpm in can Input Float
m band n (Hz)
FrqBn_AmpMx Peak Amplitude detected in all cans in band n (PSI) Input Float
Where
n=1 for low band
n=2 for mid band
n=3 for hi band
n=4 for lolo band
n=5 for transverse band
n=6 for screech band
FrqBn_HzMx Peak frequency for the peak amplitude FrqBn_PkAmpMx Input Float
detected in all cans band n (Hz)

FrqBn_ChMx Can number for the peak amplitude FrqBn_PkAmpMx detected Input Float
in all cans band n
FrqBn_AmpAvg Average peak amplitude in all cans band n (PSI) Input Float
BAPA_Temptur BAPA module (plugged into terminal board) temperature (deg C) Input Float
LowLowStrtPt Starting frequency of Low-Low Band (Hz) Input Float
LowLow_EndPt Ending frequency of Low-Low Band (Hz) Input Float
Low_StrtPt Starting frequency of Low Band (Hz) Input Float
LowMid_BrkPt Breakpoint frequency between Low Band and Mid Band (Hz) Input Float
MidHi_BrkPt Breakpoint frequency between Mid Band and High Band (Hz) Input Float
HiScrchBrkPt Breakpoint between High and Screech Band (Hz) Input Float
Trns_StrtPt Starting frequency of Transverse Band (Hz) Input Float
Trns_EndPt Ending frequency of Transverse Band (Hz) Input Float
Scrch_EndPt Ending frequency of Screech Band (Hz) Input Float
FFT_Length Length of the FFT Buffer (samples) Input Float
Sample_Rate FFT Sample Rate (Hz) (Hz) Input Float
ScanPrAvgFFT Number of Scans Per Average in the FFT output Input Float

SAMB Acoustic Monitoring Input
The Mark* VIe Acoustic Monitoring (SAMB) terminal board is a dual terminal board
providing 18 inputs for the Acoustic Monitoring System. SAMB provides two terminal
points per input channel for a maximum of 18 channels on 36 terminals. It also provides
an additional 18 buffered outputs on 36 terminals to connect external instrumentation
for monitoring the ac voltage signal that represents the dynamic pressure signals from
the combustor. SAMB includes passive electromagnetic interference (EMI) filters to
protect against very high frequency noise generated by external sources.
SAMB includes the following features:
• Eighteen signal interface channels for acoustic monitoring, supporting

dedicated-dual configuration
• Channels 1 – 9 are configurable to support PCB Piezotronics® sensors or charge
converter signal amplifier (CCSA) outputs. Sensor power for the PCB sensors
is independent of the sensor power for channels 10 – 18.
• Channels 10 – 18 are configurable to support PCB Piezotronics sensors
or CCSA outputs. Sensor power for the PCB sensors is independent
of the sensor power for channels 1 – 9.
• Eighteen buffered outputs providing ac signal content of the dynamic
pressure signals without dc bias voltage
• Thirty-six Euro-style terminal points for the customer inputs
• Thirty-six Euro-style terminal points for the buffered outputs
• EMI protection for all inputs
• EMI filtered inputs fanned to the A and B slots
Installation
Note A GE field service technician should install the PAMC. Technicians should refer
to Support Central website Acoustic Monitoring Module (PAMC) Installation in a Mark
VIe control, for complete installation instructions.
The figure, SAMB Acoustic Monitoring Terminal Board, shows the functionality of one
of the 18 channels supported by SAMB and PAMC. Connect the CCSA or PCB sensors
and the buffered outputs to the terminal blocks, as described in the table, Terminal
Point Definitions.
Hardware jumpers connect the constant current source to the SIGx line for the PCB
sensors. Each channel has hardware jumper, JPx (where x equals the input number).
The jumper should be in the CCSA position if the GE CCSA for Endevco® sensors or
any other voltage output device is used. The jumper should be in the PCB position
if a PCB sensor or any other current output device is used.

JA1/2 JB1/2
SIGx where x=1-18 SIGx SIGx

P15a 3.6mA
S 221K P24b
CCSA PCB
150K
P28a PCOM
RETx RETx RETx
BUFOUT1 BUFOUT1
BUFOUT18 BUFOUT18
P28A P28B
BAPA(1) BAPA(2)
Voltage
P15X
P15a, P28a & P24b Reg.
assignments per SIGx
PTC P1
x a b Voltage P28A
P24X1 P28X
1–4 X1 X Reg.
5–8 X2 X
9 – 12 Y1 Y
13 – 18 Y2 Y Voltage
P24X2
Reg.
Jumper Configuration for SIGx PTC P2

where x= 1 - 18 Voltage P28B
P24Y1 P28Y
Reg.
JPx pos. for JPx pos. for
PCB selection CCSA selection Voltage
CCSA P24Y2
CCSA Reg.
PCOM
Voltage
P15Y
PCB PCB Reg.
SAMB Acoustic Monitoring Terminal Board

Terminal Channels JPx Position Vendor Vendor Model Vendor I/O
Point (Two-pole) Connection
SIGx 1– 18 CCSA: Disables constant GE Energy Charge CCSA OUT+
RETx current and does not tie Converter Signal Amp OUT-
RETx to PCOM
SIGx 1 – 18 PCB: Enables constant PCB Piezotronics 111A21 102M158 Signal
RETx current and ties RETx to 102A05 102M170 Ground
PCOM 102M43 102M174


Operation
SAMB inputs an ac voltage signal from the CCSA proportional to the dynamic pressure
sensed by the Endevco pressure sensors. SAMB inputs the dynamic pressure directly
from PCB pressure sensors as an ac voltage riding on a dc bias voltage. The terminal
board provides configuration options to support the hardware listed in the figure:
SAMB Connections
Terminal Point Channels JPx Position Vendor Vendor Model Vendor I/O
(Two-pole) Connection
SIGx 1 – 18 CCSA: Disables GE Energy Charge CCSA OUT+
RETx constant current and Converter Signal OUT-
does not tie RETx to Amp
PCOM
SIGx 1 – 18 PCB: Enables PCB Piezotronics 111A21 102M158 Signal
RETx constant current 102A05 102M170 Ground
and ties RETx to 102M43 102M174
PCOM
Each channel provides a constant current source that can be connected to SIGx
(where x is the channel number) for the PCB sensors. The jumper JPx (where x
equals the channel number) is a two-pole jumper that controls the constant current
power supply and whether RETx is tied to the power ground, PCOM. When JPx
is in the CCSA position, the constant current is disabled and RETx is not tied to
PCOM. When JPx is in the PCB position, the constant current is connected to SIGx,
providing approximately 3 mA of current to power the PCB sensor. The RETx line
is tied to PCOM to provide a return path for the constant current.
A high impedance dc bias allows PAMB to detect an open connection

between the charge amplifier (or PCB sensor) and the SAMB terminal board.
Each input circuit has +28 V dc bias only.

Specifications
Item Specification
Power inputs 2 P28 inputs, each with a 2-pin connector
Bias circuit P28 on each channel with < 0.2 % dc error
Dc output gain 1 ±0.5%
Allowable offset on outputs 30 mV ±10%
Output impedance 40 Ω ±50%
Test points 2 with > ±10 V dc range, < 0.5% error tolerance, and = 2.5 mV / count resolution
Physical
Diagnostics
The SAMB terminal board has its own ID device, which is interrogated by PAMC.
The board ID is coded into a read-only chip containing the terminal board serial
number, board type, revision number, and the JA4 or JB4 connector location.
This ID is checked as part of the power-up diagnostics.

PAOC Analog Output Module
Analog Output (PAOC)

The Analog Output (PAOC) pack provides the electrical interface between one
ANALOG OUT
PWR
or two I/O Ethernet networks and an analog output terminal board. The pack
ENA1 contains a processor board common to all Mark* VIe distributed I/O packs and an
ATTN
ENA2 acquisition board pair specific to the analog output function. The pack is capable of
providing up to eight simplex 0-20 mA current loop outputs and includes an analog
LINK to digital converter for current feedback from each output.
ENET1
ENA3
TxRx
ENA4
Input to the pack is through dual RJ45 Ethernet connectors and a three-pin power
ENA5
LINK input. Output is through a DC-37 pin connector that connects directly with the
ENET2
TxRx
associated terminal board connector. Visual diagnostics are provided through
ENA6 indicator LEDs.
IR PORT
ENA7
ENA8
IS220PAOCH1A
PAOCH1A
Analog Output BPPB
BPAOH1A Pack processor board
board
Single or dual
Ethernet cables
ENET1
TBAO Analog
Output Terminal
Board ENET2
External 28 V dc
Analog Outputs power supply
(8 or 16)
Two PAOC packs for 16

outputs ENET1
ENET2
One PAOC pack for 8
outputs
28 V dc
GEH-6721L PAOC Analog Output Module System Guide 5-1

Compatibility
PAOCH1A is compatible with the analog output terminal board TBAOH1C,
and the STAO board, but not the DIN-rail mounted DTAO board. The
following table gives details of the compatibility:
Terminal Board TBAOH1C DTAO STAOH1A

Control mode Simplex-yes Dual - no TMR-no No Simplex-yes
While the PAOC will mount on a TBAOH1A or TBAOH1B terminal board, the pack will
not realize full accuracy of the analog signals due to circuit differences between the terminal
board revisions. For this reason, the PAOC is only compatible with the H1C version of
TBAO and will report a board compatibility problem with any of the earlier revisions.
No physical damage will result if a PAOC is powered up on an older board in error.
Installation
¾ To install the PAOC pack
2. Directly plug the PAOC I/O pack into the terminal board connectors.
Note The PAOC mounts directly to a Mark VIe terminal board. Simplex terminal
boards have a single DC-37 pin connector that receives the PAOC. The PAOC is a
simplex-only pack.

See also the Auto-Reconfiguration section.

Wizard again.
Operation
Processor




Status LEDs
Processor LEDs

present
LED Status

ATTN
or module.
ATTN
every 4 sec

Analog Output Hardware
The PAOC includes eight simplex 0-20 mA analog outputs capable of 18 V compliance.
A 16-bit digital-to-analog converter (DAC) commands and drives the output current
with an external transistor amplifier. A board temperature sensor is included to warn
the control if the pack’s internal temperature becomes excessive.
PAOC Analog Output Pack
Terminal
Board
Multiplexor
Analog to Analog
Digital
Output
Converter
16-bit Feedbacks
8-Inputs
Ethernet
communications Processor
Terminal
Digital to Board
Analog Output Analog
Linear
Converter Suicide Outputs
Output
16-bit Relay
Drive
8-Outputs
Each analog output circuit also includes a normally open mechanical relay to enable or
disable operation of the output. When the disable relay is de-activated, the output opens
through the relay, open-circuiting that PAOC’s analog output from the customer load
that is connected to the terminal board. The mechanical relay’s second normally-open
contact is used as a status signal to indicate position of the relay with an LED.

PAOC Analog Output Pack
From
Digital to
processor Analog Board
Converter Temperature
16-bit Sensor
Suicide
Relay
ENA
Suicide
Enable
and Reset
Circuitry Analog output
to terminal
board
Suicide
Status
Feedback Return
Current Feedback Hardware

The PAOC includes current feedback monitoring for each of the eight simplex 0-20
mA analog outputs. A 50 Ω resistor on the terminal board and a 16-bit analog to
digital converter is used to sense and monitor the output current.
Reference Null
Analog to
Multiplexor
Digital
Converter 8 Circuits
16-bit
Current Feedback
from Terminal
Board

Thermal De-rating Guidelines
This is the pack external With eight linear, high-compliance analog outputs, the PAOC pack is subject
temperature inside the to application limitations depending on its potential ambient environment. I/O
cabinet, not cabinet external packs are specified to have an operating temperature range of -30 to 65ºC
temperature. (-22 to +149 ºF), as measured external to the pack.
Depending on the application, and due to its dense triple board configuration, the PAOC
packs ambient environment maximum must be de-rated. The following is a list of output
configurations and the appropriate de-rating that must be applied. The minimum output
impedance is defined as the minimum series equivalent resistance of the customers load,
as seen by the terminal board screws across the output range of 0-20 mA.
Maximum PAOC pack ambient temperature in degrees Celsius (degrees

Fahrenheit) inside cabinet:
Number of Minimum Output Resistance (per output, ohms)

outputs
0 250 500 1000
1 65º (149 ºF) 65º (149 ºF) 65º (149 ºF) 65º (149 ºF)
2 60º (140 ºF) 65º (149 ºF) 65º (149 ºF) 65º (149 ºF)
3 60º (140 ºF) 60º (140 ºF) 60º (140 ºF) 65º (149 ºF)
4 55º (131 ºF) 60º (140 ºF) 60º (140 ºF) 65º (149 ºF)
5 55º (131 ºF) 55º (131 ºF) 60º (140 ºF) 60º (140 ºF)
6 50º (122 ºF) 55º (131 ºF) 55º (131 ºF) 60º (140 ºF)
7 50º (122 ºF) 50º (122 ºF) 55º (122 ºF) 60º (140 ºF)
8 45º (104 ºF) 50º (122 ºF) 55º (122 ºF) 55º (122 ºF)
ID Line
Power Management

Connectors
Specifications
The following table provides information specific to the PAOC.
Item Specification
Number of channels Eight current output channels, single-ended (one side connected to common)
Analog outputs 0-20 mA, up to 900 Ω burden (18 V compliance)
Response better than 50 rad/sec
Accuracy ±0.5% over -30 to 65ºC (-22 to +149 ºF) temperature and 0 to 900 Ω load impedance
±0.25% typical at 25ºC (+77 ºF) and 500 Ω load
D/A converter resolution 16-bit resolution
Frame rate 100 Hz on all eight outputs
Physical

Diagnostics



Configuration

PAOC-Mod_Config
AnalogOut1 First of eight analog outputs - Board Point Point Edit (Output FLOAT)
Output_MA Output mA selection Unused, 0-20 mA, 0-200 mA
Low_Value Output in engineering units at low mA -3.4082e + 038 to 3.4028e + 038
High_Value Output value in engineering units at high mA -3.4082e + 038 to 3.4028e + 038
D/A_ErrLimit DA error threshold in percent 0 to 100 %
Suicide_Enab Suicide enable for faulty output Enable, disable
Output_State State of the outputs when offline PwrDownMode, HoldLastVal,
Output_Value
DitherAmpl Dither in % current of scaled output mA 0 to 10
Dither_Freq Dither rate in Hertz Unused, 12.5, 25.0
33.33, 50.0, 100.0
IS220PAOC PointDefs Description Direction Type
L3DIAG_PAOC I/O diagnostic indication Input BIT
LINK_OK_PAOC I/O link okay indication Input BIT
ATTN_PAOC I/O attention indication Input BIT
IOPackTmpr I/O pack temperature Input FLOAT
OutSuicide1 Status of suicide relay for output 1 Input BIT
: : Input BIT
Out1MA Measure output current in mA Input FLOAT
: : Input FLOAT

TBAO Analog Output
The Analog Output (TBAO) terminal board supports 16 analog outputs with a current
range of 0-20 mA. Current outputs are generated by the I/O processor, which can be local
(Mark* VIe control) or remote (Mark VI control). The outputs have noise suppression
circuitry to protect against surge and high-frequency noise. TBAO has two barrier-type
terminal blocks for customer wiring and six D-type cable connectors.
x DC-37 pin connectors

x
x 2
x 1 JT1 JT2 with latching fasteners
x 4 x 3
Eight Analog x 5
x 6
Outputs x 8
x 7
x 10 x 9
x 12 x 11
x 14 x 13 J ports conections:
x 16
x 15
x 18 x 17 Plug in PAOC I/O Pack(s)
x 20 x 19 JS1 JS2 for Mark VIe system
x 22 x 21
x 24 x 23 or
x
Cables to VAOC I/O boards
x for Mark VI;
x 26 x 25
28 x 27
Eight Analog x
x 29 The number and location depends
Outputs x 30
x 32
x 31 on the level of redundancy required.
x 33 JR1 JR2
x 34
x 36 x 35
x 38 x 37
x 40 x 39
x 42
x 41
x 44 x 43
x 46 x 45
x 48 x 47
x
x
Barrier Type Terminal

Shield
Blocks can be unplugged
Bar
from board for maintenance
TBAO Analog Output Terminal Board
Compatibility
In Mark VIe control system, TBAO works with the PAOC I/O pack and supports
simplex applications only. The I/O packs plug into the D-type connectors
and communicate over Ethernet with the controller.
In Mark VI control system, TBAO works with VAOC processor and supports simplex and
TMR applications. Cables with molded plugs connect TBAO to the VME rack where the
VAOC board is located. In TMR systems, TBAO is cabled to three VOAC boards.

Installation
Attach TBAO to a vertical mounting plate. Connect the wires for the 16 analog outputs
directly to the two I/O terminal blocks mounted on the left of the board. Each point
can accept two 3.0 mm (#12AWG) wires with 300 V insulation per point using spade
or ring type lugs. Each block is held down with two screws and has 24 terminals.
A shield terminal strip attached to chassis ground is located immediately to the left
of each terminal block. Make cable connections to TBAO follows:
• In Mark VIe control systems, plug the PAOC I/O packs directly into selected
D-type connectors. Special side mounting brackets support the packs.
• In Mark VI control systems, connect cables with molded plugs to the D-type
connectors on the TBAO and to the VME rack where the VAOC processor is
located. Use two cables for simplex or six cables for TMR.
The following figure shows details of TBAO wiring and cabling.
For Mark VIe

Analog Output Termination Board TBAO control, use I/O
JT1 JT2 Packs
x For Mark VI
Output 1 (Return) x
x 1 Output 1 (Signal) control, use
2
x 3 Output 2 (Signal) cables as
Output 2 (Return) x 4
Output 3 (Return) x x 5 Output 3 (Signal) follows:
6
Output 4 (Return) x
x 7 Output 4 (Signal)
8 To J4
Output 5 (Return) x
10 on I/O
Output 6 (Return) x 12 rack T
Output 8 (Return) x x 15 Output 8 (Signal)
16
x 17 Output 9 (Signal) JS1 JS2 To J3
Output 10(Return) x x 19 Output 10(Signal) on I/O
20
x 21 Output 11(Signal) rack T
Output 11(Return) x 22
Output 12(Return) x
x 23 Output 12(Signal)
24
x
x To J4
x 25 Output 13 (Signal) on I/O
Output 13(Return) x 26
Output 14(Return)
x 27 Output 14 (Signal) rack S
x 28
Output 15(Return) x 29 Output 15 (Signal)
x 30
Output 16(Return)
x 31 Output 16 (Signal) JR1 JR2 To J3
x 32
x 33 on I/O
x 34
x 35 rack S
x 36
x 37
x 38
x 39
x 40
x 41
x 42
x 43
x 44
x 45 To J4
x 46
x 47 on I/O
x 48
x
rack R
To J3
on I/O
rack R
I/O Terminal block with barrier terminals
Terminal blocks can be unplugged from
terminal board for maintenance
Up to two #12 AWG wires per point with 300
volt insulation
TBAO Terminal Board Wiring

Operation
TBAO supports 16 analog control outputs. Driven devices should not exceed a
resistance of 500 Ω (900 Ω if using I/O packs) and can be located up to 300 m
(984 ft) from the turbine control cabinet. The VAOC or PAOC contains the D/A
converter and drivers that generate the controlled currents. The output current is
measured by the voltage drop across a resistor on the terminal board.
Filters reduce high-frequency noise and suppress surge on each output near the point
of signal exit. The following figure shows TBAO in a simplex system.
TBAO Terminal Board

Noise
JR1 suppression
Current output 50 ohms 01 Signal
NS Circuit #1
02 Return
03 Signal
04 Return Circuit #2
Current feedback 05 Signal
Current feedback
07 Signal
return
09 Signal
Group 1
(8)
ID 11 Signal
To I/O
13 Signal
Processors
15 Signal
JR2 16 Return Circuit #8

50 ohms 17 Signal
NS 18 Return Circuit #9
19 Signal
21 Signal
23 Signal
25 Signal
Group 2
(8)
27 Signal
ID 28 Circuit #14
Return
29 Signal
31 Signal
Analog Outputs, Simplex

In a TMR system, each analog current output is fed by the sum of the currents from
the three I/O processors, as shown in the drawing below. The total output current is
measured with a series resistor that feeds a voltage back to each I/O processor. The
resulting output is the voted middle value (median) of the three currents.
TBAO Terminal Board

Noise
JR1 Suppression
Current output 50 ohms
01 Signal
NS Circuit #1
02 Return
03 Signal
Current feedback
05 Signal
Current feedback 06 Return Circuit #3
Return 07 Signal
ID 09 Signal
JS1 Group 1
(8) 10 Return Circuit #5
11 Signal
ID 13 Signal
To I/O processors JT1 15 Signal
ID
JR2 17 Signal
19 Signal
21 Signal
ID
JS2 23 Signal
Group 2 25 Signal
(8) 26 Circuit #13
Return
ID 27 Signal
To I/O processors 28 Circuit #14
JT2 Return
29 Signal
31 Signal
ID 32 Return Circuit #16
Analog Output, TMR

Specifications
Item Specification
Number of channels 16 current output channels, single-ended (one side connected to common)
Analog output current 0-20 mA
Customer load resistance Up to 500 Ω burden with VOACH1B and TBAOH1B and 900 Ω burden (18 V compliance)
with PAOC and TBAOH1C
Physical
Size 10.16 cm wide x 33.02 cm high (4.0 in x 13.0 in)
Diagnostics
Configuration
There are no jumpers or hardware settings on the board.

STAO Simplex Analog Output
The Simplex Analog Output (STAO) terminal board is a compact analog output terminal
board, designed for DIN-rail or flat mounting. STAO has eight 0-20 mA analog outputs
driven by the PAOC I/O pack. The on-board circuits and noise suppression are the same
as those on TBAO terminal board. High-density Euro-block type terminal blocks are
mounted on the board for wiring to the customer’s devices. An on-board ID chip identifies
the board to the I/O processor for system diagnostic purposes. The I/O pack plugs into
the D-type connector and communicates with the controller over Ethernet.
Installation
There is no shield terminal The STAO plus a plastic insulator mounts in a panel or on a sheet metal carrier that
strip with this design. then mounts on a DIN-rail. Optionally, the STAO plus insulator mount on a sheet
metal assembly that then bolts directly to a cabinet. Driven devices should not exceed
a resistance of 900 Ω and can be located up to 300 m (984 ft) from the turbine control
cabinet. Two types of Euro-block terminal blocks are available:
• STAOH1 has an unpluggable mount terminal block with 36 terminals.

• STAOH2 has a permanently mounted terminal block with 36 terminals.
The eight analog outputs are wired directly to the terminal block as shown in the
following figure. There are two screws for the SCOM connection. Typically #18
AWG wires (shielded twisted pair) are used. I/O cable shield terminal uses an external
mounting bracket supplied by GE or the customer. E1 and E2 are mounting holes
for the chassis ground screw connection (SCOM). DIN-type terminal boards can
be stacked vertically on the DIN-rail to conserve cabinet space.

STAO Terminal Board
E1
SCOM
Screw connections Screw connections
2 1 Output 1 (Signal)
Output 1 (Return)
3 Output 2 (Signal)
Output 2 (Return) 4
5 Output 3 (Signal) DC-37 pin connector
Output 3 (Return) 6
7 Output 4 (Signal) JA1 with latching fasteners
Output 4 (Return) 8
9 Output 5 (Signal)
Output 5 (Return) 10
11 Output 6 (Signal)
Output 6 (Return) 12 13 Output 7 (Signal)
15 Output 8 (Signal)
Output 8 (Return) 16 JA1
17 Chassis Ground
Chassis Ground 18
19
20
21 Plug in PAOC pack
22
23 SCOM on Mark VIe
24
26 25 17 & 18
27
28
29
30
31
32
33
34
35
36
TB1
Euro-Block type
terminal block
E2
SCOM
Plastic insulator
and metal carrier
DIN-rail mounting
STAO Wiring and Cabling

Operation
STAO supports eight analog control current outputs. On each output, the voltage drop
across the local loop current sense resistor is measured and the signal is fed back to
the I/O processor that controls the current. Filters reduce high-frequency noise and
suppress surge on each output near the point of signal exit. The I/O processor contains
the D/A converter and drivers that generate the controlled currents.
Analog Outputs STAO Terminal Board

Maximum Load
4-20 mA,
Noise
500 ohms JA1
suppresion
50 ohms Output current
Signal 01 JA1
Circuit #1
Return 02 Plug in
PAOC pack
Signal 03
Circuit #2 Return SCOM on Mark VIe
04
Signal 05 Current feedback
Circuit #3 Return 06 Current feedback
Signal 07
Circuit #4 Return Current return
08
Signal 09
Circuit #5 Return 10
ID
Signal 11
Signal 13 Eight analog
outputs
Signal 15
STAO Terminal Board
Specifications
Item Specification
Number of channels Eight current output channels, single-ended (one side connected to common)
Analog output current 0-20 mA
Customer load resistance Up to 900 Ω burden with PAOC pack
Physical

Diagnostics
Configuration

PCAA Core Analog Module
Core Analog Module (PCAA)

The Core Analog (PCAA) module and associated Core Analog (TCAS and TCAT)
CORE ANALOG I /O
terminal board provide a large portion of the analog signal I/O required to operate a
gas turbine. PCAA and TCAT provide thermocouple inputs, 4-20 mA current loop
I/O, seismic inputs, Linear Variable Differential Transformer (LVDT) excitation and
inputs, pulse rate inputs, and servo coil outputs. PCAA may be applied in simplex,
dual, and TMR systems. A single TCAT terminal board fans signal inputs to one, two,
or three connected PCAA modules. The shield ground and 24 V field power terminals
on an adjacent JGPA board supplement the terminals on PCAA and TCAT.
PWR
ATTN
PCAA contains a processor board common to all Mark* VIe distributed I/O, two
application I/O boards, and a terminal board. The complete module is regarded as the
ENET1
LINK
least replaceable unit and there is no support provided to diagnose or replace the
TxRx
individual boards making up the module.
ENET2
LINK
TxRx
Input to the module is through dual RJ45 Ethernet connectors and 28 V dc power
IS230PCAAH1A
connector P5. Field device I/O is through 120 Euro-style box terminals on the module
edge. Power for a JGPA board is through connector P4. Module connection to TCAT
is through two 68-pin cables on connectors P1 and P2.
The signals on PCAA are separated into two groups. Signal inputs that may be fanned
from a single input into a single, dual, or TMR PCAA modules are routed through the
TCAT terminal board. Signals that are dedicated to a single PCAA module are wired
to the terminals on PCAA. This creates the signal split shown in the following table. It
is possible to use PCAA without TCAT if the fanned inputs are not required.
GEH-6721L PCAA Core Analog Module System Guide 6-1

PCAA Terminals TCAT Terminals
# Signals Signal Type Screws/Signal # Signals Signal Type Screws/Signal
25 Thermocouples 2 12 Fanned seismic inputs 2
10 Analog 4-20 mA inputs 2 24 Fanned analog 4-20 mA 2
inputs
2 Analog 4-20 mA or ±10 V 2 12 24 V output power at 25 mA 1
in
2 Analog 4-20 mA outputs 2 3 Voting 4-20 mA outputs 2
1 ±12 V power output 2 12 Fanned LVDT Feedback 2
6 LVDT Excitation outputs 2 2 Fanned Mag. Pulse Rate 2
Inputs (servo flow meter)
6 Servo coil driver outputs 3 1 Common connection 1
1 Servo suicide relay input 2
2 TTL pulse inputs+power 4
P4 Connector
P5 Connector
P1 Connector
P2 Connector
PCAA Core Analog

TCAT
PS2
PR2
PS1
PR1
PT2
PT1
BCAA
Processor
BCAB
Board
R
TCAS P2 P1
PCAA-TCAT Connection Diagram - Simplex (PCAA cover omitted to show board relationship)
BCAA TCAT
Processor
BCAB
Board
PR2
PR1
PS2
PS1
PT2
PT1
T
TCAS P2 P1
BCAA BCAA
Processor Processor
BCAB BCAB
Board Board
S
TCAS P2 P1 TCAS P2 P1
PCAA-TCAT Connection Diagram - TMR (PCAA cover omitted to show board relationship)

Compatibility
The PCAA module is fully compatible with all other Mark VIe I/O
packs and controllers. PCAA supports the frame rates, redundancy, and
networking as shown in the following table.
PCAA IONet Frame TCAT Comments

Quantity Connections Rate Connections
Simplex One or Two 40 ms Zero or One TCAT optional on simplex configurations
Simplex One 10 ms Zero or One Only one IONet at 10 msec frame rates
TMR One 40 ms One TMR configurations only support one IONet per PCAA.
TMR One 10 ms One
Installation
¾ To install the PCAA module
1. Securely mount the PCAA module.
2. Connect the JGPA power connection to the P4 connector on PCAA.
3. Connect the PCAA module to an optional associated TCAT terminal board using
two 68-pin cables on connectors P1 and P2. Connectors on TCAT are paired by
a network connection. PR1 and PR2 go to a PCAA connected to the R controller
network, PS1 and PS2 go to a PCAA connected to the S controller, and PT1 and
PT2 go to a PCAA connected to the T controller. It is important to fully seat the
cable mounting screws, finger-tight only, into PCAA and TCAT to ensure proper
cable grounding. Failure to secure the cables may result in an inability of PCAA to
read the electronic ID on TCAT and may reduce the quality of other signals.
Note When removing 68-pin cables, ensure that the hex posts in the board-mounted
connectors do not turn when backing out the cable thumbscrews.
4. Plug in one or two Ethernet cables depending on the system configuration. When
a single IONet connection is used, the module operates correctly over either port.
If dual connections are used, standard practice is to hook ENET1 to the network
associated with the R controller. However, the PCAA is not sensitive to Ethernet
connections, and negotiates proper operation over either port. If TMR PCAA
modules are present, the network connection should match with the connection
made to TCAT. For example, the PCAA module with R IONet connection should
have cables that go to the TCAT PR1 and PR2 connectors.
5. Check grounding of the JGPA shield wire terminals. In most applications, JGPA
shield ground terminals are electrically tied to the sheet metal the board is mounted on.
The mounting then supplies the ground path for the terminals. In some applications, it
is required to define a shield ground that is independent of the mounting sheet metal.
For these applications, the JGPA is mounted using hardware that isolates the board
from the sheet metal. In these applications, it is important to provide a suitable ground
wire between one or more JGPA terminals and the required shield ground potential.
6. Apply power to the module through the P5 connector and check the
power and Ethernet status indicator lights.

7. Use the ToolboxST* application to configrue the I/O pack as necessary.

Wizard again.
Wiring
The PCAA module features 120 pluggable Euro-style box terminals. A JGPA
board mounts adjacent to the PCAA module and uses Euro-style box terminals to
provide forty eight shield termination points (green) plus twelve 24 V dc output
terminals (orange) for 4-20 mA transmitters. The Euro-style box terminals on
TCAT accept conductors with the following characteristics:
Conductor Type Minimum Maximum

Conductor cross section solid 0.2 mm² NA
Conductor cross section solid NA 2.5 mm²
Conductor cross section stranded 0.2 mm² NA
Conductor cross section stranded NA 2.5 mm²
Conductor cross section stranded, with ferrule without plastic sleeve 0.25 mm² NA
Conductor cross section stranded, with ferrule without plastic sleeve NA 2.mm²
Conductor cross section stranded, with ferrule with plastic sleeve 0.25 mm² NA
Conductor cross section stranded, with ferrule with plastic sleeve NA 2.5 mm²
Conductor cross section AWG/kcmil 24 AWG NA
Conductor cross section AWG/kcmil NA 12 AWG
2 conductors with same cross section, solid 0.2 mm² NA
2 conductors with same cross section, solid NA 1 mm²
2 conductors with same cross section, stranded 0.2 mm² NA
2 conductors with same cross section, stranded NA 1.5 mm²
2 conductors with same cross section, stranded, ferrules without plastic sleeve 0.25 mm² NA
2 conductors with same cross section, stranded, ferrules without plastic sleeve NA 1 mm²
2 conductors with same cross section, stranded, TWIN ferrules with plastic sleeve 0.5 mm² NA
2 conductors with same cross section, stranded, TWIN ferrules with plastic sleeve NA 1.5 mm²

The following table lists the terminal assignments for the PCAA module.
TCAS Screw Terminal Assignments

Name Function Name Function
1 TC1H Thermocouple1 3 TC2H Thermocouple2
2 TC1L 4 TC2L
6 TC3L 8 TC4L
10 TC5L 12 TC6L
14 TC7L 16 TC8L
18 TC9L 20 TC10L
22 TC11L 24 TC12L
26 TC13L 28 TC14L
30 TC15L 32 TC16L
34 TC17L 36 TC18L
38 TC19L 40 TC20L
42 TC21L 44 TC22L
46 TC23L 48 TC24L
49 TC25H Thermocouple25 51 TFH1 TTLpulserate input #1
50 TC25L 52 TFL1
55 TFH2 TTLpulserate input #2 53 TFPWR1
56 TFL2 54 TFL1
57 TFPWR2 59 ASIH1 Analog 4-20 mA input #1
58 TFL2 60 ASIL1
61 ASIH2 Analog 4-20 mA input #2 63 ASIH3 Analog 4-20 mA input #3
62 ASIL2 64 ASIL3
66 ASIL4 68 ASIL5
69 ASIH6 Analog 4-20 mA input #6 71 APWRP12 ±12 V power output
70 ASIL6 72 APWRN12

TCAS Screw Terminal Assignments
74 ASIL7 76 ASIL8
78 ASIL9 80 ASIL10
81 ASIH11 Analog 4-20 mA ±10 V input #11 83 ASIH12 Analog 4-20 mA ±10 V input #12
Note Odd-Even Terminal Grouping
82 ASIL11 84 ASIL12
85 ASOH1 Analog 4-20 mA Output #1 87 ASOH2 Analog 4-20 mA Output #2
86 ASOL1 88 ASOL2
89 SVO1L Servo Output #1 and #2. 95 SVO3L Servo Output #3 and #4.
Note Odd-Even Terminal Grouping Note Odd-Even Terminal Grouping
90 SVO2L 96 SVO4L
91 SVO1H 97 SVO3H
92 SVO2H 98 SVO4H
93 SVO1X 99 SVO3X
94 SVO2X 100 SVO4X
101 SVO5L Servo Output #5 and #6. 107 SVRL1 Servo Suicide Relay Input
Note Odd-Even Terminal Grouping 1
102 SVO6L 108 SVRL2
103 SVO5H 109 LVDTEXH1 LVDT Excitation Output #1
104 SVO6H 110 LVDTEXL1
105 SVO5X 111 LVDTEXH2 LVDT Excitation Output #2
106 SVO6X 112 LVDTEXL2
113 LVDTEXH3 LVDT Excitation Output #3 115 LVDTEXH4 LVDT Excitation Output #4
114 LVDTEXL3 116 LVDTEXL4
117 LVDTEXH5 LVDT Excitation Output #5 119 LVDTEXH6 LVDT Excitation Output #6
118 LVDTEXL5 120 LVDTEXL6

Operation
Module Overview
The PCAA module consists of four separate circuit boards in a single physical assembly.
The module is regarded as the least replaceable unit because of the difficulty of isolating a
failure to a single board. The module is not designed for replacement of individual boards.
TCAS
BCAB
4-20 mA INs
J3 and J4
Thermocouple INs
Vibration INs
MPU INs
Signal conditioning and suppression circuitry
TMR TB Cable
P1 and P2
Connectors
TB1 120 Screws
BCAA
LVDT INs
LVDT EXC OUTs

J1 and J2
TTL INs
10 mA Servo OUTs
4-20 mA OUTs
+/-15 V Pwr Supply
P4 Processor Board
28 V
P5 28 V Input
PCAA Board Relationship Diagram
TCAS Terminal Board

The IS200TCAS terminal board provides the customer terminals and signal routing into
the BCAA and BCAB boards. TCAS accepts bulk 28 V control power through the P5
connector. It then provides the power through connector P4 to a JGPA board in the input
cable shield termination location. TCAS provides the P1 and P2 68 pin connectors for
IS200TCAT terminal board cables. Internal to the module the TCAS terminal board
routes signals to connectors for the BCAA and BCAB analog processing boards.

BCAA and BCAB Analog Processing Boards
Inside the module cover the BCAA and BCAB boards provide power, analog
signal conditioning, and analog/digital conversion.
BCAA is the main printed circuit board in the PCAA module. This board provides the main
±15 V power and the majority of the digital and analog interface to the processor board. In
addition, this board provides the signal conditioning required to interface 12 LVDT sensors,
five 4-20 mA and six servo outputs, and two TTL flow sensors to the processor board.
The BCAB interface board provides the signal conditioning required to

interface the thermocouples, 4-20 mA inputs, pulse rate flow sensors and
vibration inputs to the control electronics.
BCAA
Power Supply
ACOM P15 N15 P5 N5
PS
Mon PS OK
4 2
MFLOW
6 2
TFLOW
P1 and P2 Connectors
2
J1 and J2 Connectors
SV1
DataBus
2
SV2 & Control
Processor
2 DAC1
SV3 Board
2
SV4 4
3
2
SV5 3
2
SV6
DAC2
DATP1
4
MA1
4
MA2
4
MA3
4 DAC3 ADC
MA4
4
MA5
8-1 Mux
2 MX8
Current Mon Mux
AFS11&12
Suicide Rly Out Reg
Suicide Rly Fbk Reg
Excitation Flt Reg

12
LVDT Excitation 1- 6
EX MON
24 MX7
LVDT FBK 1-12
MX1 - 6
BCAA Block Diagram

BCAB
26 MX1
Thermocouple IN 1 - 13
25 Thermocouple IN 14 - 25 MX2
and Cold Junction
+/- 0.0248 V
Bias
20 MX5
4-20 mA/Temp IN S1 - 10
J3 and J4 Connectors
4 AFS11
4-20 mA/V IN S11 - 12 AFS12
24 MX3
4-20 mA IN T1 - 12
24 MX4
4-20 mA IN T13 - 24
24
Vibration IN 1 - 12 dc
MX6
Vibration IN 1 - 12 RMS
VIBDCRMS
MXSA0 - 3
4 Pulse Rate Flow Sensor MF1

IN 1&2 MF2
BCAB Block Diagram

Processor


Status LEDs
Processor LEDs

Green PWR Displays the presence of control power
Green LINK Provided for each Ethernet port to indicate if a valid Ethernet connection is present.
Yellow TxRx Provided for each Ethernet port to indicate when the pack is transmitting or receiving
data over the port.
Red / Green ATTN Displays pack status
LED Status
LED Flashing Pattern Description

Red ATTN LED out There are no detectable problems with the pack.
LED solid on A critical fault is present that prevents the pack from operating. There could be
hardware failures on the processor or acquisition boards, or there is not any application
code loaded.
4 Hz 50% An alarm condition is present in the I/O pack. These alarms include: wrong pack
/ terminal board combination, terminal board is missing, or errors in loading the
application code.
1.5 Hz 50% The pack is not online.
0.5 Hz 50% This is used during factory testing.
Recalibration
The recalibration of a PSVO, PSVP, PCAA, MVRA, and MVRF servo board is required
when a new terminal board is used on a system. The controller saves the barcode of the
terminal board and compares it against the current terminal board during reconfiguration
load time. Any time a recalibration is saved, it updates the barcode name to the current
board. Liquid Fuel regulators do not have to be recalibrated (where applicable).
ID Line
The four boards that make up the PCAA module contain electronic ID parts
that are read during power initialization. A similar part associated with each
cable connection on the TCAT terminal board allows the processor to confirm
correct matching of all board revisions plus processor firmware and report
board revision status to the system level control.
Power Management
The PCAA includes power management in the 28 V input circuit. The management
applying power, the circuit provides a fast current limit function to prevent a power
disturbance in the module from propagating back onto the 28 V power system. When
power is present and working properly, the green PWR indicator will light. If the current
limit function operates, the indicator will be out until the problem is cleared.

Connectors
• Connectors P1 and P2 provide cable connections to a TCAT terminal board.
• An RJ45 Ethernet connector named ENET1 on the module side is
the primary system interface.
• A second RJ45 Ethernet connector named ENET2 on the module side is
the redundant or secondary system interface.
• A 3-pin power connector P5 on the module is the input point for 28 V
dc power for the module and terminal boards.
• A power connector P4 on the module provides 28 V dc power to a JGPA
board located for wire shield termination.
Note The module operates from a power source that is applied directly to the module
P5 connector, not through the normal power connector located on the processor board.
Signal Response
The PCAA module is designed to run at frame rates of 40 and 10 ms. For each
signal type an accuracy specification is listed that includes all effects such as aging,
temperature, power supply input variation, and product variation. For each signal type
a typical accuracy at 25ºC with mean and standard deviation is also listed. This typical
accuracy is similar to the accuracy that can be expected in normal operation while the
specified accuracy is an absolute worst case limit on the signal accuracy.
Thermocouples
PCAA supports the following thermocouple types and temperature ranges:
Type Range °F Range °C

E -60 to +1150 -51 to +621
J -60 to +1500 -51 to +816
K -60 to +2000 -51 to +1093
T -60 to +750 -51 to +399
S 0 to 3200 -17.78 to 1760
A single cold junction is provided with each PCAA module. The module accepts a
controller backup cold junction value, CJBackup, in the event a problem is detected
with the local sensor. The PCAA may be configured to use a controller provided
remote cold junction value, CJRemote. All thermocouple inputs are biased with a dc
voltage that will drive the temperature signal full scale negative in the event of an
open wire. Accuracy exceeds ±0.1% of full scale over the full specified operating
temperature of PCAA. Typical measured mean accuracy at 25ºC is ±0.01% with a
standard deviation of 0.016%. Primary source of temperature drift for thermocouple
inputs is a precision calibration reference rated at 0.0008%/ºC worst case.

The units (°C or °F) are based 4-20 mA Inputs
on the ThermCplUnit settings.
See section ThermCplUnit PCAA meets the specification of ±0.25% for 4-20 mA inputs, ±0.5% for voltage inputs
Parameter over the full PCAA operating temperature range. Typical measured mean current input
accuracy at 25ºC is ±0.05% with a standard deviation of 0.016%. Primary source of
temperature drift for analog inputs is a precision calibration reference rated at 0.0008%/ºC
worst case. All inputs have a jumper to select grounded or floating measurements. When
the Open/GND jumper is in the Open position the input accepts a maximum of 7 volts
common mode relative to the PCAA ground. As a group it is possible to specify an
upper and lower current level for a valid input. Each input may then be individually
configured to produce a diagnostic when current is outside the specified limits.
Analog inputs 11 and 12 may also be configured as voltage inputs. In

support of sensors on legacy systems a single ±12 V power supply output
is provided on PCAA with rating of 50 mA.
4-20 mA Outputs
Typical measured mean accuracy at 25ºC is ±0.1% with standard deviation of

0.11%. The two outputs on PCAA behave as typical simplex analog outputs. The
three outputs on TCAT, when driven from triple PCAA modules, exhibit full fault
tolerance. An output failure on one of the three PCAA modules results in a very
short disturbance to the output with full recovery to the commanded value. All five
analog outputs are provided with independent read-back of the output current and an
output relay. If incorrect operation of the output is detected, the relay is automatically
opened to protect the connected device against excessive output current. All analog
output circuits have greater than 18 V output drive capability.
Seismic Inputs
TCAT seismic inputs are biased with a small dc current for open wire detection. Inputs
go through a high-pass filter at 4 Hz and low pass filter at 600 Hz. The filtered signal
goes through an RMS conversion followed by a 1 Hz filter. The result is sampled
and used to perform a calculation to determine inches per second peak vibration. In
parallel with the primary signal path, the inputs are monitored for the presence of dc
voltage to drive the annunciation of a failed or open sensor. PCAA meets accuracy of
±2% over the full PCAA operating temperature range. Typical measured mean seismic
input accuracy at 25ºC is ±0.02% with standard deviation of 0.25%.
LVDT
Each of six excitation outputs provides a 7 Vrms, 3.2 kHz sine wave and is capable of
driving 60 mA. Input sampling takes place at 100 Hz. PCAA meets LVDT input voltage
accuracy of ±1% over the full range of operating temperature and load impedances.
Typical measured mean accuracy at 25ºC is ±0.07% with standard deviation of 0.05%.
Position feedback accuracy in the PCAA is dominated by initial calibration quality and
any drift experienced in the circuits after calibration. In PCAA, drift is determined
by the precision voltage reference used for internal circuit calibration, rated for
0.0008%/ºC worst case temperature drift and almost no measurable aging.

Servos
Servo output features in the PCAA Module :
PCAA
Six output drivers capable of full scale output
of 10 mA.
Regulators run at 100 Hz
Servo output accuracy ±3.5%
Two of six outputs controlled by optional input
signal that removes output drivers and biases
output closed
PCAA regulator types supported include the following.
PCAA
Reg Type Description
Position Set RegGain = 0 and adjust the current regulator command, ServoCurrentRef through the system
output, Reg#_NullCor.
LiquidFuel FlowInput1 = FlowRate1-4 FlowInput2 = Unused
LiquidFuel FlowInput1 = FlowRate1-4 and FlowInput2 = FlowRate1-4.
Input is the maximum of the two values.
Position PositionInput1 = Position 1 selected from LVDT1 through LVDT12 and PositionInput2 = Unused and
PositionInput3 = Unused.
Not supported
Position PositionInput1 = Position 1 selected from LVDT1 through LVDT12 and PositionInput2 = Position 2
selected from LVDT1 through LVDT12 and PositionInput3 = Unused
Position PositionInput1 = Position 1 selected from LVDT1 through LVDT12 and PositionInput2 = Position 2
selected from LVDT1 through LVDT12 and PositionInput3 = Position 3 selected from LVDT1 through
LVDT12.
SpeedRatio Outer P2 pressure loop regulating the maximum of two P2 pressure feedbacks feeding the reference to
the inner position loop deriving its feedback from the maximum of two LVDTs.
LiquidFuel Outer flow rate loop regulating the maximum of two flow rate feedbacks providing the reference to the
inner position loop deriving its feedback from the maximum of two LVDTs.
wPosition

PCAA implements four regulator types. The Speed Ratio Valve (SRV) regulator in
the PCAA is an enhanced version of the SRV control in the Mark VI product. The
PCAA provides support for both the outer P2 pressure loop and the inner position
loop. The PCAA can run both loops at 100 Hz compared to 200 Hz for the PSVO’s
inner position loop and 25 Hz for the controller’s outer P2 loop.
Output current range is fixed at 10 mA. PCAA meets a servo output accuracy of ±3.5%
of full scale over the full range of operating temperature and load impedance. Typical
measured mean accuracy at 25ºC is ±0.5% with standard deviation of 0.07%.
To allow continuous movement of the servo system to avoid sticking, PCAA

features adjustable amplitude dither with frequency selected to be 50 Hz,
25 Hz, 16.67 Hz, 12.5 Hz, and 8.13 Hz.
The first two servo outputs are equipped with an output shut down relay. Terminals
107 and 108 must be disconnected for servo 1 and 2 to be enabled. If terminals
107 and 108 are shorted together, the servo driver is disconnected from the output
terminals and a passive circuit biases the servo closed. This feature is used when
it is required to include servo action in a control protective response. The TREG
K4CL relay is often used for this purpose in simplex systems. If protective action
is not needed on these servos, leave terminals 107 and 108 open. Servos three
through six are not affected by the shut down relay action.
LVDT signal conditioning on the PCAA uses the measured value of excitation
voltage to correct for excitation changes. One PCAA module may be providing
excitation on an LVDT that is being read by all three PCAA modules in a TMR
set. Application blockware must be provided to pass the excitation voltage monitor
inputs, ServoExcitMonitor_R, ServoExcitMonitor_S, ServoExcitMonitor_T to the
ExcMon_fromR and ExcMon_fromS outputs through the Move block function.

Position Valve Servo System
The Position Valve Servo system is used to control the Gas Control Valves (GCV) on the
fuel skids of heavy-duty gas turbines and the Inlet Guide Vanes (IGV) on the compressor
of the heavy-duties. Refer to the diagram Position Valve Servo System.
GCV or guide vane position is fed back to the digital position regulator in the PCAA
using LVDT sensors. The TCAS terminal board provides the six LVDT excitation signal
pairs: LVDTEXH1_R/LVDTEXL1_R through LVDTEXH6_R/LVDTEXL6_R. These
excitation outputs are connected to the primary-side of the LVDT position sensor. The
primary-side signal is a 3.2 kHz sine wave excitation with a 7.07 V RMS amplitude.
The LVDT secondary-side signal amplitude is proportional to the position change in the
valve. The LVDT secondary-side is connected to one of the twelve TCAT terminal board
LVDT input signal pairs: LVDT1H/LVDT1L through LVDT12H/LVDT12L. The TCAT
terminal board is used to fan the LVDT signal pair to the TMR PCAA set: PCAA (R),
PCAA (S) and PCAA (T) through cabling. The BCAA acquisition board provides signal
conditioning to convert the RMS voltage from the secondary-side of the LVDT to a dc
equivalent signal read by the processor through analog-to-digital (A/D) converters.
The PCAA firmware can run up to six independent digital servo regulators. Each
loop is performed at a 100 Hz sample rate. Details of the Position digital regulator
are covered in the next section. The digital regulator output, ServoCurrentRef
is written to a digital-to-analog (D/A) converter. The negated output of the D/A
is the current command for the analog current regulator.
The BCAA acquisition board has six analog current regulators, one per digital servo
regulator. All six analog current regulators are rated for 10 mA only. Each current output
provides an internal suicide protection relay controlled by the PCAA firmware. Each
of the six servo outputs supports either three-coil servos or two-coil servos and each
provides a jumper on the TCAS terminal board to configure the output.
The jumper is placed in the TMR position for the 3-coil servo and placed in the opposite
position for the 2-coil servo. For example, for the 3-coil servo using Servo output 1:
PCAA SVO1H_R/SVO1L_R outputs are connected to coil 1, TCAS

JP15_R is placed in 1-2_TMR

JP15_S is placed in 1-2_TMR

JP15_T is placed in 1-2_TMR
For the simplex 2-coil servo connection, PCAA_R SV01H/L outputs are connected
to coil 1 and SV01X_R/SVO1L_R outputs are connected to coil 2. TCAS
JP15_R is placed in 2-3_Simplex (non-TMR position).
Servo outputs 1 and 2 also provide a means to externally suicide the outputs through
the TCAS inputs SVRL1/2. For the Mark VIe, the PPRO provides an external contact
connected across SVRL1 and SVRL2. If the contact closes, the K1 relay is energized and
the servo output is isolated from the digital regulator control, providing a direct connection
through a current limiting resistor (15 mA fixed output), as long as the K1 relay is energized.

Position Valve Servo System

Digital Servo Regulator_Position
The digital Position regulator is a proportional regulator generating a servo

current command proportional to the error signal, the difference between the
position reference from the controller and the valve position feedback. Refer
to the diagram Digital Servo Regulator_Position.
Three feedback options are supported: Single position feedback, dual

position feedbacks or three position feedbacks.
• Setting PositionInput1 equal to one of the twelve LVDT inputs can

configure the single position feedback option.
• The dual feedback option is selected when the configuration parameters,
PositionInput1 and PositionInput2 are assigned to different LVDT inputs.
• The three feedback option is enabled by setting each of the following
configuration parameters to a unique LVDT input: PositionInput1,
PositionInput2 and PositionInput3.
Each of the position inputs enabled run through a Position Calculation function that
converts the dc volts signal representing RMS volts to a valve position in percent
where 0% represents fully closed and 100% represents a fully open valve.
The Position Limit function’s input is the following based on the configuration:
• Equal to the Position Calculation output for a single position feedback.

• Equal to the maximum select from two Position Calculation outputs
for the dual position input configuration.
• Equal to the median select for the three position input configuration. The Position
Limit function checks the feedback range of Reg#_Fdbk. The range defined in
percent over nominal is configurable using the parameter, Fdbk_Suicide. The
suicide only works if it is enabled by EnabPosFbkSuic.
In the next figure, the proportional regulator error, is equal to the position reference
command from the controller, Reg#Ref minus the position feedback, Reg#_Fdbk.
Proportional regulator error is multiplied by a composite gain defined by the multiplication
of the configuration parameter, RegGain and the controller output, Reg#_GainAdj.
The product of the gain and position error defines a current in percent. The amount
of current required to negate the spring force used to close the valve if the servo fails
is compensated by the configuration parameter, RegNullBias. The controller system
output, Reg#_NullCor is used to correct the null bias value when one of the TMR servos
is suicided. The resultant output from the proportional position regulator is a current
command in percent with the Monitor variable name, ServoCurrentRef.
After the initial configuration setting is made for the position loop, the user calibrates the
position valve feedbacks. This is done by using ToolboxST to select the LVDT calibration
mode and setting the controller output CalibEnab# equal to TRUE. In the calibration mode,
the user can use the servo output in the open-loop mode to force the valve to the fully
closed position and also to the fully open position. During the calibration mode, the PCAA
assigns the RMS voltage that represents the open and closed position to the configuration
parameters for each LVDT that is used: MinVrms and MaxVrms. The user selects
Calibrate and Save to store the LVDT Excitation output voltage is read and stored in the
LVDT configurable parameter ExcitMonCal. The excitation voltage is used to compensate
for excitation voltage changes during runtime. The user must also verify that the LVDT
parameter ExcitSelect comes from the proper Excitation voltage source (R, S, or T).

Digital Servo Regulator - Position

Speed Ratio Valve Servo System
The Speed Ratio Valve Servo system is used to control the main fuel-feed Speed
Ratio Valve (SRV) whose output feeds the GCVs on the fuel skids of the heavy-duty
gas turbines. The SRV control is a multi-loop servo. The P2 pressure provides
the outer loop feedback and the valve position provides the inner loop control.
Refer to the diagram Speed Ratio Valve Servo System.
The outer loop SRV pressure is fed back to the digital pressure loop in the PCAA
using pressure sensors. These pressure sensors have 4-20 mA outputs that are
connected to one of the TCAS terminal board dedicated SRV analog inputs:
ASIH11_R / ASIL11_R and/or ASIH12_R / ASIL12_R.
Note The pressure inputs are not fanned, and redundant pressure inputs are connected
to separate PCAA modules when the SRV is configured as TMR.
The inner loop P2 valve position is fed back to the digital position loop in the PCAA using
LVDT sensors. The LVDT secondary-side is connected to one of the twelve TCAT terminal
board LVDT input signal pairs: LVDT1H/LVDT1L through LVDT12H/LVDT12L. The
TCAT terminal board is used to fan the LVDT signal pair to the TMR PCAA set: PCAA (
R), PCAA (S) and PCAA (T) through cabling. The BCAA acquisition board provides
signal conditioning to convert the RMS voltage from the secondary-side of the LVDT to a
dc equivalent signal read by the processor through analog-to-digital (A/D) converters.
The PCAA firmware uses one of the six independent digital servo regulators.
The SRV loop is run at a 100 Hz sample rate. Details of the Speed Ratio Valve
digital regulator are covered in the next section. The digital regulator output,
ServoCurrentRef is written to a digital-to-analog (D/A) converter. The output of
the D/A is the current command for the analog current regulator.

Speed Ratio Valve Servo System

Digital Servo Regulator – Speed Ratio
The digital Speed Ratio Valve regulator is a proportional plus integral (PI) outer
regulator with an inner proportional position regulator generating a servo current
command. The SRV output is based on a multi-loop control using the P2 pressure
feedback for the outer loop and the valve position for the inner loop feedback.
Refer to the diagram Digital Servo Regulator - Speed Ratio.
The outer P2 pressure loop derives its pressure feedback from either a single pressure
input or the maximum select of two pressure inputs. For a single pressure input, the
configuration parameter PressureInput1 is assigned to either AnalogInput11 or 12.
For a dual pressure input, PressureInput1 is assigned to AnalogInput11 or 12 and
PressureInput2 is assigned to AnalogInput11 or 12. The Pressure Limit Check checks the
range of the maximum select or the single feedback depending on the configuration. If
the pressure feedback, Reg#_Pressure is less than PresFdbkLoLim or Reg#_Pressure is
greater than PresFdbkHiLim then the pressure loop is assumed to be open loop and the
SRV servo out will suicide if the EnabPressureFbkSuic parameter is set to Enable.
The SRV pressure error, Reg#Ref minus Reg#Pressure has an integrator convergence
error added to it. The objective of the convergence error is to keep the PI controller
between PCAA ( R), PCAA (S) and PCAA (T) together. The PI output for (R, S
and T), Reg#_IntOut is read by the controller. The average error, Reg#_IntConv
is calculated from the three inputs. Each SRV regulator for R, S and T takes the
average, subtracts its own PI output value from this, multiplies it by a gain value,
K_Conv_OuterReg to come up with the convergence error to move the integrator for
PI R, S and T together. The PI proportional gain, K_OuterReg and the integral time
constant, Tau_OuterReg provide the PI adjustments. The clamping is controlled by
the parameters: HiLim_OuterReg and LowLim_OuterReg. The PI outer loop output,
Reg#_IntOut is the position command for the inner position loop.
The inner position loop supports two feedback options: Single position feedback and
the maximum select of two position feedbacks. Setting PositionInput1 equal to one
of the twelve LVDT inputs can configure the single position feedback option. The
maximum select of two position feedbacks is selected when the configuration parameters,
Each of the position inputs enabled run through a Position Calculation function that
converts the dc volts signal representing RMS volts to a valve position in percent
where 0% represents fully closed and 100% represents a fully open valve.
The Position Limit function’s input is the following based on the configuration: equal to
the Position Calculation output for a single position feedback or equal to the maximum
select from two Position Calculation outputs for the dual position input configuration. The
Position Limit function checks the feedback range of Reg#_Fdbk. The range defined
in percent over nominal is configurable using the parameter, Fdbk_Suicide.
The proportional regulator error, Reg#_Error is equal to the position reference command
from the controller, Reg#Ref minus the position feedback, Reg#_Fdbk. Reg#_Error
is multiplied by a composite gain defined by the multiplication of the configuration
parameter, RegGain and the controller output, Reg#_GainAdj. The product of the
gain and position error defines a current in percent. The amount of current required to
negate the spring force used to close the valve if the servo fails is compensated by the
configuration parameter, RegNullBias. The controller system output, Reg#_NullCor
is used to correct the null bias value when one of the TMR servos suicides for some
reason. The resultant output from the proportional position regulator is a current

After the initial configuration setting is made for the position loop, the user calibrates
the position valve feedbacks. This is done by using ToolboxST to select the LVDT
calibration mode and setting the controller output CalibEnab# equal to TRUE. In the
calibration mode, the user can use the servo output in the open-loop mode to force
the valve to the fully closed position and also to the fully open position. During the
calibration mode, the PCAA assigns the RMS voltage that represents the open and closed
position to the configuration parameters: MinVrms and MaxVrms. The user selects
Calibrate and Save to store the LVDT Excitation output voltage in the LVDT configurable
parameter ExcitMonCal. The excitation voltage is used to compensate for excitation
voltage changes during runtime. The user must also verify that the LVDT parameter
ExcitSelect comes from the proper Excitation voltage source (R, S, or T).

Digital Servo Regulator - Speed Ratio

Liquid Fuel Valve Servo System
The Liquid Fuel Servo system is used with gas turbines using the liquid fuel
option. Refer to the diagram Liquid Fuel Valve Servo System.
The flow rate is fed back to the digital flow rate regulator in the PCAA using Liquid Fuel
flow meter with magnetic pickup outputs. The flow meter output is connected to one of
the two TCAT terminal board magnetic flow sensor input signal pairs: MFI1H/MFI1L
through MFI2H/MFI2L or two TCAS terminal board TTL flow sensor input signals:
TFH1/L1 through TFH2/L2. The TCAT terminal board is used to fan the magnetic
input signal pair to the TMR PCAA set: PCAA ( R), PCAA (S) and PCAA (T) through
cabling. The BCAA acquisition card provides signal conditioning to convert the variable
frequency, variable amplitude input to a digital pulse. The digital pulse from the
magnetic flow sensor signal conditioning or the TTL sensor conditioning feeds a counter
used to determine the frequency of the pulse train from the flow meter.
The processor board uses one of the six independent digital servo regulators. The
Liquid Fuel servo regulator is sampled at a 100 Hz rate. Details of the Liquid
Fuel digital regulator are covered in the next section. The digital regulator output,
ServoCurrentRef is written to a digital-to-analog (D/A) converter. The output of
the D/A is the current command for the analog current regulator.
The BCAA acquisition board has six analog current regulators, one per digital servo
regulator. All six analog current regulators are rated for 10 mA only. Each current
output provides an internal suicide protection relay controlled by the processor board
software. Each of the six servo outputs supports either three-coil servos or two-coil
servos and each provides a jumper on the TCAS terminal board to configure the
output. The jumper is placed in the TMR position for the 3-coil servo and placed in
the Open position for the 2-coil servo. For the 3-coil servo using Servo output 1,
PCAA SVO1H_R/SVO1L_R outputs are connected to coil 1, PCAA (S) SV01H/L
outputs are connected to coil 2 and PCAA (T) SV01H/L outputs are connected to coil
3. For the simplex 2-coil servo connection, PCAA SVO1H_R/DVO1L_R outputs
are connected to coil 1 and SV01X/L outputs are connected to coil 2.
Servo outputs 1 and 2 also provide a means to externally suicide the outputs through
the TCAS inputs SVRL1/2. For the Mark VIe, the PPRO provides an external contact
connected across SVRL1 and SVRL2. If the contact closes, the K1 relay is energized and
the servo output is isolated from the digital regulator control, providing a direct connection
through a current limiting resistor (15 mA fixed output), as long as the K1 relay is energized.

Liquid Fuel Valve Servo System

Digital Servo Regulator - Liquid Fuel
The Digital Liquid Fuel regulator is a proportional regulator generating a servo

current command proportional to the error signal, the difference between the
Liquid Fuel flow rate reference from the controller and the flow rate feedback.
Refer to the diagram Digital Servo Regulator - Liquid Fuel.
Two flow rate feedback options are supported: Single flow rate feedback or the
dual flow rate option. Setting FlowInput1 equal to one of the four flow rate inputs
configures the single flow rate option. The dual feedback option is selected when
the configuration parameters, FlowInput1 and FlowInput2 are assigned to different
flow inputs. Unlike the LVDT calibration available for the position inputs, there
is no ToolboxST calibration function for the flow inputs.
Each of the enabled flow rate inputs runs through a Flow Rate Calculation function
that converts the revolutions per minute frequency to a flow rate percentage where
0% represents no flow and 100% represents a rated flow.
The Flow Rate Limit Check’s input is the following based on the configuration: equal
to the flow rate output for a single feedback or equal to the maximum select from two
flow rates. The Flow Rate Limit Check looks for the flow rate feedback, Reg#_Fdbk
to be out of range. The range is defined using configurable minimum and maximum
flow limits in percent of nominal. There is also a configurable delay that must be
exceeded before a diagnostic alarm is generated. If the flow feedback exceeds either
flow limit for the defined delay the servo will suicide, if enabled.
The proportional regulator error, Reg#_Error is equal to the flow rate reference command
from the controller, Reg#Ref minus the flow rate feedback, Reg#_Fdbk. Reg#_Error
is multiplied by the composite gain defined by the multiplication of the configuration
parameter, RegGain and the controller output, Reg#_GainAdj. The product of the gain
and flow rate error defines a current in percent. The amount of current required to

Digital Servo Regulator - Liquid Fuel

Liquid Fuel Valve with Position Feedback Servo System
The Liquid Fuel Valve with Position Feedback Servo system is used with gas
turbines using the liquid fuel option. The Liquid Fuel Valve with Position Feedback
is the multi-loop control system. The fuel flow rate is the feedback for the outer
loop and the valve position is the inner loop feedback. Refer to the diagram
Liquid Fuel Valve with Position Feedback Servo System.
The flow rate is fed back to the digital flow rate regulator in the PCAA using Liquid
Fuel flow meter with magnetic pickup outputs. The flow meter output is connected
to one of the two TCAT terminal board magnetic flow sensor input signal pairs:
MFI1H/MFI1L through MFI2H/MFI2L or one of the PCAA TTL flow sensor input
signal pairs. The TCAT terminal board is used to fan the magnetic input signal pair
to the TMR PCAA set: PCAA ( R), PCAA (S) and PCAA (T) through cabling. The
BCAA acquisition card provides signal conditioning to convert the variable frequency,
variable amplitude input to a digital pulse. The digital pulse feeds a counter used
to determine the frequency of the pulse train from the flow meter.
The inner loop valve position is fed back to the digital position loop in the PCAA
using Linear Variable Differential Transformer (LVDT) sensors. The TCAS terminal
board provides the six LVDT excitation signal pairs: LVDTEXH1_R/LVDTEXL1_R
through LVDTEXH6_R/LVDTL6_R. The primary-side signal is a 3.2 kHz sine wave
excitation with a 7.07 V RMS amplitude. The LVDT secondary-side is connected to
one of the twelve TCAT terminal board LVDT input signal pairs: LVDT1H/LSVT1L
through LVDT12H/LVDT12L. The TCAT terminal board is used to fan the LVDT
signal pair to the TMR PCAA set: PCAA ( R), PCAA (S) and PCAA (T) through
cabling. The BCAA acquisition board provides signal conditioning to convert the
RMS voltage from the secondary-side of the LVDT to a dc equivalent signal read
by the processor through analog-to-digital (A/D) converters.
The processor board will use one of the six independent digital servo regulators.
The Liquid Fuel Valve with Position Feedback servo regulator is sampled at a 100
Hz rate. Details of the Liquid Fuel Valve with Position Feedback digital regulator
are covered in the next section. The digital regulator output, ServoCurrentRef
is written to a digital-to-analog (D/A) converter. The output of the D/A is the
current command for the analog current regulator.
The BCAA acquisition board has six analog current regulators with a 10 mA
rating. Each current output provides an internal suicide protection relay controlled
by the BPPB software. Each of the six servo outputs supports either three-coil
servos or two-coil servos and each provides a jumper on the TCAS terminal board
to configure the output. The jumper is placed in the TMR position for the 3-coil
servo and placed in the Open position for the 2-coil servo.
Servo outputs 1 and 2 also provide a means to externally suicide the outputs the TCAS
inputs SVRL1/2. For the Mark VIe the PPRO provides an external contact connected
across SVRL1 and SVRL2. If the contact closes, the K1 relay is energized and the servo
output is isolated from the digital regulator control, providing a direct connection through
a current limiting resistor (15 mA fixed output), as long as the K1 relay is energized.

Liquid Fuel Valve with Position Feedback Servo System

Digital Servo Regulator – Liquid Fuel with Position
The Digital Liquid Fuel with Position regulator is a proportional plus integral (PI) outer
flow rate regulator with an inner proportional position regulator generating a servo current
command. The Liquid Fuel with Position output is based on a multi-loop control using the
liquid fuel flow rate feedback for the outer loop and the valve position for the inner loop
feedback. Refer to the diagram Digital Servo Regulator - Liquid Fuel with Position.
The outer flow rate loop derives its feedback from either a single flow rate input or the
maximum select of two flow rate inputs. For a single flow rate input, the configuration
parameter FlowInput1 is assigned to FlowRate1 through FlowRate4. For the maximum
select of two flow rates, the configuration parameter, FlowInput1 is equal to one of four
flow rate feedbacks and FlowInput2 is equal to a different one of the four flow feedbacks.
The Flow Rate Limit Check checks the range of the maximum select or the single
feedback depending on the configuration. If the flow rate feedback, Reg#_FlowFdbk is
less than FlowFdbkLoLim or Reg#_PressureFlowFdbk is greater than FlowFdbkHiLim
then the flow loop is assumed to be open loop and the SRV servo out will suicide.
The flow rate error, Reg#Ref minus Reg#FlowFdbk has an integrator convergence
error added to it. The objective of the convergence error is to keep the PI controller
between PCAA (R), PCAA (S) and PCAA (T) together. The PI output for (R, S and
T), Reg#_IntOut is read by the controller. The median selected value, Reg#_IntConv
is calculated from the three inputs. Each LFBV regulator for R, S, and T takes the
average, subtracts its own PI output value from this, multiplies it by a gain value,
K_Conv_OuterRegto come up with the convergence error to move the integrator for
PI R, S, and T together. The PI proportional gain, K_OuterReg and the integral time
constant, Tau_OuterReg provide the PI adjustments. The clamping is controlled by
the parameters: HiLim_OuterReg and LowLim_OuterReg. The PI outer loop output,
Reg#_IntOut is the position command for the inner position loop.
The inner position loop supports two feedback options: Single position feedback and
the maximum select of two position feedbacks. Setting PositionInput1 equal to one
of the twelve LVDT inputs can configure the single position feedback option. The
maximum select of two position feedbacks is selected when the configuration parameters,
The valve percent Each of the enabled position inputs run through a Position Calculation function that
representation can also be converts the dc volts signal representing RMS volts to a valve position in percent
configured for the opposite where 0% represents fully closed and 100% represents a fully open valve.
where 100% is equivalent
to fully closed. The Position Limit function’s input is the following based on the configuration: equal to
the Position Calculation output for a single position feedback or equal to the maximum
select from two Position Calculation outputs for the dual position input configuration. The
Position Limit function checks the feedback range of Reg#_Fdbk. The range defined in
percent over nominal is configurable using the parameter, Fdbk_Suicide; if enabled.

The proportional regulator error, Reg#_Error is equal to the position reference command
from the controller, Reg#Ref minus the position feedback, Reg#_Fdbk. Reg#_Error
is multiplied by a composite gain defined by the multiplication of the configuration
parameter, RegGain and the controller output, Reg#_GainAdj. The product of the
gain and position error defines a current in percent. The amount of current required to
After the initial configuration setting is made for the position loop, the user calibrates
the position valve feedbacks. This is done by using ToolboxST to select the LVDT
calibration mode and setting the controller output CalibEnab# equal to TRUE. In the
calibration mode, the user can use the servo output in the open-loop mode to force
the valve to the fully closed position and also to the fully open position. During the
calibration mode, the PCAA assigns the RMS voltage that represents the open and closed
position to the configuration parameters: MinVrms and MaxVrms. The user selects
Calibrate and Save to store the LVDT Excitation output voltage in the LVDT configurable
parameter ExcitMonCal. The excitation voltage is used to compensate for excitation
voltage changes during run time. The user must also verify that the LVDT parameter
ExcitSelect comes from the proper Excitation voltage source (R, S, or T)

Digital Servo Regulator - LiqFuel_wPos
Pulse Inputs
Mark VIe has shaft speed inputs on PTUR and PPRO and flow inputs on PSVO.
PCAA is intended for use with PTUR and PPRO so PCAA does not include shaft
speed inputs. PCAA includes two TTL (5v active) pulse rate inputs with output
power. TCAT has two fanned magnetic pulse rate inputs. All inputs are for flow
measurements associated with servo regulation and work up to 20,000 Hz. Pulse
input accuracy is greater than ±0.05% of full scale input.

Specifications
The following table provides information specific to the PCAA module
with the included TCAS terminal board.
Item Location Specification

Number of Inputs PCAA 25 thermocouple inputs
Ten 4-20 mA inputs
Two 4-20 mA or ±10 V configurable inputs
Two active pulse rate inputs
One servo coil suicide relay input affecting the first two servo outputs
Number of Outputs PCAA Six servo coil driver outputs
Two 4-20 mA outputs
One ±12 V dc power output
Six LVDT excitation outputs
JGPA Twelve 24 V power outputs for 4-20 mA transmitters
Signal Accuracy
Thermocouple inputs PCAA ±0.10% including all sources of error
±0.06% typical at 25ºC
Analog 4-20 mA inputs PCAA and ±0.25% including all sources of error
TCAT ±0.10% typical at 25ºC
Analog 0-10 V dc inputs PCAA ±0.50% including all sources of error
Seismic inputs TCAT ±2.00% including all sources of error
LVDT input TCAT ±1.00% including all sources of error
LVDT excitation monitor input PCAA ±1.00% including all sources of error
LVDT excitation output PCAA 7 V ac RMS ±5.00% including all error sources, ±3.00% typical at 25ºC
3.2 kHz output sine wave frequency.
60 mA output drive current capability.
(LVDT position calculation uses monitor value, not excitation output)
Servo driver output PCAA ±3.50% including all sources of error
Analog 4-20 mA output PCAA and ±0.75% including all sources of error
TCAT ±0.43% typical at 25ºC
24 V Power output JGPA and 24 V dc ±0.5% over current ranges of 0 to 25 mA.
TCAT
Other Specifications
Power supply input voltage 28 V dc ±5%
Physical
Size PCAA 33.02 cm high x 17.8 cm wide (13 in x 7 in)
Technology ALL Surface-mount
Temperature ALL Operating: -30 to 65ºC (-22 to +149 ºF)

Diagnostics
The module performs the following self-diagnostic tests:

• As a group, the 4-20 mA analog inputs have a specified high and low
current range for a valid signal. If a signal falls outside the specified
range, the signal health is declared to be bad.
scan. Measured values are compared against expected values, and are
used to confirm the health of the analog to digital converter circuits. If the
reference value does not fall within a defined range, an alarm is generated
to indicate a potential problem with signal accuracy.
• Analog output current is sensed on the terminal board using a small burden resistor.
The pack conditions this signal and compares it to the commanded current to
confirm the health of the digital to analog converter circuits.
• Thermocouple circuits are biased with a small dc current. If a thermocouple circuit
opens, the temperature signal goes to a full-scale negative reading.
• Seismic input circuits are biased with a small dc current. If a seismic sensor circuit
opens, an alarm is generated and the signal health is set to indicate a problem.
Details of the individual diagnostics are available from the ToolboxST. The diagnostic
signals can be individually latched, and then reset with the RESET_DIA signal if they go
healthy. Additional diagnostic information may be found in the module alarm listing.

Configuration
Analog Input
The PCAA is able to interface to several different types of 4-20 mA transmitters. Each
input has a jumper next to the terminals that is used to determine if the return terminal is
grounded or floating. The default position of the jumper is floating or open. The JGPA
board provides twelve 24 V dc terminals, one for each 4-20 mA transmitter input.
24 V dc PWR
CL
T 4-20 mA ASIH
250
Open
Two wire 4-20mA ASIL GND
transmitter
24 V dc PWR
CL
4-20 mA ASIH
T 250
Return Open
Three wire 4-20mA ASIL GND
transmitter
Externally powered 24 V dc PWR

4-20mA transmitter CL
4-20 mA ASIH
Power 250
Supply T Return Open
GND
ASIL

The last two 4-20 mA inputs on PCAA feature an additional jumper that removes the
250 Ω burden resistor for ±10 V dc input applications. When the jumper is in the MA
position, the input behaves the same as the first ten inputs. When the jumper is in the
VOLT position the burden resistor is removed and the input acts as a voltage input.
Voltage transmitter-
PWR
10V dc CL
+/-10V
250
T Return
ASIH VOLT
MA Open
GND
ASIL
Jumper Pos 1-2 Pos 2-3 Notes

JP1 OPEN GND Analog In 1
JP13 MA VOLT Analog In 11
JP14 MA VOLT Analog In 12
Analog Input Jumper Summary

Servo Output
Correct position selection for servo configuration jumpers are listed
under each servo regulator type.
Jumper Pos 1-2 Pos 2-3 Notes

JP15 TMR Simplex Servo1 output select
ThermCplUnit Parameter
The ThermCplUnit parameter affects the native units of the controller application variable.
It is only indirectly related to the tray icon and associated unit switching capability of the
HMI. This parameter should not be used to switch the display units of the HMI.
Do not change the ThermCplUnit parameter in the

ToolboxST application because these changes will require
corresponding changes to application code and to the
Format Specification or units of the connected variable.
This parameter modifies the actual value sent to the
controller as seen by application code. Application code
that is written to expect degrees Fahrenheit will not work
Caution correctly if this setting is changed. External devices, such
as HMIs and Historians, may also be affected by changes
to this parameter.

TCAT Core Analog Terminal Board
The Core Analog (TCAT) terminal board provides additional I/O terminals for
the PCAA module. It handles input signals that are fanned to one or three PCAA
modules. Inputs include twelve seismic, twelve LVDT, twenty four 4-20 mA, and
two magnetic pulse rate inputs. An individual 24 V dc power source is included for
all twenty four 4-20 mA inputs with half on TCAT and half on an adjacent JGPA
board. TCAT outputs consist of three 4-20 mA voted signals.
Field wire terminal points are provided by 120 pluggable Euro-style box terminals.
Terminal grouping is a set of 48 terminals, a set of 24, and a second set of 48. A JGPA
board adjacent to the TCAT field terminals provides twelve additional 24 V dc outputs for
4-20 mA devices as well as shield wire terminals. Power to JGPA is supplied by TCAT
connector P3 or P4 and is the diode-or of power from the connected PCAA modules.
Pairs of 68 pin cables provide connection between TCAT and one or more PCAA modules.
PR1 and PR2 go to a PCAA connected to the R IONet. PS1 and PS2 go to a PCAA
connected to the S IONet. PT1 and PT2 go to a PCAA connected to the T IONet. TCAT
provides an electronic ID on each cable connection. Cables are always used in pairs and
PCAA uses the electronic ID to confirm that correct TCAT cables are in place.

TCAT Terminal Board

Installation
TCAT with an underlying insulating plastic carrier mounts to a metal back
base. Screws are located at the top and bottom of the field terminals with a
third screw approximately in the center of the board.
Wiring
The TCAT terminal board features 120 pluggable Euro-style box terminals. A
JGPA board mounts adjacent to the TCAT terminal board and uses Euro-style
box terminals to provide forty eight shield termination points plus twelve 24 V
dc output terminals for 4-20 mA transmitters. The Euro-style box terminals on
TCAT accept conductors with the following characteristics:
TCAT Terminal Conductor Size Range

Conductor cross section solid 0.2 mm² NA
Conductor cross section solid NA 2.5 mm²
Conductor cross section stranded 0.2 mm² NA
Conductor cross section stranded NA 2.5 mm²
Conductor cross section stranded, with ferrule without plastic sleeve 0.25 mm² NA
Conductor cross section stranded, with ferrule without plastic sleeve NA 2.5 mm²
Conductor cross section stranded, with ferrule with plastic sleeve 0.25 mm² NA
Conductor cross section stranded, with ferrule with plastic sleeve NA 2.5 mm²
Conductor cross section AWG/kcmil 24 AWG NA
Conductor cross section AWG/kcmil NA 12 AWG
2 conductors with same cross section, solid 0.2 mm² NA
2 conductors with same cross section, solid NA 1 mm²
2 conductors with same cross section, stranded 0.2 mm² NA
2 conductors with same cross section, stranded NA 1.5 mm²
2 conductors with same cross section, stranded, ferrules without plastic sleeve 0.25 mm² NA
2 conductors with same cross section, stranded, ferrules without plastic sleeve NA 1 mm²
2 conductors with same cross section, stranded, TWIN ferrules with plastic sleeve 0.5 mm² NA
2 conductors with same cross section, stranded, TWIN ferrules with plastic sleeve NA 1.5 mm²

The following table lists the terminal assignments for the TCAT terminal board
TCAT Screw Terminal Assignments

1 AFT1H Analog Fanned #1 3 AFT2H Analog Fanned #2
2 AFT1L 4 AFT2L
5 AFT3H Analog Fanned # 3 7 AFT4H Analog Fanned # 4
6 AFT3L 8 AFT4L
10 AFT5L 12 AFT6L
14 AFT7L 16 AFT8L
18 AFT9L 20 AFT10L
22 AFT11L 24 AFT12L
25 APWR13 24 V power 39 AFT13H Analog Fanned # 13
26 no connect 40 AFT13L
27 APWR14 41 AFT14H Analog Fanned # 14
28 APWR15 42 AFT14L
30 APWR17 44 AFT15L
32 APWR19 46 AFT16L
33 APWR20 24 V power output for 4-20 mA 47 AFT17H Analog Fanned # 17
input devices
34 APWR21 48 AFT17L
36 APWR23 50 AFT18L
38 PCOM Common 52 AFT19L
54 AFT20L 56 AFT21L
58 AFT22L 60 AFT23L
61 AFT24H Analog Fanned # 24 63 VFI1H Seismic Input # 1
62 AFT24L 64 VFI1L
65 VFI2H Seismic Input # 2 67 VFI3H Seismic Input # 3
66 VFI2L 68 VFI3L
70 VFI4L 72 VFI5L

TCAT Screw Terminal Assignments
74 VFI6L 76 VFI7L
78 VFI8L 80 VFI9L
82 VFI10L 84 VFI11L
85 VFI12H Seismic Input # 12 87 MFI1H Mag pickup flow input
86 VFI12L 88 MFI1L
89 MFI2H Mag pickup flow input 91 LVDTH1 LVDT Input # 1
90 MFI2L 92 LVDTL1
93 LVDTH2 LVDT Input # 2 95 LVDTH3 LVDT Input # 3
94 LVDTL2 96 LVDTL3
98 LVDTL4 100 LVDTL5
113 LVDTH12 LVDT Input # 12 115 ATOH3 TMR 4-20 mA
114 LVDTL12 116 ATOL3
117 ATOH4 TMR 4-20 mA 119 ATOH5 TMR 4-20 mA
118 ATOL4 120 ATOL5

Operation
TCAT provides fanning of input signals to one or more PCAA modules. This is done with
high reliability passive circuits to ensure reliability in redundant applications.
TCAT accepts 28 V dc power from connected PCAA modules. It then does a

diode-or of the power sources to obtain redundant power input for the 24 V dc
outputs. Each 24 V output on TCAT is provided with an individual voltage regulator
that includes thermal shutdown for branch circuit protection.
Note An over current condition on one 24 V dc output will result in only that output
being shut down. When the overload is removed the terminal will return to 24 V dc.
TCAT accepts ±15 V dc power from connected PCAA modules. It then does a
diode-or of the power sources to obtain redundant power. The ±15 V dc power
is then used internally to voltage bias the seismic inputs.
Specifications
Please refer to the signal specifications listed in the PCAA documentation
for details of the signals on TCAT.
Item Specification
Number of inputs Twenty-four 4-20 mA signals.
Twelve seismic signals.
Twelve LVDT windings.
Two magnetic pulse rate flow signals.
Number of outputs Three 4-20 mA hardware voted analog outputs.
Twelve 24 V dc outputs with 25 mA capability.
Twelve 24 V dc additional outputs on JGPA with 25 mA capability.
Power supply voltage 28 V dc ±5% from one or more PCAA modules.
±15 V dc from one or more PCAA modules.
(both supplies routed through the cabling between PCAA and TCAT).
Pulse rate input Minimum signal for proper measurement at 2 Hz is 33 mVpk, and at 12 kHz is 827 mVpk.
Physical
Size 33.02 cm high x 17.8 cm wide (13 in x 7 in)
Technology Surface-mount
Temperature Operating: -30 to 65ºC (-22 to +149 ºF)

Diagnostics
All diagnostics associated with TCAT are performed in PCAA and
documented for that module.
Configuration
Analog Input
The TCAT is able to interface with several different types of 4-20 mA transmitters.
Each input has a jumper next to the terminals that is used to determine if the
return terminal is grounded or floating. The default position of the jumper is
floating or open. The combination of TCAT + JGPA provides twenty-four 24
V dc terminals, one for each 4-20 mA transmitter input.
24 V dc PWR
CL
4-20 mA ASIH
T 250
Return Open
transmitter
24 V dc PWR
CL
4-20 mA ASIH
T 250
Return Open
transmitter
Externally powered 24 V dc PWR

4-20mA transmitter CL
4-20 mA ASIH
Power 250
Supply T Return Open
GND
ASIL

JGPA Ground and Power Board
The PCAA core analog module and TCAT terminal board each provide twelve 4-20 mA
inputs that are not provided with 24 V power for field devices. The Ground and Power
(JGPA) board is a long narrow board that mounts adjacent to PCAA where shield wires
are terminated. JGPA provides shield wire terminal points that may be tied directly to
the underlying functional earth sheet metal or wired to a preferred grounding point. In
this respect it is very similar to the JGND board offered as an option with other Mark VIe
terminal boards. JGPA also provides twelve individually regulated and protected 24 V field
device power outputs. Each output is sufficient to power a single 4-20 mA field device.
JGPA receives power from PCAA or TCAT through a 28 V power feed on connector
P1. Power passes through twelve regulators and is available on TB3 screws 1-12.
TB3 uses terminals colored orange to set them apart from the terminals provided for
shield wire termination. Shield terminals are on TB1 and TB2 using twenty-four
conventional green euro-style box terminals for each.
28 V from 24 V
PCAA or regulators
TCAT
Terminal Board, top view
P1
U1 U2 U3 U4 U5 U6 IS200JGPAG1A U7 U8 U9 U10 U11 U12
E1 E2
TB1 TB3 TB2
Connection screws on
Euro terminal block
Terminal Board, side view
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
24 V field device
Shield wire power ouputs Shield wire
connections connections
(ground) (ground)
JGPA Terminal Board

Installation
JGPA is installed adjacent to the terminals on PCAA and TCAT. Power is provided
to JGPA through a cable from P1 to PCAA or TCAT. JGPA mounts on a sheet metal
bracket that is at ground potential. When mounted with conductive hardware the
ground path for JGPA shield wires is through the mounting bracket. If alternate shield
wire grounding is desired the JGPA may be mounted with non-conductive washers
and hardware. With isolated mounting, ground is defined by one or more wires
from JGPA shield ground terminals to the desired ground location.
The terminals on JGPA have the following conductor capacities.

Conductor cross section solid 0.2 mm²
Conductor cross section solid 2.5 mm²
Conductor cross section stranded 0.2 mm²
Conductor cross section stranded 2.5 mm²
Conductor cross section stranded, with ferrule without plastic sleeve 0.25 mm²
Conductor cross section stranded, with ferrule without plastic sleeve 2.5 mm²
Conductor cross section stranded, with ferrule with plastic sleeve 0.25 mm²
Conductor cross section stranded, with ferrule with plastic sleeve 2.5 mm²
Conductor cross section AWG/kcmil 24 AWG
Conductor cross section AWG/kcmil 12 AWG
2 conductors with same cross section, solid 0.2 mm²
2 conductors with same cross section, solid 1 mm²
2 conductors with same cross section, stranded 0.2 mm²
2 conductors with same cross section, stranded 1.5 mm²
2 conductors with same cross section, stranded, ferrules without plastic sleeve 0.25 mm²
2 conductors with same cross section, stranded, ferrules without plastic sleeve 1 mm²
2 conductors with same cross section, stranded, TWIN ferrules with plastic sleeve 0.5 mm²
2 conductors with same cross section, stranded, TWIN ferrules with plastic sleeve 1.5 mm²
Operation
JGPA provides regulated 24 V dc power to the twelve terminals of TB3.
Note An over current condition on one 24 V dc output results in only that output being
shut down. When the overload is removed, the terminal returns to 24 V dc.

Specifications
Item Specification
Number of ground points 24 terminals on TB1 and 24 terminals on TB2. Ground points use green terminal housings.
Outputs 12 outputs at 24 V dc ±5%, 30 mA capability on TB3. Power outputs use orange terminal
housings.
Physical
Size 33 cm high x 3.2 cm wide (13 in x 1.25 in)
Technology Through hole
Diagnostics
There are no diagnostics specifically associated with JGPA, only those relating
to devices that may be powered by JGPA.
Configuration
There is no configuration associated with JGPA.

Notes

PCLA Core Analog Module - Aero
Core Analog I/O for Aero (PCLA)

The Core Analog I/O for Aero-derivative gas turbines (PCLA) and associated Core Analog
(SCLS and SCLT) terminal boards provide a large portion of the analog signal I/O required
to operate an engine. PCLA and SCLT provide thermocouple inputs, RTD inputs, voltage
inputs, and 4-20 mA current loop inputs and outputs. PCLA can be applied in simplex
controller simplex I/O, dual controller simplex I/O, dual controller TMR I/O and TMR
controller TMR I/O control systems. A single SCLT terminal board fans signal inputs to
one or three connected PCLA(s).
PCLA provides the electrical interface between one or two Ethernet I/O networks and
the terminal board. It contains a processor board common to all Mark VIe distributed
I/O. Input to the PCLA module is through dual RJ-45 Ethernet connectors and a 28 V
dc power connector P1.
Field device I/O is connected through 72 Euro-style box terminals on the SCLS edge and is
connected through 48 Euro-style box terminals on the SCLT edge. Connection to SCLS
is through 96-pin J3 and 48-pin J4 connectors on SCLS. The connection between SCLS
and SCLT is through one 68-pin cable on the J2 connector on SCLS, and the JR/JS/JT
connector on SCLT.
GEH-6721L PCLA Core Analog Module - Aero System Guide 7-1

It is possible to use TMR The signals on TMR PCLAs are separated into two groups. Signal inputs that can be
PCLAs without SCLT if the fanned from a single input into a TMR PCLA are routed through the SCLT terminal
fanned inputs are not required. board. Signals that are dedicated to a single TMR PCLA are wired to the terminals
on SCLS. This creates the signal split as indicated in the following table.
SCLS Terminals SCLT Terminals

# Signals Signal Type Screws/ # Signals Signal Type Screws/
Signal Signal
8 Thermocouples 2 8 Fanned Thermocouples 2
4 Analog 4-20 mA inputs or ±10 V 4 4 Fanned Analog 4-20 mA inputs 4

inputs or ±5 V inputs or ±10 V inputs or ±5 V inputs
8 RTD 3 6 TMR (Triple Modular 2
Redundant) Analog 4-20
mA outputs
1 Analog 4-20 mA outputs 2 1 Common connection 4
1 Common connection 6
NC (Not Connected) Screws 8
PCLA Module
Ethernet Connectors
Terminals for field devices
Input P28 power
SCLT Connectors
PCLA Module fitting

screws
SCLS Base screws

4 corners
SCLS Plates
PCLA Core Analog

P1 for P28 power
Ethernet connectors
Magnified View of Connectors
BCLA is the acquisition board. The processor board resides on BCLA.

SCLS is the simplex terminal board.
Terminals for
field devices
BCLA
PROCESSOR
BOARD
J2
SCLS
PCLA Simplex with SCLS
SCLT is the terminal board, which can be used either for simplex Input/Outputs
or for fanned Inputs, redundant Outputs. When the SCLT is used with a simplex
PCLA module, the concept of fanning does not apply. Instead, the SCLT serves as
a simplex I/O expansion board as shown in the following figure.
BCLA SCLT
PROCESSOR
BOARD
J2 JT JS JR
SCLS
PCLA Simplex with SCLT for More I/O Channels

BCLA SCLT
PROCESSOR
BOARD
J2 JT JS JR
R
SCLS
BCLA BCLA
PROCESSOR PROCESSOR
BOARD BOARD
J2 J2
S T
SCLS SCLS
PCLA TMR with SCLT
Compatibility
The PCLA module is fully compatible with all other Mark VIe I/O packs and controllers.
The PCLA module is designed to run at frame rates of 10, 20, 40, 80, 160, 320 ms. PCLA
supports frame rates, redundancy, and networking as indicated in the following table.
PCLA IONet Frame SCLT Comments

Quantity Connections Rate Connections
Simplex 1 or 2 10 ms 0 or 1 SCLT optional on simplex configurations. One or two IONets
supported.
TMR 1 10 ms 1 TMR configurations only support one IONet per PCLA.

Installation
¾ To install the PCLA module
Refer to the PCLA Core 1. Securely mount the SCLS board with the help of four mounting
Analog figure in the Functional holes at the four corners.
Description section.
2. Directly plug the PCLA into the terminal board connectors J3 and J4.
3. Mechanically secure the pack using two-side mounting holes.
4. If SCLT is the part of configuration then the SCLT and a plastic insulator mount on a
sheet metal carrier that then mounts on a DIN-rail. Optionally, the SCLT and plastic
insulator mounts on a sheet metal assembly and then bolts directly to a cabinet.
5. Connect the SCLS to an optional associated SCLT terminal board using one 68-pin
cable. The connection between SCLS and SCLT is through one 68-pin cable on
the J2 connector on SCLS and the JR/JS/JT connector on SCLT.
6. If using a simplex configuration, connect the JR connector on SCLT to the J2
connector on SCLS through the 68-pin cable. If using a TMR configuration,
connectors on SCLT are paired by a network connection. For example, JR1
connects to the SCLS-PCLA through the R controller network, JS connects to
the SCLS-PCLA through the S controller, and JT connects to the SCLS-PCLA
through the T controller. It is important to fully seat the cable mounting screws,
finger-tight only, into PCLA and SCLT to ensure proper cable grounding. Failure
to secure the cables may result in an inability of PCLA to read the electronic
ID on SCLT and may reduce the quality of other signals.
Note When removing 68-pin cables, ensure that the hex posts in the board-mounted
connectors do not turn when backing out the cable thumbscrews.
7. Plug in one or two Ethernet cables depending on the system configuration. When
a single IONet connection is used, the module operates correctly over either
port. If dual connections are used, standard practice is to hook ENET1 to the
network associated with the R controller. However, the PCLA is not sensitive
to Ethernet connections, and negotiates proper operation over either port. If
TMR PCLA modules are present, the network connection should match with the
connection made to the SCLT. For example, the PCLA module with R IONet
connection should have cables that go to the SCLT JR connector.
8. Check grounding of the SCLS/SCLT shield wire terminals. In most applications,
shield ground terminals are electrically tied to the sheet metal the board is mounted
on. The mounting then supplies the ground path for the terminals.
9. Apply power to the module through the P1 connector on PCLA and check
the power and Ethernet status indicator lights.
10. Use the ToolboxST* application to configure the PCLA as necessary.
If the configuration being downloaded contains

distributed I/O with different module IDs than the
configuration currently running, the download may
install incorrect firmware to some I/O packs or modules.
If this occurs, make sure the controller is running the
Attention new configuration, restart the entire system, and then
start the ToolboxST Download Wizard again.

Operation
Module Overview
The PCLA module consists of two separate circuit boards in a single physical assembly.
The BCLA acquisition board and a processor board common to all Mark VIe distributed
I/O. BCLA is interfaced with an SCLS and an optional SCLT in simplex configuration.
In TMR, one SCLT is connected to three (SCLS-PCLA) sets. Typical block diagram of
the PCLA along with the terminal boards is displayed in the following figure.
THERMOCOUPLE INPUT Analog INPUT 4-20ma output

8*2 Terminals 4*4 Terminals 6*2 Terminals
4 X AI SCLT
28 v T
28 v S
Jumpers,Burden
Curr Fdbk T
Filter, current
28 v R
R, . filter
Curr Fdbk R
sense
Filter & Filter & Filter &
CJ CJ CJ
Filter Filter Filter
JT
To T PCLA
JS
JR To S PCLA
J2 J1 Input power supply
Analog INPUT
4*4 Terminals P28V power
THERMOCOUPLE INPUT 4-20ma output
8*2 Terminals 1*2 Terminals RTD INPUT
Jumpers,Burden R-
R, . filter 8*3 terminals
SCLS
Filter, current
sense
Filter &
CJ Filter
Filter
J3 J4
P3 P4
Current loops + Multiplexers BCLA

Multiplexers, Multiplexers, + gain
Suicide relays
gain gain
Internal
power
supply
Final Layer I,V sense + A to
D to A
MUX & A to D D
Adress,data
, & control Processor board
PCLA-SCLS-SCLT Block Diagram

BCLA Analog Processing Board
Inside the module cover the BCLA board provides power, analog signal conditioning, and
analog/digital conversion. BCLA is the main printed circuit board in the PCLA module.
This board provides the main ±15 V power and the majority of the digital and analog
interface to the processor board. In addition, this board provides the signal conditioning
required to interface the thermocouples, analog inputs, RTDs and the analog outputs.
Processor




Status LEDs
Processor LEDs

present
LED Status

ATTN
or module.
ATTN
every 4 sec

ID Line
The processor board and acquisition board within the PCLA I/O module contain electronic
ID parts that are read during power initialization. A similar part located on SCLS
terminal board. A similar part associated with cable connection on the SCLT terminal
board allows the processor to confirm correct matching of all board revisions plus
processor firmware and report board revision status to the system level control.
Power Management
The SCLS-PCLA includes power management in the 28 V input circuit. The management
applying power, the circuit provides a fast current limit function to prevent a power
disturbance in the module from propagating back onto the 28 V power systems. When
power is present and working properly, the green PWR indicator will light. If the current
limit function operates, the indicator will be out until the problem is cleared.
Connectors
• An RJ45 Ethernet connector named ENET1 on the module side is
• A second RJ45 Ethernet connector named ENET2 on the module side is
• A 3-pin power connector P1 on PCLA is the input point for 28 V dc
power for the module and terminal boards.
• Connector J2 on SCLS provides cable connections to an SCLT terminal board.
Thermocouples
The PCLA supports E, J, K, S, and T types of thermocouples. Simplex inputs
from field are terminated on SCLS. There are eight simplex thermocouple inputs.
TMR inputs from field are terminated on SCLT and then fanned out to three PCLA
modules. There are eight fanned (TMR) thermocouple inputs.
The PCLA input board accepts 16 (8 each from SCLS and SCLT) signals at mV levels
from the thermocouples wired to the terminal board. The thermocouple input section
consists of differential multiplexers, amplifier gain stages, a main multiplexer, and a
16-bit analog to digital converter that sends the digital data to the adjacent processor
board. Each input has hardware filters, and the converter samples at up to 120 Hz.
Thermocouples can be grounded or ungrounded. Thermocouples can be located up to 300

meters (984 feet) from the turbine I/O cabinet with a maximum two-way cable resistance
of 450 Ω. Linearization for individual thermocouple types is performed by the PCLA.

From PCLA TC Input Section
Terminal
Boards
SCLS/
SCLT
TC1
TC2
Differential Multiplexors
Multiplexor
TC3
A/D To
. . Converter Processor board
Thermocouple 16-bit
.
Inputs
. .
. .
TC16
Cold
Junction
reference
PCLA TC Section
A single cold junction is provided with each SCLS board. Three cold junctions, one for
each PCLA, are provided on SCLT. The module accepts a controller backup cold junction
value, CJBackup, in the event a problem is detected with the local sensor. The PCLA may
be configured to use a controller-provided remote cold junction value, CJRemote.
All thermocouple inputs are biased with a dc voltage that will drive the temperature signal
full scale negative in the event of an open wire. There is a configuration to report an
open thermocouple as fail cold or fail hot. Measurement accuracy for thermocouple
is 0.1% full scale, or 53 uV excluding the cold junction reading.
Thermocouple Limits
The units (°C or °F) are based Thermocouple inputs support a full-scale input range of -16.0 mV to + 63.0 mV.
on the ThermCplUnit settings. The following table demonstrates typical input voltages for different thermocouple
Refer to the Configuration, types versus the minimum and maximum temperature range. The cold junction
ThermCplUnit section. temperature is assumed to range from -30 to 65°C (-22 to 149 °F).
Thermocouple Type E J K S T
Low range, °F -60 -60 -60 0 -60
°C -51 -51 -51 -17.78 -51
mV at low range with reference at 70°C (158 °F) -7.174 -6.132 -4.779 -0.524 -4.764
High range, °F 1100 1400 2000 3200 750

°C 593 760 1093 1760 399
mV at high range with reference at 0°C (32 °F) 44.547 42.922 44.856 18.612 20.801

Analog Voltage or Current Inputs
±10 V voltage inputs
±5 V voltage inputs
4-20 mA current inputs
The inputs can be configured as current or voltage inputs using jumpers (JP#A)
on SCLS or SCLT. The PCLA accepts input voltage signals from the terminal
board, four input channels from SCLS and four input channels form SCLT. The
analog input section consists of analog multiplexer blocks, several gain and
scaling selections, and a 16-bit analog-to-digital converter.
PCLA Analog Input section
Terminal
Multi pl ex or
Board Analog to
SCLS / Digital
SCLT Converter
16-bit
4 each
inputs
Ethernet
Processor
communications
PCLA Analog Input Section
The inputs can be individually configured as ±5 V or ±10 V scale signals or 4-20

mA, depending on the input configuration. The terminal board provides a 250
Ω burden resistor when configured for current inputs yielding a 5 V signal at 20
mA. These analog input signals are first passed through a passive, low-pass filter
network with a pole at 75.15 Hz. The measurement accuracy offered by PCLA is
0.1% of the full scale over the operating temperature range.
The inputs can be configured as current or voltage inputs using jumpers (JP#A) on the
terminal boards SCLA/SCLT. The JP#A jumper removes the 250 Ω burden resistor
for voltage input applications. Each input has one more jumper (JP#B) on the board
that is used to determine if the return terminal is grounded or floating.

RTD Inputs
The PCLA accepts eight 3-wire The terminal board supplies a 1 mA dc multiplexed (not continuous) excitation
RTD inputs from the SCLS current to each RTD. The eight RTDs can be located up to 300 m (984 ft) from the
terminal board. turbine control cabinet with a maximum two-way cable resistance of 15 Ω. The
on-board noise suppression is provided on SCLS. The first two RTD channels (1 and
2) can be configured for either fast or normal mode scanning. Channels 3 to 8 are
only normal mode scan channels. Fast RTDs are scanned 25 times per second and
slow RTD channels are scanned four times per second using a time sample interval
related to the power system frequency. The processor performs linearization for
the selection of RTD types. PCLA RTD signals are as follows.
SCLS Terminal
Board BCLA
Excitation
8 RTD inputs
Noise J4
suppression
Excitation 1 V, I
A
sense,
RTD comp
B Signal 2 NS Processor
C and
Return 3 A-D
SCOM
A/ D converter
(8) RTDs
RTD
RTD Signals on PCLA

The following table indicates the types of RTD used and the temperature ranges.
RTD Type Name/Standard Configuration Name Range °C Range °F

**
100 Ω platinum SAMA 100 PT100_SAMA -51 to 593 -60 to 1100
DIN 43760 PT100_DIN -51 to 852 -60 to 1566
IEC-751
MINCO_PD
MINCO_PE
PT100_DIN
MINCO_PA MINCO_PA -51 to 630 -60 to 1167
IPTS-68
PT100_PURE
MINCO_PB MINCO_PB -51 to 630 -60 to 1166
PT100_USIND
Rosemount 104 Rosemount 104 -51 to 630 -60 to 1166
120 Ω nickel MINCO_NA MINCO_NA -51 to 259 -60 to 499
N 120
200 Ω platinum PT 200 MINCO_PK -51 to 629 -60 to 1164
MINCO_PN MINCO_PN -51 to 629 -60 to 1164
Note ** PCLA does not support the MINCO_CA and CU10 RTD types.

Analog Current Outputs (0-20 mA)
PCLA supports one simplex The PCLA 0-20 mA analog outputs are capable of 18 V compliance voltages. A 14-bit
0-20 mA output through SCLS Digital to Analog converter commands a current reference to the current regulator loop
and six 0-20 mA simplex/ TMR in the PCLA that senses current both in the PCLA and on the terminal board. In TMR
(voted) configurable set of mode, the three current regulators in each PCLA share the commanded current loads
outputs through SCLT. among themselves. Analog output status feedbacks for each output include:

• Individual current (output current sourced from within the PCLA)
• Total current (as sensed from the terminal board, summed current in TMR mode)
Analog Current Outputs
Each analog output circuit also includes a normally open mechanical relay to enable
or disable operation of the output. The relay is used to remove a failed output from a
TMR system allowing the remaining two PCLAs to create the correct output without
interference from the failed circuit. When the output enable relay is de-activated,
the output opens through the relay, open-circuiting that PCLA's analog output from
the customer load that is connected to the terminal board.
The mechanical relay’s second normally open contact is used as a status to indicate
position of the relay to the control and includes an LED. One amber LED per channel
indicates the output enable relay status for each analog output. When the enabled
output of a particular channel is normal, the LED is turned on. If incorrect operation
of the output is detected, the relay is automatically opened to protect the connected
device against excessive output current and the LED is turned off.

Conditions for Operating the Output Enable Relay to
De-energized State
The analog output enable relay is enabled only under the following conditions:
Condition 1:
• PCLA configuration must be TMR

• SuicEnable must be set to True from configuration
• Individual current feedback is greater than half of total current feedback plus
TMR_DiffLimit set from the ToolboxST application
Condition 2:
• PCLA configuration must be TMR

• SuicEnable must be set to True from configuration
• Percentage Difference in commanded AnalogOut value and Reference
feedback by Full-scale Analog Output is greater than D/A_ErrLimit
set from the ToolboxST application.
The accuracy of the output is 0.5% of full scale and the maximum
output load supported is 800 Ω.

Specifications
The following table provides information specific to the PCLA module with
the SCLS and SCLT terminal boards included.
Item Specification
Number of channels Simplex SCLS has 8 thermocouples, 4 analog inputs, 8 RTDs, 1 current output
SCLT (Simplex configuration) has 8 thermocouples, 4 analog inputs, 6 current outputs
Number of channels TMR SCLT (TMR configuration) has 8 thermocouples, 4 analog inputs, 6 current outputs
Power Supply Input voltage 28 V dc ±5% through P1 on PCLA
Power consumption 19.8 W maximum
Boards BCLA, SCLS, SCLT (optional), processor board
Fault detection Incorrect ID chip on each board
Physical
Operating Temperature -30 to 65 ºC (-22 to 149 ºF)
Technology Surface mount for all boards
Thermocouple
Number of channels 8 channels on SCLS, 8 channels on SCLT
Thermocouple types E, J, K, S, T thermocouples, and mV inputs
Span -16.0 mV to +63.0 mV
A/D converter resolution 16-bit A/D converter
Cold junction compensation Reference junction temperature measured
Cold junction temperature Cold junction accuracy 1.1 ºC (2 ºF)
accuracy
Measurement accuracy 53 µV (excluding cold junction reading). ±0.1% FS for simplex thermocouple inputs
Example: For type K, at 1000 °F, including cold junction contribution,
RSS error= 3 °F
74.2 µV (excluding cold junction reading). ±0.14% FS for fanned thermocouple inputs
Common mode rejection Ac common mode rejection 110 dB at 50/60 Hz, for balanced impedance input. Both
hardware and firmware filtering
Common mode voltage ±5 Volts
Normal mode rejection Rejection of 250 mV rms at 50/60 Hz, ±5%,
Both hardware and firmware filtering provides a total of 80 dB NMRR
Scan time All inputs are sampled at up to 120 times per second per input
Maximum lead resistance 450 W maximum two-way cable resistance, cable length up to 300 m (984 ft)
Fault detection High/low (hardware) limit check
Monitor readings from all thermocouples, cold junctions, calibration voltages, and
calibration zero readings
Analog Inputs
Number of channels 4 channels on SCLS, 4 channels on SCLT
Input span ±5 V dc, ±10 V dc, or 0-20 mA
Input span, transmitters 1 - 5 V dc across a precision resistor (usually 250 W)
A/D converter resolution 16-bit A/D converter
Scan time 8.33 ms for 60 Hz line frequency, 10 ms for 50 Hz line frequency

Item Specification
Measurement accuracy 0.1% of full scale over the full operating temperature range
Noise suppression on inputs A hardware filter with cut off frequency at 76 Hz, single pole down break at 500 rad/sec.
A software filter, using a two-pole, low-pass filter, is configurable for: 0 Hz, .75 Hz, 1.5
Hz, 3 Hz, 6 Hz, 12 Hz
Dc common mode rejection 80 dB with from -5 to +7 peak V common mode voltage
Common mode voltage range ±5 V (±2 V CMR for the ±10 V inputs)
Maximum lead resistance 15 W maximum two-way cable resistance, cable length up to 300 m (984 ft).
RTD Inputs
Number of channels 8 simplex channels of 3-wire RTDs on SCLS
RTD types 100, and 200 W platinum
120 W nickel
Scan time Normal scan 250 ms (4 Hz)
Fast scan 40 ms (25 Hz)
Measurement accuracy 0.1% of full scale
Common mode rejection Ac common mode rejection 60 dB at 50/60 Hz,
Dc common mode rejection 80 dB
Common mode voltage range ±5 Volts
Normal mode rejection Rejection of up to 250 mV rms is 60 dB at 50/60 Hz system frequency for normal scan
Maximum lead resistance 15 W maximum two-way cable resistance
Analog Outputs
Number of channels 1 simplex channel on SCLS, 6 simplex / TMR channels on SCLT
Accuracy 0.5% full scale with respect to the command
Load on output currents 800 W burden for 4-20 mA output
Compliance Voltage 18 V dc (based on output load value)

Diagnostics
The module performs the following self-diagnostic tests:
• A power up self test that includes checks of RAM, flash memory, Ethernet
ports, and most of the processor board hardware.
• As a group, the 4-20 mA analog inputs have a specified high and low
current range for a valid signal. If a signal falls outside the specified
range, the signal health is declared to be bad.
scan. Measured values are compared against expected values, and are
used to confirm the health of the analog to digital converter circuits. If the
reference value does not fall within a defined range, an alarm is generated
to indicate a potential problem with signal accuracy.
resistor. PCLA conditions this signal and compares it to the commanded current
to confirm the health of the digital to analog converter circuits.
• The analog output enable relay is continuously monitored for agreement
Thermocouple circuits are biased with a small dc current. If a thermocouple circuit

opens, the temperature signal goes to a full-scale negative reading. There is a
configuration to report an open thermocouple as fail cold or fail hot.
• Each RTD type has hardware limit checking based on preset (non-configurable) high
and low levels set near the ends of the operating range. If this limit is exceeded,
an alarm is generated to indicate a potential problem with the signal.
• The resistance of each RTD is checked and compared with the correct value.
If the resistance is high or low, a fault is created.
Details of the individual diagnostics are available from the ToolboxST application.
The diagnostic signals can be individually latched, and then reset with the
RESET_DIA signal if they go healthy. Additional diagnostic information may
be found in the PCLA Diagnostic Alarms section.

Configuration

Module_Configuration
Min_MA_Input Minimum mA for Healthy 4-20 mA Input 0 to 21 mA
Max_MA_Input Maximum mA for Healthy 4-20 mA Input 0 to 21 mA
RTDRate Select Scan Rate For RTD 1 and 2 Fast, Slow
SysFreq System Frequency (used for noise rejection) 60 Hz, 50 Hz
SCLS Analog Inputs Terminal board connected to PCLA Variable Edit (Input FLOAT)
AnalogIn1 First of 10 Analog Inputs – board variable. (Input FLOAT)
Variable edit
Low_Value Value of input in engineering units at low end -3.4082 e + 038 to 3.4028 e + 038
of scale
High_Value Value of input in engineering units at high end -3.4082 e + 038 to 3.4028 e + 038
of scale
Input _Filter Bandwidth of input signal filter Unused, 0.75, 1.5 Hz, 3 Hz, 6 Hz, 12
Hz
SCLS TC Inputs First of 8 thermocouples, point signal Variable Edit (Input FLOAT)
ThermoCpl Type Select thermocouples type or mV input Unused, mV, E, J, K , S , T
mV inputs are primarily for maintenance,
but can also be used for custom remote
CJ compensation. Standard remote CJ
compensation also available.
ThermCplHot Select Open TC to be reported Failed Hot Disable, Enable
ThermCplUnit Select TC Display Unit Deg °C or °F deg_F, deg_C
This value needs to match units of attached
variable. See section ThermCplUnit
Parameters
SCLS CJ Inputs Cold junction for TC 1- 8 Variable Edit (Input FLOAT)
ColdJuncType Select CJ Type Local, Remote
ColdJuncUnit Select CJ Display Unit Deg °C or °F deg_F, deg_C
SCLS RTD Inputs 8 RTD’s, point signal Variable Edit (Input FLOAT)

RTD Type Select RTD type or ohms input Unused,
RTD linearization supported by RTD PT100_DIN, MINCO_PA,
MINCO_PB, MINCO_PK,
MINCO_PA, MINCO_NA, MINCO_PN
OHMS, PT100_SAMA,
ROSEMONT_104
RTDUnit Select RTD Display Unit Deg °C or °F deg_F, deg_C
SCLT Auxiliary terminal Board Not Used, 1
SCLT Analog Inputs Terminal board connected to PCLA Variable Edit (Input FLOAT)
AnalogIn1 First of 10 Analog Inputs – board variable. (Input FLOAT)
Variable edit
Low_Value Value of input in engineering units at low end -3.4082 e + 038 to 3.4028 e + 038
of scale
High_Value Value of input in engineering units at high end -3.4082 e + 038 to 3.4028 e + 038
of scale
Input _Filter Bandwidth of input signal filter Unused, 0.75, 1.5 Hz, 3 Hz, 6 Hz, 12
Hz
TMR Diff Limit Difference limit for voted inputs in % of 0 to 100
high-low values
SCLT TC Inputs First of 8 thermocouples, point signal Variable Edit (Input FLOAT)
ThermoCpl Type Select thermocouples type or mV input Unused, mV, E, J, K, S, T
mV inputs are primarily for maintenance,
but can also be used for custom remote
CJ compensation. Standard remote CJ
compensation also available.
TMR DiffLimt Diagnostic limit, TMR input vote difference 0 to 100
Limit condition occurs if three temperatures in
R, S, and T differ by more than a preset value
(ºF); this creates a voting alarm condition.
ThermCplHot Select Open TC to be reported Failed Hot Disable, Enable
ThermCplUnit Select TC Display Unit Deg °C or °F deg_F, deg_C
SCLS CJ Inputs Cold junction for TC 1- 8 Variable Edit (Input FLOAT)

ColdJuncType Select CJ Type Local, Remote
ColdJuncUnit Select CJ Display Unit Deg °C or °F deg_F, deg_C
This value needs to match units of attached
variable.
TMR_DiffLimt Diag Limit, TMR Input Vote Difference, in Eng 0 to 100
Units

AnalogOut1 First of 7 analog outputs is simplex only - Variable edit (Output FLOAT)
board variable
Output_MA Type of output current, mA selection Unused, 0-20 mA
Hold Last Value
Output_Value
Low_Value Output in Engineering Units at low mA -3.4082 e + 038 to 3.4028 e + 038
High_Value Output value in Engineering Units at high mA -3.4082 e + 038 to 3.4028 e + 038
Suicide_Enab Suicide for faulty output current, TMR only Enable, disable
TMR SuicLimit Suicide threshold for TMR operation 0 to 20 mA
D/A Err Limit Difference between D/A reference and output, 0 to 100%
in % for suicide, TMR only

Point Signal Description-Variable Edit (Enter Signal Direction Type
Connection)
Variables
L3DIAG_PCLA I/O diagnostic indication Input BIT
LINK_OK_PCLA I/O link okay indication Input BIT
ATTN_PCLA I/O Attention Indication Input BIT
PS18V_PCLA I/O 18 V Power Supply Indication Input BIT
PS28V_PCLA I/O 28 V Power Supply Indication Input BIT
I/O packTmpr I/O pack temperature Input FLOAT
CJRemote1 SCLS CJ Remote value (deg °F) Output FLOAT
CJBackup1 SCLS CJ Backup value (deg °F) Output FLOAT
CJRemote2 SCLT CJ Remote value (deg °F) Output FLOAT
CJBackup2 SCLT CJ Backup value (deg °F) Output FLOAT
AO Feedbacks
AOutSuicide1_R Status of Suicide Relay for Output 1 Input FLOAT
AoutSuicide2 Status of Suicide Relay for Output 2 Input FLOAT
AOutFbk1_R Feedback, Output Current, mA Input FLOAT
AoutFbk2 Total feedback, Output Current, mA Input FLOAT

ThermCplUnit

Format Specifications or units of the connected variable.
to this parameter.

SCLS Core Analog Terminal Board
SCLS provides the J2 68 pin The Core Analog (SCLS) terminal board provides the terminal and signal routing
connectors for IS200SCLT into the BCLA board. Inputs include eight thermocouple inputs, four analog inputs
terminal board cable. and eight RTD inputs. An individual 24 V dc power source is included for all four
4-20 mA inputs on SCLS. SCLS output channel consist of one 4-20 mA simplex
output signal. Seventy-two pluggable Euro-style box terminals provide field wire
terminal points. Terminal grouping is three sets of 24 terminals each.
SCLS Terminals
# Signals Signal Type Screws/Signal

8 Thermocouples 2
4 Analog 4-20 mA inputs or ±10 V inputs or ±5 V inputs 4
8 RTD 3
1 Analog 4-20 mA outputs 2

Jumpers for
Analog Inputs
SCLT
connections
BCLA
location
Terminals for
field wires
SCLS Terminal Board

Installation
Refer to the PCLA Core Analog An I/O cable shield terminal is provided adjacent to the terminal blocks. Terminals 23, 24,
Module - Aero, Installation 43, 44, 45, 46, 47, and 48 are NOT Connected terminal points. Field device I/O is through
section for more information. 72 Euro-style box terminals on the SCLS edge and is through 48 Euro-style box terminals
on the SCLT edge. SCLS and SCLT accept conductors with the following characteristics:
SCLS Terminal Conductor Size Range
Conductor type Minimum Maximum

Conductor cross section solid 0.2 mm2 2.5 mm2
Conductor cross section stranded 0.2 mm2 2.5 mm2
Conductor cross section stranded, with ferrule without plastic sleeve 0.25 mm2 2.5 mm2
Conductor cross section stranded, with ferrule with plastic sleeve 0.25 mm2 2.5 mm2
Conductor cross section AWG/kcmil 24 AWG 12 AWG
2 conductors with same cross section, solid 0.2 mm2 1 mm2
2 conductors with same cross section, stranded 0.2 mm2 1.5 mm2
2 conductors with same cross section, stranded, ferrules without plastic sleeve 0.25 mm2 1 mm2
2 conductors with same cross section, stranded, TWIN ferrules with plastic sleeve 0.5 mm2 1.5 mm2
The following table lists the terminal assignments for the SCLS terminal board
SCLS Screw Terminal Assignments
Terminal number Signal Function

1 P24V1
2 20mA1
Analog Input 1
3 VDC1
4 RET1
5 P24V2
6 20mA2
Analog Input 2
7 VDC2
8 RET2
9 P24V3
10 20mA3
Analog Input 3
11 VDC3
12 RET3
13 P24V4
14 20mA4
Analog Input 4
15 VDC4
16 RET4
17 PCOM
18 PCOM
Common points
19 PCOM
20 PCOM

21 OP1
4-20 mA output 1
22 OR1
23 NC
No Connect
24 NC
25 TC 1H
Thermocouple 1
26 TC 1L
27 TC 2H
Thermocouple 2
28 TC 2L
29 TC 3H
Thermocouple 3
30 TC 3L
31 TC 4H
Thermocouple 4
32 TC 4L
33 TC 5H
Thermocouple 5
34 TC 5L
35 TC 6H
Thermocouple 6
36 TC 6L
37 TC 7H
Thermocouple 7
38 TC 7L
39 TC 8H
Thermocouple 8
40 TC 8L
41 PCOM
Common points
42 PCOM
43 NC
44 NC
45 NC Not connected
46 NC
47 NC
48 NC
49 RTD EXC1
RTD 1
50 RTD SIG1
51 RTD RET1
52 RTD EXC2
RTD 2
53 RTD SIG2
54 RTD RET2
55 RTD EXC3
RTD 3
56 RTD SIG3
57 RTD RET3

58 RTD EXC4
RTD 4
59 RTD SIG4
60 RTD RET4
61 RTD EXC5
RTD 5
62 RTD SIG5
63 RTD RET5
64 RTD EXC6
RTD 6
65 RTD SIG6
66 RTD RET6
67 RTD EXC7
RTD 7
68 RTD SIG7
69 RTD RET7
70 RTD EXC8
RTD 8
71 RTD SIG8
72 RTD RET8
Operation
The SCLS terminal board provides the customer terminals and signal routing into the
BCLA board. SCLS provides the J2 68 pin connectors for IS200SCLT terminal board
cable. Internal to the module the SCLS terminal board routes signals to connectors for the
BCLA analog processing board. Seventy-two pluggable Euro-style box terminals provide
Field wire terminal points. Terminal grouping is 3 sets of 24 terminals each.
SCLS Terminals

8 Thermocouples 2
4 Analog 4-20 mA inputs or ±10 V Inputs or ±5 V inputs 4
8 RTD 3
1 Analog 4-20 mA outputs 2

Thermocouples
The PCLA supports E, J, K, S, and T types of thermocouples and mV inputs.
Simplex inputs from field are terminated on SCLS. There are eight simplex
thermocouple inputs. Connect the thermocouple wires directly to the thermocouple
I/O terminal blocks as described in the table. These removable blocks are mounted
on the terminal board and held down with two screws.
The eight-thermocouple inputs can be grounded or ungrounded. They can be located

up to 300 m (984 ft) from the turbine control cabinet with a maximum two-way cable
resistance of 450 Ω. SCLS terminal boards feature high-frequency noise suppression and
one cold junction reference device. The I/O processor performs the analog-to-digital
conversion and the linearization for individual thermocouple types.
Thermocouple I/O Processor on

Terminal Board SCLS BCLA
TC inputs
Cold Junction Excitation
J3
Reference
Thermocouple
High
Noise
Low Suppression
A/D
Processor
Conv
Grounded or (8 thermocouples)
ungrounded ID
Thermocouple Inputs and I/O Processor, Simplex

SCLS can accommodate four simplex analog voltage or current inputs. They can be
located up to 300 m (984 ft) from the turbine control cabinet with a maximum two-way
cable resistance of 15 Ω. Connect the input and output wires directly to two I/O terminal
blocks mounted on the terminal board. Each block is held down with two screws. A
shield terminal attachment point is located adjacent to each terminal block.
SCLS can accommodate the following analog I/O types:

• Analog input, voltage ±5 V dc, ±10 V dc, current 4-20 mA

Terminal Board SCLS
4 circuits per I/ O CONTROLLER

terminal board
SYSTEM Noise
POWERED Suppr-
ession
+24 V dc P28V
Current Limit
+/-5,10 Vdc Vdc JP#A

T N
4-20 ma S 20 ma
250 ohms
Return
JP#B
Open Return
BCLA
PCOM
A/D
Excitation
J3
Gain Stage
Analog inputs
Voltage/
Current
Analog Inputs

Analog Voltage or Current Inputs Configurations
The SCLS is able to interface to several different types of 4-20 mA transmitters.
SCLS board provides four 24 V dc terminals, one for each 4-20 mA transmitter
input. The inputs can be configured as current or voltage inputs using jumpers
(JP#A). The JP#A jumper removes the 250 Ω burden resistor for voltage input
applications. The following configurations are supported:
Analog Input Configurations
Each input has a jumper (JP#B) on the board that is used to determine if the return terminal
is grounded or floating. The default position of the jumper is floating or open. With the
noise suppression and filtering, the input ac CMR is 60 dB, and the dc CMR is 80 dB.
Channel Jumper Pos 1-2 Pos 2-3

Analog In 1 JP1A mA VDC

Analog In 1 JP1B GND OPEN

RTD Inputs
Refer to the PCLA, Operation, SCLS can accommodate eight simplex 3-wire RTD inputs. The eight inputs feature
RTD Inputs section. group isolation from the grounding system. Connect the wires for the eight RTDs
directly to the terminal blocks on the SCLS board. A shield terminal strip attached
to chassis ground is located immediately to the left of each terminal block.
For CE mark applications, double-shielded wire must

be used. All shields must be terminated at the shield
terminal strip. Do not terminate shields located at the
end device.
Caution
The terminal board supplies a 1 mA dc multiplexed (not continuous) excitation current

to each RTD. The eight RTDs can be located up to 300 m (984 ft) from the turbine
control cabinet with a maximum two-way cable resistance of 15 Ω. The on-board noise
suppression is provided on SCLS. The first two RTD channels (1 and 2) can be configured
for either fast or normal mode scanning. Channels 3 to 8 are only normal mode scan
channels. Fast RTDs are scanned 25 times per second and slow RTD channels are scanned
4 times in a second using a time sample interval related to the power system frequency.
RTD open and short circuits are The processor performs linearization for the selection of RTD types. RTD open and
detected by out-of-range values. short circuits are detected by out-of-range values. RTD inputs are automatically
calibrated using the filtered calibration source and null voltages. The RTD inputs
and signal processing are illustrated in the following figure.
SCLS RTD Section and Input Processor Board BCLA RTD Section

RTD Accuracy
RTD Type Accuracy at 400 ºF

120 Ω nickel 2 ºF
200 Ω platinum 2 ºF
100 Ω platinum 4 ºF
Analog Output
SCLS supports one simplex analog (0-20 mA ) output capable of 18 V compliance voltage.
It can be located up to 300 m (984 ft) from the turbine control cabinet. Maximum load
resistance supported is 800 Ω. Connect output wires directly to two I/O terminal blocks
mounted on the terminal board. Each block is held down with two screws. The output
channel has noise suppression circuitry to protect against surge and high frequency noise.
I/ O CONTROLLER
BCLA AO
Terminal Board SCLS

A/D D/A
Analog output
J3
Relay Current
Regulator/
Power Supply
1 channel
Signal
N
S
Return SCOM
Analog Outputs

SCLS Specifications
Item Specification
Number of channels 8 Thermocouples, 4 Analog inputs, 8 RTDs, 1 Current Output
Supply Input P28 Through P1 on PCLA
Interface With SCLT and BCLA
Fault detection Incorrect ID chip
Physical
Size 5.625 inch x 9.1 inch
Temperature -30 to 65 ºC (-22 to 149 ºF)
Thermocouple
Number of channels 8 channels on SCLS
Cold junction temperature Cold junction accuracy 1.1ºC (2 ºF)
accuracy
Monitor readings from all thermocouples, cold junctions, calibration voltages, and calibration
zero readings
Analog Inputs
Number of channels 4 Channels
RTD Inputs
Number of channels 8 Channels of 3-wire RTDs
RTD types 100, and 200 Ω platinum
120 Ω nickel
Maximum lead resistance 15 Ω maximum two-way cable resistance
Analog Output
Number of channels 1 Channel
Load on output currents 800 Ω burden for 4-20 mA output
Compliance Voltage 18 V dc

Diagnostics
Each terminal board connector has its own ID device that is interrogated by
the I/O board. The board ID is coded into a read-only chip containing the
terminal board serial number, board type, revision number. If a mismatch is
encountered, a hardware incompatibility fault is created.
Thermocouples
• Each RTD type has hardware limit checking based on preset (non-configurable) high
and low levels set near the ends of the operating range. If this limit is exceeded,
an alarm is generated to indicate a potential problem with the signal.
• The resistance of each RTD is checked and compared with the correct value.
The diagnostic signals can be individually latched, and then reset with the
RESET_DIA signal if they go healthy. Additional diagnostic information may
be found in the PCLA Diagnostic Alarms section.
Analog Outputs
The board provides the voltage drop across a series resistor to indicate the output current.
The I/O processor creates a diagnostic alarm (fault) if the output goes unhealthy.

SCLS Configuration
The SCLS is able to interface to several different types of 4-20 mA transmitters.
SCLS board provides four 24 V dc terminals, one for each 4-20 mA transmitter
Each input has a jumper (JP#B) on the board that is used to determine if the return
terminal is grounded or floating. The default position of the jumper is floating or open.



SCLT Core Analog Terminal Board
The Core Analog (SCLT) terminal board provides additional I/O terminals
for the PCLA module. It handles input signals that are fanned to one or three
PCLA modules and also handles the voted output signals. Inputs include eight
thermocouple inputs, four analog voltage or current inputs, and six 4-20 mA outputs.
An individual 24 V dc power source is included for all four 4-20 mA inputs on
SCLT. Forty-eight pluggable Euro-style box terminals provide field wire terminal
points. The following table lists I/O supported by SCLT:
SCLT Terminals
8 Fanned Thermocouples 2
4 Fanned Analog 4-20 mA inputs or ±10 V Inputs 4
or ±5 V inputs
6 TMR (triple Modular Redundant) Analog 4-20 2
mA outputs
SCLT supports simplex or TMR configurations. The connection diagrams

for both the configurations are given below.
BCLA SCLT
PROCESSOR
BOARD
J2 JT JS JR
SCLS
PCLA Diagram - Simplex board (PCLA cover omitted to display board relationship)

BCLA SCLT
PROCESSOR
BOARD
J2 JT JS JR
R
SCLS
BCLA BCLA
PROCESSOR PROCESSOR
BOARD BOARD
J2 J2
S T
SCLS SCLS
PCLA-SCLT Connection Diagram - TMR Controller TMR I/O Configuration (PCLA Cover Omitted to Display
Board Relationship)
R SCLS-PCLA
Connections
Jumpers for Analog Inputs
S SCLS-PCLA
Connections
Terminals for field wires
T SCLS-PCLA
Connections
SCLT Terminal Board

Installation
Refer to the PCLA Core Analog An I/O cable shield terminal is provided adjacent to the terminal blocks. Field
Module - Aero, Installation device I/O is through 72 Euro-style box terminals on the SCLS side and is
section for more information. through 48 Euro -style box terminals on the SCLT side. SCLS and SCLT
accept conductors with the following characteristics:
SCLT Terminal Conductor Size Range

Conductor type Minimum Maximum
Conductor cross section solid 0.2 mm2 2.5 mm2
Conductor cross section stranded 0.2 mm2 2.5 mm2
Conductor cross section stranded, with ferrule without plastic sleeve 0.25 mm2 2.5 mm2
Conductor cross section stranded, with ferrule with plastic sleeve 0.25 mm2 2.5 mm2
2 conductors with same cross section, solid 0.2 mm2 1 mm2
2 conductors with same cross section, stranded 0.2 mm2 1.5 mm2
2 conductors with same cross section, stranded, ferrules without plastic sleeve 0.25 mm2 1 mm2
2 conductors with same cross section, stranded, TWIN ferrules with plastic sleeve 0.5 mm2 1.5 mm2
The following table lists the terminal assignments for the SCLT terminal board.
SCLT Screw Terminal Assignments

1 TC 9H
Thermocouple 9
2 TC 9L
3 TC 10H
Thermocouple 10
4 TC 10L
5 TC 11H
Thermocouple 11
6 TC 11L
7 TC 12H
Thermocouple 12
8 TC 12L
9 TC 13H
Thermocouple 13
10 TC 13L
11 TC 14H
Thermocouple 14
12 TC 14L
13 TC 15H
Thermocouple 15
14 TC 15L
15 TC 16H
Thermocouple 16
16 TC 16L
17 PCOM
Common Points
18 PCOM

19 P24V5
20 20mA5
Analog Input 5
21 VDC5
22 RET5
23 P24V6
24 20mA6
Analog Input 6
25 VDC6
26 RET6
27 P24V7
28 20mA7
Analog Input 7
29 VDC7
30 RET7
31 P24V8
32 20mA8
Analog Input 8
33 VDC8
34 RET8
35 PCOM
Common points
36 PCOM
37 OP2
4-20 mA output 2
38 OR2
39 OP3
4-20 mA output 3
40 OR3
41 OP4
4-20 mA output 4
42 OR4
43 OP5
4-20 mA output 5
44 OR5
45 OP6
4-20 mA output 6
46 OR6
47 OP7
4-20 mA output 7
48 OR7

Operation
SCLT provides fanning of input signals to one or more PCLA modules. This is done with
high reliability passive circuits to ensure reliability in redundant applications. SCLT
accepts 28 V dc power from connected PCLA modules. The power supplies from all
PCLAs are connected through diodes (Diode-OR) to obtain redundant power input for
the 24 V dc outputs. Each 24 V output on SCLT is provided with an individual voltage
regulator that includes thermal shutdown for branch circuit protection. The SCLT terminal
board provides the customer terminals and 68 pin connectors for SCLS terminal board
cable. Forty-eight pluggable Euro-style box terminals provide Field wire terminal points.
Note An over current condition on one 24 V dc output will result in only that output
being shut down. When the overload is removed the terminal will return to 24 V dc.
Thermocouples
The PCLA supports E, J, K, S, and T types of thermocouples and mV inputs.
Simplex/TMR inputs from field are ended on SCLT based on the configuration. There
are eight simplex thermocouple inputs. Connect the thermocouple wires directly to the
thermocouple I/O terminal blocks as described in the table. These removable blocks
are mounted on the terminal board and held down with two screws.
The 8-thermocouple inputs can be grounded or ungrounded. They can be located up to

300 m (984 ft) from the turbine control cabinet with a maximum two-way cable resistance
of 450 Ω. SCLT-SCLS terminal boards feature high-frequency noise suppression and
one cold junction reference device. The I/O processor performs the analog-to-digital
conversion and the linearization for individual thermocouple types.

SCLT can accommodate four simplex / Fanned analog voltage or current inputs. They
can be located up to 300 m (984 ft) from the turbine control cabinet with a maximum
two-way cable resistance of 15 Ω. Connect the input and output wires directly to two I/O
terminal blocks mounted on the terminal board. Each block is held down with two screws.
A shield terminal attachment point is located adjacent to each terminal block.
SCLT can accommodate the following analog I/O types:

• Analog input, voltage ±5 V dc, ±10 V dc, current 4-20 mA

The SCLT is able to interface to several different types of 4-20 mA transmitters.
SCLT board provides four 24 V dc terminals, one for each 4-20 mA transmitter
Each input has a jumper (JP#B) on the board that is used to determine if the return terminal
is grounded or floating. The default position of the jumper is floating or open. With the
noise suppression and filtering, the input ac CMR is 60 dB, and the dc CMR is 80 dB.



Analog Outputs
SCLT supports six simplex or voted analog (0-20 mA) outputs capable of 18
V compliance voltage. It can be located up to 300 m (984 ft) from the turbine
control cabinet. Maximum load resistance supported is 800 Ω. Connect output
wires directly to two I/O terminal blocks mounted on the terminal board. Each
block is held down with two screws. The output channels have noise suppression
circuitry to protect against surge and high frequency noise.
SCLT Specifications
Please refer to the signal specifications listed in the PCLA documentation
for details of the signals on SCLT.
Item Specification
Number of channels 8 Thermocouples, 4 Analog inputs, 6 Current Outputs
Interface With SCLS and field wires
Fault detection Incorrect ID chip
Power supply voltage 28 V dc ±5% from one or more PCLA modules
Physical
Size 6.25 inch x 7 .00 inch
Thermocouple
Number of channels 8 simplex or fanned channels on SCLT based on the configuration
Cold junction temperature accuracy Cold junction accuracy 1.1ºC (2 ºF)
Analog Inputs
Number of channels 4 simplex or fanned channels based on the configuration
Maximum lead resistance 15 Ω maximum two-way cable resistance, cable length up to 300 m (984 ft)
Analog Outputs
Number of channels 6 simplex or voted channels based on the configuration
Load on output currents 800 Ω burden for 0-20 mA output
Compliance Voltage 18 V dc

Diagnostics
Each cable connector on the terminal board has its own ID device that is
the terminal board serial number, board type, revision number, and the JR, JS,
JT connector location. A hardware incompatibility fault is created when the I/O
controller reads this chip and a mismatch is encountered.
Thermocouples
Each RTD type has hardware limit checking based on preset (non-configurable)
high and low levels set near the ends of the operating range. If this limit is
exceeded, an alarm is generated to indicate a potential problem with the signal.
The resistance of each RTD is checked and compared with the correct value.
Analog Outputs
The board provides the voltage drop across a series resistor to indicate the output current.
The I/O processor creates a diagnostic alarm (fault) if any of the outputs go unhealthy.
The analog output enable relay is enabled only under following conditions:
Condition 1:
• PCLA configuration must be TMR.

• SuicEnable must be set to True from configuration.
• Individual current feedback is greater than half of total current feedback plus
TMR_DiffLimit set from The ToolboxST application.
Condition 2:
• PCLA configuration must be TMR.

• SuicEnable must be set to True from configuration.
• Percentage Difference in commanded Analogout value and Reference
feedback by Full-scale Analog Output is greater than D/A_ErrLimit
set from The ToolboxST application.
The accuracy of the output is 0.5% of full scale and the maximum
output load supported is 800 Ω.

The SCLT is able to interface to several different types of 4-20 mA transmitters.
SCLT board provides four 24 V dc terminals, one for each 4-20 mA transmitter
applications. Following configurations are supported.
Each input has a jumper (JP#B) on the board that is used to determine if the return
terminal is grounded or floating. The default position of the jumper is floating or open.

Analog In 5 JP5A ma VDC


PCNO CANopen Master Gateway Module
CANopen Master Gateway (PCNO)

The CANopen Input/Output (PCNO) pack is an NMT CANopen master that maps I/O
from CANopen Woodward® GS6 and GS16 valves to Mark* VIe controllers on the
I/O Ethernet.
The module contains a processor board common to most Mark VIe distributed I/O
modules and an acquisition carrier board fitted with a COM-C CANopen communication
module supplied by Hilscher GmbH. The COM-C module provides a CANopen fieldbus
interface through a DE-9 D-sub receptacle connector. It serves as a CANopen master
supporting a transmission rate of 500 Kbaud communicating with one to five Woodward
GS6 or GS16 valves.
The PCNO supports the following redundancy options:
• Single I/O pack with single I/O Ethernet connection (no redundancy)
• Single I/O pack with dual I/O Ethernet connections
GEH-6721L PCNO CANopen Master Gateway Module System Guide 8-1

PCNO Simplified Hardware Diagram
Compatibility
The CANopen Master Gateway Terminal board (SPIDG1A) is used to mount the PCNO
and to supply an electronic ID. Its only connection is the interface to the PCNO itself, as
the CANopen connection is made to the DE-9 D-sub receptacle connector exposed on the
side of the PCNO. Visual diagnostics are provided through indicator LEDs on the PCNO.
Terminal Board SPIDG1A

Control mode Simplex - yes Dual - no TMR - no Hot-backup-no
Note Control mode refers to the number of I/O packs used in a signal path. Simplex
uses one I/O pack with one or two network connections

Installation
¾ To install the PCNO pack
1. Securely mount the SPID terminal board.
2. Directly plug the PCNO into the terminal board connector.
3. Mechanically secure the packs using the threaded inserts adjacent to the Ethernet
ports. The inserts connect to a mounting bracket specific to the terminal board
type. The bracket should be adjusted so there is no right angle force applied
to the DC-37 pin connector between the pack and the terminal board. This
adjustment is required once during the life of the product.
operates over either port. If dual connections are used, standard practice is to hook
ENET1 to the network associated with the R controller; however, the PCNO is not
sensitive to Ethernet connections and will negotiate proper operation over either port.
5. Connect and secure the CANopen cable into the DE-9 D-sub receptacle connector.
The signal lines used are:
CAN_H CAN bus line

CAN_L CAN bus line
CAN_G CAN ground
(CAN_SHIELD) Optional shield around CAN_H and CAN_L.
As per CANopen requirements, the CANopen must be terminated on both ends of the
network, using a 120 ohm resistor across CAN_H and CAN_L. Additional details may be
found in the CANopen Additional specification “Cabling and connector pin assignment”
(CiA 303-1), which is available from the “Can-in-Automation e.V” user organization.
Note This manual can be ordered from the following website:
6. Apply power to the connector on the side of the pack. It is not necessary to
insert the connector with power removed from the cable. The PCNO has inherent
soft-start capability that controls current inrush on power application.
7. Use the ToolboxST* application to configure the I/O pack and CANopen as necessary.
Note It is recommended that a service loop/strain relief be applied to the CANopen

cable within 4 inches of the CAN connector to provide increased protection and cable
support.

Wizard again.

Operation
Processor




Status LEDs
Processor LEDs

present
LED Status

ATTN
or module.
ATTN
every 4 sec

PCNO Specific LEDs
Note If the following two LEDs (SYS RUN and NOT RDY) are off at the same time,
either power is not applied or the COM-C module is being reset. In all other conditions,
one or the other LED will be on (though maybe flashing).
A green LED labeled SYS RUN indicates two different conditions as follows:
• LED solid on – the COM-C module is configured and ready to communicate

with Woodward GS6 or GS16 valves. It is not required that the module
should have established communication with any valves.
• LED flashing non-cyclically (3 times at 5 Hz then 8 times between 0.5 Hz and 1 Hz)
– the COM-C module is either missing a CANopen configuration or its watchdog
timer maintained with the I/O pack firmware has timed out (30 ms timeout)
A yellow LED labeled NOT RDY indicates three different conditions as follows:
• LED flashing slowly cyclically (1 Hz) – COM-C module is waiting for a firmware load
• LED flashing fast cyclically (5 Hz) – COM-C firmware download in progress
• LED flashing non-cyclically (3 times at 5 Hz then 8 times between 0.5 Hz
and 1 Hz) – serious COM-C hardware for firmware error
A green LED labeled COMM OK is ON when a message is sent on the CAN bus.
A red LED labeled COMM ERR indicates the following conditions:
• LED solid on – the COM-C module has encountered configuration errors

• LED out – check COMM OK LED for communication status
CANopen Gateway Hardware

The PCNOs COM-C module is built on a CANopen core, which is based on the
Hilscher GmbH family of communication network interface modules.
The COM-C’s firmware, residing in a flash memory, is released as part of the PCNO
firmware and downloaded to the COM-C’s flash at I/O pack startup time only if necessary
(for instance when the PCNO firmware is released with an updated COM-C firmware).
The COM-C module requires a CANopen configuration file that is loaded from
the ToolboxST application. The configuration file specifies the PCNO master
parameter set as well as other standard I/O pack configuration files and requires
a PCNO reboot following the load if changed. As is the case with the COM-C
firmware file, the CANopen configuration file is stored in COM-C flash and
only downloaded from PCNO flash if necessary.
Data Flow between PCNO and Controller

Control data is passed between the PCNO I/O pack and the Mark VIe
through IONet Ethernet Global Data (EGD). PCNO uses multiple Class
1 data exchanges for inputs and outputs.

Data Flow between PCNO and Woodward GS6 or GS16 Valve
The PCNO sends outputs to the Woodward GS6 or GS16 valves in multiple RPDOs
(Receive Process Data Objects) and receives inputs in multiple TPDOs (Transmit
Process Data Objects). Fast Request with Demand and Command Bits messages
(Receive PDO 1) are sent each frame to all connected valves with a synchronization
jitter of up to 1 ms. Actual Position and Status from Valve messages (Transmit PDO
1) are received in response with a possible 1 frame period jitter.
Parameters and Online Loads

The only part of the configuration that may be changed by online loads is
the signals connected to I/O variables. Otherwise the I/O pack must be
rebooted if any other changes are needed.
Health
Each CANopen input has an associated health bit allocated in the inputs EGD exchange.
The PCNO sets input health to unhealthy when any of the following conditions occur:
• Loss of communication between the associated the Woodward GS6

valves and the CANopen master.
• Loss of COM-C module READY/RUN status.
• Standard I/O Ethernet input validation error.
Woodward GS6 and GS16 Valve Diagnostics

A number of diagnostic inputs are returned from the Woodward GS6 and GS16 valves.
For example, a “DigitalComErr” Boolean input is returned to provide an indication
of CAN communications health. Details on the meanings of these diagnostic inputs
and associated troubleshooting actions can be found in the Woodward Installation and
Operation Manual for the GS6 Gas Metering System (Manual 26171) and Installation
and Operation Manual for the GS16 Gas Metering System (Manual 26228).
Note As part of the valve purchase, the manual for corresponding valve is provided to
the customer.

Specifications
Item PCNO Specification
CANopen connection RS-485 interface through DE-9 D-sub receptacle connector
Transmit time CANopen output data from Mark VIe is received by the PCNO once per frame, up to 100
times per second. Woodward GS6 or GS16 valve RPDO1 messages for all valves are
transmitted each frame, and RPDO2 and RPDO3 messages are transmitted per valve on
a round robin basis each frame.
Receive time CANopen inputs are received by the PCNO COM-C module from the Woodward GS6
or GS16 valve as a response to their receipt of RPDO messages. CANopen inputs are
then scanned by the PCNO firmware and transmitted to the Mark VIe once per frame,
up to 100 times per second. Woodward GS6 or GS16 valves input PDO’s are received
synchronously: TPDO1 received each frame from all valves, and TPDO2-6 received
per valve on a round robin basis.
CANopen transmission speeds 500 Kbits/sec: 5 valves at 500 Kbaud with a 10 millisecond Mark VIe frame rate.
Number of slaves 1 - 5 Woodward GS6 or GS16 valves per CANopen bus
Physical
Size 8.26 cm high x 4.19 cm wide x 12.1 cm deep (3.25 in. x 1.65 in. x 4.78 in.)
Diagnostics
A green LED labeled PWR shows the presence of control power.
A red LED labeled ATTN shows pack status. This LED indicates five
different conditions as follows:
• LED out - no detectable problems with the pack

• LED solid on - a critical fault is present that prevents the pack from operating
critical faults include detected hardware failures on the processor or acquisition
boards, or there is no application code loaded.
• LED flashing quickly (¼ cycle) - an alarm condition is present in the pack
such as putting the wrong pack on the terminal board, or there is no terminal
board, or there were errors loading the application code
• LED flashing at medium speed (¾ cycle) - the pack is not online
• LED flashing slowly (2 cycle) - the pack has received a request to flash the
LED to draw attention to the pack this is used during factory test or as an aid to
confirm physical location against ToolboxST* application settings.

A green LED labeled LINK is provided for each Ethernet port to indicate
that a valid Ethernet connection is present.
A yellow LED labeled TxRx is provided for each Ethernet port to indicate when
the pack is transmitting or receiving data over the port.
If the following two LEDs (SYS RUN and NOT RDY) are off at the same time,
either power is not applied or the COM-C module is being reset. In all other
conditions, one or the other LED will be on (though maybe flashing). The SYS
RUN LED lights when the COM-C module’s SYS LED is green; the NOT RDY
LED lights when the COM-C module’s SYS LED is yellow.
A green LED labeled SYS RUN indicates three different conditions as follows:
• LED solid on – the COM-C module has established communication with

at least one Woodward GS6 or GS16 valve
• LED flashing fast cyclically (5 Hz) – CANopen master is configured and
ready to communicate with Woodward GS6 or GS16 valves but is not
connected or otherwise unable to communicate
– the COM-C module is either missing a CANopen configuration or its watchdog
A green LED labeled COMM OK mimics the COM-C COM LED when it is yellow:
• LED solid on – the COM-C module is holding the CANopen token and is able
to transmit CANopen telegrams to Woodward GS6 or GS16 valves
• LED out – the COM-C is not communicating on the CANopen network
A red LED labeled COMM ERR mimics the COM-C COM LED when it is red:
• LED solid on – the COM-C module has encountered a communication


PDIA Discrete Input Module
Discrete Input (PDIA)

The Discrete Input (PDIA) pack provides the electrical interface between one or
DISCRETE IN
PWR
two I/O Ethernet networks and a discrete input terminal board. The pack contains a
1
2
3
processor board common to all Mark* VIe distributed I/O packs and an acquisition
ATTN
4
6
5 board specific to the discrete input function. The pack accepts up to 24 contact
inputs and terminal board specific feedback signals, PDIA accepts three different
LINK voltage levels (with types TBCIH1, H2 and H3 terminal boards). Connections for
7 ENET1
8
10
9 TxRx the isolated discrete input board with voltage sensing (with type TICI board) are
11
12 available. System input to the pack is through dual RJ45 Ethernet connectors and a
LINK
three-pin power input. Discrete signal input is through a DC-37 pin connector that
13 ENET2
14
15
connects directly with the associated terminal board connector. Visual diagnostics
TxRx
16
18
17 are provided through indicator LEDs.
IR PORT
19
20
21
22
22
24
IS220PDIAH1A
In 240 V ac applications, do not inadvertently

cross-connect the 240 V ac and the dc voltages. The peak
voltage will exceed the MOV rating resulting in a failure.
The reason for this failure is that most ac supplies

operate with a grounded neutral, and if an inadvertent
connection between the 125 V dc and the ac voltage is
created, the sum of the ac peak voltage and the 125 V dc
Caution is applied to MOVs connected between dc and ground.
However, in 120 V ac applications, the MOV rating can
withstand the peak voltage without causing a failure.
GEH-6721L PDIA Discrete Input Module System Guide 9-1

PDIAH1A
Discrete Input
Pack Processor board
Application board
Single or dual
Ethernet cables
ENET1
TBCI Contact Input
Terminal Board
(3 types plus TICI) ENET2
External 28 V dc
power supply, or use
on-board power
Contact Inputs
(24) ENET1
ENET2
28 V dc
One,
two, or ENET1
three
PDIA ENET2
packs
28 V dc
Compatibility
PDIAH1A is compatible with five types of discrete contact input terminal boards,
including the TBCI boards, TICI boards, STCI boards, but not the DIN-rail mounted
DTCI board. The following table gives details of the compatibility:
Terminal Board TBCIH1, H2, H3, and TICI DTCI STCIH1A

Control mode Simplex-yes Dual - yes TMR-yes No Simplex-yes

Installation
¾ To install the PDIA pack
2. Directly plug the PDIA I/O pack into the terminal board connectors.
Note The PDIA mounts directly on a Mark VIe terminal board. Simplex terminal
boards have a single DC-37 pin connector that receives the PDIA. TMR-capable
terminal boards have three DC-37 pin connectors, one used for simplex operation,
two for dual operation, and three for TMR operation. PDIA directly supports all of
these connections.
See also Auto-Reconfiguration section.

Wizard again.

Operation
Processor




Status LEDs
Processor LEDs

present
LED Status

ATTN
or module.
ATTN
every 4 sec

Input Signals
The discrete input acquisition board provides the second stage of signal conditioning
and level shifting to interface the terminal board inputs to the control logic. Initial
signal conditioning is provided on the terminal board. The discrete input acquisition
input circuit is a comparator with a variable threshold. Each input is isolated
from the control logic through an opto-coupler and an isolated power supply.
The inputs are not isolated from each other. Each of the twenty-four inputs has
filtering, hysteresis, and a yellow status LED, that indicates when an input is picked
up. The LED will be OFF when the input is dropped-out.
INX
Threshold Ref +
- Vout
P3V3
CINX In+
+
Rin -
In-
Stat
ICOM DCOM
Variable Threshold
The input threshold is derived from the contact wetting voltage input terminal. In
most applications this voltage is scaled to provide a 50% input threshold. This
threshold is clamped to 13% to prevent an indeterminate state if the contact wetting
voltage drops to zero. If the contact wetting voltage drops below 40% of the nominal
voltage, the under-voltage detector annunciates this condition to the control. A
special test mode is provided to force the inputs from the control pack. Every
four seconds, the threshold is pulsed high and then low and the response of the
opto-couplers is checked. Non-responding inputs are alarmed.
ID Line
Power Management

Connectors
Specifications
Item Specification
Number of channels 24 dry contact voltage input channels
Input isolation in pack Optical isolation to 1500 V on all inputs
Input Filter Hardware filter, 4 ms
Ac voltage rejection 60 V rms at 50/60 Hz at 125 V dc excitation
Frame rate System dependent scan rate for control purposes
1,000 Hz scan rate for sequence of events monitoring
Fault detection Loss of contact input excitation voltage
Non-responding contact input in test mode
Incorrect terminal board
Diagnostics

• Monitoring for loss of contact input excitation voltage on the terminal board
• Detecting a non-responding contact input during diagnostic test. In this test, the
threshold is pulsed high and low and the response of the opto-couplers is checked.

Configuration

PDIA_Mod_Configuration
System Limits Enable all system limit checking Enable, disable
Redundancy Redundancy mode of the pack Simplex, Dual, TMR
PDIA_Input Terminal board connected to PDIA Connected, not connected
Contact Input
Signal Invert Inversion makes signal true if contact is open Normal, Invert
Sequence of Events Record contact transitions in sequence of events Enable, disable
Diag Vote Enable Enable voting disagreement diagnostic Enable, disable
Signal Filter Contact input filter in msec 0, 10, 20, 50
IS22PDIA Direction Type
L3DIAG_PDIA I/O diagnostic indication Input BIT
LINK_OK_PDIA I/O link okay indication Input BIT
ATTN_PDIA I/O attention indication Input BIT
IS200TBCI PointDefs
Contact01
:
Contact24

TBCI Contact Input with Group Isolation
The Contact Input with Group Isolation (TBCI) terminal board accepts 24 dry
contact inputs wired to two barrier-type terminal blocks. Dc power is wired to
TBCI for contact excitation. The contact inputs have noise suppression circuitry
to protect against surge and high-frequency noise.
x
x
JT1 DC-37 pin
x 2
x 1
x 3 connectors with
x 4
x 5 latching fasteners
x 6
12 Contact x 7 JE1 JE2
x 8
Inputs x 10
x 9
x 12
x 11
x 14
x 13
x 16
x 15 JJ -- Port
Port Connections:
Connections:
x 17 Plug in
Plug inI/O
I/O Pack(s)
pack(s)
x 18
x 19 JS1 for Mark VIe system
x 20
x 21
Shield x 22
x 23
Bar x 24 or
x
Cables
Cables to
to
x boards for
boards for Mark VI
VI;control
x 26
x 25
x 28
x 27 The number and location
x 29 depends on the level of
12 Contact x 30
x 32
Inputs x 33 JR1
x 34
x 36
x 35
x 37
x 38
x 39
x 40
x 41
x 42
x 43
x 44
x 45
x 46 Barrier type terminal blocks
x 47
x 48 can be unplugged from
x
x board for maintenance.
TBCI Contact Input Terminal Board



Control System TBCI Functionality

Mark VI control TBCI works with VTCC/VCRC and supports simplex and TMR
applications. Cables with molded plugs connect TBCI to VME
rack where the VCCC or VCRC processor board is located.
Both board versions TBCIH_B and TBCIH_C work correctly
with Mark VI and are functionally identical.
Mark VIe control TBCI works with the PDIA I/O pack and supports simplex,
dual, and TMR applications. One, two, or three PDIAs can be
plugged directly into the TBCI. Mark VIe requires the C version
of this board for correct mechanical alignment of connector
JT1 with I/O pack mechanical support.
Mark VIeS control Board revisions TBCIS1C, TBCIS2C, and TBCIS3C are safety
certified.
Board Revision Mark VI Mark VIe Mark VIeS Comments

IS200VCCC, VCRC IS220PDIA IS200YDIA
TBCIH1A Yes, all versions Yes, all versions No 125 V dc nominal, replace
with H1C
TBCIH1B Yes, all versions Yes, all versions No 125 V dc nominal, replace
with H1C
TBCIH1C Yes, all versions Yes, all versions No 125 V dc nominal
TBCIH2B Yes, all versions Yes, all versions No 24 V dc nominal, replace
with H2C
TBCIS1C No Yes, all versions Yes, all versions 125 V dc nominal, safety
certified
certified
certified
Installation
Wiring
Connect the wires for the 24 dry contact inputs directly to two I/O terminal
blocks on the terminal board. These blocks are held down with two screws and
can be unplugged from the board for maintenance. Each block has 24 terminals
accepting up to #12 AWG wires. A shield terminal strip attached to chassis ground
is located immediately to the left of each terminal block.

Power Connection
Connect TBCI to the contact excitation voltage source using plugs JE1 and
JE2, as it is displayed in following figure.
Cabling Connections
In a simplex system, connect TBCI to the I/O processor using connector JR1. In
a TMR system, connect TBCI to the I/O processors using connectors JR1, JS1,
and JT1. Cables or I/O packs are plugged in depending on the type of Mark VI,
Mark VIe, or Mark VIeS system, and the level of redundancy.
Note For a Mark VIe/VIeS control system, the I/O packs plug into TBCI and attach to
side-mounting brackets. One or two Ethernet cables plug into the pack. Firmware may
need to be downloaded.
Contact Input Terminal Board TBCI 1 1

JT1
x
3 3
Input 1 (Return)
x 1 Input 1 (Positive) JE1 JE2
x 2
x 3 Input 2 (Positive)
Input 2 (Return) x 4 Contact Excitation
Input 3 (Return) x 6 Source, 125 Vdc
Input 4 (Return)
x 8
Input 5 (Return) x 9 Input 5 (Positive)
x 10
Input 6 (Return) x 12
J - Port Connections:
x 18 JS1 Plug
J- in I/O
Port Pack(s)
Connections:
Input 10(Return) x 20 for Mark
Plug VIepacks
in I/O and
Input 11(Return)
x 22 VIeS control system
Input 12(Return) x 23 Input 12 (Positive)
x 24 or
x
Cables to
boards
Cables to Mark VI control.
for
boards for Mark VI
x control
The systemand location
number
x 25 Input 13 (Positive) The number
Input 13 (Return) x 26 depends onand
thelocation
level of
Input 14 (Return)
x 27 Input 14 (Positive) depends on the level of
x 28
Input 15 (Positive)
redundancy required.
Input 16 (Return)
x 32 JR1
Input 17 (Return)
x 34
Input 20 (Return)
x 40
Input 22 (Return)
x 43 Input 22 (Positive) Inputs 22, 23, 24
x 44
Input 23 (Return)
x 46 are 10 mA, all
Input 24 (Return)
x 48 others are 2.5 mA
x
Terminal Blocks can be unplugged Up to two #12 AWG wires per

from terminal board for maintenance point with 300 volt insulation
TBCI_1C Terminal Board Wiring and Cabling

Operation
Filters reduce high-frequency noise and suppress surge on each input near the point
of signal entry. The dry contact inputs on H1 are powered from a floating 125 V dc
(100-145 V dc) supply from the turbine control. The 125 V dc bus is current limited
in the power distribution module prior to feeding each contact input. H2 and H3
versions use lower voltages as it is displayed in the specification table.
The discrete input voltage signals pass to the I/O processor, which sends them through
optical isolators providing group isolation and transfers the signals to the system
controller. The reference voltage in the isolation circuits sets a transition threshold
that is equal to 50% of the applied floating power supply voltage. The tracking is
clamped to go no less than 13% of the nominal rated supply voltage to force all
contacts to indicate open when voltage dips below this level.
Contact Input Circuits
A pair of terminal points is provided for each input, with one point (screw) providing the
positive dc source and the second point providing the return (input) to the board. The
current loading is 2.5 mA per point for the first 21 inputs on each terminal board. The last
three have a 10 mA load to support interface with remote solid-state output electronics.
Contact input circuitry is designed for NEMA Class G creepage and clearance.

Specifications
Item Specification
Number of channels 24 contact voltage input channels
Excitation voltage H1 / S1: Nominal 125 V dc, floating, ranging from 100 to 145 V dc
H2 / S2: Nominal 24 V dc, floating, ranging from 18.5 to 32 V dc
H3 / S3: Nominal 48 V dc, floating, ranging from 32 to 64 V dc
Input current H1 / S1 (for 125 V dc applications):
First 21 circuits draw 2.5 mA (50 kΩ)
Last three circuits draw 10 mA (12.5 kΩ)
H2 / S2 (for 24 V dc applications):
First 21 circuits draw 2.5 mA (10 kΩ)
Last three circuits draw 9.9 mA (2.42 kΩ)
H3 / S3 (for 48 V dc applications):
First 21 circuits draw 2.5 mA
Last three circuits draw 10 mA
Input filter Hardware filter, 4 ms
Power consumption 20.6 W on the terminal board
Fault detection Loss of contact input excitation voltage
Unplugged cable
Physical
Size 33.02 cm high x 10.16 cm wide (13.0 in. x 4.0 in)

Diagnostics
Diagnostic tests to components on the terminal boards are as follows:
• The excitation voltage is monitored. If the excitation drops to below 40% of the
nominal voltage, a diagnostic alarm is set and latched by the I/O pack/board.
• As a test, all inputs associated with this terminal board are forced to the
open contact (fail safe) state. Any input that fails the diagnostic test is
forced to the failsafe state and a fault is created.
• If the input from this board does not match the TMR voted value
from all three boards, a fault is created.
• Each terminal board connector has its own ID device that is interrogated by the
I/O pack/board. The connector ID is coded into a read-only chip containing
the board serial number, board type, revision number, and the JR1/JS1/JT1
connector location. When the chip is read by the controller and a mismatch
Configuration

TICI Contact Input with Point Isolation
The Contact Input with Point Isolation (TICI) terminal board provides
24 point isolated voltage detection circuits to sense a range of voltages
across relay contacts, fuses, and switches.


Compatibility
The VCRC J3 and J4 front In the Mark VI control system, the TICI is controlled by the VCCC board and
connectors do not support TICI. supports simplex and TMR applications. Cables with molded plugs connect
TICI to the VME rack where the I/O boards are mounted.
In the Mark VIe control system, the TICI works with the PDIA I/O pack and
supports simplex, dual, and TMR applications. One, two, or three PDIAs plug
into the TICI to support a variety of system configurations. The I/O packs plug
into TICI and attach to side-mounting brackets. One or two Ethernet cables plug
into the pack. Firmware may need to be downloaded.

Installation
Wiring
Connect the wires for the 24 isolated digital inputs directly to two I/O terminal
blocks on the terminal board. These blocks are held down with two screws and
can be unplugged from the board for maintenance. Each block has 24 terminals
Cabling Connections
In a simplex system, connect TICI to the I/O processor using connector JR1. In
a TMR system, connect TICI to the I/O processors using connectors JR1, JS1,
and JT1. Cables or I/O packs are plugged in depending on the type of Mark VI
or Mark VIe control system, and the level of redundancy.
Isolated Contact Input Terminal Board TICI

JT1
x
Input 4 (Return)
x 8
Input 5 (Return)
x 10
Input 7 (Return) x 14 J - Port Connections:
x 18 JS1 Plug in PDIA I/O Pack(s)
Input 10(Return) x 20 for Mark VIe system
Input 11(Return) x 22
Input 12(Return) x 23 Input 12 (Positive) or
x 24
x
Cables to VCCC boards
for Mark VI;
x
x 25 Input 13 (Positive) The number and location
x 27 Input 14 (Positive) depends on the level of
x 29 Input 15 (Positive) redundancy required.
Input 16 (Return) x 32 JR1
Input 20 (Return)
x 40
x
Terminal Blocks can be unplugged Up to two #12 AWG wires per

from terminal board for maintenance point with 300 volt insulation
TICI Terminal Board Wiring and Cabling

Operation
The TICI is similar to TBCI, except for the following items:
• No contact excitation is provided on the terminal board.

• Each input is electrically isolated from all others and from the active electronics.
There are two groups of the TICI with different nominal voltage thresholds.
TICIH1 has the following input voltage ranges:
• 70-145 V dc, nominal 125 V dc, with a detection of 39 to 61 V dc

• 200-250 V dc, nominal 250 V dc, with a detection of 39 to 61 V dc
• 90-132 V rms, nominal 115 V rms, 47-63 Hz, with a detection of 35 to 76 V ac
• 190-264 V rms, nominal 230 V rms, 47-63 Hz, with a detection of 35 to 76 V ac
TICIH2 has the following input voltage range:
• 16-32 V dc, nominal 24 V dc, with a detection threshold of 9.5 to 15 V dc
TICI provides input hardware filtering with time delays of 15 ms, nominal:
• For dc applications the time delay is 15 ±8 ms

• For ac applications the time delay is 15 ±13 ms

In addition to hardware filters, the contact input state is software-filtered, using
configurable time delays selected from 0, 10, 20, 50, and 100 ms. For ac
inputs, a filter of at least 10 ms is recommended.
TICI Isolated Contact Inputs
External JR1 Simplex system

Voltage optical
P28 VDC P28V JR1 connects to
isolator
VCCC/VCRC or
ID connects to PDIA
Posxx pack for Mark VIe
Retxx system
PCOM
S S PCOM
JS1
P28V
Circuit #2
ID
--
--
For TMR Systems
PCOM
total JS1 and JT1 cable
of to I/O processors
24 VCCC/VCRC for
ccts Mark VI systems
-- JT1 or
P28V connects to PDIA
--
I/O Packs for Mark
ID
VIe systems.
PCOM
TICI Circuits for Sensing Voltage across typical device
The following restrictions should be noted regarding creepage and

clearance on the 230 V rms application:
• For NEMA requirements: 230 V single-phase

• For CE Certification: 230 V single or 3-phase

Specifications
Item Specification
Number of channels 24 input channels for isolated voltage sensing
Input voltage TICIH2:
16-32 V dc, nominal 24 V dc, with a detection threshold of 9.5 to 15 V dc
TICIH1:
70 -145 V dc, nominal 125 V dc, with a detection threshold of 39 to 61 V dc
200 -250 V dc, nominal 250 V dc, with a detection threshold of 39 to 61 V dc
90 -132 V rms, nominal 115 V rms, 47-63 Hz, with a detection threshold of 35 to 76 V ac
190-264 V rms, nominal 230 V rms, 47-63 Hz, with a detection threshold of 35 to 76 V ac
Fault detection in I/O board Non-responding contact input in test mode
Unplugged cable or failed ID chip
Physical
Temperature Operating -30 to +65ºC (-22 to +149 ºF)
Diagnostics
• The excitation voltage is monitored. If the excitation drops to below 40% of the
nominal voltage, a diagnostic alarm is set and latched by the I/O pack/board.
open contact (fail safe) state. Any input that fails the diagnostic test is
forced to the failsafe state and a fault is created.
• If the input from this board does not match the TMR voted value
from all three boards, a fault is created.
connector location. When the chip is read by the controller and a mismatch
Configuration

STCI Simplex Contact Input
The Simplex Contact Input (STCI) terminal board is a compact contact input terminal
board designed for DIN-rail or flat mounting. The STCI board accepts 24 contact inputs
that are supplied with a nominal 24, 48, and 125 V dc excitation from an external source.
The contact inputs have noise suppression to protect against surge and high-frequency
noise. The STCI works with Mark VIe and Mark VIeS systems.
Control System STCI Functionality

Mark VIe control PAIC I/O pack works with the STCI. The I/O pack plugs into
the D-type connector and communicates with the controller
over Ethernet. Only simplex systems are supported.
Mark VIeS control Board revisions STCIS1A, STCIS2A, STCIS4A, and STAIS6A
are safety certified.
Board Revision Mark VIe Mark VIeS Comments

IS220PDIA IS200YDIA
STCIH1A Yes, all versions No 24 V dc nominal, fixed terminals
STCIH2A Yes, all versions No 24 V dc nominal, plug in terminals
STCIS1A Yes, all versions Yes, all versions 24 V dc nominal, fixed terminals,
safety certified
STCIS2A Yes, all versions Yes, all versions 24 V dc nominal, plug in terminals,
safety certified
STCIS4A Yes, all versions Yes, all versions 48 V dc nominal, plug in terminals,
safety certified
STCIS6A Yes, all versions Yes, all versions 125 V dc nominal, plug in
terminals, safety certified

Installation
E1 and E2 are chassis The STCI plus a plastic insulator mounts on a sheet metal carrier that then mounts on a
grounding screws for SCOM. DIN rail. Optionally the STCI plus insulator mounts on a sheet metal assembly that then
bolts in a cabinet. The contact inputs are wired directly to the terminal block, typically
using #18 AWG wires. Shields should be terminated on a separate bracket.
Two types of Euro-block terminal blocks are available:
• STCIH1 has a permanently mounted terminal block with 52 terminals.

• STCIH2, STCIH4, and STCIH6 has a right-angle header accepting a range of
commercially available pluggable terminal blocks, with a total of 52 terminals.
E1 SCOM J1
Screw Connections
Input 1 (Signal) 2 1 Input 1 (Positive) Contact
1
3 Input 2 (Positive) excitation input
Input 2 (Signal) 4
5 Input 3 (Positive)
Input 3 (Signal) 6
Input 4 (Signal) 7 Input 4 (Positive) 3
8 DC-37 pin
Input 5 (Signal) 10 connector with
Input 6 (Signal) 12 JA1 latching fasteners
Input 7 (Signal) 14
Input 8 (Signal) 15 Input 8 (Positive)
16
Input 9 (Signal) 18
20 JA1
22 Plug in Pack
24
Input 13 (Signal) 26 25 Input 13 (Positive)
28
30
32
34
36
38
Input 20 (Signal) 40
42
48
49 Excitation (Positive)
Excitation(Positive) 50
51 Excitation (Negative)
Excitation(Negative) 52
TB1
E2 SCOM (Chassis Ground)
Euro-Block type
terminal block
Plastic insulator
DIN-rail mounting
and metal carrier
Wiring to STCI Terminal Board

Operation
The function and on-board signal conditioning are the same as those on TBCI, they
are scaled for 24, 48, and 125 V dc excitation. The input excitation range is 16 to
32 V dc, 32 to 64 V dc, and 100 to 145 V dc respectively. The threshold voltage is
50% of the excitation voltage. The contact sensing circuits are displayed in the figure.
Contact input currents are resistance limited to 2.5 mA on the first 21 circuits, and
10 mA on circuits 22 through 24. The 24 V dc supply is current limited to 0.5 A
using polymer positive temperature coefficient fuses that can be reset.
Filters reduce high-frequency noise and suppress surge on each input near the point of signal
entry. The discrete input voltage signals go to the I/O processor which passes them through
optical isolators, converts them to digital signals, and transfers them to the controller.
JE1
1
3 STCI Terminal Board
49 (+)
I/O Processor
From 24 V dc 50 (+)
power source Current limit
51 (-) 0.5 A Polyfuse
for 24 V and
52 (-) 48 V only Total of 24 circuits Gate
JA1 P5
Noise Gate
Suppr-
2.4 mA (+) 1 ession Gate
N
(-) 2
S Ref.
ID Gate
Field Contact
(+) 3
N ICOM Gate
(-) 4 S Optical Isolation
Field Contact Gate
(+)
N
(-) S
Field Contact .
.
. .
.
. . 24 Contact Inputs
.
TB1
. .
.
. .
.
. .
(+) 47
N
(-) 48 S
BCOM
24 Field
Contacts SCOM
STCI Contact Input Circuits

Specifications
Item Specification
Excitation voltage H1 / S1: Nominal 24 V dc, floating, ranging from 18 to 32 V dc (Fixed TB)
H2 / S2: Nominal 24 V dc, floating, ranging from 18.5 to 32 V dc (Pluggable TB)
H4 / S4: Nominal 48 V dc, floating, ranging from 32 to 64 V dc (Pluggable TB)
H6 / S6: Nominal 125 V dc, floating, ranging from 100 to 145 V dc (Pluggable TB)
Input current H1 / S1: For 24 V dc applications:
First 21 circuits each draw 2.5 mA (50 kΩ)
Last three circuits each draw 10 mA (12.5 kΩ)
H2 / S2: For 24 V dc applications:
Last three circuits draw 10.4 mA
Fault detection in I/O board Loss of contact input excitation voltage
Ac voltage rejection 12 V rms at 24 V dc excitation. (H1 and H2)
24 V rms at 48 V dc excitation. (H4)
60 V rms at 125 V dc excitation. (H6)
Physical
Temperature -30 to + 65ºC (-22 to 149 ºF)
Diagnostics
The I/O processor monitors the following functions on STCI:
• The contact excitation voltage is monitored. If the excitation drops to below 40%
of the nominal voltage, a diagnostic alarm (fault) is set and latched.
open contact state. Any input that fails the diagnostic test is forced to
the failsafe state (open) and a fault is created.
• The terminal board connector has an ID device that is interrogated by the
I/O processor. The connector ID is coded into a read-only chip containing
the board serial number, board type, and revision number. If a mismatch is
Configuration

PDII Isolated Discrete Input Module
Isolated Discrete Input (PDII)

The Isolated Discrete Input (PDII) pack provides the electrical interface between one or
DISCRETE
SERIAL IN
COMM
two I/O Ethernet networks and a point/group isolated discrete input terminal board. The
PWR
1 pack contains a processor board common to all Mark* VIe distributed I/O packs and an
2 ATTN
3 acquisition board specific to the isolated discrete input function.
4
LINK
5 ENET1 The pack accepts up to 16 isolated contact inputs that can be point isolated, group
6 TxRx
isolated, or a mix based on the terminal and optional board configurations. Each
7
8 channel can accept different voltage levels as follows: 24 V dc/ 48 V dc/ 125 V dc/
250 V dc/ 115 V ac rms / 230 V ac rms.
LINK
9 ENET2
10 TxRx
11 If the pack is used with terminal board SDII and the optional board WDIIH1, all 16
12 channels can be system wetted with 24 V dc, 115 V ac rms, or 230 V ac rms. When
IR PORT
using WDIIH1, each of the 16 channels can be individually set and configured as point
13 isolated and each channel can accept a different voltage level as needed. A mix of point
14 isolation and group isolation is possible in this configuration.
15
16
IS220PDIIH1A
IS220PSCAH1A If the pack is used with terminal board SDII and the optional board WDIIH2, all 16
channels can be system wetted with 48 V dc. When using WDIIH2, each of the 16
channels can be individually set and configured as point isolated and each channel can
accept a different voltage level as needed. A mix of point isolation and group isolation
is possible in this configuration.
If the pack is used with terminal board SDII and the optional board WDIIH3, all 16
channels can only be system wetted with 125 V dc. With WDIIH3, there is no option
provided to configure channels as point isolated.
System input to the pack is through dual RJ45 Ethernet connectors and a three-pin
power input. Discrete signal input is through a DC-37 pin connector that connects
directly with the associated terminal board connector. Network, pack, and contact input
status visual indicators are provided through pack front LEDs.
GEH-6721L PDII Isolated Discrete Input Module System Guide 10-1

PDIIH1A
BDIIH1A Discrete input pack
Discrete input pack Processor board
SDIIH1A Single or dual

Discrete input Ethernet cables
Terminal Board
ENET1
Contact Inputs
( 16)
ENET2
External28 V dc
power supply
Point Isolated Representation –SDII+PDII
Wetting Voltage input PDIIH1A

Discrete input board Processor board
SDIIH1A
Single or dual
Discrete input
Ethernet cables
Terminal Board
Contact Inputs JE1 JE2 ENET1
(16)
ENET2
External 28 V DC
WDIIH 1/2/3A Power supply
Wetting
Voltage board
System Wetted Representation – SDII +WDII+PDII

Compatibility
PDIIH1A is compatible with discrete contact input terminal board SDII. The
following table gives details of the compatibility:
Terminal Board SDIIH1A

Control mode Simplex-yes Dual - No TMR-No
• Simplex uses one I/O pack with one or two network connections
• Dual uses two I/O packs with one or two network connections
• TMR uses three I/O packs with one network connection on each pack
Installation
¾ To install the PDII pack
2. Directly plug one PDII I/O pack for simplex into the terminal board connectors. The
terminal board can be with or without optional board as per the user requirement.
3. Mechanically secure the pack using the threaded studs adjacent to the Ethernet
ports. The studs slide into a mounting bracket specific to the terminal board
type. The bracket location should be adjusted such that the right-angle force
Note The PDII mounts directly on a Mark VIe terminal board. Simplex terminal
boards have a single DC-37 pin connector that receives the PDII.
4. Plug in one or two Ethernet cables depending on the system configuration. The
pack operates over either port. If dual connections are used, the standard practice
is to connect ENET1 to the network associated with the R controller.
6. Use the ToolboxST* application to configure the I/O pack as necessary. While
configuring please see the diagram Operation and Different configurations,
connection styles using SDII/ SDII+WDII to make the required configuration.

Wizard again.

Operation
Processor




Status LEDs
Processor LEDs

present
LED Status

ATTN
or module.
ATTN
every 4 sec

Application Hardware
The PDII I/O pack has an internal application specific circuit board that contains
the hardware needed for the contact input function. The application board
connects between the processor and the contact input terminal board. The
application board provides the following functions:
• Provide electronic identification of the application board to the processor and

support pass-through of the terminal board identification
• Receive 16 contact input signals from the terminal board and pass
them to the processor board
• Provide 16 bi-color indicator LEDs for contact state and health indication
ID Line
The processor board and acquisition board within the I/O pack contain electronic ID parts
that are read during power initialization. A similar part located with each terminal board
and optional board. DC-37 pin connector allows the processor to confirm correct matching
of I/O pack to terminal board and report board revision status to the system level control.
Power Management
Connectors
• A DC-37 pin connector on the underside of the I/O pack connects directly to the
discrete input terminal board. The connector contains the 16 input signals, ID
signal and Wetting voltage signal (From WDII when connected).

Specifications
Item Specification
Voltage range for point isolated inputs 14 to 32 V dc, nominal 24 V dc;
19 to 64 V dc, nominal 48 V dc;
90 to 143 V ac rms, nominal 115 ac V rms, 50 Hz ±3 Hz;
90 to 265 V ac rms, nominal 230 ac V rms, 50 Hz ±3 Hz;
If the wetting voltage goes out of the ranges listed above (Configured), an
invalid voltage alarm occurs. Contact status is not reported if there is invalid
voltage. The wetting voltage is monitored only when it is present at the TB
points.
Accuracy for voltage monitoring for Invalid ±6%
voltage alarm
Channel Mix When the terminal board is used in point isolated configuration, there can
be a mix of ranges. Every channel can have a different input voltage within
any of the ranges mentioned above.
Frame rate System dependent scan rate for control purposes (10 ms, 20 ms, 40 ms, 80
ms, 160 ms, 320 ms)
Sequence of Event (SOE)—If enabled in SOE accuracy for contacts with dc voltage — ±1 ms
configuration SOE accuracy for contacts with ac voltage — ±3 ms
Fault detection Loss of contact input excitation voltage (Loss of system wetting voltage only
when WDII is connected)
Single resistor fault detection option as WDIIH1, WDIIH2, WDIIH3 —
described with terminal board Fuse Blown/ open field wire
Dual resistor fault detection as described WDIIH2, WIIH3 —

with terminal board. Fuse Blown/ open field wire
Line to line short in the field
Contact Status indication Bi-color LEDs
Green – Contact status true
Off – Contact status false or unused
RED – Line fault or invalid voltage

Diagnostics

• A check of the electronic ID information from the terminal board, optional
board, acquisition board, and processor board to confirm that the hardware
set matches, followed by a check that the application code loaded from
flash memory is correct for the hardware set
The pack performs the following diagnostic tests for contact excitation
voltage and field line monitoring:
• Monitors that contact input excitation voltage is in the valid range

• Monitors Fuse Blown/open field wire. Adds a resistor parallel to the contact
in the field and configures the channel accordingly.
• Monitors Fuse Blown/open field wire and Line-to-line short in the field. Adds
a resistor parallel to the contact and adds one resistor in series with the contact
in the field and configures the channel accordingly.

Configuration

PDII Module Configuration
Board Wetting Voltage Set the board level wetting voltage. This Dc 24 V, ac 115 V, ac 230 V
voltage is connected at JE1 or JE2 of WDII
board. This configuration is applicable only for
WDIIH1. This is the default configuration for
WDIIH2 and WDIIH3.
PDII Contact Inputs Terminal board and optional boards connected SDIIH1
to PDII SDIIH1+WDIIH1
SDIIH1+WDIIH2
SDIIH1+WDIIH3
Contact Input To enable contact input Used, Unused
Sequence of Events Record contact transitions in sequence of Enable, Disable
events
Line Monitoring/Fuse Diagnostics Provide the fault diagnostics in case of a line SDIIH1: No options selectable.
fault. SDII+WDIIH1: None,
These line faults are: Wire open or fuse blown ParallelResistor
and Line to line short. SDII+WDIIH2: None,
ParallelResistor, SeriesParallelRes
SDII+WDIIH3: None,
ParallelResistor, SeriesParallelRes
Wetting Voltage The point level wetting voltage SDIIH1: dc 24 V, dc 48 V, dc 125 V,
dc 250 V, ac 115 V, ac 230 V
SDIIH1+WDIIH1: SystemWetted, dc
24 V, dc 48 V, dc 125 V, dc 250 V, ac
115 V, ac 230 V
SDIIH1+WDIIH2: SystemWetted, dc
24 V, dc 48 V, dc 125 V, dc 250 V, ac
115 V, ac 230 V
SDIIH1+WDIIH3: WDII H3 cannot
have point isolated channels – No
option selectable. All channels are
only system wetted
Signal Filter The debounce filter to filter out very rapid Unfiltered, 10
transitions
ms, 20 ms, 50 ms, 100 ms
Note: Signal
SOE When signal filter is selected If SOE is enabled and the filter is selected then
the SOE accuracy changes to the filter time
selected

Signal Space Inputs
There are three tabs in the ToolboxST application to indicate contact health. These
tabs display the real time health of the contact for the Signal Space Input to the Mark
VIe controller from the PDII I/O pack. These signal space inputs are:
Wetting Voltage Health This tab is useful only if the contact is configured for
isolated/external wetting. For contacts configured for System wetting, this input always
displays True. For all unused contacts, this input always displays True.
• True: If the point level wetting voltage is within the tolerance limits for the
configured wetting voltage or contact is configured Unused.
• False: If the point level wetting voltage is not within the tolerance
limits for the configured wetting voltage.
Line Faults
• True: If the any of the line fault occurs on the channel.

• False: No line fault is present on the channel or contact is configured Unused
or line fault monitoring is configured for None.
Fuses
• True: If the fuse for the contact is intact or contact is configured Unused
or line fault monitoring is configured for None.
• False: If the fuse for the contact is blown.

SDII Simplex Contact Input with Point Isolation
SDII has the same physical size, The Contact Input with Point Isolation (SDII) terminal board provides 16 point isolated
customer terminal locations, voltage detection circuits to sense a range of voltages across relay contacts, fuses, and
and I/O pack mounting as other switches and other contacts. IS200SDIIH1 has pluggable Euro-style box terminals
S-type terminal boards. and a connector that accepts different option boards. Three terminals are provided
for each contact input channel. Each channel can accept different voltage levels as
follows: 24 V dc/ 48 V dc/ 125 V dc/ 250 V dc/ 115 V ac rms / 230 V ac rms. If PDII
is used with SDII only, then all 16 channels are point-isolated channels.
There are three groups of WDII option boards that connect to SDIIH1A. If the option
board WDII is connected, the point isolated channels become group isolated channels
where the system wetting voltage is provided through WDII. WDII boards have an
isolated voltage detector circuit similar to SDII to monitor the wetting voltage.
Using option board WDIIH1, all 16 channels can be system wetted with 24 V dc, 115 V ac
rms, or 230 V ac rms. When using WDIIH1 each of the 16 channels can be individually
set and configured as point isolated and each channel can accept a different voltage level
as needed. A mix of point isolation and group isolation is possible in this configuration.
Using option board WDIIH2, all 16 channels can be system wetted with 48 V dc.
When using WDIIH2, each of the 16 channels can be individually set and configured
as point isolated and each channel can accept a different voltage level as needed. A
mix of point isolation and group isolation is possible in this configuration.
Using option board WDIIH3, all 16 channels can only be system wetted with 125 V dc.
With WDIIH3, there is no option provided to configure channels as point isolated.

CONTACT
Point Isolated
No line fault monitoring
Standalone WDII with fuse removed and

SDII configured for ‘Isolated’ from Toolbox
Series with SDII Parallel with SDII Series with SDII Parallel with SDII
detector circuit detector circuit detector circuit detector circuit
USER WETTING V+ USER WETTING V+

SDII SDII SDII SDII
Point Isolated FUSE FUSE
Point Isolated Point Isolated Point Isolated Removed
Removed
1 1 Detector 1 1
Detector Detector Detector
3 3 3 3
5 5 5 5
L L
O O
A WDIIH1/2 A WDIIH1/2
D D
Repeat Repeat Repeat Repeat
USER GND
USER GND
USER GND USER GND
GROUP ISOLATED /
SYSTEM WETTED
WDIIH1 WDIIH2 WDIIH3
A B
24VDC 115VAC 230VAC
NONE/ PARALLEL R NONE / PARALLEL R NONE / PARALLEL R
NONE PARALLEL R
SDII SDII
System Wetted System Wetted
“NONE” configuration means
1 Detector 1 Detector there is no resistor connected in
3 3
5 5 series or parallel with the
contact and in this case, field
WDIIH1 WDIIH1 line monitoring is not supported.
Repeat Repeat
No resistor connected in series Line Fault Monitoring for

or in parallel with the contact Wire open /fuse blown
No Line fault monitoring
Voltage ranges same as ParallelR
Operation and Configuration Options Using SDII/ SDII+WDII

A
WDIIH2
48 V DC
NONE ParallelR SeriesparallelR
SDII SDII SDII

System Wetted System Wetted System Wetted
1 1 Detector
1 Detector Detector
3 3
3
5 5
5

Repeat Repeat Repeat
No resistor connected in series Line Fault Monitoring for Line Fault Monitoring for
or in parallel with the contact Wire Open/Fuse blown 1.Wire open/ Fuse blown
No Line fault monitoring 2.Wire shorted
“NONE” configuration means

there is no resistor connected in
series or parallel with the
contact and in this case, field B
line monitoring is not supported.
WDIIH3
125 V DC
NONE ParallelR SeriesparallelR
SDII SDII
SDII
System Wetted System Wetted
System Wetted
1 1 Detector
1 Detector Detector
3 3
3 5
5 5

Repeat Repeat Repeat
No resistor connected in series Line Fault Monitoring for Line Fault Monitoring for
or in parallel with the contact Wire Open/Fuse blown 1.Wire open/ Fuse blown
No Line fault monitoring 2.Wire shorted
Note In all the drawings in this document, the word repeat means the same blocks are
repeated for all 16 channels with different screw numbers

Installation
E1 and E2 are chassis The SDII and plastic insulator are attached to a sheet metal carrier that mounts
grounding screws for SCOM. on to the cabinet using screws. An option board if used, plugs onto SDII and
is held in place with the help of four stand-offs and the fastener hardware. The
contact inputs are wired directly to the terminal block, typically using #18 AWG
wires. Shields should be terminated on a separate bracket.
Wiring
Connect the wires for the 16 isolated digital inputs directly to 48 pin Euro-style pluggable
terminal blocks on the terminal board, with each terminal accepting up to #18 AWG
wires. Each block has three screws per every one channel of contact input and each block
can be unplugged from the board for maintenance. A shield terminal strip attached
The connections are configured as follows (see diagrams and table):

Series connection SDII-A Series connection SDII- B
SDII SDII
Point Isolated Point Isolated
1 Detector 1 Detector
3 3
5 5
Repeat Repeat
USER GND USER GND
Parallel connection SDII- C Series connection SDII-AA

SDII
Point Isolated SDII
FUSE
Point Isolated Removed
1 Detector
3 1 Detector
5 3
L 5
O
A
D WDIIH1/2
Repeat
USER GND Repeat
USER GND USER GND
Series connection SDII- BB Parallel connection SDII- CC

SDII
SDII Point Isolated FUSE
FUSE Removed
Point Isolated Removed
1
Detector
1 Detector 3
3 5
5 L
O
A WDIIH1/2
WDIIH1/2 D
Repeat
Repeat
USER GND USER GND
Series connection SDII- DD
SDII
System Wetted
1 Detector
3
5
WDIIH1
/2/3
Repeat
Note Parallel connection - When the contact is off there will be leakage of 2 to 7 mA
based on the amplitude of wetting voltage due to the parallel detector circuit. So for the
loads which are sensitive to the current of 7 mA this configuration shall not be used. For
example, if the load is a LED type indicator it will glow due to the leakage of detector
circuit even if the contact is off. For such loads, this configuration should not be used

SDII TB Point Isolated —Only SDII Point Isolated —SDII+WDIIH1/2 System
definitions Wetted
Series Series Parallel Series Series Parallel WDIIH1/2/3
contact contact Contact contact contact Contact
Channel TB SDII –A SDII–B SDII–C SDII –AA SDII–BB SDII–CC SDII–DD
screws
1 1 Contact User V+ve Contact Contact User V+ve Contact NC
connection connection connection connection
2 1 2 1
3 User GND Contact Contact User GND Contact Contact Contact
connection connection connection connection connection
1 2 1 2 1
5 NC NC NC NC NC NC Contact
connection
2
2 1 2 1
1 2 1 2 1
connection
2
2 1 2 1
1 2 1 2 1
connection
2
2 1 2 1
1 2 1 2 1
connection
2

definitions Wetted
screws
2 1 2 1
1 2 1 2 1
connection
2
2 1 2 1
1 2 1 2 1
connection
2
2 1 2 1
1 2 1 2 1
connection
2

2 1 2 1
1 2 1 2 1
connection
2

definitions Wetted
screws
2 1 2 1
1 2 1 2 1
connection
2
2 1 2 1
1 2 1 2 1
NC NC NC NC NC NC Contact
30 connection
2
2 1 2 1
1 2 1 2 1
connection
2
2 1 2 1
1 2 1 2 1
connection
2

definitions Wetted
screws
2 1 2 1
1 2 1 2 1
connection
2
2 1 2 1
1 2 1 2 1
connection
2
2 1 2 1
1 2 1 2 1
connection
2
2 1 2 1

1 2 1 2 1
connection
2

Cabling Connections
The PDII I/O pack is plugged into the SDII terminal board and attached
to the side mounting brackets. One or two Ethernet cables plug into the
pack. Firmware may need to be downloaded.
Optional WDII Board connection
E1 SCOM
Screw Connections
Input 2 2 1
B2
3 Input 1
Input 2 4
5 Z2 D2
Input 2 6
Input 4 7
8
9 Input 3
Input 4 10
11 Plug in PDII
Input 4 12
13
Input 6 14 Pack
15 Input 5
Input 6 16
17
Input 6 18
Input 8 19
20
Input 8 21 Input 7
22 D 37 Pin
Input 8 23
24
Input 10 26 25 JW 1 JA1
Connector
Input 10 27 Input 9 with Latching
28
29 Fastner
Input 10 30
31
Input 12 32
Input 12 33 Input 11
34
Input 12 35
36
Input 14 37
38
39 Input13
Input 14 40
Input 14 41
42
43 Z32 D32
Input 16 44
45 Input 15
Input 16 46
Input 16 47 B32
48 Connector to
TB1 WDII
E2 SCOM (Chassis Ground)
Euro Block Type
Terminal Block
Plastic Insulator
and metal Carrier
SDII Terminal Board Wiring and Cabling

Wiring
The PDII module features 48 pluggable Euro-style box terminals. The Euro-style box
terminals on SDII accept conductors with the following characteristics:

Conductor cross section solid 0.2 mm² 2.5 mm²
Conductor cross section stranded 0.2 mm² 2.5 mm²
Conductor cross section stranded, with ferrule 0.25 mm² 2.5 mm²
without plastic sleeve
Conductor cross section stranded, with ferrule with 0.25 mm² 2.5 mm²
plastic sleeve
Two conductors with same cross section, solid 0.2 mm² 1 mm²
Two conductors with same cross section, stranded 0.2 mm² 1.5 mm²
Two conductors with same cross section, stranded, 0.25 mm² 1 mm²
without plastic sleeve
Two conductors with same cross section, stranded, 0.5 mm² 1.5 mm²
TWIN ferrules with plastic sleeve
Fuses on WDII
Use the exact part as specified WDIIH1 and WDIIH2 have one removable fuse per channel in the supply
when replacement is needed line as per the following description:
Littlefuse – 372 series, 200 mA, 250 V radial fuse (Part number
3720200051 or 37202000511)
GE part number for fuse –342A4908AFP1
WDIIH3 has non-removable thermal fuse (PTC) in the supply line. The
fuse numbers are in the following table:
Channel SDII-TB Screws WDIIH1 Fuses-Removable WDIIH2 Fuses-Removable WDIIH3 Thermal fuses
(PTC)- Not-Removable
1 1 FU1 FU1 TR1
3
5
2 2 FU2 FU2 TR2
4
6
3 7 FU3 FU3 TR3
9
11
4 8 FU4 FU4 TR4
10
12

Channel SDII-TB Screws WDIIH1 Fuses-Removable WDIIH2 Fuses-Removable WDIIH3 Thermal fuses
(PTC)- Not-Removable
5 13 FU5 FU5 TR5
15
17
6 14 FU6 FU6 TR6
16
18
7 19 FU7 FU7 TR7
21
23
8 20 FU8 FU8 TR8
22
24
9 25 FU9 FU9 TR9
27
29
10 26 FU10 FU10 TR10
28
30
11 31 FU11 FU11 TR11
33
35
12 32 FU12 FU12 TR12
34
36
13 37 FU13 FU13 TR13
39
41
14 38 FU14 FU14 TR14
40
42
15 43 FU15 FU15 TR15
45
47
16 44 FU16 FU16 TR16
46
48

Operation
Point isolated Input Signals

The SDII provides a sensing circuit, which converts the voltage present at the TB
input to an isolated digital signal. Using the isolated signal, the firmware calculates
the voltage present at the TB input. Based on the presence and absence of voltage
at the TB input, it declares the status of contact as on or off.
Each input is isolated from each other. If SDII is used without an optional board,
all the inputs are point isolated as well as system isolated.
1
VOLTAGE DUE TO Contact processing
CONTACT ON / OFF Sensing Isolator Block
3 Circuit
BDII &
Processing
SDII board
TB
If SDII is used with optional board WDIIH1, channels can be system wetted with
24 V dc / 115 V 50/60 Hz ac rms / 230 V 50/60 Hz ac rms based on the TB points
used for field wire terminations and the channel configuration setting through the
ToolboxST application. The frequency range for AC 50 Hz and 60 Hz is ±3 Hz.
System wetting requires that the respective channel fuse be present on WDII. Removal
of the fuse allows use of the input as a point isolated signal path.
If SDII is used with optional board WDIIH2, all or some channels can be system
wetted with 48 V dc based on the TB points used for field wire terminations
and the channel configuration setting through toolbox.
If SDII is used with optional board WDIIH3, all channels are system wetted with 125 V dc.

SDII-PDII - All point isolated contact input channels
FIELD WETTING V+
CONTACT
CONTACT SENSING
1
CIRCUIT/ CURRENT
LIMIT
3 CHANNEL 1
TB
FIELD GND SDII
Contact in series with detector circuit, current limiting circuit
In the figure above, the contact is connected in series with the detector circuit. An
external current limit circuit is not necessary. The detector circuit offers current limit
of 2 mA - 7 mA based on the input wetting voltage provided by the user.
When voltage is present at TB input, the contact input setting for the contact
is on. When the contact is on, the system interprets it as true as there is
voltage present at TB input when contact is on.

FIELD WETTING V+
CONTACT CONTACT SENSING

1
CIRCUIT/ CURRENT
LIMIT
3 CHANNEL 1
L
LOADS LIKE MOTOR O
A
D
TB
FIELD GND SDII
Contact in parallel with detector circuit
In the figure above, the contact is connected in parallel with the detector circuit. This can
be used for sensing contacts in series with loads like an electric motor. An external current
limit circuit is required as the SDII does not provide any current limit for the current
flowing through contact. The user provides the wetting voltage. This configuration avoids
the need of auxiliary sensing contacts for electric motor-like loads provided the motor
voltage is within the SDII voltage sensing limit of 264 V dc or 265 V ac rms.
When the contact is off there will be leakage of 2 to 7 mA based on the amplitude of
wetting voltage due to the parallel detector circuit. So for the loads which are sensitive
to the current of 7 mA this configuration shall not be used. For example, if the load
is a LED type indicator it will glow due to the leakage of detector circuit even if the
contact is off. For such loads, this configuration should not be used.
When voltage is present at TB input, the contact input setting for the contact is on. When the
contact is on, there is no voltage at TB input and the system interprets it as false. If the user
configures the contact as an invert, when the contact is on the system interprets it as true.

In both the configurations, the contact must be connected in the first two pins
provided for each contact. For channel 1 it is screw 1 and screw 3. A comparison
of these configurations is given in the following table.
Connections Diagram Configuration System reporting System reporting

For Signal Invert when contact closed when contact open
1 Contact in series (Default) Normal True False
with detector circuit
Contact in series Invert False True
2 Contact in parallel FIELD WETTING V+

(Default) False True
with detector circuit Normal
CONTACT CONTACT SENSING
1
Contact in parallel 3
CIRCUIT/ CURRENT
LIMIT
CHANNEL 1
Invert True False
with detector circuit LOADS LIKE MOTOR
L
O
A
D
TB
FIELD GND SDII
Voltage ranges for point isolated channels

Voltage ranges:
14 to 32 V dc, nominal 24 V dc
90 to 143 V ac rms, nominal 115 ac V rms, 47-63 Hz
90 to 265 V ac rms, nominal 230 ac V rms, 47-63 Hz
When the SDII is used in point isolated configuration, there can be a mix of
ranges. That means every channel can have one of different input voltage
within any of the ranges mentioned above.
For example, channel 1 can have a contact with a user wetting voltage of 24 V dc, channel
2 can have 115 V 60 Hz ac rms, and channel 3 contact can be wetted to 48 V dc by the user.
If the wetting voltage goes out of the specified ranges listed above (for each configured
voltage), an invalid voltage alarm occurs and the status LED indicator turns RED. Contact
status is not reported if there is invalid voltage. The wetting voltage is monitored only
when it is present at the TB points and only for the following conditions:
• The contact is on for a series contact

• The contact is off for a parallel contact
Accuracy for voltage monitoring for the invalid voltage alarm is ±6%

When the voltage is above or below these levels, an invalid wetting voltage alarm is
raised. On lower side, the alarm will be generated below the range. If the wetting voltage
goes below 10 V the alarm will be cleared and contact state reported will be False healthy
in default configuration. For invert configuration, it will be True healthy.
System wetted (Group isolated) Input Signals

The contact input channels can be provided with wetting voltage through a WDII option
board. Along with the system wetting, WDIIH boards offer field line fault monitoring
with addition of one or two resistors connected in the field near the contact. WDII boards
have an isolated voltage detector circuit similar to SDII to monitor the wetting voltage.
Wetting Voltage input PDIIH1A

Discrete input board Processor board
SDIIH1A
Single or dual
Discrete input
Ethernet cables
Terminal Board
Contact Inputs JE1 JE2 ENET1
(16)
ENET2
External 28 V DC
WDIIH 1/2/3A Power supply
Wetting
Voltage board
WDIIH1A is capable of providing 115 V/ 240 V ac rms, 50/60 Hz and 24 V dc wetting

voltage with individual fuses in each supply line. The wetting voltage is connected
through JE1 or JE2 parallel connectors. Pin 1 of JE1 should be connected to positive
and pin 3 should be connected to negative. PDII can be configured to detect open field
wiring or an open fuse on WDII with the addition of one resistor in parallel with the
contact being sensed. Reversal of polarity at JE1/ JE2 is not desired.
WDIIH2A is capable of providing 48 V dc wetting voltage with fuse in supply line. The
wetting voltage is connected through JE1 or JE2 parallel connectors. Pin 1 of JE1 should
be connected to positive and pin 3 should be connected to negative. Reversal of polarity at
JE1/ JE2 is not desired. PDII can be configured to detect open field wiring or an open fuse
on WDII with the addition of one resistor in parallel with the contact being sensed. PDII
can be configured to detect open fuse/field wiring and line-to-line short with the addition
of one resistor in parallel and one resistor in series with the contact being sensed.
WDIIH3A is capable of providing 125 V dc contact wetting voltage with thermal

fuse (PTC) in supply line. The wetting voltage is connected through JE1 or JE2
parallel connectors. Pin 1 of JE1 should be connected to positive and pin 3 should
be connected to negative. Reversal of polarity at JE1/ JE2 is not desired. PDII can
be configured to detect open field wiring or an open fuse on WDII with the addition
of one resistor in parallel with the contact being sensed. PDII can be configured to
detect open fuse/field wiring and line-to-line short with the addition of one resistor
in parallel and one resistor in series with the contact being sensed.

For system wetted input signals, the contact must be connected in last two screws provided
for each contact. For channel 1 it is screw 3 and screw 5. The SDII-WDII and the contact
connection in case of system wetted contact inputs is as shown in the following diagram:
JE1/JE2
SDII
System wetted
1
Detector
3
5
WDIIH1/2/3
Repeat...
System wetted and Point isolated mixed –Input Signals

When WDIIH1 or WDIIH2 featuring removable fuses are used, there can be a mix of
system wetted contact inputs and point isolated contact inputs. Each contact is provided
with three user terminals. For system-wetted channels, contact must be wired between
last two user terminal points for that circuit. For channel 1 they are screw 3 and screw
5. In this case the detector circuit is in series with the contact and acts as the current
limit. The contact can be connected as shown in the following figure.
JE1/JE2
SDII
System wetted
1
Detector
3
5
WDIIH1/2
Repeat...

Point isolated channels when WDII is used
To use any input as a point isolated input the fuse must be removed and the signal wired
to the first two input terminals for that signal. For example, channel 1 uses screw 1 and
screw 3. The pack must be configured to accept the input as a point isolated signal. Two
ways to connect the contact are point isolated series and point isolated parallel.
CUSTOMER WETTING V+
CONTACT
SDII
Fuse removed
Point Isolated
1
Detector
3
5
TB
CUSTOMER GND
WDIIH1/2
Repeat...
Point isolated series
CUSTOMER WETTING V+
CONTACT
SDII
Fuse removed
Point Isolated
1
Detector
3
5
LOAD
TB
CUSTOMER GND
WDIIH1/2
Repeat...
Point isolated parallel

When the contact is off there will be leakage of 2 to 7 mA based on the amplitude of
wetting voltage due to the parallel detector circuit. So for the loads which are sensitive
to the current of 7 mA this configuration shall not be used. For example, if the load
is a LED type indicator it will glow due to the leakage of detector circuit even if the
contact is off. For such loads, this configuration should not be used.
While connecting and configuring point-isolated contacts using WDII the

same care must be taken as the standalone SDII. A comparison for these
configurations is given in the following table.
Connections Diagram Configuration System reporting System reporting

For Signal Invert when contact when contact
closed open
1 Contact in series CUSTOMER WETTING V+
(Default) Normal True False
SDII
with detector circuit CONTACT
Point Isolated
Fuse removed
1
Detector
3
Contact in series 5 Invert False True
TB
CUSTOMER GND
WDIIH 1/2
Repeat....
2 Contact in parallel CUSTOMER WETTING V+ (Default) Normal False True

SDII
with detector circuit Point Isolated Fuse removed
CONTACT 1
3
Detector
Contact in parallel 5 Invert True False
L
O
with detector circuit A

D
TB
CUSTOMER GND
WDIIH1/2
Repeat….
When WDIIH1 or H2 is used some channels can be configured as system wetted by

keeping fuse intact and using last two TB points. The remaining channels can be
point isolated by removing the fuse and using first two TB points.
WDIIH3 can be configured as system wetted (Board level) as it deploys

thermal fuses (PTCs), which are not removable. WDIIH3 cannot support
the point isolated and mixed configurations.

Field Line Fault Monitoring
Field line fault monitoring depends on knowledge of the contact wetting voltage
provided by the sensing circuit on WDII. When SDIIH1 is used without a
WDII, field line fault monitoring is not provided.
Note Connecting resistors other than the specified value may lead to incorrect
detection of contact position or line fault.
When WDIIH1 is used with SDII there are two configurations possible.
None – No resistor is connected in series or in parallel with the contact; no

field line monitoring. Only Contact on/off detection
Parallel Resistor – User has to add a resistor parallel to the contact in

the field. When parallel resistor is used with Contact on/off and fuse
blown/ the open field wire can be detected.
The specifications of parallel resistor for WDIIH1, 24 V dc — 3.01 kΩ, 1%,

0. 5 W. Orderable GE part number 336A4940HR-100
The specifications of parallel resistor for WDIIH1, 115 V ac — 22.1 kΩ, 1%,
3 W. Orderable GE part number 336A4940HW-100
The specifications of parallel resistor for WDIIH1, 230 V ac — 43.2 kΩ, 1%,
5 W. Orderable GE part number 336A4940HX-100
The allowable wetting voltage ranges are the same for None and Parallel resistor
configuration. Refer to the Voltage Ranges for Parallel Resistor Configuration section
for the actual voltage ranges for Parallel resistor configuration.
When WDIIH2 is used along with SDII, there are three configurations possible.
None – No resistor needs to be connected in series or parallel with the contact.

No field line monitoring. Only Contact on/off detection
Parallel Resistor – User has to add a resistor in parallel with the contact in
the field. This adds open fuse or field wire detection.

1 W. Orderable GE part number 336A4940HT-100
Series Parallel Resistor – User has to add one resistor parallel to the contact and
one resistor in series with the contact in the field. This adds open fuse or field
wire detection and line-to-line field wire short detection.

1 W. Orderable GE part number 336A4940HT-100
The specifications of series resistor for WDIIH2, 48 V dc — 3.32 kΩ, 1%,

0. 5 W. Orderable GE part number 336A4940HS-100
The permissible wetting voltage applied to WDIIH2 is equal to the most restrictive
range for any wetted contact. If series-parallel resistors are used on any input
then the voltage range listed for series-parallel inputs defines the range for all
the channels of WDIIH2. If there are no signals using series-parallel resistors,
then the less restrictive wetting voltage range applies.

Examples:
When channels 1 to 16 in WDIIH2 are configured for None, then the voltage
range applicable is the voltage range for None.
When channels 1 to 8 in WDIIH2 are configured for None and 9 to 16 are configured
for Parallel Resistor then the voltage range applicable is the voltage range for None
as the voltage ranges for None and Parallel Resistor are same.
When channels 1 to 16 in WDIIH2 are configured for Series Parallel Resistor, then
the voltage range applicable is the voltage range for Series Parallel Resistor.
When channels 1 to 4 in WDIIH2 are configured for None, channels 5 to 14 are

configured for Parallel Resistor, channel 15 is configured for Series Parallel Resistor,
and channel 16 is configured as point isolated by removing the fuse then the voltage
range applicable for all the first 15 channels is the voltage range for Series Parallel
Resistor. The voltage range applicable for the 16th channel, which is configured as point
isolated by removing the fuse, is the voltage range for point isolated inputs.
When WDIIH3 is used along with SDII, the same options as WDIIH2 are available except
the point isolated input: None, Parallel Resistor, and Series Parallel Resistor.
For parallel resistor connections, the specifications of parallel resistor for WDIIH3, 125
V dc —18.2 kΩ, 1%, 2 W. Orderable GE part number 336A4940HV-100
For Series-Parallel connections, the specifications of parallel resistor for WDIIH3, 125
V dc —18.2 kΩ, 1%, 2 W and the specification for series resistor for WDIIH3, 125
V dc—10 kΩ, 1%, 2 W. Orderable GE part number 336A4940HU-100
For WDIIH1, WDIIH2 and WDIIH3 Parallel Resistor configuration, the

resistor is connected as follows.
SDII + OPTIONBOARD
A (Pin3 SDII
channel1) B
Contact
VDC Sense
C (Pin5 SDII D
channel1)

For WDIIH2 and WDIIH3 Series Parallel Resistor configuration, the
resistors are connected as follows.
SDII + OPTIONBOARD
A (Pin3 SDII
B
channel1)
Contact
VDC Sense
C (Pin5 SDII D
channel1)
Ground Fault (In Parallel Resistor configuration)

If the user has hard ground so that common ground is tied up with the chassis
or with earth, this is the same condition as contact true for the Parallel Resistor
configuration. Irrespective of contact condition, it is treated as closed in normal
configuration and is treated as false in Invert configuration. If the lower line to the
contact is shorted to the chassis, there is no effect and it works normally and keeps
detecting contact true/false and fuse blown/line open condition.
The JPDE diagnostic shows the line fault based on its configuration for fault detection
if the JP1 jumper on JPDE is inserted. The following conditions are necessary
for this to happen: there is no hard ground; the wetting voltage is taken from
JPDE; any line to the contact is shorted to chassis in the field.

Ground Fault (In Series Parallel Resistor configuration)
If the user has hard ground so that common ground is tied up with the chassis or
with earth, this is the same condition as contact true for the Series Parallel Resistor
configuration. Irrespective of contact condition, it is treated as closed in normal
configuration and is treated as false in Invert configuration. If the lower line to the
contact is shorted to chassis, there is no effect and it works normally and keeps
detecting contact true/false and fuse blown/line open condition.
The JPDE diagnostic shows the line fault based on its configuration for fault detection
if the JP1 jumper on JPDE is inserted. The following conditions are necessary
for this to happen: there is no hard ground; the wetting voltage is taken from
JPDE; any line to the contact is shorted to chassis in the field.
Voltage Ranges for Parallel Resistor Configuration

Voltage ranges:
• 18.5 to 32 V dc, nominal 24 V dc (WDIIH1) 32 to 64 V dc, nominal 48 V dc (WDIIH2)

• 70 to 145 V dc, nominal 125 V dc (WDIIH3)
• 90 to 143 V rms ac , nominal 115 V rms ac, 50/60 Hz ±3 Hz (WDIIH1)
• 180 to 265 V rms ac, nominal 230 V rms ac, 50/60 Hz ±3 Hz (WDIIH1)
Note 250 V dc range is not supported in this configuration as no WDII board can
support 250 V dc range for system wetting.
If the wetting voltage goes out of the above ranges (Board level wetting voltage
configuration is applicable only for WDIIH1; for WDIIH2 this value is fixed to 48
V dc and for WDIIH3 it is fixed to 125 V dc), an invalid voltage alarm occurs and
the status LED indicator turns RED. Contact status is not reported if there is invalid
voltage. Accuracy for voltage monitoring for Invalid voltage alarm: ±6%.
Voltage ranges for Series Parallel resistor configuration

Voltage ranges:

Note 250 V dc range is not supported in this configuration as no WDII board can
If the wetting voltage goes out of the above ranges (Board level wetting voltage
configuration is applicable only for WDIIH1; for WDIIH2 this value is fixed to 48
V dc and for WDIIH3 it is fixed to 125 V dc), an invalid voltage alarm occurs and
the status LED indicator turns RED. Contact status is not reported if there is invalid
voltage. Accuracy for voltage monitoring for Invalid voltage alarm: ±6%.

Sequence of Event (SOE)
The Sequence of Events (SOE) function records contact transitions using time stamping
to display the sequence. It can be configured to be enabled or disabled.
Note SOE accuracy for contacts with DC voltage — ±1 ms. SOE accuracy for
contacts with AC voltage — ±3 ms
The SOEs are only for contact transitions and not for the faults related to field line
monitoring. When the system is configured for field line monitoring (Parallel/ Series
Parallel Resistor) in subsequent transitions the SOEs are logged as follows:
• If false, the contact in default configuration directly changes to the line-to-line short
condition and one SOE is logged. The contact state in the ToolboxST application
is TRUE UNHEALTHY (TRUE-U). The SOE needs to be ignored in this case,
since the actual contact state does not change from False to True.
• If true, the contact in default configuration directly changes to the open wire
is FALSE UNHEALTHY (FALSE-U). The SOE needs to be ignored in this case,
• If true, the contact in invert configuration directly changes line-to-line short
is FALSE UNHEALTHY (FALSE-U). The SOE needs to be ignored in this case,
• If false, the contact in invert configuration directly changes to open wire condition
and one SOE is logged. The contact state in the ToolboxST application is TRUE
UNHEALTHY (TRUE-U). The SOE needs to be ignored in this case, since
the actual contact state does not change from False to True.
• If false, the contact in default configuration directly changes to open wire
condition and no SOE is logged. The contact state in the ToolboxST
application is FALSE UNHEALTHY (FALSE-U).
• If true, the contact in default configuration directly changes to line-to-line
short condition and no SOE is logged. The contact state in the ToolboxST
application is TRUE UNHEALTHY (TRUE-U)
• If true, the contact in Invert configuration directly changes to open wire
condition and no SOE is logged. The contact state in the ToolboxST
application is TRUE UNHEALTHY (TRUE-U)
• If false, the contact in Invert configuration directly changes to line-to-line
short condition and no SOE is logged. The contact state in the ToolboxST
application is FALSE UNHEALTHY (FALSE-U)
If the line monitoring is configured (Parallel/ Series Parallel Resistor), and the
wetting voltage changes suddenly (within 100 ms) by more than 7.5% the wrong
detection can happen for contact open or closed condition and wrong the SOEs
can be logged. When line fault occurs, it will be declared after 20 ms during
which contact status reported is as the last contact condition.

Specifications
Item Specification
Input isolation in pack Optical isolation to 1500 V on all inputs from inputs to system and channel to
channel
Voltage range for point isolated inputs nominal 14 to 32 V dc, 24 V dc;
nominal 19 to 64 V dc, 48 V dc;
nominal 90 to 143 V ac rms, 115 ac V rms, 50/60 Hz ±3 Hz;
nominal 90 to 265 V ac rms, 230 ac V rms, 50/60 Hz ±3 Hz.
If the wetting voltage goes out of the above ranges (Configured), then in
that case an alarm is raised as invalid voltage. In case of invalid voltage,
contact status is not reported. The wetting voltage is monitored only when it
is present at the TB points
Accuracy for voltage monitoring for Invalid ±6%
voltage alarm
Channel Mix When the SDII is used in point isolated configuration, there can be a mix of
ranges. That means every channel can have one of the ranges mentioned
above.
1,000 Hz scan rate for sequence of events (SOE) monitoring
Sequence of Event (SOE)—If enabled in SOE accuracy for contacts with DC voltage — ±1 ms
configuration SOE accuracy for contacts with AC voltage — ±3 ms
System Wetting with WDII connected WDIIH1 – 24 V dc, 115 V ac rms 50/60 Hz , 230 V ac rms 50/60 Hz
WDIIH2 – 48 V dc
WDIIH3 – 125 V dc
Voltage range for System wetted inputs-None nominal 18.5 to 32 V dc, 24 V dc; (WDIIH1)
and Parallel Resistor configuration nominal 32 to 64 V dc, 48 V dc; (WDIIH2)
nominal 70 to 145 V dc, 125 V dc; (WDIIH3)
nominal 90 to 143 V rms ac , 115 V rms ac, 50/60 Hz ±3 Hz; (WDIIH1)
nominal 180 to 265 V rms ac, 230 V rms ac, 50/60 Hz ±3 Hz. (WDIIH1)
250 V dc range is not supported in this configuration as no WDII board can
Accuracy for voltage monitoring for Invalid voltage alarm: ±6%
Voltage range for System wetted 42 to 56 V dc, nominal 48 V dc; (WDIIH2)
inputs-Series Parallel Resistor configuration
90 to 145 V dc, nominal 125 V dc; (WDIIH3)
24 V dc, 250 V dc, 115 V ac and 230 V ac ranges are not supported in this
configuration.
Accuracy for voltage monitoring for Invalid voltage alarm: ±6%
Mix of point isolated and system wetted Possible with WDIIH1 and WDIIH2
channels
Fault detection Loss of contact input excitation voltage (Loss of system wetting voltage only
when WDII is connected)
Single resistor fault detection option-Parallel WDIIH1, WDIIH2, WIIH3 —
resistor Configuration Fuse Blown/ open field wire

Item Specification
Dual resistor fault detection Series Parallel WDIIH2, WIIH3 —
resistor Configuration Fuse Blown/ open field wire
Line to line short in the field
Fuse used in WDIIH1 and WDIIH2 for each WDIIH1 and WDIIH2 have removable fuses one per channel in the supply line
channel as per the following description. In case of replacement the exact part shall
be used.
Littlefuse –372 series, 200 mA, 250 V radial fuse (Part number 3720200051
or 37202000511)
GE part number – 342A4908AFP1
Fuse used in WDIIH3 WDIIH3 has non-removable thermal fuse (PTC) in the supply line
Physical

PDIO Discrete Input/Output Module
Discrete Input/Output (PDIO)

PDIO The Discrete Input/Output (PDIO) pack provides the electrical interface between one
RLY RLY
PWR
or two I/O Ethernet networks and a discrete input/output terminal board. The pack
1 x x 2
3 x x 4 ATTN contains a processor board common to all Mark* VIe distributed I/O packs and an
5 x x 6
7 x x 8 acquisition board specific to the discrete input/output function. The pack accepts up
9 x x 10
to 24 contact inputs, controls up to 12 relay outputs, and receives terminal board
11 x x 12 LINK specific feedback signals. The associated terminal board determines voltage capability
ENET1
TxRx
C-IN C-IN of PDIO. System input to the pack is through dual RJ45 Ethernet connectors and a
1 x x 2
3 x x 4 three-pin power input. Discrete signal input/output is through a DC-62 connector that
5 x x 6
connects directly with the associated terminal board connector. Visual diagnostics are
LINK
ENET2
7 x
x
x
x
8
TxRx provided through indicator LEDs.
9 10
11 x x 12
13 x x 14 Note The infrared port is not used.
IR PORT
15 x x 16
17 x x 18
19 x x 20 PDIO is the functional equivalent of a PDIA and PDOA I/O pack combined into a
21 x
x
x
x
22 single assembly. For simplex applications, it goes on a TDBS terminal board that is
23 24
the equivalent of a SRLY relay terminal board combined with a STCI contact input
IS220 PDIOH1A terminal board. For TMR applications, it goes on a TDBT terminal board that, with
the WROB option, provides the equivalent of a terminal board combined with a TBCI
contact input terminal board.
GEH-6721L PDIO Discrete Input/Output Module System Guide 11-1

The following illustration shows the connections when three PDIO packs
are mounted on a TDBT terminal board.
PDIOH1A
Discrete Input
Output pack
Processor board
Application board
Single or dual
Ethernet cables
ENET1
TDBT Contact Input
Relay Output
Relay Outputs Terminal Board ENET2
(12)
External 28 V dc
power supply
ENET1
Three
PDIO
packs ENET2
28 V dc
Contact Inputs
(24) ENET1
ENET2
28 V dc
Compatibility
PDIOH1A is compatible with two types of discrete contact input/output terminal boards:
TDBS for single PDIO applications and TDBT for TMR PDIO applications. The
relay output portion of the terminal board accepts option cards as described later in
this document. The following table gives details of the compatibility:
Terminal Board Control Mode DI Voltage DO Option Cards

TDBSH2 Simplex 24 V dc WROB, WROF, WROG
TDBTH2 TMR 24 V dc WROB
• TMR uses three I/O packs with one network connection on each.

Installation
¾ To install the PDIO pack
2. Directly plug the PDIO I/O pack into the terminal board connectors.
Note The PDIO mounts directly on a Mark VIe terminal board. Simplex terminal
boards have a single DC-62 pin connector that receives the PDIO. TMR-capable
terminal boards have three DC-62 pin connectors, one used for simplex operation,
two for dual operation, and three for TMR operation. PDIO directly supports all of
these connections.

Wizard again.

Operation
Processor




Status LEDs
Processor LEDs

present
LED Status

ATTN
or module.
ATTN
every 4 sec

Contact Input Signals
The discrete input/output acquisition board provides the second stage of signal
conditioning and level shifting to interface the terminal board inputs to the control logic.
Initial signal conditioning is provided on the terminal board. The discrete input acquisition
input circuit is a comparator with a variable threshold. Each input is isolated from the
control logic through an opto-coupler and an isolated power supply. The inputs are not
isolated from each other. Each of the twenty-four inputs has filtering, hysteresis, and a
yellow status LED, that indicates when an input is picked up. The LED will be OFF when
the input is dropped-out. The LEDs are grouped at the bottom left of the PDIO pack.
INX
Threshold Ref +
- Vout
CINX In+
+
Rin In- -
Stat
DCOM
ICOM
Variable Input Threshold

The input threshold is derived from the contact wetting voltage input terminal. In
most applications this voltage is scaled to provide a 50% input threshold. This
threshold is clamped to 13% to prevent an indeterminate state if the contact wetting
voltage drops to zero. If the contact wetting voltage drops below 40% of the nominal
voltage, the under-voltage detector annunciates this condition to the control. A
special test mode is provided to force the inputs from the control pack. Every
four seconds, the threshold is pulsed high and then low and the response of the
opto-couplers is checked. Non-responding inputs are alarmed.
Relay Command Signals

The PDIO relay command signals are the first stage of signal conditioning and level
shifting to interface the terminal board outputs to the control logic. Each output is an open
collector transistor circuit with a current monitor to sense when the output is picked up
and connected to a load. The status LEDs and monitor outputs indicate when an output
is picked up and connected to the terminal board. If an output is commanded to be
picked up and the correct load is not sensed, the status LED will be off and the monitor
line will be false. The LEDs are grouped at the top left of the PDIO pack.
To TB Relay
Driver Power
Command
From Monitor
Processor
Stat
Output
Enable Common

Output Enable
All of the outputs are disabled during power application until a variety of internal
self-tests are completed. An enable line reflects the status of all required conditions
for operation. This function provides a path independent of the command to ensure
relays stay dropped-out during power-up and initialization.
Monitor Inputs/Control
There are 15 inverting level shifting monitor input circuits. On a typical terminal
board 12 of these circuits are used as relay contact feedbacks and the other three
are used for fuse status. An inverting level shifting line is also provided from the
control to the terminal board for status feedback multiplexing control allowing the
pack to receive two sets of 15 signals from a terminal board.
Sequence Of Events
All of the inputs and outputs may be individually configured to generate SOE
records when the signal changes. Input hardware is scanned at a 1000 Hz rate
for SOE time stamping while output commands are captured when a change of
command is received through Ethernet from the controller.
ID Line
Power Management
Connectors
• A DC-62 pin connector on the underside of the PDIO pack connects directly to

Specifications
Item Specification
Number of input channels 24 DI and 12 form C contact DO
Input isolation in pack Optical isolation to 1500 V on all inputs (group isolation)
Input Filter Hardware filter, 4 ms
Ac voltage rejection 60 V rms at 50/60 Hz at 125 V dc wetting voltage
Number of relay command 12 relays
channels
Relay and coil monitoring 15 pack inputs. The selection of monitor feedbacks depends on the type of terminal board
used, based on ID chip
I/O pack response time From Ethernet command to output is typically 4 ms.
SOE reporting Each relay may be configured to report operation in the sequence of events (SOE) record.
Fault detection Loss of contact input wetting voltage
Relay position feedback using contact pair separate from load contacts
Diagnostics
• A powerup self-test that includes checks of RAM, flash memory, Ethernet

• Continuous monitoring of the internal power supplies for correct operation.
• A powerup check of the electronic ID information from the terminal
board, acquisition board, and processor board to confirm that the hardware
set matches, followed by a check that the application code loaded from
flash memory is correct for the hardware set.
• Monitoring for loss of contact input wetting voltage on the terminal board
takes place at the selected system frame rate.
• Detecting a non-responding contact input during diagnostic test. In this test, the
threshold is pulsed high and low and the response of the opto-couplers is checked.
The test typically runs once every four seconds, and can be observed as a very
brief period when all twenty-four contact input lights turn on.
• A frame rate comparison is made between the commanded state of each relay
drive and the feedback from the command output circuit.
• Relay board specific feedback is read by the pack and processed every frame.
The information varies depending on the relay board type. Refer to relay
terminal board documentation for feedback specifics.

Configuration

PDIO_Mod_Configuration
Redundancy Redundancy mode of the pack Simplex, TMR
PDIO_Input Terminal board connected to PDIO Connected, not connected
Relay Feedback Selection will enable Relay feedback inputs Used, Unused
Contact Input Selection will enable Contact Input feedbacks Used, Unused
Sequence of Events Record contact transitions in sequence of events Enable, disable
Diag Vote Enable Enable voting disagreement diagnostic Enable, disable
Signal Filter Contact input digital filter in msec (in addition to 4 0, 10, 20, 50, 100
ms hardware filter)
PDIO_Output
Relay Output Selection will enable use of the relay Used, Unused
Signal Invert Invertion makes relay closed if signal is false Normal, Invert
SeqOfEvents Record relay command transitions in sequence Enable, Disable
of events
FuseDiag Enable fuse diagnostic - Will appear Enable, Disable
as configuration item for use with Fuse
daughterboard
Output_State Select the state of the Relay condition based on PwrDownMode, HoldLastValue,
IOPack going offline with controller Output_Value

TDBS Simplex Discrete Input/Output
The Simplex Discrete Input/Output (TDBS) terminal board is a simplex contact
input/output terminal board designed for DIN-rail or flat mounting. The TDBS board
accepts 24 group isolated contact inputs that are supplied with a nominal 24, 48, or 125 V
dc wetting voltage from an external source. The contact inputs have noise suppression
to protect against surge and high-frequency noise. TDBS provides 12 form-C relay
outputs and accepts different option cards to expand relay functions.
Mark VIe Systems

In the Mark* VIe systems, the PDIO I/O pack works with the TDBS. The I/O
pack plugs into the D-type connector and communicates with the controller
over Ethernet. A single connection point for PDIO is provided with one or two
network connections possible from PDIO to the controllers.
Board Versions
Three versions of TDBS are available as follows:
Terminal Board Contact Inputs TB Type Wetting Voltage

TDBSH2A 24 Pluggable Nominal 24 V dc, floating,
ranging from 16 to 32 V dc
There are three option boards available that plug on to TDBS:
• IS200WROB turns the relay portion of TDBS into the functional equivalent of
IS200TRLYH1B. This option provides fused and sensed power distribution to the
first six relay outputs and dedicated power to the last relay output.
• IS200WROF puts a single fuse in series with each relay common
connection. Fuse voltage feedback is included.
• IS200WROG distributes power from an input connector to each relay through
a single fuse. Fuse voltage feedback is included.

Installation
The TDBS plus a plastic insulator mounts on a sheet metal carrier that then mounts on
a DIN rail. Optionally the TDBS plus insulator mounts on a sheet metal assembly that
then bolts in a cabinet. The connections are wired directly to two sets of 48 point terminal
blocks, typically using #18 AWG wires. The upper set of terminals, TB1, connects
to the relay portion of the board and the lower set of terminals, TB2, connect to the
contact input circuits. Shields should be terminated on a separate bracket.
If a relay option board is used, it plugs onto TDBS connectors JW1 and JW2 and is held in
place by the force of the connectors. The following table identifies the function of each
relay terminal point grouped as TB1 as it relates to the presence of an option board. If
external power is to be supplied it is wired to a connector provided on the option board.
• NC - normally closed contact of a form C relay

• COM - common point of a form C relay contact
• NO - normally open contact of a form C relay
• SOL - return circuit path for a solenoid that is powered by the relay board
• VSENSE - the input to a voltage sensor that looks between VSENSE and COM
• RETURN - return power path for devices powered by the WROG option
Output Relay TDBS TDBS + TDBS/WROF with TDBS/WROF without TDBS +

Terminal WROB FUSES Fuses WROB
1 1 NC NC NC NC NC
2 COM COM COM (unfused) COM POWER
3 NO NO NO NO NO
4 SOL COM (fused) VSENSE RETURN
5 2 NC NC NC NC NC
7 NO NO NO NO NO
9 3 NC NC NC NC NC
11 NO NO NO NO NO
13 4 NC NC NC NC NC
15 NO NO NO NO NO
17 5 NC NC NC NC NC
19 NO NO NO NO NO
21 6 NC NC NC NC NC

Output Relay TDBS TDBS + TDBS/WROF with TDBS/WROF without TDBS +
Terminal WROB FUSES Fuses WROB
23 NO NO NO NO NO
25 7 NC NC NC NC NC
27 NO NO NO NO NO
28 COM (fused) VSENSE RETURN
29 8 NC NC NC NC NC
31 NO NO NO NO NO
33 9 NC NC NC NC NC
35 NO NO NO NO NO
37 10 NC NC NC NC NC
39 NO NO NO NO NO
43 NO NO NO NO NO
47 NO NO NO NO NO

Contact input connections are made to the 48 terminals on the lower portion of the
terminal board, grouped as TB2. Contact wetting voltage is provided to the board through
the JE1 3-pin Mate-N-Lok® connector on the lower portion of the board.
Terminal Signal Terminal Signal

1 Wet 1 25 Wet 13
2 In 1 26 In 13
3 Wet 2 27 Wet 14
4 In 2 28 In 14
5 Wet 3 29 Wet 15
6 In 3 30 In 15
7 Wet 4 31 Wet 16
8 In 4 32 In 16
9 Wet 5 33 Wet 17
10 In 5 34 In 17
11 Wet 6 35 Wet 18
12 In 6 36 In 18
13 Wet 7 37 Wet 19
14 In 7 38 In 19
15 Wet 8 39 Wet 20
16 In 8 40 In 20
17 Wet 9 41 Wet 21
18 In 9 42 In 21
19 Wet 10 43 Wet 22
20 In 10 44 In 22
21 Wet 11 45 Wet 23
22 In 11 46 In 23
23 Wet 12 47 Wet 24
24 In 12 48 In 24
The wetting voltage output terminals are all connected in parallel and fed from the positive
voltage applied to JE1 pin 1. It is permissible to run a single wetting voltage lead from the
board terminal to a group of remote contacts and then bring the individual contact wires
back to the inputs. Negative or return wetting voltage is supplied by JE1 pin 3.

TDBS Layout

Operation
Contact Inputs
The contact input function and on-board signal conditioning are scaled for 24, 48, and
125 V dc wetting voltage. The input wetting voltage range is 16 to 32 V dc, 32 to 64
V dc, and 100 to 145 V dc respectively. The threshold voltage is 50% of the wetting
voltage. The contact sensing circuits are shown in the I/O pack description. Contact
input currents are resistance limited to 2.5 mA on the first 21 circuits, and 10 mA on
circuits 22 through 24. The 24 V dc supply on TDBSH2 is current limited to 0.5 A
using polymer positive temperature coefficient fuses that can be reset.
Relay Outputs
TDBS uses pluggable type terminals and has connectors JW1 and JW2 supporting
option board connection. The relay portion of TDBS does not change between
groups H2, H4, and H6, only the contact input circuits change. TDBS relays may
be used at any specified ac or dc voltage without regard to board group. Electrically
TDBS has the following circuit for each of the 12 relays:
TDBS
NC (1)
COM (2)
NO (3)
SOL (4)
fdbk
JW1
Twelve Circuits
JA1
48 Terminals
JW2
Without an option board, the SOL terminal associated with each relay has no
connection. TDBS is designed to support a current rating of 5 A and voltage
clearance greater than is needed for 250 V ac on all customer screw and JW1
circuits. The relay rating is the limiting item for each application.

TDBS +WROB
Option board IS200WROBH1A adds capability to TDBS to yield a combination that
has the same relay circuit functionality as an IS200TRLYH1B terminal board when
used simplex. Included are fused sensed power distribution to the first six relays
and dedicated power to the last relay. Electrically IS200TDBS plus IS200WROBH1
has the following circuit. IS200WROBH1 has default fuse values of 3.15 A.
Connector JW2 and its connections to JA1 are omitted for clarity.
TDBS
NC (1)
COM (2)
JA1
NO (3)
Fdbk on all relays SOL (4)

fdbk
48 Terminals
JW1 Total
JF1(1)
JF2(1) JP
fdbk V MOV
JF1(3) R1-6 only

JF2(3) WROBH1A
1 JG1
NC (45)
4 COM (46)
R12 only JW1
NO (47)
MOV
SOL (48)
Both sides of the power distribution on relays 1-6 are fused allowing the board
to be used in systems where dc power is floating with respect to earth. Fuse
voltage feedback is compatible with 24 V, 48 V, and 125 V dc applications
as well as 120 V and 240 V ac applications.
The following table lists the relationship between fuses, jumpers, relays, and terminals.
Relay +Fuse -Fuse Jumper Terminals

1 FU7 FU1 JP1 1-4
2 FU8 FU2 JP2 5-8
3 FU9 FU3 JP3 9-12
4 FU10 FU4 JP4 13-16
5 FU11 FU5 JP5 17-20
6 FU12 FU6 JP6 21-24

TDBS + WROF
Option board IS200WROFH1A adds an optional fuse in series with the COM
connection for each relay output by using the SOL terminal in place of COM.
Isolated voltage sensing that is not polarity sensitive is provided for each fuse. Fuse
voltage feedback is compatible with 24 V, 48 V, and 125 V dc applications as well
as 120 V and 240 V ac applications. IS200WROFH1 has default fuse values of
3.15 A. Electrically IS200TDBS plus IS200WROFH1 has the following circuit.
TDBS
NC (1)
COM unfused (2)
NO (3)
COM fused (4)

fdbk
JW1
WROFH1
A fdbk V
JA1
Twelve Circuits 48 Terminals
The normal application for this board is when it is desired that each relay output have a
fuse in series and power applied from an external source. The board has a second potential
application. If the fuse is removed from a circuit, the isolated voltage detector remains.
The fourth terminal may now be wired to either the NC or NO terminal to provide
isolated contact voltage feedback. I/O pack firmware has a configuration option to turn
off fuse blown alarm generation for a given relay if it is being used in this fashion. The
terminal table identifies this application as making the fourth screw Vsense.
Fuses FU1 through FU12 are associated with relay circuits 1 through 12 respectively.

TDBS + WROG
Option board IS200WROGH1A adds fused power distribution for all twelve relay
outputs. Isolated voltage sensing that is not polarity sensitive is provided for each
fuse. Fuse voltage feedback is compatible with 24 V, 48 V, and 125 V dc applications,
as well as 120 V and 240 V ac applications. IS200WROGH1 has default fuse values
of 3.15 A. Electrically IS200TDBS plus IS200WROGH1 has the following circuit.
TDBS
NC (1)
Was COM,
now Pwr (2)
NO (3)
Was SOL (4)
fdbk
Now Ret (4)
JW1
WROGH1 JF1
A fdbk V 3
JA1 2
1
Twelve Fuse Circuits, one JF1 input.

48 Terminals

Specifications
Item Specification
Number of input channels 24 dry contact voltage input channels
Wetting voltage H2: Nominal 24 V dc, floating, ranging from 18.5 to 32 V dc (Pluggable TB)
H4: Nominal 48 V dc, floating, ranging from 32 to 64 V dc (Pluggable TB)
Input current H2: For 24 V dc applications:
H4: For 48 V dc applications:
Fault detection in I/O board Loss of contact input wetting voltage
Ac voltage rejection 12 V rms at 24 V dc wetting voltage. (H2)
24 V rms at 48 V dc wetting voltage. (H4)
Number of relay channels 12 relays
Rated voltage on relay contacts a: Nominal 24 V dc, 48 V dc, or 125 V dc
b: Nominal 120 V ac or 240 V ac
Max load current a: 0.6 A for 125 V dc operation
b: 1.2 A for 48 V dc operation
c: 3.15 A for 24 V dc operation
d: 3.15 A for 120/240 V ac, 50/60 Hz operation
Max response time on 25 ms typical
Max response time off 25 ms typical
Contact material Silver cad-oxide
Contact life Electrical operations: 100,000
Mechanical operations: 10,000,000
Fault detection Relay position feedback using contact pair separate from load contacts.
WROBH1 Option Board
Powered Output Circuits
6 fused, associated with relays 1-6, fed from parallel connectors JF1 and JF2. Both sides
of the power source are fused for each output. MOV suppression on NO contact.
1 unfused, associated with relay 12, fed from connector JG1. MOV suppression on
NO contact.
WROFH1 Option Board
Fused Output Circuits 12 fused circuits, one per relay.
WROGH1 Option Board
Powered Output Circuits 12 fused circuits, one associated with each relay. Single side fusing of the power is
associated with the power input on JF1 pin 1. Return power path through JF1pin 3 is
not fused.

Item Specification
Physical
Size - TDBS 17.8 cm wide x 33.02 cm high (7.0 in x 13.0 in)
Diagnostics
The I/O processor monitors the following functions on TDBS:
• The contact input wetting voltage is monitored. If the wetting voltage drops to below
40% of the nominal voltage, a diagnostic alarm (fault) is set and latched.
• The TDBS provides diagnostic feedback to PDIO indicating the state of each
relay by monitoring an isolated set of contacts on each relay.
• When WROB is used with TDBS isolated voltage feedback is used to detect
fuse status for the six fuse pairs on the board.
• When WROF is used with TDBS isolated voltage feedback is used to monitor
each fuse. If voltage is present and the fuse is open a diagnostic is generated.
The diagnostic may be disabled in PDIO configuration should it be desired
to use the feedback circuit with the fuse removed.
• When WROG is used with PDIO isolated voltage feedback is used to monitor each
fuse. If voltage is present and the fuse is open a diagnostic is generated.
• The terminal board connector has an ID device that is interrogated by the I/O
processor. The connector ID is coded into a read-only chip containing the board serial
number, board type, and revision number. Any relay option card also contains an ID.
If a mismatch is encountered, a hardware incompatibility fault is created.
Configuration
There are no jumpers or hardware settings on TDBS.
Option board WROBH1 includes six jumpers that are used to apply or remove power from
a relay. Boards are produced with all six jumpers in place. The jumper is removed from
the board when a relay is to be used as dry contacts and power distribution is not desired.
There are no jumpers associated with the WROFH1 board. For each relay the
inclusion or exclusion of a series fuse is determined by the terminal point used as the
relay common. For each relay the associated WROF fuse may be removed to allow
direct use of the fuse voltage sensing circuit as a voltage detector.
There are no jumpers associated with the WROGH1 board. For each relay the
corresponding fuse may be removed if the relay is to be used to provide dry contacts.

TDBT Discrete Input/Output
The Discrete Input/Output (TDBT) terminal board is a TMR contact input/output
terminal board designed for DIN-rail or flat mounting. The TDBT board accepts 24
group isolated contact inputs that are supplied with a nominal 24, 48, or 125 V dc
wetting voltage from an external source. The contact inputs have noise suppression
to protect against surge and high-frequency noise. TDBT provides 12 form-C relay
outputs and accepts an option card to expand relay functions.
In Mark* VIe systems, the PDIO I/O pack works with the TDBT. Three I/O packs
plug into D-type connectors and communicate with the controllers over Ethernet.
Three connection points for PDIO are provided. With dual controllers the PDIO on
TDBT connector JR1 would be networked to the R controller, JS1 PDIO to the S
controller, and JT1 PDIO to both R and S controllers. With TMR controllers one
network connection is provided to each PDIO leading to the respective controller.
TDBT is not designed to operate correctly with a single PDIO I/O pack.
Board Versions
Three versions of TDBT are available as follows:
Terminal Board Contact Inputs TB Type Wetting Voltage

TDBTH2A 24 Pluggable Nominal 24 V dc, floating, ranging
from 16 to 32 V dc
TDBTH4A 24 Pluggable Nominal 48 V dc, floating, ranging
from 32 to 64 V dc
TDBTH6A 24 Pluggable Nominal 125 V dc, floating,
IS200WROB is an option board that plugs into TDBT to provide fused and sensed power
distribution to the first six relay outputs and dedicated power to the last relay output.
Note The IS200WROF and IS200WROG boards are not compatible with IS200TDBT.

Installation
The TDBT plus a plastic insulator mounts on a sheet metal carrier that then mounts
on a DIN rail. Optionally the TDBT plus insulator mounts on a sheet metal assembly
that then bolts in a cabinet. The connections are wired directly to two sets of 48
terminal blocks, typically using #18 AWG wires. The upper set of terminals, TB1,
connects to the relay portion of the board and the lower set of terminals, TB2,
connect to the contact input circuits. Screw assignments for the two sets of terminals
are identical to those found on the SRLY relay board and the STCI contact input
terminal board. Shields should be terminated on a separate bracket.
Relay Outputs
If a relay option board is used, it plugs onto TDBT connectors JW1 and JW2 and is held in
place by the force of the connectors. The following table identifies the function of each
relay terminal point grouped as TB1 as it relates to the presence of an option board. If
external power is to be supplied it is wired to a connector provided on the option board.
TB1 Relay TDBT TDBT + TB1 Relay TDBT TDBT +

Terminal WROB Terminal WROB
1 1 NC NC 25 7 NC NC
2 COM COM 26 COM COM
3 NO NO 27 NO NO
4 SOL 28
7 NO NO 31 NO NO
8 SOL 32
11 NO NO 35 NO NO
12 SOL 36
13 4 NC NC 37 10 NC NC
15 NO NO 39 NO NO
16 SOL 40
17 5 NC NC 41 11 NC NC
19 NO NO 43 NO NO
20 SOL 44
21 6 NC NC 45 12 NC NC
23 NO NO 47 NO NO
24 SOL 48 SOL

Contact Inputs
Contact input connections are made to the 48 terminals on the lower portion of the
terminal board, grouped as TB2. Contact wetting voltage is provided to the board through
the JE1 3-pin Mate-n-lok® connector on the lower portion of the board.
TB2 Signal TB2 Signal

Terminal Terminal
1 Wet 1 25 Wet 13
2 In 1 26 In 13
3 Wet 2 27 Wet 14
4 In 2 28 In 14
5 Wet 3 29 Wet 15
6 In 3 30 In 15
7 Wet 4 31 Wet 16
8 In 4 32 In 16
9 Wet 5 33 Wet 17
10 In 5 34 In 17
11 Wet 6 35 Wet 18
12 In 6 36 In 18
13 Wet 7 37 Wet 19
14 In 7 38 In 19
15 Wet 8 39 Wet 20
16 In 8 40 In 20
17 Wet 9 41 Wet 21
18 In 9 42 In 21
19 Wet 10 43 Wet 22
20 In 10 44 In 22
21 Wet 11 45 Wet 23
22 In 11 46 In 23
23 Wet 12 47 Wet 24
24 In 12 48 In 24
The wetting voltage output terminals are all in parallel and fed from the positive voltage
applied to JE1 pin 1. It is permissible to run a single wetting voltage lead from the board
terminal to a group of remote contacts and then bring the individual contact wires back
to the inputs. Negative or return wetting voltage is supplied by JE1 pin 3.

TDBT Layout

Operation
Contact Inputs
The contact input function and on-board signal conditioning are the same as those on
STCI, they are scaled for 24, 48, and 125 V dc wetting voltage. The input wetting voltage
range is 16 to 32 V dc, 32 to 64 V dc, and 100 to 145 V dc respectively. The threshold
voltage is 50% of the wetting voltage. The contact sensing circuits are shown in the I/O
pack description. Contact input currents are resistance limited to 2.5 mA on the first 21
circuits, and 10 mA on circuits 22 through 24. The 24 V dc supply on TDBTH2 is current
limited to 0.5 A using polymer positive temperature coefficient fuses that can be reset.
Relay Outputs
TDBT uses pluggable type terminals and has connectors JW1 and JW2 supporting
option board connection. The relay portion of TDBT does not change between
groups H2, H4, and H6, only the contact input circuits change. TDBT relays may
be used at any specified ac or dc voltage without regard to board group. Electrically
TDBT has the following circuit for each of the 12 relays:
TDBT
NC (1)
COM (2)
NO (3)
SOL (4)
P28
JT1
JW1
P28
Vote Twelve Circuits
To 48 Terminals
JR1
JS1
JS1 JT1
JW2
P28R
P28S P28
P28T
JR1

connection. TDBT is designed to support a current rating of 5 A and voltage clearance
greater than is needed for 250 V ac on all customer screw and JW1 circuits. The
relay contact rating is the limiting item for each application.
TDBT + WROB
Option board IS200WROBH1A adds capability to TDBT to yield a combination that has
the same relay circuit functionality as an IS200TRLYH1B terminal board when used
in a TMR system. Included are fused sensed power distribution to the first six relay
contacts and dedicated power to the last relay contact. Electrically IS200TDBT plus
IS200WROBH1 has the following circuit. IS200WROBH1 has default fuse values
of 3.15 A. Connector JW2 and its connections are omitted for clarity.
TDBT
NC (1)
COM (2)
NO (3)
P28 SOL (4)

JT1 JW1 48 Terminals
P28
Vote
P28R
P28S P28
P28T
JF1(1)
JF2(1) JP
fdbk V MOV
JS1
JF1(3) R1-6 only
JF2(3) WROBH1A
1 JG1
NC (45)
4 COM (46)
R12 only JW1
NO (47)
MOV
JR1
SOL (48)

+Fuse -Fuse Jumper Terminals

FU7 FU1 JP1 1-4
FU8 FU2 JP2 5-8
FU9 FU3 JP3 9-12
FU10 FU4 JP4 13-16
FU11 FU5 JP5 17-20
FU12 FU6 JP6 21-24

Specifications
Item Specification
Wetting voltage H2: Nominal 24 V dc, floating, ranging from 18.5 to 32 V dc (Pluggable TB)
Input current H2: For 24 V dc applications:
Fault detection in I/O board Loss of contact input wetting voltage
Ac voltage rejection 12 V rms at 24 V dc wetting voltage. (H2)
Number of relay channels 12 relays
on one TDBT board
Rated voltage on relay a: Nominal 24 V dc, 48 V dc, or 125 V dc
contacts b: Nominal 120 V ac or 240 V ac
WROBH1 Option Board
Powered Output Circuits 6 fused, associated with relays 1-6, fed from parallel connectors JF1 and JF2. Both sides of
the power source are fused for each output. MOV suppression across NO relay contact.
1 unfused, associated with relay 12, fed from connector JG1. MOV suppression across NO
relay contact.
Physical
Size - TDBT 17.8 cm wide x 33.02 cm high (7.0 in x 13.0 in)

Diagnostics
The I/O processor monitors the following functions on TDBT:
• The contact wetting voltage is monitored. If the wetting voltage drops to below
40% of the nominal voltage, a diagnostic alarm (fault) is set and latched.
• The TDBT provides diagnostic feedback to PDIO indicating the state of
each relay by monitoring an isolated set of contacts on each relay. Position
feedback is fanned out to all three PDIO packs.
• When WROB is used with TDBT isolated voltage feedback is used to
detect fuse status for the six fuse pairs on the board. TDBT provides
this feedback to all three PDIO packs.
• Each terminal board I/O pack connector has an ID device that is interrogated by
the I/O processor. The connector ID is coded into a read-only chip containing the
board serial number, board type, and revision number. WROB contains three ID
devices, one for each PDIO. If a mismatch between I/O pack, terminal board, or
option card is encountered, a hardware incompatibility fault is created.
Configuration
There are no jumpers or hardware settings on TDBT.

PDOA Discrete Output Module
Discrete Output (PDOA)

DISCRETE OUT The Discrete Output (PDOA) pack provides the electrical interface between one
PWR or two I/O Ethernet networks and a discrete output terminal board. The pack
1
2 ATTN
contains a processor board common to all Mark* VIe distributed I/O packs and
3 an acquisition board specific to the discrete output function. The pack is capable
of controlling up to 12 relays and accepts terminal board specific feedback.
LINK
4 ENET1 Electromagnetic relays (with types TRLYH1B, C, D, and F terminal boards) and
5 TxRx solid-state relays (with type TRLYH1E boards) are available. Input to the pack
6
is through dual RJ45 Ethernet connectors and a three-pin power input. Output is
LINK through a DC-37 pin connector that connects directly with the associated terminal
7 ENET2
8 TxRx
board connector. Visual diagnostics are provided through indicator LEDs.
9
IR PORT Note The infrared port is not used.
10
11
12
IS220PDOAH1A
PDOAH1A
Discrete Output
Pack Processor board
Application board
Single or dual
Ethernet cables
ENET1
TRLY Relay Output
Terminal Board
(5 types) ENET2
External 28 V dc
power supply
Relay Outputs
(6 or 12)
ENET1
ENET2
28 V dc
Three PDOA packs for TMR

ENET1
and Dual control.
ENET2
One PDOA pack for Simplex
28 V dc
GEH-6721L PDOA Discrete Output Module System Guide 12-1

Compatibility
PDOAH1A is compatible with six types of discrete (relay) output terminal boards,
including the TRLY boards and SRLY boards, but not the DIN-rail mounted DRLY boards.
Terminal Board TRLYH1B, H1C, H1D, H1E, and H1F DRLY SRLYH1A and
B
Control mode Simplex - Yes Dual - No TMR - Yes No Simplex - Yes
Installation
¾ To install the PDOA pack
2. Directly plug the PDOA I/O pack into the terminal board connectors.
applied to the DC37 connector between the pack and the terminal board. The
Note The PDOA mounts directly on a Mark VIe terminal board. Simplex terminal
boards have a single DC-37 connector that receives the PDOA. TMR-capable terminal
boards have four DC-37 connectors, one used for simplex operation and three used for
TMR operation. PDOA directly supports all of these connections.

Wizard again.

Operation
Processor




Status LEDs
Processor LEDs

present
LED Status

ATTN
or module.
ATTN
every 4 sec

The PDOA relay command signals are the first stage of signal conditioning and level
shifting to interface the terminal board outputs to the control logic. Each output is an open
collector transistor circuit with a current monitor to sense when the output is picked up
and connected to a load. The status LEDs and monitor outputs indicate when an output is
picked up and connected to the terminal board. If an output is picked up and the correct
load is not sensed, the status LED will be off and the monitor line will be false.
To TB Relay Driver
Power
Command In
Monitor
From Processor
Stat
Enable
Common
Output Enable
All of the outputs are disabled during power application until a variety of internal
self-tests are completed. An enable line reflects the status of all required conditions
for operation. This function provides a path independent of the command to ensure
relays stay dropped-out during power-up and initialization.
Monitor Inputs/Control
There are 15 inverting level shifting monitor input circuits. On a typical TRLY
terminal board 12 of these circuits are used as relay contact feedbacks and the other
three are used for fuse status. An inverting level shifting line is also provided from
the control to the terminal board for status feedback multiplexing control allowing
the pack to receive two sets of 15 signals from a terminal board.
ID Line
Power Management

Connectors
• A DC-62 pin connector on the underside of the I/O pack connects
directly to a discrete output terminal board.
• An RJ-45 Ethernet connector named ENET1 on the pack side is
• A second RJ-45 Ethernet connector named ENET2 on the pack side is
Note The terminal board provides fused power output from a power source that is
applied directly to the terminal board, not through the I/O pack connector.
Specifications
Item Specification
Number of relay channels in 12 relays (different types depending on the terminal board)
one PDOA pack
Relay and coil monitoring 15 pack inputs. The selection of monitor feedbacks depends on the type of terminal board
used, based on ID chip
I/O pack response time From Ethernet command to output is approximately in 6 ms.
SOE reporting Each relay may be configured to report operation in the Sequence of Events (SOE) record.
Physical
Size 8.26 cm high x 4.19 cm wide x 12.1 cm deep
(3.25 in. x 1.65 in. x 4.78 in.)
Diagnostics
• A power-up self-test that includes checks of RAM, flash memory,

Ethernet ports, and processor board hardware
• A comparison is made between the commanded state of each relay drive
and the feedback from the command output circuit.
• Relay board specific feedback is read by the pack and processed. The
information varies depending n the relay board type. Refer to relay terminal
board documentation for feedback specifics.
• Continuous monitoring of multi-cast communications with a PGEN pack
if the PDOA has been configured for “IO module trip from” a PGEN
for the power load unbalance (PLU) function.
Details of the individual diagnostics are available in the ToolboxST application.

The diagnostic signals can be individually latched, and then reset with
the RESET_DIA signal if they go healthy.

Configuration
At the module modification level, the selection “IO Module Trip From”, should be left
blank unless the PDOA is used with a PGEN to perform the power load unbalance (PLU)
function. See GEI-100589 for instructions on configuring the PDOA with a PGEN.

PDOA_ModGrps
System Limits Enable or disable all system limit checking. Enable, disable
Redundancy Redundancy mode of the pack Simplex, Dual, TMR
FuseSignJ3 RelayFdbk signals. Monitor fuse volts or contact volts.
PDOA_Input1
ContactInput
Signal Invert Inversion makes signal true if contact is open.
SeqOfEvents Record contact transitions in sequence of events
DiagVoteEnab Enable voting disagreement diagnostic
SignalFilter
PDOA_Output
Relay Output Used, Unused
Signal Invert Inversion makes relay closed if signal is false.
SeqOfEnvents Record relay command transitions in sequence of events
PDOA_Output1
Relay Output
Signal Invert Inversion makes relay closed if signal is false.
SeqOfEnvents Record relay command transitions in sequence of events
FuseDiag Enable fuse diagnostic

IS220PDOA PointsDef Description Direction Type
L3DIAG_PDOA I/O diagnostic indication Input BIT
LINK_OK_PDOA I/O link okay indication Input BIT
ATTN_PDOA I/O Attention Indication Input BIT
Cap1_Ready IO Pack Capture buffer 1 ready for upload-currently not used Point edit (Input BIT)
Cap2_Ready IO Pack Capture buffer 2 ready for upload-currently not used Point edit (Input BIT)
CV_Permissive CV (control valve) permissive for PGEN PLU function Point edit (Input BIT)
IV_Permissive IV (intercept valve) permissive for PGEN PLU function Point edit (Input BIT)
IS200TRLY PointDefs
Relay01
Relay01Fdbk Relay 01 contact voltage (first set of 12 relays) Point Edit (Input BIT)
Fuse01Fdbk Fuse voltage Point edit (Input BIT)

TRLYH1B Relay Output with Coil Sensing
The Relay Output with coil sensing (TRLY1B) terminal board holds 12 plug-in magnetic
relays. The first six relay circuits configured by jumpers for either dry, Form-C
contact outputs, or to drive external solenoids. A standard 125 V dc or 115/230 V
ac source, or an optional 24 V dc source with individual jumper selectable fuses and
on-board suppression, can be provided for field solenoid power. The next five relays
(7-11) are unpowered isolated Form-C contacts. Output 12 is an isolated Form-C
contact, used for special applications such as ignition transformers.


DC-64 pin connector for optional

power distribution daughterboard
TB1 J1 X
x JT1
x 2
x 1 DC-37 pin connector for I/O processor
x 4
x 3
x 5 K1R K1S K1T
x 6
x 8
x 7
x 10
x 9
x 11
x 12
x 14
x 13
x 15
x 16
x 18
x 17
x 20
x 19 JS1 J--Port
J PortConnections:
Connections:
x 21 18 sealed relays
12 Relay Outputs x 22
x 23 Plug
Plug in
in33I/O
I/O Packs
pack(s)
x 24
x for Mark VIe system
or
or
x
TB2
x 25 Cables to boards for Mark VI
x 26 Cables
control to boards
x 27
x 28 18 sealed relays for Mark VI system
x 30
x 29
x 32
x 31
x 33
JR1
x 34
x 36
x 35
x 37
x 38
x 40
x 39
x 41
x 42
x 43
x 44 K12R K12S K12T
x 46
x 45
x 48
x 47
x
J2 X
DC-64 pin connector for optional

Shield bar Barrier type terminal power distribution daughterboard
blocks can be unplugged
TRLY1B Relay Output Terminal Board

Board Mark VI control Mark VIe control Mark VIeS Safety Comments
Revision IS200VCRC, VCCC, or IS220PDOA control
VGEN IS220YDOA
TRLYH1B Yes, all versions Yes, all versions No
TRLYS1B No Yes, all versions Yes, all versions Safety certified version
Mark VI control systems TRLYH1B is controlled by the VCCC, VCRC, or VGEN board and supports simplex and
TMR applications. Cables with molded plugs connect the terminal board to the VME
rack where the I/O boards are mounted. Connector JA1 is used on simplex systems,
and connectors JR1, JS1, and JT1 are used for TMR systems.
Mark VIe /VIeS control systems The TRLY_1B works with the PDOA / YDOA I/O pack and supports simplex and TMR
applications. The I/O pack plugs into the DC-37 pin connectors on the terminal board.
Connector JA1 is used on simplex systems, and connectors JR1, JS1, and JT1 are
used for TMR systems.
Installation
Connect the wires for the 12 relay outputs directly to two I/O terminal blocks on the
terminal board as shown in the figure, TRLY1B Terminal Board Wiring. Each block is held
down with two screws and has 24 terminals accepting up to #12 AWG wires. A shield
terminal strip attached to chassis ground is located on to the left side of each terminal block.
Connect the solenoid power for outputs 1-6 to JF1. JF2 can be used to daisy chain power
to other TRLYs. Alternatively, power can be wired directly to TB3 when JF1/JF2 are not
used. Connect power for the special solenoid, Output 12, to connector JG1.
These jumpers are also for Jumpers JP1-JP6 are removed in the factory and shipped in a plastic bag. Re-install
isolation of the monitor the appropriate jumper if power to a field solenoid is required. Conduct individual
circuit when used on isolated loop energization checks as per standard practices and install the jumpers as
contact applications. required. For isolated contact applications, remove the fuses to ensure that
suppression leakage is removed from the power bus.

TRLY1B Terminal Board Wiring

Operation
Dry Contacts
When these terminal boards are used as dry contacts to switch ac voltage using circuits
01 through 06, and are simultaneously supplied with 125 V dc power through JF1,
JF2, or TB3, unless all the fuses and jumpers for a circuit are removed, ac power will
be present on the 'NO' relay terminal. In addition, when the contact closes, it will tie
the ac voltage to N 125 V dc. A similar situation exists for the P-125. Since most
ac supplies operate with a grounded neutral, the sum of the ac peak voltage and the
125 V dc is applied to MOVs connected between the dc and ground. In 120 V ac
applications, the MOV rating is sufficient to withstand that voltage. However, in 240
V ac applications the peak voltage will exceed the MOV rating, resulting in failure.
For this reason, it is preferable not to use these circuits for ac switching.
When the board is also supplied with 125 V dc, the preferred solution is not to connect
the circuits 01 through 06 to ac-powered control circuits. If there is insufficient
spare availability, remove both the fuses and the jumper for the contact in use for
ac switching, isolating the ac voltage on the contact circuit from the dc distribution
voltage. Store the jumpers and fuseholder caps separately to reduce the possibility of
inadvertent re-installation, (for example after some maintenance activity).
The risk of damage to the MOVs due to cross-connections between the ac and dc
power systems is not limited to the TRLY, but is present anywhere the 125 V dc is
exposed to cross-connection to 125 or 240 V ac. This is including but not limited
to contact sensing in motor control centers and breaker close circuits.
Simplex
Relay drivers, fuses, and jumpers are mounted on the TRLY_1B. For simplex
operation, D-type connectors carry control signals and monitor feedback voltages
between the I/O processors and TRLY1B through JA1.
Relays are driven at the frame rate and have a 3.0 A rating. The rated contact-to-contact
voltage is 500 V ac for one minute. The rated coil to contact voltage is 1,500 V
ac for one minute. The typical time to operate is 10 ms. Relays 1-6 have a 250
V metal oxide varistor (MOV) for transient suppression between normally open
(NO) and the power return terminals. The relay outputs have a failsafe feature
that vote to de-energize the corresponding relay when a cable is unplugged or
communication with the associated I/O processor is lost.

TRLY1B Circuits, Simplex System

TMR
For TMR applications, relay control signals are fanned into TRLY1B from
the three I/O processors R, S, and T through plugs JR1, JS1, and JT1. These
signals are voted and the result controls the corresponding relay driver. Power
for the relay coils comes from all three I/O processors and is diode-shared. The
following figure shows a TRLY1B in a TMR system.
TRLY1B Circuits, TMR System

Specifications
Item Specifications
Number of relay channels on one 12:
TRLY1B board 6 relays with optional solenoid driver voltages
5 relays with dry contacts only
1 relay with 7 A rating
Rated voltage on relays a: Nominal 125 V dc or 24 V dc
b: Nominal 115/230 V ac
c: 3.0 A for 115/230 V ac, 50/60 Hz operation
Maximum inrush current 10 A
Fault detection Loss of relay solenoid excitation current
Coil current disagreement with command
Unplugged cable or loss of communication with I/O board: relays de-energize if
communication with associated I/O board is lost
Physical
Temperature -30 to + 65ºC (-22 to +149 ºF)

Diagnostics
• The output of each relay (coil current) is monitored and checked against
the command at the frame rate. If there is no agreement for two
consecutive checks, an alarm is latched.
• The solenoid excitation voltage is monitored downstream of the fuses and
an alarm is latched if it falls below 12 V dc.
• If any one of the outputs goes unhealthy a composite diagnostics
alarm, L3DIAG_xxxx occurs.
• When an ID chip is read by the I/O processor and a mismatch is encountered,
a hardware incompatibility fault is created.
• Each terminal board connector has it own ID device that is interrogated by the
connector location. When the chip is read by the I/O processor and mismatch
• Relay contact voltage is monitored.
• Details of the individual diagnostics are available in the configuration
application. The diagnostic signals can be individually latched, and then
reset with the RESET_DIA signal if they go healthy.
Configuration
Board adjustments are made as follows:
• Jumpers JP1 through JP12. If contact voltage sensing is required,

insert jumpers for selected relays.
• Fuses FU1 through FU12. If power is required for relays 1-6, two fuses
should be placed in each power circuit supplying those relays. For
example, FU1 and FU7 supply relay output 1.

TRLYH1C Relay Output with Contact Sensing
The Relay Output with contact sensing (TRLYH1C) terminal board holds 12 plug-in
magnetic relays. The first six relay circuits are Form-C contact outputs to drive external
solenoids. A standard 125 V dc or 115 V ac source with fuses and on-board suppression is
provided for field solenoid power. TRLYH2C holds 12 plug-in magnetic relays. The first
six relay circuits are Form-C contact outputs to drive external solenoids. A standard 24 V
dc source with fuses and on-board suppression is provided for field solenoid power.
The next five relays (7-11) are unpowered, isolated Form-C contacts. Output 12 is an
isolated Form-C contact with non-fused power supply, used for ignition transformers. For
example, 12 NO contacts have jumpers to apply or remove the feedback voltage sensing.
TRLYH1C and 2C are the same as the standard TRLYH1B board except for the following:
• Six jumpers for converting the solenoid outputs to dry contact type are removed.
These jumpers were associated with the fuse monitoring.
• Input relay coil monitoring is removed from the 12 relays.
• Relay contact voltage monitoring is added to the 12 relays. Individual
monitoring circuits have voltage suppression and can be isolated by
removing their associated jumper.
• High-frequency snubbers are installed across the NO and SOL terminals on the
six solenoid driver circuits and on the special circuit, output 12.



TRLYH1C Relay Output Terminal Board With Voltage Sensing
Mark VI control systems TRLYH1C and 2C is controlled by the VCCC or VCRC board and supports simplex and
TMR applications. Cables with molded plugs connect the terminal board to the VME
rack where the I/O boards are mounted. Connector JA1 is used on simplex systems,
and connectors JR1, JS1, and JT1 are used for TMR systems.
Mark VIe control systems TRLYH1C and 2C works with the PDOA I/O pack and supports simplex and TMR
applications. PDOA plugs into the DC-37 pin connectors on the terminal board.
Connector JA1 is used on simplex systems, and connectors JR1, JS1, and JT1 are
used for TMR systems.

Installation
Connect the wires for the 12 relay outputs directly to two I/O terminal blocks on the terminal
board as shown in the figure, TRLYH1C Terminal Board Wiring. Each block is held down
with two screws and has 24 terminals accepting up to #12 AWG wires. A shield terminal
strip attached to chassis ground is located immediately to the left of each terminal block.
Connect the solenoid power for outputs 1-6 to JF1 normally. JF2 can be used to daisy-chain
power to other TRLYs. Alternatively, power can be wired directly to TB3 when JF1/JF2
are not used. Connect power for the special solenoid, Output 12, to connector JG1.
Jumpers JP1-12 remove the voltage monitoring from selected outputs.
Alternative Customer Power N125/24 Vdc Power

Power Wiring Return Source
P125/24 Vdc
TB3 JF1 JF2

Relay Output Terminal Board x x x x 1 1
TRLYH1C (Contact Voltage Sensing)
4 3 2 1
3 3
x
x 1 Output 01 (NC) - +
Output 01 (COM) x 2
x 3 Output 01 (NO) FU1 Out 01 FU7 JP1
Output 01 (SOL) x 4
x 5 Output 02 (NC) -
Output 02 (COM) x 6 +
x 7 Output 02 (NO)
Output 02 (SOL) x 8 FU2 Out 02 FU8 JP2
x 9 Output 03 (NC)
Powered, Output 03 (COM) x 10
Output 03 (SOL) x 11 Output 03 (NO) - +
Fused x 12
Output 04 (COM) x 14
x 13 Output 04 (NC) FU3 Out 03 FU9 JP3
Solenoids
Output 04 (SOL) 16
x 15 Output 04 (NO) - +
Form-C x
Voltage
Output 05 (COM) x 17 Output 05 (NC) FU4 Out 04 FU10
x 18 JP4 Sensing
Output 05 (SOL) x 19 Output 05 (NO)
x 20 - + Boards
Output 06 (COM) x 21 Output 06 (NC)
x 22
x 23 Output 06 (NO) FU5 Out 05 FU11 JP5
Output 06 (SOL) x 24
x - +
FU6 Out 06 FU12 JP6
Fuses Fuses
Neg,Return Pos,High
x
Output 07 (NC) JP7 Cable
x 26 Connectors
x 27 Output 07 (NO)
x 28 JA1, JR1,
Dry Output 08 (COM) 30
x 29 Output 08 (NC) JP8
x JS1, JT1
Contacts x 31 Output 08 (NO) Relays
x 32
Form-C Output 09 (COM) x 33 Output 09 (NC)
x 34 JP9
x 36
x 35 Output 09 (NO)
Output 10 (COM) x 37 Output 10 (NC)
x 38
x 39 Output 10 (NO) JP10
x 40
x 41 Output 11 (NC)
Special x 43 Output 11 (NO) JP11
x 44
Circuit, Output 12 (COM) x 45 Output 12 (NC)
x 46
Form-C, Output 12 (SOL)
x 47 Output 12 (NO) JP12
x 48
Ign. Xfmr. x
JG1 1 3
Customer Customer
Power Return
Power to Circuit 12
TRLYH1C Terminal Board Wiring

Operation
Relay drivers, fuses, and jumpers are mounted on the TRLYH1C. Relays 1-6 have a 250 V
MOV for transient suppression between the NO and power return terminals.
Relays are driven at the frame rate and have a 3.0 A rating. The rated contact-to-contact
voltage is 500 V ac for one minute. The rated coil to contact voltage is 1,500 V
ac for one minute. The typical time to operate is 10 ms. The relay outputs have a
failsafe feature that votes to de-energize the corresponding relay when a cable is
unplugged or communication with the associated I/O board is lost.
For simplex operation, a cable carries control signals and monitor feedback voltages
between the I/O board and TRLY through JA1. For TMR applications, relay control
signals are fanned into TRLY from the three I/O boards R, S, and T through plugs JR1,
JS1, and JT1. These signals are voted and the result controls the corresponding relay
driver. The 28 V power for the relay coils comes in from all three I/O boards and is
diode-shared. The following figure shows a TRLYH1C in a TMR system.

Relay Terminal Board - TRLYH1C Output 01
with Contact Voltage Sensing
NC 1
Alternate K1
TB3
Power, 20 A FU7 Com 2
1 P125/24 V dc
24 V dc or
2
125 V dc or
115 V ac or 3 NO 3
240 V ac 4 6 of these +
K1 K1 Field
circuits Snub
FU1 4
Solenoid
JF1 1 N125/24 Vdc -
Normal Power Sol
Source, pluggable 3.15 Amp
3 JP1
(7 Amp) slow-blow
JF2 Output 07
1
Power NC
3 Monitor
Daisy-Chain >14 Vdc 25
K7
>60 Vac
JA1 Com Dry
26
Contact
Monitor Select
Form-C
NO
R
K7 K7 27
I/O
Processor JP7
JR1
P28V
K#
5 of these circuits
Coil
Relay Relay
Driver
Control ID
JS1 RD
To S I/O Processor JP12 Output 12

Monitor
Voltage NC
ID
K12 45
JT1
12 of the above circuits
Com Special
To T I/O Processor
46 Circuit
NO
ID 47
K12 K12
Available for JG1 Snub
GT Ignition 1
Transformers 3
1 of these circuits Sol 48
(6 A at 120 V ac
3 A at 240 V ac)
TRLYH1C Circuits

Specifications
Item Specifications
Number of relay channels on one 12:
TRLY board 6 relays with solenoid driver voltages
5 relays with dry contacts only
1 relay with 7 A rating
Rated voltage on relays a: Nominal 125 V dc or 24 V dc
c: 3.0 A for 115/230 V ac, 50/60 Hz operation
H1C contact feedback threshold 70-145 V dc, nominal 125 V dc, threshold 45 to 65 V dc
90-132 V rms, nominal 115 V rms, 47-63 Hz, threshold 45 to 72 V ac
190-264 V rms, nominal 230 V rms, 47-63 Hz, threshold 45 to 72 V ac
H2C contact feedback threshold 16-32 V dc, nominal 24 V dc, threshold 10 to 16 V dc
Fault detection Loss of relay excitation current
NO contact voltage disagreement with command
Unplugged cable or loss of communication with I/O board; relays de-energize if
Physical

Diagnostics
Configuration
Refer to the TRLYH1C Terminal Board adjustments are made as follows:
Board Wiring figure for more
information. • Jumpers JP1 through JP12. If contact voltage sensing is required,
insert jumpers for selected relays.
• Fuses FU1 through FU12. If power is required for relays 1-6, two fuses
should be placed in each power circuit supplying those relays. For
example, FU1 and FU7 supply relay output 1.

TRLYH1D Relay Output with Solenoid Integrity Sensing
The Relay Output with Solenoid Integrity Sensing (TRLY1D) terminal board holds six
plug-in magnetic relays. The six relay circuits are Form-C contact outputs, powered and
fused to drive external solenoids. A standard 24 V dc or 125 V dc source can be used. The
board provides special feedback on each relay circuit to detect a bad external solenoid.
Sensing is applied between the NO output terminal and the SOL output terminal.
TRLY1D is similar to the standard TRLY1B board except for the following:
• There are only six relays.

• The board is designed for 24/125 V dc applications only.
• Relay circuits have a NO contact in the return side as well as the source side.
• The relays cannot be configured for dry contact use.
• Input relay coil monitoring is removed.
• The terminal board provides monitoring of field solenoid integrity.
• There is no special-use relay for driving an ignition transformer.



TRLY1D Relay Output Terminal Board
Board Revision Mark VIIS200VCRC, Mark VIe Mark VIeS Comments

VCCC IS220PDOA IS200YDOA
TRLYH1D Yes, all versions Yes, all versions No
TRLYS1D No Yes, all versions Yes, all versions Safety certified
Mark VI control systems TRLYH1D is controlled by the VCCC or VCRC board and supports simplex and TMR
applications. Cables with molded plugs connect the terminal board to the VME rack
where the I/O boards are mounted. Connector JA1 is used on simplex systems, and
connectors JR1, JS1, and JT1 are used for TMR systems.
Mark VIe / VIeS control systems TRLY1D works with the PDOA / YDOA I/O pack and supports simplex and TMR
applications. The I/O pack plugs into the DC-37 pin connectors on the terminal
board. Connector JA1 is used on simplex systems, and connectors JR1, JS1, and
JT1 are used for TMR systems.

Installation
Connect the wires for the six relay outputs directly to the TB1 terminal block on the terminal
board as shown in the figure, TRLYH1D Terminal Board Wiring. The block is held down
with two screws and has 24 terminals accepting up to #12 AWG wires. A shield terminal
strip, attached to chassis ground, is located immediately to the left of the terminal block.
Connect the solenoid power for outputs 1-6 to JF1. JF2 can be used to daisy-chain power to
other TRLYs. Alternatively, power can be wired directly to TB3 when JF1/JF2 are not used.
TRLY1D Terminal Board Wiring

Operation
The six relays have a MOV and clamp diode for transient suppression between
the NO and power return terminals. The relay outputs have a failsafe feature
that votes to de-energize the corresponding relay when a cable is unplugged or
communication with the associated I/O board is lost.
TRLY1D monitors each solenoid between the NO and SOL output terminals. When
the relay is de-energized, the circuit applies a bias of less than 8% nominal voltage
to determine if the load impedance is within an allowable band. If the impedance is
too low or high for consecutive scans, an alarm feedback is generated. The contacts
must be open for at least 1.3 seconds to get a valid reading.
110 or 125 V dc Solenoid Voltage
Announce
Yes Unknown No Unknown Yes
Solenoid Failure?
(R_NOM = 644 Ω)
Solenoid Resistance 80 Ω 153 Ω 2.2 kΩ 2.2 kΩ
24 V dc Solenoid Voltage
Announce
Yes Unknown No Unknown Yes
Solenoid Failure?
(R_NOM = 29 Ω)
Solenoid Resistance 5Ω 11 Ω 148 Ω 153 Ω

TRLY1D Solenoid Fault Announcement

For simplex operation, cables carry control signals and solenoid monitoring feedback
voltages between the I/O board and TRLY1D through JA1. For TMR applications, relay
control signals are fanned into TRLY1D from the three I/O processor boards R, S, and
T through plugs JR1, JS1, and JT1. These signals are voted and the result controls the
corresponding relay driver. Power for the relay coils comes in from all three I/O boards
and is diode-shared. The following figure shows TRLY1D in a TMR system.
TRLY1D Circuits, TMR System

Specifications
Item Specification
Number of relay channels Six relays with special customer solenoid monitoring
Rated voltage on relays Nominal 125 V dc or 24 V dc
Relay contact rating for 24 V dc voltage Current rating 10 A, resistive
Current rating 2 A, L/R = 7 ms, without suppression
Relay contact rating for 125 V dc voltage Current rating 0.5 A, resistive
Current rating 0.2 A, L/R = 7 ms, without suppression
Current rating 0.65 A, L/R = 150 ms, with suppression (MOV) across the load
Maximum response time on 25 ms typical
Maximum response time off 25 ms typical
Board size 17.8 cm by 33.0 cm (7 in by 13 in)
Fault detection Loss of solenoid voltage supply (fuse monitor)
Solenoid resistance measured to detect open and short circuits
Unplugged cable or loss of communication with I/O board (relays de-energize if
communication with associated I/O board is lost)
Physical
Diagnostics

Configuration
TRLYH1E Solid-State Relay Output

The solid-state Relay Output (TRLYH1E) terminal board is a 12-output relay board using
solid-state relays for the outputs and featuring isolated output voltage feedback on all
12 circuits. The solid-state relays allow the board to be certified for Class 1 Division 2
applications. The use of solid-state relays requires three different board types:
• TRLYH1E for 115 V ac applications

• TRLYH2E for 24 V dc applications
• TRLYH3E for 125 V dc applications
Unlike the form-C contacts provided on the mechanical relay boards,

all 12 outputs on TRLYH1E are single, NO, contacts. There is no user
solenoid power distribution on the board.



Barrier type
terminal blocks can
be unplugged from
board for
maintenance X
x JT1
x 1 MV
Relay
x 2
MV
x 4
x 3 Relay
x 6
x 5
x 8
x 7 MV
x 10
x 9
x 11 Relay
Relay
x 12
MV
x 14
x 13
x 16
x 15 MV J - Port Connections:
x 18 x 17
Relay
x 20
x 19 JS1
x 21 Plug in PDOA I/O Pack(s)
x 22 for Mark VIe system
x 24
x 23 MV
x Relay
12 Relay Outputs or
TB1
MV
MV Cables to VCCC/VCRC
Relay
Relay boards for Mark VI;
MV
MV
JA1 JR1 The number and location
Relay
depends on the level of
Relay
MV
MV Relay
Relay
Shield
bar Solid-State Output Relays
x
TRLYH1E Solid-State Relay Output Terminal Board
Mark VI control systems TRLYH#E is controlled by the VCCC or VCRC board and supports simplex and TMR
applications. Cables with molded plugs connect the terminal board to the VME rack where
the I/O boards are mounted. Connector JA1 is used on simplex systems, and connectors
JR1, JS1, and JT1 are used for TMR systems.
Mark VIe Control Systems TRLYH#E works with the PDOA I/O pack and supports simplex and TMR applications.
PDOA plugs into the DC-37 pin connectors on the terminal board. Connector JA1 is used
on simplex systems, and connectors JR1, JS1, and JT1 are used for TMR systems.

Installation
Connect the wires for the 12 solenoids directly to the I/O terminal block on the terminal
board as shown in the figure, TRLYH1E Terminal Board Wiring. The terminal block is
held down with two screws and has 24 terminals accepting up to #12 AWG wires. The dc
relays are unidirectional, so care should be taken about polarity when connecting load to
these relays. A shield terminal strip attached to chassis ground is located immediately to
the left of each terminal block. The solenoids must be powered externally by the customer.
Solid-State Relay Output Terminal Board TRLYH1E JT1
x
COM7 (NEG) MV
x 1
Relay
COM1 (NEG) x 2
MV
x 3 NO7 (POS) Relay
NO1 (POS) x 4
COM2 (NEG) x 6
x 5 COM8 (NEG)
NO2 (POS))
x 7 NO8 (POS) MV
x 8
COM3 (NEG) x 10
x 9 COM9 (NEG) Relay
Relay
11 NO9 (POS)
MV
x
NO3 (POS) x 12
x 13 COM10 (NEG) JS1 J - Port Connections:
COM4 (NEG) x 14 MV
NO4 (POS) x 16
x 15 NO10 (POS)
COM5 (NEG) x 17 COM11 (NEG) Relay Plug in PDOA I/O Pack(s)
x 18
NO5 (POS) x 19 NO11 (POS) for Mark VIe system
x 20
COM6 (NEG) x 21 COM12 (NEG) MV
x 22
NO6 (POS) x 24
x 23 NO12 (POS) or
Relay
x
Cables to VCCC/VCRC
MV
Wiring to 12 external solenoids MV
boards for Mark VI;
Relay
Relay
JA1 JR1 The number and location
MV depends on the level of
MV redundancy required.
Relay
Relay
MV
MV Relay
Relay
TRLYH1E Terminal Board Wiring

Operation
NO solid-state relays, relay drivers, and output monitoring are mounted on TRLYH1E.
During power up, relays stay de-energized while connected to any control. The relay
outputs have a failsafe feature that votes to de-energize the corresponding relay when a
cable is unplugged or communication with the associated I/O processor is lost.
For simplex operation, control signals and relay output voltage feedback signals pass
between the I/O processor and TRLY through JA1. For TMR applications, relay control
signals are fanned into TRLY from the three I/O processors R, S, and T through plugs
JR1, JS1, and JT1. These signals are voted and the result controls the corresponding
relay driver. Power for the relay drivers comes in from all three I/O processors and
is diode-shared. The following figure shows TRLYH1E in a TMR system.
Relay Terminal Board - TRLYH1E
JA1
Contact
Sensing/
Input
Sensing
R
I/O ID
Processor
Solenoid
JR1 Supply
P28V
NO
Solid-
Relay Relay Relay
ID State
Control Voting Driver
JS1 Relay
COM
Coil
To S I/O Processor TB1
ID 12 of the above circuits
JT1 GND
To T I/O Processor
ID
TRLYH1E Circuits, TMR System

Contact Voltage Feedback
In TRLYH1E, isolated feedback of voltage sensing is connected to the relay outputs. This
allows the control to observe the voltage across the relay outputs without a galvanic
connection. One contact sensing circuit is provided with each relay. This feature is similar
to the voltage sensing on TRLYH1C but with simpler hardware. The voltage sensing
circuit allows a small leakage current to pass to power the isolated circuit. The typical
leakage current is the sum of the leakage through the turned off solid-state relay and the
current through the voltage sensing circuit. The following charts indicate the typical
leakage current as a function of the applied voltage for the three board types.
TRLYH1E Typical Off-State Leakage Current-mA

RMS
25.00
Typical leakage current -
20.00
mA RMS
15.00
10.00
5.00
0.00
40 50 60 70 80 90 100 110 120 130 140
Input Voltage across contacts V RMS
TRLYH2E Typical Off-State Leakage Current
3.50
3.00
2.50
Leakage mA ..
2.00
1.50
1.00
0.50
0.00
15 16 17 18 19 20 21 22 23 24 25 26 27 28
Applied Voltage

TRLYH3E Typical Off-State Leakage Current
3.00
2.50
2.00
Leakage mA ..
1.50
1.00
0.50
0.00
60 65 70 75 80 85 90 95 100 105 110 115 120 125 130
Applied Voltage
Due to the permitted leakage current, the board may give false indications if used
in series with a low input current load, including common contact input circuits
such as those found on TBCI or STCI. To ensure correct operation, the maximum
load resistances for the three board types are as follows:
• TRLYH1E: Maximum load resistance at nominal 115 V ac is 2.5 kΩ.

• TRLYH2E: Maximum load resistance at nominal 24 V dc is 4.5 kΩ.
• TRLYH3E: Maximum load resistance at nominal 125 V dc is 25 kΩ.
Load resistance may be decreased by applying a resistor in parallel with the load so
the parallel combination satisfies the maximum resistance requirement.
Contact Voltage Rating

Solid-state relays have a finite transient voltage capability and require coordinated
voltage protection. TRLYH1E for ac applications uses a load control device that
turns off on a current zero crossing. This turn-off characteristic ensures that no
inductive energy is present in the load at turn-off time. Basic protection of the
ac relay is provided on TRLYH1E using a MOV with clamp voltage coordinated
with relay voltage rating. In addition, there is an R-C snubber circuit on the relay
output using a 56 Ω resistor in series with a 0.25 µF capacitor.
Both the TRLYH2E (for 24 V dc applications) and the TRLYH3E (for 125 V dc
applications) can interrupt currents in large inductive loads. Because a wide range of
loads may be encountered, an appropriate R-C or diode snubber circuit must be selected
for each application. The snubber should be applied at the load device using common
engineering practices. If the applied snubber does not fully control inductive switching
voltage transients, both board versions contain an active voltage clamp circuit. This
circuit activates at approximately 50-55 V dc for the H2E and at approximately 164-170 V
dc for the H3E (both values below the rating of the relay). While the clamp circuit has a
finite ability to absorb energy, it can handle the wiring inductance of a resistive load.

Specifications
Item Specification
Number of relay channels on 12 relays:
one TRLY board 115 V ac operation with TRLYH1E
24 V dc operation with TRLYH2E
125 V dc operation with TRLYH3E
Maximum operating voltage 1E:
and maximum load current 250 V rms at 47-63 Hz, 10 A at 25ºC (77 ºF) maximum
with free convection air flow de-rate current linearly to 6 A at 65ºC (149 ºF) maximum
2E:
28 V dc, 10 A dc at 40ºC (104 ºF) maximum
de-rate current linearly to 7 A dc at 65ºC (149 ºF) maximum
3E:
140 V dc, 3 A dc at 40ºC (104 ºF) maximum
de-rate current linearly to 2 A dc at 65ºC (149 ºF) maximum
Maximum off state leakage 1E: 3 mA rms
(see charts of leakage vs.
2E: 3 mA A dc at 55 V
applied voltage)
3E: 2.5 mA A dc
Max response time on 1 ms for dc relays; ½ cycle for ac relay
Max response time off 300 micro seconds for dc relays; ½ cycle for ac relay
Relay MTBF 1E: 50 years
2E: 37 years
3E: 47 years
Relay contact voltage sensing 1E: 115 V ac, 70 V ±10% ac rms
threshold 2E: 24 V dc, 15 V ±2 V dc
3E: 125 V dc, 79 V ±10% dc
Operating temperature range -30 to 65ºC (-22 to +149 ºF)
Operating humidity 5 to 95% non-condensing
Fault detection Relay current disagreement with command
Unplugged cable or loss of communication with I/O board; relays de-energize if
Physical

Diagnostics
Configuration

TRLYH1F Relay Output with TMR Contact Voting
TRLY1F and 2F do not support The Relay Output with TMR contact voting (TRLY1F) terminal board provides 12
simplex arrangements contact-voted relay outputs. The board holds 12 sealed relays in each TMR section,
for a total of 36 relays. The relay contacts from R, S, and T are combined to form a
voted Form A (NO) contact. 24/125 V dc or 115 V ac can be applied.
TRLY1F does not have power distribution. For the Mark VI and VIe control systems,
an optional power distribution board, IS200WPDFH1A, can be added so that a standard
125 V dc or 115 V ac source, or an optional 24 V dc source with individual fuses,
can be provided for field solenoid power. IS200WPDFH2A provides a single fuse in
the high side (pin 1 of J1–J4) of each power distribution circuit for ac applications
where a fuse in neutral return weire (pin 3 of J1–J4) is not desirable.
TRLY2F is same as TRLY1F except that the voted contacts form a Form B (NC)
output. Both boards can be used in Class 1 Division 2 applications.



TRLY1F Relay Output Terminal Board

Board Mark VI control Mark VIe control Mark VIeS Safety Comments
Revision IS200VCRC, VCCC IS220PDOA control
IS200YDOA
TRLYH1F Yes, all versions Yes, all versions No Normally open contacts
TRLYH2F Yes, all versions Yes, all versions No Normally closed contacts
TRLYS1F No Yes, all versions Yes, all versions Normally open contacts, safety certified
TRLYS2F No Yes, all versions Yes, all versions Normally closed contacts, safety certified
Mark VI control TRLYH1F and 2F is controlled by the VCCC, VCRC, or VGEN board and only supports TMR
systems applications. Cables with molded plugs connect JR1, JS1, and JT1 to the VME rack where the I/O
boards are mounted.
Mark VIe / VIeS TRLY1F works with PDOA / YDOA I/O pack and only supports TMR applications. Three TMR I/O
control systems packs plug into the JR1, JS1, and JT1 37-pin D-type connectors on the terminal board.
Installation
Connect the wires for the 12 solenoids directly to two I/O terminal blocks on the
terminal board as shown in the following figure, TRLY1F Terminal Board Wiring. Each
block is held down with two screws and has 24 terminals accepting up to #12 AWG
wires. A shield termination strip attached to chassis ground is located immediately
to the left side of each terminal block. Solenoid power for outputs 1-12 is available
if the WPDF daughterboard is used. Alternatively, customer power may be wired to
the terminal block. The 28 V dc power for the terminal board relay coils and logic
comes from the three I/O processors connected at JR1, JS1, and JT1.

TRLY1F Terminal Board Wiring

WPDF Power Distribution Board
If using the optional WPDF power distribution board, mount it on top of TRLY on the J1
and J2 connectors. Secure WPDF to TRLY by fastening a screw in the hole located at the
center of WPDF. Connect the power for the two sections of the board on the three-pin
connectors J1 and J4. Power can be daisy-chained out through the adjacent plugs, J2 and J3.
Note For restriction when used with the Mark VIeS Safety control system, refer to
GEH-6723, Mark VIeS Safety Control Instruction Guide.
WPDF Power Distribution Board

The solenoids must be wired as shown in the following figure. If WPDF is not
used, the customer must supply power to the solenoids.
Wiring to Solenoid using WPDF
Operation
The 28 V dc power for the terminal board relay coils and logic comes from
the three I/O processors connected at JR1, JS1, and JT1. The same relays are
used for ac voltages and dc voltages, as specified in the Specifications section.
TRLY1F and 2F use the same relays with differing circuits.
Relay drivers are mounted on the TRLY1F and drive the relays at the frame rate. The relay
outputs have a failsafe feature that votes to de-energize the corresponding relay when a
cable is unplugged or communication with the associated I/O board or I/O pack is lost.
This board only supports TMR applications. The relay control signals are routed
into TRLY1F from the three I/O processors R, S, and T through plugs JR1, JS1,
and JT1. These signals directly control the corresponding relay driver for each
TMR section R, S, and T. Power for each section’s relay coils comes in from its
own I/O processor and is not shared with the other sections.
TRLY1F features TMR contact voting. The relay contacts from R, S, and T are
combined to form a voted Form A (NO) contact. 24/125 V dc or 115 V ac can be
applied. TRLY2F is the same except that the voted contacts form a Form B (NC)
output. The following figure shows TMR voting contact circuit.

Contact voting circuit
Relay control
Driver feedback V R R S
Normally
S Open
V T R
contacts
V T S T
TRLY1F Contact Arrangement for TMR Voting
Field Solenoid Power Option

The WPDFH1A daughterboard supplies power to TRLY#F to power solenoids. WPDF
holds two power distribution circuits, which can be independently used for standard 125
V dc, 115 V ac, or 24 V dc sources. Each section consists of six fused branches that
provide power to TRLY#F. Each branch has its own voltage monitor across its secondary
fuse pair. Each voltage detector is fanned to three independent open-collector drivers for
feedback to each of the I/O processors R, S, and T. IS200WPDFH2A provides a single
fuse in the high side (pin 1 of J1–J4) of each power distribution circuit for ac applications
where a fuse in the neutral return wire (pin 3 of J1–J4) is not desirable).
WPDF should not be used without TRLY#F. Fused power flows through this board
down to the TRLY#F terminal board points. TRLY#F controls the fuse power feedback.
The following figure shows TRLY1F/WPDF solenoid power circuit.

Solenoid Power Supply WPDF

The following table lists the relationship between fuses and terminals:
Terminal Name Fuse

1 POF1 FU1
4 PRF1 FU13
5 POF2 FU2
8 PRF2 FU14
9 POF3 FU3
12 PRF3 FU15
13 POF4 FU4
16 PRF4 FU16
17 POF5 FU5
20 PRF5 FU17
21 POF6 FU6
24 PRF6 FU18
25 POF7 FU7
28 PRF7 FU19
29 POF8 FU8
32 PRF8 FU20
33 POF9 FU9
36 PRF9 FU21
37 POF10 FU10
40 PRF10 FU22
41 POF11 FU11
44 PRF11 FU23
45 POF12 FU12
48 PRF12 FU24

Specifications
Item Specification
Number of output relay channels 12
Board types H1F: NO contacts
H2F: NC contacts
Rated voltage on relays a: Nominal 100/125 V dc or 24 V dc
b: Nominal 115 V ac
Maximum load current a: 0.5/0.3 A resistive for 100/125 V dc operation
b: 5.0 A resistive for 24 V dc operation
c: 5.0 A resistive for 115 V ac

Maximum response time on 25 ms
Fault detection Coil Voltage disagreement with command
Blown fuse indication (with WPDF power daughterboard)
Unplugged cable or loss of communication with I/O board; relays
de-energize if communication with associated I/O board is lost
Physical Size 17.8 cm wide x 33.02 cm high (7.0 in x 13.0 in)
Operating Temperature -30 to 65ºC (-22 to 149 ºF)
WPDF Solenoid Power Distribution Board
Number of Power Distribution Circuits (PDC) 2: each rated 10 A, nominal 115 V ac or 125 V dc.
Number of Fused Branches 12: six for each PDC
Fuse rating 3.15 A at 25ºC (77 ºF)
2.36 A is the recommended maximum usage at 65ºC (149 ºF)

Voltage monitor, maximum response delay 60 ms typical
Voltage monitor, minimum detection voltage 16 V dc
72 V ac
Voltage monitor, max current (leakage) 3 mA
Physical
Size - TRLY#F 17.8 cm wide x 33.02 cm high (7.0 in x 13.0 in)
Size - WPDF 10.16 cm wide x 33.02 cm high (4.0 in x 13.0 in)

Diagnostics
• The voltage to each relay coil is monitored and checked against the command at the
frame rate. If there is no agreement for two consecutive checks, an alarm is latched.
• The voltage across each solenoid power supply is monitored and if it
goes below 16 V ac/dc, an alarm is created.
• If any one of the outputs goes unhealthy a composite diagnostic
• Each terminal board connector has its own ID device that is interrogated by the I/O
board. The connector ID is coded into a read-only chip containing the board serial
number, board type, revision number, and the JR1/JS1/JT1 connector location.

Configuration

SRLY Simplex Relay Output
The Simplex Relay Output (SRLY) terminal board is a simplex S-type terminal
board accepting a PDOA /YDOA I/O pack and providing 12 form C relay
output circuits through 48 customer terminals.
SRLY has the same physical size, customer terminal locations, and I/O pack mounting
as other S-type terminal boards. There will be no components higher than an attached
PDOA / YDOA I/O pack, permitting double stacking of terminal boards. Each relay
on SRLY uses an isolated contact pair as position feedback to PDOA / YDOA
SRLY has two groups:
• IS200SRLY_1 has fixed Euro-style box terminals and no ability

to accept option boards.
• IS200SRLY_2 has pluggable Euro-style box terminals and two connectors
that accept a variety of different option boards.
There are three option boards available that plug on to SRLY_2A:
• IS200WROB turns SRLY into the functional equivalent of IS200TRLY1B.

This option provides fused and sensed power distribution to the first six
relays and dedicated power to the last relay.
• IS200WROF puts a single fuse in series with each relay common
connection. Fuse voltage feedback is included.
• IS200WROG distributes power from an input connector to each relay through
a single fuse. Fuse voltage feedback is included.

Board Mark VIe Mark VIeS Comments
Revision IS220PDOA IS200YDOA
SRLYH1A Yes, all versions No Fixed terminals
SRLYH2A Yes, all versions No Pluggable terminals
SRLYH2A + WROB Yes, all versions No Pluggable terminals, six dual-fused

option powered outputs, one unfused powered
output.
SRLYH2A + WROF Yes, all versions No Pluggable terminals, one fuse in series
option with each relay common terminal.
SRLYH2A + WROG Yes, all versions No Pluggable terminals, twelve single-fused
option powered outputs.
SRLYS1A Yes, all versions Yes, all versions Fixed terminals, safety certified
SRLYS2A Yes, all versions Yes, all versions Pluggable terminals, safety certified.
SRLYS2A + WROB Yes, all versions Yes *
option
SRLYS2A + WROF Yes, all versions Yes *
option
SRLYS2A + WROG Yes, all versions Yes *
option
Note * Refer to GEH-6723, Mark VIeS Safety Control, Safety Instruction Guide for
restrictions.
Installation
SRLY and a plastic insulator mounts on a sheet metal carrier and is then mounted to a
cabinet by screws. If an option board is used, it plugs onto SRLYH2A or SRLYS2A
and is held in place by the force of the connectors. The following table identifies the
function of each terminal point as it relates to the presence of an option board.
Output Relay SRLY SRLY + WROB SRLY/WROF with SRLY/WROF without SRLY + WROG
Terminal Fuses Fuses
1 1 NC NC NC NC NC
3 NO NO NO NO NO
5 2 NC NC NC NC NC
7 NO NO NO NO NO
9 3 NC NC NC NC NC
11 NO NO NO NO NO

13 4 NC NC NC NC NC
15 NO NO NO NO NO
17 5 NC NC NC NC NC
19 NO NO NO NO NO
21 6 NC NC NC NC NC
23 NO NO NO NO NO
25 7 NC NC NC NC NC
27 NO NO NO NO NO
29 8 NC NC NC NC NC
31 NO NO NO NO NO
Output Relay SRLY SRLY + WROB SRLY/WROF with SRLY/WROF without SRLY + WROG
Terminal Fuses Fuses
33 9 NC NC NC NC NC
35 NO NO NO NO NO
39 NO NO NO NO NO
43 NO NO NO NO NO
47 NO NO NO NO NO

SRLY Terminal Board Layout

Operation
Board Groups
SRLY is available in two groups. SRLY1A comes with fixed box terminals and omits
option board connectors JW1 and JW2. SRLY2A uses pluggable type terminals
and has connectors JW1 and JW2 supporting option board connection. Electrically
SRLYH2 has the following circuit for each of the 12 relays:
SRLYH2A or SRLYS2A
NC (1)
COM (2)
NO (3)
J1
SOL (4)
fdbk
JW1
Twelve Circuits
JW2 48 Terminals
connection. SRLY is designed to support a current rating of 5 A and voltage
clearance greater than is needed for 250 V ac on all customer screw and JW1
circuits. The relay rating is the limiting item for each application.
SRLY + WROB
Option board IS200WROBH1A adds capability to SRLY2A to yield a combination
that has the same functionality as an IS200TRLY1B terminal board when used
simplex. Included are fused sensed power distribution to the first six relays and
dedicated power to the last relay. Electrically IS200SRLY2A plus IS200WROBH1
has the following circuit. IS200WROBH1 has default fuse values of 3.15 A.

SRLY2A + WROB Circuitry
Relay +Fuse -Fuse Jumper Terminals

1 FU7 FU1 JP1 1-4
2 FU8 FU2 JP2 5-8
3 FU9 FU3 JP3 9-12
4 FU10 FU4 JP4 13-16
5 FU11 FU5 JP5 17-20
6 FU12 FU6 JP6 21-24

SRLY + WROF
Option board IS200WROFH1A adds an optional fuse in series with the COM
connection for each relay by using the SOL terminal in place of COM. Isolated
voltage sensing that is not polarity sensitive is provided for each fuse. Fuse voltage
feedback is compatible with 24 V, 48 V, and 125 V dc applications as well as 120
V and 240 V ac applications. IS200WROFH1 has default fuse values of 3.15 A.
Electrically IS200SRLY2A plus IS200WROFH1 has the following circuit. Connector
JW2 and its connections to JA1 are omitted for clarity.
SRLY2A + WROF Circuitry
The normal application for this board is when it is desired that each relay have
a fuse in series and power applied from an external source. The board has a
second potential application. If the fuse is removed from a circuit, the isolated
voltage detector remains. The fourth terminal (called Fused COM above) may
now be wired to either the NC or NO terminal to provide isolated contact voltage
feedback. I/O pack firmware has a configuration option to turn off fuse blown alarm
generation for a given relay if it is being used in this fashion. The terminal table
identifies this application as making the fourth screw Vsense.

SRLY + WROG
Option board IS200WROGH1A adds fused power distribution for all twelve relays.
Isolated voltage sensing that is not polarity sensitive is provided for each fuse. Fuse
voltage feedback is compatible with 24 V, 48 V, and 125 V dc applications, as well
as 120 V and 240 V ac applications. IS200WROGH1 has default fuse values of
3.15 A. Electrically IS200SRLY2A plus IS200WROGH1 has the following circuit.
SRLY + WROG Circuitry

Specification
Item Specification
Number of relay channels on one SRLY board 12
Rated voltage on relays a: Nominal 24 V dc, 48 V dc, or 125 V dc
WROBH1 Option Board
Powered Output Circuits 6 fused, associated with relays 1-6, fed from parallel connectors JF1 and
JF2. Both sides of the power source are fused for each output.
1 unfused, associated with relay 12, fed from connector JG1
WROFH1 Option Board
Fused Output Circuits 12 fused circuits, one per relay.
WROGH1 Option Board
Powered Output Circuits 12 fused circuits, one associated with each relay. Single side fusing of the
power is associated with the power input on JF1 pin 1. Return power
path through JF1pin 3 is not fused.
Physical
Technology Surface-mount.
Temperature Operating -30 to 65ºC (-22 to +149 ºF)
Humidity Operating humidity is 5 to 95% non-condensing

Diagnostics
Terminal board connectors have their own ID device that is interrogated by the I/O pack.
The ID device is a read-only chip coded with the terminal board serial number, board
type, revision number, and plug location. When the chip is read by PDOA or YDOA
and a mismatch is encountered, a hardware incompatibility fault is created. Each of the
option boards also contains an ID device that uniquely identifies the board.
The SRLY provides diagnostic feedback to PDOA or YDOA indicating each relay position
by monitoring an isolated set of contacts on each relay. When WROB is used with SRLY
isolated voltage feedback is used to detect fuse status for the six fuse pairs on the board.
When WROF is used with SRLY isolated voltage feedback is used to monitor each fuse. If
voltage is present and the fuse is open a diagnostic alarm is generated. This alarm can be
disabled in the ToolboxST PDOA / YDOA configuration to use the feedback circuit without
the fuse. When WROG is used with SRLY, isolated voltage feedback is used to monitor
each fuse. If voltage is present and the fuse is open, a diagnostic alarm is generated.
Configuration
There are no jumpers associated with the SRLY terminal board.
There are no jumpers associated with the WROFH1 board. For each relay the inclusion
or exclusion of a series fuse is determined by the terminal point used as the relay
common. In addition for each relay the associated WROF fuse may be removed to
allow direct use of the fuse voltage sensing circuit as a voltage detector.
There are no jumpers associated with the WROGH1 board. For each relay the
corresponding fuse may be removed if the relay is to be used to provide dry contacts.

Notes

PEFV Electric Fuel Valve Gateway
Electrical Fuel Valve Gateway (PEFV)

The Electric Fuel Valve Gateway (PEFV) is an Ethernet gateway between the Mark*
VIe I/O Ethernet network and an electric fuel valve interface module. The module
communicates through the Ethernet Global Data (EGD). The fuel valve interface module
is called a Digital Valve Positioner (DVP). It is made by Woodward® Controls.
The PEFV contains a processor board common to all Mark VIe I/O packs. One of the dual
RJ45 Ethernet connectors connects to the I/O Ethernet network. The other RJ45 Ethernet
connector connects directly to the DVP. A 3-pin connector supplies power to the pack.
Engine Switches
Electric Fuel
Valve Gateway
Woodward Valve Driver

PEFV Simplified Diagram
GEH-6721L PEFV Electric Fuel Valve Gateway System Guide 13-1

Compatibility
The infrared port is not used. The Electric Fuel Valve Terminal board (TEFVH1A), in this configuration, is used to
mount the PEFV only. The connections on the board are for electronic ID only. It uses no
other connections. Visual diagnostics are provided through indicator LEDs on the PEFV.
Terminal Board TEFVH1A

Control mode Simplex-yes Dual-yes TMR-yes
• Simplex uses one I/O pack with one network connection on each pack.
• Dual uses two I/O packs with one network connections on each pack.
Note PEFV can be configured as simplex, dual, or TMR. By design, PEFV works
specifically with the Woodward Controls DVP. The DVP has three Ethernet connections
and must use all three to function properly.
Installation
¾ To install the PEFV pack
1. Securely mount the TEFVH1A terminal board.
2. Directly plug three PEFVs, for triple modular redundancy (TMR),
into the terminal board connectors.
4. Plug one Ethernet cable into the I/O Ethernet network. Connect the other
Ethernet cable to the corresponding network connector on the Woodward DVP.
The pack will operate with connections made to either port. The pack must
reboot if the connections are modified. Standard practice is to connect ENET1
to the network associated with the I/O Ethernet network.
5. Power is applied to the connector on the side of the pack. It is not necessary to
insert the connector with power removed from the cable. PEFV has inherent
6. Use the ToolboxST* application to configrue the I/O pack as necessary.

Wizard again.

Operation
Processor




Status LEDs
Processor LEDs

present
LED Status

ATTN
or module.
ATTN
every 4 sec

Electric Fuel Valve Gateway Hardware
The PEFV links the Woodward DVP to the Mark VIe through the two network
connections on the processor board. The associated terminal board provides a unique
board ID identifying PEFV to the Mark VIe system. The terminal board is not used for
any I/O connections. Data from the Mark VIe goes to the PEFV through the Ethernet
connection to the I/O Ethernet network. Next, the data is passed to the DVP through
the other Ethernet connection to the DVP. The IP addresses for these networks must
be configured correctly for the communication link to be valid.
ID Line
Power Management
Specifications
Item PEFV Specification
Transmit time Data from Mark VIe is transmitted once per frame, up to 100 times per second.
Receive time Data from DVP is received asynchronously from the Woodward DVP at a rate up to 100 times
per second. This data is transmitted to the Mark VIe synchronous to the frame at the frame
rate. The PEFV will timeout in 50 ms.
Fault detection Ethernet link ok to/from DVP
Data link ok to/from DVP
EGD Packet diagnostics
IP configuration error
Physical

Configuration
Parameter Description Selections
WGC_IP_Addr Valve Driver (DVP) IP addresses on TMR networks 192.168.128.20 (Default)
should identify defaults. Specify IP address
Note: IP address of R network given. For S and T networks, the
subnet is incremented by 1 and 2 respectively.
For example, the default R value is 192.168.128.20.
The S IP address is 192.168.129.20.
The T IP address is 192.168.130.20.
WGC_Subnet DVP network subnet mask 255.255.255.0 (Default)
Specify subnet mask.
Gateway_IP_Addr Gateway IP addresses on TMR should identify defaults (PEFV 192.168.128.1 (Default)
non-IO-net IP address). Specify IP address
Follows the same conventions as WGC_IP_Addr for the S and
T network IP addresses

Notes

PGEN Turbine Generator Monitor Module
Turbine Generator Monitor (PGEN)

The Mark* VIe Turbine-Generator Monitor (PGEN) provides the electrical interface
between one I/O Ethernet network and the TGNA turbine-generator. The pack contains a
processor board common to all Mark VIe distributed I/O packs and an acquisition board.
The pack uses 3 analog channels to monitor turbine mechanical power from voltage or
4-20 mA sensors. Each phase of generator armature current is monitored using a current
transformer input. The PGEN performs the power load unbalance (PLU) function that
was performed in the Mark VI VGEN. It does not include the power calculations (kW,
kVARS, KVA) and early valve actuation logic that was included in the VGEN.
Input to the pack is through dual RJ45 Ethernet connectors and a 3-pin power input.
The PGEN supports single Ethernet networks for simplex or TMR applications. Output
is through a DC-37 pin connector that connects directly with the associated terminal
GEH-6721L PGEN Turbine Generator Monitor Module System Guide 14-1

PWR
ATTN
LINK
TxRx
1
2
ENET1 T IONet to
LINK Controller
TxRx
Analog (power) ENET2
Inputs
ENET 1
3
2
4
2
ENET 2
IS 220PGEN
PWR
ATTN
LINK
1 TxRx
ENET1
Phase A CT 2
LINK
Current 3 CT TxRx S IONet to
4
ENET2
Controller
ENET 1
1 ENET 2
Phase B CT 2
CT IS 220PGEN
Current 3
4 PWR
ATTN
LINK
TxRx
1
ENET1 R IONet to
LINK
2
TxRx Controller
Phase C CT 3
CT
ENET2
Current 4
ENET 1
ENET 2
IS 220PGEN
IS 200 TGNA
TMR PGEN
PGEN Block Diagram
Compatibility
PGENH1A is compatible with the turbine-generator Terminal Board (TGNA).
The following table describes the compatibility:
Terminal Board TGNA

Control mode Simplex-yes Dual-no TMR-yes
• Simplex uses one I/O pack with one network connection only
• TMR uses three I/O packs with one network connection on each pack

Installation
¾ To install the PGEN pack
2. Directly plug one PGEN I/O pack for simplex or three PGEN I/O packs
for TMR into the terminal board connectors.
The bracket location should be adjusted such that there is no right angle force
Note The PGEN mounts directly to a Mark VIe terminal board. TMR-capable
terminal boards have three DC-37 pin connectors, and can also be used in simplex mode
if only one PGEN is installed. The PGEN directly supports all of these connections.
4. Plug in one Ethernet cable only. The pack operates over either port.

Wizard again.

Operation
Processor
• Local ambient temperature sensor
• Status indication LEDs
• Substantial programmable logic supporting the acquisition board
The processor board in the pack is common to all Mark VIe Ethernet
I/O packs. It contains the following:
The processor board connects to an acquisition board specific to the I/O pack
function. Upon application of input power, the soft-start circuit ramps up the
and then loads application code specific to the I/O pack type from flash memory.
The application code reads board ID information to ensure the correct matching of
application code, acquisition board, and terminal board. With a good match, the
processor attempts to establish Ethernet communications, starting with request of
a network address. The address request uses the industry standard dynamic host
The ToolboxST* configuration of the PGEN does not allow the pack to operate redundantly
from the two Ethernet inputs. The Ethernet ports on the processor auto-negotiate between
10 MB/s and 100 MB/s speed, and between half-duplex and full-duplex operation.



Status LEDs
Processor LEDs

present
LED Status

ATTN
or module.
ATTN
every 4 sec

Turbine-Generator Monitoring Hardware
The PGEN application-specific hardware consists of an analog filter acquisition board
(BPAIH3). The analog filter acquisition board provides the signal conditioning to
center and amplify the signal to improve analog-to-digital resolution.
The PGEN accepts analog input signals from the terminal board for three mechanical power
sensors and three CT currents. The analog input section consists of an analog multiplexer
block, several gain and scaling sections, and a 16-bit, analog-to-digital converter (ADC).
The three analog mechanical power inputs can be individually configured as ±5 V, ±10
V, or 4-20 mA scaled signals, depending on the input configuration. If configured
as 4-20 mA signals, the three current inputs are brought through 250 Ω burden
resistors on the terminal board. This resistance generates a 5 V signal at 20 mA. The
terminal board provides a 250 Ω burden resistor when configured for current inputs
yielding a 5 V signal at 20 mA. These analog input signals are first passed through
a passive, low pass filter network with a pole at 75.15 Hz. Voltage signal feedbacks
from calibration voltages are also sensed by the PGEN input section.
Power Load Unbalance Overspeed Control

The Power Load Unbalance (PLU) function monitors the difference between the per
unit steam turbine power based on steam pressure and the per unit generator power
based on the generator current. A PLU event occurs when turbine per unit power is
40% greater than the generator power and the difference meets both a specified rate of
change and a specified duration. When a PLU event is sensed, the steam turbine control
valves (CVs) and Intercept valves (IVs) are closed to reduce the power.
The PLU monitoring is performed by the IS220PGENH#A Iopack (PGEN) and

the IS200TGNAH#A (TGNA) terminal board. The PLU function supports either a
TMR or Simplex configuration. The Mark VIe Digital Output IOpack, IS220PDOA
and the IS200TRLYH1B (Simplex, H1F TMR) (TRLY) or terminal board controls
the steam turbine CV and IV valves. The PGEN commands the state of the relays
on the PDOA. The control of the relays in the PDOA is enhanced by a peer-to-peer
multicast packet that provides a fast communication path. The fast communication
path is in parallel with the normal pack-to-pack communication that is routed through
the signal space using the controller to transfer relay commands. The multicast
path is only used for the initiating command to the relays.
PLU events that are detected in firmware generate logic signals PLU_IV_Event to
energize IV relays and PLU_CV_Event to energize CV relays. An additional relay
communication paths is provided through PGEN signal space to allow controller
application code to control the CV and IV relays. Each relay has a configurable dropout
time so that relays can be dropped out in a staggered sequence. The actual dropout
time may vary + one IONet frame time (typically 40 msec) due to the asynchronous
interaction of the IONet communications and PGEN PLU processing. The following
Control Valve and Intercept Valve Control Logic diagram depicts this logic.

IV Permissive
Sample Logic for intercept Valves To PDOA by
Multi-cast
PLU IV Event PLU_Test_Active (*Note 1)

[C] To PDOA Intercept
Valve 1 Solenoid
Dropout
IV_Trgr(SSO) Control
Delay
RelayUse=
TstOnly
IVT_Enb(config) (*Note 2)
RelayDropTim1(config)
Ext_IV_Trgr(SSO)
Ext_IVT_Enb(config) Relay01_Tst(SSO)
RelayUse=
TstOnly
(*Note 2)
Sample Logic for Control Valves

CV Permissive
To PDOA by Multi-cast
PLU CV Event PLU_Test_Active (*Note 1)
[D] To PDOA Control
Dropout Valve 5 Solenoid
Delay Control
CV_Trgr(SSO) RelayUse=
TstOnly
(*Note 2)
CVT_Enb(config)
Relay Drop Tim5(config)
Relay05_Tst(SSO)
RelayUse=
TstOnly
(*Note 2)
Control Valve and Intercept Valve Control Logic
Note Relay activation is blocked when signal space output PLU_Test is True, so
the signal space logicals PLU_Event and PLU_IV_Event can be forced True without
activating relays. This is a test mode designed for commissioning tests if needed and
should not be used during normal operation.
Note When relays are configured as Test Only, the relay state can only be changed by
the corresponding signal space out logical RelayxTest, where x = relay number.
Power Management
The PGEN includes power management in the 28 V input circuit. The management
terminal board failure from propagating back onto the 28 V power systems.

Connectors
• A DC-37 pin connector on the underside of the I/O pack connects directly to the turbine
generator terminal board. The connector contains six input signals and an ID signal.
• A second RJ45 Ethernet connector named ENET2 on the side of the
pack can be used as an alternate to ENET1.
Note The ToolboxST configuration of the PGEN does not allow the pack to operate
from two Ethernet inputs simultaneously.

Specifications
Item Specification
Number of channels TGNA: 6 inputs total consisting of
3 pressure inputs and 3 CT current inputs
PGEN
Measurement Range Noise Suppression Accuracy
(V dc + V ac)
Analog Inputs
(channels 1-3) Pressure ±5 V dc 76 Hz single pole low pass 0.1% of full scale
±10 V dc
4-20 mA
All with 5% over range
Current Inputs
(CT channels 1-3) Current 0 to 1 A rms 507 Hz single pole low pass 0.1% of full scale
0 to 5 A rms
All with 100% over range
Input converter 16-bit analog-to-digital converter
resolution
Common mode ±5 V (±2 V CMR for the ±10 V inputs)
voltage range
Physical

Diagnostics

• Each analog or current input has hardware limit checking based on preset
(configurable) high and low levels near the end of the operating range. If this limit is
exceeded, a logic signal is set to Unhealthy in signal space, then the unhealthy signal
is forced to zero volts or mA. The signal state returns to Healthy if the signal returns
to its limits. If any signal is unhealthy, logic signal L3DIAG-PGEN is set.
• Each input has system limit checking based on configurable high and low levels. These
limits can be used to generate alarms, to enable/disable, and as latching/non-latching.
scan. Measured values are compared against expected values and are used
to confirm health of the analog to digital circuits.
I/O block SYS_OUTPUTS, input RSTDIAG can be used to direct all I/O modules to
clear from the alarm queue all diagnostics in the normal healthy state.

Configuration
Note The following information extracted from the ToolboxST application represents
a sample of the configuration information for this board. Refer to the actual
Parameter Description Sections

SystemLimits Enable or disable All system limit checking Enable, disable (default-enable)
PLU_Del_Enab Enable the PLU delay Enable, disable (default-enable)
IVT_Enab Enable the turbine control-driven IV trigger function Enable, disable (default-enable)
PLU_DiagEnab Enable voting disagreement diagnostic for PLU_Event Enable, disable (default-enable)
Ext_IVT_Enb Enable customer-driven IV trigger function Enable, disable (default-disable)
MechPwrInput Mech power through: TMR (median of 3), dual (max of DualXducer, Signal Space, TMRXducer,
first two), single Xducer, or signal space Xducer1, Xducer2
PLU_Unbal PLU unbalance threshold, percent 20 to 80 (default-40)
PLU_Delay PLU delay, seconds 0 to 0.5 (default-0)
PressRatg Reheat pressure equivalent to 100 % mech power 5 to 1500 (default-200)
(engineering units)
CurrentRatg Generator current equivalent to 100 % elect power (amps 1 to 2E6 (default-20000)
RMS)
PowerScale Scale factor that multiplies time per unit current to equate 0 to 2 (default 1.0)
generator power to per unit mechanical power
Min_MA_Input Minimum MA for healthy 4/20 mA Input 0 to 22.5 (default-4)
Max_MA_Input Maximum MA for healthy 4/20 mA Input 0 to 22.5 (default-20.40)
SystemFreq System frequency in Hz 60Hz, 50Hz (default-60Hz)
CT_Primary Generator CT primary in amperes RMS 1 to 1.2E+06 Arms (default- 20000)
CT_Secondary Generator CT secondary in amperes RMS (TGNA CT 1 to 5 Arms
input) 0 to 1 Arms (default: 0 to 5 Arms)
CVT_Enab Enable the turbine control-driven CV trigger function Enable, disable (default-Disable)

All other I/O configuration parameters are defined under the specific pack or
terminal board variables in the following sections.
PGEN Variable Definitions
Name Description Direction/Type

L3DIAG_PGEN PGEN diagnostics (Input non-voted Boolean-3 bits)
Cap1_Ready Capture buffer 1 ready for upload-not used (Input non-voted Boolean-3 bits)
Cap2_Ready Capture buffer 2 ready for upload-not used (Input non-voted Boolean-3 bits)
SysLim2analogInx Boolean set TRUE if System Limit 1 exceeded for analog input (Input Boolean)
where x = 1 to 3 x (Vgen has only 3, 4th TBD)
SysLim2AnalogInx Boolean set TRUE if system limit 2 exceeded for analog input x (Input Boolean)
where x = 1 to 3
SysLim1GenCTa Boolean set TRUE if system limit 1 exceeded for phase A (Input Boolean)
generator current
SysLim1GenCTb Boolean set TRUE if system limit 1 exceeded for phase B (Input Boolean)
generator current
SysLim1GenCTc Boolean set TRUE if system limit 1 exceeded for phase C (Input Boolean)
generator current
SysLim2GenCTa Boolean set TRUE if system limit 2 exceeded for phase A (Input Boolean)
generator current
SysLim2GenCTb Boolean set TRUE if system limit 2 exceeded for phase B (Input Boolean)
generator current
SysLim2GenCTc Boolean set TRUE if system limit 2 exceeded for phase C (Input Boolean)
generator current
PLU_Diff_Value Equal to the steam turbine per unit power based on the reheat (Input FLOAT)
pressure minus the generator per unit power (corrected by
power scale) based on generator current.
PLU_Event Boolean set TRUE if a PLU has occurred. (Input Boolean)
PLU_IV_Event Boolean set TRUE if a PLU intercept valve event has occurred. (Input Boolean)
PLU_Current Generator current (amps rms) scaled by power scale (Input Float)
SteamPressure Steam pressure (EUs) (Input Float)
CV_Permissive Boolean set TRUE to leave CV relays de-energized (Input Boolean)
IV_Permissive Boolean set TRUE to leave IV relays de-energized (Input Boolean)
Relay01Test to Solenoid 1 test (Output Boolean)
Relay12Test
PLU_Tst Boolean to command PLU test. (Output Boolean)
IV_Trgr Turbine control-driven IV trigger (Output Boolean)
Ext_IV_Trgr Customer-driven IV trigger (Output Boolean)
MechPower Mechanical power (percent) when configured through signal (Output Float)
space

IS200TGNA Variable Definitions
AnalogInputOx where x = Analog input x - Card Point Point Edit (Input FLOAT)
1 through 3
InputUse Defines analog input as either as ±10 V, ±5 V, 4-20 ±5 V ±10 V
mA or unused. 4-20 mA unused
(Default- unused)
Low_Input Defines point 1 x-axis value in volts or mA for the 0 to 10 volts or
TGNA terminal point used in calculating the gain and -10 to 20 mA
offset for the conversion to engineering units. (Default- 4.0)
High_Input Defines point 2 x-axis value in volts or mA for the 0 to 10 V or
TGNA terminal point used in calculating the gain and -10 to 20 mA
offset for the conversion to engineering units. (Default- 20.0)
Low_Value Defines point 1 Y-axis value in engineering units for ±3.402820 E+38 EUs
the TGNA terminal point used in calculating the gain (Default- 0.0)
and offset for the conversion from volts to EUs
High_Value Defines point 2 Y-axis value in engineering units for ±3.402820 E+38 EUs
the TGNA terminal point used in calculating the gain (Default- 100.0)
and offset for the conversion from volts to EUs
InputFilter Filter bandwidth in Hz (pressure inputs) 0.75 Hz, 1.5 Hz, 3 Hz, 6 Hz, 2 Hz or
unused (Default- 12Hz)
SysLim1Enabl Enable system Limit 1 fault check Enable, disable
(Default- disable)
SysLim1Latch Latch system Limit 1 fault Latch, Not Latch
(Default- Latch)
SysLim1Type System Limit 1 check type >= or <=
(Default- >=)
SysLimit1 System Limit 1 – EUs ±3.402820 E+38 EUs
(Default- 0.0)
SysLim2Enabl Enable system Limit 2 (same configuration as for Enable, disable
Limit 1) (Default- disable)
SysLim2Latch Latch system Limit 2 fault Latch, Not Latch
(Default- Latch)
SysLim2Type System Limit 2 check type >= or <=
(Default- <=)
SysLimit2 System Limit 2 – EUs ±3.402820 E+38 EUs
(Default- 0.0)
TMR_DiffLmt Difference limit for voted TMR inputs in percent 0 to 100 percent
(Default- 5)
DiagHighEnab Enable high input limit diag Enable, Disable
(Default-Enable)
DiagLowEnab Enable low input limit diag Enable, Disable
(Default-Enable)
GenCTInputOx Total generator line current x to neutral (amps rms) - Point Edit (Input FLOAT)
Card Point
where x = 1, 2, or 3
SysLim1Enabl Enable system limit 1 fault check Enable, Disable
(Default- Disable)

1 through 3
SysLim1Latch Latch system Limit 1 Fault Latch, Not Latch
(Default- Latch)
SysLim1Type System limit 1 check type >= or <=
(Default- >=)
SysLimit1 System limit 1 – EUs ±3.402820 E+38 EUs
(Default- 0.0)
SysLim2Enabl Enable system limit 2 (same configuration as for limit Enable, Disable
1) (Default- Disable)
SysLim2Latch Latch system limit 2 fault Latch, Not Latch
(Default- Latch)
SysLim2Type System limit 2 check Type >= or <=
(Default- <=)
SysLimit2 System limit 2 – EUs ±3.402820 E+38 Eus
(Default- 0.0)
TMR_DiffLmt Difference limit for voted TMR inputs in EUs ±3.402820 E+38 EUs
(Default- 100)
Relayx Solenoid x state - card point Boolean
where x = 1 through 12
RelayUse Defines relay type. CV_FASV_Type (1-4): control valve
IV_FASV_Type (5-10): intercept valve
TstOnly : test driven
Unused
Spare CV_Fas_Type(11 only)
Spare IV_Fas_Type(12 only)
(Default Relay1 – CV 1)
(Default Relay5 – IV 1)
(Default Relay11 – Spare CV)
(Default Relay12 – Spare IV)
RelayDropTim Relay dropout time - The actual dropout time can 0.0 to 5.0 seconds
vary + 1 IONet frame time (typically 40 msec) (Default Relay1 – 1.10)
due to the asynchronous interaction of the IONet (Default Relay2 –2.00)
communications and PGEN PLU processing (Default Relay3 –3.00)
(Default Relay4 – 4.00)

1 through 3
PLU Configuration
If an IS220PGEN is to connect to an IS220PDOA module to perform a coordinated PLU
Speed Control function, the two modules need to be linked in the ToolboxST configuration.
This link is configured in the text block that displays when the module is double-clicked.
The PGEN should be configured first by selecting the PLU Function Enabled check box.
After the PGEN is configured, link the PDOA to the PLU-configured PGEN by selecting
the PLU-enabled PGEN from the I/O Module Trip From drop-down list.

Additionally, the relay commands in the PGEN signal space must be connected to the
relay outputs in the PDOA signal space by using common connected variables.

TGNA Turbine-Generator
The Turbine-Generator terminal board (TGNA) acts as a signal interface board for the
Mark VIe I/O pack PGEN. In the Mark VI system, the VGEN board works with TGEN.
The TGNA provides a direct interface to three analog inputs for sensing turbine steam
pressure and three current transformer (CT) feedbacks for sensing generator current.
The three analog inputs are configurable to be 4-20 mA, ±5 V, or ±10 V inputs. There are
two jumpers for each analog input. One jumper is used to select either current (4-20 mA)
or voltage feedback. The other jumper can optionally ground the return path for the inputs.
The three CT inputs can be fed from 1 A or 5 A rated CT outputs. A separate terminal
board point is provided for the two different amp rated inputs. Configuration parameter
CT_Secondary designates which terminal board points are used.
The signals are passed on to the Mark VIe I/O packs through a 37-pin
connector. The TGNA can be used for either simplex or TMR applications.
TMR applications fan the signal to three I/O packs.
In the Mark VIe system, the PGEN I/O pack works with the TGNA. Simplex and TMR
systems are supported. In TMR systems, three PGEN packs plug into the TGNA.

Analog P28V,<R>
TGNA
Inputs TB1
P24Vn Current P28V P28V,<S>
Limiter JR1
P28V,<T>
ID
VDCn P 28V
Voltage I/P
JPx
IDCn 4-20 mA Cur I/P
Retn 250ohms
JPy Three of the above circuits
Open Ret (n= 1,2,3)(x=1,3,5) ( y=2,4,6)
JS1
CT current ID
P 28V
Inputs
Cur_A_5H 1 TB2 5A:0.0025A IA1
Cur_A_5L 2 TP2
IA2 500 ohms
Cur_A_1H 3 Phase A TP1 0.01%
Cur_A_1L 4
1A:0.0025A JT 1
ID
Cur_B_5H 1 P 28V
TB3 5A:0.0025A IB1
Cur_B_5L 2 TP4
IB2 500 ohms
Cur_B_1H 3 Phase B TP3 0.01%
Cur_B_1L 4
1A:0.0025A
Cur_C_5H 1 TB4 5A:0.0025A IC1

Cur_C_5L 2 TP6
IC2 500 ohms
Cur_C_1H 3 Phase C TP5 0.01%
Cur_C_1L 4
1A:0.0025A
TGNA Turbine-Generator Terminal Board

Installation
The TGNA accepts three analog inputs (voltage or current) and three CT inputs.
Analog input channels 1 through 3:
• Supports voltage or 4-20 mA current turbine pressure inputs

• Current-limited 24 V power supply per channel
• JP1 (3, 5) jumper for selecting current or voltage inputs
• JP2 (4, 6) configures the return as Open for true differential input or
connects return to PCOM for a 24 V return.
Connect the analog pressure sensors to the variables identified in the

table Terminal Variable Definitions.
Voltage-output sensors should use VDCx and Retx as signal connection points. Jumper
JP1 (3, 5) should be in the voltage I/P position. JP2 (4, 6) should be in differential input
position for differential feedback and in the Return to GND position for sensors supplied
with the 24 V output. Configuration parameter InputUse for the analog inputs should
be set according to the type of sensor being used, ±10 V, ±5 V, or 4-20 mA.
Current-based sensors should use IDCx and Retx as signal connection

points. Jumper JP1 (3, 5) should be in the 4-20 mA I/P position. JP2 (4,
6) should be in differential input position.
CT current Phase A, B, C
• Supports 0 to 1 A or 0 to 5 A CT secondary currents

• Separate terminal points for 0 to 1 A or 0 to 5 A CT secondary currents
Connect the secondary of the generator current CT sensors to the points identified in the
table, Terminal Point Definitions. The CT sensors should use the pair of signal points
corresponding to the secondary rating of the CT sensors, 1 A or 5 A. The configuration
parameter CT_Secondary should be set to the rating of the CT secondary.

Generator Terminal Board TGNA
JT 1
TB 1 Analog Input Jumpers
x JP 1 4-20 mA CUR I /P
x 1 P 24V(1) VOLTAGE I / P
P24 V(2) x 2
x x 3 PCOM
PCOM 4
x x 5 VDC ( 1) JP 2 RETURN TO GND
VDC (2) 6 x 7 RET ( 1) DIFFERENTIAL IN
RET (2) x 8
x x 9 IDC (1 )
IDC (2) 10 x 4-20 mA CUR I /P
RET (2) x 12 11 RET ( 1) JP3
x 13 P 24V (3) VOLTAGE I /P
NC x 14 x 15 PCOM
NC x 16 x JP4 RETURN TO GND
x 17 VDC (3 )
NC 18 x 19 DIFFERENTIAL IN
NC x 20 RET ( 3)
x x 21 IDC (3 ) JS1
NC 22 JP5 4-20 mA CUR I /P
x x 23 RET ( 3)
NC 24 VOLTAGE I /P
x
JP6 RETURN TO GND
DIFFERENTIAL IN
Cur_ A_5 H x1
Cur _A_ 5L x 2
Cur_ A_1 H x3 TB2
Cur A Test
Cur _A_ 1L x4 points JR 1
Cur_ A_5 H x 1
Cur _ A_ 5L x 2
Cur_ A_1 H x 3 TB3 Cur B Test
Cur _ A_ 1L x 4 points
Cur_ A_5 H x1
Cur _A_ 5L x 2
x3 TB4
Cur_ A_1 H Cur C Test
Cur _A_ 1L x4 points
Terminal block 1 can be

unplugged from terminal
board for maintenance TB2,
TB3, TB4 are not pluggable
TGNA Turbine-Generator Monitoring Terminal Board

CH # Point Signal Description

Analog 1 TB1-1 P24V1 +24 V output feed for pressure sensor
TB1-3 PCOM1 Power supply return for the P24 V
TB1-5 VDC1 Turbine pressure voltage, signal
TB1-7 Ret1 Turbine pressure voltage/current , return
TB1-9 IDC1 Turbine pressure 4-20 mA, signal
Phase A current TB2-1 CUR_A_5H 5 A CT current , high
TB2-2 CUR_A_5L 5 A CT current, low
TB2-3 CUR_A_1H 1 A CT current, high
TB2-4 CUR_A_1L 1 A CT current, low
Phase B current TB3-1 CUR_B_5H 5 A CT current , high
TB3-2 CUR_B_5L 5 A CT current, low
TB3-3 CUR_B_1H 1 A CT current, high
TB3-4 CUR_B_1L 1 A CT current, low
Phase C current TB4-1 CUR_C_5H 5 A CT current , high
TB4-2 CUR_C_5L 5 A CT current, low
TB4-3 CUR_C_1H 1 A CT current, high
TB4-4 CUR_C_1L 1 A CT current, low

Operation
Test points are provided for PGEN monitors generator 3-phase current and turbine mechanical power to
all CT inputs to verify the provide the PLU over-speed control for large steam turbines.
phase in the field.
Three single-phase CT inputs are provided with a normal current range of 0 to 5 A
continuous or 0 to 1 A continuous. The CTs are magnetically isolated on TGNA.
CTs connect to non-pluggable terminal blocks with captive lugs accepting up to #10
AWG wires. The total generator current is calculated from these inputs.
The three analog inputs accept 4-20 mA inputs or ±5, ±10 V dc inputs. A +24 V dc source
is available for all three circuits with individual current limits for each circuit. The 4-20
mA transducers can use the +24 V dc source from the turbine control or a self-powered
source. A jumper on TGNA selects between current and voltage inputs for each circuit. In
a TMR system, analog inputs fan out to the three I/O packs (PGEN). The 24 V dc power
to the transducers comes from all three PGEN packs, and is diode-shared on the TGNA.
Note High frequency and 50/60 Hz noise is reduced with an analog hardware filter.
Specifications
Item Specification
Inputs to TGNA and PGEN 3 one-phase generator CTs
3 analog inputs (4-20 mA, ±5, ±10 V dc)
Generator current inputs Normal current range is 0 to 5 A with over-range to 10 A or
0 to 1 A with over-range to 2 A
Nominal frequency 50/60 Hz with range of interest 45 to 66 Hz
Magnetic isolation to 1,500 V rms
Input accuracy 0.5% of full scale (5 A or 1 A) with resolution of 0.1% FS
Input burden less than 0.5 Ω per circuit
Analog inputs Current inputs: 4-20 mA
Voltage inputs: ±5 V dc or ±10 V dc
Transducers can be up to 300 m (984 ft) from the control cabinet with a two-way cable
resistance of 15 Ω.
Input burden resistor on TGNA is 250 Ω.
Jumper selection of single ended or self powered inputs
Jumper selection of voltage or current inputs
Analog Input Filter: Breaks at 72 and 500 rad/sec
Ac common mode rejection (CMR) 60 dB
Dc common mode rejection (CMR) 80 dB
Conversion accuracy Sampling type 16-bit A/D converter, 14 bit resolution
Accuracy 0.1% overall
Frame rate 720 or 600 Hz
Calculated values Total current
Mechanical power

Diagnostics
• The board provides out of sensor limits checks for each Turbine-Generator
input. The I/O processor creates a diagnostic alarm (fault) if any one of
the inputs has an out-of-range voltage/current.
interrogated by the I/O board. The ID device is a read-only chip coded with the
terminal board serial number, board type, revision number, and the JR, JS, JT
connector location. When this chip is read by the I/O processor and a mismatch
Configuration
The terminal board is configured with jumpers. For location of these jumpers, refer
to the installation diagram. The jumper choices are as follows:
• Jumpers JP1, JP3, and JP5 select either current (4-20 mA) input or voltage input
• Jumpers JP2, JP4, and JP6 select whether the return is connected to common
(Return to GND) or is left open (differential input)
The following diagrams illustrate connections for common analog inputs.
All other configuration for PGEN is done from the ToolboxST. For the location
of these jumpers, refer to the installation diagram.
Two-wire +24 V dc P24 Three-wire +24 V dc P24

Voltage input V dc Jx Voltage input V dc Jx
wiring 4-20mA T 4-20 mA
4-20 mA IDC 4-20 mA 4-20 mA IDC 4-20 mA
T
Return Return
Open Jy Open Jy
PCOM
Externally powered +24 V dc P24 Four-wire +24 V dc P24

Jx Jx
4-20 mA Voltage input V dc 5 V dc Voltage input V dc
4-20 mA IDC 4-20 mA T 4-20 mA IDC 4-20 mA

+ +
Power
Supply - -
Open Jy Max. common Open Jy
is 7.0 V dc to PCOM
PCOM
For jumpers Jx and Jy:

x = 1, 3, 5
y = 2, 4, 6

Notes

PHRA HART Enabled Analog I/O Module
HART Enabled Analog Input/Output (PHRA)

The Highway Addressable Remote Transducer (HART®) Enabled Analog
Input/Output (PHRA) pack provides the electrical interface between one or two
I/O Ethernet networks and an analog input/output terminal board. This pack
contains a processor board common to all Mark* VIe distributed I/O packs and
an acquisition board specific to the analog input function.
The pack is capable of handling up to 10 analog inputs, the first eight of which
can be configured as ±5 V inputs, or 4-20 mA current loop inputs. The last
two inputs can be configured as ±1 mA or 4-20 mA current inputs. The load
termination resistors for current loop inputs are located on the terminal board and
voltage is sensed across these resistors by the PHRA. The PHRA also includes
support for two 4-20 mA current loop outputs. In addition, in 4-20 mA mode
the PHRA can relay HART messages between HART enabled field devices and
an Asset Management System (AMS). These HART enabled field devices can
be connected through any of the inputs or outputs.
Input to the I/O pack is through dual RJ45 Ethernet connectors and a 3-pin power
input. Output is through a DC-62 pin connector that connects directly with the
associated terminal board connector. Visual diagnostics are provided through
The infrared port is not used. indicator LEDs.
PHRA
BHRA HART enabled Analog
Board Input/Output Module
BPPB
SHRA Processor board
HART Enabled
10 Analog Inputs Analog Input/Output
Two Analog Outputs Terminal Board ENET1
ENET2
(single or dual
One PHRA module Ethernet cables)
for simplex
No Dual or TMR
Control Available
PHRA Block Diagram
GEH-6721L PHRA HART Enabled Analog I/O Module System Guide 15-1
Compatibility
PHRA is compatible with the HART Enabled Analog Input Terminal Board (SHRA).
Terminal Board SHRA

Control mode Simplex-yes Dual-no TMR-no
Control mode refers to the number of I/O packs used in a signal path. Simplex
uses one I/O pack with one or two network connections.
Installation
¾ To install the PHRA pack
2. Directly plug one PHRA I/O pack into the terminal board connector.
3. Mechanically secure the pack using the threaded studs adjacent to the Ethernet
The bracket location should be adjusted such that there is no right angle force
Note The PHRA mounts directly to a Mark VIe terminal board. Simplex terminal
boards have a single DC-62 pin connector that receives the PHRA.

currently running, the download can install incorrect
Wizard again.

Operation
Processor



Status LEDs
Processor LEDs

present
LED Status

ATTN
or module.
ATTN
every 4 sec
The PHRA accepts input voltage signals from the terminal board for all 10 input
channels. The analog input section consists of an analog multiplexer block, several
gain and scaling selections, and a 16-bit analog-to-digital converter (DAC).
PHRA Analog Input Module
Terminal
M ul ti p lex o r
Board Analog to
Analog Digital
Inputs Converter
16-bit
10-Inputs
Ethernet
Processor
communications
Terminal
Board Digital to
Analog Analog
Linear
Outputs Output Converter
Drive 14-bit
2-Outputs
The inputs can be individually configured as ±5 V scale signals, depending on the input
configuration. The terminal board provides a 250 Ω burden resistor when configured
for current inputs yielding a 5 V signal at 20 mA. These analog input signals are
first passed through a second order, passive, low pass filter network with poles at
12.5 Hz and 48.3 Hz. Voltage signal feedbacks from the analog output circuits and
calibration voltages are also sensed by the PHRA analog input section.
Analog Output
The PHRA includes two 4-20 mA analog outputs capable of 18 V compliance.
A 14-bit DAC commands a current reference to the current regulator loop in the
PHRA that senses current both in the PHRA pack and on the terminal board.
Analog output status feedbacks for each output include:

• Individual current (output current sourced from within the PHRA)
• Total current (as sensed from the terminal board)

PHRA Analog Input Pack SHRA Terminal Board Max.
Load
D/A Current Noise 800
14-bit Suppr-
From Regulator/ ession ohms
Processor Power Driver
Analog
Current Fdbk Sensing Output
Total Current Sensing

Feedback
Output section of board
DC-62
Pin Connector
HART Hardware
All inputs and outputs on the BHRA are HART enabled. This means there are 12 individual
HART channels, with 10 channels for the analog inputs and two channels for the outputs.
These 12 channels are served by a pair of HART modems so that each modem is associated
with six HART channels. Inputs 1 through 5 and output 1 are multiplexed down to HART
modem A. Inputs 6 through 10 and output 2 are multiplexed down to HART modem B.
HART Modem Associations
HART channel PHRA I/O Analog Served by Modem

1 Input #1 A
2 Input #2 A
3 Input #3 A
4 Input #4 A
5 Input #5 A
6 Output #1 A
7 Input #6 B
8 Input #7 B
9 Input #8 B
10 Input #9 B
11 Input #10 B
12 Output #2 B
Refer to the Network section The number of active channels a modem is serving greatly impacts the HART data
of GEH-6721, Vol I, Mark VIe update time. If one of the six channels served by a HART modem is active, the
Control System Guide. modem is dedicated to a single field device and, under normal operating conditions,
ToolboxST data associated with this device is updated roughly once per second. If all
six channels are in use, roughly eight seconds will pass between updates.
Input
Transmit switch HART Transmit Drive Tx
IN1 Electronics
IN2 HART
Modem
IN3
Multiplexor
IN4 Rx
IN5
Output
Transmit switch
Processor
OUT1
Linear FET gate enable 2-Pole Digital to Analog
Output Drive pull-down (suicide) +
Filter Converter 14-bit
-
OUT1
Feedback
Analog IO HART Interface — Quantity 2
ID Line
Power Management

Specifications
Item Specification
Number of channels 12 channels per terminal board (10 AI, 2 AO)
Input span 4-20 mA dc, ±5 V dc, (Inputs 1-8)
4-20 mA or ±1 mA (Inputs 9-10)
Input converter resolution 16-bit analog-to-digital converter
Scan time Normal scan 5 ms (200 Hz). Note that controller frame rate is 100 Hz.
Measurement accuracy Better than 0.1% full scale over the temperature range 0 to 60°C. Typical accuracy at 25°C
is 0.007% full scale.
Noise suppression on inputs The ten circuits have a hardware filter with two poles at 12.5 Hz and 48.3 Hz. A software
filter, using a two-pole, low-pass filter, is configurable for: 0, .75, 1.5 Hz, 3 Hz, 6 Hz, 12 Hz
Dc common mode rejection 80 dB with -5 to +7 peak V common mode voltage
Common mode voltage range ±5 V
Output converter 14-bit D/A converter with 0.5% accuracy
Output load 800 Ω for 4-20 mA output
Physical
Diagnostics



Configuration

Configuration
System Limits Enable or disable system limits Enable, disable
Min_ MA_Input Select minimum current for healthy 4-20 mA input 0 to 21 mA

Max_ MA_Input Select maximum current for healthy 4-20 mA input 0 to 21 mA
AMS_Msg_Priority AMS messages have priority over controlled Enable, Disabled
messages,
AMS_Msgs_Only AMS messages only, do not send any control Enable, Disabled
messages. Generates alarm 160 when enabled.
AMS_Mux_Scans_Permited Allow AMS scan commands for Hart message 1 Enable, Disable
and 2. Hart message 3 is always allowed
Max_MA_HART_Output Minimum current sent to a HART enabled port. 0-22.5
HART COMM will not be possible during offline
modes if value is set less than 4 mA
:IS200SHRA Terminal board connected to PHRA Connected, not connected
AnalogIn1-10 First of 10 Analog Inputs – board point (Input FLOAT)
Input Type Current or voltage input type Unused, 4-20 mA, ±5 V
Low_Value Value of input in engineering units at low end of -3.4082 e + 038 to 3.4028 e + 038
scale
High_Value Value of input in engineering units at high end of -3.4082 e + 038 to 3.4028 e + 038
scale
Input _Filter Bandwidth of input signal filter Unused, 0.75, 1.5 Hz, 3 Hz, 6 Hz, 12 Hz
Hart_Enable Allow the Hart Protocol on this IO point. This must Enable, Disable
be set to true if Hart messages are needed from
this field device
Hart_Ctrl Number of variables to read from the device. Set 0-5
to zero if not used.
Hart_ExStatus Number of extended status bytes to read from the 0-26
device. Set to zero if not needed for control.
Hart_MfgID Hart field device’s manufacturers code. A 0-255
diagnostic alarm is sent if the field device ID differs
from this value and the value is non-zero. This
value can be uploaded from the PHRA if the field
device is connected. (Right-click on device name
and select Update HART IDS)
Hart_DevType Hart Field Device – Type of device. (See 0-255
Hart_MfgID)
Hart_DevID Hart Field Device – Device ID. (See Hart_MfgID) 0-116777215
Sys Lim 1 Type Input fault type Greater than or equal Less than or
equal
Sys Lim 2 Type Input fault type Greater than or equal. Less than or
equal
AnalogOut1-2 First of two analog outputs - board point Point edit (Output FLOAT)
Output_MA Type of output current, mA selection Unused, 0-20 mA
Hold Last Value
Output_Value
Low_Value Output in engineering units at low mA -3.4082 e + 038 to 3.4028 e + 038
High_Value Output value in engineering units at high mA -3.4082 e + 038 to 3.4028 e + 038
D/A Err Limit Difference between D/A reference and output, in % 0 to 100 %
Hart_Enable Allow the Hart Protocol on this IO point. This must Enable, Disable
be set to true if Hart messages are needed from
this field device
Hart_Ctrl Number of variables to read from the device. Set 0-5
to zero if not needed for control.
Hart_ExStatus Number of extended status bytes to read from the 0-26
device. Set to zero if not needed for control.
Update HART IDS Hart field device’s manufacturers code. A 0-255
diagnostic alarm is sent if the field device ID differs
from this value and the value is non-zero. This
value can be uploaded from the PHRA if the field
device is connected.
Hart_DevType Hart Field Device – Type of device. (See 0-255
Hart_MfgID)
Hart_DevID Hart Field Device – Device ID. (See Hart_MfgID) 0-116777215

Board Points (Signals) Description - Point Edit (Enter Signal Connection) Direction Type
L3DIAG_PHRA Board diagnostic Input BIT
LINK_OK_PHRA Link diagnostic input Input BIT
ATTN_PHRA Module diagnostic Input BIT
PS18V_PHRA_R I/O 18 V power supply indication Input BIT
PS28V_PHRA_R I/O 28 V power supply indication Input BIT
MuxHealth1 Health bit for PHRA Hart multiplexer Input BIT
: : Input BIT
: : Input BIT
Out1MA Feedback, Total output current, mA Input FLOAT
Out2MA Feedback, Total output current, mA Input FLOAT
Hart Signal Definitions
Each Hart field device has a set of HART signals that are read from the field
device. These signals are prefixed with either HIx_ or HOx_ where x is 1-10
for input channels and 1-2 for output channels.
Signal Type Description

Hxx_CommCnt Integer Number of times the CommStat signal was not zero after a HART message
Hxx_CommStat Bit encoded integer Hart Communication status
Bit 1 – RX buffer overflow
Bit 3 – Checksum error
Bit 4 – Framing error
Bit 5 – Overrun error
Bit 6 – Parity error
Hxx_DevCnt Integer Number of times the DevStat signal was not zero after a HART message.
Hxx_DevStat Bit encoded integer Field Device Status: bits 0-7

Bit 0 – Primary variable out of limits
Bit 1 – Non primary var out of limits
Bit 2 – Analog output saturated
Bit 3 – Analog output current fixed
Bit 4 – More status available (ExStat)
Bit 5 – Cold start
Bit 6 – Configuration changed
Bit 7 – Field device malfunction
Command response byte: bits 8-15
2: Invalid selection requested
3: Passed parameter too large
4: Passed parameter too small
5: Too few bytes received
6: Device specific device error
7: In write protect mode
8-15: Device specific
16: Access restricted
32: Device is busy
64: Command not implemented
Hxx_DevRev Integer Field Device - Device revision code as read from the device.
Hxx_HwSwRev Integer Byte 0 - Field device software revision
Byte 1 - Field device hardware revision
Hxx_mA Float Field Parm 1 – current reading of the primary signal
Hxx_PV Float Field Device Specific Control Parm 2 - Primary field device value
Hxx_SV Float Field Device Specific Control Parm 3 - Secondary value
Hxx_TV Float Field Device Specific Control Parm 4 -Third value
Hxx_FV Float Field Device Specific Control Parm 5 -Fourth value

Extended Status Bits
The extended status bits are device-specific, and can be interrogated by using an
AMS system. In general, the status bits are grouped as follows:
Bytes 0-5: Device specific status
Bytes 6-7: Operational modes
Bytes 8-10: Analog output saturation
Bytes 11-13: Analog output current fixed
Bytes 14-26: Device-specific
If needed, contact an authorized Each field device supports a specific number of control parameters and extended status
GE Representative for the bits. Refer to the Field Device documentation to determine the correct number and
appropriate Field Device configure the ToolboxST application accordingly. A diagnostic alarm message will be
documentation. generated if the Field Device and ToolboxST configuration do not match.
Hxx_ExStat_1 Bit Encoded Extended Status Bytes 1-4

SHRA HART Enabled Analog Input/Output
SHRA is not compatible with The Highway Addressable Remote Transducer (HART®) Enabled Analog Input/Output
Mark VI control systems (SHRA) terminal board is a compact analog input terminal board that accepts 10 analog
because the 62-pin connector inputs and two analog outputs, and connects to the PHRA or YHRA pack. It allows HART
of the board does not match messages to pass between the PHRA and a HART enabled field device. The 10 analog
the 37-pin D-type connector inputs accommodate two-wire, three-wire, four-wire, or externally powered transmitters.
of the Mark VI control. The two analog outputs are 4-20 mA. Only a simplex version of the board is available.
High-density Euro-block type terminal blocks are used. An on-board ID chip identifies
the board to the PHRA or YHRA for system diagnostic purposes.
Control System SHRA Functionality

Mark VIe control PHRA I/O pack works with the SHRA. The I/O pack plugs into
the D-type connector and communicates with the controller
over Ethernet. Only simplex systems are supported. All
revisions of SHRA are compatible with all PHRAs.
Mark VIeS control Board revisions SHRAS1A and SHRAS2A are safety certified.
Board Mark VIe Mark VIeS Comments

Revision IS220PHRA IS200YHRA
SHRAH1A Yes, all versions No Fixed terminals
SHRAH2A Yes, all versions No Pluggable terminals
SHRAS1A Yes, all versions Yes, all versions Fixed terminals, safety certified
SHRAS2A Yes, all versions Yes, all versions Pluggable terminals, safety
certified.

Installation
The SHRA plus a plastic insulator mounts on a sheet metal carrier that then
mounts on a DIN-rail. Optionally, the SHRA plus insulator mounts on a sheet
• SHRA1A has a permanently mounted terminal block with 48 terminals.

• SHRA2A has a right angle header accepting a range of commercially
available pluggable terminal blocks, with 48 terminals.
Typically #18 AWG wires (shielded twisted-pair) are used. I/O cable shield
termination is provided adjacent to the terminal blocks.
The following types of analog inputs/outputs can be used:

• Analog input, voltage ±5 V dc
Wiring, jumper positions, and cable connections are shown on the following figure.
SHRA Analog Input Terminal Board
E1
Jumpers Circuit Screw Connections Screw Connections Jumpers
Vdc/20mA Open/Return TB1 62-pin D shell
1 Input 1 (24V) JP1A JP1B
JP1A JP1B Input 1 (20mA) 2 latching fasteners
Input 1 3 Input 1 (Vdc)
Input 1 (Return) 4
JP2A JP2B 5 Input 2 (24V)
Input 2 Input 2 (20mA) 6 JP2A JP2B JA1
7 Input 2 (Vdc)
Input 2 (Return) 8
Input 3 Input 3 (20mA) 10
11 Input 3 (Vdc) JP3A JP3B
Input 3 (Return) 12
15 Input 4 (Vdc) JP4B
Input 4 (Return) 16 JP4A
Input 5 (Return) 20 19 Input 5 (Vdc)
21 Input 6 (24V) JP5A JP5B
JP6A JP6B Input 6 (20mA) 22
Input 6 (Return) 24
JP7A JP7B Input 7 (20mA) 26 25 Input 7 (24V) JP6A JP6B
Input 7 (Return) 28
Input 8 (20mA) 30 JP7B
20mA/1mA Input 8 31 Input 8 (Vdc) JP7A
Input 8 (Return) 32
JP9A JP9B Input 9 (20mA) 33 Input 9 (24V)
Input 9 34
Input 9 (Return) 35 Input 9 (1mA) JP8A JP8B
36 Plug in
JP10A JP10B 37 Input 10(24V)
Input 10 Input 10(20mA) 38
39 Input 10(1mA) Pack
Input 10(Return) 40 JP9A JP9B
41 PCOM
PCOM 42 43 PCOM
PCOM 44
No jumper Output 1 45 Output 1 (Signal) JP10A JP10B
Output 2 (Return) 47 Output 2 (Signal)
No jumper Output 2 48
PCOM
E2
Chassis ground

Voltage input V dc JP#A 4-20 mA Voltage input V dc JP#A
wiring 4-20mA T
4-20 mA 20 mA 4-20 mA 20 mA
T
Return Return
Open JP#B Open JP#B
PCOM

transmitter wiring transmitter wiring JP#A
4-20 mA Voltage input V dc JP#A 5 V dc Voltage input V dc
4-20 mA 20 mA T 4-20 mA 20 mA
+ +
Power
Supply - -
Open JP#B Max. common Open JP#B
is 7.0 V dc to PCOM
PCOM
SHRA Wiring, Cabling, and Jumper Positions

Operation
On the terminal board, 24 V dc power is available on the terminal board for
all the transmitters (transducers). There is a choice of current or voltage inputs
using jumpers. HART communication is only possible with the inputs set as
4-20 mA inputs, it will not take place on an input set as ±5 V dc or ±1 mA. The
two analog output circuits are 4-20 mA. There is only one cable connection, so
the terminal board cannot be used for TMR applications.
The following table displays the analog input/output capacity of the SHRA terminal board.

8 ±5 V dc, or 4-20 mA 2 4-20 mA
2 4-20 mA, or ±1 mA
SHRA Terminal Board

Controller
8 circuits per terminal
board
Noise
Mark VI powered suppression
+24 V dc 1 P28V
Current Limit
Voltage input 3 Vdc JP1A
T N
(± 5,10 V dc)
4-20 mA 2 S 20 ma
250 ohms
Return 4
JP1B I/O Pack
Open Return
41 PCOM
42
43 PCOM
44
2 circuits per terminal A/D D/A
board
P28V
+24 V dc 33 Current Limit
Excitation
±1 mA 35 1 ma JP9A JPA 1
N
4-20 mA 34 S 20 mA
250
5k ohms
Return 36 ohm
JP9B
Open Return
PCOM Current
Regulator/
Two output circuits Power
Supply
Circuits are 4-20
mA only
Signal 45
N
46 S
Return
SCOM ID
SHRA Terminal Board, and PHRA / YHRA I/O Packs
Specifications
Item Specification
Maximum lead resistance to 15 Ω maximum two-way cable resistance, cable length up to 300 m (984 ft), 24 V outputs
transmitters provide 21 mA for each connection
Load on output currents 800 Ω burden for 4-20 mA output with PHRA or YHRA pack
Physical
Diagnostics
Configuration
Configuration of the terminal board is by means of jumpers. For location of these
jumpers refer to the installation diagram. The jumper choices are as follows:
• Jumpers JP1A through JP8A select either current input or voltage input
• Jumpers JP1B through JP8B select whether the return is connected
to common or is left open
• Jumpers JP9A and JP10A select either 1 mA or 20 mA input current
• Jumpers JP9B and JP10B select whether the return is connected
to common or is left open
All other configuration is for the PHRA or YHRA, and is done from
the ToolboxST application.

PPRA Emergency Turbine Protection
Emergency Turbine Protection (PPRA)

The Emergency Turbine Protection (PPRA) I/O packs and associated TREA terminal
board provide an independent backup overspeed protection system. They also provide
an independent watchdog function for the primary control and isolated trip contact
inputs. A protection system consists of three triple modular redundant (TMR) PPRA I/O
packs mounted to a TREA terminal board with the WREA option board included.
PPRA is a derivative of the standard Mark VIe PPRO Emergency Turbine Protection
I/O pack. It adds hardware and uses altered firmware to support six speed inputs in
applications where dual speed sensors per shaft are fanned to three protection I/O packs.
The majority of the configuration, variables, and behavior of the PPRA are identical to
those found in the PPRO.
PPRA is specific to the TREA terminal board equipped with the WREA option board.
PPRA does not operate in other configurations that are supported by PPRO. PPRA also
has an Ethernet connection for IONet communications with the control modules.
The Mark VIe control is designed with a primary and backup trip protection systems that
interact at the trip terminal board level. Primary protection is provided with the Turbine
PROTECTION I/O Primary I/O pack (PTUR) operating a primary trip board (typically TRPA) when paired
PWR with PPRA/TREA. Backup protection is provided with PPRA mounted on a TREA
RUN
ATTN
terminal board.
ESTP
PPRA accepts six speed signals (configured as three sets of speed pairs) for firmware
LINK ENET overspeed, acceleration, deceleration, and a hardware implemented overspeed
OSPD
TxRx
1 protection. It monitors the operation of the primary control. PPRA monitors the status
WDOG and operation of the TREA trip board through a comprehensive set of feedback signals.
If a problem is detected, PPRA will trip the backup trip relays on the TREA board and
LINK ENET activate a trip on the primary control. PPRA is fully independent of and unaffected by
TxRx
2 the primary control operation.
IR PORT
IS220PPRAH1A
The infrared port is not used.
GEH-6721L PPRA Emergency Turbine Protection System Guide 16-1

Compatibility
Refer
Refer to
to GEI-100709,
GEI-100709, PPRA is available in a IEC 61508 certified version for use in IEC 61511 certified safety
PPRAS1A
PPRAS1A Emergency Turbine
Turbine Protection loops. PPRAS1A with TREAS1A and WREAS1A are the certified versions of the PPRA
Protection
Safety GuideSafety Instruction
for proper safety module. PPRA mounts directly on TREA, and with TREA it is required to have the
Guide for proper
loop operation andsafety
restrictions. WREA option board mounted on the PPRA application specific circuit board Option
loop operation and restrictions. Header connector. PPRA mounted on TREA with WREA will only function correctly
with three PPRA I/O packs. Single and dual pack operation is not possible.
TREA
PPRA
Control
DC-62
module
JZ1
Trip relays,
PPRA
Estop,
Overspeed Control
module
DC-62
JY1
PPRA
WREA
Control
module
DC-62
JX1
Three PPRAs with TREA and WREA
Although PPRAH1A I/O packs can be mounted

on TREAS1A terminal boards, only PPRAS1A I/O
packs mounted on TREAS1A terminal boards can be
configured for SIL applications.
Attention
In systems with a single controller, the controller R network should be connected

to the PPRA on the JX1 connector, the S network should be connected to PPRA on
the JY1 connector, and the T network should be connected to the PPRA on the JZ1
connector. All three networks are coming from the single controller.
In systems with dual controllers, the controller R network should be connected to the PPRA
on the JX1 connector, the S network should be connected to PPRA on the JY1 connector,
and both the R and S networks should be connected to the PPRA on the JZ1 connector.
In systems with three controllers, the R network should be connected to the PPRA on
the JX1 connector, the S network should be connected to PPRA on the JY1 connector,
and the T network should be connected to the PPRA on the JZ1 connector.

Note PPRA applications do not support dual network connections for all three PPRAs.
In a redundant system there is no additional system reliability gained by adding network
connections to the first two PPRAs with dual controllers or any of the three PPRAs
with TMR controllers.
Installation
The PPRA mounts directly to a Mark VIe TREA terminal board. The
installation steps are as follows:
¾ To install the PPRA I/O pack

1. Securely mount the TREA terminal board.
2. Directly plug three PPRA I/O packs into the TREA.
3. Slide the threaded posts on PPRA, located on each side of the Ethernet ports, into
the slots on the terminal board mounting-bracket. Adjust the bracket location so the
DC-62 pin connector on PPRA and the terminal board fit together securely. Tighten
the mounting bracket. The adjustment should only be required once in the life of the
product. Securely tighten the nuts on the threaded posts locking PPRA in place.
4. Plug in one or two Ethernet cables depending on the system configuration. PPRA is
not sensitive to Ethernet connections and selects the proper operation over either port.
5. Apply power by plugging in the power connector on the side of the module. The I/O
module has inherent soft-start capability that controls current levels upon application.
6. Use the ToolboxST* application to configure the module as necessary.

Wizard again.

Operation
Processor




Status LEDs
Processor LEDs

present.
Yellow TxRx Provided for each Ethernet port to indicate when the pack is transmitting or
receiving data over the port.
Red / Green ATTN Shows pack status
LED Status

Red LED out There are no detectable problems with the pack. All
ATTN
LED solid on A critical fault is present that prevents the pack from operating. 3.04 or earlier
There could be hardware failures on the processor or acquisition
boards, or there is not any application code loaded.
4 Hz 50% An alarm condition is present in the pack. These alarms include:
wrong pack / terminal board combination, terminal board is
missing, or errors in loading the application code.
1.5 Hz 50% The pack is not online
0.5 Hz 50% Flashing to draw attention to the pack. This is used during factory
testing.
ATTN
0.5 Hz 50% Application not loaded (pack)
Green Solid BIOS (at power on) - if it remains in this state, the pack is dead.
ATTN Older packs may not have the ability to display the green LED at
power on.
1 Hz 50% I/O pack in WAIT or STANDBY
every 4 sec

Six additional LEDs located on the left side of the faceplate are used for trip
status. All six LEDs stay off until all hardware application is complete. The
LEDs indicate trip status of the PPRA as follows:
RUN is green any time the I/O pack has energized the emergency trip relays. RUN turns
red any time the I/O pack has removed power from the emergency trip relays, voting to trip.
ESTP is green when the ESTOP input (if applicable) is in the run state. ESTP turns
red any time ESTOP is invoked to prevent pick up of the emergency trip relays. If the
chosen trip terminal board doesn't support ESTOP then the LED defaults to green.
OSPD turns red any time the I/O pack votes to trip in response to a detected
overspeed condition on any of the three speed inputs. OSPD is green when
an overspeed condition is not present or latched.
WDOG turns red any time a controller WDOG trip status is active. WDOG turns
green to indicate that controller WDOG trip status has been cleared.
The SIL and KREA LEDs and SIL is green when configured for SIL 2 or SIL 3 safety functionality. When
only labeled on the PPRAS1A, configured for SIL 3 if an internal fault is detected, it turns red. PPRAS1A with
but are also present on the TREAS1A and WREAS1A are required for SIL functionality.
H1A version.
KREA is green when power is detected on the krea submodule in the I/O pack.
During normal PPRA operation, all six application LEDs display green. An additional
feature, rotating LEDs, can be configured for the PPRA. Using this feature, only one LED is
turned on at a time and walked up and down the six LEDs creating a synchronized motion.
The walking is regulated by the controller IONet and synchronized across a set of three I/O
packs. This provides a quick visual indication of the system time synchronization status.

The PPRA I/O pack has an internal application specific circuit board that contains the
hardware needed for the emergency trip function. The application board connects between
the processor and the TREA terminal board and is common between PPRA and PPRO I/O
packs. The application board has an option card header that connects to a PPRA-specific
option card. The following diagram shows the functions of the application board.
PPRA Application Specific Circuit Board
In the PPRA not all of the signal conditioning is used. The option card connected
to the internal header adds support for three additional pulse rate input channels
and support for the speed pulse rate repeater outputs.
All boards within the pack contain electronic ID parts that are read during power
application. A similar part located with each terminal board connector allows the
processor to confirm correct matching of the I/O pack to the terminal board and
to report board revision status to the system level control.
The pack includes power management in the 28 V input circuit. The management
function provides a soft-start feature to control current inrush during power application.
After power is applied, the circuit provides a fast current limit function to prevent
a pack or terminal board failure from causing problems on the 28 V power. When
power is present and working properly the green PWR LED will light. If the current
limit function operates, the LED will be out until the problem is cleared.

Connectors
A DC-62 pin connector on the underside of the PPRA pack connects directly
to the terminal board. The connector contains the signals needed to sense
inputs and operate a trip terminal board.
An RJ45 Ethernet connector named ENET1 on the side of the pack is

the primary IONET-EGD connection.
A second RJ45 Ethernet connector named ENET2 on the side of the pack is the
redundant or IONET-EGD connection used on dual network configurations.
A 3-pin power connector on the side of the pack is for 28 V dc power

for the pack and terminal board.
Note The TREA trip terminal board plus WREA features contact trip inputs. The
power for those contacts is provided through a separate terminal board connector, not
from the 28 V dc power source.
Protective Functions
The PPRA performs the following protective functions in a mix of hardware,
programmable logic, and firmware. In the following diagram, standard
symbols for time delay contacts have been used:
Normally Open Normally Closed Normally Open Normally Closed

Time Delay on Close Time Delay on Open Time Delay on Open Time Delay on Close
In the following diagrams, a standard has been used to indicate signal origin and flow.
• Signal names that end with (SS) are created within PPRA and the data
flow is out to the controller through signal space.
• Signal names that end with SS are created in the controller and the data
flow is into PPRA through signal space.
• Signal names that end with (IO) are created within PPRA and the
data flow is out to the hardware.
• Signal names that end with IO indicate the signal is a hardware input into PPRA.
• Signal names that end with anything containing CFG are part of the PPRA
configuration. In this case an attempt has been made to indicate what area
of the PPRA configuration contains the variable.
• When J3 is referenced in a CFG, it refers to the connection point for the trip
relay board, TREA, and the corresponding configuration values.
• The combination IO (SS) indicates a signal that comes from the hardware inputs
to PPRA, and is then sent out to the controller as part of signal space.
If there is no special ending on a signal name, then the signal is used internal to PPRA and
is not part of the hardware or signal-space data movement. This signal is not available or
visible to applications, but it is needed to adequately describe the packs operation.

Direct/Conditional Discrete Input Trip
The contact inputs include an 8 PPRA supports the four isolated discrete contact input trip signals provided on the
ms contact de-bounce filter to TREA+WREA board. In the following figure, the direct / conditional determination
protect against false trips. is implemented in firmware while Contact # and L5Cont #_Trip are in hardware
logic. When configured for direct trip, the firmware is not in the trip path. When
configured for conditional trip, the firmware determines the communication
health (shown as network_keepalive) and populates the programmable logic
with the conditional signal from signal space. If the controller communication
is lost, the default will permit any conditional trip.
A
Network_keepalive A>=B
B L3SS_Comm, (SS)
3
Trip#_Inhbt, SS L3SS_Comm, (SS) Inhbt#_Fdbk, (SS)

A
Trip_Mode, CFG (J3, Contact#) A=B
B Cont#_TrEnab,(SS)
Direct, CNST
A
A=B
B
Conditional, CNST Trip#_EnCon,(SS)
Contact#, (IO) Cont#_TrEnab

L5Cont#_Trip, (SS)
CONTACT#
TRIP
Trip#_EnCon Inhbt#_Fdbk, SS
L5Cont#_Trip, (SS) L86MR, SS
Note that the above contact circuit is duplicated four times. Replace the symbol # with the
numbers 1-4 to obtain the correct signal name. Signals names without # in them appear only
once for all four circuits (L3SS_Comm, L86MR).
PPRA Contact Input Trips
The resulting contact trip signals are combined into a single contact
trip summary, L5Cont_Trip.
L5Cont1_Trip (SS) L5Cont_Trip
L5Cont2_Trip (SS)
L5Cont3_Trip (SS)
L5Cont4_Trip (SS)
Contact Input Trip Signal Concentration

Trip Input
PPRA monitors a trip input signal that is present on the TREA board and uses it to
cross trip the main control in the event the trip input is activated. It is also used within
the pack logic as part of the trip relay output command. The relays are not required to
close if the trip input signal is present. The main control counterpart is also present. If
the main control votes to trip, it can also cross-trip the corresponding PPRA.
HwTripin, IO J3 = TREA L86 MR, SS TRIPENAB, CFG L5 TRIPIN, ( SS)

Note: There are several inversions in the hardware signal path, but the end result is that TRIP
TRIPINFdbk is only a 1 when the Trip input is energized. In other words 1 = OK.
Contact Input Trip Input
Speed Input High Select

PPRA speed inputs are expected to be in pairs on each shaft with up to three shafts
possible (other combinations of speed inputs are not permitted). The following
table shows the TREA input screw pairs for the primary (PulseRate_A) and
secondary (PulseRate_B) speed signals, signal space (SS).
TREA Input Screw Pair (TB#) Speed Variable High-selected value

PR1H_X (43) – PR1L_X (44) PulseRate1A signal space (SS) PulseRate1 (SS) (Shaft 1)
PR4H (25) – PR4L (26) PulseRate1B (SS)
PR2H_X (45) – PR2L_X (46) PulseRate2A (SS) PulseRate2 (SS) (Shaft 1)
PR3H_X (47) – PR3L_X (48) PulseRate3A (SS) PulseRate3 (SS) (Shaft 1)
Configuration of the speed inputs is done at the PulseRate1-3 level. PPRA then applies
the PulseRate1 configuration values to both PulseRate1A and PulseRate1B. This ensures
that the two inputs that go through a high select are configured the same.
Paired speed inputs should be the same value during normal operation. Protection for
excessive difference between the two inputs is provided. The difference is calculated and
compared to a configurable threshold, Dual_DiffLimit (default 25 rpm). If the difference
exceeds the threshold a diagnostic alarm is created, Dual speed sensors mismatch.
Shaft Speed High Select, Difference Alarm

PulseRate1A, IO (SS)
A
PulseRate1B, |A-B| A Latched Alarm-

IO (SS) Dual speed sensor mismatch
B Dual_DiffLimit1, A>B
CFG (PulseRate1)
B
A
High PulseRate1, IO (SS)
Select
B

The high select diagram displays the overspeed names used for the first of three pulse rate
inputs. The same figure is repeated for PulseRate2 and 3. For all variables where the
number 1 displays, simply substitute a 2 or 3 for the 1 to get the signal name.
Note Speed inputs are sensitive to the mV level. To avoid speed difference diagnostics,
unused speed input screw pairs should be electrically tied together.
Overspeed Trip
PPRA performs firmware overspeed protection on the three values that come out
of the high speed select. While PPRA documentation follows the established
standard of calling these three inputs HP, IP, and LP the three inputs are
free to be applied as needed in a system design.

OS1_Setpoint , SS
RPM A |A|
A
A-B A OS1_SP_CfgEr
A>B
OS_Setpoint, CFG (J5, PulseRate1)
B
RPM
1 RPM
B
System Alarm, if the two setpoint
do not agree
A
MIN
OS_Stpt_PR1 OS_Setpoint_PR1
A A
zero
MULT A A+B
0.04
B MIN B
OS_Tst_Delta, CFG (J5, PulseRate1)
B
RPM
OfflineOS1tst, SS
OnlineOS1
PulseRate1, IO
A
OS1
A>=B
OS_Setpoint_PR1
B
OS1_Trip
OS1
Overspeed
Trip
OS1_Trip L86MR, SS
Frame Rate
PulseRate1, IO
A -0 A
|A-B| A
Z
Speed1_Diff
Speed1, SS B OS_Diff, CFG (%) A>B
-1 B (A & B & C)
------------------------ * RatedRPM_TA, CFG (RPM) Z
100 B
-2 C
Z
SpeedDifEn, Card CFG
Speed1_Diff SpeedDifTrip
Enable
Overspeed
Difference Trip
SpeedDifTrip L86MR, SS
Speed1_Diff
TDPU
60 Sec
Firmware Overspeed Trip, HP Shaft

Firmware Overspeed Trip functions include:
• Fault on overspeed threshold match failure between config and

signal space values when speed is zero
• Pick the lower threshold from config or signal space
• Provide a mechanism to zero the threshold for online overspeed test
• Provide a mechanism to modify the threshold for offline overspeed test,
bounded to limit increases to the threshold to 104%
Note Use a negative OS_Tst_Delta value to reduce the threshold to conduct tests.
• Compare the threshold to the calculated speed and latch overspeed
The firmware overspeed diagram displays the overspeed names used for the first of three
pulse rate inputs. The same figure is repeated for PulseRate2 and 3. For all variables
where the number 1 displays, simply substitute a 2 or 3 for the 1 to get the signal name.
OSHW_Setpoint1, SS
A
Generate an alarm if the hardware is
|A-B| A different than the firmware trip.
OSHW_Setpoint, CFG OS1HW_SP_CfgEr (SS)
B A>B
(PulseRate1)
1RPM
B
OS_Setpoint, Generate an alarm if the hardware
A setpoint changes after power-up.
HW Value
OS1HW_SP_Pend (SS)
|A-B|
PulseRate1,
A Note: OSHW_Setpoint only goes into
HWIO
the hardware at thepack power-up.
A>=B
Changes to the value require a re-
B OS1HW boot or power cycle of the pack.
Hardware
Overspeed
OS1HW Trip
OS1HW_Trip
(SS)
OS1HW_Trip, (SS) L86MRX
Hardware Overspeed Trip, HP Shaft

Hardware Overspeed Trip functions include:
• Load the independent hardware overspeed set point only when the
PPRA pack re-boots or has power cycled.
• Generate an alarm when the hardware config set point is >1 Hz different from the
value passed through signal space from the application configuration.
• Generate an alarm and signal space Boolean when the set point in config
fails to match the value stored in the hardware.
• Implement speed calculation and the trip logic entirely inside programmable logic.
• Overspeed response time will be < 20 ms at trip speed.
• Hardware overspeed is implemented for each of the six speed inputs. The configuration
and trip indication is done using the same pairs identified for firmware overspeed.
The hardware overspeed diagram shows the overspeed names used for the first of
three pulse rate input pairs. The configuration, alarms, and latched trip are performed
for the pair of inputs PulseRate1A and PulseRate1B. A detected overspeed on
either PulseRate1A or PulseRate1B will latch as OS1HW_Trip. The same figure is
repeated for pairs PulseRate2A, 2B, and PulseRate3A, 3B. The signal name for all
variables where the number 1 siaplays is substituted by a 2 or 3.
Note There is no separate enable /disable signal for this Overspeed protection. The
disable signal is created by setting a high overspeed point value. The calculated speed
will never reach the value needed to trigger OS1HW.
The actual hardware implementation depends on two configuration items:
• HWOS_Setpoint specifies the overspeed trip level in RPM

• PRScale determines the number of speed sensor pulses per revolution used to convert
pulse rate into RPM for both hardware and firmware overspeed value
The hardware implementation requires two adjacent revolutions exceeding the

HWOS_Setpoint in order to trip the system. When a trip is present, the setting of
HWOS_Setpoint is reduced by a small amount in the hardware to provide a clean trip
signal. Because there are set limits to the time integration used in the hardware detector,
the minimum RPM setting for the HWOS_Setpoint is approximately four RPM.

LP Shaft Locked Detection
There is another protection function in addition to the overspeed protection shown
on the preceding page. It generates a signal in the event the first pulse rate signal is
above minimum speed, and the second pulse rate signal is still at zero.
PR1_MIN PR2_Zero, (SS)

LockRotorByp, SS LPShaftLock, (SS)
LPShaftLock, (SS) L86MR, SS
Speed Difference Detection

There should never be a reason why the speed calculated by the pack is significantly
different from the speed calculated by the main control. Speed difference detection looks
at the difference in magnitude between pulse rate 1 from both the pack and the main
control. If the difference is greater than the set threshold for three successive samples, a
SpeedDifTrip is latched. If the main control recovers for 60 seconds, the trip is removed.
This allows the main control to recover with subsequent re-arming of the backup protection.
PulseRate1, IO
A -0 A
Z
IA-BI A
-1 Speed 1_Diff
Speed1, SS B B (A&B&C)
OS_Diff, CFG (%) A>B Z
Rated RPM_TA,
-----------------------------
100 * CFG (RPM) B
Z
-2 C
SpeedDifEn , Card CFG
Speed1 _ Diff Speed_ Diff _ Trip Speed

Enable
Difference
Trip
L 86 MR, SS Speed1 _Diff
Close immediately , 60
sec delay on opening
Speed_ Diff_ Trip
Additional logic is added whenever dual control is used. When configured for
dual control, there are separate speed inputs from the two controllers that come
into the pack. This trip logic will act if both controllers have a speed error, but
will continue to run if one controller has a valid speed signal.

Maximum Speed Hold
The I/O pack provides a maximum speed hold function that resets when:
• Using the command PR_Max_RST (from signal space)

• PR1_Zero changes to false (you first start turning)
Output values are PR1_Max, PR2_Max, and PR3_Max. These signals are used to
determine the maximum speed obtained while running or after stopping a turbine.
Overspeed Test Logic, Steam Turbine

The signal OnLineOS1Tst is used for PulseRate1, OnLineOS2Tst is used for PulseRate2,
and OnLineOS3Tst is used for PulseRate3. In the following figure, there is another
signal, Online OS1X, which initiates an online overspeed test for PulseRate1. This
signal also creates a 1.5 second reset pulse when removed.
OnlineOS1Tst, SS Online_Overspeed_1_Test
OnlineOS1X, SS
OnlineOS1X, SS TDOSX
1.5 Second Delay L97EOST_ONLZ

TDOSX
OnlineOS1X, SS L97EOST_ONLZ L97EOST_RESET
L86MR, SS L86MRX
L97EOST_RESET
Online Overspeed Test Logic
Speed State Boolean Values

The I/O pack has detection for zero speed from a set point with 1 RPM hysteresis.
The pack calculates a minimum speed signal from a set point. The rate of change
of speed from a set point is calculated resulting in a selectable acceleration trip. A
deceleration trip is then determined from a fixed 100% / Second rate.

PR_Zero
1
Hyst
0
0
RPM
PulseRate 1, IO CFG
A
PR 1_ Zero
AB
Min_ Speed, CFG (J5, PulseRate1)
B
Speed Wheel Pulse
Detected Window
TDPU
“Inactive Counter”
AND
based on last speed 1 second
(max 24 secs)
AND
(Pulse rates in Hz) PR1_ DEC
A AND AND
75 Hz A>B
B
0
PR 2_ Accel
-3.4e38 A
S AB
Acc_Setpoint, CFG (J5, PulseRate2)
B
Dec1_Trip
PR1_DEC
Dec1_Trip L86MR, SS
Acc_Trip, CFG (J5, PulseRate1)
Acc1_Trip
PR1_ACC PR1_MIN Enable Acc1_TrEnab
Acc1_Trip L86MR, SS
*Note: Where 100% is define as the OS Setpoint
HP Shaft Accel Decel and Zero
The name of the first pulse rate input is shown in the above figure. The same figure is
repeated for PulseRate2 and 3. Simply replace the 1 with a 2 or 3 to get the signal name.
Note The contact, PR2-3_Min, in the Acc1_Trip is only present for PR2 (PR2_Min)
and PR3 (PR3_Min). It is not used for PR1.

Trip Anticipate Function
Steam turbine applications provide a speed trip that uses a live set point
from signal space. This overspeed trip is vigorously changed as a function
of turbine load. This function does the following:
• Input set point is OS1_TATrpSp from signal space. Input rated RPM is
specified by RatedRPM_TA as part of pack configuration. Function test
request input is TrpAntcptTst from signal space.
• If (OS1_TATrpSP is < 103.5% OR > 116% of RatedRPM_TA) then TA_Spd_Sp (the
local set point value) = 106% of RatedRPM_TA and TA_StptLoss (Signal space) is
true and alarm L30TA is declared. Otherwise, TA_Spd_Sp = OS1_TATrpSP.
• If TrpAntcptTst is true, decrease the current value of TA_Spd_Sp by 1RPM /
second. Set the minimum value of RatedRPM_TA to 94%. If TrpAntcptTst is
false, the value of TA_Spd_Sp from above is immediately used.
• If PulseRate1 (Speed input 1 from the pulse rate input) > TA_Spd_Sp
the internal value Trp_Anticptr is set properly.
• If the pack is configured for steam turbine application (internal value SteamTurbOnly),
then TA_Trip (signal space) equals the value of Trp_Anticptr.
The figure on the following page illustrates the function described above.
RatedRPM_TA, CFG (VPRO,

Config) RPM_94%
Calc Trip RPM_103.5%
Anticipate
speed RPM_106%
references RPM_116%
RPM_1%
RPM_116%
A
TA_StptLoss,SS
A<B Alarm
OS1_TATrpSp,SS RPM L30TA
B or
A
A<B
RPM_103.5% B
TA_Spd_SP
RPM_106%
RPM_1%/sec
Rate
TA_Spd_SP TA_Spd_SPX, RPM
Ramp A
Trp_Anticptr
Reset A<B
RPM_94%
(Out=In)
B
Hyst
TrpAntcptTst
RPM_1%
PulseRate1, IO, RPM
TA_Trip,SS
SteamTurbOnly Trp_Anticptr Trip Anticipator
Trip
L12TA_TP
Trip Anticipation Function

Solenoid Voltage / Power Sense
The I/O pack provides three comparator voltage inputs used to monitor solenoid power
or solenoid voltage depending on the trip card that is connected. SOL1_Vfdbk (SS),
SOL2_Vfdbk (SS), and SOL3_Vfdbk (SS) are generated from the input signals.
Main Control Watchdog

A standard control watchdog function is provided by the pack. In this function, a
value is passed from the main control to the pack each data frame. If the pack stops
seeing the value from the main control, a counter is incremented and, after five data
frames leads to a trip. If the main control recovers for 60 seconds, the trip is removed,
allowing for the recovery of the main control with subsequent re-arming of the backup
protection. The recovery function is provided for typical activities such as cycling
power on a controller to perform maintenance. While the controller is offline, the I/O
pack associated with that controller will vote to trip. When the controller returns to
operation, the pack will remove the vote to trip. The watchdog offers monitoring of
two main controls in the event both Ethernet ports are connected. When configured
for two controls, having one control active is sufficient to prevent a trip.
ContWdog, SS
A
5 CNTR = 5; Heart_Beat_Loss = 0
A == 1; CNTR = CNTR + 1 CNTR Heart_Beat_Loss
A != B A
-1 A == 0; CNTR = CNTR - 1 CNTR = 0; Heart_Beat_Loss = 1
B 0
Z
Up - Down Counter Saturation Limit
Toggle
IO Frame Rate ContWdogEn, Card CFG
Enable
ContWdogTrip
Heart_Beat_Loss
ContWdogTrip Heart_Beat_Loss
L86MR, SS
Close immediately, 60
Sec delay on opening
Control Watchdog Trip

Stale Speed Detection
The I/O pack provides an additional main control watchdog function that is based
on a live speed signal. The protection works as follows: If the pack PulseRate1 is
determined to be zero speed the protection is turned off. If above zero speed, the
pack looks at the value of Speed1 from the main control. If the most recent Speed1
value exactly matches the Speed1 value from the last data frame then a counter is
incremented. If the counter reaches a threshold then a stale speed trip is declared
and latched. If speeds are different the counter is cleared.
Although Speed_1, SS is available as a connected

variable, it should not be forced. It can cause the
protection to trip the system if enabled.
Attention
This protection is based on the knowledge that a live speed signal always dithers or moves
some small amount. The only way you will see consecutive signals with the same value for
a period of time is if the speed calculation or worse is not functioning in the main control.
If the main control recovers for 60 seconds, the trip is removed allowing for the recovery of
the main control with subsequent re-arming of the backup protection. The protection offers
monitoring of two main controls in the event both Ethernet ports are connected. When
configured for two controls, having one control satisfy the test is sufficient to prevent a trip.
PR1_Zero, (SS)
Speed1, SS
A A >= 100; Stale_Speed = 1
A == 1; CNTR = CNTR + 1
CNTR Stale_Speed
A A
A == B
A == 0; CNTR = 0
-1 A == 0; Stale_Speed = 0
Z B
Ratchet Counter Ratchet Toggle
Frame Rate StaleSpdEn, Card CFG
Enable StaleSpdTrip
Stale_Speed
StaleSpdTrip Stale_Speed
L86MR, SS
Stale Speed Trip

Main Control Ethernet Monitor
The main control provides time synchronization across the distributed control elements.
The time synchronization is tied tightly into the time at which traffic occurs on a given
controllers IONet. The I/O pack provides monitoring of this service to ensure it is working
correctly. Gross errors in time synchronization are detected by the pack through a number
of different means, and if problems persist, the I/O pack will vote to trip. Once the trip is
latched, if the problem goes away for 60 seconds the trip shall be reset (this assumes the
control recovers from the problem and is back on line). The monitor will offer monitoring
of two main controls in the event both Ethernet ports are connected. When configured for
two controls, having one control sequencing correctly is sufficient to prevent a trip.
In the following diagram, the detection has been simplified to show monitoring of an
Ethernet frame number as the means for determining a problem is present.
Sync_Frame_Number, SS
A
5 CNTR >= 5;
A == 0; CNTR = CNTR + 1 CNTR Frame_Sync_Error=1 Frame_Sync_Error
A = B+1 A
-1 A == 1; CNTR = 0 CNTR = 0; Frame_Sync_Error=0
B 0
Z
Toggle
Frame Rate FrameSyncEnabl, Card CFG
Enable FrameSyncTrip
Frame_Sync_Error
FrameSyncTrip Frame_Sync_Error
L86MR, SS
Sync Frame Court Monitor
Trip Signal Logic

The different trip signals are combined into a composite signal that is used in the
relay output logic. The following figure shows how the signals are combined.
This function is partitioned between firmware and programmable logic. The
path to trip through hardware overspeed is done completely in hardware so that a
firmware malfunction cannot defeat the protection. The same is true of the contact
input trip signals when they are configured for direct trip.
There are differences between steam turbine protection and other protection. A
composite signal SteamTurbOnly is created for ease of use:
LargeSteam*
MediumSteam* * A number of
contacts depend on
SmallSteam* the value of
Turbine_Type, CFG
SteamTurbOnly
Steam Turbine Trip Signals

Dec1_Trip
OS1_Trip
Acc1_Trip PulseRate1
L5CFG1_Trip Trips
Dec2_Trip
OS2_Trip GT_2Shaft*
PulseRate2
Trips
Acc2_Trip
L5CFG2_Trip LM_2Shaft*
LPShaftLocked LM_3Shaft* ComposTrip1,

(SS)
Dec3_Trip
OS3_Trip PulseRate3
Trips
LM_3Shaft*
Acc3_Trip
L5CFG3_Trip
L5Cont_Trip
SpeedDifTrip
Cross_Trip, SS System
Trips
StaleSpdTrip
ContWdogTrip
FrameSyncTrip
LM_2Shaft* LM_3Shaft* PR1_Zero
Zero
Speed
Special
LMTripZEnable, CFG HPZeroSpdByp SteamTurbOnly* Case
SS
L3Z
Hardware
Overspeed
OS1HW_Trip
OS2HW_Trip
OS3HW_Trip * CFG values
Trip Combine (All Signals [SS] unless Marked)

Watchdog
Hardware in the pack monitors operation of the local firmware and provides a
watchdog trip function in the event of a firmware malfunction. The operation of
this watchdog does not show up in the normal sequencing figures. The I/O pack
hardware is designed to be in a fail-safe or trip mode if it is not properly configured
and operating. This means that with power off, while starting up, when in a hardware
reset, or otherwise not online, the pack will vote to trip. If the pack watchdog
acts, it will reset the hardware thereby generating a vote to trip.
It should also be noted that the processor board used inside the pack has hardware features
that allow the processor to differentiate between a reset caused by the watchdog hardware
and a reset caused by cycling of power. This information is available from the pack after
it re-starts. In the event that a pack votes to trip due to a reset, it is then possible to
determine if a watchdog reset or a cycling of control power caused the event.
Trip Relay Outputs

PPRA provides drivers for three emergency trip relay commands, and provides
monitoring for three status feedback signals. Trip is a combination of firmware
trip and direct trip implemented in programmable logic.
TA_Trip, (SS) TestETR1 ComposTrip1 ETR1_Enab L5ESTOP1(SS) ETR1 (IO)

SS (SS) CFG, K1_Fdbk Trip Relay,
Energize to Run,
TA_Trip_Enabl1
CFG (PPRA)
TA_Trip(SS) TestETR2 ComposTrip1 ETR2_Enab L5ESTOP1(SS) ETR2 (IO)

Energize to Run,
TA_Trip_Enabl2
CFG (PPRA)
L97EOST_ONLZ Large Steam

CFG
TA_Trip(SS) ComposTrip1 TestETR3 ETR3_Enab L5ESTOP1(SS) ETR3 (IO)

(SS) SS CFG, K3_Fdbk Trip Relay,
Energize to Run,
TA_Trip_Enabl3
CFG (PPRA)
Trip relay Outputs

Specifications
Item PPRA Specification
Speed Input Quantity Six input signals provided
Speed input Range Pulse rate frequency range 2 Hz to 20 kHz
Speed Input Accuracy Pulse rate accuracy 0.05% of reading
Speed Input Sensitivity Required peak-peak voltage rises as a function of frequency:
0 – 2 kHz requires 27 mV
2 kHz – 6 kHz requires 50 mV
Above 15 kHz requires 250 mV
Frame Rate 100 Hz maximum
Physical
Size 8.26 cm High x 4.19 cm Wide x 12.1 cm Deep (3.25 in. x 1.65 in. x 4.78 in.)
Environment
Temperature Operating: -30 to 65ºC (-22 to 149 ºF)
Temperature Shipping and Storage: -40 to 80ºC (-40 to 176 ºF)
Air Quality Pollution Degree 2, free convection at the module
Note Speed input sensitive is such that turning gear speed may be observed on a
typical turbine application.
Diagnostics

• A check of the analog feedback currents
• A comparison between the commanded state of each relay drive and the
feedback from the commanded output circuit
A failed power-up self-test is indicated by solid red lighting of the power and attention
LEDs. Failure to verify the electronic ID will result in a communication failure.
Failures of the other tests will result in a generated diagnostic alarm.

with the RESET_DIA signal if they go health.

Configuration

TurbineType Turbine Type and Trip Solenoid Configuration Unused, GT_1Shaft, LM_3Shaft,
MediumSteam, SmallSteam,
GT_2Shaft, Stag_GT_1Sh,
Stag_GT_2Sh, LargeSteam, LM_2Shaft
LMTripZEnabl On LM machine, when no PR on Z, Enable a vote Disable, Enable
for Trip
ContWdogEn Enable trip on loss of Control Outputs to PPRA Disable, Enable
SpeedDifEn Enable Trip on Speed Difference between Disable, Enable
Controller and PPRA
StaleSpdEn Enable Trip on Speed from Controller Freezing Disable, Enable
FrameMonEn Enable trip when IO-Net frame synchronization is Disable, Enable
lost
RotateLeds Rotate the Status LEDs if all status are OK Disable, Enable
LedDiags Generate diag alarm when LED status lit Disable, Enable
SilMode SIL protection level Not_SIL, SIL 2, SIL 3
RatedRPM_TA Rated RPM, used for Trip Anticipator and for 3600
Speed Diff Protection
AccelCalType Select Acceleration Calculation Time (ms) 70
OS_Diff Absolute Speed Difference in Percent For Trip 5.0
Threshold
ContactInput Contact Input Unused, Used
SeqOfEvents Record Contact transitions in Sequence of Events Disable, Enable
DiagVoteEnab Enable Voting Disagreement Diagnostic Disable, Enable
TripMode Trip Mode Direct, Conditional, Disable
TripinEnab Enable Trip Input Detection on TREA card Disable, Enable
RelayOutput Relay Signal Unused, Used
DiagSolEnab Enable Solenoid Voltage Diagnostic Disable, Enable
PRType Selects the type of Pulse Rate Input, (For Proper Unused, Speed, Speed_LM, Speed_High
Resolution)
PRScale Pulses per Revolution (outputs RPM) 0 to 1000 (FLOAT) 60
OSHW_Setpoint Hardware Overspeed Trip Setpoint in RPM 0 to 20000 (FLOAT) 0
OS_Setpoint Overspeed Trip Setpoint in RPM 0 to 20000 (FLOAT) 0
OS_Tst_Delta Off Line Overspeed Test Setpoint Delta in RPM -2000 to 2000 (FLOAT) 0
Zero_Speed Zero Speed for this Shaft in RPM 0 to 20000 (FLOAT) 0
Min_Speed Min Speed for this Shaft in RPM 0 to 20000 (FLOAT) 0

Accel_Trip Enable Acceleration Trip Disable, Enable
Acc_Setpoint Acceleration Trip Setpoint in RPM / Sec 0 to 20000 (FLOAT) 0
TMR_DiffLimt Diag Limit,TMR Input Vote Difference, in Engg 0 to 20000 (FLOAT) 5%
Units
Dual_DiffLimit Diag Limit,Dual speed sensor, in Engg Units 0 to 20000 (FLOAT) 25 RPM
Terminal Board_TREA (MainVer_1)
Variable Description Direction Type

PulseRate1 HP speed AnalogInput Real
PulseRate2 LP speed AnalogInput Real
PulseRate3 IP speed AnalogInput Real
Fan_Spd_Fbk Fanned Speed Signal Feedback :- Fanned = Input Boolean
Jumpers Closed
Tripin_Fdbk Tripin, inverse sense,True = Run Input Boolean
Contact 1 through 4 Contact Input 1 through 4 Input Boolean
K1_Fdbk L4ETR1_FB, Trip Relay 1 Feedback Input Boolean
VSen1 Voltage Sensor 1 Feedback Input Boolean
VSen2 Voltage Sensor 2 Feedback Input Boolean
VSen3 Voltage Sensor 3 - Power Monitor Feedback Input Boolean
Modules_PPRA_Variables
Board Points (Signals) Description – Point Edit (Enter Signal Direction Type
Connection)
L3DIAG_PPRA_R,_S, and I/O Diagnostic Indication Input Boolean
_T
LINK_OK_PPRA_R,_S, and I/O Link Okay Indication Input Boolean
_T
ATTN_PPRA_R,_S, and _T I/O Attention Indication Input Boolean
PS18V_PPRA_R,_S, and _T I/O 18 V Power Supply Indication Input Boolean
PS28V_PPRA_R,_S, and _T I/O 28 V Power Supply Indication Input Boolean
IOPackTmpr_R,_S, and _T I/O Pack Temperature (deg °F) Analog Input Real
K1_FdbkNV_R,_S, and _T Non Voted L4ETR1_FB, Trip Relay 1 Feedback Input Boolean
K1FLT K1 Shorted Contact Fault Input Boolean

Connection)
PR1_Zero L14HP_ZE Input Boolean
OS1_Trip L12HP_TP Input Boolean
Dec1_Trip L12HP_DEC Input Boolean
Acc1_Trip L12HP_ACC Input Boolean
TA_Trip Trip Anticipate, Trip, L12TA_TP Input Boolean
TA_StptLoss L30TA Input Boolean
OS1HW_Trip L12HP_TP Input Boolean
Repeater_FLT RS-232 Speed Repeater Fault Input Boolean
Cont1_TrEnab through 7 Configuration – Contact 1 Trip Enabled through 7 Input Boolean
Acc1_TrEnab through 3 Configuration – Accel 1 Trip Enabled through 3 Input Boolean
GT_1Shaft Configuration – Gas Turb, 1 Shaft Enabled Input Boolean
GT_2Shaft Configuration – Gas Turb, 2 Shaft Enabled Input Boolean
LM_2Shaft Configuration – LM Turb, 2 Shaft Enabled Input Boolean
LM_3Shaft Configuration – LM Turb, 3 Shaft Enabled Input Boolean
LargeSteam Configuration – Large Steam 1, Enabled Input Boolean
MediumSteam Configuration – Medium Steam Enabled Input Boolean
SmallSteam Configuration – Small Steam Enabled Input Boolean
Stag_GT_1Sh Configuration – Stag 1 Shaft, Enabled Input Boolean
Stag_GT_2Sh Configuration – Stag 2 Shaft, Enabled Input Boolean
ETR1_Enab Configuration – ETR1 Relay Enabled Input Boolean
OS1HW_SP_Pend Hardware HP overspeed setpoint changed after Input Boolean
power up
OS2HW_SP_Pend Hardware LP overspeed setpoint changed after Input Boolean
power up
OS3HW_SP_Pend Hardware IP overspeed setpoint changed after Input Boolean
power up

Connection)
OS1HW_SP_CfgErr Hardware HP Overspeed Setpoint Configuration Input Boolean
Mismatch Error
OS2HW_SP_CfgErr Hardware LP Overspeed Setpoint Configuration Input Boolean
Mismatch Error
OS3HW_SP_CfgErr Hardware IP Overspeed Setpoint Configuration Input Boolean
Mismatch Error
L5CFG1_Trip HP Configuration Trip Input Boolean
L5CFG2_Trip LP Configuration Trip Input Boolean
L5CFG3_Trip IP Configuration Trip Input Boolean
OS1_SP_CfgEr HP Overspeed Setpoint Configuration Mismatch Input Boolean
Error
OS2_SP_CfgEr LP Overspeed Setpoint Configuration Mismatch Input Boolean
Error
OS3_SP_CfgEr IP Overspeed Setpoint Configuration Mismatch Input Boolean
Error
ComposTrip1 Composite Trip 1 Input Boolean
TripIn Trip Input Input Boolean
L5Cont1_Trip through 4 Contact 1 Trip 4 Input Boolean
LPShaftLock LP Shaft Locked Input Boolean
Inhbt1_Fdbk through 4 Trip Inhibit Signal Feedback for Contact 1 through Input Boolean
7
L3SS_Comm Communication Fault Input Boolean
Trip1_EnCon through 4 Contact 1 Trip Enabled through 4 – Conditional Input Boolean
PR1_Accel HP Accel in RPM/SEC Analog Input Real
PR2_Accel LP Accel in RPM/SEC Analog Input Real
PR3_Accel IP Accel in RPM/SEC Analog Input Real
PR1_Max HP Max Speed since last Zero Speed in RPM Analog Input Real
PR2_Max LP Max Speed since last Zero Speed in RPM Analog Input Real
PR3_Max IP Max Speed since last Zero Speed in RPM Analog Input Real
Cross_Trip L4Z_XTRP - Control Cross Trip Output Boolean
OnLineOS1Tst L97HP_TST1 - On Line HP Overspeed Test Output Boolean
OnLineOS2Tst L97LP_TST1 - On Line LP Overspeed Test Output Boolean
OnLineOS3Tst L97IP_TST1 - On Line IP Overspeed Test Output Boolean
OffLineOS1Tst L97HP_TST2 - Off Line HP Overspeed Test Output Boolean
OffLineOS2Tst L97LP_TST2 - Off Line LP Overspeed Test Output Boolean
OffLineOS3Tst L97IP_TST2 - Off Line IP Overspeed Test Output Boolean
TrpAntcptTst L97A_TST - Trip Anticipate Test Output Boolean
LokdRotorByp LL97LR_BYP - Locked Rotor Bypass Output Boolean
HPZeroSpdByp L97ZSC_BYP - HP Zero Speed Check Bypass Output Boolean

Connection)
PTR1 L20PTR1 - Primary Trip Relay CMD, for Diagnostic Output Boolean
only
only
only
PR_Max_Rst Max Speed Reset Output Boolean
OnLineOS1X L43EOST_ONL - On Line HP Overspeed Test, Output Boolean
with auto reset
TestETR1 L97ETR1 - ETR1 test, True de-energizes relay Output Boolean
Trip1_Inhbt through 4 Contact 1 Trip Inhibit through 4 Output Boolean
OS1_Setpoint HP Overspeed Setpoint in RPM Analog Output Real
OS2_Setpoint LP Overspeed Setpoint in RPM Analog Output Real
OS3_Setpoint IP Overspeed Setpoint in RPM Analog Output Real
OS1_TATrpSp PR1 Overspeed Trip Setpoint in RPM for Trip Analog Output Real
Anticipate Fn
Speed1 Shaft Speed 1 in RPM Analog Output Real
OSHW_Setpoint1 HP Overspeed Setpoint in RPM Analog Output Real
OSHW_Setpoint2 LP Overspeed Setpoint in RPM Analog Output Real
OSHW_Setpoint3 IP Overspeed Setpoint in RPM Analog Output Real
ContWdog Controller Watchdog Counter Output Double Integer
Watchdog_Trip Enhanced Diagnostic - Watch Dog Trip Input Boolean
StaleSpeed_Trip Enhanced Diagnostic - Stale Speed Trip Input Boolean
Speed_Diff_Trip Enhanced Diagnostic - Speed Difference Trip Input Boolean
Frame Mon_FLT Enhanced Diagnostic - Frame Monitor Fault Input Boolean
PR1A_SPD PR1A - Dual Speed Sensor 1A Analog Input Real
PR1B_SPD PR1B - Dual Speed Sensor 1B Analog Input Real
PR2B_SPD PR2B - Dual Speed Sensor 2B Analog Input Real
PR3B_SPD PR3B - Dua; Speed Sensor 3B Analog Input Real

TREA/WREA Turbine Emergency Trip
The Aero derivative Turbine Emergency Trip (TREA) terminal board combined
with the WREA option card works with PPRA turbine I/O packs as part of the
Mark* VIe system. The inputs and outputs are as follows:
• Customer input terminals provided through two 24-point pluggable barrier terminal
blocks (H1A or S1A) or 48 pluggable Euro-style box terminals (H3A or S3A).
• Six fanned passive pulse rate devices (up to three shafts with two sensors
each) sensing a toothed wheel to measure the turbine speed.
• Three 24 V dc TREAH1A, H3A plus WREAH1A or TREAS1A, S3A plus
WREAS1A TMR voted solid-state output contacts to trip the system.
• Four 24-125 V dc voltage detection circuits for monitoring trip string.
• Four 24 V dc WREAH1A or WREAS1A contact inputs provide
additional hardware or conditional trip inputs. Wetting power is supplied
through the JH1 connector on WREA.
• One speed repeater output for each of the six speed inputs reproduces the speed
pulse rate signals using an RS–232 or RS–422 transmitter.
TREA plus WREA requires three PPRA I/O packs for correct operation.



JZ1
62-pin “D” shell

connector. Plug
PPRA I/O packs
into JX1, JY1, & JZ1
K1
K1
K1
K1
K1
K1
TB1
Solid-state trip
relays K1 & K2
JY1
K2
K2
K2
K2
K2
K2
J2
WREA daughter-
card plugs onto
J1 and J2
P2 connectors.
JX1
TB2
P1
J1
Barrier or box terminals Place jumpers over P1, P2 pin

can be unplugged from pairs to fan JX set of magnetic
board for maintenance speed inputs to JY and JZ
TREA Turbine Terminal Board

Four contact
points
TMR voting
relay output
Three speed
input circuits
Six speed
repeaters
Speed repeater
setup jumpers
WREA Terminal Option Board

Installation
When received from the factory the WREA should by default be mounted to the
TREA terminal board. Should the board have to be removed to service the TREA
fanning jumpers use the following procedure to replace the WREA.
• Align the two connectors on the WREA with those on the TREA. When
viewing the WREA the bottom of the board is considered to be the end
with the row of configuration jumpers. The connectors are keyed such
that they will only mate when aligned properly.
• Once the two boards are aligned seat the connection by firmly pressing on
the four screw heads that surround the connector.
The WREA is considered fully mounted when it cannot be pushed any farther.
For H1 and S1 board variants, voltage detection, trip contact inputs, and relay
outputs are wired to the I/O terminal blocks TB1. Passive pulse rate pick-ups are
wired to TB2. Each block is held down with two screws and has 24 terminals
accepting up to #12 AWG wires. A shield termination strip attached to chassis
ground is located immediately to the left of each terminal block.
For H3 and S3 board variants, voltage detection, trip contact inputs, and relay
outputs are wired to the I/O box terminals at the top of the board. Passive pulse
rate pick-ups are wired to the lower terminals. All terminals plug into a header
on the TREA board and accept up to a single #12 AWG wire.
When used with WREA the TREA must be configured

for fanning of the X section pulse rate pickups to the Y
and Z PPRAs. This is done by placing the jumpers on the
P1 and P2 pin pairs.
Caution

In the following table the speed inputs called PR1_Y through PR3_Z are grayed out.
While the signal paths are present as documented for use with PPRO I/O packs they
are not used and should not be connected when PPRA I/O packs are used.
TREA/WREA Terminal Board Wiring
Pin Signal Name Pin Signal Name

1 K1_PDC 2 K1_NDC
3 K2_PDC 4 K2_NDC
5 SOL1_A 6 SOL1_B
7 SOL2_A 8 SOL2_B
9 PWR_A 10 PWR_B
11 TRP_A 12 TRP_B
13 K3_PDC 14 K3_NDC
15 PWET 16 TRP1L
17 PWET 18 TRP2L
19 PCOM 20 PCOM
21 PWET 22 TRP3L
23 PWET 24 TRP4L
25 PR4H 26 PR4L
27 PR5H 28 PR5L
29 PR6H 30 PR6L
31 PR1H_Z 32 PR1L_Z
33 PR2H_Z 34 PR2L_Z
35 PR3H_Z 36 PR3L_Z
37 PR1H_Y 38 PR1L_Y
39 PR2H_Y 40 PR2L_Y
41 PR3H_Y 42 PR3L_Y
43 PR1H_X 44 PR1L_X
45 PR2H_X 46 PR2L_X
47 PR3H_X 48 PR3L_X

Contact Outputs
The contact outputs are polarity sensitive. Wire the

circuit carefully to avoid damaging the relays. There
is no contact or solenoid suppression, user must add
external solenoid suppression to avoid damaging the
Caution relays and their contacts.
A voltage detection circuit is included on TREA and WREA that is able to detect
a shorted relay when voltage is present across the open contact set.
SO L_ V
TRIP
Solenoid
S OL_P W R
TREA
Contact
Connection to TREA contact output
Trip Input
• The Trip input is configurable in PPRA to either be required or bypass the
signal. When enabled the Trip input works through a hardware path on
PPRA and does not act through PPRA firmware. When enabled the Trip
input must be powered for the trip relays to close.
• The Trip input must be connected to a CLEAN dc source battery or
filtered (< 5% ripple) rectified ac.
• There must be a minimum of 18 V dc at the Trip inputs for proper operation. The
current required was kept low to minimize drop on long cable runs.
• As the Trip input is very fast < 5 ms and the output relay contacts are also fast
(< 1 ms), best wiring practices should be utilized to avoid misoperation. Use
twisted-pair cable when possible and avoid running with ac wiring.
Contact Inputs
• Wetting power is supplied through the JH1 connector on WREA with the
following pin connections: Pin 1 is positive wetting voltage, Pin 2 is ground,
and Pin 3 is negative or return wetting voltage.
• Each contact input has two associated screw terminals on TREA. Odd numbered
terminals identified as PWET are directly connected to the JH1 pin 1 input power.
Even numbered terminals identified as TRP1L through TRP4L lead to individual
voltage detectors that share a return path to JH1 Pin 3. Because all PWET terminals
are connected together it is permissible to use a single wire from PWET to a set of
remote contacts and then use individual return wires to the TRP_L inputs.

Speed Repeater Outputs
Each speed repeater output may be configured to provide either RS–232 or RS–485 signal
levels. RS–232 provides a bipolar signal that crosses through zero as is required by many
speed inputs. It is recommended that RS–232 repeater outputs be limited in wiring length
to 10 meters and go to equipment that is grounded at the same potential as TREA / WREA.
RS–485 provides a balanced differential signal that is more suitable for long distance
transmissions. It is recommended that RS485 repeater outputs be limited in wiring length
to 500 meters. Wire type and termination should comply with published RS–485 standards.
The repeater outputs are grouped together on the J3 connector located on WREA. The
outputs are arranged to provide a signal ground and chassis ground pin pair between
each active signal pair. This makes it possible to ground the individual shields of
twisted shielded pair cable and reduces any chance of signal cross talk. The diagram
indicates the J3 pin assignments when looking into the connector.
13 NO CONNECT
PCOM 25
12 CHASSIS
SPD6_N 24
11 SPD6_P
PCOM 23
10 CHASSIS
SPD5_N 22
9 SPD5_P
PCOM 21
8 CHASSIS
SPD4_N 20
7 SPD4_P
PCOM 19
6 CHASSIS
SPD3_N 18
5 SPD3_P
PCOM 17
4 CHASSIS
SPD2_N 16
3 SPD2_P
PCOM 15
2 CHASSIS
SPD1_N 14
1 SPD1_P
WREA-J3 Connector

Speed repeater outputs from the WREA-J3 connector are wired to a transition
module ALH#5747.2 through a special 25 pin cable, 259B2434AEPxx, where xx
is the cable length in feet. It transmits the six sets of speed signals through six sets
of individually shielded, twisted pair wires. The six sets of signals connect pin to
pin as shown in the WREA-J3 connector pin assignment drawing.
The shields from each wire pair also connect the chassis connections pin to pin,
from the WREA-J3 Sub-D connector to the transition module connector. Signal and
chassis connection point numbers carry through from the transition module Sub-D
connector to the corresponding points on the box type terminal board. The cable
also has an overall shield terminated on the Sub-D connector shells at each end the
cable. That shield ties to the chassis ground on the WREA board.
The shield wires at the final connection point for the cables should be left
un-terminated and properly protected/sheathed to prevent shorting.
The DIN rail mounted transition module

connects pin to pin from a 25 pin connector
contact type Sub-D connector to the box type
screw terminal board on that module. The
special cable has 25 pin Sub-D connectors
with receptacle pins on each end.

Operation
System Design
The TREA board is designed to use three PPRA I/O packs mounted directly on it. The
TREA / WREA / PPRA assembly then forms a self-contained emergency trip function.
TREA
PPRA
Control
DC-62
module
JZ1
Trip relays,
PPRA
Estop,
Overspeed Control
module
DC-62
JY1
PPRA
WREA
Control
module
DC-62
JX1
TREAH1A, S1A, H3A, and S3A plus WREA will only function correctly with three
PPRA I/O packs. Single and dual pack operation is not possible. In systems with a
single controller the controller R network should be connected to the PPRA on the JX1
connector, the S network to PPRA on the JY1 connector, and the T network to the PPRA
on the JZ1 connector. Note that all three networks are coming from the single controller.
In systems with dual controllers the controller R network should be connected to the
PPRA on the JX1 connector, the S network to PPRA on the JY1 connector, and both the
R and S networks to the PPRA on the JZ1 connector. In systems with three controllers
the R network should be connected to the PPRA on the JX1 connector, the S network to
PPRA on the JY1 connector, and the T network to the PPRA on the JZ1 connector.
Speed Inputs
Speed inputs are associated with specific shafts. The PR1_X and PR4 speed inputs must
be wired to the two speed sensors on the first shaft. The PR2_X and PR5 speed inputs
must be wired to the two speed sensors on the second shaft, if present.
The PR3_X and PR6 speed inputs must be wired to the two speed sensors on the third
shaft, if present. Jumpers P1 and P2 must be placed on the TREA to take the first three
speed inputs (those for the X pack) and fan them to the Y and Z packs. When this
is selected, the terminal board points for Y and Z speed inputs become no-connects
and should not be used. As a check a jumper position feedback signal is provided by
TREA. If the jumpers are not in place a PPRA alarm will be generated.

Trip Input
The TREA includes a Trip input function. This consists of an optically isolated input
circuit designed for a dc input in the range of 24 V to 125 V nominal. When energized,
the circuit enables coil drive power in the X, Y, and Z relay circuits through independent
hardware paths.
The response time of this circuit of less than five milliseconds plus the response time of
the trip relays of less than one millisecond yields very fast response. Trip input status is
monitored by PPRA firmware, but the action to remove trip relay coil power is a hardware
path in PPRA. It is possible to configure PPRA to turn off the Trip input function.

TREA / WREA provides four discrete group isolated contact input trip signals to the
PPRA I/O packs. The transition threshold of the contacts tracks 50% of the applied
wetting voltage. Approximately 1% voltage hysteresis is applied to transitions. A filter
with nominal 4 ms delay, max 5 ms is present. PPRA monitors wetting voltage on JH1
and generates an alarm at voltages below approximately 40% of nominal voltage.
Voltage Monitors
The trip relays on TREA may be freely located anywhere in a trip string. Because the
trip string circuit is not fixed, there are three general-purpose isolated voltage sensor
inputs on TREA. These can be used to monitor any points in the trip system and
drive the voltage status into the system controller where action can be taken. Typical
use of these inputs may be to sense the power supply voltage for the two trip strings
(PWR) and to sense the solenoid voltage of the device being driven by the relays
(SOL1, SOL2). This set of applications is used in the wording of the board symbol,
but the sensors may be freely applied to best serve the application.

Speed Repeaters
There are six speed repeater circuits on WREA. Each repeater is associated with a specific
speed input signal and may be configured for RS–232 or RS–485 signal levels on the
output. The speed repeater is driven by an internal signal after speed input pulse detection
has taken place. While the speed sensor input signal may span a wide range of amplitude
as speed is changed the repeater output maintains constant output amplitude through all
pulse rates.
The speed repeaters do add some latency to the speed signal. In addition to copper
transmission latencies, the repeater circuitry will add between 1.5 and 2.0 usecs of
edge to edge latency. The variation is due to pulse rate input channel (pulse rate
1-3 vs. 4-6) and repeater configuration (RS–232 vs RS–485).
Trip Relays
The trip relays are made using sets of six individual form A devices arranged in a voting
pattern. Any two controllers that vote to close will establish a conduction path through the
set. Because detection of a shorted relay is important to preserve tripping reliability, there
is a sensing circuit applied to each of the sets of relays.
When the relays are commanded to open, and voltage is present across the relays, the
circuit will detect if one or more relays are shorted. This signal goes to the PPRA
I/O pack to create an alarm. The TREA sensing circuit uses the relay commands
from all three packs to avoid a false indication, in the event that one PPRA I/O
pack votes to close the relay while the other two PTUR I/O packs vote to open.
The voting arrangement is shown in the following TREA symbol.
Contacts are polarity-sensitive. External voltage

suppression must be used.
Caution

TREA + WREA Trip Boards

Specifications
Item Specification
Number of inputs 6 passive (magnetic) speed pickups
3 voltage detection circuits
1 ESTOP/TRP input
4 contact inputs
Number of outputs 3 trip contacts
6 speed repeater drivers
Contact ratings NEMA class F.
IS200TREAH1A, H3A, SIA, S3A Voltage: 28 V dc max
plus WREAH1A, SIA Max. Current 10 A dc at 40ºC (104 ºF) maximum (Trip Relays 1 and 2)
de-rate current linearly to 7 A dc at 65ºC (149 ºF) maximum.
Max. Current 5 A dc at 40ºC (104 ºF) maximum (Trip Relay 3)
No de-rating necessary at 65°C as traces are limiting factor.
Voltage detection inputs Min/max input voltage rating: 16/150 V dc max pk
Current Loading (Max leakage): 3 mA
Detection delay (max): 60 ms
Voltage isolation: Optically isolated: 2500 V rms isolation, for one min.
Surge/Spike rating: 1000 V pk for 8.3 ms
ESTOP/TRP detection Input Voltage: 24-125 V dc ±10% (18/150 V pk Min/Max)
Loading (max): 12 mA (5 typical)
Delay (max): 5 ms (<1 typical)
Contact input voltage WREAH1A ,S1A – nominal 24 V dc input
Contact input threshold Tracks 50% of wetting voltage applied to JH1 connector. Hysteresis of 1% applied
to transitions. Filter delay of 4 ms nominal, 5 ms maximum.
MPU pulse rate range 2 Hz to 20 kHz
MPU pulse rate accuracy 0.05% of reading
Speed input sensitivity Required peak-peak voltage rises as a function of frequency:
0 — 2 kHz requires 27
2 kHz — 6 kHz requires 50 mV
Physical
Size 33.0 cm high x 17.8 cm, wide (13 in. x 7 in.)
Note Speed input sensitive is such that turning gear speed may be observed on a

Diagnostics
Diagnostic tests are made on the terminal board:
• Feedback from the shorted contact detector is checked, if a shorted

relay is detected an alarm will be created.
• Feedback from speed pickup fanning jumpers is checked; if there is a mismatch
between intention and actual position, an alarm is created.
• Each speed repeater output has a receiver circuit that monitors the output. If the output
signal does not closely match the required speed signal an alarm is generated. This
diagnostic protects against shorted repeater outputs or repeater output drive failure.
• If any one of the above signals goes unhealthy, a composite diagnostic alarm
xxDIAG_PPRA occurs. The diagnostic signals can be individually latched and
then reset with the RESET_DIA signal if they go healthy.
• Terminal board connectors have their own ID device that is interrogated by the I/O
pack. The ID device is a read-only chip coded with the terminal board serial number,
board type, revision number, and plug location. When the chip is read by PPRA
and a mismatch is encountered, a hardware incompatibility fault is created.
• Wetting power presence.
Configuration
Jumpers JP1 and JP2 select the fanning of the X channel speed inputs to the Y and Z PPRA
I/O packs. PPRA operation with TREA and WREA requires that these jumpers be in place.
WREA jumpers JP1 through JP12 are used to configure output behavior of the
six speed repeater output circuits. The jumpers are located at the bottom of
WREA in the same order as the following diagram.
PR3Y PR2Y PR1Y PR3X PR2X PR1X RS485 RS485 RS485 RS485 RS485 RS485
JP11
JP12
JP10
JP1
JP9
JP8
JP7
JP6
JP5
JP4
JP3
JP2
PR6 PR5 PR4 vote vote vote RS232 RS232 RS232 RS232 RS232 RS232
Jumpers JP1 through JP6 are used to select between RS–232 signal level (default) and
RS–485 signal level on the repeater output. JP1 through JP3 configure the repeater outputs
for PR1 through PR3 while JP4 through JP6 configure repeaters for PR4 through PR6.
Jumpers JP7 through JP12 default to the PR1 through PR6 positions and should
remain in these positions when used with PPRA.

PPRF PROFIBUS Master Gateway
PROFIBUS Master Gateway (PPRF)

PROFIBUS DPM
The PROFIBUS Master Gateway (PPRF) pack is a PROFIBUS DPV0, Class 1 master
PWR
that maps I/O from PROFIBUS slave devices to Mark* VIe controllers on the I/O
SYS RUN
ATTN Ethernet.
NOT RDY
LINK
The module contains a processor board common to all Mark VIe distributed I/O modules
COMM OK
TxRx
ENET1 and an acquisition carrier board fitted with a COM-C PROFIBUS communication
COMM ERR module supplied by Hilscher GmbH. The COM-C module provides a PROFIBUS
RS-485 interface through a DE-9 D-sub receptacle connector. It serves as a PROFIBUS
DP master supporting transmission rates from 9.6 KBaud to 12 MBaud and up to 125
ACTIVE
LINK
ENET2 slaves with 244 bytes of inputs and outputs per slave.
TxRx
STANDBY
IR PORT The PPRF supports the following redundancy options:
• Single I/O pack with single I/O Ethernet connection (no redundancy)
• Single I/O pack with dual I/O Ethernet connections
IS220PPRFH1A
• Hot-backup I/O pack with dual I/O Ethernet connections
The dual I/O Ethernet connection configuration is common to other IO packs. However,
in the hot-backup two PPRFs are employed, one operating as the active PROFIBUS
master communicating with slave devices, and the other operating in a passive, stand-by
mode, ready to become the active master in the event of an active master failure
GEH-6721L PPRF PROFIBUS Master Gateway System Guide 17-1

PPRFH1A
PROFIBUS gateway module
BPRFH1A BPPB
carrier board processor board
COM-CS-DPM-E/GEES
PROFIBUS
Single or dual
communication board
Ethernet cables
ENET1
PROFIBUS ENET2
External 28 V dc
power supply
SPIDG1A
terminal board
PPRF Simplified Diagram
Compatibility
The PROFIBUS Master Gateway Terminal board (SPIDG1A) is used to mount the PPRF
and to supply an electronic ID. Its only connection is the interface to the PPRF itself, as the
PROFIBUS connection is made to the DE-9 D-sub receptacle connector exposed on the
side of the PPRF. Visual diagnostics are provided through indicator LEDs on the PPRF.
Terminal Board SPIDG1A

Control mode Simplex-yes Dual -no TMR-no Hot-backup-yes
• Simplex uses one I/O pack with one or two network connections
• Hot-backup uses two I/O packs with two network connections each pack

Installation
¾ To install the PPRF pack
1. Securely mount the SPID terminal board.
2. Directly plug the PPRF into the terminal board connector. For hot-backup
configurations, repeat steps 1 and 2 with a second SPID and PPRF.
ENET1 to the network associated with the R controller; however, the PPRF is not
5. Connect and secure the PROFIBUS cable into the DE-9 D-sub receptacle connector.
As per PROFIBUS requirements, the PROFIBUS must be terminated on either end.
6. Apply power to the connector on the side of the pack. It is not necessary to
insert the connector with power removed from the cable. The PPRF has inherent
7. Use the ToolboxST* application to configure the I/O pack and PROFIBUS as necessary.

Wizard again.

Operation
Processor




PROFIBUS Gateway Hardware
The PPRFs COM-C module, built on a PROFIBUS core based on Siemens ASPC2
technology, contains firmware that implements the PROFIBUS DP (Decentralized
Periphery) functionality. Though the COM-C module is DPV1 capable, the PPRF
only provides the basic DPV0 functionality, which includes configuring slave devices,
cyclically exchanging I/O data with them, and obtaining PROFIBUS diagnostics.
The COM-C’s firmware, residing in a flash memory, is released as part of the PPRF
firmware and downloaded to the COM-C’s flash at I/O pack startup time only if necessary
(for instance when the PPRF firmware is released with an updated COM-C firmware).
The COM-C module requires a PROFIBUS configuration file that is created by

the ToolboxST application. This file, specifying the DP master parameter set, is
loaded from the ToolboxST application along with the other standard I/O pack
configuration files, and, if changed, requires a PPRF reboot following the load. As is
the case with the COM-C firmware file, the PROFIBUS configuration file is stored
in COM-C flash and only downloaded from PPRF flash if necessary.
Data Flow between PPRF and Controller

Data flow between the PPRF and the controller is of two types, fixed I/O and
PROFIBUS I/O. The limited amount of fixed I/O includes the inputs that are common
to all I/O packs, for example L3DIAG and IOPackTmpr, but no application-driven
outputs. The set of fixed I/O is pre-defined in the PPRF firmware. PROFIBUS I/O
consists of the data exchanged with PROFIBUS slave devices, and its definition varies
according to hardware configuration specified by the application.
The PPRF is guaranteed to handle 500 inputs and 500 outputs, half Boolean and half
analog, at a 40 ms frame rate. The Boolean inputs may have input event detection enabled,
and the analogs may be configured such that point-to-variable data type conversion and
scaling take place. The PPRF does not place an architectural limit on the number of
I/O points; the 500 input/output value is not a limit but a guarantee.
Input Events
The PPRF optionally supports input Boolean sequence of event logging referred to as
input event detection. PPRF input event time tagging has a 10 ms resolution.

Specifications
Item PPRF Specification
PROFIBUS Master type DPV0 Class 1 master
PROFIBUS connection RS-485 interface through DE-9 D-sub receptacle connector
Transmit time PROFIBUS output data from Mark VIe is received once per frame, up to 100 times per
second and is asynchronously transmitted by the COM-C module to PROFIBUS slaves
as fast as possible, governed by the PROFIBUS network baud rate, number of slaves,
amount of I/O, and slave response time.
Receive time PROFIBUS inputs are asynchronously received by the PPRF COM-C module as fast as
possible, governed by the PROFIBUS network baud rate, number of slaves, amount of
I/O, and slave response time, then scanned by the PPRF firmware 100 times per second
and transmitted to the Mark VIe once per frame, up to 100 times per second.
PROFIBUS transmission speeds 9.6 KBaud to 12 MBaud
Number of slaves 125 slaves with 255 bytes of inputs and outputs per slave
I/O throughput 500 inputs and 500 outputs, half Boolean and half analog, at a 40 ms frame rate (Note:
this is a requirement, not a hard limit)
Input Event detection Available on input Booleans, 10 ms resolution

Diagnostics
The PPRF receives and stores all PROFIBUS diagnostics generated by slave devices.
In addition to any portion of the diagnostic data (including the standard and extended
portions), controller applications receive an input Boolean that is set to True when
PROFIBUS diagnostics have been received from one or more slave devices (diagnostics
presence) and also receive input Booleans set to True to identify specific slave devices
that have generated diagnostics (station diagnostics presence).
The ToolboxST application provides an Advanced Diagnostics command, as

part of the Troubleshoot Module, which can be used to display any PROFIBUS
diagnostics that are generated by slave devices.
Health
Each PROFIBUS input has an associated health bit allocated in the inputs EGD exchange.
The PPRF sets input health to unhealthy when any of the following conditions occur:
• Loss of communication between the associated slave device and

the PROFIBUS master.
• Standard I/O Ethernet input validation error.
PROFIBUS diagnostics other than the station diagnostics presence inputs, the
Station_Non_Existent diagnostic, and the diagnostics presence input become
unhealthy if any of the following conditions occur:
• The Station_Non_Existent diagnostic is True.

• The slave is not configured in the master.
The station diagnostic presence inputs and Station_Non_Existent diagnostic inputs

become unhealthy if either of the following conditions occur:

• The slave is not configured in the master.
The diagnostics presence input becomes unhealthy when the following condition occurs:

Processor LEDs
LED Label Description

present
Red / Green ATTN Shows pack or module status
Status LEDs
Red LED out There are no detectable problems with the pack or module. All
ATTN
LED solid on A critical fault is present that prevents the pack or module from 3.04 or earlier
1.5 Hz 50% The pack or module is not online.
or module.
ATTN
Green Solid BIOS (at power on) - if it remains in this state, the pack or module
ATTN is dead.
every 4 sec

PPRF LEDs
A green LED labeled SYS RUN indicates three different conditions as follows:
• LED solid on – the COM-C module has established communication

with at least one PROFIBUS slave device
• LED flashing fast cyclically (5 Hz) – PROFIBUS master is configured and ready to
communicate with slaves but is not connected or otherwise unable to communicate
– the COM-C module is either missing a PROFIBUS configuration or its watchdog
Note If the following two LEDs (SYS RUN and NOT RDY) are off at the same time,
either power is not applied or the COM-C module is being reset (which happens during
an active to backup redundant PPRF transition). In all other conditions, one or the
other LED will be on (though maybe flashing). The SYS RUN LED lights when the
COM-C module’s SYS LED is green; the NOT RDY LED lights when the COM-C
module’s SYS LED is yellow.
A green LED labeled COMM OK mimics the COM-C COM LED when it is yellow:
• LED solid on – the COM-C module is holding the PROFIBUS token and is
able to transmit PROFIBUS telegrams to slave devices
• LED flashing non-cyclically (between 0.5 Hz and 100 Hz) – the COM-C
module is sharing the PROFIBUS token with other master devices on the
network. This takes place in hot-backup configurations
• LED out – the COM-C is not communicating on the PROFIBUS network
A red LED labeled COMM ERR mimics the COM-C COM LED when it is red:
• LED solid on – the COM-C module has encountered a communication error

Green LEDs labeled ACTIVE and STANDBY that are lit solidly in
a mutually exclusive fashion:
• ACTIVE LED solid on – PPRF is the active master

• STANDBY LED solid on – PPRF is the backup master

Configuration
Parameters and Online Loads

In general, I/O pack parameters can be changed online without restarting the system. PPRF
parameters consist of I/O transfer scaling values, which are configured when Boolean
input event detection is enabled or not for given points. The PPRF is also used to change
point data type conversion and the addition and removal of variables attached to points
through online loads. A system restart is not required as long as the ToolboxST application
Compress Variables command is not run, which would rearrange the EGD exchange.
Hot-backup Redundancy
The PPRF supports a hot-backup redundancy configuration in which two PPRFs operate
in tandem, one being the active master and the other retaining a standby status. The active
master exchanges I/O with the PROFIBUS slaves and receives generated diagnostics. The
backup master operates in standby mode, not communicating with the slave devices
but ready to automatically assume the active role if any of the following occur:
• The active master looses communication connectivity with the PROFIBUS

slaves (such as, the PROFIBUS cable is disconnected)
• The active master looses communication connectivity on both I/O Ethernets (such as,
both Ethernet cables are disconnected or Ethernet switch connection, Ethernet cable
disconnection combinations, and such, occur. Redundant Ethernet connections are
required for each PPRF, and loosing a single Ethernet does not cause a switch.)
• The active master is powered down or fails.
Since the switchover time is less than 200 ms, slave watchdog timeout values should
not be set to less than that value so that the slaves do not timeout during the portion of
the interval in which no PROFIBUS communication takes place. Given that the slave
watchdog timeout is set sufficiently large, PROFIBUS I/O values should not spike or
drop-out during the switchover period. They may, however, flat-line momentarily.
Unlike what is done in dual or TMR-pack cases, in the PPRF hot-backup configuration,
the two PPRFs are assigned different producer IDs. Different controller application
variables may be assigned to the fixed Class 1 inputs that are received from each pack
(such as, L3Diag). The fixed inputs include an active/backup status Boolean from each
PPRF (PROFI_BACKUP_PPRF_R and PROFI_BACKUP_PPRF_S, respectively).
Single application variables are assigned to the PROFIBUS I/O, and data exchange
to and from those variables takes place regardless of which PPRF is active. When a
backup-to-active switch occurs, the controller automatically switches data exchange
between its variables and the newly active PPRF. The controller application
takes no part in backup switching and does not have to supply PPRF-specific,
separate variables for each PROFIBUS I/O point.
Note If there is a partial PROFIBUS network failure, where both packs are able to
communicate with different subsets of slave devices, I/O is only transferred with the
slave devices that the primary master has access to. At the same time, the backup
master does not try to transfer I/O to the slave devices it is connected to, unless a
backup-to-active master switch is initiated. However, if this is done, transfers take place
only with the slave devices connected to the newly active pack.

Notes

PPRO Backup Turbine Protection Module
Turbine Protection (PPRO)

The Emergency Turbine Protection I/O pack (PPRO) and associated terminal boards
PROTECTION I/O
provide an independent backup overspeed protection system with a backup check for
PWR
RUN generator Synchronization to a utility bus. They also provide an independent watchdog
ATTN
ESTP
function for the primary control. A typical protection system consists of three triple
modular redundant (TMR) PPRO I/O packs mounted to a separate simplex protection
LINK ENET (SPRO) terminal board. A cable, with DC-37 pin connectors on each end, connects each
OSPD
1
TxRx SPRO to the designated emergency trip board:
WSOG
LINK
SYNC
ENET • TREG: Gas Turbine Emergency Trip Terminal Board
2
TxRx
OPT • TREL: Large Steam Turbine Emergency Trip Terminal Board
IR PORT
• TRES: Small/Medium Steam Turbine Emergency Trip Terminal Board
• TREA: Turbine Emergency Trip Terminal Board
IS220PPROH1A
IS220PPROS1A
An alternate arrangement puts three PPRO I/O packs directly on TREA for a
single-board TMR protection system. The PPRO has an Ethernet connection for IONet
Infrared Port Not Used communications with the control modules.
The Mark* VIe control is designed with a primary and backup trip system that
interacts at the trip terminal board level. Primary protection is provided with
the Turbine Primary I/O pack, PTUR, operating a primary trip board (TRPG,
TRPL, TRPS, TRPA). Backup protection is provided with the PPRO I/O pack
operating a backup trip board (TREG, TREL, TRES, TREA).
PPRO accepts three speed signals, including basic overspeed, acceleration, deceleration,
and a hardware implemented overspeed. The pack monitors the operation of the primary
control and can monitor the primary speed as a sign of normal operation. PPRO
monitors the status and operation of the selected trip board through a comprehensive
set of feedback signals. If a problem is detected, PPRO will trip the backup trip
relays on the trip board and activate a trip on the primary control. The pack is fully
independent of and unaffected by the primary control operation.
A maximum of three trip solenoids can be connected between the primary and emergency
trip terminal boards. Connecting a solenoid between the boards isolates the power on both
sides of the solenoid as well as visibility of solenoid voltage as a system feedback. The
primary/emergency trip boards TRPG/TREG, TRPL/TREL, and TRPS/TRES are designed
to operate as a pair and use cabling between the boards for system connections. TRPA
and TREA are designed with no pairing required and can be used independently of each
other. When TRPA and TREA are paired, they function the same as other board pairs.
The following figure shows how the TTUR and PPRO processor boards
share in the turbine protection scheme. Either one can independently trip
the turbine using the relays on TRPG or TREG.
GEH-6721L PPRO Backup Turbine Protection Module System Guide 18-1

PTUR PR3 TTUR
28 V dc control power in,
Ethernet Out PTUR PS3 Speed Inputs
PT Inputs
PTUR PT3
JR4
two
xfrs
37 pin cables
JS4
JT4 3 Relays
Gen Synch
335V dc Honeywell
Flame Detect Only
J3 J4 J5
JR1
TRPG
JS1
JT1
9 Relays
(3 x 3 PTRs)
125 V dc J1
J2
Cable Trip Solenoids,

three circuits
J2 J1 Trip signal to
JX1 TREG TSVO TBs
JY1
JZ1
37 pin cables
12 Relays
(9 ETRs,
JH1
3 Econ Relays)
P125 VDC
from <PDM>
SPRO
JA3 Speed Inputs
28 V dc control power in, PT Inputs
two
Ethernet Out PPRO JA1
xfrs
Note: Control power may
be separate or shared with JA3 SPRO Speed Inputs
main control depending on PT Inputs
reliability targets. two
PPRO JA1
xfrs
JA3 SPRO Speed Inputs

PT Inputs
two
PPRO JA1
xfrs
PPRO Turbine Control and Protection Boards

Compatibility
PPROH1A mounts directly on either SPRO or TREA. When mounted on SPRO,
it is cable-compatible with TREG, TREL, and TRES.
Terminal Board Compatibility
Board TMR Simplex Output Output ESTOP Input Input Economy

Contacts, Contacts, Contacts, Contacts, Resistor
125 V dc 24 V dc 125 V dc 24 V dc
TREGH1B Yes No Yes Yes Yes Yes No Yes
TREGH2B Yes No Yes Yes Yes No Yes Yes
TRELH1A Yes No Yes Yes No Yes No No
TRELH2A Yes No Yes Yes No No Yes No
TRESH1A Yes Yes Yes Yes No Yes No No
TRESH2A Yes Yes Yes Yes No No Yes No
TREAH1A Yes No No Yes Yes No No No
TREAH2A Yes No Yes No Yes No No No
TREAH3A Yes No No Yes Yes No No No
TREAH4A Yes No Yes No Yes No No No
Note The TREG H3, H4, and H5 versions are the same as the H1 except that power
is provided by JX1, JY1, or JZ1. TREA H3 and H4 are the same as H1 and H2 only
Euro versions.
Simplex Main Control

Simplex backup protection is supported by the Mark VIe trip board TRES.
One PPRO network port resides on the controller IONet.
TMR backup protection is supported by all Mark VIe backup trip boards,
TREG, TREL, TREA, and TRES. In this configuration, one port on each of
three PPRO I/O packs hooks into the controller IONet.

Dual Main Control
Simplex backup protection is supported by the Mark VIe trip board TRES. When
used in this configuration, the first network connection is to the R controller. The
second network connection is to the S controller. PPRO is then responsible for
monitoring the operation of both controllers. PPRO supports two options: The pack
trips if either controller malfunctions or both controllers malfunction.
TMR backup protection is supported by all Mark VIe backup trip boards, TREG,
TREL, TREA, and TRES. This configuration uses the dual controller TMR output
standard network connection. The first PPRO pack has one network port connected
to the R controller network. The second pack has one network port connected to
the S controller network. The third pack has one network port connected to the
R controller network and one network port connected to the S controller network.
The third PPRO monitors the operation of both controllers. The pack trips if
either controller malfunctions or both controllers malfunction.
Triple Main Control

Simplex backup protection is not supported as a simplex backup. One PPRO cannot
monitor the health of all three main controls and trip on loss of a single main control.
Therefore, one of the fundamental protection features cannot be met with a single pack.
TMR Backup protection is supported when operating with a TMR main control (two out
of three running). All Mark VIe backup trip boards (TREG, TREL, TREA, and TRES)
support this configuration. The normal network configuration connects the first PPRO pack
to the R network, the second pack to the S network, and the third pack to the T network.
Note PPRO TMR applications do not support dual network connections for all three
PPROs. In a redundant system there is no additional system reliability gained by
adding network connections to the first two PPROs with dual controllers or any of the
three PPROs with TMR controllers. The additional connections simply reduce mean
time between failures (MTBF) without increasing mean time between forced outages
(MTBFO).

Installation
The PPRO mounts directly to a Mark VIe SPRO or TREA terminal board. When mounted
on a SPRO board, cables with DC-37 pin connectors on both ends are required between
the SPRO board and the selected trip terminal board. The installation steps are as follows:
¾ To install the PPRO pack

1. Securely mount the SPRO or TREA terminal board. Mount the selected
trip terminal board if SPRO is used.
2. Connect cable, with DC-37 pin connectors on each end, between SPRO and
the selected trip terminal board if TREA is not used.
3. Directly plug one PPRO module into each SPRO, or three PPRO modules into TREA.
4. Slide the threaded posts on PPRO, located on each side of the Ethernet ports, into
the slots on the terminal board mounting bracket. Adjust the bracket location so the
DC-62 pin connector on PPRO and the terminal board fit together securely. Tighten
the mounting bracket. The adjustment should only be required once in the life of the
product. Securely tighten the nuts on the threaded posts locking PPRO in place.
5. Plug in one or two Ethernet cables depending on the system configuration.
The PPRO module is not sensitive to Ethernet connections and selects
the proper operation over either port.
6. Apply power to the module by plugging in the power connector on the
side of the module. The I/O module has inherent soft-start capability
that controls current levels upon application.
7. Use the ToolboxST* application to configure the module as necessary.

Wizard again.

Operation
Processor




Status LEDs
Processor LEDs

present.
Yellow TxRx Provided for each Ethernet port to indicate when the pack is transmitting or
receiving data over the port.
LED Status

Red LED out There are no detectable problems with the pack. All
ATTN
LED solid on A critical fault is present that prevents the pack from operating. 3.04 or earlier
There could be hardware failures on the processor or acquisition
boards, or there is not any application code loaded.
4 Hz 50% An alarm condition is present in the pack. These alarms include:
wrong pack / terminal board combination, terminal board is
missing, or errors in loading the application code.
1.5 Hz 50% The pack is not online
0.5 Hz 50% Flashing to draw attention to the pack. This is used during factory
testing.
ATTN
0.5 Hz 50% Application not loaded (pack)
Green Solid BIOS (at power on) - if it remains in this state, the pack is dead.
ATTN Older packs may not have the ability to display the green LED at
power on.
1 Hz 50% I/O pack in WAIT or STANDBY
every 4 sec

There are six LEDs on the front left side of the I/O pack to indicate trip status.
All six LEDs stay off until all I/O pack hardware application is complete. The
LEDs indicate trip status of the I/O pack as follows:
RUN is green any time the I/O pack has energized the emergency trip relays. RUN turns
red any time the I/O pack has removed power from the emergency trip relays, voting to trip.
ESTP is green when the ESTOP input (if applicable) is in the run state. ESTP turns red
any time ESTOP is invoked to prevent pick up of the emergency trip relays. If the chosen
trip terminal board does not support ESTOP, then the LED defaults to green.
OSPD turns red any time the I/O pack votes to trip in response to a detected
overspeed condition on any of the three speed inputs. OSPD is green when
an overspeed condition is not present or latched.
WDOG turns red any time there is an alarm in the I/O pack that has not been cleared.
WDOG turns green to indicate all alarms in the I/O pack have been cleared.
SYNC is green when generator and bus voltage is synchronized and matched
in amplitude. SYNC turns red when the I/O pack determines that ac bus and
generator bus voltage does not satisfy the synchronization requirements, and
synchronization has been requested by the system.
OPT is reserved for options that expand the capabilities of the I/O
pack. The default display is green.
During normal I/O pack operation, all six application LEDs display green. An
additional feature, rotating LEDs, can be configured for the I/O pack. Using this
feature, only one LED is turned on at a time and walked up and down the six
LEDs creating a synchronized motion. The walking is regulated by the controller
IONet and synchronized across a set of three I/O packs. This provides a quick
visual indication of the system time synchronization status.

The PPRO I/O pack has an internal application specific circuit board that contains the
hardware needed for the emergency trip function. The application board connects between
the processor and either the SPRO or TREA terminal boards. The board has provisions for
additional hardware expansion options. The options can be added to the I/O pack through
a dedicated header. The diagram on the following page shows the functions of this board.
3 Pulse Rate ID Chip

Input
Conditioning
D C - 6 2 To I / O Pack
2 PT Input
12 Digital Signal Processor
Inputs, Estop
7 Isolated
Contact Inputs
8 Relay
Command
Outputs Processor
Pass Through to Local Power

Option Supplies
Option Header
PPRO Application Specific Circuit Board
The processor and acquisition boards within the pack contain electronic ID parts that
are read during power application. A similar part located with each terminal board
connector allows the processor to confirm correct matching of the I/O pack to the
terminal board and to report board revision status to the system level control.
The pack includes power management in the 28 V input circuit. The management function
provides a soft-start feature to control current inrush during power application. After
power is applied, the circuit provides a fast current limit function to prevent a pack
or terminal board failure from generating back onto the 28 V power system. When
power is present and working properly the green PWR LED will light. If the current
limit function operates, the LED will be out until the problem is cleared.
Connectors
A DC-62 pin connector on the underside of the PPRO pack connects directly
to the terminal board. The connector contains the signals needed to sense
inputs and operate a trip terminal board.
An RJ45 Ethernet connector named ENET1 on the side of the pack

A second RJ45 Ethernet connector named ENET2 on the side of the pack
A 3-pin power connector on the side of the pack is for 28 V dc power

for the pack and terminal board.
Note If the trip terminal board features contact trip inputs, the power for those
contacts is provided through a separate terminal board connector, not from the 28 V dc
power source.

Protective Functions
The PPRO performs the following protective functions in a mix of hardware,
programmable logic, and firmware. In the following diagram, standard
symbols for time delay contacts have been used:
Normally Open Normally Closed Normally Open Normally Closed

Time Delay on Close Time Delay on Open Time Delay on Open Time Delay on Close
In the following diagrams, a standard has been used to indicate signal origin and flow.
• Signal names that end with (SS) are created within PPRO and the data
flow is out to the controller through signal space.
• Signal names that end with SS are created in the controller and the data
flow is into PPRO through signal space.
• Signal names that end with (IO) are created within PPRO and the
data flow is out to the hardware.
• Signal names that end with IO indicate the signal is a hardware input into PPRO.
• Signal names that end with anything containing CFG are part of the PPRO
configuration. In this case an attempt has been made to indicate what area
of the PPRO configuration contains the variable.
• When J3 is referenced in a CFG, it refers to the connection point for the trip relay
board, TREA, TREG, or TREL and the corresponding configuration values.
• The combination IO (SS) indicates a signal that comes from the hardware inputs
to PPRO, and is then sent out to the controller as part of signal space.
If there is no special ending on a signal name, then the signal is used internal to PPRO and
is not part of the hardware or signal-space data movement. This signal is not available or
visible to applications, but it is needed to adequately describe the packs operation.

The contact inputs include an 8 PPRO supports the seven isolated discrete contact input trip signals provided on the
ms contact de-bounce filter to TREG, TREL, and TRES boards. In the following figure, the direct / conditional
protect against false trips. determination is implemented in firmware while Contact#, and L5Cont#_Trip
are in hardware logic. When configured for direct trip, the firmware is not in
the trip path. When configured for conditional trip, the firmware determines the
communication health (shown as network_keepalive) and populates the programmable
logic with the conditional signal from signal space. If the controller communication
is lost, the default will permit any conditional trip.
A
network_keepalive
A>=B
B L3SS_Comm, (SS)
3
Trip#_Inhbt, SS L3SS_Comm, (SS) Inhbt#_Fdbk, (SS)

A
Trip_Mode, CFG (J3, Contact#) A=B
B Cont#_TrEnab,(SS)
Direct, CNST
A
A=B
B
Conditional, CNST Trip#_EnCon,(SS)
Contact#, (IO) Cont#_TrEnab

L5Cont#_Trip, (SS)
Includes 8mSec
CONTACT#
digital filter on close,
TRIP
no delay on open Trip#_EnCon Inhbt#_Fdbk, SS
L5Cont#_Trip, (SS) L86MR, SS
Note that the above contact circuit is duplicated seven times. Replace the symbol # with the
numbers 1-7 to obtain the correct signal name. Signals names without # in them appear only
once for all seven circuits (L3SS_Comm, L86MR).
PPRO Contact Input Trips

The resulting contact trip signals are combined into a single contact
trip summary, L5Cont_Trip.
L5Cont1_Trip (SS) L5Cont_Trip
L5Cont2_Trip (SS)
L5Cont3_Trip (SS)
L5Cont4_Trip (SS)
L5Cont5_Trip (SS)
L5Cont6_Trip (SS)
L5Cont7_Trip (SS)
Contact Input Trip Signal Concentration
ESTOP
PPRO monitors the ESTOP trip signal that is present on the TREG board and uses it
to cross trip the main control in the event ESTOP is invoked. It is also used within
the pack logic as part of the trip relay output command. The relays are not required to
close if the ESTOP signal is present. The main control counterpart is also present. If
the main control votes to trip, it can also cross-trip the corresponding PPRO.
Hw Estop1, IO J3 = TREG KESTOP1_Fdbk, (SS)
KESTOP1_Fdbk, (SS) L5ESTOP1, (SS)

ESTOP1
TRIP
L5ESTOP1, (SS) L86MR, SS
Note: There are several inversions in the hardware signal path, but the end result is that
KESTOP#_Fdbk is only a 1 when Estop is energized and TREG is used. In other words 1 = OK. Only
TREG has Estop, TREL and TRES do not have Estop as it is on primary trip boards TRPL and TRPS.
Contact Input ESTOP
Overspeed Trip
PPRO provides three speed input signals feeding firmware and hardware
overspeed protection. While PPRO documentation follows the established
standard of calling these three inputs HP, IP, and LP the three inputs are
free to be applied as needed in a system design.

OS1_Setpoint , SS
RPM A |A|
A
A-B A OS1_SP_CfgEr
A>B
OS_Setpoint, CFG (J5, PulseRate1)
B
RPM
1 RPM
B
System Alarm, if the two setpoint
do not agree
A
MIN
OS_Stpt_PR1 OS_Setpoint_PR1
A A
zero
MULT A A+B
0.04
B MIN B
OS_Tst_Delta, CFG (J5, PulseRate1)
B
RPM
OfflineOS1tst, SS
OnlineOS1
PulseRate1, IO
A
OS1
A>=B
OS_Setpoint_PR1
B
OS1_Trip
OS1
Overspeed
Trip
OS1_Trip L86MR, SS
Frame Rate
PulseRate1, IO
A -0 A
|A-B| A
Z
Speed1_Diff
Speed1, SS B OS_Diff, CFG (%) A>B
-1 B (A & B & C)
------------------------ * RatedRPM_TA, CFG (RPM) Z
100 B
-2 C
Z
SpeedDifEn, Card CFG
Speed1_Diff SpeedDifTrip
Enable
Overspeed
Difference Trip
SpeedDifTrip L86MR, SS
Speed1_Diff
TDPU
60 Sec
Firmware Overspeed Trip, HP Shaft

Firmware Overspeed Trip functions include:
• Fault on overspeed threshold match failure between config and

signal space values when speed is zero.
• Pick the lower threshold from config or signal space.
• Provide a mechanism to zero the threshold for online overspeed test.
• Provide a mechanism to modify the threshold for offline overspeed test,
bounded to limit increases to the threshold to 104%.
Note If you want to reduce the threshold to conduct tests, a negative OS_Tst_Delta
value is needed.
• Compare the threshold to the calculated speed and latch overspeed.
The following diagram displays the overspeed names used for the first of three pulse rate
inputs. The same figure is repeated for PulseRate2 and 3. For all variables where the
number 1 displays, simply substitute a 2 or 3 for the 1 to get the signal name.
OSHW_Setpoint1, SS
A
Generate an alarm if the hardware is
|A-B| A different than the firmware trip.
OSHW_Setpoint, CFG OS1HW_SP_CfgEr (SS)
B A>B
(PulseRate1)
1RPM
B
OS_Setpoint, Generate an alarm if the hardware
A setpoint changes after power-up.
HW Value
OS1HW_SP_Pend (SS)
|A-B|
PulseRate1,
A Note: OSHW_Setpoint only goes into
HWIO
the hardware at PPRO power-up.
A>=B
Changes to the value require a re-
B OS1HW boot or power cycle of the PPRO.
Hardware
Overspeed
OS1HW Trip
OS1HW_Trip
(SS)
OS1HW_Trip, (SS) L86MRX
Hardware Overspeed Trip, HP Shaft

Hardware Overspeed Trip functions include:
• Load the independent hardware overspeed set point only when the
PPRO pack re-boots or has power cycled
• Generate an alarm when the hardware config set point is >1 Hz different from the
value passed through signal space from the application configuration
• Generate an alarm and signal space Boolean when the set point in config
fails to match the value stored in the hardware
• Implement speed calculation and the trip logic entirely inside programmable logic
• Overspeed response time will be < 20 ms at trip speed
Note There is no separate enable /disable signal for this Overspeed protection. The
disable signal is created by setting a high overspeed point value. The calculated speed
will never reach the value needed to trigger OS1HW.
The actual hardware implementation depends on two configuration items:
• HWOS_Setpoint specifies the overspeed trip level in RPM.

• PRScale determines the number of speed sensor pulses per revolution used to convert
pulse rate into RPM for both hardware and firmware overspeed value.
Note If a hardware overspeed trip occurs followed by the abrupt removal of the speed
signal power, it can be necessary to cycle PPRO to reset the trip condition.
The hardware implementation requires two adjacent revolutions exceeding the

HWOS_Setpoint in order to trip the system. When a trip is present, the setting
of HWOS_Setpoint is reduced by a small amount in the hardware to provide a
clean trip signal. Due to this reduction, speed must be reduced well below the
overspeed threshold before a reset may take place. Because there are set limits
to the time integration used in the hardware detector, the minimum RPM setting
for the HWOS_Setpoint is approximately four RPM.

There is another protection function in addition to the overspeed protection shown
on the preceding page. It generates a signal in the event the first pulse rate signal is
above minimum speed, and the second pulse rate signal is still at zero.
PR1_MIN PR2_Zero, (SS)

LockRotorByp, SS LPShaftLock, (SS)
LPShaftLock, (SS) L86MR, SS

There should never be a reason why the speed calculated by the pack is significantly
different from the speed calculated by the main control. Speed difference detection looks
at the difference in magnitude between pulse rate 1 from both the pack and the main
control. If the difference is greater than the set threshold for three successive samples, a
SpeedDifTrip is latched. If the main control recovers for 60 seconds, the trip is removed.
This allows the main control to recover with subsequent re-arming of the backup protection.
PulseRate1, IO
A -0 A
Z
IA-BI A
-1 Speed 1_Diff
Speed1, SS B B (A&B&C)
OS_Diff, CFG (%) A>B Z
Rated RPM_TA,
-----------------------------
100 * CFG (RPM) B
Z
-2 C
SpeedDifEn , Card CFG
Speed1 _ Diff Speed_ Diff _ Trip Speed

Enable
Difference
Trip
L 86 MR, SS Speed1 _Diff
Close immediately , 60
sec delay on opening
Speed_ Diff_ Trip
Additional logic is added whenever dual control is used. When configured for
dual control, there are separate speed inputs from the two controllers that come
into the pack. This trip logic will act if both controllers have a speed error, but
will continue to run if one controller has a valid speed signal.

Maximum Speed Hold
The I/O pack provides a maximum speed hold function that resets when:
• Using the command PR_Max_RST (from signal space)

• PR1_Zero changes to false (you first start turning)
Output values are PR1_Max, PR2_Max, and PR3_Max. These signals are used to
determine the maximum speed obtained while running or after stopping a turbine.
Overspeed Test Logic, Steam Turbine

The signal OnLineOS1Tst is used for PulseRate1, OnLineOS2Tst is used for PulseRate2,
and OnLineOS3Tst is used for PulseRate3. In the following figure, there is another
signal, Online OS1X, which initiates an online overspeed test for PulseRate1. This
signal also creates a 1.5 second reset pulse when removed.
OnlineOS1Tst, SS Online_Overspeed_1_Test
OnlineOS1X, SS
OnlineOS1X, SS TDOSX
1.5 Second Delay L97EOST_ONLZ

TDOSX
OnlineOS1X, SS L97EOST_ONLZ L97EOST_RESET
L86MR, SS L86MRX
L97EOST_RESET
Online Overspeed Test Logic
Speed State Boolean Values

The I/O pack has detection for zero speed from a set point with 1 RPM hysteresis.
The pack calculates a minimum speed signal from a set point. The rate of change
of speed from a set point is calculated resulting in a selectable acceleration trip. A
deceleration trip is then determined from a fixed 100% / Second rate.

PR_Zero
1
Hyst
0
0
RPM
PulseRate 1, IO CFG
A
PR 1_ Zero
AB
Min_ Speed, CFG (J5, PulseRate1)
B
Speed Wheel Pulse
Detected Window
TDPU
“Inactive Counter”
AND
based on last speed 1 second
(max 24 secs)
AND
(Pulse rates in Hz) PR1_ DEC
A AND AND
75 Hz A>B
B
0
PR 2_ Accel
-3.4e38 A
S AB
Acc_Setpoint, CFG (J5, PulseRate2)
B
Dec1_Trip
PR1_DEC
Dec1_Trip L86MR, SS
Acc_Trip, CFG (J5, PulseRate1)
Acc1_Trip
PR1_ACC PR1_MIN Enable Acc1_TrEnab
Acc1_Trip L86MR, SS
*Note: Where 100% is define as the OS Setpoint
HP Shaft Accel Decel and Zero
The name of the first pulse rate input is shown in the above figure. The same figure is
repeated for PulseRate2 and 3. Simply replace the 1 with a 2 or 3 to get the signal name.
Note The contact, PR2-3_Min, in the Acc1_Trip is only present for PR2 (PR2_Min)
and PR3 (PR3_Min). It is not used for PR1.

Trip Anticipate Function
Steam turbine applications provide a speed trip that uses a live set point
from signal space. This overspeed trip is vigorously changed as a function
of turbine load. This function does the following:
• Input set point is OS1_TATrpSp from signal space. Input rated RPM is
specified by RatedRPM_TA as part of pack configuration. Function test
request input is TrpAntcptTst from signal space.
• If (OS1_TATrpSP is < 103.5% OR > 116% of RatedRPM_TA) then TA_Spd_Sp (the
local set point value) = 106% of RatedRPM_TA and TA_StptLoss (Signal space) is
true and alarm L30TA is declared. Otherwise, TA_Spd_Sp = OS1_TATrpSP.
• If TrpAntcptTst is true, decrease the current value of TA_Spd_Sp by 1RPM /
second. Set the minimum value of RatedRPM_TA to 94%. If TrpAntcptTst is
false, the value of TA_Spd_Sp from above is immediately used.
• If PulseRate1 (Speed input 1 from the pulse rate input) > TA_Spd_Sp
the internal value Trp_Anticptr is set properly.
• If the pack is configured for steam turbine application (internal value SteamTurbOnly),
then TA_Trip (signal space) equals the value of Trp_Anticptr.
The figure on the following page illustrates the function described above.
RatedRPM_TA, CFG (VPRO,

Config) RPM_94%
Calc Trip RPM_103.5%
Anticipate
speed RPM_106%
references RPM_116%
RPM_1%
RPM_116%
A
TA_StptLoss,SS
A<B Alarm
OS1_TATrpSp,SS RPM L30TA
B or
A
A<B
RPM_103.5% B
TA_Spd_SP
RPM_106%
RPM_1%/sec
Rate
TA_Spd_SP TA_Spd_SPX, RPM
Ramp A
Trp_Anticptr
Reset A<B
RPM_94%
(Out=In)
B
Hyst
TrpAntcptTst
RPM_1%
PulseRate1, IO, RPM
TA_Trip,SS
SteamTurbOnly Trp_Anticptr Trip Anticipator
Trip
L12TA_TP
Trip Anticipation Function

Solenoid Voltage / Power Sense
The I/O pack provides three comparator voltage inputs used to monitor solenoid power
or solenoid voltage depending on the trip card that is connected. SOL1_Vfdbk (SS),
SOL2_Vfdbk (SS), and SOL3_Vfdbk (SS) are generated from the input signals.
Main Control Watchdog

A standard control watchdog function is provided by the pack. In this function, a
value is passed from the main control to the pack each data frame. If the pack stops
seeing the value from the main control, a counter is incremented and, after five data
frames leads to a trip. If the main control recovers for 60 seconds, the trip is removed,
allowing for the recovery of the main control with subsequent re-arming of the backup
protection. The recovery function is provided for typical activities such as cycling
power on a controller to perform maintenance. While the controller is offline, the I/O
pack associated with that controller will vote to trip. When the controller returns to
operation, the pack will remove the vote to trip. The watchdog offers monitoring of
two main controls in the event both Ethernet ports are connected. When configured
for two controls, having one control active is sufficient to prevent a trip.
ContWdog, SS
A
5 CNTR = 5; Heart_Beat_Loss = 0
A == 1; CNTR = CNTR + 1 CNTR Heart_Beat_Loss
A != B A
-1 A == 0; CNTR = CNTR - 1 CNTR = 0; Heart_Beat_Loss = 1
B 0
Z
Toggle
IO Frame Rate ContWdogEn, Card CFG
Enable
ContWdogTrip
Heart_Beat_Loss
ContWdogTrip Heart_Beat_Loss
L86MR, SS
Control Watchdog Trip

Stale Speed Detection
The I/O pack provides an additional main control watchdog function that is based
on a live speed signal. The protection works as follows: If the pack PulseRate1 is
determined to be zero speed the protection is turned off. If above zero speed, the
pack looks at the value of Speed1 from the main control. If the most recent Speed1
value exactly matches the Speed1 value from the last data frame then a counter is
incremented. If the counter reaches a threshold then a stale speed trip is declared
and latched. If speeds are different the counter is cleared.
Although Speed_1, SS is available as a connected

variable, it should not be forced. It can cause the
protection to trip the system if enabled.
Attention
This protection is based on the knowledge that a live speed signal always dithers or moves
some small amount. The only way you will see consecutive signals with the same value for
a period of time is if the speed calculation or worse is not functioning in the main control.
If the main control recovers for 60 seconds, the trip is removed allowing for the recovery of
the main control with subsequent re-arming of the backup protection. The protection offers
monitoring of two main controls in the event both Ethernet ports are connected. When
configured for two controls, having one control satisfy the test is sufficient to prevent a trip.
PR1_Zero, (SS)
Speed1, SS
A A >= 100; Stale_Speed = 1
A == 1; CNTR = CNTR + 1
CNTR Stale_Speed
A A
A == B
A == 0; CNTR = 0
-1 A == 0; Stale_Speed = 0
Z B
Ratchet Counter Ratchet Toggle
Frame Rate StaleSpdEn, Card CFG
Enable StaleSpdTrip
Stale_Speed
StaleSpdTrip Stale_Speed
L86MR, SS
Stale Speed Trip

Main Control Ethernet Monitor
The main control provides time synchronization across the distributed control elements.
The time synchronization is tied tightly into the time at which traffic occurs on a given
controllers IONet. The I/O pack provides monitoring of this service to ensure it is working
correctly. Gross errors in time synchronization are detected by the pack through a number
of different means, and if problems persist, the I/O pack will vote to trip. Once the trip is
latched, if the problem goes away for 60 seconds the trip shall be reset (this assumes the
control recovers from the problem and is back on line). The monitor will offer monitoring
of two main controls in the event both Ethernet ports are connected. When configured for
two controls, having one control sequencing correctly is sufficient to prevent a trip.
In the following diagram, the detection has been simplified to show monitoring of an
Ethernet frame number as the means for determining a problem is present.
Sync_Frame_Number, SS
A
5 CNTR >= 5;
A == 0; CNTR = CNTR + 1 CNTR Frame_Sync_Error=1 Frame_Sync_Error
A = B+1 A
-1 A == 1; CNTR = 0 CNTR = 0; Frame_Sync_Error=0
B 0
Z
Toggle
Frame Rate FrameSyncEnabl, Card CFG
Enable FrameSyncTrip
Frame_Sync_Error
FrameSyncTrip Frame_Sync_Error
L86MR, SS
Sync Frame Court Monitor
Trip Signal Logic

The different trip signals are combined into a composite signal that is used in the
relay output logic. The following figure shows how the signals are combined.
This function is partitioned between firmware and programmable logic. The
path to trip through hardware overspeed is done completely in hardware so that a
firmware malfunction cannot defeat the protection. The same is true of the contact
input trip signals when they are configured for direct trip.
There are differences between steam turbine protection and other protection. A
composite signal SteamTurbOnly is created for ease of use:
LargeSteam*
MediumSteam* * A number of
contacts depend on
SmallSteam* the value of
Turbine_Type, CFG
SteamTurbOnly
Steam Turbine Trip Signals

Dec1_Trip
OS1_Trip
Acc1_Trip PulseRate1
L5CFG1_Trip Trips
Dec2_Trip
OS2_Trip GT_2Shaft*
PulseRate2
Trips
Acc2_Trip
L5CFG2_Trip LM_2Shaft*
LPShaftLocked LM_3Shaft* ComposTrip1,

(SS)
Dec3_Trip
OS3_Trip PulseRate3
Trips
LM_3Shaft*
Acc3_Trip
L5CFG3_Trip
L5Cont_Trip
SpeedDifTrip
Cross_Trip, SS System
Trips
StaleSpdTrip
ContWdogTrip
FrameSyncTrip
LM_2Shaft* LM_3Shaft* PR1_Zero
Zero
Speed
Special
LMTripZEnable, CFG HPZeroSpdByp SteamTurbOnly* Case
SS
L3Z
Hardware
Overspeed
OS1HW_Trip
OS2HW_Trip
OS3HW_Trip * CFG values
Trip Combine (All Signals [SS] unless Marked)

Watchdog
Hardware in the pack monitors operation of the local firmware and provides a
watchdog trip function in the event of a firmware malfunction. The operation of
this watchdog does not show up in the normal sequencing figures. The I/O pack
hardware is designed to be in a fail-safe or trip mode if it is not properly configured
and operating. This means that with power off, while starting up, when in a hardware
reset, or otherwise not online, the pack will vote to trip. If the pack watchdog
acts, it will reset the hardware thereby generating a vote to trip.
It should also be noted that the processor board used inside the pack has hardware features
that allow the processor to differentiate between a reset caused by the watchdog hardware
and a reset caused by cycling of power. This information is available from the pack after
it re-starts. In the event that a pack votes to trip due to a reset, it is then possible to
determine if a watchdog reset or a cycling of control power caused the event.
Sync Check and K25A Sync Relay Command

The pack provides two PT inputs and performs a backup synchronizing check. SPRO
does not use fanned PT inputs; there are three direct PT paths.
CFG(J3, K25K_Fdbk)
SyncCheck(Used, Unused)
SystemFreq(50,60)
VoltageDiff
TurbRPM
ReferFreq
FreqDiff
PhaseDiff
GenVoltage
BusVoltage GenFreq, (SS)
Sync Check
SynCk_Perm, SS Function BusFreq, (SS)
Slip GenPT_KVolts, (SS)
SynCk_ByPass, SS
BusPT_KVolts, (SS)
DriveFreq, SS Phase GenFreqDiff, (SS)
GenPhaseDiff, (SS)
GenPT_KVolts, IO GenVoltsDiff, (SS)

Sync
BusPT_KVolts, IO
Window
L25A_Cmd, (IO)(SS)
The pack provides a command to monitor feedback for the K25A sync relay and
K25A coil. The feedback is named K25A_Fdbk, (SS).
K25A
L25A_ Cmd, (IO)(SS) K25A_ Enab, (SS)
Used
Sync Check Relay,
Energize to Close
SyncCheck , CFG (J3, K25A_ Fdbk) Breaker, K25A
On TTUR through TREG
Sync Check and K25A Sync Relay Command

Servo Suicide Relay Command
The I/O pack provides a command to a servo suicide relay, and provides coil-monitoring
feedback named K4CL_Fdbk, (SS). This signal is typically used in a simplex
control of a gas turbine system where it is highly desirable for the pack emergency
protection to have a hardware path to close the fuel valves.
Compos Trip 1, ( SS ) K 4 CL _ Enab , ( SS ) Online OS 1 Tst , ( SS ) K 4 CL , ( 10 )
Used
Servo Clamp Relay
Energize to Clamp
RelayOutput , CFG ( J 3 , K 4 CL _ Fdbk ) K 4 CL
Servo Suicide Relay Command
Trip and Economizing Relay Outputs

The I/O pack provides drivers for three emergency trip relay commands, and provides
monitoring for three status feedback signals. Trip is a combination of firmware trip
and direct trip implemented in programmable logic. The pack contains drivers for
three economizing relay commands and monitoring for three status feedback signals.
Economizing relays are used when it is desirable to introduce some series resistance
in a solenoid coil path to reduce current once the solenoid is picked up. Logic for the
economizing relay drivers is a time-delayed copy of the emergency trip relays as shown.
Note The reset signal applied to this function is not edge triggered. A continuously
applied reset can result in output cycling in the presence of an intermittent trip signal.
The duration of the reset should only be sufficient to allow the reset to complete and
should not be maintained.

TA_Trip, (SS) TestETR1 ComposTrip1 ETR1_Enab L5ESTOP1(SS) ETR1 (IO)
Energize to Run,
TA_Trip_Enabl1 TRES, TREL Used
CFG (PPRO)
ETR1 SOL1_Vfdbk KE1_Enab TD_KE1

IO (SS) CFG, KE1_Fdbk
2 Second Delay on Pickup
KE1 (IO)
Economizing Relay,
TD_KE1 Energize to Econ,
TA_Trip(SS) TestETR2 ComposTrip1 ETR2_Enab L5ESTOP1(SS) ETR2 (IO)

Energize to Run,
CFG (PPRO)

KE2 (IO)
Economizing Relay,
L97EOST_ONLZ Large Steam

CFG
TA_Trip(SS) ComposTrip1 TestETR3 ETR3_Enab L5ESTOP1(SS) ETR3 (IO)

(SS) SS CFG, K3_Fdbk Trip Relay,
Energize to Run,
CFG (PPRO)

KE3 (IO)
Economizing Relay,
Note: TREL, TRES, and TREA do not have economizing relays so the KE1, KE2, and KE3 drivers are not
not used when those boards are configured. Estop is only on TREG and TREA so it is bypassed when driving
ETR1-3 with TREL and TRES.
Trip and Economizing Relay Outputs

Specifications
Item PPRO Specification
Speed Input Quantity Three input signals provided
Speed input Range Pulse rate frequency range 2 Hz to 20 kHz
Speed Input Accuracy Pulse rate accuracy 0.05% of reading
Speed Input Sensitivity Required peak-peak voltage rises as a function of frequency
6 kHz- 10 kHz requires 100 mV
Generator and Bus Voltage Inputs Input voltage range 75 to 130 V rms. Loading less than 3 VA.
Frequency accuracy 0.05% over 45 to 66 Hz range.
Frame Rate 100 Hz maximum
Pulse Duration Limitation Trip contact input can only be detected if the pulse contact is greater than 8 ms.
Physical
Environment
Temperature Operating: -30 to 65ºC (-22 to 149 ºF)
Temperature Shipping and Storage: -40 to 80ºC (-40 to 176 ºF)
Air Quality Pollution Degree 2, free convection at the module
Vibration
Seismic Universal Building Code (UBC) – Seismic Code section 2312 Zone 4 with operation
without trip
Shipping (by road) Bellcore GR-63-CORE Issue 1, 1995 0.5 g, 5-100 Hz, 10 min. per octave, 1
sweep/axis x 3 axes, ~ 42 min./axis
3 shocks of 15 g, 2 ms impulse each repeated for all axes
Operating at site 1.0 g horizontal. 0.5 g vertical at 15 to 120 Hz
IEC 60721-3-2
Agency Approvals
Safety Standards UL 508A Safety Standard Industrial Control Equipment
CSA 22.2 No. 14 Industrial Control Equipment
EN 61010-1 Safety of Electrical Equipment, Industrial Machines (Low Voltage
Directive)

Item PPRO Specification
Printed Wire Board Assemblies UL 796 Printed Circuit Boards
UL recognized Board manufacturer
ANSI IPC guidelines
ANSI IPC/EIA guidelines
Electromagnetic Compatibility (EMC) EN 61000-4-2 Electrostatic Discharge Susceptibility
EN 6100 4-3 (ENV 50140) Radiated RF Immunity
EN 61000-6-2 Generic Immunity Industrial Environment
EN 61000-4-4 Electrical Fast Transient Susceptibility
EN 61000-4-5 Surge Immunity
EN 61000-4-6 Conducted RF Immunity
EN 55011 Radiated and Conducted RF Emissions
ANSI/IEEE C37.90.1 Surge
Note Speed input sensitivity is such that turning gear speed may be observed on a
Diagnostics

• A check of the analog feedback currents
• A comparison between the commanded state of each relay drive and the
feedback from the commanded output circuit

with the RESET_DIA signal if they go health.

Configuration

TurbineType Turbine Type and Trip Solenoid Configuration Unused, GT_1Shaft, LM_3Shaft,
MediumSteam, SmallSteam,
GT_2Shaft, Stag_GT_1Sh,
Stag_GT_2Sh, LargeSteam,
LM_2Shaft
LMTripZEnabl On LM machine, when no PR on Z,Enable a vote for Trip Disable, Enable
TA_Trp_Enab1 Steam, Enable Trip Anticipate on ETR1 Disable, Enable
ContWdogEn Enable trip on loss of Control Outputs to PPRO Disable, Enable
SpeedDifEn Enable Trip on Speed Difference between Controller and PPRO Disable, Enable
StaleSpdEn Enable Trip on Speed from Controller Freezing Disable, Enable
DiagSolPwrA When using TREL/TRES, Sol Power, Bus A, Diagnostic Enable Disable, Enable
DiagSolPwrB When using TREL/TRES, Sol Power, Bus B, Diagnostic Enable Disable, Enable
DiagSolPwrC When using TREL/TRES, Sol Power, Bus C, Diagnostic Enable Disable, Enable
FrameMonEn Enable trip when IO-Net frame synchronization is lost Disable, Enable
Redundancy Redundancy mode of the module Simplex, DUAL, TMR
RotateLeds Rotate the Status LEDs if all status are OK Disable, Enable
LedDiags Generate diag alarm when LED status lit Disable, Enable
RatedRPM_TA Rated RPM, used for Trip Anticipater and for Speed Diff Protection
AccelCalType Select Acceleration Calculation Time (msec)
OS_Diff Absolute Speed Difference in Percent For Trip Threshold
Terminal Board_SPRO (MainVer_1)

PulseRate1 HP speed AnalogInput REAL
PulseRate2 LP speed AnalogInput REAL
PulseRate3 IP speed AnalogInput REAL
BusPT_KVolts Kilo-Volts RMS AnalogInput REAL
GenPT_KVolts Kilo-Volts RMS AnalogInput REAL

Terminal Board_TREA (MainVer_1)

PulseRate1 HP speed AnalogInput REAL
PulseRate2 LP speed AnalogInput REAL
PulseRate3 IP speed AnalogInput REAL
Fan_Spd_Fbk Fanned Speed Signal Feedback :- Fanned = Jumpers Closed Input BOOL
NotUsedA1 and A2 Kilo-Volts RMS AnalogInput REAL
KESTOP1_Fdbk ESTOP1,inverse sense,True = Run Input BOOL
NotUsedA3 through A9 Contact Input 1 through 7 Input BOOL
K1_Fdbk L4ETR1_FB, Trip Relay 1 Feedback Input BOOL
NotUsedA10 L4ETR3_FB, Trip Relay 1 Feedback Input BOOL
NotUsedA11 through When TREG, Current Economizing Relay for Trip Solenoid 1-3 Input BOOL
A13
NotUsedA14 Drive Control Valve Servos Closed. Input BOOL
NotUsedA15 Synch Check Relay Input BOOL
VSen1 Voltage Sensor 1 Feedback Input BOOL
VSen2 Voltage Sensor 2 Feedback Input BOOL
VSen3 Voltage Sensor 3 - Power Monitor Feedback Input BOOL
Terminal Board_TREG (AuxVer_1)

KESTOP1_Fdbk ESTOP1, inverse sense,K4 relay,True = Run Input BOOL
Contact1 through 7 Contact Input 1 through 7 Input BOOL
KE1_Fdbk Current Economizing Relay for Trip Solenoid 1 Input BOOL
K4CL_Fdbk Drive Control Valve Servos Closed. Input BOOL
K25A_Fdbk Synch Check Relay Input BOOL

Terminal Board_TREL (AuxVer_1)

NotUsed1 Placeholder for Estop, not used on TREL Input BOOL
NotUsed2 When TREG, Current Economizing Relay for Trip Solenoid 1 Input BOOL
K4CL_Fdbk Drive Control Valve Servos Closed Input BOOL
Terminal Board_TRES (AuxVer_1)

NotUsed1 Placeholder for Estop, not used on TREL Input BOOL
K4CL_Fdbk Drive Control Valve Servos Closed Input BOOL

Modules_PPRO_Variables
L3DIAG_PPRO_R,_S, and _T I/O Diagnostic Indication Input BOOL
LINK_OK_PPRO_R,_S, and _T I/O Link Okay Indication Input BOOL
ATTN_PPRO_R,_S, and _T I/O Attention Indication Input BOOL
PS18V_PPRO_R,_S, and _T I/O 18 V Power Supply Indication Input BOOL
PS28V_PPRO_R,_S, and _T I/O 28 V Power Supply Indication Input BOOL
IOPackTmpr_R,_S, and _T IO Pack Temperature (deg °F) AnalogInput REAL
K1_FdbkNV_R,_S, and _T Non Voted L4ETR1_FB, Trip Relay 1 Feedback Input BOOL
K1FLT K1 Shorted Contact Fault Input BOOL
K2FLT K2 Shorted Contact Fault Input BOOL
PR1_Zero L14HP_ZE Input BOOL
OS1_Trip L12HP_TP Input BOOL
Dec1_Trip L12HP_DEC Input BOOL
Acc1_Trip L12HP_ACC Input BOOL
TA_Trip Trip Anticipate Trip, L12TA_TP Input BOOL
TA_StptLoss L30TA Input BOOL
OS1HW_Trip L12HP_TP Input BOOL
SOL1_Vfdbk When TREG, Trip Solenoid 1 Voltage Input BOOL
L25A_Cmd L25A Breaker Close Pulse Input BOOL
Cont1_TrEnab through 7 Config – Contact 1 Trip Enabled through 7 Input BOOL
Acc1_TrEnab through 3 Config – Accel 1 Trip Enabled through 3 Input BOOL
GT_1Shaft Config – Gas Turb, 1 Shaft Enabled Input BOOL
GT_2Shaft Config – Gas Turb, 2 Shaft Enabled Input BOOL
LM_2Shaft Config – LM Turb, 2 Shaft Enabled Input BOOL
LM_3Shaft Config – LM Turb, 3 Shaft Enabled Input BOOL

LargeSteam Config – Large Steam 1, Enabled Input BOOL
MediumSteam Config – Medium Steam Enabled Input BOOL
SmallSteam Config – Small Steam Enabled Input BOOL
Stag_GT_1Sh Config – Stag 1 Shaft, Enabled Input BOOL
Stag_GT_2Sh Config – Stag 2 Shaft, Enabled Input BOOL
ETR1_Enab Config – ETR1 Relay Enabled Input BOOL
OS1HW_SP_Pend Hardware HP overspeed setpoint changed after power up Input BOOL
OS2HW_SP_Pend Hardware LP overspeed setpoint changed after power up Input BOOL
OS3HW_SP_Pend Hardware IP overspeed setpoint changed after power up Input BOOL
KE1_Enab Config – Economizing Relay 1 Enabled Input BOOL
OS1HW_SP_CfgErr Hardware HP Overspd Setpoint Config Mismatch Error Input BOOL
OS2HW_SP_CfgErr Hardware LP Overspd Setpoint Config Mismatch Error Input BOOL
OS3HW_SP_CfgErr Hardware IP Overspd Setpoint Config Mismatch Error Input BOOL
K4CL_Enab Config – Servo Clamp Relay Enabled Input BOOL
K25A_Enab Config – Synch Check Relay Enabled Input BOOL
L5CFG1_Trip HP Config Trip Input BOOL
L5CFG2_Trip LP Config Trip Input BOOL
L5CFG3_Trip IP Config Trip Input BOOL
OS1_SP_CfgEr HP Overspd Setpoint Config Mismatch Error Input BOOL
OS2_SP_CfgEr LP Overspd Setpoint Config Mismatch Error Input BOOL
OS3_SP_CfgEr IP Overspd Setpoint Config Mismatch Error Input BOOL
ComposTrip1 Composite Trip 1 Input BOOL
L5ESTOP1 ESTOP1 Trip Input BOOL
L5Cont1_Trip through 7 Contact 1 Trip 7 Input BOOL
LPShaftLock LP Shaft Locked Input BOOL
Inhbt1_Fdbk through 7 Trip Inhibit Signal Feedback for Contact 1 through 7 Input BOOL
L3SS_Comm Communication Fault Input BOOL
Trip1_EnCon through 7 Contact 1 Trip Enabled through 7 – Conditional Input BOOL
BusFreq SFL2 hz AnalogInput REAL
GenFreq DF2 hz AnalogInput REAL
GenVoltsDiff DV_ERR KiloVolts rms - Gen Low is Negative AnalogInput REAL
GenFreqDiff SFDIFF2 Slip hz - Gen Slow is Negative AnalogInput REAL

GenPhaseDiff SSDIFF2 Phase degrees - Gen Lag is Negative AnalogInput REAL
PR1_Accel HP Accel in RPM/SEC AnalogInput REAL
PR2_Accel LP Accel in RPM/SEC AnalogInput REAL
PR3_Accel IP Accel in RPM/SEC AnalogInput REAL
PR1_Max HP Max Speed since last Zero Speed in RPM AnalogInput REAL
PR2_Max LP Max Speed since last Zero Speed in RPM AnalogInput REAL
PR3_Max IP Max Speed since last Zero Speed in RPM AnalogInput REAL
SynCk_Perm L25A_PERM - Sync Check Permissive Output BOOL
SynCk_ByPass L25A_BYPASS - Sync Check ByPass Output BOOL
Cross_Trip L4Z_XTRP - Control Cross Trip Output BOOL
OnLineOS1Tst L97HP_TST1 - On Line HP Overspeed Test Output BOOL
OnLineOS2Tst L97LP_TST1 - On Line LP Overspeed Test Output BOOL
OnLineOS3Tst L97IP_TST1 - On Line IP Overspeed Test Output BOOL
OffLineOS1Tst L97HP_TST2 - Off Line HP Overspeed Test Output BOOL
OffLineOS2Tst L97LP_TST2 - Off Line LP Overspeed Test Output BOOL
OffLineOS3Tst L97IP_TST2 - Off Line IP Overspeed Test Output BOOL
TrpAntcptTst L97A_TST - Trip Anticipate Test Output BOOL
LokdRotorByp LL97LR_BYP - Locked Rotor Bypass Output BOOL
HPZeroSpdByp L97ZSC_BYP - HP Zero Speed Check Bypass Output BOOL
PTR1 L20PTR1 - Primary Trip Relay CMD, for Diagnostic only Output BOOL
PR_Max_Rst Max Speed Reset Output BOOL
OnLineOS1X L43EOST_ONL - On Line HP Overspeed Test, with auto reset Output BOOL
TestETR1 L97ETR1 - ETR1 test, True de-energizes relay Output BOOL
Trip1_Inhbt through 7 Contact 1 Trip Inhibit through 7 Output BOOL
OS1_Setpoint HP Overspeed Setpoint in RPM AnalogOutput REAL
OS2_Setpoint LP Overspeed Setpoint in RPM AnalogOutput REAL
OS3_Setpoint IP Overspeed Setpoint in RPM AnalogOutput REAL
OS1_TATrpSp PR1 Overspeed Trip Setpoint in RPM for Trip Anticipate Fn AnalogOutput REAL
DriveFreq Drive (Gen) Freq (hz), used for non standard drive config AnalogOutput REAL
Speed1 Shaft Speed 1 in RPM AnalogOutput REAL
OSHW_Setpoint1 HP Overspeed Setpoint in RPM AnalogOutput REAL
OSHW_Setpoint2 LP Overspeed Setpoint in RPM AnalogOutput REAL
OSHW_Setpoint3 IP Overspeed Setpoint in RPM AnalogOutput REAL
ContWdog Controller Watchdog Counter Output DINT

TPROH#C Emergency Protection
TPROH#C is not supported The Emergency Protection (TPRO) terminal board hosts three PPRO I/O packs.
by the Mark VI control. It conditions speed signal inputs for the PPROs and contains a pair of potential
transformers (PTs) for bus and generator voltage input. It has three DC-37 pin
connectors, each adjacent to the PPRO pack connectors. Each DC-37 accepts a
cable leading to a Mark* VIe backup trip relay terminal board.
• TPROH1C features two 24 barrier terminals, each in a pluggable block

• TPROH2C features two 24 pluggable Euro-style box terminals


Compatibility
TPROH#C works with the PPRO I/O pack and supports simplex and TMR
applications. In TMR systems, TPROH#C connects to three PPRO I/O packs. Both
TPROH1CD and H12C accept direct mounting of three PPROH1As and provide DC-37
connectors for three cables to the selected backup trip relay terminal boards. TPRO
is cable-compatible with the trip boards listed in the following table.

125 V dc 24 V dc 125 V dc 24 V dc Resistor
TREGH1A Yes No Yes Yes Yes Yes No Yes
TRESH1A Yes No Yes Yes No Yes No No
TRESH2A Yes No Yes Yes No No Yes No

Installation
The TPROH1C or TPROH2C and a plastic insulator mount on a sheet metal carrier,
which mounts on a DIN-rail. Optionally, the TPRO and insulator mount on a sheet
metal assembly, which bolts directly in a panel. Speed signals and PT inputs are
wired directly to the terminal block using typical #18 AWG wires. The TPROH1C
barrier terminal block is removable for board replacement. The TPROH2C is a
pluggable Euro-Block type terminal block with removable terminals.
The R, S and T PPRO I/O packs mount on TPRO connectors JR1, JS1 and JT1,
respectively. Three DC-37 pin conductor cables plug into TPRO connectors JX1, JY1
and JZ1 with the other ends attached to the selected backup trip terminal boards.

Transformers
Jumper
connections
Cold Junctions
(only 3 used at a
time)
Mag pickups
TPROH#C Terminal Board

The following figure shows how TPRO and three PPROs are connected to a trip
relay board for the backup protection in a Mark VIe control system. PTUR, TTUR
and a primary trip relay terminal provide primary protection.
Turbine Control and Protection Boards

Operation
In the following drawing, the PT inputs to TPRO are shown on terminals 1-4.
TPRO Signal Inputs
For terminal 8 (MARET) to Nine speed inputs are shown on terminals 31-48. Terminals 5, 9, and 11 offer P24 output
act as the return path for for the customer. Terminal 8 (MARET) acts as the return path for the P24 output. The P24
24 V output and 4-20 mA output is derived by ORing the 28 V power supply of I/O packs R, S, and T. If any of the
input, ensure that JP1B is I/O pack are switched off, P24 V output can still be sourced. Terminals 6, 10, and 12 are
at position (1-2). 4-20 mA inputs, are reserved for future control expansions, and are fanned to R, S, and T
PPRO connectors. Terminal 8 (MARET) acts as return path for the 4-20 mA input.
Similarly, terminals 13 through 30 are thermocouple inputs reserved for future KPRO
expansion. The operator must select between 4-20 mA and thermocouple inputs,
but not both. Jumpers JPX, JPY, JPZ along with jumpers JP1A and JP1B facilitate
this choice. If speed inputs are TTL-based, then TB3 terminals are used along with
even-numbered terminals 32-48, as shown in the following table.

Input Signal TBConnector Terminal Number Description
PulseRate1 MAG1TTL_R TB3 1 For TTL input High
MX1L TB2 32 Return for TTL input
MAG1TTL_S TB3 4 For TTL input High
MY1L TB2 38 Return for TTL input
MAG1TTL_T TB3 7 For TTL input High
MZ1L TB2 44 Return for TTL input
P24V1 TB1 5 For TTL input Sensor Power
MARET TB1 8 For TTL input Sensor Power Return

Specification
Item Specification
Generator and bus voltage sensors Two single-phase potential transformers, with secondary output supplying a
nominal 115 V rms
Each input has less than 3 VA of loading.
Allowable voltage range for synch is 75 to 130 V rms
Each PT input is magnetically isolated with a 1,500 V rms barrier.
Cable length can be up to 1,000 ft. of 18 AWG wiring.
Magnetic speed pickup pulse rate range 2 Hz to 20,000 Hz
Magnetic speed pickup pulse rate accuracy 0.05% of reading
0 — 2 kHz requires 27 mV
2 k Hz — 6 kHz requires 50 mV
above 15 kHz requires 250 mV
P24V1 There are three 24 V outputs for customer (not voted), with each supporting a
P24V2 max current output of 25 mA.
P24V3
Diagnostics
The TPRO board and backup trip relay terminal board contain electronic ID parts that
are read during power initialization. This information is used by PPRO to confirm
a valid hardware arrangement prior to starting normal operation.
Configuration
JPX, JPY and JPZ jumpers should ALL be in the (1, 4, 7, 10) position when thermocouple
inputs are used OR ALL in the (3, 6, 9, 12) position when 4-20 mA inputs are used.
JP1A jumper position (1, 2) selects the 4-20 mA input from input terminal TB1-6. JP1A
jumper position (2, 3) selects the VDC input from input terminal TB1-7. JP1B should
be in the standard (1, 2) position by default. The (2, 3) position (no connect) is used
when a 4-20 mA signal is used from the field when the sensor itself is powered by
the customer. Therefore, the customer is offering a differential signal pair (I20MA1,
MARET) to be processed differentially, in which MARET must be kept floating.

TREA Turbine Emergency Trip
The Aeroderivative Turbine Emergency Trip (TREA) terminal board works
with PPRO and YPRO turbine I/O packs as part of the Mark VIe or Mark VIeS
system respectively. The inputs and outputs are as follows:
• Customer input terminals provided through two 24-point pluggable barrier

terminal blocks (H1A or S1A, H2A or S1A) or 48 pluggable Euro-style
box terminals (H3A or S3A, H4A or S4A).
• Nine passive pulse rate devices (three per X/Y/Z section) sensing a
toothed wheel to measure the turbine speed.
• Jumper blocks that enable fanning of one set of three speed inputs to
all three PPRO or YPRO I/O packs.
• Two 24 V dc (H1A / S1A, H3A / S3A) or 125 V dc (H2A / S2A, H4A /
S4A) TMR voted output contacts to trip the system.
• Daughterboards connectors for optional feature expansion.
For TMR systems, signals fan out to the JX1, JY1, and JZ1 DC-62
PPRO or YPRO connectors.



JZ1
62-pin D shell
connector. Plug
the I/O packs
K1
K1
K1
K1
K1
K1
into JX1, JY1, &
JZ1
TB1
Solid-state trip
relays K1 & K2
JY1
K2
K2
K2
K2
K2
K2
J2
Optional daughterboard
P2 plugs onto J1 and
J2 connectors
JX1
TB2
P1
J1
Barrier or box terminals Place jumpers over P1,P2 pin

can be unplugged from pairs to fan JX set of magnetic
board for maintenance speed inputs to JY and JZ
TREA1A Turbine Terminal Board

Board Mark VIe control Mark VIeS Safety Features

Revision IS220PPRO control
IS200YPRO
TREAH1A Yes, all versions No 24 V dc - Barrier Connectors
TREAH2A Yes, all versions No 125 V dc - Barrier Connectors
TREAH3A Yes, all versions No 24 V dc - Euro Connectors
TREAH4A Yes, all versions No 125 V dc - Euro Connectors
TREAS1A Yes, all versions Yes, all versions 24 V dc - Barrier Connectors, safety certified
TREAS2A Yes, all versions Yes, all versions 125 V dc - Barrier Connectors, safety certified
TREAS3A Yes, all versions Yes, all versions 24 V dc - Euro Connectors, safety certified
TREAS4A Yes, all versions Yes, all versions 125 V dc - Euro Connectors, safety certified
Installation
For H1 / S1 and H2 / S2 board variants, voltage detection and the breaker relay
are wired to the I/O terminal blocks TB1. Passive pulse rate pick-ups are wired to
TB2. Each block is held down with two screws and has 24 terminals accepting
up to #12 AWG wires. A shield termination strip attached to chassis ground
For H3 / S3 and H4 / S4 board variants, voltage detection and the breaker relay
are wired to the I/O box terminals at the top of the board. Passive pulse rate
pick-ups are wired to the lower terminals. All terminals plug into a header on
the TREA board and accept up to a single #12 AWG wire.
The TREA must be configured for the desired speed

input connections using the following table. Jumpers P1
and P2 select fanning of the X section pulse rate pickups
to the Y and Z PPROs / YRPOs.
Caution
Speed Input Connections Function Jumper

Wire to all 9 pulse inputs: Each set of three pulse inputs goes to its own Cannot use jumper: place in
PR1_X – PR3_Z dedicated I/O pack. STORE position.
Wire to bottom 3 pulse inputs only: The same set of signals are fanned to all the Use jumper: place over pin pairs.
PR1_X – PR3_X. NO wiring to I/O packs.
PR1_Y-PR3_Z

Screw terminal connections are listed in the following table. Terminal names starting
with DBRD are reserved for the addition of an optional daughterboard.
TREA Terminal Board Wiring
Pin Signal Name Pin Signal Name

1 K1_PDC 2 K1_NDC
3 K2_PDC 4 K2_NDC
5 SOL1_A 6 SOL1_B
7 SOL2_A 8 SOL2_B
9 PWR_A 10 PWR_B
11 TRP_A 12 TRP_B
13 K4_PDC 14 K4_NDC
15 K5_PDC 16 K5_NDC
17 K6_PDC 18 K6_NDC
19 DBRD1_A 20 DBRD1_B
31 PR1H_Z 32 PR1L_Z
33 PR2H_Z 34 PR2L_Z
35 PR3H_Z 36 PR3L_Z
37 PR1H_Y 38 PR1L_Y
39 PR2H_Y 40 PR2L_Y
41 PR3H_Y 42 PR3L_Y
43 PR1H_X 44 PR1L_X
45 PR2H_X 46 PR2L_X
47 PR3H_X 48 PR3L_X

Contact outputs
The contact outputs are polarity sensitive. Wire the

circuit carefully to avoid damaging the relays. There
is no contact or solenoid suppression, user must add
external solenoid suppression to avoid damaging the
Caution relays and their contacts.
A voltage detection circuit is included on TREA that is able to detect a shorted

relay when voltage is present across the open contact set.
SO L_ V
TRIP
Solenoid
S OL_P W R
TREA
Contact
Connection to TREA contact output
E-Stop/TRP Input
• The TRP input is configurable in PPRO / YPRO to either be required or bypass
the signal. When enabled, the TRP input works through a hardware path on
the I/O pack and does not act through the PPRO / YPRO firmware. When
enabled, TRP must be powered for the trip relays to close.
• The ESTOP must be connected to a CLEAN dc source battery or
• There must be a minimum of 18 V dc at the TRP inputs for proper operation. The
• As the TRP is very fast < 5 ms and the output relay contacts are also fast (<
15 ms), best wiring practices should be utilized to avoid disoperation. Use
twisted-pair cable when possible and avoid running with ac wiring.

Operation
The TREA board is designed using three PPRO or YPRO I/O packs mounted directly
on it. This module assembly forms a self-contained emergency trip function.
TREA
Class 1 Div. 2
emergency trip Control module
relay, E-stop,
speed inputs
DC62
DC62
JZ1
P3
Control module
DC62
DC62
JY1
P3
Control module
DC62
DC62
JX1
P3
Note TREA1A, 2A, 3A, and 4A only functions correctly with three I/O packs.
Simplex operation is not possible.

Speed Inputs
When used with three PPRO or YPRO I/O packs mounted directly on the TREA, the
speed inputs provide two options. Each I/O pack can receive a dedicated set of three
speed inputs from their respective TREA terminal points as is done on SPRO. As an
option, jumpers P1 and P2 can be placed on the TREA to take the first three speed inputs
from the X I/O pack and fan them to the Y and Z I/O packs. When this is selected, the
terminal board points for the Y and Z speed inputs become no-connects and should not
be used. As a check, when the PPRO or YPRO is configured for either fanned or direct
speed input, a feedback signal is provided by TREA. If there is a mismatch between
the jumper position and I/O pack configuration, an alarm will be generated.
E-Stop
The TREA includes an E-Stop function. This consists of an optically isolated
input circuit designed for a dc input in the range of 24 V to 125 V nominal. When
energized, the circuit enables coil drive power in the X, Y, and Z relay circuits
through independent hardware paths. The response time of this circuit of less than
five milliseconds plus the response time of the trip relays of less than one millisecond
yields very fast E-Stop response. E-Stop is monitored by PPRO or YPRO firmware,
but the action to remove trip relay coil power is a hardware path in the I/O pack. It
is possible to configure PPRO or YPRO to turn off the E-Stop function.
Voltage Monitors
The trip relays on TREA may be freely located anywhere in a trip string. Because the
trip string circuit is not fixed, there are three general-purpose isolated voltage sensor
inputs on TREA. These can be used to monitor any points in the trip system and
drive the voltage status into the system controller where action can be taken. Typical
use of these inputs may be to sense the power supply voltage for the two trip strings
(PWR) and to sense the solenoid voltage of the device being driven by the relays
(SOL1, SOL2). This set of applications is used in the wording of the board symbol,
but the sensors can be freely applied to best serve the application.
Trip Relays
The trip relays are made using sets of six individual form devices arranged in a voting
set. Because detection of a shorted relay is important to preserve tripping reliability, there
is a sensing circuit applied to each of the sets of relays. When the relays are commanded to
open, and voltage is present across the relays, the circuit will detect if one or more relays
are shorted. This signal goes to the PPRO or YPRO I/O pack to create an alarm. The TREA
sensing circuit uses the relay commands from all three packs to avoid a false indication, in
the event that one I/O pack votes to close the relay while the other two PTUR or YTUR I/O
packs vote to open. The voting arrangement is displayed in the following TREA symbol.
Contacts are polarity-sensitive, external voltage

suppression MUST be used.
Caution

Trip Relays
KX1 KY1
K1_DCP Relay V Monitor JZ1
KY1
KZ1
JX1
KZ1 KX1
JY1
K1_DCN JZ1
KX2 KY2
K2_DCP
Relay V Monitor
KY2
KZ2
Relay Drivers
P28X
KZ2 KX2
JX1
K2_DCN KX1 R
D
SOLn_A R
Trip Voltage KX2
JX1 P28Y D
Monitor JY1
SOLn_B
2 Circuits JZ1 JY1
KY1 R ID
TRP_A D
Estop Monitor JX1
1 Circuit JY1 KY2 R
TRP_B P28Z D
TMR Output JZ1
PWR_A JZ1
Solenoid Power JX1 KZ1 R JY1
JY1 D
Monitor
PWR_B JZ1
1 Circuits
KZ2 R
D
Alternate Sol Input
on WTEA
X Channel Speed
Inputs (3 circuits)
MP PRnH_X
U JX1
Suppression
JX1
PRnL_X JY1
Optional Speed JZ1
Fanning Jumper
P1 Speed Fan ID
Y Channel Speed
Sense
Inputs (3 circuits)
MP PRnH_Y
U JY1
Suppression
JX1
PRnL_Y
Optional Speed
Fanning Jumper
Z Channel Speed P2
Inputs (3 circuits)
MP PRnH_Z
U JZ1
Suppression
PRnL_Z
ID
TREA1A Trip Board
Note The above drawing is simplified with many circuit paths omitted for clarity.

Specifications
Item Specification
Number of inputs 3 x 3 passive (magnetic) speed pickups
1 ESTOP/TRP input
Number of outputs 2 trip contacts
Contact ratings NEMA class F. Minimum operations: 100,000.
IS200TREA1A, 3A Voltage: 28 V dc max
Max. Current 10 A dc 40ºC (104 ºF) maximum
de-rate current linearly to 7 A dc 65ºC (149 ºF) maximum.
Leakage: 2.21 mA max
IS200TREA2A, 4A Voltage: 145 V dc max
Max. Current 3 A dc 40ºC (104 ºF) maximum
de-rate current linearly to 2 A dc 65ºC (149 ºF) maximum
Leakage: 3.31 mA max
Voltage isolation: Optically isolated: 2500 V rms isolation, for one min.
MPU input circuit sensitivity 27 mV pk (detects 2 rpm speed)
Physical
Size 33.0 cm high x 17.8 cm, wide (13 in. x 7 in.)

Diagnostics
• Feedback from the shorted contact detector is checked, if a shorted

relay is detected an alarm will be created.
between intention and actual position, an alarm is created.
xxDIAG_PPRO or xxDIAG_YPRO occurs. The diagnostic signals can be
individually latched and then reset with the RESET_DIA signal if they go healthy.
board type, revision number, and plug location. When the chip is read by PPRO or
YPRO and a mismatch is encountered, a hardware incompatibility fault is created.
Configuration
Jumpers JP1 and JP2 select the fanning of the 3 X section passive speed pickups to
the S and T section PPROs or YPROs. Place the jumper over the pin pairs if you
want to fan the 3 R speed input to the other two TMR sections.

TREG Turbine Emergency Trip
The Gas Turbine Emergency Trip (TREG) terminal board provides power to three
emergency trip solenoids and is controlled by the I/O pack or control board (see table
below). Up to three trip solenoids can be connected between the TREG and TRPG
terminal boards. TREG provides the positive side of the dc power to the solenoids and
TRPG provides the negative side. The I/O pack or control board provides emergency
overspeed protection, emergency stop functions, and controls the 12 relays on TREG, nine
of which form three groups of three to vote inputs controlling the three trip solenoids.
TREG Turbine Emergency Trip Terminal Board

Control System TREG Functionality

Mark VI control IS215VPRO works with the TREG terminal board. Cables with
molded plugs connect TREG to the IS215VPRO module.
Mark VIe control TREG is controlled by the PPRO pack on SPRO or TPRO.
The PPRO I/O packs plug into the D-type connectors on
SPRO or TPRO. Cables with molded plugs connect TREG
to the terminal board.
Mark VIeS control Board revisions TREGS1B and TREGS2B are safety certified.
TREG connects to the SPRO terminal board.
Terminal Board Revisions

In the Mark VIe control system:
• H1B is the primary version for 125 V dc applications. Control power from the
JX1, JY1, and JZ1 connectors are diode combined to create redundant power
on the board for status feedback circuits and powering the economizing relays.
Power separation is maintained for the trip relay circuits.
• H2B is used for 24 V dc applications. All other features are the same as H1B.
In the Mark VI control system:
• H3B is a special version of H1B for use in systems with redundant TREG boards.
Feedback circuit and economizing relay power is provided only by the JX1 connector.
Feedback circuit and economizing relay power is provided only by the JY1 connector.
Feedback circuit and economizing relay power is provided only by the JZ1 connector.
In redundant TREG applications, it is typical to find one H3B and one H4B board
used together. It is important that system repairs be done with the correct board type
to maintain the control power separation designed into these systems.

In the Mark VIeS Safety control system:
• S1B is the primary version for 125 V dc applications. Control power from the
JX1, JY1, and JZ1 connectors are diode combined to create redundant power
on the board for status feedback circuits and powering the economizing relays.
Power separation is maintained for the trip relay circuits.
• S2B is used for 24 V dc applications. All other features are the same as S1B.
Board Mark VI control Mark VIe control Mark VIeS Safety Features
Revision IS215VPRO IS220PPRO control
IS200YPRO
TREGH1A Yes, all versions No No Use TREGH1B as
replacement
TREGH1B Yes, all versions Yes, all versions No 125 V dc applications
TREGH2B Yes, all versions Yes, all versions No 24 V dc applications
TREGH3B Yes, all versions No No Mark VI control only, 125 V dc,
special 28 V power
special 28 V power
special 28 V power
TREGS1B No Yes, all versions Yes, all versions 125 V dc, safety certified
TREGS2B No Yes, all versions Yes, all versions 24 V dc, safety certified

Installation
TREG2B is a 24 V dc version The three trip solenoids, economizing resistors, and the emergency stop are wired directly
of the terminal board. to the first I/O terminal block. Up to seven trip interlocks can be wired to the second
terminal block. The wiring connections are displayed in the following figure:
Power 125V dc To TRPG, 12 wires To TSVO

boards on
SMX systems
Turbine Emergency Trip
J2 J1
Terminal Board TREG JH1
JZ1
x
x 1 SOL 1 or 4
PWR_N1 x 2
4
x 3 RES 1A
RES 1B x
x 5 SOL 2 or 5
PWR_N2 x 6
x 7 RES 2A
RES 2B x 8
10
x 9 SOL 3 or 6
PWR_N3 x
x 11 RES 3A
RES 3B x 12
x 13 E-TRP (H)
E-TRP (H) x 14
x 15
E-TRP (L) x 16 JUMPER
x 17
x 18 I/O
x 19 JY1
x 20 controller
x 21
x 22
x 23
x 24
x
x
x 25
x 26
x 28
x 27
x 29 I/O
PWR_P2 (for probe) x 30 JX1 controller
x 31 PWR_P1 (for probe)
x 32
x 33
x 34
x 35 Contact TRP1 (H)
Contact TRP1 (L) x 36
38
Contact TRP2 (L) x
x
Contact TRP4 (L) 42
x
Contact TRP5 (L) 44
x
I/O
controller
Up to two #12 AWG wires per Terminal blocks can be unplugged
point with 300 volt insulation from terminal board for maintenance
TREG Terminal Board Wiring

Operation
TREG is entirely controlled by the PPRO / YPRO I/O pack or IS215VPRO board.
The connections to the control modules are the J2 power cable and trip solenoids.
In simplex systems, a third cable carries a trip signal from J1 to the TSVO terminal
board, which provides a servo valve clamp function upon turbine trip.
Control of Trip Solenoids
The solenoid circuit has a Both TRPG and TREG control the trip solenoids so that either one can remove
metal oxide varistor (MOV) for power and actuate the hydraulics to close the steam or fuel valves. The nine trip
current suppression and a 10 relay coils on TREG are supplied with 28 V dc from the PPRO / YRPO I/O pack
Ω, 70 W economizing resistor. or IS215VPRO board. The trip solenoids are supplied with 125 V dc through plug
J2, and draw up to 1 A with a 0.1 second L/R time constant.
A separately fused 125 V dc feeder is provided from the turbine control for the solenoids,
which energize in the run mode and de-energize in the trip mode. Diagnostics monitor
each 125 V dc feeder from the power distribution module at its point of entry on the
terminal board to verify the fuse integrity and the cable connection.
Two series contacts from each emergency trip relay (ETR1, 2, 3) are connected to the
positive 125 V dc feeder for each solenoid, and two series contacts from each primary
trip relay (PTR1, 2, 3 in TRPG) are connected to the negative 125 V dc feeder for
each solenoid. An economizing relay (KE1, 2, 3) is supplied for each solenoid with
a normally closed contact in parallel with the current limiting resistor. These relays are
used to reduce the current load after the solenoids are energized. The ETR and KE relay
coils are powered from a 28 V dc source from the I/O controller. Each I/O controller in
each of the R8, S8, and T8 sections supplies an independent 28 V dc source.
The 28 V dc bus is current limited and used for power to an external manual emergency trip
contact, shown as E-Stop. Three master trip relays (K4X, K4Y, K4Z) disconnect the 28 V
dc bus from the ETR, and KE relay coils if a manual emergency trip occurs. Any trip that
originates in either the protection module (such as EOS) or the TREG (such as a manual
trip) will cause each of the three protection module sections to transmit a trip command
over the IONet to the control module, and may be used to identify the source of the trip.
In addition, the K4CL servo clamp relay will energize and send a contact feedback
directly from the TREG terminal board to the TSVO servo terminal board. TSVO
disconnects the servo current source from the terminal block and applies a bias
to drive the control valve closed. This is only used on simplex applications
to protect against the servo amplifier failing high.
Note The primary and emergency overspeed systems can trip the hydraulic trip
solenoids independent of this circuit.

Trip
Terminal Terminal Board TREG 
solenoid JX1
Board TRPG
1 or 4 KE1 KX1 KY1 KX1 RD I/O Pack
02 - + 01 section R8
KX2 J3
KY1 KZ1 RD
J2 J2 ID
Mon KX3 RD
04 KZ1 KX1
Optional
P28X1 Mon
economizing 03
resistor, K4X KX1,2,3
Trip solenoid 28 V dc
100 ohm,
2 or 5 KE2 KX2 KY2 
70W 04 - + 05 JY1
KY1 RD I/O Pack
KY2 KZ2 section S8
J2 J2 J3
Mon
KY2 RD
KZ2 KX2 ID
08 KY3 RD
07
Trip P28Y1 Mon
solenoid K4Y KY1,2,3
28 V dc
3 or 6 KE3 KX3 KY3
06 - + 09
JZ1 
KY3 KZ3 KZ1 RD I/O Pack
J2 J2 section T8
Mon
KZ2 J3
KZ3 KX3 RD
12 ID
11 KZ3 RD
PWR_N1 02
P28Z1 Mon
for test 06
Sol pwr monitor K4Z KZ1,2,3
10 JX1 28 V dc
Mon JY1
J2 J2 JZ1
- N125V
+ P125V KE1,2,3 JX1
P28VV 2 JY1
30 RD
PWR_P1 JX1 3 JZ1
31 PWR_P2 JY1 Mon
for test probe JZ1 KE1,2,3
Three economizing relay circuits
Trip interlock
K4CL JX1 P125X seven circuits
To TSVO P28VV 2 To Exc 35 TRP1H
boards on J1
RD JY1 NS
3 JX1
SMX systems K4CL JZ1 36 TRP1L
K4CL JY1 TRP NS
Servo clamp JZ1
Mon 13
N125X
To relay 14 ETRPH
K25A on J2 P28VV CL
J2 16
TTUR JX1 K4X ETRPL
2 JY1 E-Stop
RD 15
3 JZ1 K4Y JUMPR
JH1 Mon
P125X K4Z 17 JUMPR
JX1
N125X
JY1 18 Second E-STOP
BCOM JZ1 when applicable
TREG Board, Trip Interlocks, and Trip Solenoids

Solenoid Trip Tests
Application software in the controller is used to initiate tests of the trip solenoids.
Online tests allow each of the trip solenoids to be manually tripped one at a time,
either through the PTR relays from the controller, or through the ETR relays from
the protection module. A contact from each solenoid circuit is wired back as a
contact input to give a positive indication that the solenoid has tripped. Primary
and emergency offline overspeed tests are provided too for verification of actual
trips due to software simulated trip overspeed conditions.
Specifications
Item Specification
Number of trip solenoids Three solenoids per TREG (total of six per I/O controller)
Trip solenoid rating H1 / S1- 125 V dc standard with 1 A draw
H2 / S2 - 24 V dc is alternate with 1 A draw
Trip solenoid circuits Circuits rated for NEMA class E creepage and clearance
Circuits can clear a 15 A fuse with all circuits fully loaded
Solenoid inductance Solenoid maximum L/R time constant is 0.1 second
Suppression MOV across the solenoid
Relay outputs Three economizer relay outputs, two second delay to energize
Driver to breaker relay K25A on TTUR
Servo clamp relay on TSVO
Solenoid control relay contacts Contacts are rated to interrupt inductive solenoid loads at 125 V dc, 1 A
Bus voltage can vary from 70 to 145 V dc
Trip inputs Seven trip interlocks to the I/O controller protection module, 125/24 V dc
One emergency stop hard wired trip interlock, 24 V dc
Trip interlock excitation H1 / S2- Nominal 125 V dc, floating, ranging from 100 to 145 V dc
H2 / S2- Nominal 24 V dc, floating, ranging from 18.5 to 32 V dc
Trip interlock current H1 / S1 for 125 V dc applications:
Circuits draw 2.5 mA (50 Ω)
H2 or S2 for 24 V dc applications:
Trip interlock isolation Optical isolation to 1500 V on all inputs
Trip interlock filter Hardware filter, 4 ms
Trip interlock ac voltage rejection 60 V rms 50/60 Hz at 125 V dc excitation
Size 17.8 cm wide x 33.02 cm, high (7.0 in x 13.0 in)

Diagnostics
The I/O controller runs diagnostics on the TREG board and connected devices.
The diagnostics cover the trip relay driver and contact feedbacks, solenoid voltage,
economizer relay driver and contact feedbacks, K25A relay driver and coil, servo
clamp relay driver and contact feedback, and the solenoid voltage source. If any
of these do not agree with the desired value then a fault is created.
TREG connectors JX1, JY1, and JZ1 have their own ID device that is interrogated by I/O
controller. The ID device is a read-only chip coded with the terminal board serial number,
board type, revision number, and the plug location. When the chip is read by the I/O
board and a mismatch is encountered, a hardware incompatibility fault is created.
Configuration
A jumper must be placed across terminals 15 and 17 if the second emergency stop
input is not required. There are no switches on the terminal board.

TREL Turbine Emergency Trip
The Large Steam Turbine Emergency Trip (TREL) terminal board is used for the
emergency overspeed protection for large steam turbines. TREL is controlled by
the PPRO I/O pack or IS215VPRO board in the protection module, and provides
power to three emergency trip solenoids, which can be connected between the TREL
and TRPL terminal boards. TREL provides the positive side of the 125 V dc to the
solenoids and TRPL provides the negative side. I/O controller provides emergency
overspeed protection, emergency stop functions, and controls the nine relays on TREL,
which form three groups of three to vote inputs controlling the three trip solenoids.
The three groups are called ETR (emergency trip) 1, 2, and 3.
• TREL is only available in TMR form.

• TREL has no economizing relay as with TREG.
• TREL has no E-Stop function as with TREG.
A second TREL board may be driven from the protection module.

Installation
The three trip solenoids are wired to the first I/O terminal block. Up to seven trip
interlocks are wired to the second terminal block. The wiring connections are shown
in the following figure. Connector J2 carries three power buses from TRPL, and
JH1 carries the excitation voltage for the seven trip interlocks.
TREL Terminal Board Wiring

Operation
TREL is entirely controlled by the PPRO I/O pack or IS215VPRO board. The only
connections to the turbine control are the J2 power cable and the trip solenoids. In
simplex systems, a third cable carries a trip signal from J1 to the TSVO terminal
board, providing a servo valve clamp function upon turbine trip.
The solenoid circuit has an Both TRPL and TREL control the trip solenoids 1 and 2 so that either one can remove
MOV for current suppression power and actuate the hydraulics to close the steam or fuel valves. ETR3 is set up to
on TRPL. supply power to trip solenoid #3. The nine trip relay coils on TREL are supplied with
28 V dc from I/O controller. The trip solenoids are supplied with 125 V dc (or 24 V
dc) through plug J2, and draw up to 1 A with a 0.1 second L/R time constant.
A separately fused 125 V dc feeder is provided from the PDM to the solenoids.
Diagnostics monitor each 125 V dc feeder from the PDM at its point of entry on the
terminal board to verify the fuse integrity and the cable connection.
Note A normally closed contact from each relay is used to sense the relay status
for diagnostics.
Two series contacts from each of the emergency trip relays (ETR1, 2, 3) are connected
to the positive 125 V dc feeder for each solenoid, and two series contacts from each of
the primary trip relays are connected to the negative 125 V dc feeder for each solenoid.
The ETR relay coils are powered from a 28 V dc source from the I/O controller. Each I/O
controller in each of the R8, S8, and T8 sections supplies an independent 28 V dc source.
The K4CL servo clamp relay will energize and send a contact feedback directly from the
TREL terminal board to the TSVO servo terminal board. TSVO disconnects the servo
current source from the terminal block and applies a bias to drive the control valve closed.
This is only used on simplex applications to protect against the servo amplifier failing high.
Note The primary and emergency overspeed systems will trip the hydraulic trip
solenoids independent of this circuit.
Solenoid Trip Tests


TREL Terminal Board, Trip, Interlocks, and Trip Solenoids

Specifications
Item Specification
Number of trip solenoids Three solenoids per TREL (total of six per I/O controller)
Trip solenoid rating H1 - 125 V dc standard with 1 A draw
H2 - 24 V dc is alternate with 3 A draw
Solenoid inductance Solenoid maximum L/R time constant is 0.1 sec
Suppression MOV on TRPL across the solenoid
Relay Outputs Driver to breaker relay K25A on TTUR.
Solenoid control relay contacts Contacts are rated to interrupt inductive solenoid loads at 125 V dc, 1 A.
Bus voltage can vary from 70 to 145 V dc
Trip inputs Seven trip interlocks to the I/O controller protection module, 125/24 V dc
Trip interlock excitation H1 - Nominal 125 V dc, floating, ranging from 100 to 145 V dc
H2 - Nominal 24 V dc, floating, ranging from 18.5 to 32 V dc
Trip interlock current H1 for 125 V dc applications:
H2 for 24 V dc applications:
Trip interlock ac voltage rejection 60 V rms at 50/60 Hz at 125 V dc excitation
Diagnostics
The protection module runs diagnostics on the TREL board and connected devices. The
diagnostics cover the trip relay driver and contact feedbacks, solenoid voltage, K25A relay
driver and coil, servo clamp relay driver and contact feedback, and the solenoid voltage
source. If any of these do not agree with the desired value, a fault is created.
TREL connectors JX1, JY1, and JZ1 have their own ID device that is interrogated by the
I/O controller. The ID device is a read-only chip coded with the terminal board serial
number, board type, revision number, and the plug location. When the chip is read by the
I/O controller and a mismatch is encountered, a hardware incompatibility fault is created.
Configuration

TRES Turbine Emergency Trip
The Small Steam Turbine Emergency Trip (TRES) terminal board is used for the
emergency overspeed protection for small/medium size steam turbines. TRES is
controlled by the PPRO I/O pack or IS215VPRO board. TRES provides power to
three emergency trip solenoids, which can be connected between the TRES and TRPS
terminal boards. TRES provides the positive side of the 125 V dc to the solenoids
and TRPS provides the negative side. The PPRO I/O pack or IS215VPRO board
provides emergency overspeed protection, emergency stop functions, and controls
the three relays on TRES, which control the three trip solenoids.
• TRES has both simplex and TMR form.

• There are seven dry contact inputs for trip interlocks.
• TRES has no economizing relays.
• There are no emergency stop inputs.
In the TRES, the seven dry contact inputs excitation and signal are monitored
and fanned to the protection module. The board includes the synch check relay
driver, K25A, and associated monitoring, the same as on TREG, and the servo
clamp relay driver, K4CL, and its associated monitoring. A second TRES
board cannot be driven from the protection module.

Installation
The three trip solenoids are wired to the first I/O terminal block. Up to
seven trip interlocks are wired to the second terminal block. The wiring
connections are shown in the following figure.
Connector J2 carries three power buses from TRPS, and JH1 carries the
excitation voltage for the seven trip interlocks.
TRES Terminal Board Wiring

Operation
In simplex systems, a third Both TREL and TRES control the trip solenoids 1 and 2 so that either one can remove
cable carries a trip signal from power and actuate the hydraulics to close the steam or fuel valves. ETR3 is set up to
J1 to the TSVO terminal board, supply power to trip solenoid #3. The nine trip relay coils on TRES are supplied with 28
providing a servo valve clamp V dc from the I/O controller. The trip solenoids are supplied with 125 V dc (or 24 V
function upon turbine trip. dc) through plug J2, and draw up to 1 A with a 0.1 second L/R time constant.
The solenoid circuit has an A separately fused 125 V dc feeder is provided from the PDM for the solenoids.
MOV for current suppression Diagnostics monitor each 125 V dc feeder from the PDM at its point of entry on the
on TREL. terminal board to verify the fuse integrity and the cable connection.
Note A normally closed contact from each relay is used to sense the relay status
for diagnostics
Two series contacts from each of the emergency trip relays (ETR1, 2, 3) are connected
to the positive 125 V dc feeder for each solenoid, and two series contacts from each of
the primary trip relays are connected to the negative 125 V dc feeder for each solenoid.
The ETR relay coils are powered from a 28 V dc source from the I/O controller. Each I/O
controller in each of the R8, S8, and T8 sections supplies an independent 28 V dc source.
The primary and emergency The K4CL servo clamp relay will energize and send a contact feedback directly from the
overspeed systems will trip TRES terminal board to the TSVO servo terminal board. TSVO disconnects the servo
the hydraulic trip solenoids current source from the terminal block and applies a bias to drive the control valve closed.
independent of this circuit. This is only used on simplex applications to protect against the servo amplifier failing high.
Solenoid Trip Tests


J2, power
buses from
TRPS
Terminal Board TRES Terminal
JA1 PwrA_N Board
Simplex P28A PwrB_N PwrC_N
system TRPS
uses JA1 P28X
PwrA_P PwrB_P
PwrC_P
P28Y
P28
P28Z Sol.
ID To JX1, Power
JX1 JY1,JZ1, Monitor
JA1 J2
J2
I/O
2 RD ETR1
Controller
3 SUS1A 01
PwrA_P SUS1B Trip
02
To X,Y,Z, A
Mon solenoid
ETR1
ETR1 SOL1A 03 - +
ID ETR1 SOL1B 04
PwrA_P 08
Several terminals
P28 PwrA_N positions for
JY1 PwrA_N 09 different
I/O applications
Controller 2 RD ETR2
3 J2
J2
To X,Y,Z, A
Mon
SUS2A 11
ETR2
PwrB_P SUS2B 12 Trip
ID
solenoid
ETR2 SOL2A 13
- +
P28 ETR2 SOL2B 14
JZ1 PwrB_P
18
PwrB_N
I/O PwrB_N
2 RD 19
Controller ETR3
J2
3 J2
To X,Y,Z,A SUS3A 21
Mon
ETR3 PwrC_P SUS3B 22 Trip
ID solenoid
ETR3 SOL3A 23 - +
P28VV
To TSVO ETR3 SOL3B 24
boards on J1 K4CL JX1
2 JY1 PwrC_P
SMX systems RD 3 28
JZ1 PwrC_N
PwrC_N
K4CL JA1 29
Servo Clamp To JX1, JY1,
K4CL Mon JZ1, JA1
To TTURH1B J25 Exc_P
Excitation
To relay K25A JX1 volts 35 TRP1A
J2 2 NS
on TTUR JY1
RD 3
JZ1 7 36 TRP1B
JA1 NS
JH1 Mon
Excit_P . Trip interlock
From .
Excitation_N .
PDM
BCOM 7 circuits as above
TRES Terminal Board, Trip Interlocks, and Trip Solenoids

Specifications
Item Specification
Number of trip solenoids Three solenoids per TRES
Trip solenoid rating 125 V dc standard with 1 A draw
24 V dc is alternate with 3 A draw
Solenoid inductance Solenoid maximum L/R time constant is 0.1 sec
Suppression MOV on TRPS across the solenoid
Relay Outputs Driver to breaker relay K25A on TTUR
Solenoid control relay contacts Contacts are rated to interrupt inductive solenoid loads at 125 V dc, 1 A.
Bus voltage can vary from 70 to 145 V dc.
Trip inputs Seven trip interlocks to the PPRO I/O pack or IS215VPRO board
Trip interlock excitation H1 - Nominal 125 V dc, floating, ranging from 100 to 145 V dc
H2 - Nominal 24 V dc, floating, ranging from 18.5 to 32 V dc
Trip interlock current H1 for 125 V dc applications:
H2 for 24 V dc applications:
Trip interlock ac voltage rejection 60 V rms at 50/60 Hz at 125 V dc excitation
Diagnostics
The I/O controller runs diagnostics on the TRES board and connected devices. The
diagnostics cover the trip relay driver and contact feedbacks, solenoid voltage, K25A relay
driver and coil, servo clamp relay driver and contact feedback, and the solenoid voltage
source. If any of these do not agree with the desired value, a fault is created.
TRES connectors JA1, JX1, JY1, and JZ1 have their own ID device that is interrogated by
the I/O controller. The ID device is a read-only chip coded with the terminal board serial
number, board type, revision number, and the plug location. When the chip is read by the
I/O controller and a mismatch is encountered, a hardware incompatibility fault is created.
Configuration

SPRO Emergency Protection
The Emergency Protection (SPRO) terminal board hosts a PPRO or YPRO I/O
pack. It conditions speed signal inputs for the I/O pack and contains a pair of
potential transformers (PTs) for bus and generator voltage input. It has a DC-37
pin connector adjacent to the PPRO or YPRO I/O pack connector that accepts
a cable leading to a backup trip relay terminal board.
The following figure displays how the SPRO and PPRO / YPRO with cabling
into a trip relay board form the backup protection in a Mark VIe or Mark
VIeS control system. Primary protection is provided by PTUR or YTUR,
TTUR, and a primary trip relay terminal board.

Turbine Control and Protection Boards

Compatibility
BoardRevision Mark VI control Mark VIe control Mark VIeS Safety Features
IS200VPRO IS220PPRO control IS220YPRO
SPROH1A No Yes, all versions No 24 Barrier terminals in a pluggable
block
SPROH2A No Yes, all versions No 24 pluggable Euro-style box
terminals
SPROS1A No Yes, all versions Yes, all versions Barrier terminals, safety certified
The SPRO accepts direct mounting of one PPROH1A or YPROS1A and provides
DC-37 connector for a cable to the selected backup trip relay terminal board. SPRO
is cable-compatible with the trip boards listed in the following table.

Contacts Contacts Contacts Contacts Resistor
125 V dc 24 V dc 125 V dc 24 V dc
TRESH1A Yes Yes Yes Yes No Yes No No
TRESH2A Yes Yes Yes Yes No No Yes No
* TREGS1B Yes No Yes Yes Yes Yes No Yes
* TREGS2B Yes No Yes Yes Yes No Yes Yes
* Mark VIeS Safety control compatible version
Installation
The SPRO and a plastic insulator mount on a sheet metal carrier, which mounts on
a DIN-rail. Optionally, the SPRO and insulator mount on a sheet metal assembly,
which bolts directly in a panel. Speed signals and PT inputs are wired directly to
the terminal block using typical #18 AWG wires. The SPRO1A barrier terminal
block is removable for board replacement. The SPRO2A Euro-block type terminal
block has terminals that can be removed for board replacement.
The I/O pack mounts directly on connector JA1 of the SPRO. A DC-37
pin conductor cable plugs into connector JA3 of SPRO with the other end
attached to the selected backup trip terminal board.

Operation
In the following drawing, the PT inputs to SPRO are displayed on terminals 1-4.
Three speed inputs are displayed on terminals 19-24. Terminals 7-15 are reserved
for future control feature expansion and are routed to the JA1 I/O pack connector.
Terminals 5-6 and 16-18 have no board connection. The JA1 and JA3 connectors
provide locations for the I/O pack and the trip terminal board cables.
Generator PT
NS
GENH 1
NS
GENL 2
P T In p uts
BUSH 3 NS
ID
BUSL 4 NS Chip
5
KPRO1 7
KPRO2 8 Bus PT
KPRO3 9
KPRO4 10
DC-62
KPRO5 11
KPRO6 12 DC-37
KPRO7 13
KPRO8 14
JA3
KPRO9 15
16 JA1
Expansion I/O
17
18
Speed Inputs
MAG1H 19 NS Filter
Clamp
MAG1L 20 NS Ac Coupled
NS Filter
MAG2H 21
Clamp
MAG3H 23 NS Filter
Clamp
SPROH1A or SPROS1A
SPRO Signal Inputs

SPRO Inputs
Terminal Signal Name Variable Name Description

1 GENH GenPT_KVolts Generator PT input high.
2 GENL Generator PT input low
3 BUSH BusPT_KVolts Bus PT input high
4 BUSL Bus PT input low
5 Not connected
6 Not connected
7 KPRO1 Unused, left for future control feature expansion.
16 Not connected
17 Not connected
18 Not connected
19 MAG1H PulseRate1 Magnetic pickup-1 high input
20 MAG1L Magnetic pickup-1 low input

Specifications
Item Specification
Generator and bus voltage sensors Two single-phase potential transformers, with secondary output supplying a
nominal 115 V rms
Allowable voltage range for synch is 75 to 130 V rms
Magnetic speed pickup pulse rate range 2 Hz to 20,000 Hz
Magnetic speed pickup pulse rate 0.05% of reading
accuracy
Physical
Diagnostics
The SPRO board and backup trip relay terminal board contain electronic ID parts that
are read during power initialization. This information is used by PPRO or YPRO to
confirm a valid hardware arrangement prior to starting normal operation.
Configuration

PRTD Input Module
RTD Input (PRTD)

RTD The Resistance Temperature Device (RTD) Input (PRTD) pack provides the
PWR electrical interface between one or two I/O Ethernet networks and a RTD input
ATTN
terminal board. The pack contains a processor board common to all Mark* VIe
distributed I/O packs and an acquisition board specific to the thermocouple input
function. The I/O pack is capable of handling up to eight RTD inputs and can handle
LINK
ENET1 16 RTD inputs on the TRTD terminal boards.
TxRx
Note The PRTD pack supports only simplex operation.
LINK
ENET2 Input to the pack is through a DC-37 pin connector that connects directly with the
TxRx associated terminal board connector, and a three-pin power input. Output is through
dual RJ45 Ethernet connectors. Visual diagnostics are provided through indicator
IR PORT LEDs.
IS220PRTDH1A
GEH-6721L PRTD Input Module System Guide 19-1

PRTDH1A
RTD Input
Module
BRTDH1A BPPB
output board processor board
TRTDH1D
RTD Input
One PRTD module for Terminal Board
Simplex control (use the
A connector for first eight
RTD inputs) Single or dual
Ethernet cables
ENET1
16 RTD Inputs
JA1 ENET2
External 28 V dc
power supply
ENET1
Two PRTD modules for
Simplex control of 16 RTDs JB1 ENET2
(one module on A connector for
first eight RTDs, one on B 28 V dc
connector for second eight RTDs)
PRTD Block Diagram
Compatibility
PRTDH1A is compatible with the RTD input terminal boards TRTDH1D,
H2D, and the SRTD board, but not the DIN-rail mounted DRTD board. The
following table gives details of the compatibility.
Terminal Board TRTD SRTD

Version and Inputs TRTDH1D, H2D 8 RTD
Control mode Simplex - Yes Dual - No TMR - No Simplex - Yes
The PRTD provides galvanic isolation of the TRD input circuit. This requires
changes in the terminal board transient protection, provided on the TRTDH1D and
TRTDH2D boards. The H1D version of the board provides filtering compatible with
the standard scan rate of PRTD. The H2D version of the terminal board provides less
filtering to allow proper performance when the fast scan rate of PRTD is selected.
If PRTD is mounted on an earlier revision of the TRTD board, an incompatibility
will be reported, although no physical damage will occur.

Installation
¾ To install the PRTD pack
2. Directly plug one or two PRTD (for simplex control of eight or 16
RTDs) into the terminal board connectors.
ports. The inserts connect with a mounting bracket specific to the terminal board
type. The bracket location should be adjusted such that there is no right angle force
Note The PRTD mounts directly to a Mark VIe terminal board. Simplex terminal
boards (TRTDH1D) have two DC-37 pin connectors that receive the PRTDs, one for
each set of 8 RTD inputs.
4. Plug in one or two cables (depending on system configuration) to negotiate proper

operation over either port. If dual connections are used the standard practice is
to hook ENET1 to the network associated with the R controller.

Wizard again.

Operation
Processor




Status LEDs
Processor LEDs

present
LED Status

ATTN
or module.
ATTN
every 4 sec

The PRTD input board accepts eight three-wire RTD inputs from the RTD terminal board.
The pack supplies a 10 mA dc multiplexed (not continuous) excitation current to each RTD,
which can be grounded or ungrounded. The eight RTDs can be located up to 300 meters
(984 feet) from the turbine I/O cabinet with a maximum two-way cable resistance of 15 Ω.
The A/D converter in the pack samples each signal and the excitation current four
times per second for normal mode scanning, and 25 times per second for fast mode
scanning, using a time sample interval related to the power system frequency.
Linearization for the selection of RTD types is performed in software by the processor.
RTD open and short circuits are detected by out of range values. An RTD, which
is determined to be out of hardware limits, is removed from the scanned inputs
in order to prevent adverse affects on other input channels. Repaired channels are
reinstated automatically in 20 seconds, or can be manually reinstated.
Calibration
RTD inputs are automatically calibrated using the filtered calibration
source and null voltages.
ID Line
Power Management

Connectors
The following table provides information specific to the PRTD pack.
Item PRTD Specification

Number of channels 8 channels per pack (16 channels per terminal board)
RTD types 10, 100, and 200 Ω platinum
10 Ω copper
120 Ω nickel
Span 0.3532 to 4.054 V
A/D converter resolution 14-bit resolution
Scan time Normal scan 250 ms (4 Hz)
Fast scan 40 ms (25 Hz)
Measurement accuracy RTD Type Group Gain Accuracy at 400 °F
120 Ω Nickel Normal_ 1.0 1.1°C (2 °F)
200 Ω Platinum Normal_1.0 1.1°C (2 °F)
100 Ω Platinum Normal_ 1.0 2.22°C (4 °F)
100 Ω Platinum -51 to +204ºC Gain_ 2.0 1.11°C (2 °F)
(-60 to 400 °F)
10 Ω Copper 10 Ω Cu_10 5.55°C (10 °F)
Common mode rejection Ac common mode rejection 60 dB at 50/60 Hz,
Dc common mode rejection 80 dB
Common mode voltage range ±5 Volts
Normal mode rejection Rejection of up to 250 mV rms is 60 dB at 50/60 Hz system frequency for normal scan

RTD Types and Ranges
The units (°C or °F) are based RTD inputs are supported over a full-scale input range of 0.3532 to 4.054 V. The
on the ThermCplUnit settings. following table shows the types of RTD used and the temperature ranges.
See section ThermCplUnit
Parameter.
RTD Type Name/Standard Range °C Range °F

10 Ω copper MINCO_CA GE 10 Ω Copper -51 to +260 -60 to +500
100 Ω platinum SAMA 100 -51 to +593 -60 to +1100
100 Ω platinum DIN 43760 -51 to +700 -60 to +1292
IEC-751
MINCO_PD
MINCO_PE
PT100_DIN
100 Ω platinum MINCO_PA -51 to +700 -60 to +1292
IPTS-68
PT100_PURE
100 Ω platinum MINCO_PB -51 to +700 -60 to +1292
Rosemount 104
PT100_USIND
120 Ω nickel MINCO_NA -51 to +249 -60 to +480
N 120
200 Ω platinum PT 200 -51 to +204 -60 to +400
Diagnostics
The pack performs the following self-diagnostic tests
• A power-up self-test that includes checks of RAM, Flash memory, Ethernet

• Each RTD type has hardware limit checking based on preset (non-configurable)
exceeded, a logic signal is set, and the input is no longer scanned. If any
one of the 8 input’s hardware limits is set it creates a composite diagnostic
alarm, L3DIAG_PRTD, referring to the entire board. Details of the individual
diagnostics are available from the toolbox. The diagnostic signals can be
individually latched, and then reset with the RESET_DIA signal
• Each RTD input has system limit checking based on configurable high and low levels.
These limits can be used to generate alarms, and can be configured for enable/disable,
and as latching/non-latching. RESET_SYS resets the out of limit signals
• Details of the individual diagnostics are available from the toolbox. The
diagnostic signals can be individually latched, and then reset with the
RESET_DIA signal if they go healthy

Configuration

PRTD_Mod_Config
System Limits Enable or disable all system limit checking Enable (default), disable
Auto Reset Automatic restoring of RTDs removed from scan Enable (default), disable
GroupRate RTD’s 1-8 sample rate and n+ system frequency filter if 4 Hz 4 Hz, 50 Hz filter
sampling 4 Hz, 60 Hz filter (default)
25 Hz
SwConfigDefs
RTD Type Select RTD type or ohms input Unused (default)
RTDs linearizations supported by RTD, (unused inputs are CU10 MINCO_CA
removed from scanning) PT100_DIN MINCO_PD
PT100_PURE MINCO_PA
PT100_USIND MINCO_PB
N120 MINCO_NA
MINCO_PIA PT100_SAMA
PT200 MINCO_PK Ohms
SysLim1 Enabl Enable system limit 1 fault check Enable, disable (default)
Enables or disables a temperature limit for each RTD,
can be used to create an alarm
SysLim1 Latch Latch system limit 1 fault Latch (default), unlatch
Determines whether the limit condition will latch or
unlatch for each RTD; reset used to unlatch.
SysLim1 Type System limit 1 check type ( >= or <= ) Greater than or equal (default),
Limit occurs when the temperature is greater than or equal (>=), Less than or equal
or less than or equal to a preset value.
System Limit 1 System limit 1 - Deg °F or Deg °C. -60 to 1,300 (default)
Enter the desired value of the limit temperature
SysLim2 Enabl Enable system limit 2 fault check Enable, disable (default)
Enables or disables a temperature limit used to create an alarm
SysLim2 Latch Latch system limit 2 fault Latch (default), unlatch
Determines whether the limit condition will latch or unlatch; reset
used to unlatch.
SysLim2 Type System limit 2 check type (>= or <= ). Greater than or equal,
Limit occurs when the temperature is greater than or equal (>=), Less than or equal (default)
or less than or equal to a preset value.
System Limit 2 System limit 2 - Deg °F or ohms. -60 to 1,300 (default)
Enter the desired value of the limit temperature, Deg °F or ohms
RTDGain Select RTD sensor gain. Normal_1_0 (default)
Gain 2.0 is for higher accuracy if ohms<190. Gain_2_0
10 Ω Cu_10_0
RTDUnit Temperature units in degree Celsius or degree Fahrenheit for any deg_F
selected Rtd Type except Ohms and Unused. If RtdType is Ohms, deg_C
this parameter does not apply.

Point Signal Description-Point Edit (Enter Signal Connection) Direction Type
L3DIAG_PRTD_R I/O diagnostic indication Input BIT
LINK_OK_PRTD_R I/O link okay indication Input BIT
ATTN_PRTD_R I/O attention indication Input BIT
IOPackTmpr_R I/O pack temperature Input FLOAT
SysLim1RTD1_R System limit 1 Input BIT
: : Input BIT
: : Input BIT
PS18V_PRTD_R I/O 18V Power Supply Indication Input Bool
PS28V_PRTD_R I/O 28V Power Supply Indication Input Bool
RtdUnit Parameter
The RtdUnit parameter affects the native units of the controller application variable. It
is only indirectly related to the tray icon and associated unit switching capability of the
Note RtdUnits do not apply if RtdType selected is of Ohms type.
Do not change the RtdUnit parameter in the ToolboxST

application because these changes will require
to this parameter.

TRTD RTD Input
The RTD Input (TRTD) terminal board accepts 16, three-wire RTD inputs. These
inputs are wired to two barrier type terminal blocks. The inputs have noise
suppression circuitry to protect against surge and high frequency noise. TRTD
communicates with one or more I/O processors, which convert the inputs to digital
temperature values and transfer them to the controller.
There are four versions of TRTD as follows:
• TRTDH1B is a TMR version that fans out the signals to three VRTD
boards using six DC-type connectors.
• TRTDH1C is a simplex board with two DC-type connectors for VRTD.
• TRTDH1D is a simplex board with two DC-type connectors for PRTD, normal scan.
• TRTDH2D is a simplex board with two DC-type connectors for PRTD, fast scan.
Mark VI Control Systems

In the Mark VI control system, TRTDH1B and TRTDH1C works with the
VRTD processor and supports simplex and TMR applications. One TRTDH1C
connects to the VRTD with two cables. In TMR systems, TRTDH1B connects
to three VRTD processors with six cables.
Mark VIe Control Systems

In the Mark VIe control system, TRTDH1D and TRTDH2D works with the
PRTD I/O pack and support simplex applications only. Two PRTD packs
plug into the TRTD for a total of 16 inputs.

TRTDH1C, H1D, H2D Terminal Board TRTDH 1B Terminal Board
TRTD capacity for
+ 16 RTD inputs +
2 1 1
3 2
4 4 3
Eight RTD 6 5 DC-37 pin 5 JTA JTB
7 Connectors Eight RTD 6
Inputs 8 8 7
10 9 With latching Inputs 9
11 10
12 fasteners 12 11
14 13 13
15 14
16 16 15
18 17 17
19 18
20 JA1 20 19
22 21 21
23 22 JSA JSB
24 24 23
J Ports:
26 25 Plug in PRTD I /O Pack(s) 25

27 26
28 for Mark VIe 28 27
Eight RTD 30 29 29
31 or Eight RTD 30
Inputs 32 JB1 Cable(s) to VRTD 32 31
33 Inputs 33
34 35 34 JRA JRB
36 board(s) for Mark VI ; 35
37 36 37
38 39 38
40 the number and location 40 39
42 41 41
43 depends on the level of 42
44 44 43
46 45 redundancy required . 45
47 46 47
48 48
+ +
Shield Barrier Type terminal

Bar Blocks can be unplugged
from board formaintenance
RTD Input Terminal Boards
Installation
Connect the wires for the 16 RTDs directly to the two terminal blocks on the
terminal board. Each block is held down with two screws and has 24 terminals
Double-shielded wire must be used. All shields must

be terminated at the shield terminal strip. Do not end
shields located at the end device.
Caution
In a TMR Mark VI control system, TRTDH1B provides redundant RTD inputs by

fanning the inputs to three VRTD boards in the R, S, and T racks. The inputs meet
the same environmental, resolution, suppression, and function requirements and codes
as the TRTDH1C terminal board; however, the fast scan is not available.

RTD Terminal Board TRTDH1C
Screw Connections Screw Connections

x
x 1 Input 1 (Exc)
Input 1 (Sig) x 2
x 3 Input 1 (Ret)
Input 2 (Exc) x 4
Input 2 (Ret)
x 5 Input 2 (Sig)
x 6
x 7 Input 3 (Exc)
Input 3 (Sig) x 8
x 9 Input 3 (Ret)
Input 4 (Exc) x 10
x 11 Input 4 (Sig)
Input 4 (Ret) x 12
Input 5 (Sig)
x 13 Input 5 (Exc)
x 14
Input 6 (Exc) x 15 Input 5 (Ret) JA1
x 16
x 17 Input 6 (Sig)
Input 6 (Ret) x 18
x 19 Input 7 (Exc)
Input 7 (Sig) x 20
x 21 Input 7 (Ret) First 8 RTDs
Input 8 (Exc) x 22 J-Port Connections:
x 23 Input 8 (Sig) to JA1
Input 8 (Ret) x 24
x Plug in PRTD I/O Pack(s) for
Mark VIe
x
or
x 25 Input 9 (Exc)
Input 9 (Sig) x 26
x 27 Input 9 (Ret)
Input 10 (Exc) x 28 Cable to VRTD I/O board(s) for
x 29 Input 10 (Sig)
Input 10 (Ret) x 30 Mark VI;
x 31 Input 11 (Exc)
Input 11 (Sig) x 32 JB1
x 33 Input 11 (Ret) The number and location
Input 12 (Exc) x 34
x 35 Input 12 (Sig) depends on the number of
Input 12 (Ret) x 36
Input 13 (Sig)
x 37 Input 13 (Exc) inputs required.
x 38 Second 8
x 39 Input 13 (Ret)
Input 14 (Exc) x 40 RTDs to JB1
x 41 Input 14 (Sig)
Input 14 (Ret) x 42
Input 15 (Sig)
x 43 Input 15 (Exc)
x 44
Input 16 (Exc)
x 45 Input 15 (Ret)
x 46
x 47 Input 16 (Sig)
Input 16 (Ret) x 48
x
A Excxx
Application Note:
- Optional Ground: connnect the B wire to ground;
RTD
- RTD Group wiring, that is sharing the B wire;
B Sigxx
tie the B wires together at the RTDs,
C
Retxx tie the Sigxx signals together at the TRTD terminal
b board, and interconnect with one wire.
TRTDH1C RTD Terminal Board Wiring

Operation
TRTD supplies a 10 mA dc multiplexed (not continuous) excitation current to each RTD,
which can be grounded or ungrounded. The 16 RTDs can be located up to 300 m (984 ft)
from the turbine control cabinet with a maximum two-way cable resistance of 15 Ω.
The A/D converter in the I/O processor samples each signal and the excitation current
four times per second for normal mode scanning and 25 times per second for fast
mode scanning, using a time sample interval related to the power system frequency.
Software performs the linearization for the selection of 15 RTD types.
RTD open and short circuits are detected by out-of-range values. An RTD that is
determined to be outside the hardware limits is removed from the scanned inputs to
prevent adverse effects on other input channels. Repaired channels are reinstated
automatically in 20 seconds or can be manually reinstated.
All RTD signals have high-frequency decoupling to ground at signal entry.

RTD multiplexing in the I/O processor is coordinated by redundant pacemakers
so that the loss of a single cable or I/O processor does not cause the loss
of any RTD signals in the control database.
TRTDH1C RTD I/O Processor Board

Terminal Board
I/O Processor is either
remote (Mark VI) or
Noise Excitation
suppression JA1 local (Mark VIe)
Excitation
RTD To
Signal NS controller
Return A/D
Processor VMEbus
Conv
Grounded or
ungrounded ID
(8) RTDs
Noise
Suppression JB1
Excitation
RTD
Signal NS JB1 cables to I/O processor
VRTD for Mark VI systems
Return or
Grounded or connects to PRTD I/O pack
ungrounded for Mark VIe systems
(8) RTDs ID
TRTD (Simplex) Inputs and Signal Processing

Signals
TerminalBoard TRTDH1B PM= Pacemaker
Tx = VRTD transmit
Rx = VRTD receive
Noise
JRA
suppression ID
Excitation
RTD PM, Tx
Signal NS PM, Rx, S
Return JSA
ID
Grounded or
ungrounded PM, Tx
(8) RTDs to JRA, JSA, JTA
PM, Rx, R
JTA
ID
PM, Tx
PM, Rx, R
Noise JRB
suppression ID
Excitation
RTD PM, Tx
Signal NS PM, Rx, T
Return JSB
ID
Grounded or
ungrounded (8) RTDs to JRB, JSB, JTB PM, Tx
PM, Rx, T
JTB
ID
PM, Tx
PM, Rx, S
TRTDH1 TMR-Capable RTD Terminal Board
Calibration

Specifications
Item Specification
Number of channels Eight channels per terminal board
10 Ω copper
120 Ω nickel
Span 0.3532 to 4.054 V
High/low (software) system limit check
Failed ID chip
RTD Accuracy
RTD Type Group Gain Accuracy at 400 ºF

120 Ω nickel 120 Ω nickel 2 ºF
200 Ω platinum Normal_ 1.0 2 ºF

100 Ω platinum -51 to 240ºC (- 60 to 400 ºF) Gain_ 2.0 2 ºF
10 Ω copper 10 Ω Cu_10 10 ºF

RTD inputs are supported over a full-scale input range of 0.3532 to 4.054 V. The
following table shows the types of RTD used and the temperature ranges.

10 Ω copper MINCO_CA GE 10 Ω Copper -51 to +260 -60 to +500
100 Ω platinum SAMA 100 -51 to +593 -60 to +1100
100 Ω platinum DIN 43760 -51 to +700 -60 to +1292
IEC-751
MINCO_PD
MINCO_PE
PT100_DIN
100 Ω platinum MINCO_PA -51 to +700 -60 to +1292
IPTS-68
PT100_PURE
100 Ω platinum MINCO_PB -51 to +700 -60 to +1292
Rosemount 104
PT100_USIND
120 Ω nickel MINCO_NA -51 to +249 -60 to +480
N 120
200 Ω platinum PT 200 -51 to +204 -60 to +400
Diagnostics
Diagnostic checks include the following:
exceeded, a logic signal is set and the input is no longer scanned. If any one
of the input’s hardware limits is set, it creates a composite diagnostic alarm,
L3DIAG_xxxx, referring to the entire board. Details of the individual diagnostics
are available from the toolbox. The diagnostic signals can be individually
latched, and then reset with the RESET_DIA signal.
• Each RTD input has system limit checking based on configurable high and low
levels. These limits can be used to generate alarms, and can be configured
for enable/disable, and as latching/non-latching. RESET_SYS resets the
out of limit signals. In TMR systems, limit logic signals are voted and the
resulting composite diagnostic is present in each controller.
• The resistance of each RTD is checked and compared with the correct
value, and if high or low, a fault is created.
• Each connector has its own ID device, which is interrogated by the I/O processor
board. The terminal board ID is coded into a read-only chip containing the terminal
board serial number, board type, revision number, and the connector location. If
a mismatch is encountered, a hardware incompatibility fault is created.

Configuration
SRTD Simplex RTD Input

The Simplex Resistance Temperature Device (RTD) Input (SRTD) terminal board
is a compact RTD terminal board, designed for DIN-rail or flat mounting. The
board has eight RTD inputs and connects to the PRTD I/O processor. High-density
Euro-block type terminal blocks are mounted to the board. An on-board ID chip
identifies the board to the I/O processor for system diagnostic purposes.
Mark VIe Systems

In the Mark* VIe systems, the PRTD I/O pack works with the SRTD. The I/O
pack plugs into the DC-37 pin connector and communicates with the controller
Installation
The SRTD and a plastic insulator mount on a sheet metal carrier which mounts on a
DIN rail. Optionally the SRTD and insulator mount on a sheet metal assembly that bolts
directly to a cabinet. The eight RTDs are wired directly to the Euro-style box type terminal
block, which has 36 terminals and is available in two types. Typically #18 AWG wires
(shielded twisted triplet) are used. I/O cable shield terminal uses an external mounting
bracket supplied by GE or the customer. Terminals 25 through 34 are not connected. E1
and E2 are mounting holes for the chassis ground screw connection (SCOM).

Euro Block type SRTD Terminal Board
terminal block
DC-37 pin shell

E1 Screw Connections connector with
latching fasteners
2 1 Input 1 (Excitation)
Input 1 (Signal)
3 Input 1 (Return)
Input 2 (Excitat) 4
5 Input 2 (Signal) JA1
Input 2 (Return) 6
7 Input 3 (Excitation)
Input 3 (Signal) 8
9 Input 3 (Return)
Input 4 (Excitat) 10
11 Input 4 (Signal) JA1
Input 4 (Return) 12
Input 5 (Signal) 14
15 Input 5 (Return) Plug in PRTD Pack
17 Input 6 (Signal)
Input 6 (Return) 18
Input 7 (Signal) 20
21 Input 7 (Return
23 Input 8 (Signal)
Input 8 (Return) 24
NC 26
25 NC
27 NC
NC 28
29 NC
NC 30 NC
31
NC 32
33 NC
NC 34
35 SCOM
SCOM 36
E2 SCOM - Chassis ground
Plastic insulator
and metal carrier
DIN-rail mounting option
Application Notes: Excxx

A
- Optional Ground: connnect the B wire to ground;
- RTD Group wiring, that is sharing the B wire; RTD
tie the B wires together at the RTDs,
Sigxx B
tie the Sigxx signals together at the RTD terminal
C
board, and interconnect with one wire. b Retxx
SRTD Terminal Board Wiring and Cabling
Two types of Euro-style box type terminal blocks are available:
• Terminal board SRTDH1 has a permanently mounted terminal block with 36 terminals.
• Terminal board SRTDH2 has a right-angle header accepting a range of commercially
available pluggable terminal blocks, with a total of 36 terminals.

Operation
The terminal board supplies a 10 mA dc multiplexed (not continuous) excitation current
to each RTD, which can be grounded or ungrounded. The eight RTDs can be located
up to 300 m (984 ft) from the turbine control cabinet with a maximum two-way cable
resistance of 15 Ω. The on-board noise suppression is similar to that on the TRTD.
The RTD inputs and signal processing are illustrated in the figure.
The A/D converter in the PRTD pack samples each signal and the excitation current
four times per second for normal mode scanning, and 25 times per second for fast
mode scanning, using a time sample interval related to the power system frequency.
Linearization for the selection of 15 RTD types is performed by the processor.
PRTD I/O Pack

SRTD Terminal
Board
Excitation
8 RTD inputs
Noise JA1
1 suppression
Excitation
A
RTD
B Signal 2 NS A/D Processor
C
Return 3
Grounded or SCOM
ungrounded
A/D converter
(8) RTDs
ID
Plug in PRTD I/O pack

SRTD Board and Input Processor Board
RTD open and short circuits are detected by out-of-range values. An RTD that is
determined to be out of hardware limits is removed from the scanned inputs to
prevent adverse affects on other input channels. Repaired channels are reinstated
automatically in 20 seconds, or can be manually reinstated.
Calibration

Specifications
Item Specification
Number of channels Eight channels per terminal board
10 Ω copper
120 Ω nickel
Span 0.3532 to 4.054 V
High/low (software) system limit check
Incorrect ID chip
RTD Accuracy
RTD Type Group Gain Accuracy at 400 ºF

120 Ω nickel 120 Ω nickel 2 ºF
100 Ω platinum -51 to 240ºC (- 60 to 400 ºF) Gain_ 2.0 2 ºF
10 Ω copper 10 Ω Cu_10 10 ºF

RTD inputs are supported over a full-scale input range of 0.3532 to 4.054 V. The
following table shows the types of RTD used and the temperature ranges.

10 Ω copper MINCO_CA GE 10 Ω Copper -51 to 260 -60 to 500
100 Ω platinum SAMA 100 -51 to 593 -60 to 1100
100 Ω platinum DIN 43760 -51 to 700 -60 to 1292
IEC-751
MINCO_PD
MINCO_PE
PT100_DIN
100 Ω platinum MINCO_PA -51 to 700 -60 to 1292
IPTS-68
PT100_PURE
100 Ω platinum MINCO_PB -51 to 700 -60 to 1292

Rosemount 104
PT100_USIND
120 Ω nickel MINCO_NA -51 to 249 -60 to 480
N 120
200 Ω platinum PT 200 -51 to 204 -60 to 400

Diagnostics
Diagnostic checks include the following:
exceeded, a logic signal is set and the input is no longer scanned. If any one
of the input’s hardware limits is set, it creates a composite diagnostic alarm,
L3DIAG_xxxx, referring to the entire board. Details of the individual diagnostics
are available from the toolbox. The diagnostic signals can be individually
latched, and then reset with the RESET_DIA signal.
• Each RTD input has system limit checking based on configurable high and low
levels. These limits can be used to generate alarms, and can be configured
for enable/disable, and as latching/non-latching. RESET_SYS resets the
out of limit signals. In TMR systems, limit logic signals are voted and the
resulting composite diagnostic is present in each controller.
• The resistance of each RTD is checked and compared with the correct
value, and if high or low, a fault is created.
• Each connector has its own ID device, which is interrogated by the I/O processor
board. The terminal board ID is coded into a read-only chip containing the terminal
board serial number, board type, revision number, and the connector location. If
Configuration

PSCA Serial Communication I/O Module
Serial Communication Input/Output (PSCA)

The Serial Communication Input/Output (PSCA) pack provides the electrical
SERIAL COMM
PWR
interface between one or two I/O Ethernet networks and a serial communications
TX1 terminal board. The pack contains a processor board common to all Mark* VIe
RX1 ATTN
TX2 distributed I/O packs and a serial communications board. The communications
board contains six serial transceiver channels, each of which can be individually
LINK configured to comply with RS-232, RS-422, or RS-485 half duplex standards. Input
RX2 ENET1
TX3 TxRx to the pack is through dual RJ45 Ethernet connectors and a three-pin power input.
RX3 Output is through a DC-62 pin connector that connects directly with the associated
terminal board connector. One of the Ethernet ports can be used to support Ethernet
LINK
TX4 ENET2 Modbus communication on Simplex Networks. Visual diagnostics are provided
RX4 TxRx
through indicator LEDs.
TX5
IR PORT
RX5
TX6
RX6
IS220PSCAH1A
PSCAH1A
Communications
BSCAH1A BPPB
Module processor board
communications
board
SSCAH1A Single or dual

Six serial Communications
Terminal Board Ethernet cables
communication ENET1
channels
ENET2
External 28 V dc
power supply
GEH-6721L PSCA Serial Communication I/O Module System Guide 20-1

Compatibility
PSCAH1A is compatible with the SSCAH1A terminal board, but not the DIN-rail
mounted DSCB board. The following table gives details of the compatibility:
Terminal Board DSCB SSCAH1A

Control mode No Simplex-yes
Installation
¾ To install the PSCA pack
2. Directly plug one PSCA pack into the terminal board connector.
Note The PSCA mounts directly to a Mark VIe SSCA terminal board. The simplex
terminal board has a single DC-62 pin connector that receives the PSCA.
ENET1 to the network associated with the R controller, however, the PSCA is not

Wizard again.

Operation
Processor




Status LEDs
Processor LEDs

present
LED Status

ATTN
or module.
ATTN
every 4 sec

Serial Channels
The BSCA board in the pack contains six independently configurable serial channels. The
processor board configures the channels with one of three mode inputs as follows:
Mode Transceiver
0 RS-232
1 RS-422
2 RS-485 half duplex only
3 Default/reset state (fail safe)
Jumpers on the SSCA terminal board are used to set up the terminal scheme
for the selected communication mode.
Data Flow from PSCA to Controller

Data flow from PSCA to the Mark VIe controller is of two types, fixed I/O and
Modbus I/O. Fixed I/O is associated with the smart pressure transducers and the
Kollmorgen® electric drive data. This data is completely processed every frame,
the same as conventional I/O. The required frame rate is 100 Hz. These signals
are mapped into signal space, using the .tre file, and have individual health bits,
use system limit checking, and have offset/gain scaling.
Modbus I/O is the I/O associated with the Modbus ports. Because of the quantity of these
signals, they are not completely processed every frame; instead they are packaged and
transferred to the Mark VIe controller, over the IONet through a special service. This
can accommodate up to 2400 bytes, at 4 Hz, or 9600 bytes at 1 Hz, or combinations
thereof. This I/O is known as second class I/O, where coherency is at the signal level
only, not at the device or board level. Health bits are assigned at the device level, the
Mark VIe controller expands (fully populate) for all signals, and system limit checking
is not performed. Two consecutive time outs are required before a signal is declared
unhealthy. Diagnostic messages are used to annunciate all communication problems.
Honeywell® Pressure Transducers: Serial ports 1 and 2 support the Honeywell

pressure configuration. It reads inputs from the Honeywell Smart Pressure
Transducers, type LG-1237. As an option (pressure transducers or Modbus)
this service is available only on ports 1 and 2. The pressure transducer protocol
utilizes interface board DS200XDSAG#AC, and RS-422. Each port can service
up to six transducers. The service is 375 kbaud, asynchronous, nine data bits,
(11 bits including start and stop). It includes communication miss counters, one
per device, and associated diagnostics as failsafe features.
After four consecutive misses, it forces the input pressure to 1.0 psi, and posts a diagnostic.
After four consecutive hits (good values) it removes the forcing and the diagnostic.

Kollmorgen Electric Drive: Three ports (any three, but no more than three) support
the Kollmorgen electric drive. It communicates with a Kollmorgen Electric Fast Drive
FD170/8R2-004 at a 19200 baud rate, point-to-point, using RS-422.
Serial Modbus Master Service: The current Modbus design supports the Master mode
on all six serial ports, however the design does not preclude the future enhancement of
Modbus slave mode of operation. It is configurable at the port level as follows:
• Physical connection: RS-232, RS-422, RS-485

• Baud Rate. 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115000
• Parity: none, odd, even
• Data Bits: seven, eight
• Stop Bits: one, two
• Station addresses
• Multidrop, up to eight devices per port; maximum of 18 devices per board
• RTU
• Time-out (seconds) per device
• 32-bit data format, i.e. byte format
• Device reponse delay time
The Modbus service is configurable at the signal level as follows:
• Signal type
• Register number
• Read/write
• Transfer rate, 0.5, 1, 2, or 4 Hz
• Scaling, offset, and gain
The service supports function codes 1-7, 15, and 16; it also supports double 16-bit
registers for floating point numbers and 32-bit counters. It periodically (20s)
attempts to reestablish communications with a dead station.
Type casting and scaling of all I/O signals to/from engineering units are supported
on the PSCA and the toolbox, for both fixed I/O and Modbus I/O.

Ethernet Modbus Master Service: The PSCA can use one of its two Ethernet ports
to support the Ethernet Modbus Master Protocol. This configuration can only be used
with a simplex network. The Ethernet IP address for Modbus can not be included in
the range of the IONET submask range. All Ethernet Modbus stations are configured
on Port 7 through the ToolboxST* application. The Ethernet Modbus implementation
follows the Open Modbus/TCP Specification for a Class 1 device.
The ToolboxST application will allow up to 18 Ethernet Modbus stations to be attached

to the PSCA. The CPU loading for each station varies depending on the number of
Modbus registers being requested and the update rate. Also, the field device connect
and data response rate may vary. Data throughput should be validated in system test
when multiple stations and/or large amounts of data are being transferred
The following parameters are defined for all stations on the PSCA Ethernet port,
• TCP/IP Address for the PSCA Ethernet port

• TCP/IP Subnet mask
• TCP/IP Gateway IP address of intermediate router. (optional)
The next set of parameters are defined for each field device station
• Field Device TCP/IP address

• Field Device TCP/IP port (Modbus default is 502)
• Modbus Station Address (optional)
• TCP/IP connection timeout (TCP/IP default is 75 seconds)
• TCP/IP read/write timeout
• 32-bit data format i.e. byte order
• Open Modbus/TCP IP protocol
The Modbus service is configurable at the signal level as follows:
• Signal type
• Register number
• Read/write
• Transfer rate, 0.5, 1, 2, or 4 Hz
• Scaling, offset, and gain
The service supports function codes 1-7, 15, and 16. It also supports double 16-bit
registers for floating point numbers and 32-bit counters. It periodically (20s)
attempts to re-establish communications with a dead station.
Type casting and scaling of all I/O signals to/from engineering units are supported on
the PSCA and the ToolboxST application, for both fixed I/O and Modbus I/O.

ID Line
Power Management
Connectors

Specifications
The following table provides information specific to the PSCA pack.
Item PSCA Specification

Channels Six independently configurable serial channels
One Ethernet Modbus Channel (simplex network)
Communication choices RS-232 Mode
RS-422 Mode
RS-485 Mode half duplex only
Ethernet Modbus Mode
RS-232 Mode Cable distance: 50 ft
Communication Rate: 19,200 baud maximum
RS-422 Mode Cable distance: 1000 ft
Communication Rate: 375 Kbps maximum
Number of Drops: 8
RS-485 Mode Cable distance: 1,000 ft
Communication Rate: 375 Kbps maximum
Number of drops: 8
Physical
Diagnostics

• Analog inputs such as pressure and position have system limit checking based on
configurable high and low levels. These limits can be used to generate alarms, to
enable/disable, and as latching/non-latching. RESET_SYS reset the out of limits


SSCA Simplex Serial Communication Input/Output
The Simplex Serial Communication Input/Output (SSCA) terminal board is a compact
serial communication terminal board that provides up to six communication channels.
Each channel may be configured for RS-232C, RS-485, or RS-422 signaling. The
PSCA I/O pack works with the SSCA. The I/O pack plugs into the DC-37 pin
connector and communicates with the controller over Ethernet.
Installation
There is no shield termination The SSCA board is mounted on a DIN-rail using a sheet metal carrier and plastic
strip with this design. insulator mount. This assembly will also bolt directly into a cabinet. There
are two types of Euro-Block terminal blocks available:
• SSCAH1 has a permanently mounted terminal block with 48 terminals.

• SSCAH2 has a right-angle header accepting a range of commercially available
pluggable terminal blocks, with 48 terminals.
Typically, SSCA uses #18 AWG (shielded twisted pair) wiring. The I/O cable shield
termination is on an external mounting bracket supplied by the customer or by GE.
The chassis ground connection uses E1 and E2 as mounting holes. One of the SCOM
terminals (37-48) must be connected to a suitable shield ground.
SSCA Jumper Positions

Operation
The SSCA terminal board includes six connection points for each of the six serial
communication channels. The points include four signal lines A-D, a signal return, and a
shield common (SCOM). The signal assignments are shown in the following table.
Protocol A B C D Notes
RS-422 TX+ TX- RX+ RX- Cable length up to 1000 ft.
RS-485 TX/RX+ TX/RX- Jumper Jumper Cable length up to 1000 ft
from A from B
RS-232 DTR/RTS TX CTS RX Cable length up to 50 ft or 2500 pF
Return for RS-232C is through the terminal called RET.
The signals for all six serial communication channels are arranged in the
same order. Viewing into the box terminals, the signal order is SCOM,
A, B, C, D, Ret viewed left to right.
The groups of six signals for a serial channel are assigned to terminals adjacent to each
other. Viewing the bottom set of terminals the channels are five, four, and one viewed
left to right. The top set of terminals contain channels six, three, and two viewed left to
right. The board SCOM connections are grouped on the right side of the terminals. A
simple diagram is included on SSCA to aid in identifying signal locations.
The explicit terminal board screw connections are:
SCOM A B C D RET
Channel 1 26 28 30 32 34 36
Channel 2 25 27 29 31 33 35
Channel 3 13 15 17 19 21 23
Channel 4 14 16 18 20 22 24
Channel 5 02 04 06 08 10 12
Channel 6 01 03 05 07 09 11
When using RS-422 or RS-485, there is the need to provide a termination resistor at
either end of a transmission line. SSCA provides selectable termination resistors for
each pair of signal lines. Jumpers JP1A and JP1B apply or remove the termination
resistors between signals A-B and C-D. The same function is repeated for each
serial communication channel. The default jumper position is to disconnect the
termination resistor. The SSCA is clearly marked to show the relationship of the
termination jumpers and the serial communication channel signals.

In RS-232C systems, it is often not desirable to have a hard ground of the RET signal
path on both ends of a cable. SSCA includes jumper selectable grounding options
for each of the six RET lines. The line may be grounded through a 100 Ω resistor
or through a 0.01 uF capacitor / 1M Ω resistor parallel combination. If the device
attached to SSCA features a hard ground of the RET line then the capacitive ground
should be selected on SSCA. If there is not a hard ground on the connected equipment
then the resistive ground (default position) should be selected on SSCA.
RET ground jumpers are identified on SSCA as JP1R through JP6R. Positions
are shown as RES and CAP for resistive and capacitive return connection.
The jumpers are clearly labeled on the SSCA.
Specifications
Item Specification
Number of channels Six channels
Termination resistors Jumper selectable between open and resistor of 121 Ω, ½ W, 1%.
RS-232C return path ground Selectable between resistive ground of 100 Ω, ½ W, 1% or
1M Ω, ½ W, 1% in parallel with 0.01 uF, 500 V, 10% capacitor.
Maximum drops in RS-422 or RS-485 systems Eight drops maximum
Temperature Operating: -30 to 65ºC (-22 ºF TO 149 ºF)

Diagnostics
Diagnostic tests are made on the terminal board components as follows:
The JA connector on the terminal board has its own ID device that is interrogated
by the PSCA I/O pack. The ID device is a read-only chip coded with the
terminal board serial number, board type, revision number, and the J connector
location. When this chip is read by the I/O processor and a mismatch is
Configuration
Configuration of the terminal board is by means of jumpers. For location of these
jumpers refer to the operation section. The jumper choices are as follows:
• Jumpers JP1A through JP6A apply or remove termination resistors between

signal lines A and B for the six serial communication channels.
• Jumpers JP1B through JP6B apply or remove termination resistors between
signal lines C and D for the six serial communication channels.
• Jumpers JP1R through JP6R select whether the return has a resistive
or capacitive connection to SCOM.
All other configuration for the PSCA is done from the ToolboxST application.
Electronic selection of the serial communications method, either RS-232,
RS-422, or RS-485, is internal to the PSCA.

DPWA Transducer Power Distribution
DPWA provides excitation The Transducer Power Distribution (DPWA) terminal board is a DIN-rail mounted power
power to LG-1237 Honeywell distribution board. It accepts input voltage of 28 V dc ±5%, provided through a two-pin
pressure transducers. Mate-N-Lok® connector. Connectors are provided for two independent power sources
to allow the use of redundant supplies. The input can accept power from a floating
isolated voltage source. The input to DPWA includes two 1 kΩ resistors from positive
and negative input power to SCOM. These center a floating power source on SCOM.
Attenuated input voltage is provided for external monitoring. Output power of 12 V dc
±5% is connected to external devices through a Euro- type terminal block, using screw
terminals and AWG#18 twisted-pair wiring. DPWA provides three output terminal pairs
with a total output rated at 0 to 1.2 A. The outputs are compatible with the XDSAG#AC
interface board. Outputs are short circuit-protected and self-recovering.

Installation
The DPWA terminal board Mount the DPWA assembly on a standard DIN-rail. Connect input power to connector P1.
includes two screw terminals, If multiple DPWA boards are used, use connector P2 as a pass-through connection point
15 and 16, for SCOM (ground) for the power to additional boards. If a redundant power input is provided, connect power
that must be connected to a to connector P3 and use connector P4 as the pass-through to additional boards. Connect the
good shield ground. wires for the three output power circuits on screw terminal pairs 9-10, 11-12, and 13-14.
DPWA Power Distribution Terminal Board P12 9

s P12V1
10
P28V dc P12R1
P28V dc to P12Vdc,
1 P1 P12 V dc 1.2 Amp P12 11
s P12V2
2 Isolation 12
P12R2
P2
P12 13
s P12V3
Return 14
s P12R3
15
SCOM
P3 16
SCOM
100k
P4
20 k
1
1k 1k PSRet
SCOM 2
Bus SCOM
centering
bridge 100 k 100 k
SCOM
20 k 20 k
3
SCOM PS28VA
4 SCOM
5
PS28VB
6
SCOM
DPWA Board Block Diagram

Operation
DPWA has an on-board power converter that changes the 28 V dc to 12 V
dc for the transducers. A redundant 28 V dc supply can be added if needed.
The following figure shows the DPWA power distribution system feeding
power to 12 LG-1237 pressure transducers.
Controller Fuel skid
Power for channel A XDSA P1

Outer valve
+ Adr= 0 Press Xdr
1 GP1OA
DPWA 12 Vdc +/-5% 2
Power LG-1237
1.2 Amp 3 Chan A
P1 P12 9 + 4
1 + 28 V P2
Return 10 5 Outer valve
2 to Adr= 1 Press Xdr
12 V 6 GP2OA
28 Vdc +/- 5% P12 LG-1237
11 + 7
Return 8
Isol 12
P2
1 P12 13 +
2 Return P3
14 Outer valve
+ Adr= 2 Press Xdr
Grd1 9 Power GP1OB
15 LG-1237
Redundant Grd2 10
power supply
16 11 Chan B
when required P3 12 P4
13 Outer valve
Adr= 3 Press Xdr
14 LG-1237 GP2OB
15
Return 100K Stab-on
1 16
SCOM 20K
2
P4
P28_J1 100K nearest gnd
3
SCOM 20K
4
P28_J2 100K 5
SCOM 20K 6 XDSA P1
Pilot valve
+ Adr= 4 Press Xdr
1 LG-1237 GP1PA
Power
2
3 Chan A
4 P2
5 Pilot valve
Adr= 5 Press Xdr
6 LG-1237 GP2PA
7
8
P3
Pilot valve
Adr= 6 Press Xdr
Power for channel B + 9 Power LG-1237
GP1PB
10
DPWA 12 V dc +/-5% 11 Chan B
12 P4
1.2 Amp Pilot valve
P1 13 Adr= 7 Press Xdr
P12 9 + 14 GP2PB
28 V LG-1237
to Return 10 15
12 V 16 Stab-on
P12 11 +
Return 12
Isol
P2 nearest gnd
P12 13 +
Return 14
Grd1 15
XDSA P1
Grd2 16 Inner valve
+ Adr= 8 Press Xdr
P3 1 Power LG-1237 GP1IA
2
3 Chan A
4 P2
5 Inner valve
Adr= 9 Press Xdr
Return 100K 6 LG-1237 GP2IA
P4 1 VDCx 7
SCOM 20K 2 Retx 8
P28_J1 100K 3 VDCx
SCOM 20K 4 Retx P3
Inner valve
P28_J2 100K + Adr= 10 Press Xdr
5 VDCx 9 Power GP1IB
20K LG-1237
SCOM 6 Retx 10
11 Chan B
12 P4
13 Inner valve
Power supply Adr=11 Press Xdr
14 LG-1237 GP2IB
monitoring 15
voltage 16 Stab-on
inputs
nearest gnd
DPWA Power Distribution to XDSA and Smart Pressure Transducers

Specifications
Item Specification
Number of Channels Three power output terminal pairs
Input voltage 28 V dc ±5%, provisions for redundant source
Input current Limited by protection to no more than 1.6 A steady state
Output voltage 12 V dc ±5%, maximum total current of 1.2 A, short circuit protected, and self-recovering
Monitor voltages Attenuated by 6:1 ratio
Diagnostics
DPWA features three voltage outputs to permit monitoring of the board input power.
The voltage monitor outputs are all attenuated by a 6:1 ratio to permit reading the 28
V dc using an input voltage with 5 V dc full scale input. Terminal 1 (PSRet) is the
attenuated voltage present on the power input return line. Terminal 3 (PS28VA) is the
attenuated voltage present on the P1 positive power input line. Terminal 5 (PS28VB) is
the attenuated voltage present on the P3 positive power input line. Terminals 2, 4, and 6
provide a return SCOM path for the attenuator signals. In redundant systems, monitoring
PS28VA and PS28VB permits the detection of a failed or missing redundant input. In
systems with floating 28 V power, with the input centered on SCOM, the positive and
return voltages should be approximately the same magnitude as a negative voltage on the
return. If a ground fault is present in the input power, it may be detected by positive or
return attenuated voltage approaching SCOM while the other signal doubles.
Configuration

XDSA Transducer Interface
XDSA provides signal routing The Transducer Interface (XDSA) terminal board is intended for installation adjacent
to type LG-1237 Honeywell to one or more type LG-1237 Honeywell® Smart Pressure Transducers featuring serial
Smart Pressure Transducers. communications. The board accepts 12 V dc input power and serial data communications
and routes the signals through four cables, with DB-25 connectors on each end,
compatible with the Honeywell sensors. The board is designed with two independent
circuits that support redundant sensor arrangements. Jumpers are provided to set
sensor addresses and to select serial communications termination resistance. XDSA
has features allowing connection of multiple XDSA boards in one system.
Installation
The following figure shows the wiring connections for the XDSA terminal board. Two
DPWA terminal boards supply 12 V dc ±5% to terminals 1, 2, 9, and 10. Terminals 3
through 8 and 11 through 16 are used for RS-422 multidrop communications. Each XDSA
terminal board functions as two independent boards. A stab-on ground connection is
located on each end of the board, one for each of the board sections. The board connects
to four pressure sensors using cables with DB25 connectors on each end.

Nearest Ground
Stab - on
Adr = 0 Cable with DB-25
+ pin connectors
1 on both ends
2
P1
3 Chan A
5 Adr = 1 Cable with DB-25

pin connectors
6 on both ends
7
P2
8
Adr = 2 Cable with DB-25

+ pin connectors
9
on both ends
10
P3
11
Chan B
12
13 Adr = 3 Cable with DB-25

pin connectors
14 on both ends
15
P4
16
Stab - on XDSA
Nearest Ground
XDSA Terminal Board Block Diagram
The following figure shows the power connection of three XDSA terminal boards and
two DPWA boards. DPWA boards supply 12 V dc ±5% using AWG#18 shielded
twisted-pair wiring. Each XDSA terminal board supplies power for four LG-1237
pressure transducers using cables with DB-25 connectors on each end.
Note Power is separated between the two sections of the XDSA terminal board
preserving the redundancy of the pressure sensing system. A separate ground is also
provided for each section of the board.

Controller Fuel Skid
XDSA P1
Outer Valve
Power for Chan A + 1 Power
Adr= 0 Press Xdr GP1OA
LG-1237
DPWA 2
12 Vdc +/-5%
3 Chan A
P1 1.2 Amp P12 +
28 V 9 4 P2
1 + Outer Valve
28 VDC +/-5% to Return 10 5 Press Xdr
2 Adr= 1 GP2OA
12 V 6 LG-1237
P12
11 + 7
Return 12 8
Isol
P2
1 P12 13 +
2 Return P3
14 Outer Valve
Adr= 2 Press Xdr
Grd1
+ 9 Power GP1OB
LG-1237
15 10
Redundant Grd2 Chan B
16 11
Power Supply
P3 12 P4
when Required Outer Valve
13 Adr= 3 Press Xdr
14 GP2OB
LG-1237
100K 15
Return 1 16 Stab-on
SCOM 20K
P4 2
P28_J1 100K Nearest Gnd
3
SCOM 20K
4
P28_J2 100K
5
SCOM 20K
6 XDSA P1
Pilot Valve
Adr= 4 Press Xdr
+ 1 GP1PA
Power LG-1237
2
3 Chan A
4 P2
5 Pilot Valve
Adr= 5 Press Xdr GP2PA
6 LG-1237
7
8
P3
Pilot Valve
Adr= 6 Press Xdr
+ 9 Power GP1PB
LG-1237
Power for Chan B 10
11 Chan B
DPWA 12 Vdc +/-5% 12 P4
Pilot Valve
P1 1.2 Amp P12 13 Adr= 7 Press Xdr
28 V 9 + 14
GP2PB
Return LG-1237
to 10 15
12 V 16 Stab-on
P12 +
11
Return
Isol 12
P2 Nearest Gnd
P12 +
13
Return
14
Grd1
15
Grd2 XDSA P1
Inner Valve
16
Adr= 8 Press Xdr
P3 + 1 GP1IA
Power LG-1237
2
3 Chan A
4 P2
5 Inner Valve
Adr= 9 Press Xdr GP2IA
Return 100K VDCx 6 LG-1237
P4 1 7
SCOM 20K
2 Retx 8
P28_J1 100K
3 VDCx
SCOM 20K
4 Retx P3
Inner Valve
P28_J2 100K Adr= 10 Press Xdr
5 VDCx + 9 Power GP1IB
20K LG-1237
SCOM 6 Retx 10
11 Chan B
12 P4
Power Supply Inner Valve
13 Adr=11 Press Xdr
Monitoring 14 GP2IB
LG-1237
15
16 Stab-on
nearest gnd
DPWA Power Supplies and XDSA Terminal Boards

The following figure shows the serial communication wiring for three XDSA terminal
boards connected to a pair of serial communication channels. The pass-through serial
path is wired for signals from the sensors to the control. Refer to Mark VI or Mark VIe
Serial Communication Controller documentation for specific connection points.
Controller Fuel Skid
XDSA P1
Adr= 0 Press Xdr Outer Valve
1
Power LG-1237 GP1OA
2
Chan A , RS 422
3
Chan A
+ 4
P2
Tx 5
Press Xdr Outer Valve
6 Adr= 1
Port #1 LG-1237 GP2OA
7
+
Rx 8
P3
Adr= 2 Press Xdr Outer Valve
Chan B, RS 422 9
Power LG-1237 GP1OB
+ 10
Tx 11 Chan B
12
Port #2 13
P4
+ Adr= 3 Press Xdr Outer Valve
Rx 14 GP2OB
LG-1237
15
16 Stab-on
Nearest Gnd
XDSA P1
Adr= 4 Press Xdr Pilot Valve
1 LG-1237 GP1PA
Power
2
3 Chan A
4 P2
5 Press Xdr Pilot Valve
Adr= 5
6 LG-1237 GP2PA
7
8
P3
Adr= 6 Press Xdr Pilot Valve
9 Power LG-1237 GP1PB
10
11 Chan B
12 P4
13 Press Xdr Pilot Valve
Adr= 7
14 LG-1237 GP2PB
15
16 Stab-on
Nearest Gnd
XDSA P1
Adr= 8 Press Xdr Inner Valve
1 Power LG-1237 GP1IA
2
3 Chan A
4 P2
5 Press Xdr Inner Valve
Adr= 9
6 LG-1237 GP2IA
7
8
P3
Adr= 10 Press Xdr Inner Valve
9 Power LG-1237 GP1IB
10
11 Chan B
12 P4
13 Adr=11 Press Xdr Inner Valve
14 LG-1237 GP2IB
15
16 Stab-on
Nearest Gnd
XDSA Serial Communication Wiring Diagram

Operation
The following figure shows the functional block diagram for the XDSA terminal
board. It shows the actual board layout. Input terminal 1 and output connector P1
are at the bottom of the board. Input power of 12 V dc ±5% is applied to terminals
1 (positive) and 2 (negative). Serial transmissions from a control are received on
terminals 3 (positive) and 4 (negative) with transmission path termination set by
jumper JP1. Serial output from connected pressure sensors is on terminals 5 (positive)
and 6 (negative). Terminals 7 (positive) and 8 (negative) provide a pass-through
path for an additional XDSA board as shown in the Installation section. Device
address selections are determined by jumpers JP3 and JP4.
XDSA
SHLD2
0BCHAIN
16 -
1BCHAIN
RX
15 +
0COMBR
14 -
1COMBR
TX P4
13 +
0COMBT
12 -
RX
11 1COMBT
+
10 DCOMB JP2
9 P12VB
0 0 P3
1 JP5 1 JP6
Power
Supplies
0ACHAIN
8 -
1ACHAIN
RX
7 +
0COMAR
6 -
1COMAR
TX P2
5 +
0COMAT
4 -
RX
3 1COMAT
+
2 DCOMA JP1
1 P12VA
0 0 P1
1 JP3 1 JP4
Power
Supplies
SHLD1
DPWA Power Distribution to XDSA and Smart Pressure Transducers

Specifications
Item Specification
Number of Channels DB-25 connections for four pressure sensors
Input voltage 12 V dc ±5% from DPWA or equivalent
Diagnostics
No diagnostic features are provided on this module.
Configuration
Six jumpers are provided on the XDSA terminal board to select both RS-422 serial
communication termination resistors and the address of the pressure sensors.
Jumpers JP1 and JP2 determine if the serial input terminating resistor is in or out.
In is selected for the XDSA board that is at the end of the transmission path. Out
is selected for all other XDSA boards within the signal path.
Jumpers JP3 through JP6 set the address of the sensors wired to P1 through P4. The sensor
address is set by four signals on the DB-25 connector. The signals are a combination of
fixed wiring and jumper positions on the two least significant bits. Each jumper has two
positions, labeled 0 and 1. See the following table to determine the correct sensor address.
Connector A3 (8) A2 (4) A1 (2) A0 (1) Possible Values

P1 JP4 JP3 0 0 0, 4, 8
P2 JP4 JP3 0 0 1, 5, 9
P3 JP6 JP5 1 0 2, 6, 10
P4 JP6 JP5 1 1 3, 7, 11

PSVO Servo Control Module
Servo Control (PSVO)

SERVO The Servo Control (PSVO) pack provides the electrical interface between one or two I/O
PWR Ethernet networks and a TSVO servo terminal board. The pack contains a processor
ATTN board common to all Mark* VIe distributed I/O packs and an I/O board specific to the
servo function. The pack uses the adjacent WSVO servo driver module to handle two
servo valve position loops, with a selection of five servo valve output currents from
LINK
ENET1 10-120 mA dc. The pack supplies LVDT excitation, and accepts eight LVDT feedbacks
TxRx
and two pulse rate inputs from fuel flow meters.
LINK
ENA1 ENET2 Input to the pack is through dual RJ45 Ethernet connectors, and 28 V dc power is
TxRx
ENA2
supplied from the terminal board. Output is through a DC-62 pin connector that connects
directly with the associated terminal board connector. Visual diagnostics are provided
IR PORT through indicator LEDs.
IS220PSVOH1A
PSVOCH1A
Servo Pack BPPB
BSVOH1A processor board
board
Single or dual
Ethernet cables
TSVCH1A ENET1
Servo
Terminal WSVO
Board ENET2
Servo
driver
Servo coil outputs
LVDT excitation
LVDT inputs
Pulse rate inputs ENET1
WSVO ENET2
Three PSVO packs and WSVOs for TMR

ENET1
One PSVO pack and WSVO for Simplex
WSVO ENET2
GEH-6721L PSVO Servo Control Module System Guide 21-1

Compatibility
PSVOH1A is compatible with the Servo Terminal Board TSVCH1A, but
not the DIN-rail mounted DSVO board or the TSVOH1B. The following
table gives details of the compatibility:
Terminal Board TSVCH1A TSVOH1B DSVO SSVO

Control mode Simplex-yes Dual - yes TMR-yes No No Simplex-yes
Installation
The PSVO along with its ¾ To install the PSVO pack
associated WSVO servo driver
assembly mounts directly
to a Mark VIe TSVOH1D 2. Directly plug one (simplex) or three I/O packs (for TMR) into
terminal board. the terminal board connectors.
3. Mechanically secure the I/O packs using the threaded inserts adjacent to the Ethernet
4. Plug the WSVO servo driver assemblies into the J2 48-pin connectors
and secure with the four screws.
5. Plug in one or two Ethernet cables depending on the system configuration. The I/O
pack operates over either port. If dual connections are used, standard practice is to
hook ENET1 to the network associated with the R controller, however, the PSVO is
not sensitive to Ethernet connections and negotiates proper operation over either port.
6. Apply power to the I/O packs and drivers using the power switches on TSVO. Use
SW3 for R, SW2 for S, and SW1 for T, and check the indicator lights.
7. Use the ToolboxST* application to configure the I/O packs as necessary.

Wizard again.

Operation
Processor




Status LEDs
Processor LEDs

present
LED Status

ATTN
or module.
ATTN
every 4 sec

Recalibration
BSVO Servo Board

The BSVO board multiplexes 24 analog channels into a 16-bit A/D converter. The
100 kHz A/D has a ±10 V dc range, and handles the servo current regulator signals,
the LVDT inputs, and power supply monitoring. The current references for the
analog current regulators on WSVO are generated on the BSVO by a 14-bit D/A
converter. Excitation for the LVDTs is developed using a D/A converter outputs a
sine wave with a frequency of 3.2 kHz. This is filtered and passed to the WSVO.
The board provides signal conditioning for two pulse rate channels and passes the
signals to the processor board to determine the pulse rate.
WSVO Servo Driver Assembly

The servo driver assembly has a power supply that converts the P28 voltage input to a
positive 15 V and negative 15 V output for the servo current regulator circuits. There are
two servo current regulators working off the current references from the servo pack.
The servo driver circuit has a selection of five configurable gains, and the assembly
contains the servo suicide relays and excitation output driver circuits.
Verification
The three ways to verify servo performance through stroking the actuator are manual,
position ramping, and step current. In manual mode, the desired value is entered
numerically and the performance monitored from the trend recorder. Select Verify
Position to apply a ramp to the actuator, and select Verify Current to apply a step input to
the actuator. The trend recorder displays any abnormalities in the actuator stroke.
ID Line
Power Management

Speed Pickups
An interface is provided for two passive magnetic speed inputs or two TTL
active sensor inputs with a frequency range of 2 to 12,000 Hz. The PSVO
signal-conditioning circuit is optimized for flow divider sensors, whereas the
PTUR circuit is optimized for primary speed inputs.
Pulse rate inputs can be configured for a variety of applications. Flow types are used for
flow divider fuel flow measurements. Speed type is used for normal single shaft turbines.
Speed high type provides extended speed range above the standard speed type. Speed LM
type is designed for LM applications. Speed_HSNG type is used for applications where
compensation for inconsistent tooth spacing on the speed wheel is desired. This pulse
rate type will map the spacing of the teeth on the speed wheel in order to remove this
periodic variation from speed measurements. Mapping locked status bits (HSNGn_Stat)
are in signal space so that the mapping status of the algorithm can be observed. If
the status indicator for a pulse rate input is false then the mapping algorithm sees too
much variation in the tooth-tooth measurements to lock onto the tooth geometry. The
Lock_Limit parameter can be adjusted in 1% increments to allow for more tooth-to-tooth
variation per revolution caused by some of the following issues: magnetized speed wheel,
electro-magnetic interference from outside sources and improper wiring or shielding
practices. Increasing the Lock_Limit value will allow the next generation speed algorithm
to stay locked with increased variation. Warning: The cost for opening the Lock_Limit
will allow for more speed variation. If the speed variation is too high when opening up the
Lock_Limit, go to the source of the problem as listed above and correct the issue there.
Connectors

Specifications
The following table provides information specific to the PSVO I/O pack and WSVO driver.
Item Specification
Number of inputs Eight LVDT windings
Two pulse rate signals
Number of outputs Two servo valve currents
Two excitation sources for LVDTs
Two excitation sources for pulse rate transducers
Power supply voltage Nominal 28 V dc
LVDT accuracy 1% with 14-bit resolution
LVDT input filter Low pass filter with 3 down breaks at 50 rad/sec ±15%
LVDT common mode rejection CMR is 1 V, 60 dB at 50/60 Hz
LVDT excitation output Frequency of 3.2 ±0.2 kHz
Voltage of 7.00 ±0.14 V rms
Pulse rate accuracy 0.05% of reading with 16-bit resolution at 50 Hz frame rate
Noise of acceleration measurement is less than ±50 Hz/sec for a 10,000 Hz signal being
read at 10 ms
Pulse rate input Minimum signal for proper measurement at 2 Hz is 33 mVpk, and at 12 kHz is 827 mVpk
Magnetic PR pickup signal Generates 150 V p-p into 60 kΩ
Active PR Pickup Signal Generates 5 to 27 V p-p into 60 kΩ
Servo valve output accuracy 2% with 12-bit resolution
Dither amplitude and frequency adjustable
Fault detection Servo current out of limits or not responding
Regulator feedback signal out of limits
Servo suicided
Calibration voltage range fault
The LVDT excitation is out of range
The input signal varies from the voted value by more than the TMR differential limit
Failed ID chip
Physical

Diagnostics



Configuration
IS200TSVC Variable Definitions

ServoOutput# Servo Output X measured current in percent. Point Edit (Input Real)
where # = 1 or 2
RegNumber Maps a specific regulator to a given servo output. Unused, Reg1, Reg2
(Default-Unused)
Servo_MA_Out Nominal servo current rating in milliamperes. 10 mA, 20 mA, 40 mA, 80 mA,
120 mA
(Default-10 mA)
EnablCurSuic Enable Current Suicide Function Enable, Disable
(Default-Disable)
EnablFbkSuic Enable Position Feedback Suicide Function Enable, Disable
(Default-Disable)
EnblAutGain Enable Auto Gain function. Approved for 4_LV_LM, 3_LVLMX and Enable, Disable
4_LVLMX regulator configurations. (Default-Disable)
Coil_RS_Only Configuration parameter is enabled when the PSVO is driving a 2-coil Enable, Disable
servo. For 2-coil servo, no load is connected to the SxTH/L where x (Default-Disable)
= 1or 2 terminal screws.
AV_Selector Configuration selector to map one of the specified variables to the Coil_OHMs,
PSVO variable, ServoxMonitorNV where x = 1 or 2. Compliance_Voltage
LM_Auto_Gain
MA_CMD_PCT
(Default-Compliance_Voltage)
Curr_Suicide Current command is compared to the actual feedback current. If 0 to 100
the error exceeds the configuration limit, Curr_Suicide (%), then the (Default-5)
Servo output will suicide.
Fdbk_Suicide The position feedback, Regx_Fdbk (%) is compared against the 0 to 100
value, 100% + Fdbk_Suicide (%). If Regx_Fdbk (%) where x = 1 or (Default-5)
2 exceeds that value, the regulator assumes the feedback has gone
open loop and the servo must be suicided if this condition and the
EnablFbkSuic = Enable.
OpenCoilSuic If configuration parameter, OpenCoilSuic = Enable, then the servo coil Enable, Disable
open detection function will suicide the servo if the function detects an (Default-Disable)
open ckt. Note: Set OpenCoildiag = Enable to receive a diagnostic
message to why the servo suicide occurred.
ShrtCoilSuic If configuration parameter, ShrtCoilSuic = Enable, then the servo Enable, Disable
coil short ckt. detection function will suicide the servo if the function (Default-Disable)
detects a short ckt. Note: Set ShrtCoildiag = Enable to receive a
diagnostic message to why the servo suicide occurred.
OpenCoildiag If enabled, a specific diagnostic message is generated for why the Enable, Disable
servo suicide occurred; i.e. Servo x Suicide due to Open servo coil. (Default-Disable)

ShrtCoildiag If enabled, a specific diagnostic message is generated for why the Enable, Disable
servo suicide occurred; i.e. Servo x Suicide due to Short circuit of (Default-Disable)
servo coil.
TBmAJmpPos TSVC terminal board mA jumper position selection. This should 10 mA, 20 mA, 40 mA, 80 mA,
match the jumper selection on the TSVC to allow the open / short 120 mA_A, 120 mA_B
circuit servo coil detection to work correctly. (Default-10 mA)
RopenTimeLim Time in seconds required for the open circuit condition of the servo 0 to 100
coil to be in effect before a diagnostic and / or suicide of the servo (Default-1)
(if enabled) occurs.
RShrtTimeLim Time in seconds required for the short circuit condition of the servo 0 to 100
coil to be in effect before a diagnostic and / or suicide of the servo (Default-1)
(if enabled) occurs.
RcoilOpen Defines the initial value for the open circuit resistance in ohms. After 1 to 10E+09
the LVDT calibration, the value for RcoilOpen = 2 * (Servo Compliance (Default- 1000000)
Voltage / Servo Current) measured during the calibration mode.
RcoilShort Defines the initial value for the short circuit resistance in ohms. 1 to 10E+09
After the LVDT calibration, the value for RcoilShort = 0.5 * (Servo (Default- 0)
Compliance Voltage / Servo Current) measured during the calibration
mode.
TMR_DiffLimt Diagnostic limit, TMR Input Vote difference in % 0 to 110
(Default-25)
FlowRatex Bipolar input = PRxH – PRxL, Point Edit (Input Real)
where x = 1 or 2 Unipolar = TTLx - PRxL
PRType Define the pulse rate feedback type or basic speed range. See Flow, Speed, Speed_High,
section Speed Pickups for description of types. Speed_HSNG, Speed_LM,
Unused
PRScale Scaling: pulses per revolution (outputs RPM) 0 to 1000
TeethPerRev Number of teeth on speed wheel (per revolution) 1 to 512
Speed_x_ms Calculation rate of speed in milliseconds. Speed is calculated at this 5 to 1000
rate and averaged over the previous time interval specified by this
period.
Using a value other than an integer multiple of

the application frame period can have adverse
impact on use of this control.
Attention

Accel_x_ms This is the averaging period for acceleration calculation in 10 to 1000
milliseconds. The acceleration is calculated every Accel_X_ms. It
is based on the difference between two speed samples divided by
the sample period. Each acceleration calculation is the average of
acceleration over the period specified by this parameter. For example,
if Accel_x_ms is 40 then acceleration will be the average acceleration
over the previous 80 ms.
Using a value other than an integer multiple of

the application frame period can have adverse
impact on use of this control.
Attention
Lock_Limit HSNG speed type locking limit for teeth mapping (percent). See 1 to 100
section Speed Pickups for description of Lock_Limit function.
SysLim1Enabl If enabled, System Limit 1 is active. Enable, Disable
(Default-Disable)
SysLim1Latch If enabled, the System Limit 1 function will latch its state if the Latch, NotLatch
FlowRate exceeds the limit function defined by SysLim1Type and (Default-Latch)
SysLimit1.
SysLim1Type Defines the compare function used in the Limit1 expression. >=, <=
(Default->;=)
SysLimit1 Defines Limit1 value to be used for the input, FlowRate. 0 to 20,000
(Default-0)
SysLim2Enabl If enabled, System Limit 2 is active. Enable, Disable
(Default-Disable)
SysLim2Latch If enabled, the System Limit 2 function will latch its state if the Latch, NotLatch
FlowRate exceeds the limit function defined by SysLim2Type and (Default-Latch)
SysLimit2.
SysLim2Type Defines the compare function used in Limit 2’s expression. >=, <;=
(Default->=)
SysLimit2 Defines Limit2 value to be used for the input, FlowRate. 0 to 20,000
(Default-0)
TMR_DiffLimt Diagnostic limit, TMR Input Vote difference in % 0 to 20,000
(Default-5)
Regulator
Parameters
Common The following parameters are common for all regulator
Reg_Type Regulator Algorithm Type Unused, no_fbk, 1_LVposition,
1_PulseRate, 2_LVpilotCyl,
2_LVposMAX, 2_LVposMIN,
2_PlsRateMAX, 3_LV_LMX,
3_LVposMID, 4_LV_LM,
4_LV_LMX, 4_LVp/cylMAX

Dither_Freq Dither rate in hertz. 12_5hz, 25hz, 33_33hz, 50hz,
100hz, Unused
(Default-100hz)
DitherAmpl Dither in % current 0 to 10
(Default-2)
LVDT_Margin Defines the over range in % for the LVDT input. A diagnostic is 0 to 100
generated if this value is exceeded. (Default-2)
LVDT1input LVDT input selection LVDT1, LVDT2, LVDT3,
LVDT4, LVDT5, LVDT6,
LVDT7, LVDT8, Unused
(Default-Unused)
RegGain Position loop Gain in % current / Eng Units or usually % current / -200 to +200
% position. (Default-1)
RegNullBias Regulator Null Bias provides a fixed current command in percent to -100 to +100
cancel or null the spring force of the valve which will close the valve if (Default-0)
the servo suicides or shuts down.
TMR_DiffLimt Diagnostic limit, TMR Input Vote difference in % 0 to 150
(Default-5)
RegType Pulse Rate Regulator used with a single LVDT Input. = 1 LV position
MaxPOSvalue Position in Eng. units (usually %) at the maximum end stop of the -15 to 150 (Default-100)
valve.
MinPOSvalue Position in Eng. Units (usually %) at the minimum end stop of the -15 to 150 (Default-0)
valve.
MnLVDT1_Vrms LVDT1 Vrms at the minimum end stop of the valve. These values are 0 to 7.1 (Default-1)
normally set by the Auto-Calibrate function. For TMR, the first value is
LVDT1 Vrms from PSVO-R’s perspective, the second from PSVO-S
and the last from PSVO-T’s perspective.
MxLVDT1_Vrms LVDT1 Vrms at the maximum end stop of the valve. These values are 0 to 7.1 (Default-1)
LVDT1 Vrms from PSVO-R’s perspective, the second from PSVO-S
RegType Pulse Rate Regulator used with a single fuel flow divider = 1_PulseRate
feedback.
PRateInput1 Pulse Rate input selection PR1, PR2, Unused
(Default-Unused)
RegType Pilot Cylinder Regulator with two LVDT position feedbacks. = 2_LVpilotCyl
MaxPOSvalue Position in Eng. units (usually %) at the maximum end stop of the -15 to 150
valve. (Default-100)
MinPOSvalue Position in Eng. Units (usually %) at the minimum end stop of the -15 to 150
valve. (Default-0)
MnLVDTx_Vrms LVDTx Vrms at the minimum end stop of the valve. These values are 0 to 7.1
where x = 1 to 2 (Default-1)
LVDTx Vrms from PSVO-R’s perspective, the second from PSVO-S

MxLVDTx_Vrms LVDTx Vrms at the maximum end stop of the valve. These values are 0 to 7.1
PilotGain Pilot loop gain in % current / Eng. unit -200 to +200
(Default-1)
RegType Position Regulator using the maximum select from 2 LVDT = 2_LVposMAX
inputs for feedback.
valve. (Default-0)
RegType Position Regulator using the minimum select from 2 LVDT inputs = 2_LVposMIN
for feedback.
valve. (Default-0)
RegType Pulse Rate Regulator using the maximum select from two fuel = 2_PlsRateMAX
flow divider feedbacks.
PRateInput1 Pulse Rate 1 input selection PR1, PR2, Unused
(Default-Unused)
PRateInput2 Pulse Rate 2 input selection PR1, PR2, Unused
(Default-Unused)
RegType Position Regulator using the median select from 3 LVDT inputs = 3_LV_LMX
for feedback. Originally designed for the LMX100 gas turbine.
CurBreak Current break for nonlinear servo current 0 to 100
(Default-2)
CurClpNg Servo Current Clamp (%) Negative -300 to 300
(Default -300)

CurClpPs Servo Current Clamp (%) Positive -300 to 300
(Default- 300)
CurSlope1 Slope current gain modifier for low position error values 0 to 10
(Default-1)
CurSlope2 Slope current gain modifier for position error > CurBreak limit 0 to 10
(Default-1)
DefltValue If all position sensors or LVDTs are bad, the regulator feedback is 0 to 110
assigned to this value in percent. (Default-100)
LagTau Position loop Lag Breakpoint (seconds), zero to disable 0 to 10
(Default-0)
LeadTau Position loop Lead Breakpoint (seconds), zero to disable 0 to 10
(Default-0)
valve. (Default-0)
SelectMinMax If 2 of the 3 LVDTs are healthy, this parameter determines whether Max, Min
a minimum select or maximum select is made for the remaining two (Default-Max)
sensors.
SensorOofRTD Sensor Out of Range Time Delay (seconds) 0 to 2000
(Default-10)
SenSpreadMx Sensor Spread Maximum (%) -2000 to 2000
(Default-1000)
SensoSpreadTD Sensor Spread Time Delay (seconds) 0 to 2000
(Default-10)
RegType Position Regulator using the median select from 3 LVDT inputs = 3_LVposMID
for feedback. Originally designed for heavy-duty gas turbines.
valve. (Default-0)

RegType Position Regulator selecting one of two ratio-metric LVDT pairs =4_LV_LM
for the position feedback. Originally designed for the LM1600,
LM2500, and LM6000 gas turbines.
(Default-2)
(Default -300)
(Default- 300)
(Default-1)
(Default-1)
(Default-0)
(Default-0)
LVDTVsumMarg Allowable rang exceed error (%) for ratio-metric sum 1 to 100
(Default-2)
MaxPOSvalue Position in Eng. Units (usually %) at the maximum end stop of the -15 to 150
valve. (Default-0)
PosDefltEnab Position Default Enable / Disable Enable, Disable
(Default-Enable)
PosDiffcmp1 Position Difference Limit1 (%) 0 to 110
(Default-3)
PosDiffcmp2 Position Difference Limit2 (%) 0 to 110
(Default-3)
PosDifftime1 Position Difference Limit1 Timeout (seconds) 0 to 10
(Default-0.5)

PosDifftime2 Position Difference Limit2 Timeout (seconds) 0 to 10
(Default-0.5)
PosSelect Position Selection Mode Avg, Max, Min
(Default-Avg)
RegType Position Regulator selecting from 2 LVDT ratio-metric pairs for = 4_LV_LMX
feedback.
(Default-2)
(Default- -300)
(Default- 300)
(Default-1)
(Default-1)
(Default-0)
(Default-0)
valve. (Default-0)
SelectMinMax If 2 of the 3 LVDTs are healthy, this parameter determines whether Max, Min
a minimum select or maximum select is made for the remaining two (Default-Max)
sensors.
SensorOofRTD Sensor Out of Range Time Delay (seconds) 0 to 2000
(Default-10)
SenSpreadMx Sensor Spread Maximum (%) -2000 to 2000
(Default-1000)
SensoSpreadTD Sensor Spread Time Delay (seconds) 0 to 2000
(Default-10)
SenSumChkTD Volts RMS Sum Check Out of Range Time Delay (seconds) 0 to 2000
(Default-10)

RegType Pilot Cylinder Regulator with two LVDT position feedbacks. = 4_LVp/cylMAX
valve. (Default-0)
PilotGain Pilot loop gain in % current / Eng. unit -200 to +200
(Default-1)
Parameter Description Value Range / Default

MonType Monx will equal sensor position expressed in percent assigned in the = 1_LMposition
4_LV_LM regulator where x = 1 to 8
LMPOSin Maps RegxSenyPos in Dither rate in hertz. Reg1SenAPos,
Reg1SenBPos,
Reg1SenCPos,
Reg1SenDPos,
Reg2SenAPos,
Reg2SenBPos,
Reg2SenCPos,
Reg2SenDPos,
Unused
(Default-Unused)
TMR_DiffLimt Diagnostic limit, TMR Input Vote difference in % -10 to 150
(Default-5)
MonType Monx will equal sensor position expressed in Vrms assigned in the = 1_LMVRMS
4_LV_LM regulator where x = 1 to 8
LMPOSin Maps RegxSenyPos in Dither rate in hertz. Reg1SenAVrms,
Reg1SenBVrms,
Reg1SenCVrms,
Reg1SenDVrms
Reg2SenAVrms,
Reg2SenBVrms,
Reg2SenCVrms,
Reg2SenDVrms,
Unused
(Default-Unused)
MonType Monx will equal the scaled value from the LVDT assigned through = 1_LVposition
LVDT1input where x = 1 to 8
LVDT_Margin Defines the over range in % for the LVDT input. A diagnostic is generated 0 to 100
if this value is exceeded. (Default-2)

LVDTxinput LVDTx input selection LVDT1, LVDT2, LVDT3,
where x = 1
(Default-Unused)
MaxPOSvalue Position in Eng. units (usually %) at the maximum end stop of the valve. -15 to 150
(Default-100)
MinPOSvalue Position in Eng. Units (usually %) at the minimum end stop of the valve. -15 to 150
(Default-0)
where x = 1 (Default-1)
LVDTx Vrms from PSVO-R’s perspective, the second from PSVO-S and
the last from PSVO-T’s perspective.
where x = 1 (Default-1)
MonType Monx will equal the maximum selected scaled value from two LVDTs = 2_LVposMAX
assigned through LVDTyinput where x = 1 to 8 and y = 1 to 2.
where x = 1 to 2
(Default-Unused)
(Default-100)
(Default-0)
(Default-5)
MonType Monx will equal the minimum selected scaled value from two LVDTs = 2_LVposMIN

where x = 1 to 2
(Default-Unused)
(Default-100)
(Default-0)
(Default-5)
MonType Monx will equal the median selected scaled value from three LVDTs = 3_LVposMID
where x = 1 to 3
(Default-Unused)
(Default-100)
(Default-0)
where x = 1 to 3 Diagnostic limit, TMR Input Vote difference in % (Default-1)
-10 to 150
(Default-5)

PSVO Variable Definitions
Name Description Description Type

L3DIAG_PSVO PSVO I/O Diagnostic indication Input non-voted Boolean-3
bits
LINK_OK_PSVO PSVO I/O Link OK indication Input non-voted Boolean-3
bits
ATTN_PSVO PSVO I/O Attention indication Input non-voted Boolean-3
bits
PS18V_PSVO PSVO I/O 18 V Power Supply indication Input non-voted Boolean-3
bits
PS28V_PSVO PSVO I/O 28 V Power Supply indication Input non-voted Boolean-3
bits
IOPack_Tmpr PSVO I/O Pack Temperature (deg °F) Analog Input non-voted Real
Rx_SuicideNV ServoOutputx Suicide relay status where x = 1 or 2 Input non-voted Boolean-3
bits
RegxFbkFail Regulator x feedback fault status where x = 1 or 2 Input voted Boolean
RegxSenorSpreadAlm Regulator x Sensor Spread Alarm status where x = 1 or 2 Input voted Boolean
Reg1Suicide ServoOutput1 Suicide relay status Input voted Boolean
Reg2Suicide ServoOutput2 Suicide relay status Input voted Boolean
HSNG1_Stat Pulse rate 1 high speed next generation stability status (TRUE Input voted Boolean
for tooth – tooth distance inside Lock_Limit for tooth geometry
compensation)
HSNG2_Stat Pulse rate 2 high speed next generation stability status (TRUE Input voted Boolean
compensation)
Reg1_PosAFlt Regulator 1 4_LV_LM Position A failure Input voted Boolean
Reg2_PosAFlt Regulator 2 4_LV_LM Position A failure Input voted Boolean
Reg1_PosBFlt Regulator 1 4_LV_LM Position B failure Input voted Boolean
Reg2_PosBFlt Regulator 1 4_LV_LM Position B failure Input voted Boolean
Reg1_PosDif1 Regulator 1 4_LV_LM Position Difference 1 failure Input voted Boolean
Reg1SenAFlt Regulator 1 Sensor A fault Input voted Boolean
Reg1SenBFlt Regulator 1 Sensor B fault Input voted Boolean
Reg1SenCFlt Regulator 1 Sensor C fault Input voted Boolean
Reg1SenDFlt Regulator 1 Sensor D fault Input voted Boolean
Reg2SenAFlt Regulator 2 Sensor A fault Input voted Boolean
Reg2SenBFlt Regulator 2 Sensor B fault Input voted Boolean
Reg2SenCFlt Regulator 2 Sensor C fault Input voted Boolean
Reg2SenDFlt Regulator 2 Sensor D fault Input voted Boolean
RegCalMode Regulator under Calibration Input voted Boolean

Reg1SenA2LVSumFlt Regulator 1 Sensor A 2LV Summation Fault Input voted Boolean
Reg1SenB2LVSumFlt Regulator 1 Sensor B 2LV Summation Fault Input voted Boolean
Reg2SenA2LVSumFlt Regulator 2 Sensor A 2LV Summation Fault Input voted Boolean
Reg2SenB2LVSumFlt Regulator 2 Sensor B 2LV Summation Fault Input voted Boolean
Reg1_Fdbk Regulator 1 position feedback Analog Input voted REAL
Reg2_Fdbk Regulator 2 position feedback Analog Input voted REAL
MiscFdbk1a Regulator 1 Position A when 4_LV_LM, Analog Input voted REAL
Pilot when one of the Pilot Cylinder regs.
MiscFdbk1b Regulator 1 Position B when 4_LV_LM, Analog Input voted REAL
MiscFdbk2a Regulator 2 Position A when 4_LV_LM, Analog Input voted REAL
MiscFdbk2b Regulator 2 Position B when 4_LV_LM, Analog Input voted REAL
Reg1_Error Position error for the Regulator 1 position loops and pulse rate Analog Input voted REAL
error for the Pulse Rate reg.
Reg2_Error Position error for the Regulator 2 position loops and pulse rate Analog Input voted REAL
error for the Pulse Rate reg.
Accel1 Acceleration value of the card point FlowRate1 Analog Input voted REAL
Accel2 Acceleration value of the card point FlowRate2 Analog Input voted REAL
Monx Value assigned to Monx based on configuration parameters Analog Input voted REAL
found in the Monitor Tab.
where x = 1 to 8
Excit_Monx Excitation Monitor x (Vrms) where x = 1 or 2 Analog Input voted REAL
Reg1FdbkSelState 3LVLMX or 4LVLMX Regulator 1 Sensor Tri-select State Input DINT
Reg2FdbkSelState 3LVLMX or 4LVLMX Regulator 2 Sensor Tri-select State Input DINT
ServoOutxNV Servo Output x measured current (%) where x = 1 or 2 Analog Input non-voted Real
ServoxMonitorNV Servo x AvSelection Monitor where x = 1 or 2 Analog Input non-voted Real
CalibEnab1 Enable Calibration Regulator 1 Output Boolean
CalibEnab2 Enable Calibration Regulator 2 Output Boolean
SuicidForcex Force Suicide on Servo x where x = 1 or 2 Output Boolean
PosDiffEnabx Position Difference Enable for Regulator 1 when configured Output Boolean
as 4_LV_LM where x = 1 or 2
Reg1SenxFReq Force a Sensor A fault on Regulator 1 configured as 4LVLMX Output Boolean
or 3LVLMX where x = A, B, C, and D
Reg2SenxFReq Force a Sensor A fault on Regulator 2 configured as 4LVLMX Output Boolean
or 3LVLMX where x = A, B, C, and D
XSuicServo1 X pack Force Suicide for Servo 1 where X = R, S, and T Output Boolean
XsuicServo2 X pack Force Suicide for Servo 2 where X = R, S, and T Output Boolean
Regx_Ref Regulator x Position reference (%) where x = 1 or 2 Output Boolean
Regx_NullCor Regulator x Null Bias Correction (%) where x = 1 or 2 Output Boolean

SysLimxPRn System Limit for pulse rate input X, where x=1 or 2 and n=1 Input Boolean
or 2
ActivateCalibCmd Activate calibration command Inputed voted Boolean

TSVC Servo Input/Output
The Servo Input/Output (TSVC) terminal board interfaces to two electro-hydraulic servo
valves that actuate the steam/fuel valves. Valve position is measured with linear variable
differential transformers (LVDT). TSVC is designed specifically for the PSVO I/O pack
and the WSVO servo driver, and will not work with the VSVO processor. The terminal
board supports simplex, dual, and TMR control. Three 28 V dc supplies come in through
plug J28. Plugs JD1 or JD2 are for an external trip from the protection module.
TSVCH1A Terminal Board

External trip DC-48 pin connector
JD1 JD2
x DC-62 pin connectors
x
x 2 x 1 with latching fasteners
x 4 x 3
x 5 JT2 JT1
x 6
x 8 x 7
x 10 x 9 PSVO I/O Pack
x 12 x 11
LVDT inputs x 13
x 14
Pulse rate inputs x 16 x 15
x 18 x 17
LVDT excitation x 19 WSVO Servo Driver
x 20
Servo coil outputs x 22 x 21
x 23 JS2 JS1
x 24
x TB1
x
TB2
x 26 x 25
x 28 x 27
x 30 x 29
x 32 x 31
x 33 JR2 JR1
x 34
x 36 x 35
x 38 x 37
x 40 x 39
x 42 x 41
x 44 x 43
x 46 x 45
x 48 x 47
x
TB4/3 J28 x
Shield bar 28 V dc supply
Barrier type terminal Excitation outputs

blocks can be unplugged (S&T) non-isolated
TSVC Servo Terminal Board
TSVCH1 T1 through T4 isolation transformers provide galvanic isolation between the

WSVO's excitation output driver and the primary-side of the LVDT/R position sensor.
TSVCH2 excludes the isolation transformers T1 through T4 resulting in no galvanic

isolation between the WSVO excitation driver output and the LVDT/R position sensor.

Installation
Sensors and servo valves are wired directly to two I/O terminal blocks. Each block is
held down with two screws and has 24 terminals accepting up to #12 AWG wiring. A
shield terminal strip attached to chassis ground is located immediately to the left of
each terminal block. External trip wiring is plugged into either JD1 or JD2.
Each servo output can have three coils in TMR configuration. The size of each coil
current is jumper selected using JP1, 3, 5 for Servo 1, and JP2, 4, 6 for servo 2.
JD1 JD2
External Trip from Servo/LVDT Terminal Board TSVCH1A
1 1
PCOM GND 2 2
x
LVDT 1 (H) JT2 JT1
x 1
LVDT 1 (L) x 2
x 3 LVDT 2 (H)
LVDT 2 (L) x 4
LVDT 3 (L) x 6
x 5 LVDT 3 (H)
LVDT 4 (L) x 8
x 7 LVDT 4 (H)
9 JP6 Servo Coil 02 T
LVDT 5 (L) x 10
x LVDT 5 (H)
LVDT 6 (L) x 12
x 11 LVDT 6 (H)
LVDT 7 (L) x 14
x 13 LVDT 7 (H) JP5 Servo Coil 01 T
x 15 LVDT 8 (H)
LVDT 8 (L) x 16
x 17 Excit R1 (H)
Excit R1 (L) x 18 JP4 Servo Coil 02 S
x 19 Excit R2 (H)
Excit R2 (L) x 20
Excit S1 (L) x 22
x 21 Excit S1 (H)
x 23 Excit T1 (H) JP3 Servo Coil 01 S JS2 JS1
Excit T1 (L) x 24
x
Up to two #12 AWG wires per

point with 300 V insulation
x
x 25Servo 1 R (H) JP2 Servo Coil 02 R
Servo 1 R (L) x 26
x 27Servo 1 S (H)
Servo 1 S (L) x 28
x 29Servo 1 T (H) JP1 Servo Coil 01 R
Servo 1 T (L) x 30
x 31Servo 1 SMX R (H)
Servo 2 SMXR(H) x 32
Servo 2 R (L) x 34
x 33Servo 2 R (H) Jumper Choices:
x 35Servo 2 S (H) 120B +/-120 mA (75 ohm coil)
Servo 2 S (L) x 36 JR2 JR1
Servo 2 T (L) x 38
x 37Servo 2 T (H) 120A +/-120 mA (40 ohm coil)
x 39Pulse 1 TTL (H) 80 +/- 80 mA
Pulse 2 TTL (H) x 40
Pulse 1 PCOM
x 41Pulse 1 24V (H) 40 +/- 40 mA
x 42
x 43Pulse 1 Mag (H) 20 +/- 20 mA
Pulse 1 (L) x 44
x 45Pulse 2 24V (H) 10 +/- 10 mA
Pulse 2 PCOM x 46
x 47Pulse 2 Mag (H) 1 P28R
Pulse 2 (L) x 48
x 2 P28S Power
TB4 TB3 3 P28T Supplies
Terminal blocks can
4 PCOM 28 V dc
be unplugged
J28 5 PCOM
1 2 1 2
ETH2
LVDT Excitation ETL2
(S&T) non-
isolated DC-48-pin DC-62 pin
ESH2 connector for connector for
ESL2 WSVO R PSVO R
Servo/LVDT Terminal Board Wiring

Three 28 V dc power supplies for the R, S, and T board functions are
connected to J28. Two non-isolated LVDT excitations sources for S and T
are wired to terminal block TB3 and TB4.
PSVO
The three J1 connectors for the PSVO I/O packs are <R>, <S>, and <T>.
These plug into the DC-37 pin connector with latching fasteners, and bolt
to a side bracket holding the packs in place.
WSVO
The three J2 connectors for the WSVO servo drivers are R, S, and T. Each WSVO is
held down with four screws. The WSVO servo driver and PSVO I/O pack are ordered
as a set and should be replaced if diagnostics indicate a servo problem.
The PSVO pack and WSVO driver can be replaced with the unit running by
removing power from the failed channel with the corresponding manual enable
switch, SW1, or SW2, or SW3. Power to each channel is indicated with LEDs
on the board and LEDs on each solid-state power switch.
Operation
The TSVC servo terminal board provides two channels consisting of bi-directional servo
current outputs, LVDT position feedback, LVDT excitation, and pulse rate flows inputs.
It provides excitation for, and accepts inputs from, up to eight LVDT valve position
inputs. There is a choice of one, two, three, or four LVDTs for each servo control loop.
The two pulse rate inputs are used for gas turbine fuel flow measurement.
Each servo output is equipped with an individual suicide relay under firmware control
that shorts the PSVO output signal to signal common when de-energized, and recovers
to nominal limits after a manual reset command is issued. Diagnostics monitor the
output status of each servo voltage, current, and suicide relay.
Each of the servo output channels can drive either one or two-coil servos in simplex
applications, or two or three-coil servos in TMR applications. The two-coil TMR
applications are for 200# oil gear systems where each of two control pack drive one coil
each, and the third control pack has no servo coil interface. Servo cable lengths up to 300 m
(984 ft) are supported with a maximum two-way cable resistance of 15 Ω. Since there are
many types of servo coils, a variety of bi-directional current sources are jumper selectable.
Note The primary and emergency overspeed systems will trip the hydraulic solenoids
independent of this circuit
A trip override relay K1 is provided on the terminal board, which is driven from
the protection pack. If an emergency overspeed condition is detected in the
protection module, the K1 relay will energize and disconnect the servo output
and apply a bias to drive the control valve closed. This is only used on simplex
applications to protect against the servo amplifier failing high, and is functional
only with respect to the servo coils driven from <R>.

Controller
Servo Terminal Board Servo Pack <R>

TSVCH1A Digital Servo Driver <R>
PSVO servo
( Input Portion) WSVO
LVDT (or LVDR) JR1 regulator
1 8 Ckts . A/D converter
LVDT1H
3.2k Hz, Regulator
A/D
7 V rms
excitation LVDT1L 2 P28VR
source SCOM
JS1
J28 D/A
28 V dc for <R> D/A
1 Servo driver To servo
28 V dc return 4 converter Voltage
P28VS
28 V dc for <S> 2
Limit outputs
28 V dc return 5 JT1 P28V
3 on TSVC
28 V dc for <T>
Enable switch,
fuse, and light
P28VT
Configurable
P24V1 41 CL Gain
P28V
PCOM 42 JR1 3.2KHz To TSVC
continued excitation
Pulse rate P1TTL 39
Pulse
inputs
Rate
active probes 43
(
P1H
2 - 20 kHz PR
TTL P1L 44
JS1
continued
45 CL
P24V2 PSVO Servo Pack <S> WSVO Driver <S>
46
PCOM
40 JT1
P2TTL continued
Pulse rate 47
(
PR P2H PSVO Servo Pack <T> WSVO Driver <T>

inputs,
magnetic P2L 48
MPU
pickups
Noise
2 - 20 kHz suppression
TSVC continued
LVDT and Pulse Rate Inputs (Part 1 of 2)
Note Only two pulse rate probes on one TSVC are used.
In TMR applications, the LVDT signals fan out to three packs through JR1, JS1, and
JT1. Three connectors also bring power into TSVC where the three voltages are diode
high-selected and current limited to supply 24 V dc to the pulse rate active probes.
For TMR systems, each servo channel has connections to three output coils with
a range of current ratings up to 120 mA, selected by jumper.

Controller
Servo Terminal Board TSVCH1A (continued)
Servo Pack R Digital Servo Driver R

PSVO servo WSVO
JD1 Trip input from
regulator P28V
A/D converter 1
P not used for
2
A/D Regulator TMR
JD2
1
Suicide relay P28V 2
D/A JP1
120B
D/A Servo driver 120
JR1 Servo coil from R
converter Voltage
80 25 S1RH
40
P28V Limit 20
10 31
N
22 ohms
2 Ckts . S
89 ohms
Configurable
26 S1RL 1k ohm
Gain
3.2KHz 17 ER1H 3.2KHz,

excitation N 7V rms
Pulse 2 Ckts S 18 excitation
ER1L
Rate source
JS1 JP2 For LVDTs
120B
120 Servo coil from S
80 27
40 S1SH
20
10 N
S
2 Ckts. 28 S1SL
PSVO Servo Pack S 21 ES1H 3.2KHz,

WSVO Driver S
1 Ckt. N 7V rms
S 22 ES1L excitation
JT1 source
JP3
120B
120
80
Servo coil from T
29 S1TH
40
20
10
N
S
2 Ckts. 30 S1TL
PSVO Servo Pack T WSVO Driver T 23 ET1H 3.2KHz,

N 7V rms
1 Ckt. S 24 ET1L excitation
source
Noise suppression For LVDTs
TSVC Servo Coil Outputs and LVDT Excitation (Part 2 of 2)

Jumper Label Nominal Coil Internal Application
Coil Type Current Resistance Resistance
(Ohms) (Ohms)
101 ±10 mA 1000 180 Simplex and TMR
202 ±20 mA 125 442 Simplex
403 ±40 mA 62 195 Simplex
404 ±40 mA 89 195 TMR
805 ±80 mA 22 115 TMR
120A6 ±120 mA (A) 40 46 Simplex
120B7 ±120 mA (B) 75 10 TMR
The table above defines the standard servo coil resistance and their associated
internal resistance, selected with the terminal board jumpers shown in the figure.
In addition to these standard servo coils, it is possible to drive non-standard
coils by using a non-standard jumper setting. For example, an 80 mA, 125 Ω
coil could be driven by using a jumper setting 120B.
Note The excitation source is isolated from signal common (floating) and is capable of
operation at common mode voltages up to 35 V dc, or 35 V rms, 50/60 Hz.
Control valve position is sensed with either a four-wire LVDT or a three-wire

linear variable differential reluctance (LVDR). Redundancy implementations for
the feedback devices are determined by the application software to allow the
maximum flexibility. LVDT/Rs can be mounted up to 300 m (984 ft) from the
turbine control with a maximum two-way cable resistance of 15 Ω.
Two LVDT/R transformer isolated excitation sources are located on the terminal board
for simplex applications and another two transformer isolated excitation sources for
TMR applications. A fifth and sixth non-isolated excitation source are provided
for the customer’s use. Excitation voltage is 7 V rms and the frequency is 3.2 kHz
with a total harmonic distortion of less than 1% when loaded.
A typical LVDT/R has an output of 0.7 V rms at the zero stroke position of the
valve stem, and an output of 3.5 V rms at the designed maximum stoke position
(some applications have these reversed). The LVDT/R input is converted to dc and
conditioned with a low pass filter. Diagnostics perform a high/low (hardware) limit
check on the input signal and a high/low system (software) limit check.
Inputs support both passive magnetic pickups and active pulse rate transducers (TTL type)
interchangeable without configuration. Normally, these inputs are not used on steam
turbine applications, but are usually for liquid fuel flow measurement, and monitoring
flow divider feedback in gas turbine applications. Pulse rate inputs can be located up to
300 m (984 ft) from the turbine control cabinet. This assumes shielded-pair cable is used
with typically 70 nF single ended or 35 nF differential capacitance and 15 Ω resistance.
A frequency range of 2 to 30 kHz can be monitored at a normal sampling rate of

either 10 or 20 ms. Magnetic pickups typically have an output resistance of 200 Ω
and an inductance of 85 MHz excluding cable characteristics. The transducer is a
high-impedance source, generating energy levels insufficient to cause a spark.

Specifications
Item Specification
Number of inputs Eight LVDT windings
Two pulse rate signals, magnetic or TTL
External trip signal to shut off servo outputs
Number of outputs Two servo valves, three coils each, ±(10, 20, 40, 80, 120) mA
Four excitation sources for LVDTs (transformer isolation)
Two excitation sources for LVDTs (no transformer isolation)
Two 24 V dc excitation sources for pulse rate transducers
Power supply voltage Nominal 24 V dc from three supplies P28R, P28S, P28T
Power supply current 5 A dc (Poly-Fuse or current limit rating for each input is 1 A dc)
Pulse rate input Minimum signal for proper measurement at 2 Hz is 33 mVpk, and at 12 kHz is 827 mVpk
Magnetic PR pickup signal Generates 150 V p-p into 60 Ω
Active PR pickup signal Generates 5 to 27 V p-p into 60 Ω
Failed ID chip
Physical

Diagnostics
PSVO makes diagnostic checks on the terminal board components as follows:
• The output servo current is out of limits or not responding, creating a fault.
• The regulator feedback (LVDT) signal is out of limits, creating a fault. If
the associated regulator has two sensors, the bad sensor is removed from
the feedback calculation and the good sensor is used.
• If any one of the above signals go unhealthy a composite diagnostic alarm,
L#DIAG_PSVO occurs. Details of the individual diagnostics are available from
the ToolboxST* application. The diagnostic signals can be individually latched,
and reset with the RESET_DIA signal if they go healthy.
interrogated by the I/O processor. The ID device is a read-only chip coded
with the terminal board serial number, board type, revision number, and the J
Configuration
In a simplex system, servo 1 is configured for the correct coil current with jumper JP1, and
servo 2 is configured with jumper JP4. In a TMR system, each servo output can have three
coils. In this case, each coil current is jumper selected using JP 1-3 for servo 1, and JP 4-6
for servo 2. All other servo board configuration is done from the ToolboxST application.
Power must be applied to the three channels, so check that all three switches SW1,
SW2, and SW3 are ON, and the power indicators for P28 R, S, and T are lit.

Notes

PSVP Servo Control - Steam
Servo Control - Steam (PSVO)

The PSVP servo pack, WSVO servo driver and the SSVP terminal board provide an
electro-hydraulic control for both new and retrofit steam turbine applications. The following
are salient features for this product:
• Six position sensor input channels
• Two servo outputs with a parallel feature allowing isolation of a failure in electronics
• Two excitation outputs with a hot-backup redundancy feature for single position sensor
valves
• A pulse rate input optimized for turbine speed feedback similar to the PTUR and PPRO
pulse rate inputs
The product firmware supports single, minimum-select or maximum-select dual, and mid-select
triple position sensor input position regulators. The single and maximum-select dual pilot
cylinder position regulators are available. The product does not support the flowrate regulators
for liquid-fuel control or any of the position regulators supporting the land and marine (LM)
gas turbines.
Input to the pack is through dual RJ-45 Ethernet connectors, and 28 V dc power is supplied
from the terminal board. The PSVP output is through a 62-pin connector that connects directly
GEH-6721L PSVP Servo Control - Steam System Guide 22-1

with the associated terminal board connector. Visual diagnostics are provided through indicator
light emitting diodes (LEDs).
P28OFF P28ON
P28N P28ON PSVP ONLY
P28IN
JUA
JUB
2 1
SW1
low high
TB1 JA 2 is the 48-
pin connector
WSVO for WSVO
LVDT 1 (H) Servo
LVDT 1 (L)
LVDT 2 (H)
LVDT 2 (L) PWR
LVDT 3 (H) ATTN
LVDT 3 (L)
LVDT 4 (H) T1
LVDT 4 (L) EX1 LINK
LVDT 5 (H) EX2 TxRx
LVDT 5 (L)
LVDT 6 (H)
JA2
LVDT 6 (L) SV1 LINK
Excitation 1 (H) SV2 TxRx
Excitation 1 (L)
Excitation 2 (H)
Excitation 2 (L) T2
Servo 1 (H)
Servo 1 (L)
Servo 2 (H)
Servo 2 (L) Sservo 2 (H)
Sservo 2 (L) IS220PSVP
Pulse Rate (H)
Pulse Rate (L) JA 1 is the 62-
pin connector
JP1 JP2 for PSVP
+/- 120 B mA
+/- 120 A mA
+/- 80 mA
Up to two # 12 AWG
+/- 40 mA
JLB
JLA
wires per point with +/- 20 mA
300 V insulation +/- 10 mA
Compatibility
The PSVP is designed in PSVPH1A is compatible with the DIN-rail mounted servo terminal board SSVP,
particular for retrofit steam but not the TSVO or TSVC servo terminal boards.
turbine applications.
Terminal Board Control Mode
SSVPHxx Simplex, Dual, TMR
TSVOHxx Not compatible
TSVCHxx Not compatible
Control mode refers to the number of I/O packs used in a signal path.
• Simplex uses one PSVP, WSVO, and SSVP set with one or two
network connections on each I/O pack.
• Dual uses two PSVP, WSVO, and SSVP sets with one network
connection on each I/O pack.
• TMR uses three PSVP, WSVO, and SSVP sets with one network
connection on each I/O pack.

Installation
¾ To install the PSVP
1. Securely mount the terminal board.
Note The PSVP along with its associated WSVO servo driver assembly mounts
directly to SSVP terminal board.
2. Directly plug one PSVP I/O pack into the terminal board connector.
3. Mechanically secure the pack using the threaded inserts adjacent to the Ethernet
type. The bracket location should be adjusted such that there is no right angle
force applied to the 62-pin connector between the pack and the terminal board.
The adjustment should only be required once in the life of the product.
4. Plug the WSVO servo driver assembly into the J2 48-pin connector
and secure it with the four screws.
ENET1 to the network associated with the R controller; however, the PSVP is not
sensitive to Ethernet connections and negotiates proper operation over either port.
6. Plug the 28 V power into the SSVP P28IN 2-pin connector. Be sure the high
is connected to pin 1 and the low is connected to pin 2.
7. If PSVP redundancy is simplex, insert the plug for suicide protection
from the protection module.
8. If PSVP redundancy is dual, plug the RJ-45 connector from SSVP_R JLA to
SSVP_S JUA, and from SSVP_R JLB to SSVP_S JUB.
9. Apply power to the PSVP subassembly using the SW1 power switch on
the SSVP. Check the indicator lights on the PSVP.
10. Use the ToolboxST* application to configure the I/O pack as necessary. Refer
to the Auto-Reconfiguration section for more information.

Attention entire system, and then restart the ToolboxST Download
Wizard.

Operation
Processor



Recalibration

Status LEDs
PSVP LEDs

Green SV1 Servo #1 is able to output current and not suicided.
Green SV2 Servo #2 is able to output current and not suicided.
Green EX1 Excitation Output #1 is active and connected to position sensor.
Green EX2 Excitation Output #2 is active and connected to position sensor.
Processor LEDs

Green LINK Provided for each Ethernet port to indicate if a valid Ethernet connection is present.
Yellow TxRx Provided for each Ethernet port to indicate when the pack is transmitting or receiving
data over the port.
LED Status
LED Flashing Pattern Description

Red ATTN LED out There are no detectable problems with the I/O pack or module.
Solid Booting - prior to reading Dallas ID

0.5 Hz 50% Application not loaded (I/O pack or module)
Green ATTN Solid BIOS (at power on) - if it remains in this state, the I/O pack or module is dead.
1 Hz 50% I/O pack or module in WAIT or STANDBY
Two 4 Hz flashes every Application online
4 sec

PSVP Circuitry
The PSVP has a BSVP application board that provides six rms to V dc converters
for position feedback. The rms to V dc converters accept a maximum of 7.07
V rms sine wave input. They change the ac input signal into a 10 V dc input,
read by the 16-bit analog-to-digital converter. The digitized position information
is used in the valve position control loop in the PSVP firmware. The output of
the position regulator is written to an analog-to-digital converter located on the
BSVP. This analog output feeds the WSVO current regulator.
The PSVP also controls the servo suicide relay on the WSVO and the isolation
relay on the SSVP. It inputs the servo driver output voltage and the servo current.
Coil ohms are calculated in firmware by using the servo current feedback and
the voltage monitored at the SSVP servo terminal points.
The excitation source for the LVDT/R position sensor is generated using the
processor board’s field programmable gate array (FPGA) to control a digital-to-analog
converter. The converter’s 3.2 kHz sine wave is outputted to the SSVP terminal
board where the excitation driver is located. The excitation redundancy control
is performed by a micro-controller located on the BSVP.
The PSN has a faster response The decision to switch from one excitation source to the hot backup is determined by the
time than what can be excitation current feedback and excitation voltage feedback from the SSVP terminal
achieved through IONet / board. If the excitation current and/or voltage is outside its prescribed operating window,
PSVP firmware. the micro-controller will send a command to de-energize the KE1 or KE2 switchover
relay on one SSVP and energize the KE1 or KE2 switchover relay on the SSVP that
has the redundant excitation source. The state information for this switchover control
is passed to the other PSVP through a Private Serial Network (PSN). The PSN is a
RS-422 based serial network that works in concert with a FPGA / micro-controller
excitation switchover function. The following figure shows the PSVP circuitry.

P28 K3 1
22-8
2
WSVO JD1
Current Regulator 1 PCOM 1
SUIMON 2
SUICDRVH JD2
RMS-to-VDC Converter K2
1 LV1H ACO SSV1H 21
Open P28
Rectifie Servo #1 I Ref M
Wire ckt. LP
2 LV1L r Filter SERVOxH 120A
120B ma JP1
& load DACIREF
DAC ma80ma SV1H 17
40ma
3 RMS-to-VDC Converter VMFBK 20ma
LV2H Open SV1DACIREF 10ma 10
Rectifie SV1L 18
LP IMFBK
Wire ckt.
4 LV2L r Filter ACOM
& load
KS1
5 LV3H RMS-to-VDC Converter Current Regulator 2
Open SUIMON
Rectifie LP
Wire ckt. SUICDRVH
6 LV3L r Filter K2
& load A/D ACO SSV2H 22
P28
Servo #2 I Ref M
7 LV4H RMS-to-VDC Converter Block 120A
Open DACIREF SERVOxH 120B ma JP2
Rectifie LP DAC ma80ma SV2H 19
Wire ckt. 40ma
8 LV4L r Filter 20ma
& load SV2DACIREF VMFBK 10ma 10
IMFBK SV2L 20
9 LV5H RMS-to-VDC Converter
Open ACOM
Rectifie LP
Wire ckt.
10 LV5L r Filter KS2
& load
EX1OUTEN KE1
11 LV6H RMS-to-VDC Converter RMS-to-VDC Converter
Open EX1VFBK
Rectifie LP LP Rectifie EX1VMH
Wire ckt. LVDT Excitation Sine Cntrl
12 LV6L r Filter Filter r EX1VML 1:1
& load Cur_Mon EX1H 13
Excitatio
23 PR1H DAC n
LP Filter EX1IM EX1VMH
Clamp PTUR-type Pulse Rate RMS-to-VDC Converter EX1L 14
24 & Filter Ckt.
Driver
PR1L LP Rectifie EX2VMH
Filter r LVDT Excitation Sine Cntrl EX1VML
EX2VML 1:1 EX2H 15
Excitatio Cur_Mon
DAC n
LP Filter EX2IM EX2VMH
Conn Driver EX2L 16
BSVP FPGA EX2VML
EX2VFBK
RAM uP
EX2OUTEN KE2
FLASH
OUT_A RS422
RJ45
Ethernet
2
IN_LA JLA
45
RJ-
Enet
#2 PSVP
OUT_B RS422
RJ45
Sfwr
1
Manual On/Off Ethernet IN_LB JLB
Enet
45
RJ-
Switch #1
OUT_A RS422
RJ45
Circuit PTC
IN_UA JUA
Breaker 1A
P1
P28IN P28 ON
DC-DC Converter
OUT_B RS422
RJ45
BPPB IN_UB JUB

Window
Detector
PSVP
SSVP
Mark* VIe Control Vol. II System Hardware Guide

Pulse Rate Input
The PSVP pulse rate input The PSVP module has one pulse rate input designed for turbine speed, but not for flow
is similar to the PTUR and rate feedback used for liquid-fuel control. The pulse rate input circuit in the PSVP
PPRO pulse rate inputs. enhances the turbine speed signal. The 28 V dc input on the BPPB is not used to power
the PSVP I/O module. The 28 V dc source is connected to the P28IN connector on the
SSVP to power the PSVP, WSVO servo driver and the SSVP terminal board.
The PSVP signal-conditioning An interface is provided for one passive magnetic speed input. There is no provision
circuit is designed for the for active pulse rate sensors or TTL input. A frequency range of 2 to 20,000 Hz
primary speed input, the same is supported. The pulse rate input is not designed for flow divider sensors and
as the PTUR or PPRO. the corresponding liquid fuel regulators are not included.
Pulse rate inputs can be configured for a variety of applications. Speed type is the default
setting normally used with turbine control. Speed_high type provides an extended speed
range above the standard speed type. Speed_HSNG type is an improved pulse rate
detection method that eliminates discontinuities due to hardware and software gearing,
and eliminates alias speed values associated with non-uniform pulse rate. Speed_HSNG
should be used for all turbine applications unless otherwise specified.
Increasing the Lock_Limit The Speed_HSNG type will map the spacing of the teeth on the speed wheel to remove
value will allow the next periodic variation from speed measurements. HSNGn_Stat mapping locked status bits
generation speed algorithm to are in signal space so the mapping status of the algorithm can be observed. If the status
stay locked with increased indicator for a pulse rate input is false, then the mapping algorithm detects too much
variation. variation in the tooth-tooth measurements to lock onto the tooth geometry. The Lock_Limit
parameter can be adjusted in 1% increments. This allows greater tooth-to-tooth variation
per revolution, which can be caused by some of the following issues:
• A magnetized speed wheel

• Electro-magnetic interference from outside sources
• Improper wiring or shielding practices
The impact of opening the Lock_Limit is increased speed

variation. If the speed variation becomes excessive after
increasing the Lock_Limit, identify the source of the
problem (listed above) and correct the issue.
Caution
WSVO
The WSVO servo driver is used for both the PSVP and PSVO applications. The WSVO
has two servo current regulators to drive the servo outputs on the SSVP terminal board.
It provides the dc-to-dc converter (28 V dc to +15 / -15 V dc) to power the analog
circuitry. It also has two excitation voltage drivers that are not used by the PSVP. The
excitation drivers for the PSVP are located on the SSVP to optimize the excitation output
for load steps in the excitation switchover scheme used in this module.

Position Feedback
The PSVP / SSVP has six Linear Variable Differential Transformer (LVDT) or Linear
Variable Differential Reluctance (LVDR) sensor inputs, each of which includes:
• SSVP Open-wire detection circuit and load

• BSVP rms to V dc converter
Note Although there are six LVDT signal inputs, there are only two excitation outputs.
Each excitation output can only support two LVDTs, effectively limiting the number of
LVDTs that a PSVP can support to four for certain applications.
For dual and TMR PSVP The SSVP open-wire circuitry provides weak pull-up and pull-down resistors to
redundancy, the position sensor the appropriate power rails, adding approximately one mA of dc current into the
feedbacks must be fanned feedback windings of the LVDT or LVDR. If the circuit on the feedback side of the
external to the SSVP. position transducer opens, the PSVP detects the absence of this additional dc current.
It flags the controller that a position sensor connection has opened using the Out of
Range detection logic in the PSVP firmware. The SSVP provides a 20 kilo-ohm
resistive load for the feedback winding of the LVDT or LVDR.
The BSVP rms to V dc converter has a high impedance differential amplifier, providing
common mode voltage protection. The rectifier and low-pass filtering is designed to scale
the dc signal output where 10 V dc is equivalent to 7.07 V rms at the input. The rms to
V dc converter outputs are multiplexed into a single 16-bit analog-to-digital converter.
Each converter output is sampled every five milliseconds or at a 200 Hz rate.
Position Sensor Types

Most LVDTs used for sensing valve positions are three-wire with bias
winding as shown in the following figure.
LVDT
P/N 185A1328P020 Red
Yellow
Connector
+
V_a
-
Blue
Stroke (in.)
LVDT with Bias Winding
The LVDT with bias winding has a primary excitation winding defined by the red
and blue wire connections. The red wire connects to SSVP EXnH, and the blue wire
connects to EXnL where n = 1-2. The two secondary windings are connected in series,
providing a position output between the yellow and blue wires. The yellow wire is
connected to SSVP LVxH where x = 1-6 and the blue wire is connected to SSVP LVxL.
A bias winding has also been added to aid in the detection of sensor failures.

A sliding magnetic core or armature is located within the LVDT, coupling the primary
and secondary windings. The secondary windings are connected in series, aiding each
other electrically. The output voltage is above zero when the core is positioned equally
between the two secondary windings. Moving the core from the center position will
create a voltage proportional to the distance from the null position.
The steam turbine product line The LVDR is a linear variable differential reluctance transducer, having a single
normally uses LVDRs. coil and a center tapped with a movable magnetic core or armature. Normally, the
excitation source is applied across the entire winding through the black and red
wires. The valve position feedback is extracted from the center-tapped point on the
coil (white wire) and the low side (red wire) of the excitation.
LVDR Black
Ex.: GE P/N 119C9639-1
Connec tor
White
Red
Stroke (in.)
LVDR Position Sensor
Recommended Wiring Practices

The excitation black wire is connected to the SSVP EXnH screw. The excitation red wire is
connected to the SSVP EXnL screw where n = 1 –2. The position sensing high-side white
wire is connected to SSVP LVxH. the red wire is connected to SSVP LVxL where x = 1-6.

22-12
Position Terminal Terminal
Sensor Strip 2 Strip 1 shield
Red 1 13
LVDR 1
M
14 O 7 V_rms
2 N
White 2 3 1
+ EMC Rectifier
Diff A/D
&
Gain
20 k
V ac Voltage Amp Sub - uP

- Clamps & Filter System
Black 3 2
4 additional LVDT
chs
shield PSVP
Stroke (in.)
SSVP
Shielded Bar
Less than 60 ft 3 wire Less than 1000 ft shielded

shielded cable twisted pair cable

Servo Outputs
The PSVP module has two servo channels. The servo loop is comprised of the following:
• Firmware position regulator

• Dither control and digital-to-analog converter
• Current regulator
• Current limiting resistors
• Simplex protection
• Parallel option with failure isolation
The PSVP processor executes the firmware position regulator for Servo 1 and
Servo 2 every five milliseconds or at a 200 Hz rate. The position reference
command is a system output from the controller and the position feedback is the
digitized and scaled value from the BSVP / SSVP circuitry.
The dither control adds a square wave signal to the output from the position regulator.
The user defines the magnitude and frequency of the dither. Dither frequency options
are 100, 50, 25, 33, or 12.5 Hz. Dither can also be turned off and unused. The
dither magnitude can be adjusted as a percent of the rated current.
The dithered regulator output is written to a digital-to-analog converter. The converter

output is the analog current command for the WSVO analog current regulator. The
fixed-gain proportional-plus-integral current regulator provides a voltage-controlled
current source output with discrete nominal current ratings of 10, 20, 40, 80, and 120 mA.
When the configuration for the PSVP is properly set, a suicide relay on the WSVO limits the
current regulator output if the coil ohms calculation function detects any of the following:
• A coil open or coil short condition

• A current regulator control loss
• An open or out-of-range position feedback
The SSVP current limiting resistors reduce the power dissipation of the current
driver to prevent a shorted output. Berg Jumpers on the SSVP are provided to select
the proper nominal current rating for the coil driver application.
Refer to the figure in the PSVP For simplex controller application of the PSVP module, an externally controlled relay is
Circuitry section. provided on the SSVP (controlled by the PPRO) to disable the WSVO servo driver and
select a positive biased current to drive the valve closed. The PSVO / WSVO / TSVC
and the PSVP / WSVO / SSVP servo outputs can be paralleled, but only the PSVP
module can isolate a failure of the WSVO. The isolation circuitry is controlled by
the PSVP through the KS1 and KS2 relays on the SSVP terminal board.

Verification
The three ways to verify servo performance through stroking the actuator are manual,
position ramping, and step current. In manual mode, the desired value is entered
numerically and the performance is monitored from the trend recorder.
Refer to GEH-6700, ¾ To verify servo performance

ToolboxST* user guide for Mark
1. Select Verify Position to apply a ramp to the actuator.
VIe Control, chapter 9 Trender.
2. Select Verify Current to apply a step input to the actuator. The trend recorder
displays any abnormalities in the actuator stroke.
ID Line
Power Management
Connectors

Specifications
The following table provides information specific to the PSVP pack and WSVO driver.
Item Specification
Number of inputs Six LVDT / R windings*
Single pulse rate input
Number of outputs Two servo valve currents
Two excitation sources with redundant control capability for LVDT / Rs.
Power supply voltage Nominal 28 V dc
LVDT accuracy 1% with 16-bit resolution
LVDT input filter Low pass filter with 3 down breaks at 50 rad/sec ±15%
LVDT common mode range CMR is 15 V dc, 10 V rms
at 50/60 Hz

Pulse rate accuracy 0.05% of reading with 16-bit resolution at 50 Hz frame rate
Noise of acceleration measurement is less than ±50 Hz/sec for a 10,000 Hz signal being
read at 10 ms
Pulse rate input Minimum signal for proper measurement at 2 Hz is 36 mV p-p.
Magnetic PR pickup signal Generates 150 V p-p into 60 kΩ
Servo valve output accuracy 2% with 12-bit resolution
Dither amplitude and frequency adjustable
Servo suicide
Calibration voltage range fault
The LVDT excitation is out of range
The input signal varies from the voted value by more than the TMR differential limit
Failed ID chip
Physical
* Although there are six LVDT signal inputs, there are only two excitation outputs. Each excitation output can only support
two LVDTs, effectively limiting the number of LVDTs that a PSVP can support to four for certain applications.

Diagnostics

exceeded, a logic signal is set and the input is no longer scanned. The
L3DIAG_xxxx logic signal refers to the entire board.
• The pulse rate input has system limit checking based on configurable high and
low levels. These limits can be used to generate alarms, to enable/disable, and
as latching/non-latching. RESET_SYS resets the out of limits.
resistor. The pack conditions this signal and compares it to the commanded
• Servo coil resistance is calculated based on servo terminal point voltage
and current. The calculated resistance is compared against configurable
limits to generate open and/or shorted coil alarms.
Details of the individual diagnostics are available from the ToolboxST application. The
diagnostic signals can be individually latched and then reset with the RESET_DIA
signal if they go healthy. Suicide alarms require a RESET_SUIC signal before
the servo relays will un-suicide. Excitation alarms require a RESET_DIAG to
rearm excitation switchover when excitation sharing is used.

Configuration
Valid Servo Configurations with TMR I/O

Servo #1 Configuration Option 1
* Coil_Parallel (cfg) Coils_not_parallel
RegType (cfg) 3LVposMID
* Coil_Parallel (cfg) Coils_not_parallel
RegType (cfg) 3LVposMID
* The parameter Coil_Parallel is not visible in ToolboxST for a TMR PSVP. It is forced by
the firmware to Coils_not_parallel.
Note LVDT or LVDR position sensors can be used. LV_position, 2LVposMIN or

2LVposMAX are supported but are not normally used.

Option One: TMR LVDR and Triple Coil Servo

Valid Servo Configurations with Dual LVDR and Dual Coil
Servo, Coils Not Paralleled
Servo #1 Option 2 Option 2 with fanned Option 3 Option 4
Configuration inputs
Coil_Parallel (cfg) Coils_not_parallel Coils_not_parallel Coils_not_parallel Coils_not_parallel
RegType (cfg) 1_Lvposition 2LVMax 1_Lvposition 1_Lvposition
Servo #2 Option 2 Option 2 Option 2 Option 2
Configuration
Coil_Parallel (cfg) Coils_not_parallel Coils_not_parallel Coils_not_parallel Coils_not_parallel
RegType (cfg) 1LVposition 1LVposition 1LVposition 1LVposition
Note If PSVP-S powers on before PSVP-R, the controller selects the PSVP-S
signal-space inputs as the voted data to be used. LVDT or LVDR position sensors can
be used. 2LVposMIN, 2LVposMAX or 3LVposMID are supported for two or three
sensors per servo but are not normally used.
Option Two: Dual LVDR and Dual Coil Servo

Valid Servo Configurations with Simplex LVDR and Dual Coil
Servo, Coils Not Paralleled
Servo #1 Configuration Option 3 Option 4
Coil_Parallel (cfg) Coils_not_parallel Coil_parallel
RegType (cfg) 1_Lvposition 1_Lvposition
Coil_Parallel (cfg) Coils_not_parallel Coils_not_parallel
RegType (cfg) 1LVposition 1LVposition
Option Three: Simplex LVDR and Dual Coil Servo with Coils not Paralleled

Valid Servo Configuration with Simplex LVDR and Dual Coil
Servo, Coils Paralleled
Coil_Parallel (cfg) Coil_parallel Coil_parallel
RegType (cfg) 1_Lvposition 1_LVposition
Coil_Parallel (cfg) Coil_parallel Coil_parallel
RegType (cfg) 1LVposition 1LVposition
Option Four: Simplex LVDR and Dual Coil Servo with Coils Paralleled

Controller Software Support for Dual PSVP I/O Configurations
In the dual I/O redundancy configuration, the controller(s) use the I/O pack health
to determine which I/O pack inputs to use. For example, assume the controller(s)
voted or selected PSVP(_R) for system inputs. Also assume that LVDT1 input on
PSVP(_R) is out of range, resulting in a unhealthy LVDT1 input, and LVDT1 from
PSVP(S) is healthy. Because PSVP(_R) is the voted I/O pack for system inputs, the
controller software is constrained due to the unhealthy LVDT1 input.
The dual I/O redundancy configuration can be enhanced by using the Pre-Vote block
on PSVP(_R) and PSVP(S) system inputs. The Pre-Vote block frees the controller
software to determine whether PSVP(_R) or PSVP(S) input should be used.
Recommended Controller Software Selection Logic for Pre-Vote Outputs
Voted Source <R> Healthy <S> Healthy Vote Mismatch Pre-Vote Output to
Use
<R> or <S> NO NO NO or YES Default to Safe Value
<R> or <S> NO YES NO or YES <S>
<R> or <S> YES NO NO or YES <R>
<R> YES YES NO <R>
<S> YES YES NO <S>
<R> or <S> YES YES YES * Application
Dependent
* The application determines whether to use either PSVP(_R) system input or PSVP(S) system input.
Voted Source PSVP(_R) or PSVP(S) system inputs are selected for

use by controller
<R> Healthy PSVP(_R) pack is healthy
<S> Healthy PSVP(S) pack is healthy
Vote Mismatch PSVP(_R) system input – PSVP(S) system input > TMR
Diff Limit
Pre-Vote Output to Use Result of controller software selection logic

Valid Servo Configuration with Simplex LVDR and Dual Coil
Servo, Coils Paralleled
Coil_Parallel (cfg) Coil_parallel *
RegType (cfg) 1_LVposition
Coil_Parallel (cfg) Coil_parallel *
RegType (cfg) 1LVposition
* This parameter is forced to Coils_Parallel internal to a Simplex PSVP for all regulator
types except Pilot/Cylinder.
Note LVDT or LVDR position sensors can be used. 2LVposMIN, 2LVposMAX or

3LVposMID are supported for two or three sensors per servo but are not normally used.
Option Five: Simplex LVDR and Dual Coil Servo with Coils Paralleled
Note Dual IONet is permissible for frame rates of 25 and 50 Hz. The 100 Hz frame
rate is not permissible due to firmware execution limitations.

Simplex PSVP: Pilot / Cylinder Configuration
The Pilot / Cylinder regulator types are used on low-pressure hydraulic systems
with an inner pilot position loop. For pilot / cylinder regulator types, both servo
outputs must be assigned to the same regulator. Each servo output is configured
for ±120 mA current, yielding a total current of ±240 mA.
The 2_LVpilotCyl regulator type configuration uses one position sensor for the
outer cylinder valve and one position sensor for the inner pilot cylinder loop.
Independent excitation outputs are provided on the SSVP to supply 7.07 V
rms at 3.2 kHz to the LVDT or LVDR sensor input.
The 4_LVp/cylMAX selects the maximum from two position inputs from both the outer
cylinder position loop and the inner pilot position loop. The PSVP / WSVO / SSVP
provides two excitation outputs. Each excitation output is designed to support two
LVDT/R position sensors assuming the total current does not exceed 60 mA.
Servo with Paralleled Coils
Dual IONet is permissible for For a servo with parallel coils, Servo drive #1 and Servo drive #2 are paralleled. Set
frame rates of 25 and 50 Hz. the Servo Tab configuration parameter, Coil_Parallel to Coils_Parallel for both servos.
The 100 Hz frame rate is not With this new configuration, the PSVP module allows the suicide to remain enabled for
permissible due to firmware protection. The servos have an isolation contact provided for each servo circuit located on
execution limitations. the SSVP. If Servo drive #1 hardware fails, the WSVO suicides Servo drive #1 output.
Simultaneously, the SSVP opens the isolation contact controlled by the KS1 relay. The
relay isolates Servo drive #1 from Servo drive #2, allowing Servo drive #2 to continue to
run. This results in half the rated current of ±120 mA being supplied to the servo valve.

Not used
SSVP ( R) UA UB Servo
Pilot Valve #1
LVDR EX1 H P 28
SV1 H
Coil (s)
Exc
#1
W
Ar m ature
H EX1 L SV1 L
P 28
S SV2 H
L EX2 H V
Pilot Valve #2 O SV2L
LVDR Exc EX2L
#1
K1
Ar m ature
KS1
H JD1
P 28
LV1 H
L KS2
JD2
LV1L
Cylinder Valve #1
LVDR LV2 H
Exc
#1 LV2L I/O Net
Enet 1
P
Ar m ature
H
LV3 H ( R)
Enet 2
LV3L S I/O Net
L LV4 H V ( S)
Cylinder Valve #2 LV4L P
LVDR Exc LV5 H
#1
LV5L
28 V 28 V( R)
Ar m ature
H LV6 H
LV6L
L LA LB
Not used
Simplex PSVP: Dual Pilot / Dual Cylinder Valves with Dual Coil Servo (coils paralleled)

Not used
SSVP (R) UA UB Servo

Pilot Valve #1
LVDR EX1H P28
SV1H Coil (s)
Exc
#1
W
Armature
H EX1L SV1L
P28
S SV2H
L EX2H V
Cylinder Valve #1 O SV2L
LVDR Exc EX2L
#1
K1
Armature
KS1
H JD1
P28
LV1H
L KS2
JD2
LV1L
LV2H
LV2L I/O Net
Enet 1
LV3H P (R)
Enet 2
LV3L S I/O Net
LV4H V (S)
LV4L P
LV5H
LV5L
LV6H
28 V 28 V(R)
LV6L
LA LB
Not used
Simplex PSVP: Single Pilot / Single Cylinder Valves with Dual Coil Servo (coils paralleled)

Servo with Non-paralleled Coils
Dual IONet is permissible for If the pilot cylinder servo coils have separate coil connections, set the PSVP Servo Tab
frame rates of 25 and 50 Hz. configuration parameter, Coil_Parallel to Coils_not_parallel. For this case, the isolation
The 100 Hz frame rate is not contacts are always closed and the suicide contacts work like all other servo products.
permissible due to firmware
execution limitations.
Not used
SSVP(R) UA UB Servo
Pilot Valve #1
LVDR EX1H P28
SV1H Coil(s)
Exc
#1
W
Armature
H EX1L SV1L
P28
S SV2H
L EX2H V
LVDR Exc EX2L
#1
K1
Armature
KS1
H JD1
P28
LV1H
L KS2
JD2
LV1L
Cylinder Valve #1
LVDR LV2H
Exc
#1 LV2L I/O Net
Enet1
P (R)
Armature
LV3H
H
Enet2
LV3L S I/O Net
L LV4H V (S)
Cylinder Valve #2 LV4L P
LVDR Exc LV5H
#1
LV5L
28 V 28 V(R)
Armature
H LV6H
LV6L
L LA LB
Not used
Simplex PSVP: Dual Pilot / Dual Cylinder Valves with Dual Coil Servo (not paralleled)

Not used
SSVP ( R) UA UB Servo
Pilot Valve #1
LVDR EX1 H P 28
SV1 H
Coil (s)
Exc
#1
W
Ar mature
H EX1 L SV1 L
P 28
S SV2 H
L EX2 H V
LVDR Exc EX2L
#1
K1
Ar m ature
KS1
H JD1
P 28
LV1 H
L KS2
JD2
LV1L
LV2 H
LV2L I /O Net
Enet 1
LV3 H P ( R)
Enet 2
LV3L S I /O Net
LV4 H V ( S)
LV4L P
LV5 H
LV5L
28 V 28 V ( R)
LV6 H
LV6L
LA LB
Not used
Simplex PSVP: Single Pilot / Single Cylinder Valves with Dual Coil Servo (not paralleled)
Dual PSVP: Pilot / Cylinder Configuration

The Dual PSVP redundancy configuration provides paralleled servo outputs per
PSVP, and each PSVP drives a single servo coil. The dual PSVP configuration
provides redundancy for both of the following:
• A servo driver failure on the PSVP, maintaining 100% forcing for the servo coil
• A servo coil failure with reduced forcing dependent on the overdrive
capability of the servo coil
The 2_LVpilotCyl regulator type configuration uses one position sensor for the
outer cylinder valve and one position sensor for the inner pilot cylinder loop.
Independent excitation outputs are provided on the SSVP to supply 7.07 V
rms at 3.2 KHz to the LVDT or LVDR sensor input.
The 4_LVp/cylMAX selects the maximum from two position inputs from both the outer
cylinder position loop and the inner pilot position loop. The PSVP / WSVO / SSVP
provides two excitation outputs. Each excitation output is designed to support two
LVDT/R position sensors assuming the total current does not exceed 60 mA.

Not used
SSVP(R) UA UB Servo
Pilot Valve #1
LVDR EX1H P 28
SV1 H
Coil (s)
Exc
#1
W
Ar mat ur e
H EX1L SV1L
P28
S SV2 H
L EX 2 H V
LVDR
Exc EX2L
#1
K1
Ar m ature
KS1
H JD 1
P28
LV 1H
KS2
L JD 2
LV 1L
Cylinder Valve # 1
LVDR LV 2H
Exc
#1 LV 2L I/O Net
Enet 1
P (R)
A rm atur e
LV 3H
H
Enet 2
LV 3L S
L LV 4H V
Cylinder Valve #2 LV 4L P
LVDR Exc LV 5H
#1
LV 5L
28V 28 V (R)
Ar m at ur e
H LV 6H
LV 6L
L LA LB
SSVP(S ) UA UB
P 28
EX1H SV1 H
EX1L W SV1L
P28
S SV2 H
EX 2 H V
O SV2L
EX2L
K1
KS1
JD 1
P28
LV 1H
KS2
JD 2
LV 1L
LV 2H
LV 2L
Enet 1
I/O Net
LV 3H P (S)
Enet 2
LV 3L S
LV 4H V
LV 4L P
LV 5H
LV 5L
LV 6H
28 V 28 V (S)
LV 6L
LA LB
Not used
Dual PSVP: Dual Pilot / Dual Cylinder Valves with Dual Coil Servo

Servo with Non-paralleled Coils
The paralleled servo coils The pilot / cylinder servo with individual coil connections and servo outputs paralleled
configuration is not supported. is supported. In this configuration, the PSVP Servo Tab configuration parameter,
Coil_Parallel entry is not used. The PSVP firmware overrides this selection,
forcing the PSVP servo outputs to be paralleled per PSVP.

Not used
SSVP(R) UA UB Servo
Pilot Valve #1
LVDR EX1H P28
SV1H Coil (s)
Exc
#1
W
Armature
H EX1L SV1L
P28
S SV2H
L EX2H V
LVDR Exc EX2L
#1
K1
Armature
KS1
H JD1
P28
LV1H
L KS2
JD2
LV1L
LV2H
LV2L I/O Net
Enet 1
LV3H P (R)
Enet 2
LV3L S
LV4H V
LV4L P
LV5H
LV5L
LV6H
28 V 28 V (R)
LV6L
LA LB
SSVP (S) UA UB
P28
EX1H SV1H
EX1L W SV1L
P28
S SV2H
EX2H V
O SV2L
EX2L
K1
KS1
JD1
P28
LV1H
KS2
JD2
LV1L
LV2H
LV2L I/O Net
Enet 1
LV3H P (S)
Enet 2
LV3L S
LV4H V
LV4L P
LV5H
LV5L
LV6H
28 V 28 V (S)
LV6L
LA LB
Not used
Dual PSVP: Single Pilot / Single Cylinder Valves with Dual Coil Servo

The PSVP / SSVP does not support the TMR redundancy
configuration for the pilot / cylinder regulator.
Attention
PSVP Position Regulators

The following six servo position regulators are supported by the PSVP:
• Single LVDT/R position feedback, RegType = 1_LVposition

• Dual LVDT/R feedback minimum select, RegType = 2_LVposMIN
• Dual LVDT/R feedback maximum select, RegType = 2_LVposMAX
• Triple LVDT/R position feedback middle select, RegType = 3_LVposMID
• Single LVDT/R pilot cylinder, RegType = 2_LVpilotCyl
• Dual LVDT/R pilot cylinder maximum select, RegType = 4_LVp/cylMAX
There is a seventh position regulator option, RegType = no_fbk. With this option, a
position regulator runs in the control software, and the PSVP provides the position
feedback through the system input variable, Regn_fdbk where n = 1 or 2. The
controller’s position regulator output can be assigned to the System output, Regn_Ref
where the PSVP maps this value to the current regulator command.
Each of the position regulator types are comprised of the following blocks:
• Feedback Conditioning
• Proportional Regulator
• Calibration section
The configuration parameter RegType determines the number of feedback position sensors.
In addition, it determines the initial position feedback selection. Before the selection
process takes place, the Reg_Calc_Position block scales the position sensor feedback from
V rms to percent, where usually 100% is defined as a fully open valve. An out-of-range
check is performed on the V rms position value before the scaling takes place. The
out-of-range limit is defined by the configuration parameter LVDT_Margin in units of
percent. An out-of-range is declared if the V rms value is less than –LVDT_Margin(%)
or greater than LVDT_Margin(%) + 100% of the feedback range.
RegType No. of Position Sensors Selection Criteria

1_LVposition 1 No selection required.
2_LVposMIN 2 Select the minimum of the two position sensors.
2_LVposMAX 2 Select the maximum of the two position sensors.
3_LVposMID 3 Select the middle value from the three position values.
2_LVpilotCyl 1 pilot sensor No selection required.
1 cylinder sensor
4_LVp/cylMAX 2 pilot sensors Select the maximum from the two pilot sensor values and select
2 cylinder sensors the maximum from the two cylinder sensor values.

After the selection of the sensor feedback is complete, the selected position feedback
runs through a limit check function. The limits are defined by the configuration
parameter Fdbk_Suicide. The value is units of percent of feedback. A value of 5%
would declare an exceeded limit if the selected position feedback is greater than
105% or less than –5% where 100% is usually defined as a fully open valve. For
the 2_LvpilotCyl and the 4_LVp/cylMAX regulator types, the position feedback
PilotFdbkn is used for the limit check. If the configuration parameter EnabFbkSuic
= TRUE and the Fdbk_suicide limit is exceeded, the servo output will suicide (zero
current). This condition implies that the feedback has gone open loop due to either
a damaged sensor or a sensor excitation / feedback wiring open or short.
The proportional regulator error Regn_error is equal to the reference command from
the controller Regn_Ref minus the resultant position sensor feedback Regn_fdbk where
n is the regulator number 1 or 2. The position regulator output is defined as:
Servo_mA_refs(%) = Regn_error(%) * Reg_Gain(%servo current / % valve position) +
(RegNullBias(% current) + Regn_NullCor(% current))
where
Servo_mA_refs is the analog current regulator command in percent of servo

current nominal of 10, 20, 40, 80, or 120 mA
• Reg_Gain is the configuration parameter defining the gain from

percent position to percent servo current.
• RegNullBias is the portion of current required to null the spring force of the servo
actuator. For 3-coil servos, the null bias will be ⅓ of the total. For 2-coil individual,
the null bias will be ½ of the total. For 2-coil paralleled or single coil servos, the null
bias is assigned 100% of the total current needed to balance the spring force.
• Regn_NullCor is used by the controller to correct a null bias imbalance
if one of the PSVPs in a dual or TMR redundancy configuration goes
offline or the servo output suicides.
At startup or when a new PSVP is installed on site, a servo valve calibration should
be performed. During the calibration procedure, the servo is used to push the valve
to the maximum open-end point and the maximum closed-end point. At these end
points, the LVDT/R feedback voltage is read and stored. The PSVP uses this value
for scaling purposes when the Reg_Calc_Position function runs.
Note Servo regulator configuration settings (Reg_Gain, and so forth) are application
and site specific. Consult the equipment specific Controls Setting Specification or
equivalent document for proper configuration.

Digital Servo Regulator RegType = 1_LVposition
RegType I/O Configuration

LVDT1input Reg_Gain
GEH-6721L
EnabFbkSuic
RegNullBias
TMR_DiffLimt Fdbk_Suicide
Regn_Ref n=1- CalibEnabn

2 (so) Regn_error (si) n=1- 2 (so)
n=1- 2
+ +
+

X Regn_servo_mA_ref_pct
LVDT1
LVDT2 - +
LVDT3 M
LVDT4 Reg Calc. Limit
U Position(%) Regn_NullCor
LVDT5 Position* Check* Regn_fdb
LVDT6 X n=1- 2 (so)
k (si) n=1-
2
Calibrate
Function* MnLVDT1_Vrms(cfg),
Reg_Sensor_Hdwr_Hi MxLVDT1_Vrms(cfg)
Reg_Sensor_Hdwr_Lo
RegCalMode
Reg_Sensor_Offset (si)
Reg_Sensor_Gain
CalibEnabn (so)
Reg_Sensor_End_Stop_Min n=1- 2
Param_Name(cfg) - Servo config parameter (Toolbox view)

Signal_Name - signal from A/D in (no Toolbox view)
Variable_Name - internal vars to Servo (no Toolbox view)
* - indicates a detailed drawing with title per block name.
Input_Name MaxPosValue LVDT_Margin
- Input to controller from Servo (Toolbox view)
(si)
System Guide
Output_Name MinPosValue
- Output from controller to Servo (Toolbox view) I/O Configuration
(so)
22-35
Digital Servo Regulator RegType = 2_LVposMIN
22-36
LVDT1input RegType I/O Configuration
Reg_Gain
LVDT2input EnabFbkSuic
RegNullBias
Status_B Regn_error
LVDT1 (si) n=1- 2
LVDT2
LVDT3 M Regn_Ref
LVDT4 Reg Calc. Status_A
U n=1- 2 (so) CalibEnabn
LVDT5 Position*
LVDT6 X n=1- 2 (so)
Stat Stat
A B +
PositionA(%) A +
+
PositionB(%) B X Regn_servo_mA_ref_pct
LVDT1
- +
M
Reg Calc. Limit
U MIN M
Regn_NullCor
Position* Check* Regn_fdb
X n=1- 2 (so)
k (si) n=1-
LVDT6 2
Minimum Select
Calibrate MnLVDT1_Vrms(cfg),
Function* MxLVDT1_Vrms(cfg)
Reg_Sensor_Hdwr_Hi
Reg_Sensor_Hdwr_Lo MnLVDT2_Vrms(cfg),
MxLVDT2_Vrms(cfg)
Reg_Sensor_Offset
RegCalMode
Reg_Sensor_Gain (si)
Reg_Sensor_End_Stop_Min CalibEnabn
(so) n=1- 2

(si)
- Output from controller to Servo (Toolbox view)
(so) I/O Configuration

Digital Servo Regulator RegType = 2_LVposMAX
LVDT1input RegType I/O Configuration
Reg_Gain
LVDT2input
GEH-6721L
EnabFbkSuic
RegNullBias
LVDT1 Status_B
LVDT2
LVDT3 M Regn_Ref
LVDT4 Reg Calc. Status_A n=1- 2 (so)
U CalibEnabn
LVDT5 Position* Regn_error
LVDT6 X n=1- 2 (so)
n=1- 2 (si)
PositionA(%) Stat Stat
A B
A + +
+
B X

Regn_servo_mA_ref_pct
LVDT1
PositionB(%) - +
M
Reg Calc. Limit
U MAX M Regn_NullCor
Position* Check*
X Regn_fdbk n=1- 2 (so)
(si) n=1- 2
LVDT6
Maximum Select
Calibrate MnLVDT1_Vrms(cfg),
Function* MxLVDT1_Vrms(cfg)
Reg_Sensor_Hdwr_Hi
MnLVDT2_Vrms(cfg),
Reg_Sensor_Hdwr_Lo MxLVDT2_Vrms(cfg)
Reg_Sensor_Offset
RegCalMode
CalibEnabn
Reg_Sensor_End_Stop_Min (so) n=1- 2

Input_Name
- Input to controller from Servo (Toolbox view) MaxPosValue LVDT_Margin
(si)
System Guide
(so)
22-37
Digital Servo Regulator RegType = 3_LVposMID
22-38
LVDT1input RegType RegNullBias I/O Configuration
LVDT2input
EnabFbkSuic Reg_Gain
LVDT3input TMR_DiffLimt
Fdbk_Suicide
LVDT1
LVDT2
LVDT3 M
LVDT4 Reg Calc. Regn_Ref CalibEnabn
U
LVDT5 Position* n=1- 2 (so) Regn_error
LVDT6 X n=1- 2 (so)
(si) n=1- 2
PositionA(%) + +
+
X Regn_servo_mA_ref_pct
LVDT1
- +
M Limit
Reg Calc. Median
U PositionB(%) Regn_NullCor
Position* Select Check*
X Regn_fdbk n=1- 2 (so)
(si) n=1- 2
LVDT6
PositionC(%)
LVDT1
M
Reg Calc.
U MnLVDT1_Vrms(cfg),
Position*
X MxLVDT1_Vrms(cfg)
Calibrate
LVDT6 Function* MnLVDT2_Vrms(cfg),
Reg_Sensor_Hdwr_Hi MxLVDT2_Vrms(cfg)
Reg_Sensor_Hdwr_Lo MnLVDT3_Vrms(cfg),
MxLVDT3_Vrms(cfg)
Reg_Sensor_Offset
RegCalMode
CalibEnabn
Reg_Sensor_End_Stop_Min (so) n=1- 2

(si)
Output_Name - Output from controller to Servo (Toolbox MinPosValue
(so) view) I/O Configuration

Digital Servo Regulator RegType = 2_LVpilotCyl
RegType
I/O Configuration
RegNullBias
GEH-6721L
LVDT1input
LVDT2input Reg_Gain Pilot_Gain
TMR_DiffLimt
Regn_Ref
n=1 (so) CalibEnabn
Regn_error n=1 (so)
(si) n=1
LVDT1 Regn_fdbk
LVDT2 + +
M (si) n=1 + + +
LVDT3 Reg Calc. Limit Servo_mA_refn
U CylinderPos(%) X X
LVDT4 Position* Check* -
LVDT5 X
- +
LVDT6

Regn_NullCor
LVDT1 PilotFdbk n=1 (so)
LVDT2 M
LVDT3 Reg Calc. Limit (si)
LVDT4 U PilotPos(%)
Position* Check*
LVDT5 X
LVDT6
Calibrate
Reg_Sensor_Hdwr_Hi
MxLVDT1_Vrms(cfg)
Reg_Sensor_Hdwr_Lo
RegCalMode
Reg_Sensor_Gain
CalibEnabn
Reg_Sensor_End_Stop_Min (so) n=1
Param_Name(cfg) - Servo config parameter (Toolbox

view)
Variable_Name - internal vars to Servo (no Toolbox view) MaxPosValue
Input_Name - Input to controller from Servo LVDT_Margin
(si) (Toolbox view)
System Guide
Output_Name - Output from controller to Servo MinPosValue
(so) (Toolbox view) I/O Configuration
22-39
Digital Servo Regulator RegType = 4_LVp/cylMax
22-40
LVDT1input I/O Configuration
LVDT2input TMR_DiffLimt RegNullBias
LVDT3input RegType Reg_Gain
LVDT4input Pilot_Gain
LVDT1 Regn_Ref
LVDT2 M Regn_err CalibEnabn
Reg Calc. n=1 (so) or (si) n=1 (so)
LVDT3 U
LVDT4 X Position* n=1
LVDT5
LVDT6 Regn_fdb + +
MAX Limit k (si) n=1 + + +
Select
CylinderPos(%) Check*
X X Servo_mA_refn
LVDT1 -
LVDT2 M - +
LVDT3 Reg Calc.
U
LVDT4 Position*
LVDT5 X
Regn_NullC
LVDT6
or n=1
(so)
LVDT1
LVDT2 M
LVDT3 Reg Calc.
LVDT4 U Position*
LVDT5 X PilotFdbk
LVDT6 MAX Limit (si)
Select
PilotPos(%) Check*
LVDT1
LVDT2 M
LVDT3 Reg Calc.
LVDT4 U
Position*
LVDT5 X
LVDT6
Calibrate
Reg_Sensor_Hdwr_Hi
MxLVDT1_Vrms(cfg)
Reg_Sensor_Hdwr_Lo
RegCalMode
Reg_Sensor_Gain
CalibEnabn
Reg_Sensor_End_Stop_Min (so) n=1

* a detailed drawing with title per block name.
- indicatesInput_Name MaxPosValue
- Input to controller from Servo (Toolbox view) LVDT_Margin
(si)
(so)

PSVP Variable Definitions

L3DIAG_PSVP PSVP I/O diagnostic indication Input non-voted Boolean 3 bits
LINK_OK_PSVP PSVP I/O Link OK indication Input non-voted Boolean 3 bits
ATTN_PSVP PSVP I/O attention indication Input non-voted Boolean 3 bits
PS18V_PSVP PSVP I/O 18 V power supply indication Input non-voted Boolean 3 bits
PS28V_PSVP PSVP I/O 28 V power supply indication Input non-voted Boolean 3 bits
IOPackTmpr PSVP I/O pack temperature in degrees °F Analog input non-voted Real
Rx_SuicideNV ServoOutputx suicide relay status where x = 1 or 2 Input non-voted Boolean 3 bits
Regx_CalibratedNV Regulator x (x=1 or 2) has been calibrated. Input non-voted Boolean 3 bits
Reg1_Suicide ServoOutput1 suicide relay status Input voted Boolean
Reg2_Suicide ServoOutput2 suicide relay status Input voted Boolean
HSNG_Stat Pulse rate high speed next generation stability status (TRUE Input voted Boolean
for tooth to tooth distance inside Lock_Limit for tooth geometry
compensation)
RegCalMode Regulator under calibration Input voted Boolean
Reg1_Fdbk Regulator 1 position feedback Analog input voted REAL
Reg2_Fdbk Regulator 2 position feedback Analog input voted REAL
PilotFdbk1 Regulator 1 pilot feedback when 2_LvpilotCyl or 4_LVp/cylMax Analog input voted REAL
PilotFdbk2 Regulator 2 pilot feedback when 2_LvpilotCyl or 4_LVp/cylMax Analog input voted REAL
Reg1_Error Position error for the regulator 1 position loops and pulse rate Analog input voted REAL
error for the pulse rate reg.
Reg2_Error Position error for the regulator 2 position loops and pulse rate Analog input voted REAL
error for the pulse rate reg.
Accel Acceleration value of the variable PulseRate Analog input voted REAL
Monx where x = 1 to 6 Value assigned to Monx based on configuration parameters Analog input voted REAL
found in the Monitor tab
Exn_ActiveNV Excitation #n active(on) where n = 1 or 2 Input non-voted Boolean 3 bits
Excit_Monx Excitation monitor x (V rms) where x = 1 or 2 Analog input voted REAL
ServoOutx Servo output x measured current (%) where x = 1 or 2 Analog input non-voted Real
ServoxMonitorNV Servo x AvSelection monitor where x = 1 or 2 Analog input non-voted Real
CalibEnab1 Enable calibration regulator 1 Output Boolean
CalibEnab2 Enable calibration regulator 2 Output Boolean
SuicidForcex Force suicide on servo x where x = 1 or 2 Output Boolean
Regx_Ref Regulator x position reference (%) where x = 1 or 2 Output Boolean
Regx_NullCor Regulator x null bias correction (%) where x = 1 or 2 Output Boolean
SysLimxPR System limit for pulse rate input X, where x=1 or 2 Input Boolean
ActivateCalibCmd Activate calibration command Inputed voted Boolean

SSVP Servo Input/Output
T1 through T2 isolation The Servo I/O (SSVP) terminal board connects to two electro-hydraulic servo valves that
transformers provide galvanic actuate the steam valves. Valve position is measured with linear variable differential
isolation between the SSVP’s transformers (LVDT) or linear variable differential reluctance transformers (LVDR).
excitation output driver and the SSVP is designed specifically for the PSVP I/O pack and the WSVO servo driver.
primary-side of the LVDT/R It does not work with the VSVO board or the PSVO pack. The SSVP is a simplex
position sensor. terminal board. Dual redundancy is supported by using two SSVPs and fanning
the inputs externally. Likewise, for TMR redundancy, use three SSVPs and fan
the LVDT inputs externally by using jumpers to send the signal from one SSVP
to another SSVP. A single 28 V dc supply comes in through plug P28IN. Plugs
JD1 or JD2 are for an external trip from the protection module.
P28OFF P28ON
P28N P28ON PSVP ONLY
P28IN
JUA
JUB
2 1
SW1
low high
TB1 JA 2 is the 48-
pin connector
WSVO for WSVO
LVDT 1 (H) Servo
LVDT 1 (L)
LVDT 2 (H)
LVDT 2 (L) PWR
LVDT 3 (H) ATTN
LVDT 3 (L)
LVDT 4 (H) T1
LVDT 4 (L) EX1 LINK
LVDT 5 (H) EX2 TxRx
LVDT 5 (L)
LVDT 6 (H)
JA2
LVDT 6 (L) SV1 LINK
Excitation 1 (H) SV2 TxRx
Excitation 1 (L)
Excitation 2 (H)
Excitation 2 (L) T2
Servo 1 (H)
Servo 1 (L)
Servo 2 (H)
Servo 2 (L) Sservo 2 (H)
Sservo 2 (L) IS220PSVP
Pulse Rate (H)
Pulse Rate (L) JA 1 is the 62-
pin connector
JP1 JP2 for PSVP
+/- 120 B mA
+/- 120 A mA
+/- 80 mA
Up to two # 12 AWG
+/- 40 mA
JLB
JLA
wires per point with +/- 20 mA

300 V insulation +/- 10 mA
SSVP Terminal Board

Terminal Board Options
The SSVP accepts direct mounting of the PSVPH1A I/O pack and the WSVOH1A
servo driver module. There are four options for the SSVP terminal board:
• SSVPH1A provides the 24-point barrier style input connector.

• SSVPH2A provides the Euro-style connector.
• IS230SSVPH1A barrier style with subassembly
• IS230SSVPH2A Euro-style with subassembly
The IS230SSVPHxx is a subassembly comprised of the PSVP I/O pack, the WSVO
servo driver, the SSVP terminal board, and the DIN-rail mechanical assembly.
Subassembly PSVP WSVO SSVP Description

IS230SSVPH1A H1A H1A H1A DIN-rail subassembly with a SSVP
providing a 24-point barrier-strip type
customer connector
IS230SSVPH2A H1A H1A H2A DIN-rail subassembly with a SSVP
providing a Euro-style customer connector

Installation
The SSVP can only be used Sensors and servo valves are wired directly to the TB1 I/O terminal block. The block is
with the PSVP I/O pack. held down with two screws and has 24 terminals accepting up to #12 AWG wiring. A
shield terminal strip attached to chassis ground is located immediately to the left of
the terminal block. External trip wiring is plugged into either JD1 or JD2.
Each SSVP servo output can support one coil of a three-coil electro-hydraulic
servo-actuator or paralleled-coils from a two-coil servo. Based on the rated
coil current, the user selects the current limiting resistor value to limit thermal
stress on the current driver in case of a shorted output. Jumper, JP1 selects
the resistor value for Servo 1 and JP2 is for Servo 2.
The P28 power input for the PSVP and WSVO comes into the servo through the
SSVP connector labeled P28IN. Switch, SW1 is used to enable the P28 bus that feeds
the PSVP pack and the WSVO servo driver module. A LED labeled P28IN lights
if 28 V dc has been applied to the SSVP. The P28ON LED will remain OFF until
the user turns SW1 to the P28ON position. A third LED, PSVP_ONLY will light
if the PSVO pack is accidently plugged into the JA1 connector.
Connecting to the PSVP

The SSVP simplex terminal board has one DC-62 pin connector, JA1 to accommodate
the PSVP pack. The JA1 inputs LVDT and the pulse rate signals from the SSVP input
circuits. It outputs current command signals to the WSVO and receives feedback status
information from the WSVO. It outputs excitation reference to the excitation drivers on
the SSVP. It supports I/O from the RS-422 drivers to support the Private Serial Network
used to control the excitation switchover and the isolation protection for servos paralleled.
Connecting to the WSVO

The JA2 connector is for the WSVO servo driver module. The WSVO module is held
down with four screws. If a diagnostic indicates a servo problem, it is recommended
to replace both the PSVP pack and the WSVO servo driver module.
Turn the SSVP input power switch, SW1 to OFF before

removing the PSVP, WSVO, TB1, P28 connector, and
serial connectors.
Attention

Operation
The SSVP servo terminal board provides two channels consisting of bi-directional
servo current outputs, six channels of LVDT/R position feedback, two channels of
LVDT/R excitation, and one pulse rate input. It provides four excitation outputs,
and accepts inputs from up to six LVDT valve position inputs. There is a choice
of one, two, or three LVDT/Rs for each servo control loop. The single pulse
rate input is used for the steam turbine primary speed.
Each servo output is equipped with an individual suicide relay under firmware
control that shorts the WSVO output signal-to-signal common when de-energized,
and recovers to nominal limits after a manual reset command is issued. Each servo
output also includes an isolation relay to isolate a short from other servos that
are connected in parallel to the suicided servo. Diagnostics monitor the output
status of each servo voltage, current, and suicide relay.
Each of the servo output channels can drive either one or two-coil servos in simplex
applications, or two or three-coil servos in TMR applications. Servo cable lengths up to 300
m (984 ft) are supported with a maximum two-way cable resistance of 15 Ω. Since there are
many types of servo coils, a variety of bi-directional current sources are jumper selectable.
The primary and emergency A trip override relay K1 is provided on the terminal board, which is driven from
overspeed systems will trip the PPRO protection I/O pack. If an emergency overspeed condition is detected
the hydraulic solenoids in the protection module, the K1 relay energizes, disconnects the servo output,
independent of this circuit. and applies a bias to drive the control valve closed. This is only used on simplex
applications to protect against the servo amplifier failing high, and is functional
only with respect to the servo coils driven from <R>.

SSVP Operational Flow 1 of 2

SSVP Operational Flow 2 of 2

TMR
In TMR applications, the LVDT/R signals are fanned externally through customer
wiring to LVDT inputs SSVP_R, SSVP_S, and SSVP_T. For 3-coil servos, SSVP_R servo
output connects to coil one, SSVP_S connects to coil two, and SSVP_T connects to the
third coil of the 3-coil servo actuator. Redundant power for the TMR configuration
is handled by independent 28 V dc sources for each SSVP.
Servo Coils
The excitation source is isolated The following table defines the standard servo coil resistance and their associated internal
from signal common (floating) resistance, selected with the terminal board jumpers. In addition to these standard servo
and is capable of operation at coils, it is possible to drive non-standard coils by using a non-standard jumper setting. For
common mode voltages up to example, an 80 mA, 125 Ω coil could be driven by using a jumper setting 120B.
15 V dc, or 10 V rms, 50/60 Hz.
Note Servo configuration settings (Reg_Gain, jumpers, and so forth) are application
and site specific. Consult the equipment specific Controls Setting Specification or
equivalent document for proper configuration.
Servo Coil Resistance and Associated Internal Resistance
Current Rating Current Coil Resistance Internal Resistance

(Ohms) (Ohms)
10 ±10 mA 1000 170 ±10%
20 ±20 mA 125 432 ±10%
40 ±40 mA 62 - 89 185 ±10%
80 ±80 mA 22 105 ±10%
120A ±120 mA (A) 40 18 ±10%
120B ±120 mA (B) 75 0
Refer to the PSVP Servo Control valve position is sensed with either a three or four-wire LVDT, or a three-wire
Control, Operation, linear variable differential reluctance (LVDR) transducer. Redundancy implementations
Recommended Wiring for the feedback devices are determined by the application software to allow the
Practices section for more maximum flexibility. LVDT/Rs can be mounted up to 300 m (984 ft) from the
information. turbine control with a maximum two-way cable resistance of 15 Ω.
Two LVDT/R transformer-isolated excitation sources are located on the terminal board.
Excitation voltage is 7.07 V rms, and the frequency is 3.2 kHz with a total harmonic
distortion of less than 1%. A typical LVDT/R has an output of 0.7 V rms at the zero
stroke position of the valve stem, and an output of 3.5 V rms at the designed maximum
stoke position (some applications have these reversed). The LVDT/R input is converted
to dc and conditioned with a low pass filter. Diagnostics perform a high/low (hardware)
limit check on the input signal and a high/low system (software) limit check.
The pulse rate input supports a single passive magnetic pickup only. The TTL type active
pulse rate transducer is not supported. The MPU can be located up to 300 m (984 ft)
from the turbine control cabinet. This assumes shielded-pair cable is used with typically
70 nF single ended or 35 nF differential capacitance, and 15 Ω resistance.
A frequency range of 2 to 20 kHz can be monitored. Magnetic pickups

typically have an output resistance of 200 Ω and an inductance of 85 mH
excluding cable characteristics. The transducer is a high-impedance source,
generating energy levels insufficient to cause a spark.

Specifications
Item Specification
Number of inputs Six LVDT windings
One pulse rate signal, magnetic only
External trip signal to shut off servo outputs
Number of outputs Two servo valves, ±(10, 20, 40, 80, 120) mA
Two excitation sources for LVDT / Rs (transformer isolation)
Power supply Nominal 28 V dc from single supply, P28
voltage Pin 1 is Hi
Pin 2 is Lo
Power supply 1.5 A dc (Poly-Fuse or current limit rating for each input is 1 A dc)
current
LVDT excitation Frequency of 3.2 ±0.2 kHz
output Voltage of 7.07 ±0.14 V rms
Pulse rate input Minimum signal for proper measurement at 2 Hz is 36 mV p-p
Magnetic PR Generates 150 V p-p into 60 Ω
pickup signal
Failed ID chip
Physical
Diagnostics
PSVP makes diagnostic checks on the terminal board components as follows:
• The output servo current is out of limits or not responding, creating a fault.
• The regulator feedback (LVDT) signal is out of limits, creating a fault. If
the associated regulator has two sensors, the bad sensor is removed from
the feedback calculation and the good sensor is used.
• If any one of the above signals goes unhealthy a composite diagnostic alarm,
L3DIAG_PSVP occurs. Details of the individual diagnostics are available from
the ToolboxST application. The diagnostic signals can be individually latched
and reset with the RESET_DIA signal if they go healthy.

Configuration
Power must be applied to In a simplex system, servo 1 is configured for the correct coil current with jumper
P28IN connector. Check that JP1. Servo 2 is configured with jumper JP2. In a TMR system, one servo from
the P28IN LED is lit, the SW1 three different SSVPs provides the drivers needed for three coils. In this case,
switch is ON, and the P28ON the LVDT inputs are fanned externally to all three SSVPs. All other servo board
power indicator is lit. configuration is done from the ToolboxST application.
Module Level Parameters

Exc_Sharing Connections for sharing excitation of LVDT (for dual configuration Unused
only) R1_S1_only,
For example: R1_S1 and R2_S2 means R1_S2_only,
Excitation output 1 of R PSVP and output 1 of S PSVP connected R2_S1_only,
to the same LVDT coil R2_S2_only,
Excitation output 2 of R PSVP and output 2 of S PSVP connected R1_S1_and_R2_S2,
to the same LVDT coil R1_S2_and_R2_S1
Serial_Links These are the serial link cable connections where upper refers to Unused
the serial connectors at the top of the SSVP and lower refers to the R_upper_to_S_lower
serial connectors at the bottom of the SSVP. All connections from R_lower_to_S_upper
A labeled connectors must go to A connectors on other SSVPs.
All connections from B connections must go to B connectors on
other SSVPs. Upper connectors can only be connected to lower
connectors.
For dual systems, only R and S can be used with connections
R_upper_to_S_lower or R_lower_to_S_upper.
For TMR systems, there are only two available combinations of

connections. They are uniquely identified by one connection pair
selected from the option list.
R_upper_to_S_lower option configures:
R upper connected to S lower
S upper connected to T lower
T upper connected to R lower
R_lower_to_S_upper option configures:

R upper connected to T lower
S upper connected to R lower
T upper connected to S lower
AccelCalTime This is the acceleration calculation time for speed algorithms 0 to 100 ms (default is 100)
Speed and Speed_High. Use integer multiples of controller frame
period.
UcntrlDiag It enables micro-controller diagnostics. This should always be Enable (default), Disable
enabled unless nuisance exciter alarms (73 or 74 category 3 only)
are occurring, and replacing the PSVP hardware did not correct
the problem.

IS200SSVP Configuration Definitions

ServoOutput# Servo Output X measured current in percent. Point Edit (Input Real)
Where # = 1 or 2
RegNumber Maps a specific regulator to a given servo output Unused, Reg1, Reg2
(Default-Unused)
Servo_MA_Out Nominal servo current rating in mA 10 mA (default), 20 mA,
40 mA, 80 mA, 120 mA
EnablCurSuic Enable Current Suicide Function Enable, Disable (default)
EnablFbkSuic Enable Position Feedback Suicide Function Enable, Disable (default)
AV_Selector Configuration selector to map one of the specified variables to the Coil_OHMs, Compliance_Voltage,
PSVP variable, ServoxMonitorNV where x = 1 or 2. MA_CMD_PCT,
Servo_Screw_Voltage,
Excitation_Current
Curr_Suicide Current command is compared to the actual feedback current. If 0 to 100 (default 5)
the error exceeds the configuration limit, Curr_Suicide (%), then
the Servo output will suicide.
Fdbk_Suicide The position feedback, Regx_Fdbk (%) is compared against the 0 to 100 (default 5)
value, 100% + Fdbk_Suicide (%). If Regx_Fdbk (%) where x = 1
or 2 exceeds that value, the regulator assumes the feedback has
gone open loop and the servo must be suicided if this condition
and the EnablFbkSuic = Enable to the end should have been
placed in description for OpenCoilSuic instead of Fdbk_Suicide.
OpenCoilSuic If configuration parameter, OpenCoilSuic = Enable, then the servo Enable, Disable (default)
coil open detection function will suicide the servo if the function
detects an open ckt. Set OpenCoildiag = Enable to receive a
diagnostic message as to why the servo suicide occurred.
If the Coil_Parallel parameter is set to Coils_Parallel, set

OpenCoilSuic to Disable. This allows the servo to keep generating
current if one of the two servo coils fails to open.
If one coil fails and remains open, the calculated coil resistance
value doubles to a value that is at the nominal open circuit
threshold. Set the OpenCoilDiag parameter to Enable so the open
coil failure is annunciated for this case.
ShrtCoilSuic If configuration parameter ShrtCoilSuic = Enable, then the servo Enable, Disable (default)
coil short ckt. Detection function will suicide the servo if the
function detects a short ckt. Set ShrtCoildiag = Enable to receive
a diagnostic message as to why the servo suicide occurred.
OpenCoildiag If enabled, a specific diagnostic message is generated to show Enable, Disable (default)
why the servo suicide occurred, such as Servo x Suicide due to
Open servo coil.
ShrtCoildiag If enabled, a specific diagnostic message is generated to show Enable, Disable (default)
why the servo suicide occurred, such as Servo x Suicide due to
Short circuit of servo coil.

Coil_Parallel If set to Coils_Parallel then the servo is connected to 2 servo Coils_parallel,
coils wired in parallel. The coil resistance calculation determines Coils_not_parallel (default)
the resistance of a single coil for use with the short and open
circuit coil protection. If set to Coils_not_parallel then the servo is
connected to a single servo coil.
TBmAJmpPos This is the SSVP terminal board mA jumper position selection. It 10 mA (default), 20 mA, 40 mA, 80
should match the jumper selection on the SSVP mA, 120 mA A, 120 mA B
RopenTimeLim This is the time in seconds required for the open circuit condition 0 to 100 (default 1)
of the servo coil to be in effect before a diagnostic and / or suicide
of the servo (if enabled) occurs.
RShrtTimeLim This is the time in seconds required for the short circuit condition 0 to 100 (default 1)
of the servo coil to be in effect before a diagnostic and / or suicide
of the servo (if enabled) occurs.
RcoilOpen This defines the initial value for the open circuit resistance in 1 to 10E+09 (default 1000000)
ohms. After the LVDT calibration, the value for RcoilOpen is 2
* (Servo_Screw_Volts / Servo Current) measured during the
calibration mode.
RcoilShort This defines the initial value for the short circuit resistance in 1 to 10E+09 (default 0)
ohms. After the LVDT calibration, the value for RcoilShort is 0.5
* (Servo_Screw_Volts / Servo Current) measured during the
calibration mode.
TMR_DiffLimt Diagnostic limit, TMR Input Vote difference in % 0 to 110 (default 25)
Pulse Rates Bipolar input = PRH – PRL Point Edit (Input Real)
PRType This Define the pulse rate feedback type or basic speed range. Speed, Speed_High, Speed_HSNG
(unused)
PRScale Scaling: pulses per revolution (outputs RPM) 0 to 1000
Speed_x_ms This is the calculation rate of speed in milliseconds. Speed is 5 to 1000
calculated at this rate and averaged over the previous time interval
specified by this period.
Using a value other than an integer multiple

of the associated application frame rate can
have an adverse impact on use of this in
control.
Attention
Accel_x_ms This is the averaging period for acceleration calculation in 10 to 1000
milliseconds. The acceleration is calculated every Accel_X_ms. It
is based on the difference between two speed samples divided by
the sample period. Each acceleration calculation is the average
of acceleration over the period specified by this parameter. For
example, if Accel_x_ms is 40 then acceleration is the average
acceleration over the previous 80 ms.

Using a value other than an integer multiple

of the associated application frame rate can
have an adverse impact on use of this in
control.
Attention
Lock_Limit This is the HSNG speed type-locking limit for teeth mapping 1 to 100 (must be a positive integer)
(percent).
SysLim1Enabl If enabled, System Limit 1 is active. Enable, Disable (default)
SysLim1Latch If enabled, the System Limit 1 function will latch its state if the Latch (default), NotLatch
PulseRate exceeds the limit function defined by SysLim1Type
and SysLimit1.
SysLim1Type Defines the compare function used in the Limit1 expression. >= (default), <=
SysLimit1 Defines Limit1 value to be used for the input, PulseRate. 0 to 20,000 (default 0)
SysLim2Enabl If enabled, System Limit 2 is active. Enable, Disable (default)
SysLim2Latch If enabled, the System Limit 2 function will latch its state if the Latch (default), NotLatch
PulseRate exceeds the limit function defined by SysLim2Type
and SysLimit2.
SysLim2Type Defines the compare function used in Limit 2’s expression >= (default), <=
SysLimit2 Defines Limit2 value to be used for the input, PulseRate 0 to 20,000 (default 0)
TMR_DiffLimt Diagnostic limit, TMR Input Vote difference in % 0 to 20,000 (default 5)
Excitation PSVP supports 2 LVDT excitation channels. An individual set
of configuration parameters are supplied for each Excitation
x where x = 1 through 2.
StandAloneDiag Non-shared diagnostic enable, diagnostics cannot be disabled for 1 = enable (default) , 0 = disable
excitation outputs that have been configured as shared by the
Exc_Sharing parameter
Common The following parameters are common for all regulators
RegType Regulator Algorithm Type Unused, no_fbk, 1_LVposition,
2_LVpilotCyl,
2_LVposMAX, 2_LVposMIN,
3_LVposMID,
4_LVp/cylMAX
Dither_Freq Dither rate in hertz. 12.5 Hz, 25 Hz, 33.33 Hz, 50 Hz,
100 Hz (default), Unused
DitherAmpl Dither in % current 0 to 10 (default 2)
RegGain Position loop Gain in % current / Eng Units or usually % current / -200 to +200 (default 1)
% position
RegNullBias Regulator Null Bias provides a fixed current command in percent -100 to +100 (default 0)
to cancel or null the spring force of the valve which will close the
valve if the servo suicides or shuts down.
TMR_DiffLimt Diagnostic limit, TMR Input Vote difference in % 0 to 150 (default 5)

LVDT PSVP supports six LVDT input channels. An individual set of
Parameters configuration parameters as listed below are supplied for each
LVDTx where x = 1 through 6.
Enable Selects this LVDT to be used by the PSVP monitor or position Enable or Disable (default)
regulator for servo control use
LVDT_Margin This defines the over range in % for the LVDT input. A diagnostic 0 to 100 (default 2)
is generated if this value is exceeded.
MinVrms LVDT1 V rms is at the minimum end stop of the valve. These 0 to 7.1 (default 1)
values are normally set by the Auto-Calibrate function.
MaxVrms LVDT1 V rms is at the maximum end stop of the valve. These 0 to 7.1 (default 1)
values are normally set by the Auto-Calibrate function.
MaxPOSvalue Position in Eng. units (usually %) at the maximum end stop of -15 to 150 (default 100)
the valve
MinPOSvalue Position in Eng. units (usually %) at the minimum end stop of -15 to 150 (default 0)
the valve
TMR_DiffLimt Diagnostic limit, TMR Input vote difference in % 0 to 150 (default 5)
RegType Position regulator used with a single LVDT Input = 1 LV position
LVDT1input Defines which LVDT input from the SSVP will be used by the LVDT1, LVDT2, LVDT3, LVDT4,
position regulator for input 1 LVDT5, LVDT6, or Unused (default)
RegType Pilot cylinder regulator with two LVDT position feedbacks = 2_LVpilotCyl
PilotGain Pilot loop gain in % current / Eng. unit -200 to +200 (default 1)
LVDT1input Defines which LVDT input from the SSVP will be used for the LVDT1, LVDT2, LVDT3, LVDT4,
cylinder feedback mapped into Regx_fdbk where x = 1 or 2 LVDT5, LVDT6, or Unused (default)
LVDT2input Defines which LVDT input from the SSVP will be used for the pilot LVDT1, LVDT2, LVDT3, LVDT4,
feedback mapped into PilotFdbk. LVDT5, LVDT6, or Unused (default)
RegType Position regulator using the maximum select from 2 LVDT = 2_LVposMAX
inputs for feedback
LVDT1input Defines which LVDT input from the SSVP the position regulator LVDT1, LVDT2, LVDT3, LVDT4,
will use for input 1. LVDT5, LVDT6, or Unused (default)
will use for input 2. LVDT5, LVDT6, or Unused (default)
RegType Position regulator using the minimum select from 2 LVDT = 2_LVposMIN
inputs for feedback
will use for input 1 LVDT5, LVDT6, or Unused (default)
RegType This is the position regulator using the median select from = 3_LVposMID
3 LVDT inputs for feedback. It was originally designed for
heavy-duty gas turbines.

RegType Four LVDT pilot cylinder with maximum select of two LVDTs =4_LVp/cylMAX
for cylinder feedback and maximum select of two LVDTs for
the pilot feedback
PilotGain Pilot loop gain in % current / Eng. unit -200 to +200 (default 1)
LVDT1input Defines which LVDT input from the SSVP will be used for the first LVDT1, LVDT2, LVDT3, LVDT4,
input into the maximum select of the cylinder feedback mapped LVDT5, LVDT6, or Unused (default)
into Reg_fdbk.
second input into the maximum select of the cylinder feedback LVDT5, LVDT6, or Unused (default)
mapped into Reg_fdbk.
LVDT3input Defines which LVDT input from the SSVP will be used for the first LVDT1, LVDT2, LVDT3, LVDT4,
input into the maximum select of the pilot feedback, PilotFdbk. LVDT5, LVDT6, or Unused (default)
second input into the maximum select of the pilot feedback, LVDT5, LVDT6, or Unused (default)
PilotFdbk.
MonType Monx equals the scaled value from the LVDT assigned = 1_LVposition
through LVDT1input where x = 1 to 6
LVDTxinput LVDTx input selection LVDT1, LVDT2, LVDT3, LVDT4,
where x = 1 LVDT5, LVDT6, Unused (default)
MonType Monx equals the maximum selected scaled value from two = 2_LVposMAX
LVDTs assigned through LVDTyinput where x = 1 to 6 and
y = 1 to 2.
where x = 1 to 2 LVDT5, LVDT6, Unused (default)
TMR_DiffLimt Diagnostic limit, TMR Input Vote difference in % -10 to 150 (default 5)
MonType Monx equals the minimum selected scaled value from two = 2_LVposMIN
y = 1 to 2.
TMR_DiffLimt Diagnostic limit, TMR Input Vote difference in % -10 to 150 (default 5)
MonType Monx equals the median selected scaled value from three = 3_LVposMID
y = 1 to 3.
TMR_DiffLimit Diagnostic limit, TMR Input Vote difference in % -10 to 150 (default 5)
SystemLimits Enable system limit checking Enable (default), Disable

Notes

PTCC Thermocouple Input Module
Thermocouple Input (PTCC)

THERMOCOUPLE The Thermocouple Input (PTCC) pack provides the electrical interface between one or
PWR two I/O Ethernet networks and a thermocouple input terminal board. The pack contains
ATTN
a processor board common to all Mark* VIe distributed I/O packs and an acquisition
board specific to the thermocouple input function. In the Simplex configuration using
TBTCH1C, each pack is capable of handling up to 12 thermocouple inputs, for a total
LINK
ENET1 of 24 inputs using two packs. In the Simplex configuration using TBTCH1B, each pack
TxRx is capable of handling up to 12 thermocouple inputs, for a total of 24 inputs provided
the packs only use the JRA and JTB connectors. In the TMR configuration with the
LINK TBTCH1B terminal board, three packs are used with three cold junctions, but only 12
ENET2
TxRx
thermocouples are available. Input to the pack is through dual RJ45 Ethernet connectors
and a three-pin power input. Output is through a DC-37 pin connector that mates directly
IR PORT with the associated terminal board connector. Visual diagnostics are provided through
indicator LEDs.

IS220PTCCH1A
PTCCH1 supports E, J, K, S, T types of standard thermocouples and mV inputs. The
mV span is –8 mV to +45 mV.
PTCCH2 supports E, J, K, S, T as well as B, N, and R types of standard thermocouples

and mV inputs. The mV span for PTCCH2 is –20 mV to +95 mV.
GEH-6721L PTCC Thermocouple Input Module System Guide 23-1

PTCCH1A
Thermocouple
Input Module Processor board
Application board
Single or dual
Ethernet cables
ENET1
TBTCH1B
One PTCC module for Thermocouple Input
Simplex control (any of the Terminal Board ENET2
outside set of connectors)
External 28 V dc
JTB
power supply
Thermocouple
Inputs ENET1
ENET2
JSB
28 V dc
Two PTCC modules for
Dual control (any 2 of the
outside set of connectors) ENET1
ENET2
Three PTCC modules for JRB
28 V dc
TMR control
Compatibility
PTCCH1A/PTCCH2A is compatible with the thermocouple input terminal board
TBTC, and the STTC board, but not the DIN-rail mounted DTTC board. The
following table gives details of the compatibility.
Terminal Board TBTC STTC

Version and TBTCH1B (24 TC)* TBTCH1B TBTCH1B STTCH1A
Inputs TBTCH1C (24 TC)* (12 TC) (12 TC) (12 TC)
Control Mode Simplex - Yes Dual - Yes TMR - Yes Simplex - Yes
*Support of 24 thermocouple inputs on TBTC in the Simplex configuration requires the

use of two PTCC packs. Packs must be connected to JRA and JTB when using TBTCH1B.

Installation
¾ To install the PTCC pack
2. Directly plug the PTCC I/O pack into the terminal board connectors.
applied to the DC37 connector between the pack and the terminal board. The
Note The PTCC mounts directly to a Mark VIe terminal board. Simplex terminal
boards (TBTCH1C) have two DC-37 pin connectors that receive the PTCC, one for
each set of 12 TC inputs. TMR capable terminal boards (TBTCH1B) have six DC-37
pin connectors. These can be used in dual mode if two packs are installed, and in
simplex mode if only one PTCC is installed. The PTCC directly supports all of these
connections.

Wizard again.

Operation
Processor




Status LEDs
Processor LEDs

present
LED Status

ATTN
or module.
ATTN
every 4 sec

The PTCC input board accepts 12 signals at mV levels from the thermocouples
wired to the terminal board. The analog input section consists of six differential
multiplexers, a main multiplexer, and a 16-bit analog to digital converter that sends
the digital data to the adjacent processor board. Each input has hardware and
firmware filters, and the converter samples at up to 120 Hz.
Type E, J, K, S, and T thermocouples can be used with PTCCH1, and they can be grounded
or ungrounded. Type E, J, K, S, T, B, N and R thermocouples can be used with PTCCH2,
and they can be grounded or ungrounded. Thermocouples can be located up to 300 meters
(984 feet) from the turbine I/O panel with a maximum two-way cable resistance of 450 Ω.
Linearization for individual thermocouple types is performed in software by the I/O

pack board. A thermocouple, which is determined to be out of the hardware limits, is
removed from the scanned inputs in order to prevent adverse affects on other input
channels. If two packs are used, and both Cold Junction (CJ) devices are within the
configurable limits, then the average of the two is used for CJ compensation.
BPTCH1A TC Input Board

From
Terminal
Board
TC1
Differential Multiplexors (6)
TC2
TC3
Multiplexor
A/D To
. . Converter Processor board
Thermocouple 16-bit
.
Inputs
. .
. .
ID
TC12
Cold
Junction
reference
ID

Thermocouple Limits
TBTC with PTCCH1 or VTCC
Thermocouple inputs support a full-scale input range of -8.0 mV to + 45.0 mV.

The following table shows typical input voltages for different thermocouple types
versus the minimum and maximum temperature range. The CJ temperature is
assumed to range from -30 to 65°C (-22 to +149 °F).
The units (°C or °F) are based

on the ThermCplUnit settings.
Thermocouple Type PTCCH1 E J K S T
See section ThermCplUnit
Parameter Low range, °F -60 -60 -60 0 -60
°C -51 -51 -51 -17.78 -51
mV at low range with reference -7.174 -6.132 -4.779 -0.524 -4.764
at 70°C (158 °F)
High range, °F 1100 1400 2000 3200 750
°C 593 760 1093 1760 399
mV at high range with reference 44.547 42.922 44.856 18.612 20.801
at 0°C (32 °F)
TBTC with PTCCH2
Thermocouple inputs support a full-scale input range of -20.0 mV to + 95.0 mV.

The following table shows typical input voltages for different thermocouple types
versus the minimum and maximum temperature range. The CJ temperature is
assumed to range from -30 to 65°C (-22 to +149 °F).
Thermocouple Type PTCCH2 E J K S T

Low range, °F -60 -60 -60 0 -60
°C -51 -51 -51 -17.78 -51
mV at low range with reference -7.174 -6.132 -4.779 -0.524 -4.764
at 70°C (158 °F)
High range, °F 1832 2192 2372 3200 752
°C 1000 1200 1300 1760 400
mV at high range with reference 76.373 69.553 52.41 18.612 20.869
at 0°C (32 °F)
Thermocouple Type PTCCH2 B N R

Low range, °F 32 -60 0
°C 0 -51 -17.78
mV at low range with reference at 70°C -0.0114 -3.195 -0.512
(158 °F)
High range, °F 3272 2282 3092
°C 1800 1250 1700
mV at high range with reference at 0°C (32 13.593 45.694 20.220
°F)

Cold Junctions
The units (°C or °F) are based The CJ signals go into signal space and are available for monitoring. Normally
on the ThermCplUnit settings. the average of the two is used. Acceptable limits are configured, and if a CJ
See section ThermCplUnit goes outside the limit, a logic signal is set. A 1 °F error in the CJ compensation
Parameter will cause a 1 °F error in the thermocouple reading.
Hard-coded limits are set at -40 to 85°C (-40 to +185 ºF), and if a CJ goes
outside this, it is regarded as bad. Most CJ failures are open or short circuit.
If the CJ is declared bad, the backup value is used. This backup value can be
derived from CJ readings on other terminal boards, or can be the configured
default value (refer to signals in the section, Configuration).
ID Line
Power Management

Specifications
Item Specification
Number of channels 12 channels per pack
Thermocouple types E, J, K, S, T thermocouples, and mV inputs for PTCCH1
E, J, K, S, T, B, N, R thermocouples, and mV inputs for PTCCH2
Span -8 mV to +45 mV for PTCCH1
-20 mV to +95 mV for PTCCH2
A/D converter Sampling type 16-bit A/D converter
Cold junction compensation Reference junction temperature measured in each module
TMR board has three cold junction references
Cold junction temperature accuracy Cold junction accuracy 1.1ºC (2 ºF)
Conformity error Maximum software error 0.14ºC (0.25 ºF)
Measurement accuracy PTCCH1 = 53 µV (excluding cold junction reading).
RSS error= 3 °F
PTCCH2 = 115 µV (excluding cold junction reading).
RSS error= 6 °F
Common mode rejection AC common mode rejection 110 dB at 50/60 Hz, for balanced impedance input.
Both hardware and firmware filtering
Common mode voltage ±5 Volts
Normal mode rejection Rejection of 250 mV rms at 50/60 Hz, ±5%,
Both hardware and firmware filtering provides a total of 80 dB NMRR
Scan time All inputs are sampled at up to 120 times per second per input
High/low system (software) limit check
Monitor readings from all TCs, CJs, calibration voltages, and calibration zero
readings

Diagnostics
• A power-up self-test that includes checks of RAM, flash memory,

Ethernet ports, and processor board hardware
• A comparison is made between the commanded state of each relay drive
and the feedback from the command output circuit.
• Relay board specific feedback is read by the pack and processed. The
information varies depending n the relay board type. Refer to relay terminal
board documentation for feedback specifics.
• Continuous monitoring of multi-cast communications with a PGEN pack
if the PDOA has been configured for “IO module trip from” a PGEN
for the power load unbalance (PLU) function.
Details of the individual diagnostics are available in the ToolboxST application.

the RESET_DIA signal if they go healthy.

Configuration

PTCC_Mod_Config
SysFreq System Frequency (used for noise rejection) 60Hz, 50Hz
SystemLimits Enable or Disable All System Limit Checking Disable, Enable
AutoReset Automatic restoring of thermocouples removed Disable, Enable
from scan
PTCC Point Config
Thermocouple01 First of 24 thermocouples, point signal Point Edit (Input FLOAT)
Thermocouple12
ThermCplType Select thermocouples type or mV input For PTCCH1- Unused, mV, T,K,J,E, or S
Unused inputs are removed from scanning. The For PTCCH2- Unused, mV, T,K,J,
mV inputs are primarily for maintenance, but can E,S,B,N, or R
also be used for custom remote CJ compensation.
Standard remote CJ compensation is also
available.
ThermCplUnit Select thermocouples display unit in °C or °F. This
value needs to match units of attached variable.
See section ThermCplUnit Parameter.
ReportOpenTC H1A is not available. H2A can select open Fail_Cold, Fail_Hot
thermocouple to be reported on either Failed_Hot
or Failed_Cold
LowPassFiltr Enable 2 Hz low pass filter Enable, Disable
SysLimit1 System Limit 1 in °C, °F, or mV -450 to 3500 (FLOAT)
SysLim1Enabl Enable system limit 1 fault check , a temperature Enable, Disable
limit which can be used to create an alarm.
SysLim1 Latch Latch system limit 1 fault NotLatch, Latch
unlatch; reset used to unlatch
SysLim1Type System limit 1 check type limit occurs when the >=, <=
temperature is greater than or equal (>=), or less
than or equal to (<=) a preset value
SysLimit2 System Limit 2 in °C, °F, or mV -450 to 3500 (FLOAT)
SysLim2 Enabled Enable system limit 2 fault check , Enable,
a temperature limit which can be used to create Disable
an alarm.

SysLim2Latch Latch system limit 2 fault NotLatch, Latch
unlatch; reset used to unlatch >=, <=
System limit 2 check type limit occurs when the
temperature is greater than or equal (>=), or less
than or equal to (<=) a preset value
SysLim2Latch
TMR_DiffLimt Diagnostic limit, TMR input vote difference in -450 to 3500 (FLOAT)
engineering units
Limit condition occurs if three temperatures in R,
S, T differ by more than a preset value (ºF); this
creates a voting alarm condition.
PTCC_CJ_Config Cold junction reference similar configuration as for
thermocouples but no low pass filter
ColdJuncType Select CJ Type Remote, Local
ColdJuncUnit Select TC Display Unit Deg °C or °F. Value needs Deg_F, Deg_C
to match units of attached variable
SysLimit1 System Limit 1 - Deg °F or Deg °C -40 to 185 (FLOAT)
SysLim1Enabl Enable System Limit 1 Fault Check Disable, Enable
SysLim1Latch Latch System Limit 1 Fault NotLatch, Latch
SysLim1Type System Limit 1 Check Type ( >= or <;= ) >;=, <;=
SysLimit2 System Limit 2 - Deg °F or Deg °C -40 to 185 (FLOAT)
SysLim2Enabl Enable System Limit 2 Fault Check Disable, Enable
SysLim2Latch Latch System Limit 2 Fault NotLatch, Latch
SysLim2Type System Limit 2 Check Type ( >;= or < ) >=, <;=
TMR_DiffLimt Diag Limit, TMR Input Vote Difference, in Eng -450 to 3500 (FLOAT)
Units

L3DIAG_PTCC_R I/O Diagnostic Indication Input BIT
L3DIAG_PTCC_S I/O Diagnostic Indication Input BIT
L3DIAG_PTCC_T I/O Diagnostic Indication Input BIT
LINK_OK_PTCC_R I/O Link Okay Indication Input BIT
LINK_OK_PTCC_S I/O Link Okay Indication Input BIT
LINK_OK_PTCC_T I/O Link Okay Indication Input BIT
ATTN_PTCC_R I/O Attention Indication Input BIT
ATTN_PTCC_S I/O Attention Indication Input BIT
ATTN_PTCC_T I/O Attention Indication Input BIT
PS18V_PTCC_R I/O 18 V Power Supply Indication Input BIT
PS18V_PTCC_S I/O 18 V Power Supply Indication Input BIT
PS18V_PTCC_T I/O 18 V Power Supply Indication Input BIT
PS28V_PTCC_R I/O 28 V Power Supply Indication Input BIT

PS28V_PTCC_S I/O 28 V Power Supply Indication Input BIT
PS28V_PTCC_T I/O 28 V Power Supply Indication Input BIT
IOPackTmpr_R IO Pack Temperature (deg °F) AnalogInput FLOAT
IOPackTmpr_S IO Pack Temperature (deg °F) AnalogInput FLOAT
IOPackTmpr_T IO Pack Temperature (deg °F) AnalogInput FLOAT
SysLim1TC1 System limit 1 for thermocouple 1 Input BIT
↓ ↓ ↓ ↓
SysLim1CJ1 System limit 1 for cold junction 1 Input BIT
↓ ↓ ↓ ↓
SysLim2CJ1 System limit 1 for cold junction 2 Input BIT
CJBackup Backup Cold Junction Temperature (°F or °C based on Cold AnalogOutput FLOAT
Junction configuration)
CJRemote1 Remote Cold Junction Temperature. Used when Cold Junction AnalogOutput FLOAT
set to Remote (°F or °C based on Cold Junction configuration)
ThermCplUnit Parameter

to this parameter.

TBTC Thermocouple Input
The Thermocouple Input (TBTC) terminal board accepts 24-type E, J, K, S, or T
thermocouple inputs. It accepts additional B, N and R types of thermocouple inputs only
when used with PTCCH2 in Mark VIe control system. These inputs are wired to two
barrier-type blocks on the terminal board. TBTC communicates with the I/O processor
through DC-type connectors. Two types of the TBTC are available, as follows:
• TBTC1C for simplex applications has two DC-type connectors.

• TBTC1B for TMR applications has six DC-type connectors.
TBTCH1C or TBTCS1C Terminal Board TBTCH1B or TBTCS1B Terminal Board

Simplex TMR
x x
x TBTCH1C or TBTCS1C, x TBTCH1B or TBTCS1B,
2
x 1 x 1 JTA JTB
x capacity for x 2 capacity for
x 4
x 3 x 4
x 3
x 5 24 thermocouple x 5 24 thermocouple
12 TC x 6 x 6
x 7 inputs x 7 inputs (with Packs
Inputs x 8 x 8
x 9 x 9 only 12 inputs)
x 10 x 10
x 12
x 11 x 12
x 11
x 13 x 13
x 14 x 14
x 16
x 15 x 16
x 15
x 18
x 17 J ports: x 18
x 17
20
x 19 JA1 20
x 19
x x JSA JSB
x 22
x 21 Plug in I/O pack(s) x 22
x 21
x 24
x 23 x 24
x 23
x x
or
x x
x 26
x 25 Cables to boards x 26
x 25
x 28
x 27 for Mark VI control x 28
x 27
x 29 x 29
12 TC x 30 x 30
32
x 31 32
x 31
Inputs x
x 33
JB1 For TBTCH1B or
x
x 33
JRA JRB
x 34 x 34
x 35 TBTCS1B the number x 35
x 36 and location of I/O points x 36
x 38
x 37 x 38
x 37
x 39 depends on the level of x 39
x 40 redundancy required. x 40
x 42
x 41 x 42
x 41
x 44
x 43 x 44
x 43
x 46
x 45 x 46
x 45
x 48
x 47 x 48
x 47
x x
x x
Shield Bar BarrierType Terminal Shield Bar BarrierType Terminal

Ground Blocks can be unplugged Ground Blocks can be unplugged
from board for from board for
maintenance maintenance
Thermocouple Terminal Board, I/O Processor, and Cabling

Control System TBTC Functionality

Mark VI control TBTC works with the VTCC processor and supports simplex and TMR applications.
One TBTCH1C connects to the VTCC with two cables. In TMR systems, TBTCH1B
connects to three VTCC boards with six cables.
Mark VIe control In the Mark VIe system, TBTC works with the PTCC I/O pack and supports simplex,
dual, and TMR applications. In simplex systems, two PTCC packs plug into the
TBTCH1C for a total of 24 inputs. With the TBTCH1B, one, two, or three PTCC packs
can be connected, supporting a variety of system configurations.
Simplex pack 12 inputs
Simplex packs 24 inputs
TMR packs 12 inputs
TBTC accepts 24-type E, J, K, S, or T thermocouple inputs for PTCCH1 pack and
24-type E, J, K, S, T, B, N, or R thermocouple inputs for PTCCH2 pack.
Mark VIeS control Board revisions TBTCS1B and TBTCS1C are safety certified.
Support of 24 thermocouple inputs on TBTC requires the use of two YTCC packs.
Board Revision Mark VI control Mark VIe control Mark VIeS Safety Comments
IS200VTCC IS220PTCC control IS200YTCC
TBTCH1A Yes, all versions No No Use TBTCH1B as replacement
TBTCH1B Yes, all versions Yes, all versions No TMR capable
TBTCH1C Yes, all versions Yes, all versions No Simplex applications
TBTCS1B No Yes, all versions Yes, all versions TMR capable, safety certified
TBTCS1C No Yes, all versions Yes, all versions Simplex applications, safety
certified
Installation
Connect the thermocouple wires directly to the two I/O terminal blocks. These removable
blocks are mounted on the terminal board and held down with two screws. Each block
has 24 terminals accepting up to #12 AWG wires. A shield terminal strip attached
to chassis ground is located on the left side of each terminal block.
Mark VI control system Cable the TBTC J-type connectors to the I/O processors
in the VME rack.
Mark VIe / VIeS control Plug the I/O packs directly into the TBTC J-type connectors.
systems The number of cables or I/O packs depends on the level of

Operation
Simplex
Mark VI control system For simplex systems using TBTCH1C, one VTCC is used.
Mark VIe /VIeS control For simplex systems, two I/O packs plug into TBTC,
systems obtaining 24 thermocouple inputs.
Termination Board Thermocouple I/O Processor

TBTCH1B or TBTCS1B <R>
JRB Excitation.
ID I/O Processor is either
Cold Junc. remote (Mark VI control)
Refer.
Thermocouple High or
local (Mark VIeS)
Low NS
Grounded or Noise JSB

ungrounded Suppression ID
A/D Processor
(12) thermocouples Conv.
JTB
ID
JRA
ID
Cold Junc.
Refer.
Thermocouple High
Low NS
Grounded or JSA
ungrounded ID
(12) thermocouples
Other selected J-ports cable to I/O
processor board for Mark VI control systems,
or
I/O packs for Mark VIeS control systems,
JTA for <S> and <T>.
ID
Thermocouple Inputs and I/O Processor, Simplex

TMR
For TMR systems using TBTCH1B / TBTCS1B, the thermocouple signals fan out to
three J-connectors. The Mark VI control system accommodates 24 inputs. The Mark
VIe/VIeS control systems accommodate 12 inputs. The TBTC terminal board supports
all thermocouple spans documented for the associated thermocouple I/O processor.
Termination Board Thermocouple I/O Processor

TBTCH1B or TBTCS1B <R>
JRB Excitation.
ID I/O Processor is either
Cold Junc. remote (Mark VI) or
Refer. local (Mark VIe)
Thermocouple High
Low NS
Grounded or Noise JSB

ungrounded Suppression ID
A/D Processor
(12) thermocouples Conv.
JTB
ID
JRA
ID
Cold Junc.
Refer.
Thermocouple High
Low NS
Grounded or JSA
ungrounded ID
(12) thermocouples
Other selected J-ports cable to I/O
Processor Board for Mark VI systems,
or
I/O Packs for Mark VIe,
JTA for <S> and <T>.
ID
Thermocouple Inputs and I/O Processor, TMR systems

Thermocouple Limits
Thermocouple inputs support full-scale input ranges. The following tables display
typical input voltages for different thermocouple types versus the minimum
and maximum temperature range. Cold junction (CJ) temperature ranges are
assumed to be from -30 to 65°C (-22 to 149 °F).
TBTCH1 and TBTCS1
Thermocouple Type E J K S T
Low range, °F -60 -60 -60 0 -60
°C -51 -51 -51 -17.78 -51
mV at low range with reference at 70°C (158 -7.174 -6.132 -4.779 -0.524 -4.764
°F)
High range, °F 1100 1400 2000 3200 750
°C 593 760 1093 1760 399
mV at high range with reference at 0°C (32 °F) 44.547 42.922 44.856 18.612 20.801
TBTC with PTCCH2
Thermocouple Type PTCCH2 B E J K N R S T

Low range, °F 32 -60 -60 -60 -60 0 0 -60
°C 0 -51 -51 -51 -51 -17.78 -17.78 -51
mV at low range with reference -0.0114 -7.174 -6.132 -4.779 -3.195 -0.512 -0.524 -4.764
at 70°C (158 °F)
High range, °F 3272 1832 2192 2372 2282 3092 3200 752
°C 1800 1000 1200 1300 1250 1700 1760 400
mV at high range with reference 13.593 76.373 69.553 52.41 45.694 20.220 18.612 20.869
at 0°C (32 °F)
Cold Junctions
The CJ signals go into signal space and are available for monitoring. Normally
the average of the two is used. Acceptable limits are configured, and if a CJ
goes outside the limit, a logic signal is set. A 1 °F error in the CJ compensation
will cause a 1 °F error in the thermocouple reading.
Hard-coded limits are set at -40 to 85°C (-40 to +185 ºF), and if a CJ goes outside this,
it is regarded as bad. Most CJ failures are open or short circuit. If the CJ is declared
bad, the backup value is used. This backup value can be derived from CJ readings
on other terminal boards, or can be the configured default value.

Specifications
Item Specification
Number of channels 24 channels per terminal board
Thermocouple types E, J, K, S, T thermocouples, and mV inputs if TBTC is connected to PTCCH1 /
VTCCH1
E, J, K, S, T, B, N ,R thermocouples, and mV inputs if TBTC is connected to

PTCCH2 / VTCCH2
Span -8 mV to +45 mV if TBTC is connected to PTCCH1 / VTCCH1
-20 mV to +95 mV if TBTC is connected to PTCCH2 / VTCCH2

Cold junction compensation Reference junction temperature measured at two locations on each H1C / S1C
terminal board.
TMR H1B board has six CJ references. Only three available with packs.
Cold junction temperature accuracy CJ accuracy 1.1ºC (2 ºF)
Monitor readings from all TCs, CJs, calibration voltages, and calibration zero
readings.
Diagnostics
• Each thermocouple type has hardware-limit checking (HLC) based on preset

(non-configurable) high and low levels set near the ends of the operating range. If
this limit is exceeded, a logic signal is set and the input is no longer scanned. If any
one of the inputs hardware limits is set, it creates a composite diagnostic alarm.
I/O board. The board ID is coded into a read-only chip containing the terminal
board serial number, board type, revision number, and the J connector location. If
• When operating with the I/O processor a very small current is injected into each
thermocouple path. This is done to detect open circuits and is of a polarity to
create a low temperature reading should a thermocouple open.
Configuration

STTC Simplex Thermocouple Input
The Simplex Thermocouple Input (STTC) terminal board is a compact terminal board
designed for DIN-rail or flat mounting. The board has 12 thermocouple inputs and
connects to the PTCC thermocouple processor board or to the YTCC pack on the
Mark VIeS SIS. The on-board signal conditioning and cold junction reference is
identical to those on the larger TBTC board. High-density Euro-Block type terminal
blocks are mounted to the board, and two types are available. An on-board ID chip
identifies the board to the processor for system diagnostic purposes.
Control System STTC Functionality

Mark VIe control PTCC I/O pack works with the STTC. The I/O pack plugs into
the DC-37 pin connector and communicates with the controller
Mark VIeS control Board revisions STTCS1A and STTCS2A are safety certified.
Board Revision Mark VIe control Mark VIeS Safety control Comments
IS220PTCC IS200YTCC
STTCH1A Yes, all versions No Fixed terminals
STTCH2A Yes, all versions No Plug in terminals
STTCS1A Yes, all versions Yes, all versions Fixed terminals, safety certified
STTCS2A Yes, all versions Yes, all versions Plug in terminals, safety certified

Installation
Shield screws are provided The STTC and a plastic insulator mount on a sheet metal carrier, which mounts on a DIN
on this board, internally rail. The STTC and insulator mount on a sheet metal assembly that bolts directly in a
connected to SCOM. panel. Thermocouples are wired directly to the terminal block using typical #18 AWG
wires. The Euro-block type terminal block has 42 terminals that can be fixed or removable.
Note Shield screws are provided on this board, internally connected to SCOM.
E1
Screw Connections Screw Connections
TB1 DC-37 pin
1 Input 1 (+) connector with latching
Input 1 (-) 2
3 Shield fasteners
Shield 4 JA1
5 Input 2 (+)
Input 2 (-) 6 7 Input 3 (+)
Input 3 (-) 8
9 Shield JA1
Shield 10
11 Input 4 (+)
Input 4 (-) 12
13 Input 5 (+) Plug in I/O Pack
Input 5 (-) 14
15 Shield
Shield 16
17 Input 6 (+)
Input 6 (-) 18 or
19 Input 7 (+)
Input 7 (-) 20
21 Shield
Shield 22 cable to
23 Input 8 (+)
Input 8 (-) 24
25 Input 9 (+) I/O Processor Board
Input 9 (-) 26
Shield 27 Shield
28
29 Input 10 (+)
Input 10 (-) 30
31 Input 11 (+)
Input 11 (-) 32
33 Shield
Shield 34
35 Input 12 (+)
Input 12 (-) 36
37 NC
NC 38
39 NC
NC 40 Shield
Shield 41
42
Euro-Block type E2 SCOM (Chassis Ground)

terminal block
Plastic insulator
and metal carrier
DIN-rail mounting option
STTC Thermocouple Terminal Board
Note Shields should be terminated on designated terminals on TB1.
Two types of Euro-Block terminal blocks are available as follows:
• Terminal board STTCH1 and STTCS1 has a permanently mounted

terminal block with 42 terminals.
• Terminal board STTCH2 and STTCS2 has a right-angle header accepting a range of
commercially available plugged terminal blocks, with a total of 42 terminals.
Note E1 and E2 are holes for chassis grounding screws.

Operation
Connection of the STTC to the I/O pack or board that contains the A/D converter is
displayed in the following figure. The I/O pack or board provides excitation for the cold
junction (CJ) reference on the terminal board. The 12 thermocouple signals plus the CJ
signal and the connection to the identity chip (ID) come through connector JA1.
STTC Terminal Board

I/O Pack
Local CJ Excitation
JA1
reference (1)
Remote CJ
references
Thermocouple Noise Suppression

1 Pos
2 Neg NS A/D Processor
3 Shld
Grounded or
ungrounded SCOM
(12) thermocouples
A/D converter
ID
Plug in pack
or
cable to board
STTC and I/O Processor

Specifications
Item Specification
Number of channels 12 channels per terminal board
Thermocouple types E, J, K, S, T thermocouples, and mV inputs if STTC is connected to PTCCH1
E, J, K, S, T, B, N, R thermocouples, and mV inputs if STTC is connected to
PTCCH2
Span -8 mV to +45 mV if STTC is connected to PTCCH1
-20 mV to +95 mV if STTC is connected to PTCCH2
Cold junction compensation Reference junction temperature measured at one location
Cold junction temperature accuracy Cold junction accuracy -17ºC (2 ºF)
Check ID chip on JA1 connector
Diagnostics
• Each thermocouple type has hardware-limit checking based on preset

(non-configurable) high and low levels set near the ends of the operating range. If
this limit is exceeded, a logic signal is set and the input is no longer scanned. If any
one of the inputs hardware limits is set, it creates a composite diagnostic alarm.
I/O board. The board ID is coded into a read-only chip containing the terminal
board serial number, board type, revision number, and the J connector location. If
• When operating with the I/O processor a very small current is injected into each
thermocouple path. This is done to detect open circuits and is of a polarity to
create a low temperature reading should a thermocouple open.
Configuration

PTUR Turbine Specific Primary Trip
Primary Turbine Specific Primary Trip (PTUR)

TURBINE I/O The Primary Trip Protection (PTUR) pack provides the electrical interface between one
PWR or two I/O Ethernet networks and a turbine control terminal board. The pack contains a
K25
K25P ATTN
processor board common to all Mark* VIe distributed I/O packs, a board specific to the
DCT turbine control function, and an analog acquisition daughterboard. The pack plugs into
the TTURH1C terminal board and handles four speed sensor inputs, bus and generator
LINK
K1 ENET1 voltage inputs, shaft voltage and current signals, eight flame sensors, and outputs to
K2 TxRx the main breaker. Input to the pack is through dual RJ45 Ethernet connectors and a
K3 three-pin power input. Output is through a DC-62 pin connector that connects directly
LINK with the associated terminal board connector. Visual diagnostics are provided through
ENET2
TxRx
indicator LEDs.
IR PORT
As an alternative to TTURH1C, three PTUR I/O packs can be plugged directly into a
TRPAH1A terminal board. This arrangement handles four speed inputs per PTUR, or
alternately fans the first four inputs into all three PTURs. Two solid-state primary trip
relays are provided by TRPA. This arrangement does not support bus and generator
voltage inputs, shaft voltage or current signals, flame sensors, or main breaker output.
IS220PTURH1A Refer to TRPAH1A documentation for additional details.


GEH-6721L PTUR Turbine Specific Primary Trip System Guide 24-1

PTURH1A Turbine Control Pack
KTURH1A BTURH1A BPPB processor
board board board
Single or dual
Ethernet cables
TTURH1C Turbine ENET1
Terminal Board
ENET2
K25 and K25P output External 28 V dc

Speed Sensor inputs power supply
Shaft Voltage
Bus & Gen. Voltages
ENET1
ENET2
28 V dc
Three PTUR packs for

ENET1
TMR operation
One PTUR pack for ENET2
Simplex operation
28 V dc
Trip signals, 8 flame

detectors, to TRPx
Compatibility
PTURH1A is compatible with the Turbine Terminal Board TTURH1C, and
the STUR board, but not the DIN rail-mounted DTUR or other TTUR boards.
The following table gives details of the compatibility:
Terminal Board TTURH1C, TRPAH1A and H2A DTUR STURH1A

Control mode Simplex - no TMR - yes No Simplex - yes

Installation
¾ To install the PTUR I/O pack
2. Directly plug the PTUR I/O pack into the terminal board connectors.
Note The PTUR mounts directly to a Mark VIe TTURH1C terminal board. The TMR
capable terminal board has three DC-62 pin connectors for I/O packs, and can also be
used in simplex mode if only one PTUR is installed. The PTUR directly supports
all of these connections.

Wizard again.

Operation
Processor




Status LEDs
Processor LEDs

present
LED Status

ATTN
or module.
ATTN
every 4 sec

In the simplex application, up to four pulse rate signals may be used to measure turbine
speed. Circuits to convert pulse rate to digital speed are in the PTUR pack. Generator
and bus voltages are brought into PTUR for automatic synchronizing in conjunction
with the turbine controller and GE excitation system. TTUR has permissive generator
synchronizing relays and controls the main breaker relay coil 52G. Shaft voltage is
picked up with brushes and monitored along with the current to the machine case. PTUR
alarms high voltages and tests the integrity and continuity of the circuitry.
In TMR applications there are separate sets of four speed inputs for each PTUR,
R, S, and T. All other l inputs fan to the three PTUR packs. Control signals from
R, S, and T are voted before they actuate permissive relays K25 and K25P. Relay
K25A is controlled by the I/O controller and TREG boards. All three relays have
two normally open contacts in series with the breaker close coil.
Generator Breaker 52G

feedback
a
TTURH1C Terminal Board PTUR Terminal Board TTURH1C 02 01
(input portion) Turbine Pack (continued)
PR3
Gen. 17 suppression P3 P3 PR3
GENH
volts
120 V ac NS MUX
from PT GENL 18 28Vdc
A/D
TMR JP1
SMX
Bus K25P
BUSH 19
volts RD Sync Perm
Ac&Dc
120 Vac NS Mon
20 Shaft test
from PT BUSL TMR
SMX
JP2
To Trip K25
SPRO solenoids RD Auto Sync
SVH
21 Mon
Flame
175V NS sensors K25A
SVL 22 Sync.check
from PPRO
Pulse
Shaft Rate
Mon
SCH 23 itor
14V NS
24 JR4 J8
SCL
08 06,7 05 04 03
TTL1_R
5 (TB3)
Machine case B M A
)
MPU1RH 41 K A U
#1 Primary Filter 8 flame
Magnetic NS Clamp To R N T
MPU1RL 42 AC sensors and
Speed PU Coupling K25A H O
6 (TB3)
3 trip signals
TTL2_R to TRPX P125Gen
)
MPU2RH 43 Filter
#2 Primary
Clamp
Magnetic NS AC
MPU2RL 44 Note 1: TTL option only
Speed PU Coupling
available on first two 52G
45 Speed pickups.
#3 Primary Filter b
Clamp
Magnetic NS AC Note 2: An external normally
46
Speed PU Coupling
closed auxiliary breaker Breaker coil
47 contact must be provided in
#4 Primary Filter
Clamp the breaker close coil circuit
Magnetic NS AC N125Gen
48 as indicated.
Speed PU Coupling
Note 3: Signal to K25A
comes from TREG/PPRO
PTUR with TTURH1C Terminal Board, Simplex System

Speed Pickups
The median speed signal is used An interface is provided for four passive, magnetic speed inputs with a frequency
for speed control and for the range of 2 to 20,000 Hz. Using passive pickups on a sixty-tooth wheel, circuit
primary overspeed trip signal. sensitivity allows detection of 2-RPM turning gear speed to determine if the turbine
is stopped (zero speed). If automatic turning gear engagement is provided in the
turbine control, this signal initiates turning gear operation.
Pulse rate inputs can be configured for a variety of applications. Flow types are used for
flow divider fuel flow measurements. Speed type is used for normal single shaft turbines.
Speed high type provides extended speed range above the standard speed type. Speed LM
type is designed for LM applications. Speed_HSNG type is used for applications where
compensation for inconsistent tooth spacing on the speed wheel is desired. This pulse
rate type will map the spacing of the teeth on the speed wheel in order to remove this
periodic variation from speed measurements. Mapping locked status bits (HSNGn_Stat)
are in signal space so that the mapping status of the algorithm can be observed. If the
status indicator for a pulse rate input is false, then the mapping algorithm sees too
much variation in the tooth-tooth measurements to lock onto the tooth geometry. The
Lock_Limit parameter can be adjusted in 1% increments to allow for more tooth-to-tooth
variation per revolution caused by some of the following issues: magnetized speed wheel,
electro-magnetic interference from outside sources and improper wiring or shielding
practices. Increasing the Lock_Limit value will allow the next generation speed algorithm
to stay locked with increased variation. Warning: The cost for opening the Lock_Limit
will allow for more speed variation. If the speed variation is too high when opening up the
Lock_Limit, go to the source of the problem as listed above and correct the issue there.
The primary overspeed trip calculations are performed in the controller using
algorithms similar to (but not the same as) those in the PPRO protection board.
The fast trip option used on gas turbines runs in PTUR.

52Ga
Generator Breaker
Feedback
Terminal Board TTURH1C PTUR R Terminal Board TTURH1C 02 01
(input portion) (continued)
B52GH
B52GL
Noise
P3 P3 PR3
PR3
GENH 17 Suppression MUX
Gen. Volts 28 V dc
120 Vac NS
GENL 18 A/D JP1 TMR
from PT
SMX
Trip K25P
signals 2 RD Sync
BUSH 19
PS3 3 Permissve
Bus Volts To PS3
120 Vac NS Flame TMR
20 S JP2
from PT BUSL sensors SMX
K25
To From 2
RD Auto Sync
SPRO Ac & Dc <S> 3
PT3
SVH 21
PT3 Shaft test
175V To K25A
NS
SVL 22 T From Sync check
<T> from PPRO
Pulse
Shaft Rate JR4
SCH 23 Mon
JS4 itor
14V NS
SCL 24 JT4
5 (TB3) PR3 08 07 06 05 04 03
Machine Case TTL1R contin J8
)
MPU1RH 41
BKRH
#1 Primary
AUTO
MAN
Filter
Clamp
Magnetic NS AC S Trips to TRPX,
MPU1RL 42
Speed PU Coupling
PTUR R, S, T,
4 Circuits*
3 (TB3) PS3 and Flame P125Gen
TTL1S Detector inputs
contin
)
MPU1SH 33
#2 Primary Filter
52Gb
Magnetic Clamp P3
NS AC
Speed PU MPU1SL 34 Coupling
4 Circuits*
Bkr Coil
1 (TB3) PT3
TTL1T
contin T
)
MPU1TH 25 PTUR N125Gen

#3 Primary Filter
Clamp
Magnetic NS AC
Speed PU MPU1TL 26 Coupling
4 Circuits*
P3
Note 1: TTL option only available on the first

two circuits of each group of 4 pickups.
PTUR Packs with TTURH1C Terminal Board, TMR System

Primary Trip Solenoid Interface
The normal primary overspeed trip is calculated in the controller and passed to the PTUR
and then to the chosen primary trip terminal board . TRPx contains relays for interface
with the electrical trip devices (ETD). TRPx typically works in conjunction with an
emergency trip board (TREG) to form the primary and emergency sides of the interface to
the ETDs. PTUR supports up to three ETDs driven from each TRPx/TREx combination.
There are a number of different trip boards supported by PTUR. TRPG is targeted
at gas turbine applications and works in conjunction with TREG for emergency
trip. TRPS is used for small and medium size steam turbine systems and is
controlled by the PTUR I/O pack. TRPL is intended for large steam turbine
systems and is controlled by the PTUR I/O pack for emergency trip. Additional
trip boards are being developed for other specific applications.
In support of the trip board operation, PTUR provides a number of discrete

inputs used to monitor signals such as trip relay position, synchronizing
relay coil drive, and ETD power status.
Note The reset signal applied to this function is not edge triggered. A continuously
applied reset can result in output cycling in the presence of an intermittent trip signal.
The duration of the reset should only be sufficient to allow the reset to complete and
should not be maintained.
Automatic Synchronizing
All synchronizing connections are located on the TTUR terminal board. The generator
and bus voltages are provided by two, single phase, potential transformers (PTs) with a
fused secondary output supplying a nominal 115 V rms. Measurement accuracy between
the zero crossing for the bus and generator voltage circuits is 1 degree.
Turbine speed is matched against the bus frequency. The generator and bus voltages are
matched by adjusting the generator field excitation voltage from commands sent between
the turbine controller and the excitation controller over the Unit Data Highway (UDH). A
command is given to close the breaker when all permissions are satisfied. The breaker
is predicted to close within the calculated phase/slip window. Feedback of the actual
breaker closing time is provided by a 52G/a contact from the generator breaker (not an
auxiliary relay) to update the database. An internal K25A sync check relay is provided
on the TTUR; the independent backup phase/slip calculation for this relay is performed
in the protection module. Diagnostics monitor the relay coil and contact closures
to determine if the relay properly energizes or de-energizes upon command.

Synchronizing Modes
There are three basic synchronizing modes: Off, Manual, and Auto. Traditionally, these
modes are selected from a generator panel mounted selector switch:
Off - The breaker cannot be closed by the controller. The check relay will not
pick up. Manual - The operator initiates breaker close, which is still subject to the
K25A Sync Check contacts driven by the PPRO I/O pack or IS215VPRO board.
The manual close is initiated from an external contact on the generator panel,
normally connected in series with a sync mode in manual contact. Auto - The
system automatically matches voltage and speed, and then closes the breaker
at the right time to hit top dead center on the synchroscope. All three of the
following functions must agree for this closure to occur:
• K25A - sync check relay, checks the allowable slip/phase window, from
the PPRO I/O pack or IS215VPRO board
• K25 - auto sync relay, provides precision synchronization, from
the PTUR I/O pack or VTUR board
• K25P - sync sequence permissive, checks the turbine sequence status,
from the PTUR I/O pack or VTUR
The K25A relay should close before the K25 or else the sync check function will interfere
with the auto sync optimizing. If this sequence is not executed, a diagnostic alarm is
posted, a lockout signal is set true in signal space, and the application code may prevent
any further attempts to synchronize until a reset is issued and the correct coordination is
set up. Details of the various checks are discussed in the following sections.
Hardware
The synchronizing system interfaces to the breaker close coil through the
TTURH1C terminal board. Three Mark VIe relays must be picked up, plus external
permissions must be true before a, breaker can be closed.
The K25P relay is directly driven from the controller application code. In a TMR
system, it is driven from R, S, and T, using ⅔ logic voting. For a simplex system,
it may be configured by jumper to be driven from R only.
The K25 relay is driven from the PTUR auto sync algorithm, which is
managed by the controller application code. In a TMR system, it is driven
from R, S, and T, using ⅔ logic voting. Again for a simplex system, it may
be configured by jumper to be driven from R only.
The K25A relay is located on TTUR, but is driven from the PPRO sync check
algorithm, which is managed by the controller application code. The relay is driven
from PPRO, R8, S8, and T8, using ⅔ logic voting in TREG/L/S.
The sync check relay driver (located on TREG/L/S) is connected to the K25A relay
coil (located on TTUR) through cabling through J2 to TRPG/L/S. It then goes
through JR1 (and JS1, JT1) to JR4 (and JS4, JT4) on TTUR.
Both sides of the breaker close coil power bus must be connected to the TTUR board.
This provides diagnostic information and measures the breaker closure time, through
the normally open breaker auxiliary contact, for optimization.

The breaker close circuit is rated to make (close) 10 A at 125 V dc, but
to open only 0.6 A. A normally open auxiliary contact on the breaker is
required to interrupt the closing coil current.
Generator Synchronizing System

TTUR Cont'd
P28
TTURH1C R PTUR PR3 K25P
Cont’d K25 K25A
P3
T
+0.3 hz Cont’d 2/3 2/3
Generator, Slip RD RD S
PT secondary, 17 P3 (0.25 hz) P125/24 VDC
PR3
nomin. 115V ac +0.12 hz From JR4
(75 to 130 V ac), 01 03
18 (0.1 hz)
45 to 66 Hz Phase
+10 Deg K25P
Fan out Gen lag Gen lead CB_Volts_OK 04
connection PS3 02
Bus, to S
PT secondary, 19 Auto Synch K25
L52Ga
nomin. 115V ac Algorithm CB_K25P_PU 05
(75 to 130 V ac), 20 L52G
45 to 66 Hz PT3 K25A 06
S PTUR JT4 52Gb
to T CB_K25_PU 07
T PTUR
JS4
CB_K25A_PU Breaker
Close
Coil
08
JR4
N125/24 Vdc
JT1
JS1 TRPG/TRPL/TRPS
JR1
J2
J2
R8 SPRO
Generator,
PT secondary, 1 JA3
nomin. 115V ac
(75 to 130 V ac), JX1
2
45 to 66 Hz K25A
Fan out 2/3
RD
Relay
Bus, connection
PT secondary, 3 Driver
nomin. 115V ac
(75 to 130 V ac), 4
45 to 66 Hz
R8 PPRO
Sync Check
Slip Algorithm
JA1 TREG/TREL/TRES
+0.3 Hz
-10 Deg +10 Deg

Phase
-0.3 Hz
JA3 JY1
JA1
S8 PPRO S8 SPRO
JA3 JZ1
JA1
T8 PPRO T8 SPRO

Sync Check
The K25A sync check function is based on phase lock loop techniques. The PPRO
/ YPRO I/O pack or IS215VPRO board performs the calculations for this function,
but interfaces to the breaker close circuit are located on the TTUR board, not TPRO.
Limit checks are performed against adjustable constants as follows:
• Generator under-voltage
• Bus under-voltage
• Voltage error
• Frequency error (slip), with a maximum value of 0.33 Hz, typically set to 0.27 Hz
• Phase error with a maximum rotational value of 30°, typically set to 10°.
In addition, sync check arms logic to enable the function, and provides bypass logic
for dead bus closure. The sync window below is based on typical settings:
SLIP
+0.27 Hz
PHASE
-10 +10 Degrees
-0.27 Hz
Typical Sync Window
Auto Sync
The Auto Sync K25 function uses zero voltage crossing techniques. It compensates
for the breaker time delay, which is defined by two adjustable constants with logic
selection between the two (for two breaker applications). The PTUR / YTUR I/O
pack or VTUR board performs the calculations for phase, slip, acceleration, and
anticipated time lead for the breaker delay. The time delay parameter is adjusted
(up to certain limits) based on the measured breaker close time.
In addition, auto sync arms logic to enable the function, and bypasses logic to provide for
dead bus or manual closure. The auto sync projected sync window is shown below, where
positive slip indicates that the generator frequency is higher than the bus frequency.
SLIP
0.3 Hz
0.12 Hz
Gen. Lag 0 10 Gen. Lead (phase degrees)
Auto Sync Projected Window
The projected window is based on current phase, current slip, and current acceleration.
The generator must currently be lagging and have been lagging for the last 10
consecutive cycles, and projected (anticipated) to be leading when the breaker
actually reaches closure. Auto sync does not allow the breaker to close with negative
slip; speed matching typically aims at around + 0.12 Hz slip.

Synchronization Display
A special synchronization screen is available on the HMI with a real-time graphical
phase display and control pushbutton. The display items are listed in table.
Sync Display Description

Dynamic Parameters Voltages: Generator, Bus, Difference
Frequencies: Generator, Bus, Slip (difference)
Phase: Difference angle, degrees

Status Indication Mode: Sync OFF, MANUAL, AUTO
Sync Monitor: OFF, ON
Dead bus breaker: Open/close
Second breaker if applicable: Open/close
Sync permissive: K25P
Auto sync enabled

Raise/lower
Speed adjust:
Raise/lower
Voltage adjust:
Sync Permissive Gen voltage: OK/not OK
Bus voltage: OK/not OK
Gen frequency: OK/not OK
Bus frequency: OK/not OK
Difference volts: OK/not OK
Difference frequ: OK/not OK
Phase: K25, OK/not OK
K25A, OK/not OK
Limit Constants Upper and lower limits for the above permissive
Breaker Performance Diagnostics: Slow check relay
Sync relay lockup
Breaker #1 close time out of limits
Breaker #2 close time out of limits
Relay K25P trouble

Control Pushbuttons Sync monitor: ON, OFF
Speed adjust: RAISE, LOWER
Voltage adjust: RAISE, LOWER

Application Code
The application code must sequence the turbine and bring it to a state
where it is ready for the generator to synchronize with the system bus. For
automatic synchronization, the code must:
• Match speeds
• Match voltages
• Energize the sync permissive relay, K25P
• Arm (grant permission to) the sync check function (PPRO, K25A)
• Arm (grant permission to) the auto sync function (PTUR, K25)
The following illustrations represent positive slip (Gen) and negative phase (Gen).
Oscilloscope Voltage Phasors Sync Scope

V_Bus
V_Gen
time V_Bus
V_Gen,
Lagging

Automatic Algorithm Descriptions
This section describes the synchronizing algorithms in the PTUR I/O
pack, and in the PPRO I/O pack.
PTUR runs the auto sync algorithm. Its basic function is to monitor two Potential
Transformer (PT) inputs, generator and bus, to calculate phase and slip difference,
and when armed (enabled) from the application code, and when the calculations
anticipate top center, to attempt a breaker closure by energizing relay K25. The
algorithm uses the zero voltage crossing technique to calculate phase, slip, and
acceleration. It compensates for breaker closure time delay (configurable), with
self-adaptive control when enabled, with configurable limits. It is interrupt driven
and must have generator voltage to function. The configuration can manage the
timing on two separate breakers. For details, refer to the figure.
The algorithm has a bypass function, two signals for redundancy, to provide dead
bus and Manual Breaker Closures. It anticipates top dead center; therefore, it uses a
projected window, based on current phase, slip, acceleration, and breaker closure time. To
pickup K25, the generator must be currently lagging, have been lagging for the last 10
consecutive cycles, and projected (anticipated) to be leading when the breaker actually
reaches closure. Auto sync will not allow the breaker to close with negative slip. In this
fashion, assuming the correct breaker closure time has been acquired, and the sync check
relay is not interfering, breaker closures with less than 1 degree error can be obtained.
Slip is the difference frequency (Hz), positive when the generator is faster than the
bus. Positive phase means the generator is leading the bus; the generator is ahead in
time, or the right hand side on the synchroscope. The standard window is fixed and
is not configurable. However, a special window has been provided for synchronous
condenser applications where a more permissive window is needed. It is selectable
with a signal space Boolean and has a configurable slip parameter.
The algorithm validates both PT inputs with a requirement of 50% nominal amplitude
or greater; that is, they must exceed approximately 60 V rms before they are accepted
as legitimate signals. This is to guard against cross talk under open circuit conditions.
The monitor mode is used to verify that the performance of the system is correct,
and to block the actual closure of the K25 relay contacts; it is used as a confidence
builder. The signal space Input Gen_Sync_Lo will become true if the K25 contacts are
closed when they should not be closed, or if the Sync Check K25A is not picked up
before the Auto Sync K25. It is latched and can be reset with Sync_Reset.
The algorithm compensates for breaker closure time delay, with a nominal breaker
close time, provided in the configuration in milliseconds. This compensation is
adjusted with self-adaptive control, based upon the measured breaker close time. The
adjustment is made in increments of one cycle (16.6/20 ms) per breaker closure and
is limited in authority to a configurable parameter. If the adjustment reaches the limit,
a diagnostic alarm Breaker Slower/Faster than limits allows is posted.

Signal Space, Outputs;
Algorithm Inputs
PTUR Config
SystemFreq
CB1CloseTime
CB1AdaptLimt
CB1AdapEnbl Slip
+0.3 Hz
CB1FreqDiff (0.25Hz)
L3window
CB1PhaseDiff +0.12 Hz
etc. (0.1Hz) Signal Space, inputs
for Phase Algorithm Outputs
CB2_Selected +10 Deg
CB2 Gen Gen
TTUR AS_Win_Sel Lag Lead
17 GenFreq
Generator, Phase, Slip, Freq, BusFreq
PT secondary 18 Amplitude, Bkr Close GenVoltsDiff
GenFreqDiff
19 Time, Calculators
GenPhaseDiff
Bus, CB1CloseTime
PT secondary 20 Gen lagging (10) CB2CloseTime
01
L52Ga 02 L52G
Sync_Perm_AS , L83AS
AND
PT Signal Validation
L3window AND
L52G
Ckt_Bkr
Sync_Bypass1
Sync_Bypass0
AND OR L25_Command
Min close pulse

TTUR
Max(6,bkr
close time)
K25
Sync_Monitor AND
Sync_Perm
Synch_Reset
CB_Volts_OK Diagn Gen_Sync_LO
CB_K25P_PU
CB_K25_PU
CB_K25A_PU
CB_Volts_OK
CB_K25P_PU
CB_K25_PU
CB_K25A_PU
Automatic Synchronizing on PTUR

The sync check algorithm is performed in the PPRO I/O packs. Its basic function is
to monitor two Potential Transformer (PT) inputs, and to calculate generator and bus
voltage amplitudes and frequencies, phase, and slip. When it is armed (enabled) from
the application code, and when the calculations determine that the input variables
are within the requirements, the relay K25A will be energized. The above limits
are configurable. The algorithm uses the phase lock loop technique to derive the
above input variables, and has a bypass function to provide dead bus closures. The
window in this algorithm is the current window, not the projected window (as used
on the auto sync function), therefore it does not include anticipation.
The Sync Check will allow the breaker to close with negative slip. The
window is configurable for phase and slip.
The following diagnostics relating to the auto sync function are generated by PPRO:
• K25A Relay (sync check) Driver mismatch requested state. This means the I/O
controller cannot establish a current path from PPRO to the TREx terminal board.
• K25A Relay (sync check) Coil trouble, cabling to P28V on TTUR. This means the
K25A relay is not functional; it could be due to an open circuit between the TREx and
the TTUR terminal boards or to a missing P28 V source on the TTUR terminal board.

Signal Space, Outputs;
Algorithm Inputs
PPRO Config
SynchCheck used/unused
SystemFreq
FreqDiff
TurbRPM
Slip
PhaseDiff
*ReferFreq PR_Std +0.3 Hz L3window
+10 Deg
Phase Signal Space, inputs;
PR1/PR2 Algorithm Outputs
Gen Lag Gen Lead
TPRO
DriveFreq
1 center freq BusFreq
Generator, GenFreq
PT secondary 2 Phase Lock Loop GenVoltsDiff
Phase, Slip, Freq, GenFreqDiff
3 Amplitude GenPhaseDiff
Bus, Calculations
PT secondary 4
GenVolts
A L3GenVolts
GenVoltage 6.9 A>B
B
BusVolts
A L3BusVolts
BusVoltage A>B AND
6.9 B
GenVoltsDiff
A
VoltageDiff 2.8 A<B L3window AND
B
SynCk_Perm L25A_Command
OR
SynCk_Bypass
dead bus TREG/L/S
L3GenVolts AND TRPG/L/S TTUR
PTUR
*Note: L3BusVolts
"ReferFreq" is a configuration parameter, used to K25A
make a selection of the variable that is used to RD
establish the center frequency of the "Phase Lock
Loop". It allows a choise between:
(a): "PR_Std" using speed input , PulseRate1, on a
single shaft application; speed input, PulseRate2,on
all multiple shaft applications.
(b): or "SgSpace", the Generator freq (Hz), from signal
space (application code), "DriveFreq".
Choice (b) is used when (a) is not applicable.
PPRO Sync Check

PTUR Procedures
The hardware interface may be verified by forcing the three synchronizing
relays, individually or in combination. If the breaker close coil is connected
to the TTUR terminal board, then the breaker must be disabled so as not to
actually connect the generator to the system bus.
¾ To verify the hardware interface

1. Operate the K25P relay by forcing output signal Sync Perm found under PTUR,
card points. Verify that the K25P relay is functional by probing TTUR screws
3 and 4. The application code has direct control of this relay.
2. Simulate generator voltage on TTUR screws 17 and 18. Operate the K25 relay by
forcing TTUR, card point output signals Sync_Bypass1 =1, and Sync_Bypass0 = 0.
Verify that the K25 relay is functional by probing screws 4 and 5 on TTUR.
3. Simulate generator voltage on SPRO screws 1 and 2. Operate the K25A relay by
forcing SPRO, card point output signals SynCK_Bypass =1, and SynCk_Perm
1. The bus voltage must be zero (dead bus) for this test to be functional. Verify
that the K25A relay is functional by probing screws 5 and 6 on TTUR.

¾ To simulate a synchronization
1. Disable the breaker
2. Establish the center frequency of the PPRO I/O pack PLL; this depends on the
configuration, under J3:IS200TREx, signal K25A_Fdbk, ReferFreq.
a. If ReferFreq is configured PR_Std, and is configured for a single
shaft machine, then apply rated speed (frequency) to input PulseRate1;
that is SPRO screw pairs 31/32, 37/38, and 43/44.
b. If ReferFreq is configured PR_Std and is configured for a multiple
shaft machine, then apply rated speed (frequency) to input PulseRate 2,
that is SPRO screw pairs 33/34, 39/40, and 45/46.
c. If ReferFreq is configured SgSpace, force PPRO signal space output DriveRef
to 50 or 60 (Hz), depending on the system frequency.
3. Apply the bus voltage, a nominal 115 V ac, 50/60 Hz, to TTUR screws
19 and 20, and to SPRO screws 3 and 4.
4. Apply the generator voltage, a nominal 115 V ac, adjustable frequency, to TTUR
screws 17 and 18 and to SPRO screws 1 and 2. Adjust the frequency to a value giving
positive slip, that is PTUR signal GenFreqDiff of 0.1 to 0.2 Hz. (10 to 5 sec scope).
5. Force the following signals to the TRUE state:
− PTUR, Sync_Perm, then K25P should pick up

− PTUR, Sync_Perm_AS, then K25 should pulse when the voltages are in phase
− PPRO, SynCK_Perm, then K25A should pulse when the voltages are in phase
6. Verify that the TTUR breaker close interface circuit, screws 3 to 7, is being
made (contacts closed) when the voltages are in phase.
7. Run a trend chart on the following signals:
− PPRO: GenFreqDiff, GenPhaseDiff, L25A_Command, K25A_Fdbk

− PTUR: GenFreqDiff, GenPhaseDiff, L25_Command,
CB_K25_PU, CB_K25A_PU
8. Use an oscilloscope, voltmeter, synchroscope, or a light to verify that the
relays are pulsing at approximately the correct time.
9. Examine the trend chart and verify that the correlation between the
phase and the close commands is correct.
10. Increase the slip frequency to 0.5 Hz and verify that K25 and K25A
stop pulsing and are open.

Return the slip frequency to 0.1 to 0.2 Hz, and verify that K25 and K25A
are pulsing. Reduce the generator voltage to 40 V ac and verify that K25
and K25A stop pulsing and are open.
In special cases where a faster overspeed trip system is required, the VTUR
Fast Overspeed Trip algorithms can be enabled. The system employs a speed
measurement algorithm using a calculation for a predetermined tooth wheel.
Two overspeed algorithms are available as follows:
PR_Single uses two redundant VTURs by splitting up the two redundant PR

transducers, one to each board. PR_Single provides redundancy and is the
preferred algorithm for LM gas turbines.PR_Max uses one VTUR connected to
the two redundant PR transducers. PR_Max allows broken shaft and deceleration
protection without the risk of a nuisance trip if one transducer is lost.
The fast trips are linked to the output trip relays with an OR-gate. VTUR computes
the overspeed trip instead of the controller, so the trip is very fast. The time from
the overspeed input to the completed relay dropout is 30 ms or less.

Input Signal Space
Firmware
Config. Inputs
param. Scaling
Input, PR1 RPM PulseRate1
PR1Type, d RPM/sec Accel1
PR1Scale 2
PulseRate2 dt
------ Four Pulse Rate Circuits ------- RPM PulseRate2
PulseRate3 Accel1 RPM/sec Accel2
Accel2 RPM PulseRate3
PulseRate4 Accel3 RPM/sec Accel3
Accel4 RPM PulseRate4
AccelCal Type RPM/sec Accel4
Fast Overspeed Protection
FastTripType PR_Single
PulseRate1 A
PR1Setpoint A>B S FastOS1Trip
PR1TrEnable B
R
PR1TrPerm
PulseRate2 A
A>B S
PR2Setpoint B FastOS2Trip
PR2TrEnable R
PR2TrPerm
PulseRate3 A
PR3Setpoint A>B S FastOS3Trip
PR3TrEnable B
R
PR3TrPerm
PulseRate4 A
A>B S FastOS4Trip
PR4Setpoint B
PR4TrEnable R
PR4TrPerm
InForChanA Accel1
Accel2 Input AccelA
Accel3 cct. A S
Accel4 select A>B AccATrip
AccASetpoint
B R
AccelAEnab
AccelAPerm
InForChanB Accel1
Accel2 Input AccelB
Accel3 cct. A S AccBTrip
Accel4 select A>B
AccBSetpoint B R
AccelBEnab Fast Trip
AccelBPerm Path
ResetSys, VCMI, Mstr False = Run
OR
PTR1 Primary Trip Relay, normal Path, True= Run True = Run Output, J4,PTR1
AND
PTR1_Output
PTR2 Primary Trip Relay, normal Path, True= Run AND True = Run Output, J4,PTR2
PTR2_Output
PTR3 True = Run Output, J4,PTR3
PTR3_Output -------------Total of six circuits -----
PTR4 True = Run Output, J4A,PTR4
PTR4_Output Output, J4A,PTR5
PTR5 True = Run
PTR5_Output True = Run Output, J4A,PTR6
PTR6
PTR6_Output
Fast Overspeed Algorithm, PR-Single

OS1_Setpoint , SS
A
RPM
OS_Setpoint, CFG |A-B| A
(PulseRate1) OS1_SP_CfgEr (SS)
B A>B
RPM
1RPM
B
A
OS_Setpoint_PR1
MIN
B A A
MIN
Zero
( A*4% A+B
OS_Tst_Delta, CFG (PulseRate1) or B)
B OffLineOS1Tst Online_Overspeed_
B
RPM SS 1_Test
PulseRate1, IO (SS)
A
Note: For PulseRate1
A>=B
the decision to zero
OS_Setpoint_PR1
B OS1 the setpoint depends
on OnlineOS1Tst, SS
Firmware (not self- resetting) or
Overspeed
OS1 OS1_Trip OnLineOS1X, SS
Trip
(SS) (self-resetting). For
PulseRate 2 & 3 it is
OS1_Trip, (SS) L86MRX, SS only dependent on
HP Config OnLineOS#Tst, SS
Trip (not self-resetting).
OS1_SP_CfgEr, (SS) PR1_Zero, (SS) L5CFG1_Trip
(SS)
L5CFG1_Trip, (SS) L86MRX
Fast Overspeed Algorithm, PR-Max
Shaft Voltage and Current Monitor

Bearings can be damaged by the flow of electrical current from the shaft to
the case. This current can occur for several reasons:
• A static voltage can be caused by droplets of water being thrown off

the last stage buckets in a steam turbine. This voltage builds up until a
discharge occurs through the bearing oil film.
• An ac ripple on the dc generator field can produce an ac voltage on the shaft with
respect to ground through the capacitance of the field winding and insulation.
Note that both of these sources are weak, so high impedance instrumentation
is used to measure these voltages with respect to ground.
• A voltage can be generated between the ends of the generator shaft due to
dissymmetries in the generator magnetic circuits. If the insulated bearings on the
generator shaft breakdown, the current flows from one end of the shaft through the
bearings and frame to the other end. Brushes can be used to discharge damaging
voltage buildup, and a shunt should be used to monitor the current flow.
The dc test is driven from the The turbine control continuously monitors the shaft to ground voltage and current, and
R controller only. If the R alarms excessive levels. There is an ac test mode and a dc test mode. The ac test applies an
controller is down, this test ac voltage to test the integrity of the measuring circuit. The dc test checks the continuity
cannot be run successfully. of the external circuit, including the brushes, turbine shaft, and the interconnecting wire.

Flame Detectors
With the TRPG primary trip terminal board, the primary protection system monitors
signals from eight Geiger-Mueller® . With no flame present the detector charges up
to the supply voltage. The presence of flame causes the detector to charge to a level
and then discharge through the TRPG. As the flame intensity increases, the discharge
frequency increases. When the detector discharges, the primary protection system
converts the discharged energy into a voltage pulse. The pulse rate varies from 0 to
1,000 pulses/sec. These voltage pulses are fanned out to all three modules
ID Line
Power Management
Connectors

Specifications
The following table gives information specific to the PTUR.
Item PTUR Specification

Number of inputs 4 Passive speed pickups
1 Shaft voltage and 1 current measurement
1 Generator and 1 bus voltage
Generator breaker status
Eight flame detectors from TRPG
Number of outputs Automatic synchronizing control to main breaker
Primary trip solenoid interface, 3 outputs to TRPG
Speed sensor range MPU pulse rate range 2 Hz to 20 kHz
Speed sensor accuracy MPU pulse rate accuracy 0.05% of reading
Shaft voltage monitor Voltage signal is ±5 V dc pulses from 0 to 2,000 Hz
Shaft voltage dc test Applies a 5 V dc source to test integrity of the circuit. Circuit reads a differential
resistance between 0 and 150 Ω within ±5 Ω. Readings above the BrushLimit
ohms setting indicate a fault. Returned signal is filtered to provide 40 dB of noise
attenuation at 60 Hz.
Shaft voltage ac test Applies a test voltage of 1 kHz to the input of the PTUR shaft voltage circuit (R
module only).
Shaft current input Measures ac voltage up to 0.1 V pp
Generator and bus voltage sensors Two single phase potential transformers, with secondary output supplying a nominal
115 V rms.
Each input has less than 3 VA of loading. Allowable voltage range for sync is 75
to 130 V rms.
Synchronizing measurements Frequency accuracy 0.05% over 45 to 66 Hz range.
Zero crossing of the inputs is monitored on the rising slope.
Phase difference measurement is better than ±1°.
Contact voltage sensing 20 V dc indicates high and 6 V dc indicates low. Each circuit is optically isolated
and filtered for 4 ms.
Physical

Diagnostics

• ·L3BKR_GXS – the Sync Check Relay on TTUR is Slow.
• L3BKR_GES – the Auto Sync Relay on TTUR is Slow.
• Breaker #1 Slower than Adjustment Limit Allows.
• Breaker #2 Slower than Adjustment Limit Allows.
• Synchronization Trouble – the K25 Relay on TTUR Locked Up.
• Diagnostic information includes status of the solenoid relay driver, contact, high
and low flame detector voltage, and the sync relays. If any one of the signals goes
unhealthy a composite diagnostic alarm, L3DIAG_PTUR occurs.
the RESET_DIA signal if they go healthy. Details of the individual
diagnostics are available from the toolbox.

Configuration

PTUR_Mod_Cfg
System Limits Enable or disable all system limit checking Enable, disable
Redundancy Used to specify the voting mode for the card Simplex or TMR
AccelCalType Select acceleration calculation time (msec) 10 … 100
TripType Select fast trip algorithm Unused, PR_Single, PR_Max
DecelStpt Deceleration setpoint, RPM/sec 0 … 1500
Trip Type (2)
DecelEnab Deceleration enable Disable, Enable
FastOS1Stpt Fast Overspeed trip #1 setpoint, Max (PR1, PR2), RPM 0 ... 20000
FastOS1Enabl Fast Overspeed trip #1 enable Disable, Enable
FastOS2Stpt Fast Overspeed trip #2 setpoint, Max (PR3, PR4), RPM 0 ... 20000
FastOS2Enabl Fast Overspeed trip #2 enable Disable, Enable
DiffSetpoint Difference Speed trip setpoint, RPM 0 ... 20000
DiffEnable Difference Speed trip, enable Disable, Enable
PR1Setpoint Fast Overspeed trip #1, setpoint, PR1, RPM 0 .. 20000
PR1TrEnable Fast Overspeed trip #1, enable Disable, Enable
AccASetpoint Acceleration trip setpoint, Change A, RPM/sec 0 ... 1500
. . .
InForChanA Input change selection for Accel/Decel trip Accel, Accel2, Accel3, Accel4.
. . .
DiagSo1PwrA When using TRPL/S, Sol Power, Bus A, Diagnostic enable. Enable, Disable
. . .
PTUR_PR_Cfg
PRType Define the pulse rate feedback type or basic speed range. (for Flow, Speed, Speed_High,
proper resolution). See section Speed Pickups for description Speed_HSNG, Speed_LM,
of types. Unused
PRScale Pulses per revolution (outputs RPM) 0 to 1,000

Speed_x_ms Calculation rate of speed in milliseconds. Speed is calculated 10 to 1000
at this rate and averaged over the previous time interval
specified by this period.
Using a value other than an integer

multiple of the application frame period
can have adverse impact on use of this
control.
Attention
Accel_x_ms This is the averaging period for acceleration calculation 20 to 1000
in milliseconds. The acceleration is calculated every
Accel_X_ms. It is based on the difference between two speed
samples divided by the sample period. Each acceleration
calculation is the average of acceleration over the period
specified by this parameter. For example, if Accel_x_ms is 40
then acceleration will be the average acceleration over the
previous 80 ms.
Using a value other than an integer

multiple of the application frame period
can have adverse impact on use of this
control.
Attention
Lock_Limit HSNG speed type locking limit for teeth mapping (percent). 1 to 100
See section Speed Pickups for description of Lock_Limit
function.
SysLim1Enabl Enable system limit 1 fault check Enable, Disable
SysLim1Type System limit 1 check type (>= or <=) >= or <=
SysLimit1 System limit 1 - RPM 0 to 20,000
SysLim2Enabl Enable system limit 2 fault check (as above) Enable, Disable
. . .
TMRDiffLimit Diag Limit, TMR input vote difference, in Eng units 0 to 20,000
PTUR_ShV_Cfg Shaft voltage monitor
SysLim1Enabl Enable system limit 1 Enable, Disable
SysLim1Type System limit 1 check type (>= or <=) >= or <=
SysLimit1 Select alarm level in frequency Hz 0 to 100
SysLim2Enabl Select system limit 2 (as above) Enable, Disable
TMRDiffLimt Diag limit, TMR input vote difference, in Hertz 0 to 100
PTURShC_Cfg Shaft current monitor
ShuntOhms Shunt ohms 0 to 100
ShuntLimit Shunt maximum test ohms 0 to 100

BrushLimit Shaft (Brush + Shunt) maximum ohms 0 to 100
SysLim1Enable Select system limit 1 Enable, Disable
SysLim1Latch Select whether alarm will latch Latch, Not Latch
SysLim1Type Select type of alarm initiation >= or <=
SysLimit1 Current Amps, select alarm level in Amps 0 to 100
SysLim2Enable Select system limit 2 Enable, Disable
. . .
PTUR_PT_Cfg Generator potential transform
PT_Input PT primary in Eng units (kv or percent) for PT_Output 0 to 1,000
PT_Output PT output in volts rms, for PT_Input - typically 115 0 to 150
SysLim1 Select alarm level in k volts rms 0 to 1,000
SysLim2 Select alarm level in k volts rms 0 to 1,000
PTUR_CB_Cfg Circuit Breaker
System Frequency Select frequency in Hz 50 or 60
CB1CloseTime Breaker 1 closing time, ms 0 to 1,000
CB1 AdaptLimit Breaker 1 self adaptive limit, ms 0 to 1,000
CB1 AdaptEnabl Enable breaker 1 self adaptive adjustment Enable, Disable
CB1FreqDiff Breaker 1 special window frequency difference, Hz 0.15 to 0.66
CB1PhaseDiff Breaker 1 special window phase Diff, degrees 0 to 20
CB2CloseTime Breaker 2 closing time, ms (as above) 0 to 1,000
. . .
PTUR_Flm_Cfg
FlmDetTime Flame detector time interval 0.160, 0.080, 0.040 sec
FlameLimitHI Flame threshold LimitHI (HI detection cnts means LOW 0 … 160
sensitivity.
Flame_Det Flame detector used/unused Used, Unused
PTUR_Rly1_Cfg
PTR_Output Primary protection relay used/unused Unused, used
DiagVoteEnab Enable voting disagreement diagnostic Enable, Disable
PTUR_Estop_Cfg
DiagVoteEnab Enable voting disagreement diagnostic Enable, Disable
IS220PTUR Distributed I/O turbine module
Note When FlameLimHi and FlameLimLo are set to the default value of 0, flame
detection is turned off and the flame present signal FDn_Flame is always true.

PTUR Auto Sync Signal Space Interface
PTUR Signal Space Output

Sync_Perm_AS Auto sync permissive Traditionally known as L83AS
Sync_Perm Sync permissive mode, L25P Traditionally known as L25P; interface to control the K25P
relay
Sync_Monitor Auto Sync monitor mode Traditionally known as L83S_MTR; enables the Auto Sync
function, except it blocks the K25 relays from picking up
Sync_Bypass1 Auto Sync bypass Traditionally known as L25_BYPASS; to pickup L25 for
Dead Bus or Manual Sync
Sync_Bypass0 Auto Sync bypass Traditionally known as L25_BYPASSZ; to pickup L25 for
Dead Bus or Manual Sync
CB2 Selected #2 Breaker is selected Traditionally known as L43SAUTO2; to use the breaker
close time associated with Breaker #2
AS_WIN_SEL Special Auto Sync window New function, used on syncronous condenser applications
to give a more permissive window
Sync_Reset Auto Sync reset Traditionally known as L86MR_TCEA; to reset the Sync
Lockout function
PTUR Signal Space Inputs

Ckt_BKR Breaker State (feedback) Traditionally known as L52B_SEL
CB_Volts_OK Breaker Closing Coil Voltage is present Used in diagnostics
CB_K25P_PU Breaker Closing Coil Voltage is present Used in diagnostics
downstream of the K25P relay contacts
CB_K25_PU Breaker Closing Coil Voltage is present Used in diagnostics
downstream of the K25 relay contacts
CB_K25A_PU Breaker Closing Coil Voltage is present Used in diagnostics
downstream of the K25A relay contacts
Gen_Sync_LO Sync Lock out Traditionally known as L30AS1 or L30AS2; it
is a latched signal requiring a reset to clear
(Sync_Reset). It detects a K25 relay problem
(picked up when it should be dropped out) or
a slow Sync Check (relay K25A) function
L25_Comand Breaker Close Command to the K25 relay Traditionally known as L25
GenFreq Generator frequency Hz
BusFreq Bus frequency Hz
GenVoltsDiff Difference Voltage between the Generator Engineering units, kV or percent
and the Bus
GenFreqDiff Difference Frequency between the Generator Hz
and the Bus
GenPhaseDiff Difference Phase between the Generator and Degree
the Bus
CB1CloseTime Breaker #1 measured close time ms
CB2CloseTime Breaker #2 measured close time ms
GenPT_Kvolts Generator Voltage Engineering units, kV or percent

PTUR Signal Space Inputs
BusPT_Kvolts Bus Voltage Engineering units, kV or percent
J4:IS200TRPGH1A TRPG terminal board, 8 flame detectors Connected, not connected
Board Points Signals Description - Point Edit Direction Type

L3DIAG_PTUR I/O Diagnostic Indication Input BIT
LINK_OK_PTUR I/O Link Okay Indication Input BIT
ATTN_PTUR I/O Attention Indication Input BIT
ShShntTst_OK Shaft voltage monitor shunt test OK Input BIT
ShBrshTst_OK Shaft voltage brush + shunt test OK Input BIT
CB_Volts_OK L3BKR_VLT circuit breaker coil voltage available Input BIT
CB_K25P_PU L3BKR_PERM sync permissive relay picked up Input BIT
CB_K25_PU L3KBR_GES auto sync relay picked up Input BIT
CB_K25A_PU L3KBR_GEX sync check relay picked up Input BIT
Gen_Sync_LO Generator sync trouble (lockout) Input BIT
L25_Command ——– Input BIT
Kq1_Status ——– Input BIT
: : Input BIT
Kq6_Status ——– Input BIT
HSNG1_Stat Pulse rate 1 high speed next generation stability status (TRUE Input BIT
compensation)
HSNG2_Stat Pulse rate 2 high speed next generation stability status Input BIT
FD1_Flame ——– Input BIT
: : Input BIT
FD16_Flame ——– Input BIT
SysLim1PR1 ——– Input BIT
: : Input BIT
SysLim1PR4 ——– Input BIT
SysLim1SHV Ac shaft voltage frequency high L30TSVH Input BIT
SysLim1SHC Ac shaft current high L30TSCH Input BIT
SysLim1GEN ——– Input BIT
SysLim1BUS ——– Input BIT
SysLim2PR1 (same set as for Limit1 above) Input BIT
GenFreq Hz frequency Input FLOAT
BusFreq Hz frequency Input FLOAT
GenVoltsDiff KiloVolts rms-Gen Low is negative Input FLOAT
Gen Freq Diff Slip Hz-Gen Slow is negative Input FLOAT
Gen Phase Diff Phase Degrees-Gen Lag is negative Input FLOAT

Board Points Signals Description - Point Edit Direction Type
CB1CloseTime Breaker #1 close time in milliseconds Input FLOAT
CB2CloseTime Breaker #2 close time in milliseconds Input FLOAT
Accel1 RPM/SEC Input FLOAT
: : Input FLOAT
Accel4 RPM/SEC Input FLOAT
FlmDetPwr1 335 V dc Input FLOAT
ShTestAC L97SHAFT_AC SVM_AC_TEST Output BIT
ShTestDC L97SHAFT_DC SVM_DC_TEST Output BIT
FD1_Level 1 = high detection counts level Output BIT
: : Output BIT
FD16_Level 1 = high detection counts level Output BIT
Sync_Perm_AS L83AS - auto sync permissive Output BIT
Sync_Perm L25P - sequencing sync permissive Output BIT
Sync_Monitor L83S_MTR - monitor mode Output BIT
Sync_Bypass1 L25_BYP-1 = auto aync bypass Output BIT
Sync_Bypass0 L25_BYPZ-0 = auto sync permissive Output BIT
CB2_Selected L43SAUT2 - 2nd breaker selected Output BIT
AS_Win_Sel L43AS_WIN - special window selected Output BIT
Sync_Reset L86MR_SYNC - sync trouble reset Output BIT
Kq1 L20PTR1 - primary trip relay Output BIT
: : Output BIT
Kq6 L20PTR6 - primary trip relay Output BIT

TTUR_1C Primary Turbine Protection Input
The Primary Turbine Protection (TTUR) terminal board work with the VTUR board
and the PTUR / YTUR I/O packs. The inputs and outputs are as follows:
• 12 pulse rate devices sensing a toothed wheel to measure the turbine speed
• Generator voltage and bus voltage signals taken from potential transformers
• 125 V dc output to the main breaker coil for automatic generator synchronizing
• Inputs from shaft voltage and current sensors to measure induced
shaft voltage and current
• Three overspeed trip signals to the trip board
• Additional I/O signals from the trip board
TTUR has three relays, K25, K25P, and K25A, that all have to close to provide
125 V dc power to close the main breaker 52G.
The signals to PTUR / YTUR use the PR3 and JR4 connector for simplex systems. For
TMR systems, signals fan out to the PR3, PS3, PT3, JR4, JS4, and JT4 connectors.



Breaker
Generator volts TB1 x
x DC-62 and
Bus volts x 2
x 1 DC-37 pin
Shaft volts x 3
x 4 connectors
x 6
x 5
Shaft current x 7
x 8
x 9
x 10
x 11
x 12
x 14
x 13
x 15 JT4 PT3
x 16
x 18
x 17
x 19 JS4 PS3
x 20
x 22
x 21
x 24
x 23
x
Plug I/O packs
into PR3, PS3,
TB2
x and PT3
x 26
x 25
Magnetic speed x 28
x 27
x 30
x 29
pickups (12) x 31
x 32 JR4 PR3
x 34
x 33
x 36
x 35
x 37
x 38 Plug cables into
x 39
x 40 JR4, JS4, and JT4 for
x 41
x 42
x 43 TRPx trip board
x 44
x 46
x 45
x 47
J8
x 48
x
TB3 x
Wiring to To Sync
Shield bar TTL speed check relay
pickups from Proctection
Barrier type terminal Pack
TTUR Primary Turbine Protection

Control System TBAI Functionality

Mark VI control TTURH1C cannot be used with the Mark VI control system.
Use the TTURH1B terminal board.
Mark VIe control TTURH1C supports connection of TRPG, TRPS, TRPA
boards and the PTUR I/O pack. TTURH2C contains altered
internal power distribution for special applications. It is not
interchangeable with a TTURH1C.
Mark VIeS Safety Board revision TTURS1C is safety certified and required.
control
IS200VTUR IS220PTUR control IS200YTUR
TTURH1A Yes, all versions No No Use TTURH1B as replacement
TTURH1B Yes, all versions No No
TTURH1C and No Yes, all versions No
2C
TTURS1C No Yes, all versions Yes, all versions Safety certified

Installation
Pulse rate pick ups, shaft pick ups, potential transformers, and the breaker relay are wired
to the two terminal blocks TB1 and TB2. Each block is held down with two screws
and has 24 terminals accepting up to #12 AWG wires. A shield terminal strip attached
Jumpers JP1 and JP2 select either simplex or TMR for relay drivers K25 and
K25P. Removing wire jumper WJ1 isolates the K25A control line to the TRPX
board. TB3 is for optional TTL connections to active speed pickups; these devices
require an external power supply. Simplex systems use cable connectors PR3
and JR4. TMR systems use all six cable connectors.
Turbine Terminal Board

TTURH1C or TTURS1C JP1 DC-62 pin and DC-37
K1 JT4 PT3
pin connectors With
TB1 TMR SMX latching fasteners
x
x 1 P125GEN K2 JP2
52G (L) x 2
x 3 P125GEN
AUTO x 4
BKRH x 6
x 5 MAN TMR SMX
N125GEN x 8
x 7 BKRH
K3
NC x 10
x 9 NC
NC x 12
x 11 NC
NC x 14
x 13 NC
NC 16
x 15 NC
x JS4 PS3
x 17 Gen (H)
Gen (L) x 18
Bus (L)
x 19 Bus (H)
x 20
x 21 ShaftV (H)
ShaftV (L) x 22
x 23 ShaftC (H)
ShaftC (L) x 24
x Plug I/O packs
into PR3, PS3,
and PT3
TB2
x
TB3 Screw Connections
x 25 PR 1T (H)
PR 1T (L) x 26 TTL1T 01
PR 2T (L) x 28
x 27 PR 2T (H)
TTL2T 02
x 29 PR 3T (H) JR4 PR3
PR 3T (L) x 30
PR 4T (L) x 32
x 31 PR 4T (H)
x 33 PR 1S (H) TTL1S 03
PR 1S (L) x 34
x 35 PR 2S (H) TTL2S 04
PR 2S (L) x 36
PR 3S (L) x 38
x 37 PR 3S (H)
x 39 PR 4S (H) TTL1R 05 Plug cables into JR4, JS4,
PR 4S (L) x 40
PR 1R (L) x 42
x 41 PR 1R (H) TTL2R 06 and JT4 for TRPx trip board
PR 2R (L) x 44
x 43 PR 2R (H)
x 45 PR 3R (H)
PR 3R (L) x 46
x 47 PR 4R (H) 02
PR 4R (L) x 48 J8 WJ1
x 01
TB3 To Sync
x
check relay
from Protection
pack
TTUR Terminal Board Wiring

Operation
The PTUR or YTUR I/O pack plugs into TTURH1C or TTURS1C respectively,
as shown in the following figure. Either one or three I/O packs can be used.
The TRPX trip board connects to the J4 connectors.
52G
a
Generator Breaker
Feedback
Terminal Board R
(TTURH1C or TTURS1C Controller Terminal Board 02 01
(input portion) TTURH1C or TTURS1C
L H
P3 P3 PR3 (continued) G G
Noise PR3 2 2
5 5
17 Suppression B B
GENH MUX
Gen. Volts 28Vdc
120 V ac NS
GENL 18 A/D JP1 TMR
from PT
SMX
Trip K25P
signals 2 Sync.
BUSH 19 RD Permissve
PS3 3
Bus Volts To PS3
120 V ac NS Flame TMR
S JP2
from PT BUSL 20 sensors SMX
K25
To From 2
RD Auto Sync.
SPRO Ac & Dc S 3
PT3
SVH 21
PT3 Shaft test
175V To K25A
NS Sync
SVL 22 T From
check
T
from
Pulse Protection
Shaft Rate JR4 pack
SCH 23
Mon
JS4 itor
14V NS
SCL 24
JT4
5 (TB3) PR3 08 07 06 05 04 03
Machine Case TTL1R contin J8
)
PR1RH 41
#1 Primary Filter H N O
R A T
Magnetic NS Clamp S Trips to TRPX, K M U
AC B A
Speed PU PR1RL 42 Controller
Coupling R, S, T,
3
4 Circuits* and Flame P125Gen
PS3
TTL1S Detector inputs
) (TB3) contin
PR1SH 33
#2 Primary Filter 52G
Magnetic Clamp P3 b
NS AC
Speed PU PR1SL 34 Coupling
4 Circuits*
Bkr Coil
1 (TB3) PT3 T
TTL1T contin
) Controller
PR1TH 25 N125Gen
#3 Primary Filter
Clamp
Magnetic NS AC
Speed PU PR1TL 26 Coupling
Note: TTL option only available
4 Circuits* P3 on the first two circuits of each
group of 4 speed pickups*.
TTUR and Controller, TMR system
Note Passive or active Pulse rate devices can be used.

In the simplex application, up to four pulse rate signals can be used to measure turbine
speed. Generator and bus voltages are brought into TTUR for automatic synchronizing in
conjunction with PTUR or YTUR, the turbine controller, and excitation system. TTUR has
permissive generator synchronizing relays and controls the main breaker relay coil 52G.
Note All three relays have two normally open contacts in series with the breaker
close coil.
In TMR applications, all inputs, except speed, fan to the three PTUR or YTUR
packs. Control signals coming into TTUR from R, S, and T are voted before
they actuate permissive relays K25 and K25P. Relay K25A is controlled by
the PPRO or YPRO and TREG boards through J8.

Specifications
Item Specification
Number of inputs 12 passive speed pickups
1 shaft voltage and 1 shaft current measurement
1 generator and 1 bus voltage. Generator breaker status contact.
Signal to K25A relay from PPRO or YPRO
Number of outputs Generator breaker coil, 5 A at 125 V dc
Power supply voltage Nominal 125 V dc to breaker coil
Shaft voltage monitor Signal is frequency of ±5 V dc (0 – 1 MHz) pulses from 0 to 2,000 Hz
Shaft voltage wiring Up to 300 m (984 ft), with maximum two-way cable resistance of 15 Ω
Shaft voltage dc test Applies a 5 V dc source to test integrity of the external turbine circuit and
measures dc current flow.
Shaft voltage ac test Applies a test voltage of 1 kHz to the input of the PTUR shaft voltage circuit
(R module only).
Shaft current input Measures shaft current in amps ac (shunt voltage up to 0.1 V pp)
Generator and bus voltage sensors Two single phase potential transformers, with secondary output supplying a
nominal 115 V rms
Generator breaker circuits (synchronizing) External circuits should have a voltage range within 20 to 140 V dc. The
external circuit must include a NC breaker auxiliary contact to interrupt the
current. Circuits are rated for NEMA class E creepage and clearance. 250
V dc applications require interposing relays.
Contact voltage sensing 20 V dc indicates high and 6 V dc indicates low. Each circuit is optically
isolated and filtered for 4 ms.
Physical
Note Speed input sensitivity is such that turning gear speed can be observed on a

Diagnostics
• Feedback from the solenoid relay drivers is checked; if there is a problem

with the control signal a fault is created.
• Feedback from the relay contacts; if there is a problem with the
control signal a fault is created.
• Loss of solenoid power creates a fault.
• Slow sync check relay, slow auto sync relay, slow breaker, and locked
up K25 relay; all of these create a fault.
L3DIAG_PTUR or L3DIAG_YTUR occurs. The diagnostic signals can be
individually latched and then reset with the RESET_DIA signal if they go healthy.
board type, revision number, and plug location. When the chip is read by PTUR or
YTUR and a mismatch is encountered, a hardware incompatibility fault is created.
Configuration
Jumpers JP1 and JP2 select either simplex (SMX) or TMR for relay drivers K25 and
K25P. Wire jumper WJ1 is installed; removing this will isolate the K25A control
line to the TRPX board. There are no switches on the board.

TRPG Turbine Primary Trip
The Gas Turbine Primary Trip (TRPG) terminal board is controlled by the Primary
Turbine Protection I/O pack (YTUR or PTUR) or by the VTUR board. TRPG
contains nine magnetic relays in three voting circuits to interface with three trip
solenoids (ETDs). The TRPG works in conjunction with the TREG to form the
primary and emergency sides of the interface to the ETDs. TRPG also accommodates
inputs from eight Geiger-Mueller® for gas turbine applications.
ETD power
x DC-37 pin type

x
x 1 JT1 connectors
x 2 J1
x 4
x 3 with latching
Trip solenoids x 5
Power monitoring x 6 fasteners
x 8
x 7
x 10
x 9
x 12
x 11
x 14
x 13
x 16
x 15
x 17 J - Port Connections:
x 18 Cables to TTURH1C
x 20
x 19 JS1
x 21 or TTUR
x 22
x 24
x
or
x
x 25 Cables to VTURboards
x 26
x 27 for Mark VI system
x 28
x 30
x 29
Flame sensor x 31
x 32
signals (8) x 33 JR1
x 34
36
x 35
x Cable to
x 38
x 37
x 39 TREG
x 40
x 42
x 41 J2
x 44
x 43 335 V from rack
x 45 J4
Shield bar x 46 J5 power supplies
x 48
x 47
J3 R, S, T
x
x
TRPG Terminal Board and Cabling
Control System TRPG Functionality

Mark VI control TRPG works with the VTUR board and supports simplex and
TMR applications. Cables with molded plugs connect TRPG
to the VME rack where the VTUR board is located.
Mark VIe control TRPG is controlled by the PTUR packs on TTURH1C and
supports simplex and TMR applications. The I/O packs plug
into the D-type connectors on TTURH1C, which is cabled to
TRPG.
Mark VIeS Safety Board revision TRPGS1B and TRPGS2B are safety certified.
control

Board Revisions
IS200VTUR IS220PTUR control IS200YTUR
TRPGH1A Yes, all versions No Use TRPGH1B as
replacement
TRPGH2A Yes, all versions No Use TRPGH2B as
replacement
TRPGH1B Yes, all versions Yes, all versions No TMR applications, has three
voting relays per trip solenoid
TRPGH2B Yes, all versions Yes, all versions No Simplex applications
TRPGH3B Yes, all versions No No TMR, Mark VI control only,
special P28 power
TRPGS1B No Yes, all versions Yes, all versions Safety certified TMR
application, has three voting
relays per trip solenoid
TRPGS2B No Yes, all versions Yes, all versions Safety certified simplex
applications, has one relay
per trip solenoid
Version Difference
Board TMR Simplex Output contact, Output contact, 28 V Power use

125 V dc, 1 A 24 V dc, 3 A
TRPGH1A* Yes No Yes No Normal
TRPGH2A* No Yes Yes No Normal
TRPGH1B Yes No Yes Yes Normal
TRPGS1B
TRPGH2B No Yes Yes Yes Normal
TRPGS2B
TRPGH3B Yes No Yes Yes Special
* H1A and H2A are not used for new applications. TRPGH3B features special handling of 28 V control power and is
otherwise identical to a TRPG1B.

Installation
Connect the wires for the three trip solenoids directly to the first I/O terminal
block. Connect the wires for the (if used) to the second terminal block.
Connect the power for the to the J3, J4, and J5 plug.
Connect the 125 V dc power for the trip solenoids to the J1 plug. Transfer
power to the TREG board using the J2 plug.
Turbine Primary Trip Terminal Board TRPG

125 V dc
J1
JT1
x
2
x 1 125 Vdc (P)
Trip Solenoid 1 or 4 x
4
x 3 125 Vdc (P)
6
x 5 125 Vdc (P)
x 7
x 8
x 9 125 Vdc (N)
125 Vdc (N) x 10
x 12
x 14
x 13 JS1
x 15 Cables to TTURH1C or TTURS1C
x 16
x 18
x 19
x 20
x 21 or
x 22
x 23
x 24
Cables to control rack VTUR boards
x
for Mark VI system
JR1
x
x 25
x 26
x 27
x 28
x 30
x 29 J2
x 31
x 32
Flame 1 (L) x 34
x 33 Flame 1 (H)
x 35 Flame 2 (H) Cable to TREG
Flame 2 (L) x 36
x 37 Flame 3 (H)
Flame 3 (L) x 38
x 39 Flame 4 (H)
Flame 4 (L) x 40
335 V dc
Flame 5 (L) x 42
x 41 Flame 5 (H) J4
Flame 6 (L)
x 43 Flame 6 (H)
x 44 335 V dc
x 45 Flame 7 (H) J5
Flame 7 (L) x 46
x 47 Flame 8 (H) 335 V dc
Flame 8 (L) x 48 J3
x

point with 300 V insulation from terminal board for maintenance
TRPG Terminal Board Wiring

Operation
A metal oxide varister (MOV) The I/O pack/board provides the primary trip function by controlling the relays on
and a current limiting resistor TRPG, which trip the main protection solenoids. In TMR applications, the three inputs
are used in each ETD circuit. are voted in hardware using a relay ladder logic two-out-of-three voting circuit. The
I/O pack/board monitors the current flow in its relay driver control line to determine
its energize or de-energize vote/status of the relay coil contact status. Supply voltages
are monitored for diagnostic purposes. A normally closed contact from each relay on
TRPG is monitored by the diagnostics to determine its proper operation.
PDM 125 V dc + - Monitoring outputs

Terminal Board TRPG J1 01 03 05 09 10
H1A (TMR), H2A (Simplex) P125 Terminal
Trip Board TREG
JR1 N125 Solenoid
From R "PTR 1/4"
RD KR1 KR1 KS1 1 or 4 KE1
02 - + 01
RD KR2 KS1 KT1

ID J2 J2
RD KR3 Mon
KT1 KR1 04
28 Vdc
Optional 03
Mon economizing Trip
"PTR 2/5" resistor Solenoid
KR1, 2,3
KR2 KS2 04 2 or 5 05 KE2
- +
These relays in TMR systems
From S JS1 KS2 KT2 J2 J2
RD KS1
Mon
KT2 KR2 08
RD KS2
ID 07
RD KS3
Trip
28 Vdc "PTR 3/6" Solenoid
KR3 KS3 3 or 6 KE3
Mon 06 - + 09
KS1 ,2,3 KS3 KT3 J2 J2

JT1 Mon
From T
RD KT1 KT3 KR3 12
11
RD KT2
ID To JR1, 02
RD KT3 JS1, JT1 06
Solenoid
28 Vdc Power Monitor 10
Mon J2 J2
N125 Vdc -
KT1,2,3 +
8 signals to 3 monitor
JR1 ,JS1,JT1 signals to J3
JR1,JS1,JT1 Voltage Supply
and Monitor 335 V dc from R
FLAME1H 33 NS 335 V dc Voltage Supply
J4
34 and Monitor 335 V dc from S
NS J5
FLAME1L Voltage Supply
Supply 8 and Monitor 335 V dc from T
Eight flame detectors
detector circuits
TRPG and Connections to Controller and Trip Solenoids
The primary overspeed trip comes from the controller and is passed to the I/O pack/board,
and then to TRPG. TRPG works in conjunction with the TREG board, which is controlled
by the emergency overspeed system. This TRPG/TREG combination can drive three ETDs.

Flame Detectors
With the TRPG primary trip terminal board, the primary protection system monitors
signals from eight Geiger-Mueller® . With no flame present the detector charges up
to the supply voltage. The presence of flame causes the detector to charge to a level
and then discharge through the TRPG. As the flame intensity increases, the discharge
frequency increases. When the detector discharges, the primary protection system
converts the discharged energy into a voltage pulse. The pulse rate varies from 0 to
1,000 pulses/sec. These voltage pulses are fanned out to all three modules
Specifications
Item Specification
Trip solenoids 3 solenoids per TRPG
Solenoid rated voltage/current 125 V dc standard with up to 1 A draw
24 V dc is alternate with up to 1 A draw (H1B, H2B, H3B)

Solenoid response time L/R time constant is 0.1 sec
Current suppression MOV on TREG
Current economizer Terminals for optional 10 Ω, 70 W economizing resistor on TREG
Control relay coil voltage supply Relays are supplied with 28 V dc from JR1, JS1, and JT1
8 detectors per TRPG
Flame detector supply voltage/current 335 V dc with 0.5 mA per detector
Diagnostics
The I/O board runs the TRPG diagnostics. These include feedback from the trip solenoid
relay driver and contact, solenoid power bus, and the flame detector excitation voltage
too low or too high. A diagnostic alarm is created if any one of the signals go unhealthy
(beyond limits). Connectors JR1, JS1, and JT1 on the terminal board have their own
ID device, which is interrogated by the I/O board, and if a mismatch is encountered, a
hardware incompatibility fault is created. The ID device is a read-only chip coded with the
terminal board serial number, board type, revision number, and the plug location.
Configuration

TRPA Turbine Primary Trip
TRPA cannot be used with the The Aeroderivative Turbine Primary Trip TRPA1A and 2A terminal boards work
Mark VI control system. with PTUR / YTUR I/O packs and with TTUR terminal boards as part of the Mark
VIe / VIeS control system. The inputs and outputs are as follows:
• Twelve passive pulse rate devices (four per R/S/T section) sensing a toothed wheel to
measure the turbine speed. Or, six active pulse rate inputs (two per TMR section)
• Two 24 V dc (H1A) or 125 V dc (H2A) TMR voted output contacts
to the main breaker coil for trip coil.
• One 24-125 V dc ‘Fail-safe’ ESTOP input for removing power from trip relays.
For TMR systems, signals fan out to the PR3, PS3, PT3, JR4, JS4, and JT4 connectors.


Board Revision Mark VIe control Mark VIeS Safety control Comments
IS220PTUR IS200YTUR
TRPAH1A Yes, all versions No 24 V dc output contact rating
TRPAH2A 125 V dc output contact
rating
TRPAS1A Yes, all versions 24 V dc output contact rating,
safety certified
TRPAS2A 125 V dc output contact
rating, safety certified

Installation
TTL pulse rate pick ups, voltage detection, E-Stop, and the breaker relay are
wired to the I/O terminal blocks TB1. Passive pulse rate pick-ups are wired to
TB2. Each block is held down with two screws and has 24 terminals accepting
up to #12 AWG wires. A shield termination strip attached to chassis ground
The TRPA must be configured for the desired speed input connections using
the following table. Jumpers JP1 and JP2 select fanning of the R section pulse
rate pickups to the S and T PTURs or YTURs.
Speed Input Connections Function Jumper

Wire to all 12 pulse inputs: Each set of (4) pulse inputs goes to its own Cannot use jumper:
dedicated PTUR or YTUR I/O pack.
PR1_R – PR4_T Place in STORE position
Wire to TTL pulse inputs: Each set of (2) pulse inputs goes to its own Cannot use jumper:
dedicated PTUR or YTUR I/O pack.
TTL1_R – TTL2_T Place in STORE position
Wire to bottom 4 pulse inputs only: The same set of signals are fanned to all the Use jumper:
PR1_R – PR4_R PTUR or YTUR I/O packs.
Place over pin pairs
NO wiring to TTL1_R-TTL2_T or
PR1_S-PR4_T
Wire to bottom 2 pulse inputs: Cannot fan the TTL signals. Only the R PTUR Cannot use jumper:
will receive data.
TTL1_R – TTL2-R Place in STORE position

TRPAH1A or TRPAS1A Terminal Board
DC-62 pin
TB 1 type connector
x
x 1
JT 4 PT 3 with latching
x 2 fasteners
Voltage sensing x 4
x 3
x 5
inputs (4) x 6
x 8
x 7
Voted Relay DC x 9
x 9
outputs (2) x 10 x 11
x 12 x 13
14 x 15
x
E-STOP interlock 16 x 17
x
(1) 28 x 19 JS 4 PS 3
x
20 x 21
x
TTL speed 22 x 23
x
pickups Plug I/O packs
x
(3x2) into PR3, PS3,
TB 2 and PT3
Speed pickups only supported x
2 x 25
through I/O pack not through x
26 x 27
J(R/S/T)4 connectors. x
38 x 29
x
Magnetic speed x
30 x 31 P1 JR 4 PR 3
pickups (3x4) 32 x 33
x 34 x 35 DC-37 pin connector
x 36 37
x Plug cables into
x 38
x
39 P2 JR4, JS4, and JT4 to
x 40 39
x 42 x
41 TTUR. For just trip
x 43 contacts, e-stop,
x 44
x
x 46 45 and voltage sensing
48 x 47
x circuits.
x
Place jumpers over pin

Shield bar
pairs to fan JR set of
magnetic speed inputs
Barrier type terminal to JS and JT
TRPA Terminal Board Wiring

Contact Outputs
• The contact outputs are polarity sensitive. Wire the circuit carefully
to avoid damaging the relays.
• There is no contact or solenoid suppression, user must add external solenoid
suppression to avoid damaging the relays and their contacts.
SOL_V
Solenoid
SOL_PWR
Kn_DCP
DC
contact voltage
TRPA contact
Kn_DCN
Ideal connection
Connection to TRPA contact output
E-Stop/TRP input
• The TRP inputs must be powered for the relays to operate. If the user does
not need or use an ESTOP, then jumper the local TRP power source (P24O/R)
to the respective TRP inputs at the terminal board.
• The ESTOP must be connected to a CLEAN dc source – battery or
• There must be a minimum of 18 V dc at the TRP inputs for proper operation. The
• As the TRP is very fast < 5 ms and the output relay contacts are also fast (< 15 ms),
best wiring practices should be utilized to avoid misoperation. Use twisted-pair
cable when possible and avoid running with ac wiring and so on.

E-STOP
(push-pull button)
15
16
17
18
Ideal connection
TP (17,18); (15,16)
E-STOP
(push-pull button)
15
16
17
18
typical connection
TP (15,17)
E-STOP
(push-pull button)
24-125Vdc
15
battery source 16
17
18
User supplied
power source
TP (15,16)
15
Jumpers 16
17
if no external 18
ESTOP/TRP
Required.
Typical E-Stop connection options

Operation
System Design
The TRPA board is designed for application in two different ways. When a TTUR terminal
board is used to hold three PTUR or YTUR I/O packs the TRPA terminal board may be
connected using three cables with DC-37 pin connectors on each end. In this mode of
operation the TRPA provides two contact voted trip relay outputs, ESTOP, and four voltage
sensors. TTUR provides the normal set of features described for that board. The TRPA
speed inputs are not active and should not be connected with this board arrangement.
TRPA TTUR
Primary trip relay Speed inputs Control module
Voltage detection Synchronizing relays
E-stop Bus & gen voltage
feedbacks
323A5750Px
DC37
DC62
DC62
DC37
PR3
JT4
JR4
P3
Control module
323A5750Px
DC37
DC62
DC62
DC37
PR3
JS4
JR4
P3
Control module
323A5750Px
DC37
DC62
DC62
DC37
PR3
JR4
JR4
P3
The TRPA board can also be used with three I/O packs mounted directly to it. In
this mode of operation the speed inputs to TRPA become active paths into the I/O
pack, allowing for a single terminal board primary trip solution.

TRPA
Class 1 Div. 2
primary trip relay Control module
voltage detection
E-stop
Speed inputs
DC62
DC62
PT3
P3
Control module
DC62
DC62
PS3
P3
Control module
DC62
DC62
PR3
P3
TRPA1A and TRPA2A only functions correctly with three PTUR or YTUR
I/O packs. Simplex operation is not possible.
Speed Inputs
When used with PTUR or YTUR I/O packs mounted directly on the TRPA the speed
inputs provide two options. Each PTUR or YTUR I/O pack can receive a dedicated set of
four speed inputs from their respective TRPA terminal points as is done on TTUR. As
an option, jumpers P1 and P2 can be placed on the TRPA to take the first four speed
inputs (those for the R pack) and fan them to the S and T packs. When this is selected the
terminal board points for S and T speed input become no-connects and should not be used.
E-Stop
The TRPA includes an E-Stop function. This consists of an optically isolated input
circuit designed for a dc input in the range of 24 V to 125 V nominal. When energized
the circuit enables coil drive power in the R, S, and T relay circuits through independent
hardware paths. The response time of this circuit of less than five milliseconds
plus the response time of the trip relays of less than one millisecond yields very
fast E-Stop response. E-Stop is monitored by PTUR or YTUR, but the action to
remove trip relay coil power is entirely in the hardware of TRPA.

Voltage Monitors
The trip relays on TRPA can be freely located anywhere in a trip string. Because
the trip string circuit is not fixed, there are four general-purpose isolated voltage
sensor inputs on TRPA. These can be used to monitor any points in the trip system
and drive the voltage status into the system controller where action can be taken.
Typical use of these inputs may be to sense the power supply voltage for the two
trip strings and to sense the solenoid voltage of the device being driven by the
relays. This set of applications is used in the wording of the board symbol, but
the sensors can be freely applied to best serve the application.
Trip Relays
The trip relays are made using sets of six individual form A devices arranged in a voting
set. Because detection of a shorted relay is important to preserve tripping reliability there
is a sensing circuit applied to each of the sets of relays. When the relays are commanded
to open and voltage is present across the relays the circuit will detect if one or more relays
are shorted. This signal goes to the I/O pack to create an alarm. The TRPA sensing circuit
uses the relay commands from all three packs to avoid a false indication in the event that
one I/O pack votes to close the relay while the other two I/O packs vote to open.
TRPA
TTUR (3) Control modules
Class 1 Div. 2
primary trip relay Speed inputs
Synchronizing relays
Bus & gen voltage
feedbacks
323A5750Px
P(R/S/T)3
J(R/S/T)4
J(R/S/T)4
DC37
DC62
DC62
DC37
P3
TRPA
(3) Control modules
Class 1 Div. 2
primary trip relay
Speed inputs
P(R/S/T)3
DC62
DC62
P3
TRPA and I/O Pack, TMR System

TRPA Typical Voted Contact Configuration
Note The above figure is simplified with many circuit paths omitted for clarity.

Terminal Board Speed Input Screw Assignments
Circuit MnnH TB1/2 MnnL TB1/2 TTL TB3

1T M1TH 25 M1TL 26 TTL1_T 01
2T M2TH 27 M2TL 28 TTL2_T 02
3T M3TH 29 M3TL 30 —
4T M4TH 31 M4TL 32 —
1S M1SH 33 M1SL 34 TTL1_S 03
2S M2SH 35 M2SL 36 TTL2_S 04
3S M3SH 37 M3SL 38 —
4S M4SH 39 M4SL 40 —
1R M1RH 41 M1RL 42 TTL1_R 05
2R M2RH 43 M2RL 44 TTL1_R 06
3R M3RH 45 M3RL 46 — —
4R M4RH 47 M4RL 48 — —

Specifications
Item Specification
Number of inputs 3x4 passive (magnetic) speed pickups or 3x2 active (TTL) speed pickups.
1 ESTOP/TRP input
Number of outputs 2 trip contacts:
1 ESTOP/TRP power source.
Contact ratings NEMA class F. Minimum operations: 100,000
IS200TRPA1A Voltage: 24 V dc nominal
5 A dc resistive
3 A dc with L/R = 7 milliseconds and no suppression
3 A dc with L/R = 100 milliseconds with suppression
Active Voltage Clamp Limiting max. voltage <= 60 V dc
IS200TRPA2A Voltage: 125 V dc nominal
1 A dc resistive
1 A dc with L/R = 7 milliseconds and no suppression
1 A dc with L/R = 100 milliseconds with suppression
Active Voltage Clamp Limiting max. voltage <= 200 V dc
Voltage isolation: Optically isolated: 2500 V rms isolation, for one min
ESTOP/TRP voltage source 24 V dc no-load, 0.3 to 1K source impedance
0 – 2kHz requires 27 mV
2kHz – 6kHz requires 50 mV
Above 15kHz requires 250 mV
Physical
Size 33.0 cm high x 17.8 cm , wide (13 in x 7 in)

Diagnostics
• Feedback from the shorted contact detector checked; if there is a problem

with the control signal an alarm should be created.
• Feedback from the ESTOP/TRP input is checked; if there is a problem
with the signal a fault should be created.
between intention and actual position, an alarm should be created.
DIAG_PTUR or DIAG_YTUR occurs. The diagnostic signals can be individually
latched and then reset with the RESET_DIA signal if they go healthy.
board type, revision number, and plug location. When the chip is read by PTUR
Configuration
Jumpers JP1 and JP2 select the fanning of the 4 R section passive speed pickups
to the S and T section PTURs or YTURs. Place the jumper over the pin pairs
to fan the 4 R speed input to the other two TMR sections.

TRPL Turbine Primary Trip
The Large Steam Turbine Primary Trip (TRPL) terminal board is used for the primary
overspeed protection of large steam turbines. TRPL is controlled by the turbine Primary
Turbine Protection controller (VTUR or PTUR), and contains nine magnetic relays
in three voting circuits to interface with three trip solenoids (ETDs). TRPL works
in conjunction with the TREL terminal board to form the primary and emergency
sides of the interface to the ETDs. These two terminal boards are used in a similar
way as TRPG and TREG are used on gas turbine applications.
Up to three trip solenoids can be connected between the TREL and TRPL terminal boards.
TREL provides the positive side of the 125 V dc to the solenoids and TRPL provides the
negative side. In addition, two manual emergency stop functions can be connected.

In the Mark VI control system, the TRPL works with the VTUR board and only
supports TMR systems applications. Cables with molded plugs connect TRPL
to the VME rack where the VTUR board is located.
Mark VIe Control Systems

In the Mark VIe control system, the TRPL is controlled by the PTUR I/O packs
on TTURH1C and only supports TMR applications. The I/O packs plug into the
D-type connectors on TTURH1C, which is cabled to TRPL.

Installation
Connect the wires for the three trip solenoids directly to the first I/O terminal block.
Connect the wires for the primary emergency stop and optional secondary emergency
stop to the second terminal block. Connect the trip solenoid power to plugs JP1, JP2,
and JP3. The wiring connections are shown in the following figure.
Install a jumper across terminals 9 and 11 for the PTR3 trip. If a second emergency stop is
required, remove the jumper from terminals 46 and 47 and connect the wires here.
TRPL Primary Trip Terminal Board JT1

(Large Steam Turbine) 125/24 V dc, bus A JP1
125/24 V dc, bus B JP2

x
x 1
Trip solenoid 1 or 4 x 2
x 3 PwrA_P 125/24 V dc, bus C JP3
PwrA_P x 4
x 5
PwrB_P x 8
x 7 PwrB_P
x 9
x 11
x 12
x 13 JS1
x 15
x 16
x 17
PwrC_P x 18 Cables to TTURH1C
x 19 PwrC_P
x 21
PwrA_N x 22
PwrC_N x 24
x 23 PwrB_N
or
x
Cables to VTUR boards

for Mark VI system
x
x 25 JR1
x 26
x 27
x 28
x 29
x 30
x 31
x 32
x 33
x 34
x 35
x 36
x 37
x 38
x 39 NC1 Misc. tie points, J2
NC2 x 40
x 41 NC3 no internal
NC4 x 42
connection
Primary E- x 43 TRP1
TRP2 x 44
Stop x 45 TRP4 Primary E-Stop Cable to TREL
TRP3 x 46
x 47 TRP5
To second TRP6 x 48
TRPL x
Up to two #12 AWG wires To add secondary E-Stop, Terminal blocks can be
per point with 300 volt remove jumper across unplugged from board for
insulation terminals 46 and 47 maintenance
TRPL Terminal Board Wiring

Operation
TRPL is used for TMR applications only. Three separate power buses, PwrA,
PwrB, and PwrC for solenoid power, are brought in through connectors JP1, JP2,
and JP3, and then distributed to TREL through connector J2.
The power buses have a nominal voltage of 125 V dc (70 to 145 V dc) or
24 V dc (18 to 32 V dc). The board includes power bus monitoring (three
buses). The maximum current per bus is 3 A.
Each of the three trip solenoids is controlled by three relays using 2/3 contact voting.
The relay output rating (for 100,000 operations) is as follows:
• At 24 V dc, 3 A, L/R = 100 ms, with suppression

• At 125 V dc, 1.0 A, L/R = 100 ms, with suppression
The trip circuits include solenoid suppression, associated solenoid voltage

monitoring, and trip relay contact monitoring. In the TRPL, the hardwired
trip (E-Stop) and associated monitoring provides approximately 6.6 V dc to
the I/O board when the K4 relays are picked up.

125/24 Vdc bus C
125/24 Vdc bus B J2, power
buses to
125/24 Vdc bus A
TREL
JP1 JP2 JP3

Terminal Board TRPL
PwrA_P PwrB_P PwrC_P Terminal
Board TREL
P28R1 to PwrB_N PwrC_N Trip
JR1 PwrA_N
monitor solenoid
R J4
RD KR1 KS1 #1 or 4
KR1 SOL1 02 02 ETR1
- +
PTR 1
RD KR2 KS1 KT1
J2 J2
RD KR3
KT1 KR1 01
ID P28 VR
03
Solenoid volts monitor
Mon K4R Trip
to JR1,JS1,JT1 04
PwrA_N
PwrA_P solenoid
KR1,2,3
PTR 2 KR2 KS2 #2 or 5
SOL2 06 - + 05 ETR2
JS1 P28S1 to
monitor KS2 KT2
S J4 J2 J2
RD KS1
KT2 KR2 05
RD KS2
07
Solenoid volts monitor
RD KS3 to JR1,JS1,JT1 08
ID
PwrB_N Trip
PwrB_P
P28 VS solenoid
#3 or 6
Mon K4S 10 08 ETR3
- +
PwrC_N J2
KS1,2,3 J2
P28T1 to
JT1 Solenoid volts monitor
T J4 monitor
to JR1,JS1,JT1 9
RD KT1
"PTR 3" KR3 KS3
11
RD KT2
KS3 KT3
RD KT3
ID
P28 VT KT3 KR3
39
Miscellaneous tie Mon K4T
40 PwrC_P PwrC_P 18
points; no internal
41
connections KT1,2,3 19
42 To JR1,
JS1, JT1 Sol PwrA_P
TRP1 43 Pwr PwrB_P
Primary E-Stop TRP2 44 Monitor PwrC_P
CL P28VV
TRP4 45 PwrA_N 22
K4R
PwrB_N 23
Jumper TRP3 46 K4S PwrC_N 24
TRP5 47 K4T
JR1
Secondary E-Stop when JS1
applicable, remove jumper To To relay JT1
48 P28R1 JR1 K25A on
to enable function. Mon
P28S1 JS1 TTUR driven
TRP6 (3) from TREL
P28T1 JT1
J2
TRPL Terminal Board

Specifications
Item Specification
Trip solenoids 3 solenoids per TRPx
24 V dc is alternate with up to 3 A draw

Solenoid response time L/R time constant is 0.1 sec with suppression
Current suppression MOVs
Primary Emergency Stop, manual One with optional secondary E-Stop
Diagnostics
The ID device is a read-only The I/O controller runs the TRPx diagnostics. These include feedback from the trip
chip coded with the terminal solenoid relay driver and contact, solenoid voltage, and solenoid power bus. A diagnostic
board serial number, board alarm is created if any one of the signals goes unhealthy (beyond limits). The Jx1
type, revision number, and connectors on the terminal board have their own ID device, which is interrogated by the
the plug location. I/O board, and if a mismatch is encountered, a hardware incompatibility fault is created.
Configuration
There are no switches or hardware settings on the terminal board. Terminals 9 and
11 must use a jumper to include the PTR 3 trip. Terminals 46 and 47 must use
a jumper if only one manual emergency stop is required.

TRPS Turbine Primary Trip
The Small Steam Turbine Primary Trip (TRPS) terminal board is used for the primary
overspeed protection of small and medium size steam turbines. TRPS is controlled by
the Primary Turbine Protection controller (VTUR or PTUR), and contains three magnetic
relays to interface with three trip solenoids (ETDs). TRPS works in conjunction with
the TRES terminal board to form the primary and emergency sides of the interface to
the ETDs. These two terminal boards are used in a similar way as TRPG and TREG
are used on gas turbine applications, except with the following differences:
• Two-out-of-three voting is done in the relay drivers and not using relay
contacts as with TRPG and TRPL.
• In a simplex application, the voting is bypassed and the relay drivers
are controlled by a single signal from JA1.
• There are no economizing relays.
• There are no flame detector inputs.
Up to three trip solenoids can be connected between the TRES and TRPS terminal boards.
TRES provides the positive side of the 125 V dc to the solenoids and TRPS provides the
negative side. In addition, two manual emergency stop functions can be connected.

In the Mark VI control system, the TRPS works with the VTUR board and
supports simplex and TMR applications. Cables with molded plugs connect
TRPS to the VME rack where the VTUR board is located.
Mark VIe Controls Systems

In the Mark VIe control system, TRPS is controlled by the PTUR I/O packs on
TTURH1C and supports simplex and TMR applications. The I/O packs plug into
the D-type connectors on TTURH1C, which is cabled to TRPS.

Installation
Connect the wires for the three trip solenoids to the first I/O terminal block. Connect the
wires for the primary emergency stop and optional secondary emergency stop to the
second terminal block. Connect the trip solenoid power to plugs JP1, JP2, and JP3. If
a second emergency stop is required, remove the jumper from terminals 46 and 47, and
connect the wires here. The wiring connections are shown in the following figure.
Primary Trip Terminal Board TRPS JP1 JT1

(Small/Medium Steam Turbine) 125/24 V dc, bus A
JP2
125/24 V dc, bus B
x
x 1 PwrA_P1 JP3
PwrA_P2 x 2
x 3 PwrA_P3 125/24 V dc, bus C
SUS1A x 4
x 6
x 5 SUS1B
SUS1C x 7 SUS1D
SOL1A x 8
x 10
x 9 SOL1B PTR1
PwrB_P2 x 12
x 11 PwrB_P1
x 14
x 13 PwrB_P3 JS1
SUS2A
x 16
x 15 SUS2B J - Port Connections:
SUS2C
18
x 17 SUS2D
SOL2A x
PTR2
x 20
x 19 SOL2B Cables to TTURH1C
PwrC_P2 x 22
x 21 PwrC_P1 for Mark VIe system
x 23 PwrC_P3
SUS3A x 24
x
or
PTR3
Cables to VTUR boards
for Mark VI system
x
x 25 SUS3B K4_3
SUS3C x 26 JA1 JR1
x 27 SUS3D
SOL3A x 28
x 29 SOL3B
x 30 K4_1
x 31
x 32
x 33
x 34
x 35 K4_2
PwrA_N x 36
PwrC_N x 38
x 37 PwrB_N
NC2 x 40
x 39 NC1 J2
x 41 NC3
NC4 x 42
Primary E- x 43 TRP1
TRP2 x 44
Stop x 45 TRP4 Primary
TRP3 x 46
TRP6 x 48
x 47 TRP5 E-Stop Cable to TRES
x
Jumper

point with 300 V insulation from terminal board for maintenance
TRPS Terminal Board Wiring

Operation
TRPS is used for TMR and simplex applications. Three separate power buses, PwrA,
PwrB, and PwrC for solenoid power, are brought in through connectors JP1, JP2,
and JP3, and then distributed to TRES through connector J2.
The power buses have a nominal voltage of 125 V dc (70 to 145 V dc) or
24 V dc (18 to 32 V dc). The board includes power bus monitoring (three
buses). The maximum current per bus is 3 A.
Each of the three trip solenoids is controlled by a relay driver. The relay
output rating (for 100,000 operations) is as follows:
• At 24 V dc, 3 A, L/R = 100 ms, with suppression

• At 125 V dc, 1.0 A, L/R = 100 ms, with suppression
The trip circuits include solenoid suppression, associated solenoid voltage

monitoring, and trip relay contact monitoring. In the TRPS, the hardwired
trip (E-Stop) and associated monitoring provides approximately 6.6 V dc to
the I/O board when the K4 relays are picked up.

125/24 V dc bus C
J2, power
125/24 V dc bus B
125/24 V dc bus A buses to
TRES
Terminal Board TRPS JP1 JP2 JP3
Simplex JA1
system P28A PwrB_P PwrC_P Terminal
PwrA_P
uses Board TRES
P28R PwrA_N PwrB_N PwrC_N
JA1
K4_1
P28S PwrA_P1 01
P28 PwrA_P2 02
P28T PwrA_P
PwrA_P3 03
ID
SUS1A 04
JR1 J2
Solenoid volts
J2
monitor to JR1, SOL1A
R 2 RD PTR1 JS1, JT1, JA1
3 SUS1B 05
SUS1C 06
PwrA_N Trip
To R,S,T, A SUS1D 07
Mon solenoid
PTR1 08 -
PTR1 SOL1A +
PTR1 SOL1B 09
ID
K4_2 36 Several terminal
P28 positions for
JS1 different
PwrB_P1 11 applications
S 2 RD PTR2 PwrB_P2 12
3 PwrB_P
PwrB_P3 13
To R,S,T, A SUS2A 14
Mon Solenoid volts J2
SOL2A J2
PTR2 monitor to JR1,
JS1, JT1, JA1
ID SUS2B 15
K4_3 SUS2C 16
PwrB_N Trip
P28 SUS2D 17 solenoid
PTR2
JT1 SOL2A 18 - +
PTR2 SOL2B 19
2 RD PTR3 37
T
3
To R,S,T, A PwrC_P1 21
Mon
PwrC_P2 22
PTR3 PwrC_P
PwrC_P3 23
NC1 39 ID
Misc. tie points, To JR1, SUS3A 24
NC2 40 JS1,JT1, Solenoid volts J2
no internal PwrA_P SOL3A J2
NC3 41 JA1 Sol. monitor to JR1,
connections Power PwrB_P JS1, JT1, JA1
NC4 42 Monitor SUS3B 25
PwrC_P
TRP1 43 SUS3C 26
PwrC_N Trip
Primary E-Stop SUS3D 27
TRP2 44 solenoid
CL P28VV PTR3
SOL3A 28 - +
TRP4 45 K4_1 PTR3 SOL3B 29
Jumper
TRP3 46 K4_2 38
TRP5 47 K4_3
Secondary E-Stop when JA1
AND J2 To relay K25A on
applicable, remove jumper JR1 To R,S,T,A
48 Monitor TTUR driven from
to enable function. JS1
(3) TRES
TRP6 JT1
TRPS Terminal Board

Specifications
Item Specification
Trip solenoids 3 solenoids per TRPx
24 V dc is alternate with up to 3 A draw

Solenoid response time L/R time constant is 0.1 sec with suppression
Current suppression MOVs
Primary Emergency Stop, manual One with optional secondary E-Stop
Diagnostics
The ID device is a read-only The I/O controller runs the TRPx diagnostics. These include feedback from the trip
chip coded with the terminal solenoid relay driver and contact, solenoid voltage, and solenoid power bus. A diagnostic
board serial number, board alarm is created if any one of the signals goes unhealthy (beyond limits).
type, revision number, and
the plug location. The Jx1 connectors on the terminal board have their own ID device, which is interrogated by
the I/O board, and if a mismatch is encountered, a hardware incompatibility fault is created.
Configuration
There are no switches or hardware settings on the terminal board. Terminals
46 and 47 must use a jumper if only one manual emergency stop is required;
remove jumper if secondary E-Stop is used.

STUR Simplex Primary Turbine Protection Input
The Simplex Primary Turbine Protection Input (STUR) terminal board is a simplex
S-type terminal board version of the turbine terminal board (TTUR). It provides a
connection for the turbine specific primary trip (PTUR), speed and synchronizing
inputs, and trip relay outputs or a cable to drive a primary trip board.
STUR is used for the following:
• Mechanical drives requiring overspeed protection but no synchronizing function.

• Generator drive systems requiring overspeed and primary synchronization.
• Other applications requiring the four pulse input circuits of PTUR.
This terminal board has the same physical size, customer terminal locations, and I/O
pack mounting as other S-type terminal boards. There will be no components higher
than an attached PTUR I/O pack permitting double stacking of terminal boards.
There are four groups:
• IS200STURH1 omits synchronizing hardware and includes trip relays.

• IS200STURH2 includes synchronizing hardware and trip relays.
• IS200STURH3 omits synchronizing hardware and includes a DC-37 pin
connector for a cable leading to a trip terminal board.
• IS200STURH4 includes synchronizing hardware and includes a DC-37 pin
connector for a cable leading to a trip terminal board.
STUR provides the following major functions:
• Provides a DC-62 pin connector for mounting a single PTUR I/O pack.
• Accepts up to four speed input signals.
• A 48 terminal Euro-style box connector for customer connection
points is supplied on the board.
• Provides two trip solenoid outputs, K1 and K2, with each composed
of a safety relay (H1, H2).
• Provides a DC-37 pin connector for connecting a TPRG, TPRL, TPRS,
or TPRA primary trip relay (H3, H4).
• Accepts two PT inputs supporting primary synchronization (H2, H4). They accept
generator voltage and bus voltage signals taken from potential transformers.
• Provides two relay outputs supporting primary synchronization (H2,
H4). Two relays, K25 and K25P, have to close to provide 125 V dc
power needed to close the main breaker 52G.

Installation
STUR and a plastic insulator mount on a sheet metal carrier. The carrier
is then mounted to a cabinet by screws.
K1
K25 K25P
1
2
3
4
5
6 K2
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 J
23 J
24 1
25 2
26
27
PT
PT
28 T P
29
30 R T
31
32 P U
33
34 G R
35
36
37
38
39
40
41
42
43
44
45
46
47
48
TB1
STUR Terminal Board
STUR Terminal Board Layout

Customer Terminal Assignments
Terminal Signal Name Description

STURH1A STURH2A STURH3A STURH4A
1 K1_NO1_In K1_NO1_In Parallel connection to terminal 2.
2 K1_NO1_In K1_NO1_In Relay K1 Normally Open contact #1
3 K1_Centertap K1_Centertap Relay K1 Common
4 K1_NC_Out K1_NC_Out Relay K1 Normally Closed
5 K1_NO2_In K1_NO2_In Relay K1 Normally Open Contact #2 in
6 K1_NO2_Out K1_NO2_Out Relay K1 Normally Open Contact #2 ret.
7 K1_NO2_Out K1_NO2_Out Parallel connection to terminal 6
8 K2_NO1_In K2_NO1_In Parallel connection to terminal 9
9 K2_NO1_In K2_NO1_In Relay K2 Normally Open contact #1
10 K2_Centertap K2_Centertap Relay K2 Common
11 K2_NC_Out K2_NC_Out Relay K2 Normally Closed
12 K2_NO2_In K2_NO2_In Relay K2 Normally Open Contact #2 in
13 K2_NO2_Out K2_NO2_Out Relay K2 Normally Open Contact #2 ret.
14 K2_NO2_Out K2_NO2_Out Parallel connection to terminal 13
15 SOL1_In SOL1_In Solenoid 1 voltage sensor + input
16 SOL1_Ret SOL1_Ret Solenoid 1 voltage sensor - input
17 SOL2_In SOL2_In Solenoid 2 voltage sensor + input
18 SOL2_Ret SOL2_Ret Solenoid 2 voltage sensor - input
19 no connect
20 no connect
21 GENH GENH Generator PT input high
22 GENL GENL Generator PT input low
23 BUSH BUSH Bus PT input high
24 BUSL BUSL Bus PT input low
25 B52GH B52GH Output (PGEN) to B52G feedback contact
26 B52GL B52GL Return side of B52G feedback contact
27 PGEN PGEN Positive breaker coil power input
28 AUTO AUTO Output of K25P contact closure
29 MAN MAN Output of K25 contact closure
30 BKRH BKRH 52G Breaker Coil positive output.
31 BKRH BKRH Parallel connection to terminal 30
32 NGEN NGEN Negative breaker coil power connection
33 no connect
34 no connect
35 no connect
36 no connect
37 TTL1 TTL1 TTL1 TTL1 Active speed pickup input 1

Terminal Signal Name Description
38 PR1_H PR1_H PR1_H PR1_H Passive speed pickup input 1
39 PR1_L PR1_L PR1_L PR1_L Speed pickup 1 return (active and passive)
Operation
Board Groups
STUR is available in four distinct configurations. STUR is not available with fixed box
terminals. It uses pluggable type terminals. Two groups offer on-board trip relays and
two groups offer DC-37 pin connectors for using an external trip board. Components
supporting generator applications will be omitted from two groups used for mechanical
applications and added for groups used for generator applications.
STUR Board Variations
Board Version Generator Trip Application

Application Connections
STURH1A No Trip relays Mechanical drive turbines
STURH2A Yes Trip relays Generator drive turbines
STURH3A No DC-37 pin Pulse inputs only, mechanical drive
connector requiring features provided by a
separate primary trip board.
STURH4A Yes DC-37 pin Generator drive turbines requiring

connector features provided by a separate
primary trip board.

1 T ri p C o n t a c ts
K1
J A1
K1
/ fr o m
K2
Relay
To
TPRx through DC-37 pin cable

K2
Position K1MON
K2MON
J2
+
M o n it o r s
Voltage
Sol1_Vfdbk Detector
+ Voltage
Sol2_Vfdbk Detector
K25
To J A 1
GENH K25P
GENL
BUSH
P ri m a r y S y n c .
BUSL
B52GH
B52GL Voltage L52G
P_Gen Detector
Auto K25P Voltage BKRVLT
Man K25 Detector To J2
BKRH Voltage BKRPRM
Direct connect PTUR

Detector
N_Gen Voltage BKRGES
Detector
Voltage BKRGXS
Detector JA1
Spd 1
TUR
S p e e d In p uts
P
Spd 2 d to
S pee
Spd 3
MPU
S
Spd 4
STUR
48
STUR Schematic
Speed Input
STUR provides four speed input circuits that accept passive speed sensors or active
speed sensors. When passive sensors are used the signal is applied between terminals
PR#_H and PR#_L where # is 1 through 4. Sensitivity of the passive sensor input is such
that the PTUR I/O pack is able to sense speeds as low as 2RPM. When active speed
sensors are used the signal is applied between terminals TTL# and PR#_L.

Trip Relays
STUR version H1 and H2 provides two trip solenoid outputs, K1 and K2,
with each composed of a safety relay that uses forcibly guided contacts. Relay
position feedback is provided to PTUR using one of the contact pairs in the
relay. Extra customer terminals are provided to allow connecting two or three
STUR boards in a redundant tripping configuration.
If three STUR boards are to have their trip relays connected as a TMR voting set two
sets of normally open contacts are required of each board. Two out of three voting
is then provided when the following connection pattern is followed:
The above diagram displays four locations that require two wires on a single
terminal as indicated by the wire junctions used. The STUR terminal board has
been designed to provide dual terminals on these circuits to permit TMR wiring
with no more than one wire on each terminal point. The four redundant terminals
are listed in the connection chart in the Installation section.
Primary Synchronizing
All voltage based feedback of STURH2 and STURH4 used with PTUR provides support for synchronized closure
synchronizing relay status is of a 52G primary breaker. Two PT inputs are provided for Bus and Generator
based on a voltage return path voltage on terminals 21 through 24. Breaker positive power at 24, 48, or 125 V dc
through terminal 32. is applied to terminal 27 (PGEN) and the return is applied to terminal 32 (NGEN).
The presence of this voltage is indicated by the BKRVLT signal. Positive power
passes through a permissive relay K25P to terminal 28 (AUTO) with power indicated
by the BKRPRM signal. Power then passes through the synchronizing pilot relay
K25 to terminal 29 (MAN) as indicated by the BKRGES signal.
If a backup sync-check relay is used it is to be wired between terminals 29 and 30

(BKRH) with closure indicated by signal BKRGXS. If a backup sync-check is not used
a jumper between terminals 29 and 30 is used to complete the circuit and BKRGXS
and BKRGES both indicate that power is applied to the breaker coil. The breaker coil
or a pilot relay is to be wired between terminals 31(BKRH) and 32 (NGEN).
Please refer to GEI-100575 PTUR documentation for a detailed description

of the synchronizing process.

Feedback Signals
Feedback signals are dependent on the group of STUR. Possible
signals include the following:
• Relay position feedback from STUR K1 and K2 trip relays.

• Solenoid voltage feedback associated with K1 and K2.
• Five voltage feedbacks associated with the sync function. The following
signals are formed by testing the voltage between the desired signal and
the return side of the power bus or N125GEN.
− BKRVLT – Voltage status of the power bus used to close the breaker.
− L52G – Voltage feedback from an auxiliary contact on the 52G breaker. A
separate set of customer screw terminals provides input.
− BKRPRM – Voltage status of the breaker close permissive relay contact, K25P.
− BKRGES – Voltage status of the combination of the K25P contacts
wired in series with the K25 contacts.
− BKRGXS – Voltage status of the series combination of K25P, K25,
and an auxiliary backup sync check relay (K25A) which equals the
voltage applied to the breaker coil or a pilot relay.
• Two sync relay coil drive feedback signals.
• Feedback signals provided by a trip card wired to J2
The relationship between feedback and STUR group is as follows
Relay Solenoid Sync Circuit Sync Relay Trip Card

Position Volts Volts Coils Feedback
STURH1 Yes Yes
STURH2 Yes Yes Yes Yes
STURH3 Yes
STURH4 Yes Yes Yes
Emergency Stop Circuit

STUR contains no provisions for an emergency stop circuit.
Failure Detection
An external test signal is required for speed input testing. Normal running speed signal
failure detection is achieved through redundant signals applied to STUR. PT inputs
require external test signals for proper feedback. Trip relays, depending on which
STUR version is being tested, use forcibly guided contacts ensuring a feedback contact
accurately represents the power contact position. Breaker closure relay contact logic
includes voltage based status feedback announcing any unexpected behavior.

Trip Board Comparison
The following table compares existing primary trip boards to STUR.
Trip Board Comparison Chart
Board TMR/Simplex Output Output Estop Sync Support Trip
Contacts 125 V Contacts 24 V Output Count

TRPGH1B TMR 1A No No Yes 3
TRPGH2B Simplex 1A 3A No Yes 3
TRPLH1A TMR 1A 3A Yes Yes 3
TRPSH1A TMR/Simplex 1A 3A Yes Yes 3
TRPAH1A TMR No 5A Yes No 2
TRPAH2A TMR 1A No Yes No 2
STURH1A Simplex 0.5A 5A No No 2
STURH2A Simplex 0.5A 5A No Yes 2
STURH3A Simplex (TRPx) (TRPx) No No (TRPx)
STURH4A Simplex (TRPx) (TRPx) No Yes (TRPx)
Simplex Turbine Applications

In simplex applications STUR accepts up to four pulse rate signals used to measure turbine
speed. The PT signals provide voltage input from both sides of a 52G circuit breaker
permitting automatic synchronization to be performed. The on-board trip relays provided
by the H1 and H2 groups of STUR create a self-contained overspeed and synchronizing
function. It is also possible to use the H3 or H4 group of STUR in a simplex application
with a simplex trip terminal board cabled into STUR using the DC-37 pin connection.
TMR Turbine Applications

Three STUR/PTUR combinations can be used where TMR applications are needed. A
typical application would use a TMR trip terminal board with group H3 or H4 of STUR.
This provides trip relay outputs that are wired to vote on the terminal board. It is possible
to use three H1 or H2 STUR boards in a TMR normally open tripping configuration as
each trip relay provides two normally open contacts. When this is desired the STUR
provides two parallel customer terminals on select points to allow TMR relay contact
voting wiring to be installed without two wires under one terminal.

Specifications
Item Specification
Number of inputs 4 passive or active speed pickups
1 generator and 1 bus voltage potential transformer (H2, H4)
1 generator breaker status contact. (H2, H4)
Number of outputs 2 Primary trip relays (H1, H2)
2 Synchronizing relays (H2, H4)
1 DC-37 connector for primary trip terminal board (H3, H4)

Generator and bus voltage sensors Two single phase 115 V ac rms potential transformer inputs. Each input has
less than 3 VA of loading.
Generator breaker circuits (synchronizing, External circuits should have a voltage range within 20 to 140 V dc. Circuits
K25, K25p) are rated for NEMA class E225 creepage and clearance. 250 V dc applications
require interposing relays.
Contact rating 3.15 A at 24 V dc, 1.2 A at 48 V dc, 0.4 A at 125 V dc, resistive.
Contact voltage sensing 20 V dc indicates high and 6 V dc indicates low. Each circuit is optically isolated
and filtered for 4 ms. Circuits will accept up to 145 V dc input.
Trip Relays (K1, K2) Contact Rating: 4 A at 24 V dc, 4 A at 48 V dc, 2 A at 125 V dc for normally
open contacts resistive. 4 A at 24 V dc, 4 A at 48 V dc, 0.3 A at 125 V dc for
normally closed contacts resistive.
Minimum contact load >50 mW.
Maximum Switching Rate: 3 operations/minute at rated load, 60
operations/minute at minimum load
Associated printed circuit board designed for minimum of 20 A surge rating for
10 milliseconds.
Physical
Size 15.9 cm high x 17.8 cm, wide (6.25 in x 7 in)
Temperature -30 to +65°C (-22 to 149 °F)
Humidity 5% to 90% non-condensing

Diagnostics
Diagnostic tests are made on the STUR as follows:
• Feedback from the solenoid relay drivers is checked; if there is a problem

• Feedback from the relay contact position is checked; if there is a problem
• Loss of solenoid power creates a fault.
• Slow synch check relay, slow auto synch relay, slow breaker, and locked
up K25 relay; all of these create a fault.
L3DIAG_PTUR occurs. The diagnostic signals can be individually latched and
then reset with the RESET_DIA signal if they go healthy.
board type, revision number, and plug location. When the chip is read by PTUR
Configuration

PVIB Vibration Monitor Module
Vibration Monitor (PVIB)

The Infrared port is not used. The Vibration Monitor (PVIB) pack provides the electrical interface between one
or two I/O Ethernet networks and the TVBA vibration terminal board. The pack
contains a processor board common to all Mark* VIe distributed I/O packs, an
acquisition board and a daughterboard. The pack uses channels 1 through 8 to read
vibration or proximity information from the following sensor types: Proximitors®,
accelerometers with an integrated output (Channels 1-3 only), Velomitor®, or
seismics. Channels 9 through 12 only support proximitors and channel 13 can input
either a Keyphasor® signal-type or a proximity-type signal.
Input to the pack is through dual RJ45 Ethernet connectors and a 3-pin power input. The
PVIB supports dual Ethernet networks for frame rates slower than 100 Hz. It supports
single Ethernet network for frame rates of 3.125, 6.25, 12.5, 25, 50, and 100 Hz. Output
is through a DC-37 pin connector that connects directly with the associated terminal
BAFAH1A
PVIBH1A
Vibration BPPB
KAPAH1A Module processor board
board
Single or dual
Ethernet cables
ENET1
TVBA Vibration
Terminal Board
ENET2
External 28 V dc
Keyphasor (1)
power supply
Vibration Inputs (8)
Position Inputs (4) ENET1
ENET2
28 V dc
Three PVIB modules for TMR ENET1

One PVIB module for Simplex
ENET2
No Dual control available
28 V dc
PVIB Block Diagram
GEH-6721L PVIB Vibration Monitor Module System Guide 25-1

Compatibility
PVIBH1A is compatible with the Vibration Terminal Board (TVBA), but not compatible
with the TVIB. The following table gives details of the compatibility:
Terminal Board TVBA TVIB

Control mode Simplex-yes TMR-yes No
Installation
¾ To install the PVIB pack
2. Directly plug the PVIB I/O pack into the terminal board connectors.
Note The PVIB mounts directly to a Mark VIe terminal board. TMR-capable terminal
boards have three DC-37 pin connectors and can also be used in simplex mode if only
one PVIB is installed. The PVIB directly supports all of these connections.
7. Verify that the TVBA's N28 power supply daughterboard is seated
properly in the TVBA connector.

Wizard again.

Operation
Processor




Status LEDs
Processor LEDs

present
LED Status

ATTN
or module.
ATTN
every 4 sec

Vibration Monitoring Hardware
The PVIB application-specific hardware consists of the analog filter acquisition
board (BAFA), and the analog processing daughterboard (KAPA). The analog filter
acquisition board provides the signal conditioning to center and amplify signal to improve
analog-to-digital resolution. The first eight channels can be used for vibration and
position signal information. Channels 9 through 12 support position information only.
Channel 13 contains circuitry to support pedestal or slot-type Keyphasor.
Each of the 13 differential amplifier inputs has a digital analog converter (DAC)
bias adjustment to null the dc content of the signal to better center the signal for
the analog-to-digital (A/D) input range. The DAC bias command is stored in the
microprocessor to be used in the gap calculation for the Proximitor sensors. The
input channel’s gain stage allows the vibration signal to be amplified. Channels
1 through 8 and 13 have gain adjustments of 1x, 2x, 4x, or 8x, and channels 9
through 12 have gain adjustments of 1x and 4x for the vibration signal. Channels
1 through 8 and 13 use a multi-pole anti-aliasing filter with a band-pass frequency
range of 7 kHz. Channels 9 through 12 use a multi-pole anti-aliasing filter with
a cutoff-frequency of 2.2 kHz. The BAFA also provides voltage monitoring of
the precision reference and the different supply voltages.
The analog processing board, KAPA, has the A/D conversion, the digital-to-analog (D/A)
conversion, and the digital pre-processing for the PVIB. The A/D block has 16 channels,
sampling at a frequency of 80 kHz with 14-bit A/Ds. The digital pre-processing is handled
by a field-programmable gate-array (FPGA). The FPGA reads the A/Ds, digitally filters
the sampled signals and the information is passed on to micro processor memory. The
FPGA also runs the high-frequency section of the tracking filter and the 1x and 2x
functions. The tracking filter is used to determine the vibration content of a turbine caused
by a given rotation speed. The 1x vibration is the peak-to-peak magnitude of the radial
movement in sync with the turbine shaft speed. The 1x calculation also provides the
phase relationship of the vibration phasor relative to the Keyphasor. The 2x calculation
provides the radial vibration component that is at twice the speed of the shaft.

Vibration Monitoring Application Firmware
The vibration monitoring on the PVIB is as follows:
Channels 1 through 3 can be used for position information from Proximitors,

wideband vibration information from Proximitors, accelerometers with integrated
outputs, Velomitors, and Seismics. 1x and 2x information can be derived from
Proximitors viewing axial vibration information when a Keyphasor is used. Tracking
filters are normally used in Mark V LM control applications.
Gapx_Vibx_Wideband_Filtering runs every 10 ms activating the low-pass filter for the

gap calculation, the wideband vibration filter, and the maximum/minimum detect for
the peak-to-peak calculation. The Gap Scaling and Limit Check runs at the frame rate.
This function converts the gap value from counts to the desired engineering units (EU).
The system limit check provides the user with two detection limits and Boolean outputs
for the status. The Vibx Wideband Scaling and Limit Check block runs every frame.
The peak-to-peak calculation is based on the Vmax and Vmin values of the Gapx_Vibx
Wideband Filtering. The wideband peak-to-peak signal is filtered and then scaled to EU.
The re-scaled wideband peak-to-peak signal is then run through a limit check. The limit
check provides the Booleans, SysLim1VIBx and SysLim2VIBx for the limit check status.
Three tracking filters calculate the peak vibration for the LM applications when
accelerometers are used. The tracking filters provide the vibration that occurs at
the rotor speeds defined by the system outputs, LM_RPM_A, LM_RPM_B, and/or
LM_RPM_C. LMVib1A is the vibration detected on channel 1 based on the rotor
speed, LM_RPM_A. LMVib1B is the vibration detected on channel 1 based on
rotor speed, LM_RPM_B and LMVib1C is based on LM_RPM_C.
The 1x and 2x filters provide the peak-to-peak vibration vector relative to the Keyphasor
input from channel 13. VIB1X1 is the peak-to-peak magnitude of the vibration from
channel 1 relative to the rpm based on the Keyphasor. Vib1xPH1 is the phase angle in
degrees of the vibration vector from channel 1 relative to the Keyphasor. VIB2X1 is the
peak-to-peak magnitude of the vibration from channel 1 relative to twice the Keyphasor
rpm. VIB2XPH1 is the phase angle in degrees of the 2x vibration vector from channel 1.

Channels 4 through 8 can be used for position information from Proximitors, wideband
vibration information from Proximitors, Velomitors, and Seismics. 1x and 2x information
can be derived from Proximitors viewing axial vibration information when a Keyphasor
is used. Channels 4 through 8 are identical to channels 1 through 3 with the exception
of the tracking filters. Channels 4 – 8 do not include the tracking filters.
Controller
Vibration Inputs System
Gapx_Vibx Wideband Filtering Gap Scaling & Limit Check for Ch 1 - 8 Variables
GAP1_VIB1
Signal
System SysLim1GAP1
Cond., GAP
PR01 SCALING Limit
A/D & FILTER SysLim2GAP1
Check
Logic
Vib1
WIDEBAND Vmax Pk-Pk System SysLim1VIB1

MAX / MIN
VIBRATION Calc & SCALING Limit
DETECTION SysLim2VIB1
FILTER Vmin Filter Check
Vibx Wideband Scaling & Limit Check for Ch 1- 8
System SysLim1ACCy
RMS
FILTER SCALING Limit SysLim2ACCy
(Mag. only)
Check LMVib1z
Tracking Filters based on LM_RPM_A, B & C where y=1 to 3
& z = A,B or C
VIB1X1
RMS
VIB2X1
FILTER (Mag. & SCALING
Vib1xPH1
Phase) Vib2xPH1
Vibration 1X & 2X Calculations based on Key Phasor GAP3_VIB3
SysLim1GAP3
Gap1_Vib1 Vibration Calculations
SysLim2GAP3
Vib3
SysLim1VIB3
SysLim2VIB3
Signal SysLim1ACCy
Cond., SysLim2ACCy
PR03
A/D &
Gap3_Vib3 Vibration Calculations LMVib1z
Logic where y=7 to 9
& z = A,B or C
VIB1X3
VIB2X3
Gapx_Vibx Wideband Filtering Gap Scaling & Limit Check for Ch 1 - 8 Vib1xPH3
Vib2xPH3
GAP4_VIB4
Signal
System SysLim1GAP4
Cond., GAP
PR04 SCALING Limit
Check
Logic
Vib4
WIDEBAND Vmax Pk-Pk System SysLim1VIB4

MAX / MIN
VIBRATION Calc & SCALING Limit
DETECTION SysLim2VIB4
FILTER Vmin Filter Check
Vibx Wideband Scaling & Limit Check for Ch 1- 8
RMS VIB1X4
VIB2X4
FILTER (Mag. & SCALING
Vib1xPH4
Phase) Vib2xPH4
Vibration 1X & 2X Calculations based on Key Phasor
Gap4_Vib4 Vibration Calculations
GAP8_VIB8
SysLim1GAP8
SysLim2GAP8
Signal Vib8
Cond., SysLim1VIB8
PR08
A/D &
Gap8_Vib8 Vibration Calculations SysLim2VIB8
Logic VIB1X8
VIB2X8
Vib2xPH8
Vib1xPH8
Gapx_Vibx_Wideband_Filtering Diagram

Channels 9-12 are used for position information only. The Gapx_Pos_Filtering runs
every 10 ms and filters the position information. Gapx_Pos Scaling and Limit Check
runs every frame. This function rescales the gap value from counts representing volts
to EU based on the PVIB configuration. The System Limit Check can be used to set
a Boolean at minimum or maximum limit values configured by the user.
Channel 13 supports position feedback and Keyphasor feedback. The Key_Phasor

Filtering runs every 10 ms. A low-pass filter is used for the Gap filter calculation
when the rotor speed is greater than or equal to 100 rpm. Below 100 rpm, the filter
converts to a median select of the present and last two values. At very low speeds,
the hardware Keyphasor comparator is not usable and the runtime application code
determines speed by counting pulses detected through the system input, GAP13_KPH1.
The Keyphasor Filtering function also calculates the speed of the rotor.
The Gap13 KP Scaling and Limit check runs every frame. The Gap Scaling
Limit Check performs the same way it does for channels 1 through 12. This
function also inputs the three rotor speeds, LM_RPM_A, LM_RPM_B, and
LM_RPM_C that are calculated externally to the PVIB.
Signal Space Inputs for Sensor Types
Signal Space Gapn_Vibn Gapy_Posn Gap13_Kph1 Vib1xn LMVibnA Vibn

Input (y = 1-4)
Vib1xPhn LMVibnB
Vib2xn LMVibnC
Vib2xn
Sensor Type
PosProx Channels 1-8 Channels 9-12 Channel 13 Channels 1-8
VibProx-KPH Channels 1-8 Channels 1-8 Channels 1-8
VibLMAccel Channels 1-8 Channels 1-3 Channels 1-8
VibSeismic Channels 1-8 Channels 1-8
VibVelomitor Channels 1-8 Channels 1-8
KeyPhasor Channel 13
VibProx Channels 1-8 Channels 1-8
n=channel

Position / Keyphasor
Inputs
Controller
System
Gapx_Pos Filtering Gapx Pos Scaling & Limit Check Variables
GAP9_POS1
Signal
System SysLim1GAP9
Cond., GAP
PR09 SCALING Limit
Check
Logic
Gap9_POS1 Gap Calculations
Signal GAP12_POS4
Cond.,
PR12
A/D &
Gap12_POS4 Gap Calculations SysLim1GAP12
Logic SysLim2GAP12
Key Phasor Filtering Gap13_KP Scaling & Limit Check
Signal
Cond., GAP System
PR13 SysLim1GAP13
A/D & FILTER Limit
Logic Check SysLim2GAP13
RPM_KP <
45 RPM SCALING GAP13_KPH1
MEDIAN
SELECT
RPM
RPM_KPH1
Calculation
(to
RPM to Phase
KAPA
Compensation
FPGA)
System
Outputs
LMA_Inc LM_RPM_A
(to
RPM to
KAPA LMB_Inc LM_RPM_B
Counts
FPGA)
LMC_Inc LM_RPM_C
Gap13_KPH1 Calculations
Gapx_Pos_Filtering Diagram

Gapx_Vibx_Wideband_Filtering Function
The Gapx_Vibx_Wideband_Filtering function runs at 100 Hz rate. The gap or position
filter is a 2-pole, low-pass filter with a fixed cutoff frequency of 8 Hz. The output of the
gap filter, LP_Gap is expressed in counts and passes through a rolling-average filter to
account for the slower activation rate Gap Scaling and Limit Check function.
The wideband vibration information can be shaped or conditioned based on the

configuration parameter and FilterType. FilterType equal to Low-pass, Band-pass, or
High-pass are used for the Seismic and Velomitor sensor types. FilterType equals to None
is used by all the other sensor types. The Low-Pass filter can be configured for 2, 4, 6, or
8 pole behavior through the parameter Filtrlpattn. The 3 db frequency cutoff frequency,
Filtrlpcutoff, is also adjustable. The High-pass filter can also be configured for 2, 4, 6
and 8 pole to sharpen the attenuation characteristics of the filter through the parameter,
Filtrhpattn. The cutoff frequency, Filtrhpcutoff, is adjustable in configuration.
The wideband filtered vibration output, Vfout, goes through a minimum or maximum
peak detect function. The detect function is based on the Keyphasor detected speed
in rpm. If the rotor speed is less than 60 or greater than 2250 rpm, the capture
window is 160 ms wide. If the speed range is between 60 and 480 rpm, the capture
window is 2000 ms wide. If the speed range is between 480 and 2250 rpm, the
capture window is 250 ms. The objective is to capture at least two cycles of
vibration information to get an accurate peak-to-peak calculation.
Vibx Wideband Scaling and Limit Check

The Vibx Wideband Scaling and Limit Check operates on channels 1 through
8 of the PVIB. The calculation rate for the function is 0.5, 4 or 6.25 Hz. The
calculation rate is based on the peak-to-peak scan times. For example, a scan
time of 160 ms requires a calculation rate of 6.25 Hz.
The Vibx Wideband Scaling and Limit Check inputs are:
Vfmax
Vfmin
The Vibx Wideband Scaling and Limit Check outputs are:
VIBx, the wideband vibration in EU
SysLim1VIBx, the System Limit #1 Boolean; (Boolean is True if VIBx exceeds system
limit 1)
SysLim2VIBx, the System Limit #2 Boolean. (Boolean is True if
VIBx exceeds system limit 2)
The system output uses the System Limit Reset Boolean. If Reset is True,
a latched System Limit Boolean is cleared.
The filtered peak-to-peak wideband vibration signal, FVMpp equals to

Vfmax – Vfmin. FVMpp passes through a single-pole low-pass filter with
an adjustable cutoff frequency, VIB_PP_Fltr.

The Vibx Wideband Scaling and Limit Check scaling block converts the filtered
wideband peak-to-peak vibration from counts to EU peak or EU peak-peak,
depending on the configuration parameter VibType. The scaling values are
determined by the following configuration parameters:
VibType – determines the type of sensor being used.
Scale – gain factor expressed in volts/EU
GnBiasOvride – Gain Bias Override allows the user to override the default
sensor gain value and use the configuration parameter, Gain. See table Probe
Nominal Settings for sensor default values.
Gain – used only when GnBiasOvride = Enables and modifies the resolution of the
incoming signal. Use of settings other than 1x DO NOT increase the net gain of the
Vibx system input. The gain is applied to the input in the hardware, but is divided out in
firmware for a net gain of 1. This provides amplification to small signals before being
digitized to improve signal to noise ratio. The maximum signal amplitude (peak in volts)
times the selected gain factor should not exceed 10 volts to avoid saturation.
The Vibx Wideband Scaling and Limit Check provides two System Limit blocks. The
following configuration parameters control the behavior of the System Limit block:
SysLimxEnabl – the System Limit (x=1 or 2) Enable is set to Enable

to select the use of the block.
SysLimxType – the System Limit (x=1 or 2) Type selects whether the

limit check does a >= check or a <= check.
SysLimitx – System Limit (x=1 or 2) is the limit value used in the >= or <= check.
SysLimxLatch – System Limit (x=1 or 2) Latch determines whether the Boolean

status flag is latched or unlatched. If the Boolean status flag is latched, the flag
will remain True, even if the limit value is no longer exceeded.
The system input or System Limit Boolean status flag is SysLimxVIBy where x is the
System Limit block number (1 or 2) and y is the PVIB channel input number (1–8).

Gap Wideband Scaling and Limit Check
The Gap Wideband Scaling and Limit Check operates on channels 1 through 8 of the PVIB.
The calculation rate for the function is based on the frame rate selected for IONet. The Gap
Wideband Scaling and Limit Check input, Avg_LP_Gap is from the Gapx_Vibx Wideband
Filtering block. The system inputs or Gap Wideband Scaling and Limit Check outputs are:
Gapx_VIBx, the position or gap value in engineering units (EU) for Proximitors, voltage
in V dc for accelerometers with integrated outputs, seismics and Velomitors.
SysLim1GAPx, the System Limit #1 Boolean; (Boolean is True if

GAPx_VIBx exceeds system limit 1)
SysLim2GAPx, the System Limit #2 Boolean. (Boolean is True if

GAP_VIBx exceeds system limit 2)
The system output used is the System Limit Reset Boolean. If Reset is True,

The Gap Wideband Scaling and Limit Check scaling block converts the
average-filtered gap signal, Avg_LP_Gap from counts to engineering units or
Volts (dc) depending on the configuration parameter VibType. The scaling values
are determined by the following configuration parameters:
ScaleOff – offset value in EU (used for position proximitors only)
Snsr_Offset – the sensor offset or bias voltage (V dc) is used to remove

most of the dc bias of the input signal and move it within the A/D input
range. Used only when GnBiasOvride = Enable
GnBiasOvride – Gain Bias Override allows the user to override the sensor-specific
default values for dc bias and Gain and use the configuration parameters, Gain and
Snsr_Offset. See table Probe Nominal Settings for sensor default values.
Gain – used only when GnBiasOvride = Enable and modifies the resolution of the
Gapx system input. The gain is applied to the input in the hardware, but is divided out in
times the gain factor chosen should not exceed 10 volts to avoid saturation.
The Gap Wideband Scaling and Limit Check provides two System Limit blocks. The



The system input or System Limit Boolean status flag is SysLimxGAPy where x is the
System Limit block number (1 or 2) and y is the PVIB channel input number (1- 8).

Gapx_POSy Gap Calculations
The Gapx_POSy Gap Calculations consists of the Gapx_Pos Filtering and the Gapx_Pos
Scaling and Limit Check where x is the PVIB channel number 9 through 12 and y is
the position number 1 - 4. The Gapx_POSy Gap Calculation’s outputs are:
Gapx_POSy, the position or gap value in engineering units (EU) for Proximitors
SysLim1GAPx, the System Limit #1 Boolean; (Boolean is True if

GAPx_POSy exceeds system limit 1)
SysLim2GAPx, the System Limit #2 Boolean. (Boolean is True if

GAP_POSy exceeds system limit 2)
The system output used is the System Limit Reset Boolean. If Reset is True,
The Gapx_Pos Filtering is executed at a 100 Hz rate. The vibration input for this
function comes from an array with 5 kHz sampled data. The gap or position filter is
a 2-pole low-pass filter with a fixed cutoff frequency of 8 Hz. The output of the gap
filter is expressed in counts and passes through a rolling-average filter to account for
the slower execution rate Gapx_Pos Scaling and Limit Check function.

The Gapx_Pos Scaling and Limit Check scaling block converts the average-filtered
gap signal, Avg_LP_Gap from counts to EU. The conversion is based upon the scaling
variables gain factor SCALE, and the offset value Scale_Off. The scaling values and
scaling block topology are determined by the following configuration parameters:
ScaleOffset – offset value in EU
Snsr_Offset – the sensor offset or bias voltage (V dc) is used to remove

default values for DC bias and Gain and use the configuration parameters, Gain and
The Gapx_Pos Scaling and Limit Check provides two System Limit blocks. The following
configuration parameters control the behavior of the System Limit block:



The system input or System Limit Boolean status flag is SysLimxGAPy where x is the
System Limit block number (1 or 2) and y is the PVIB channel input number (9 -12).

Gap13_KPH1 Calculations
The Gap13_KPH1 Calculations consists of the Keyphasor Filtering and the Gap13_KP
Scaling and Limit Check. The Gap13_KPH1 Calculation’s outputs are:
GAP13_KPH1, the position or gap value in EU for the Keyphasor Proximitor
SysLim1GAP13, the System Limit #1 Boolean; (Boolean is True if

GAP13_KPH1 exceeds limit 1)
SysLim2GAP13, the System Limit #2 Boolean. (Boolean is True if

GAP13_KPH1 exceeds limit 2)
The Gap13_KPH1 system outputs are:
SysLimReset, the System Limit Reset Boolean, (If Reset is True, a

latched System Limit Boolean is cleared)
LM_RPMx, rotor shaft speed in rpm from different stages of the turbine. (x = A, B or C)
The Keyphasor Filtering is executed at a 100 Hz rate. The input for this function
comes from an array with 5 kHz sampled data. The Keyphasor Filtering uses the
low-pass filter when the rotor speed based on the Keyphasor is greater than or equal
to 100 rpm and uses a median select function if the speed is below 100 rpm. The
gap or position filter is a 2-pole low-pass filter with a fixed cutoff frequency of 8
Hz. The median select filter uses the present value (n), the previous (n-1) and the
value 2 samples back (n-2) to perform a median select on. The output of either
filter is expressed in counts and passes through a rolling-average filter to account
for the slower execution rate Gap13_KP Scaling and Limit Check.
The Keyphasor Filtering also uses the input to pass through a single-pole low-pass
filter with a cutoff fixed at 2.3 Hz. The output of this filter is added to the
configuration parameter KPH_Thrshld whose sign is based on the parameter,
KPH_Type. The output is written to the KAPA FPGA DAC.
The Keyphasor Filtering function reads the time registers from the KAPA FPGA and
calculates the signal space output, RPM_KPH1 in units of rpm.

The Gap13_KP Scaling and Limit Check scaling block converts the average-filtered gap
signal, Avg_LP_Gap from counts to EU. The Gap13_KP calculation runs at the frame
rate. The scaling values are determined by the following configuration parameters:
Snsr_Offset – the sensor offset or bias voltage (Vdc) is used to remove

default values for DC bias and Gain and use the configuration parameters, Gain and
The Gap13_KP Scaling and Limit Check provides two System Limit blocks. The



The system input or System Limit Boolean status flag is SysLimxGAP13

where x is the System Limit block number (1 or 2).

1X and 2X Calculations Based on Keyphasor
The 1x and 2x calculations based on Keyphasor provides the peak-to-peak vibration
component (harmonic magnitude and phase) at both the Keyphasor frequency and
twice the frequency. The calculations consist of two sections:
• Low-Pass filter
• Magnitude and Phase Calculation
• The system inputs from the 1x and 2x calculations are:
Vib1Xy, the peak-to-peak magnitude of the vibration phasor that is

rotating at the Keyphasor frequency
Vib1xPHy, the phase angle between the Keyphasor and the ViB1Xy vibration phasor
Vib2Xy, the peak-to-peak magnitude of the vibration phasor that is rotating

at the twice the Keyphasor frequency
Vib1xPHy, the phase angle between the Keyphasor and the Vib2Xy vibration phasor
where y is the PVIB channel number from 1 to 8.
The Vibration 2x function is the same as the 1x function except the results are
a peak-to-peak magnitude of the 2x vibration phasor, Vib2Xy rotating at twice
the Keyphasor frequency and a phase of Vib2xPHy.
The scaling block converts the input units to Engineering units (EU). The scaling
values are determined by the following configuration parameters:

Tracking Filters Based on LM_RPM_A, B, and C
The tracking filters based on LM_RPM_A, B, and C provide the peak vibration
component (harmonic magnitude only) at the speeds: LM_RPM_A, LM_RPM_B,
and LM_RPM_C. The Tracking filters require both filter stages executing at 100
Hz and the magnitude calculation executing at the frame rate.
The system inputs from the tracking filters are:
• LMVibxA, the peak magnitude of the vibration component rotating

at LM_RPM_A (RPM) speed
• LMVibxB, the peak magnitude of the vibration component rotating
at LM_RPM_B (RPM) speed
• LMVibxC, the peak magnitude of the vibration component rotating
at LM_RPM_C (RPM) speed
• SysLim1ACCx, the System Limit Boolean status of Limit1 where x = 1-9
• SysLim2ACCx, the System Limit Boolean status of Limit2 where x = 1-9
The scaling block converts the phasor magnitude to EU. The scaling values are
determined by the following configuration parameters:
The Tracking Filter provides two System Limit blocks. The following configuration
parameters control the behavior of the System Limit block:



ID Line
Power Management

Specifications
Item Specification
Number of TVBA: 13 probes
Channels Eight Vibration (First three channels only support accelerometer inputs), four Position, one Keyphasor
PVIB: 13 probes supported
Vibration Inputs Measurement Range Accuracy Frequency
(V dc + V ac) (V ac portion)
Proximity Displacement +1 to –20 V peak 0 to 4.5 V pp ±0.030 V pp* 5 to 200 Hz
(channels 1-8) (1% at 3 V pp*)

±0.150 V pp*(5% 200 to 700 Hz
at 3 V pp*)
Seismic Velocity +1 to –1 V peak 0 to 1.00 V peak Max [2% reading, 5 to 200 Hz
(channels 1-8) ±.008 V peak]

Max [5% 200 to 700 Hz
reading,±.008 V
peak]
Velomitor Velocity -8.75 to 15.625 V 0 to 3.625 V peak Max [2% reading, 5 to 200 Hz
peak
(channels 1-8) ±.008 V peak]
Max [5% 200 to 700 Hz
reading,±.008 V
peak]
Accelerometer Velocity (tracking -8.75 to -11.5 0 to 1.5 V peak ±0.015 V peak 10 to 350 Hz
filter)
(channels 1-3) V peak
Position Inputs
Position Displacement -0.5 to -20 V dc N/A ±0.2 V dc N/A
(channels 1-13) (Gap) (1% of full scale)

Keyphasor Displacement -0.5 to -20 N/A ±0.2 V dc N/A
(channel 13 only) (Gap) V dc (1% of full scale)

Speed N/A N/A ±0.1 % of full scale 2 to 20,000 rpm
speed
Phase N/A N/A ±1 degree for 1x Up to 333 Hz
±2 degrees for 2x Up to 667 Hz
(1x vibration component with respect to key slot)
Buffered Outputs Amplitude accuracy is 0.1 % for signal to Bently Nevada* 3500 system.
A -11 V dc ±5% bias is added to output when a seismic probe used.
Sinks a minimum of 3 mA when interfacing a velomiter
Probe Power -24 V dc from the -28 V dc bus, each probe supply is current limited. 12 mA load per transducer
Probe Signal Minimum of 14-bit resolution for full scale ranges defined
Resolution
Open Circuit Open ckt. Defined as a gap voltage more positive than -1.0 V dc for Proximity, Accelerometer and
Detection Velomitor inputs and a bias current >1 mA for Seismic.

Item Specification
Common Mode Minimum of 5 V dc
Voltage
CMRR at 50/60 Hz -50 dB
* V pp - V peak-peak
Probe Nominal Settings
Probe Type Gain Snsr_Offset (Vdc) Scale(typical value)

Proximity 1x 10 200 mv/mil
Seismic 8x 0 150 mv/ips
Velomitor 2x 12 100 mv/ips
Accelerometer 4x 10 150 mv/ips
Position 1x 10 200 mv/mil
Keyphasor 1x 10 200 mv/mil
Note These are the default settings used if GnBiasOvride=Disable.
Diagnostics

• Each vibration input has hardware limit checking based on preset (configurable)
exceeded, a logic signal is set and the input is no longer scanned. The logic
signal, L3DIAG_PVIB, refers to the entire board.


Configuration

System Limits Enable system limits Enable, Disable
Vib_PP_Fltr First order filter time constant (sec) 0.01 to 2
MaxVolt_Prox Maximum Input Volts (negative), healthy Input, Prox -4 to 0
MinVolt_Prox Minimum Input Volts (negative), healthy Input, Prox -24 to -16
MaxVolt_KP Maximum Input Volts (negative), healthy Input, Keyphasor -4 to 0
MinVolt_KP Minimum Input Volts (negative), healthy Input, Keyphasor -24 to -16
MaxVolt_Seis Maximum Input Volts (positive), healthy Input, Seismic 0 to 1.5
MinVolt_Seis Minimum Input Volts (negative), healthy Input, Seismic -1.5 to 0
MaxVolt_Acc Maximum Input Volts, healthy Input, Accel or Velomitor -12 to +1.5
MinVolt_Acc Minimum Input Volts, healthy Input, Accel or Velomitor -24 to -1
All the other I/O configuration parameters are defined under the specific pack or
terminal board variables given in the following sections.
PVIB Variable Definitions
Name Description Setting

L3DIAG_PVIB PVIB Diagnostics (Input Boolean)
SysLim1GAPx Boolean set TRUE if System Limit 1 exceeded for Gap x input (Input FLOAT)
where x = 1 to 13
SysLim2GAPx Boolean set TRUE if System Limit 2 exceeded for Gap x input (Input FLOAT)
where x = 1 to 13
SysLim1VIBx Boolean set TRUE if System Limit 1 exceeded for Vib x input (Input FLOAT)
where x = 1 to 8
SysLim2VIBx Boolean set TRUE if System Limit 2 exceeded for Vib x input (Input FLOAT)
where x = 1 to 8
SysLim1ACCx Boolean set TRUE if System Limit 1 exceeded for Accelerometer x input (Input FLOAT)
where x = 1 to 9
SysLim2ACCx Boolean set TRUE if System Limit 2 exceeded for Accelerometer x input (Input FLOAT)
where x = 1 to 9
LMVibxA Vib, 1X component, for LM_RPM_A, input x - Card Point Point Edit (Input FLOAT)
where x = 1-3
Fltrlpcutoff Low Pass 3db point (cutoff in Hz) 1.5 to 5 Hz
SysLimEnabl Enable System Limit 1 Fault Check Enable, Disable

SysLim1Type System Limit 1 Check Type >= or <=
SysLimit1 System Limit 1 – Vibration in mils (Prox) or inch / sec (Seismic, -100 to +100
Accelerometer)
SysLim2Enabl Enable System Limit 2 (same configuration as for Limit 1) Enable, Disable
SysLimit2 System Limit 2 – Vibration in mils (Prox) or inch/sec (Seismic, -100 to +100
Accelerometer)
TMR_DiffLmt Difference Limit for Voted TMR Inputs in Volts or Mils -100 to +100
LMVibxB Vib, 1X component, for LM_RPM_B, input x - Card Point Point Edit (Input FLOAT)
where x = 1-3
Accelerometer)
Accelerometer)
LMVibxC Vib, 1X component, for LM_RPM_C, input x - Card Point Point Edit (Input FLOAT)
where x = 1-3
Accelerometer)
Accelerometer)
PM_KPH Speed of Keyphasor in RPM (Input FLOAT)

Vib1Xy Vibration, 1X component only, displacement for input y (Input FLOAT)
where y = 1
through 8
Vib1xPHy Angle of 1X component to Keyphasor for input y (Input FLOAT)
where y = 1
through 8
Vib2Xy Vibration, 2X component only, displacement for input y (Input FLOAT)
where y = 1
through 8
Vib2xPHy Angle of 2X component to Keyphasor for input y (Input FLOAT)
where y = 1
through 8
LM_RPM_A Speed A in RPM (Output FLOAT)
LM_RPM_B Speed B in RPM (Output FLOAT)
LM_RPM_C Speed C in RPM (Output FLOAT)
IS200TVBA Variable Definitions
Name Description Choices

GAPx_VIBx Average Air Gap (Prox) or V dc (other sensors) - Card Point(s) Point Edit (Input FLOAT)
VIB_Type Type of vibration probe Unused, PosProx, VibProx,
VibProx-KPH1, VibLMAccel,
VibVelomitor, Keyphasor
VIB_Scale Volts/mil or Volts/ips 0 to 2
ScaleOff Scale offset for Prox position only, in mils 0 to 90
GnBias Ovride Gain Bias Override Enable, Disable
Snsr_Offset Amount of bias voltage (dc) to remove from input signal used ±13.5 V dc
to max. A/Ds signal range used only when GnBiasOvride is
enabled
SysLim1Enabl Enable System Limit 1 Enable, Disable
SysLim1Latch Latch the alarm Latch, Not Latch
SysLimi1Type System Limit 1 Check Type >= or <=
SysLimit1 System Limit 1 – GAP in negative volts (Velomitor) or positive -100 to +100
mils (Prox)
mils (Prox)
TMR_DiffLimt Difference Limit for Voted TMR Inputs in Volts or Mils -100 to +100

Vibx where x =1 through Vibration, displacement (pk-pk) or velocity (pk) - Card Point Point Edit (Input FLOAT)
8
FilterType Filter used for Velomitor and Seismic only None, Low Pass, High Pass or
Band Pass
Fltrhpcutoff High Pass 3db point (cutoff in Hz) 4 to 30 Hz
Fltrhpattn Slope or attenuation of filter after cutoff 2, 4, 6 or 8 pole
Fltrlpcutoff Low Pass 3db point (cutoff in Hz) 300 to 2300 Hz
Fltrlpattn Slope or attenuation of filter after cutoff 2, 4, 6 or 8 pole
mils (Prox)
GAPx+8_POSx Position Probe - Card Point Point Edit (Input FLOAT)
Type Type of vibration probe Unused or PosProx
Scale Volts/mil 0 to 2
Snsr_Offset Amount of voltage bias (dc) to remove from input signal used ±13.5 V dc
enabled
mils (Prox)
mils (Prox)
GAP13_KPH1 Keyphasor Probe air gap - Card Point Point Edit (Input FLOAT)
Type Type of vibration probe Unused, Keyphasor or PosProx
Scale Volts/mil 0 to 2
Snsr_Offset Amount of voltage bias (dc) to remove from input signal used ±13.5 V dc
enabled

mils (Prox)
mils (Prox)

TVBA Vibration Input
The Vibration Input (TVBA) terminal board acts as a signal interface board for the
PVIB / YVIB I/O pack. The TVBA provides a direct interface to seismic (velocity),
Proximitors®, Velomitors®, and accelerometer-type probes. The terminal board provides
signal suppression and electromagnetic interface (EMI) protection for each input signal.
Signals are also connected to a pull-up bias to allow open circuit detection.
The signals are passed on to the I/O packs through a 37-pin connector. The TVBA can be
used for either simplex or TMR applications. TMR applications fan the signal to three I/O
packs. The TVBA contains buffered outputs to additional connectors beyond the standard
37-pin connection. This feature allows, special 9 and 25 pin connectors to feed the Bently
Nevada* 3500 monitoring system. A bayonet nut connection (BNC) connection for each
channel is also included with this feature, to feed other third party monitoring equipment.
Mark VIe / VIeS control systems do not use RKPS power supplies. Power is obtained
from sourced +28 V power supplies, and there is no external source for
-28 V power. For this reason, the TVBA has three removable daughterboards
to convert +28 to -28. These boards, WNPS (negative power supply) are the
source for all negative power used by the TVBA.
TVBA Terminal Board WNPS -28V Power Supply

JPxC
JA1
OPEN
x ...
... ...
x 2
x 1 .
x 3 ... 37 - pin "D" shell
x 4 ...
... type connectors
COM x 6
x 5 .
x 7 ...
x 8
Common x 10
x 9 JPxB
Vibration x 11
signals
x 12 x 13
...
JB1 ...
... JT1 S PVA
x 14 ...
.
x 16
x 15 ...
x 17 ... PA
x 18 ... . V
JPxC x 20
x 19 ...
...
...
.
OPEN
x 22
x 21
24
x 23 Seismic JPxA
x
x
JC1
... ...
...
.
JS1 S
COM JPxB
x ...
x 25 ...
.
Open x 26 S PVA
x 28
x 27
x 30
x 29 JD1
x 31
...
... V PA
x 32 .
x 34
x 33
Vibration x 35 P2 P1
x 36 JR1 JPxA
signals x 38
x 37 Prox or Accel
x 40
x 39 P6 P5 P4 P3 S
x 42
x 41
x 44
x 43
x 45 P10P9 P8 P7 JPxB
x 46
x 48
x 47 S PVA
x 14 13 12 P11
V PA
Shield bar Velometer JPxA
Plugs for Bently-Nevada data S

Connectors to Bently-Nevada
Portable monitoring gathering 3500 fixed Vibration
& equipment
Monitoring System
TVBA Vibration Terminal Board

Installation
The TVBA accepts 14 sensor inputs that are wired directly to two I/O terminal blocks.
Each block is held down with two screws and has 24 terminals accepting up to #12 AWG
wires. A shield termination attachment point is located adjacent to each terminal block.
Input Channels 1 through 8:
• Support Proximitors, Seismics, Accelerometers (channel 1, 2, 3 only), and Velomitors

• Current-limited -24 V power supply per channel
• JPxA jumper for configuring the open circuit check support and 3 mA
constant current feed for Velomitors
• JPxB configures the JA1 and JB1 outputs for the Bently Nevada 3500 rack
• JPxC configures PR0xL as Open for true differential input or connects
PR0xL to PCOM for a -24 V return.
Input Channels 9 through 12:
• Support Proximitors sensors only

• No jumper configuration
Input Channel 13:
• Support Proximitors or Keyphasor® proximity sensors

• No jumper configurations
-28 V power supply board, WNPS:
• Converts +28 V from PVIB/YVIB to -28 V used by the current-limited -24 V outputs
• One WNPS per PVIB/YVIB
• Independent +28 V inputs and common -28 V bus for all three WNPSs

TVBA VIBRATION TERMINAL BOARD
P28VR
<S>
JR1 JS1 JT1
<T>
P28VS P28VS P28VT
P2 Brd_IdR Brd_IdS Brd_IdT
8
N28R ID ID ID
<S>
<T>
N28R for N28S for N28T for
N2 monitoring monitoring monitoring
8
P28
N28
S P,A 3 mA
1 N24Vxx v
S CL JPxA JA1 &
PCOM
V 2
JB1
P PRxxH
S DB25
R
O S PRxxL
3
X S P, V,A
PCOM OPEN
Vib or Pos
NC S JPxB
Prox., or Eight of the PCOM -11V
Seismic, or above ccts
Accel, or
Velometer
N28 Neg Volt Ref P1 thru P8
BNC
N24Vxx P28
25 form H2x
S CL JC1
26 PRxxH
P S DB25
R
O 27 PRxxL
S
X PCOM
Position
Prox Four of the
above ccts
P9 thru P12
BNC
N28 form H2x
3 N24Vx P28
x S
7
CL
3 JD1
P PRxxH
8 S DB9
R
O 3 PRxx
X
9 L S
PCOM Where:
Refer or
P = Prox;
Keyphasor One of the above ccts for Mark VIe or S = Seismic; P13 thru P14
prox. Mark VIeS; V = Velomiter. BNC
Two of the above ccts for B/N interface. form H2x
Brd_IdR P28VR N28R Brd_IdS P28VS N28S Brd_IdT P28VT N28T
P to N P to N P to N
converter converter converter
ID WNP ID WNP ID WNP

S S S
TVBA Input Screw Assignments:
Ch. # Signal TB Ch. # Signal TB Ch. # Signal TB Ch. # Signal TB Ch. # Signal TB Ch. # Signal TB
Name Pt. Name Pt. Name Pt. Name Pt. Name Pt. Name Pt.
------- -------- ---- ------- -------- ---- ------- -------- ---- ------- -------- ---- ------- -------- ---- ------- -------- ----
N24V01 1 4 N24V04 10 N24V07 19 10 N24V10 28 13 N24V13 37 unused 46
1 7
PR01H 2 PR04H 11 PR07H 20 PR10H 29 PR13H 38 unused 47
PR01L 3 PR04L 12 PR07L 21 PR10L 30 PR13L 39 unused 48
N24V02 4 5 N24V05 13 N24V08 22 11 N24V11 31 14 N24V14 40
2 8
PR02H 5 PR05H 14 PR08H 23 PR11H 32 PR14H 41
PR02L 6 PR05L 15 PR08L 24 PR11L 33 PR14L 42
N24V03 7 6 N24V06 16 N24V09 25 12 N24V12 34 unused 43
3 9
PR03H 8 PR06H 17 PR09H 26 PR12H 35 unused 44
PR03L 9 PR06L 18 PR09L 27 PR12L 36 unused 45
TVBA Terminal Board

Customer Terminal Points
Signal Name Pin # Description

N24V01 1 -24 V power supply output feed for input #1
PR01H 2 Input #1 signal high side
PR01L 3 Input #1 signal low side

Signal Name Pin # Description
PCOM 40 -24 V power supply output feed for input #14 (used only with Bently monitoring)
SIG9 41 Input #14 signal high side (used only with Bently monitoring)
P24V9 42 Input #14 signal low side (used only with Bently monitoring)
NC 48-48 Unused
Operation
The TVBA supports 14 sensor connections:
• Eight Vibration or position (ckts 1 through 8)

• Four Position only (ckts 9 through 12)
• One Reference probe (Keyphasor) or position, (ckts 13)
• One Reference probe (Keyphasor) or position, (ckt 14) (for Bently
Nevada 3500 interface only)
Keyphasor Inputs
Vibration Inputs accommodate the following transducers:
• Proximitor
• Seismic
• Velomiter
• Accelerometers (first three inputs on PVIB or YVIB only)
Vibration signal is superimposed upon a dc bias voltage to make up the

defined input voltage range from table 1.
• Add a -11 V dc, ±5%, bias to the B/N buffered signal
When configured for seismic transducer:
• Add a negative bias to the input for open circuit detection

• Open the PRxxL signal to allow a true differential reading and meet
common mode rejection requirements
The open circuit reading for the gap voltage (dc component) has the following value:
• Prox, Accel, Velomitor more positive than -1.0 V dc

• Seismic more negative than -15 V dc
Position Inputs open circuit reading for the gap voltage (dc component)
has a value more positive than -1.0 V dc.
Phasor Inputs open circuit reading for the gap voltage (dc component)
has a value more positive than -1.0 V dc.

Probe Power Supplies
Each channel provides a -24 V power supply. The supply is capable of producing a
maximum of 12 mA. The supply is current limited to meet Class 1, Div. 2 requirements.
Output: -24.5 V (-23 to –26)

Iout: 12 mA maximum
Buffered Outputs
Each channel provides additional outputs other than the standard 37-pin connection.
The signal output is a buffered version of the monitored signal. Each channel is output
on a BNC connector. Each channel is also output through a 25-pin (Vib/Position)
or 9-pin (Keyphasor) connector designed to interface with the Bently Nevada 3500
monitoring system. Requirements on the buffers are as follows:
• Amplitude accuracy 0.1%

• Add a -11 V dc, ±5%, bias on seismic signals
• Sink 3 mA when interfacing with a Velomitors
• Unity-gain buffered output drives an impedance of 1500 Ω, capacitive up to 1000
pF, with less than 10% overshoot for DB9 and DB25 connectors.
• The buffered outputs drive both DB25, DB9, and BNC coaxial connectors in
parallel. Both the center pin and the shell of the BNC are resistively isolated
from the DB connectors. The isolation is sufficient that the DB connector's
voltage remains within spec if the BNC connector is shorted.
• BNC output drives an impedance of 2E+06 ohm or higher.
WNPS Power Supply Daughterboard

Three redundant external power supplies provide the power for the TVBA. If one power
supply goes down, the offline power supply can be replaced without bringing down the
terminal board. To maintain this feature, the TVBA has three removable daughterboards
to provide +28 to -28 V power converters. The daughterboards can be removed while the
TVBA is online by disconnecting the I/O pack power (R, S, or T), and removing the
WNPS. The daughterboards must be mounted to meet all vibration and seismic standards.
The WNPS uses the corresponding channel (R, S, or T) 28 V bus to manufacture the
required power for the vibration probes and on any board chips requiring power. A
monitor feed for each -28 V supply should be fed back to the I/O pack for monitoring.
The TVBA combines three -28 sources using diodes from the daughterboards to
create the TVBA N28 bus. A TVBA configured with the TMR daughterboards
provide enough current to supply 14 Proximitors at 18 mA, 14 buffered outputs at
12 mA, with one channel shorted at approximately 200 mA for a total of 540 mA
without failure. Current sharing by the supplies make this condition possible. A
TVBA with a single WNPS is not expected to handle this condition.
Electrical Characteristic:
Input: 28 V ±5%
Output: -28 V ±5%
Output Ripple: 1% of dc value
Iout: 400 mA maximum

Specifications
Requirement Limits
Vibration Input Options
Number of channels supporting vibration probes (Proximitor, Seismic, or Velomitor) 8
Number of channels with selectable pull up of ±28, or constant current. 8
Number of channels with PRxxL Open/Pcom jumper (Seismic support) 8
Number of buffed outputs with selectable bias (Seismic support) 8
Power Supply
Number of N24 outputs 14
N24 voltage -24.5 normal
(-23 to -26) V dc
N24 maximum current 12 mA
Buffered Outputs
Number of buffered outputs 14
Amplitude accuracy ±0.1%
Amplitude accuracy at DB connectors with BNC shorted ±0.1%
DB9 and DB25 Connectors ability to drive load Min. 1500 Ω,
Max 1000 pF
w/ <10% overshoot
BNC Connectors ability to drive load Min. 2E+06 ohms
Max. 1000 pF
W/ < 10% overshoot
WNPS
N28 voltage 28 normal
(-26.6 to -29.4) V dc
N28 ripple 280 mV pk (1%)
N28 maximum current 400 mA
Operating temperature -30 to 65ºC (-22 to 149 ºF)

Diagnostics
• The board provides the open circuit detection for each vibration input.
The I/O processor creates a diagnostic alarm (fault) if any one of the
inputs has an out-of-range voltage.
Configuration
Jumper settings for TVBA as follows:
Jumpers J1A through J8A
• Seismic (S) N28 high-impedance bias for open-circuit protection

• Prox or Accel (P, A) P28 high-impedance bias for open-circuit protection
• Velomitor (V) 3 mA constant current N24 voltage source select
Jumpers J1B through J8B
• Prox, Velomitor or Accel (P, V, A) bypass dc blocking capacitor for BN outputs

• Seismic (S) select dc block capacitor for BN outputs
Jumpers J1C through J8C
• PCOM provides N28 return path for power supply

• OPEN no N28 return path through terminal board
All other configuration is for PVIB is done from the toolbox. For the location
of these jumpers, refer to the installation diagram.

Notes

PDM Power Distribution Modules
Power Distribution Modules (PDM)

The Power Distribution Modules (PDM) are designed specifically for the Mark* VIe
system. The PDM uses individual boards to accept and condition primary control
power inputs of 125 V dc, 48 V dc, 24 V dc, and 115/230 V ac for use in redundant
combinations. Applied power is distributed to system terminal boards for use in field
circuits and converted to 28 V dc for operation of the Mark VIe I/O packs. The term
PDM is used as a name for all of the individual pieces forming the power distribution
for a system. The PDM is divided into two different categories:
Core distribution circuits are a portion of the PDM serving as the primary
power management for a cabinet or series of cabinets. Input power from one
or more sources is received by a corresponding module or board. The power is
distributed to terminal boards and one or more bulk power supplies producing
28 V dc power to operate the control electronics. The 28 V power is monitored
and distributed by one or more 28 V output boards.
Ac input power is received by a JPDB module. JPDB accepts two independent ac

sources. Dc input power is managed by JPDE (24 V/48 V) and JPDF (125 V).
The 28 V dc control power output board (JPDS or JPDM) hosts a PPDA I/O pack
providing system feedback. Ribbon cables can daisy chain other core boards in the
system to the board holding the PPDA I/O pack. The PPDA produces system feedback
signals for all power bus voltages, branch circuit status, ground fault detection, and
bulk power supply health. Complete monitoring and system feedback sets this power
system apart from conventional methods of power distribution.
Bulk power supplies are considered a part of the core PDM system.
Branch circuit boards split the power output from the PDM core components into
individual ac and dc circuits for use in the cabinets. Branch circuits do not connect to
the PPDA I/O pack for system feedback. Elements receiving power from the branch
circuits provide their own power status feedback signals to the control system. Branch
circuit elements are usually single circuit boards rather than modules.
GEH-6721L PDM Power Distribution Modules System Guide 26-1

RST
Control JPDP
System JPDS or JPDM Power
PPDA
Feedback 28 V Control Power
R S T JPDL
PS PS PS Pack
RST
24/48 V Pwr Supply

JPDE Dc
24/48 V Pwr Supply JPDD
24VDC Power
24/48 V Pwr Supply
Dc
JPDD Power
sources. JPDB, JPDE , and JPDF

do not connect simultaneously .
Dc Power
PS runs f rom one of three

Ac Power JPDR Distribution Boards
Selector Board Select1 of 2
Local Ac Power
Distribution Boards
Ac Input
JPDB Ac
115/230VAC JPDA
Power
x2
Ac Input
Ac
JPDA
Power
JPDD Dc
JPDF
125 V Battery Power
125VDC
Dc
JPDD
Power
Core Circuits Branch Circuits

DACA
DACA
Ac to Dc
Converter Modules
Power Distribution Module (PDM) Basic Layout

Operation
Core Components
Core components of the PDM receive primary control power inputs of 125 V dc, 24 V dc,
and 115/230 V ac for use in redundant combinations. These components are identified as:
• IS220PPDA I/O pack – The power diagnostic pack mounts on a JPDS, JPDM,
or a JPDC board. Ribbon cables are used to daisy chain other core boards to
the board hosting the PPDA. The pack can identify connected core boards and
pass feedback signals to one or two IONet connections. PPDA has numerous
indicator LEDs providing visual power distribution system status.
• IS2020JPDB ac module – The JPDB module consists of a sheet metal structure
containing two sets of input line filters and an IS200JPDB circuit board. Power input
from two separate ac sources passes through the line filters to the JPDB board. The
board provides output for bulk 28 V dc control power supplies, terminal boards, and
other loads. There are two versions of the IS200JPDB board: IS2020JPDBG2 has
provisions for the connection of an external ac selector module and IS2020JPDBG1
omits this feature. The JPDB board uses ribbon cable connections for system feedback
through PPDA including both ac bus voltages and individual branch circuit feedback.
• IS2020JPDC combination board - The JPDC combines input and output functions
from several designs to provide distribution of 125 V dc, 115/230 V ac, and 28 V dc
to other boards within a turbine control system. The JPDC module consists of a
sheet metal structure containing diode assembly, two resistors, and a JPDC board. It
provides a single 115/230 V ac connection at the bottom, one or two 125 V dc battery
input connections, and up to three separate 28 V dc source connections.
• IS200JPDE 24/48 V dc input board – The JPDE board mounts on a sheet metal
structure. Power input is accepted from a battery and two dc power supplies. It could
be provided with an optional dc circuit breaker and filter when using a battery power
source. The JPDE board distributes the dc power to terminal boards and other loads.
In small systems, JPDE could be used between a battery and 150 W dc power supplies.
The JPDE board uses ribbon cable connections for system feedback through PPDA
including dc bus voltage, ground fault detection, and individual branch circuit status.
• IS2020JPDF 125 V dc module – The JPDF module consists of a sheet metal structure
containing a dc circuit breaker, input filter, series diode, current limiting resistors,
and an IS200JPDF circuit board. Power from a 125 V dc battery feeds through the
circuit breaker, filter, and diode to the JPDF board. The board also has connections
for two DACA modules providing ac input/125 V dc output. When one or both
DACA modules are used, the ac is provided by a wire harness between JPDB and
JPDF. The result is a module that could accept power from a battery and / or one or
two ac sources creating a highly reliable dc supply. The IS200JPDF board distributes
dc power to bulk dc: dc supplies, terminal boards, and other loads. Two special output
circuits, with series current limiting resistors, are provided for specific applications.
The JPDF board uses ribbon cable connections for system feedback through PPDA
including dc bus voltage, ground fault detection, and individual branch circuit status.
• IS200JPDM 28 V dc control power output board – JPDM is similar to JPDS
except it has fewer output connectors and includes branch circuit fuses. JPDM is
used for systems requiring 28 V dc supplies with current limit exceeding branch
circuit capability. This includes systems that use two or more 500 W systems
connected together forming a redundant control power source.

• IS200JPDS 28 V dc control power output board – The JPDS board mounts on a
sheet metal structure. Provisions are made supporting a PPDA I/O pack mounted
on the JPDS circuit board. The JPDS circuit board contains three independent 28
V dc power buses with one bulk power supply input for each bus. Barrier screw
terminals connect the power buses when a single bus with multiple supplies is
desired. Output circuits from JPDS do not contain fuses with the exception of
three auxiliary circuits. The JPDS board design depends on the current limit of the
attached power supplies for branch circuit protection. The JPDS board uses ribbon
cable connections for system feedback through PPDA including dc bus voltage,
power supply status contact feedback, and auxiliary circuit status.
Note PPDA does not take direct protective actions. It only reports information to the
system controllers where corrective action can be programmed.
• DACA ac to dc conversion module – This module takes incoming ac power and

converts it to 125 V dc. It is used in conjunction with or in place of 125 V battery power.
DACA provides capacitive energy storage for power-dip ride through when required.
• PS control power supplies – There are six different control power supplies
used on the Mark VIe. There are two power supply ratings; 150 W and 500 W
for voltage inputs of 24 V dc, 125 V dc, and 115/230 V ac.
Status Feedback
The Mark VIe controller uses a PPDA I/O pack for system feedback. The core JPDx
boards can function without a working connection to the PPDA making it a non-critical
element of the system. There are no provisions for PPDA redundancy without using
a fully redundant set of JPDx boards. The PPDA pack provides timely information
supporting system maintenance. PPDA provides five analog signal inputs with an
electronic ID for each connected core PDM component. PPDA checks the ID lines to
determine what boards are attached and then populates the corresponding signal space
values. PPDA also operates local indicator lamps showing system status.
Branch Circuit Boards

Branch circuit boards JPDP, JPDL, JPDA, and JPDD provide additional distribution
of dc/ac power for output of the core PDM elements. These boards are not connected
to the PPDA feedback cable. Branch circuit boards are identified as:
• IS200JGND – JGND is used with terminal boards when field wire grounding
is kept separate from the terminal board ground.
• IS200JPDA – The JPDA board is used to distribute a single ac power output
into multiple loads. This board has four switched ac outputs. Each load has
a switch, for maintenance purposes, and a fuse on the line side with LEDs
for each load. JPDAG1A has 15 A fuses for wire protection. JPDAG3A
has empty fuse holders accepting a ¼ in x 1- ¼ in fuse.
• IS200JPDD – The dc power distribution board (JPDD) board is used to distribute a
single dc power output into multiple loads. It can be used with a single input of
24 V, 48 V, or 125 V dc. Each load has a switch for maintenance purposes and
fuses with a local indicator light. JPDDG1A has 15 A fuses for wire protection.
JPDDG3A has empty fuse holders accepting a ¼ in x 1- ¼ in fuse.

• IS200JPDL – The JPDL board provides two control power I/O pack power output
connectors for each of the R, S, and T power sources. JPDL can be connected in
series with other JPDL boards providing power to a vertical column of terminal
boards and their associated I/O packs. Each output is protected with a self-resetting
fuse that is coordinated with the wire size the pack connectors can accept.
• IS200JPDP – The local power distribution board (JPDP) receives R, S, and T power
from the 28 V control power board (JPDS or JPDM) and distributes it to the local
pack power distribution board (JPDL). JPDP contains no fuses or indicators.
Valid PDM Core Card Combinations
JPDC terminal board combines PPDA can receive feedback from as many as six connected core PDM components.
functionality of JPDM, JPDB, The following rules apply when cabling components into a PPDA:
and JPDF terminal boards.
• JPDS, JPDM, or JPDC is selected as the power distribution main
board that hosts a PPDA I/O pack.
• A maximum of six boards can be used with a single PPDA I/O pack.
• When used, a single JPDM or JPDC board counts as two boards due to
the large number of PPDA feedback signals used.
• Either JPDM or JPDS can be used. The two board types cannot be mixed in a system.
• A maximum of two of any given board type can be used.
The following figure shows all possible combinations for JPDS, JPDM
and JPDC terminal boards.
PDM Main Boards
JPDS JPDM JPDC

JPDS (2 nd) JPDM (2 nd) JPDE (1 st )
JPDE (1 st ) JPDE (1 st ) JPDE (2 nd)
JPDE (2 nd) JPDE (2 nd) JPDF (1 st )
Auxiliary
boards JPDF (1 st ) JPDF (1 st ) JPDB (1 st )
supported by
individual
m ain board
JPDF (2 nd) JPDF (2 nd) Max four auxiliary
boards can be
JPDB (1 st ) JPDB (1 st ) connected to m ain
JPDC board at any
given tim e
JPDB (2 nd) JPDB (2 nd)
Max five auxiliary Max four auxiliary
boards can be boards can be
connected to m ain connected to m ain
JPDS board at any JPDM board at any
given tim e given tim e
With a second JPDM,
only two m ore
auxiliary boards can
be added
Core Card Combinations

Circuit Protection
Circuit protection for the Mark VIe PDM includes:
• Fault current protection limits the current to the capability of the system components.
• Branch circuit system feedback
• Ground fault protection in floating systems
• Redundant applications, if possible
Connector Conventions
Systems using multiple power applications create the possibility of making wrong
connections such as applying the wrong power to a load or interconnecting power
buses. The Mark VIe PDM use specific connector conventions to eliminate this
problem. The specific connectors are shown in the following table.
Power from main PDM Connector

125 V dc from JPDF to JPDD 2 pin Mate-N-Lok®
125/230 V ac from JPDB to JPDA 3 pin Mate-N-Lok
24/48 V dc from JPDE to JPDD 4 pin in-line Mate-N-Lok
28 V dc control power from JPDS to JPDP 3x2 pin Mate-N-Lok
28 V dc control power from JPDP to JPDL 5 pin in-line Mate-N-Lok
Dc power supply output to JPDE, JPDS, JPDM 3x3 pin Mate-N-Lok (power + status)
DACA connection to JPDF 3x4 pin Mate-N-Lok
Exceptions to the above table exist. An effort has been made to clearly mark the connector
function on the boards. For example: a 5-pin in-line Mate-N-Lok connector is used on
JPDB and JPDF to pass ac power between the boards. Both connectors are clearly marked
for their intended use and are physically placed to ensure proper connection.
Existing terminal boards designs present the greatest risk of being improperly
connected. These boards use a three position Mate-N-Lok for power input regardless
of whether it is an ac or dc connection. The existing boards also have two parallel
connectors to allow power daisy-chain wiring within a panel.
The JPDF board can detect an improper wiring connection, such as applying ac power
on a floating 125 V dc battery buss, and report it through the PPDA I/O pack.

P28 Control Power Protection
JPDS/JPDM control power characteristics are as follows:
• The negative side of JPDS/JPDM is grounded at every I/O pack to FE. This
grounding aids in the conduction of transient noise to earth.
Note It is impossible to float the JPDM/JPDS power supply.
• The supply voltage provided by the approved power sources can be 28 V ±5%.
• The I/O packs are designed with minimal power disturbance ride-through capability.
• Bulk energy storage is provided by the control power supplies.
• Control power cannot be used for tasks such as contact wetting for field inputs. External
connections are controlled and filtered by the terminal board/pack combination.
• JPDS/JPDM, JPDP, and JPDL support independent control power systems for
each controller and associated I/O pack. A redundant control system maintains
a separation of control power ensuring system reliability.
System Monitoring
Incoming power is monitored as follows:
• Incoming power is monitored by every I/O pack. An alarm will signal any
incoming power that falls below 28 V – 5%. The control can continue
to operate depressed voltage in most cases.
• Depressed voltage effects are dependent on the connected field
devices. Determining the voltage required for failure can only be
accomplished if the entire system is analyzed.
• A second alarm will be sounded if the control power falls below 16 V. The 16 V
alarm can help isolate the source of failure during further analysis.
• JPDS and JPDM provide voltage monitoring for R, S, and T power buses.
• Mark VIe power supplies include a dry contact status feedback circuit. This contact
will be closed when the power supply is operating normally and will open if it is not.
The controller reads the status signals as a Boolean value. These values are necessary
when multiple supplies are connected in parallel for redundant systems. They provide
the only way to determine when one supply is not functioning correctly.
• The JDPM monitors all fused output branch circuits and indicates a fuse failure.
• Both JDPM and JPDS power supplies provide four test points, with current limited
by 10 kΩ series resistors, used to connect external test equipment.

Branch Circuit Protection
Branch circuit protection, starting at the terminal board and working back
toward the power source is shown below:
• Terminal boards supplying output power to field devices provide individual branch
circuit protection using a small three terminal regulator. The regulator includes a
thermal shut down feature that responds quickly to any overload condition.
• All I/O packs have a fast acting solid-state circuit breaker at the power input
point. This breaker ensures that any problem with a connected terminal
board can not propagate to other system components.
• The pack circuit breaker is used as a soft-start feature for the pack. Hot-plugging
the 28 V dc power into a pack results in a very gradual turn-on of the pack.
This ensures no other system component can be affected.
• The JPDL includes a self-recovering fuse coordinated with the wiring to the pack.
This device limits current in the event of a short circuit or failure of the protection
within the pack. The fuse can protect the wiring, but it doesn’t always act fast
enough to prevent disturbance of other packs on the same power bus.
• The JPDP board uses only copper conductors and connections. It can
carry the same circuits as the JPDL.
• The JPDM board uses individual branch circuit fuses in the positive
output to the JPDP board. These fuses can protect wiring and circuit
boards between JPDM and the protection on JPDL. Auxiliary outputs are
protected by self-resetting devices rated at 1.4 A.
• The JPDS board does not use fuses like JPDM. The board is rated for Class I
Division 2 (potentially explosive atmosphere) and the use of fuses is not desired.
The JPDS wiring is protected by self-restarting devices rate at 1.4 A.
• Each power supply has current limiting on the output. Current limiting is sufficient to
protect the wiring through the JPDP and JPDL when a single 500 W power supply or
up to three 150 W supplies are wired together to power a system bus. When JPDS
is used for distribution, this current limit protects branch circuit wiring. Multiple
supplies, exceeding 500 W, use JPDM or JPDS with external fuses.
Distribution component design provides control power branch circuit protection.

Specific areas that require monitoring are:
• Supply current limit protecting wiring cannot exceed 500 W. The maximum
allowable wire size must be used in the Mate-N-Lok connectors.
• Maximum allowable wire sizes must also include wiring to Ethernet
switches and control rack power supplies.
• Parallel supplies, yielding a total capability greater than 500 W, must use
JPDM or JPDS with external branch circuit protection.

Ac Power Protection
Specific characteristics of ac power distribution components are:
• Ac power distribution components are designed for using a grounded neutral supply.
• By design, the JPDB board can not be damaged if the line and
neutral connections are reversed.
• JPDB and JPDA boards have fuses in the line side only. Reversing the connections
between line and neutral can eliminate series circuit protection.
• An ac power source, similar to US domestic applications could have a 230
V ac winding with the grounded neutral on a center tap. In this case, both
neutral connections of the JPDB must be wired.
• The connectors on JPDB are arranged on the board edge in an AC1, AC2, AC1, and
AC2 pattern. A wire harness can be created to pick up line connections from two
adjacent connectors yielding 230 V ac from dual 115 V ac feeds. This arrangement
puts a fuse on both line connections for proper circuit protection.
Note The preceding items do not apply when using a 230 V ac input power source
with a grounded neutral connection.
• JPDB is designed with sufficient voltage clearance between the two ac

inputs, such as two 208 V or 230 V, from a three-phase source and
cannot cause voltage clearance problems.
• JPDB uses input filtering to provide a transients known and controlled
voltage environment for the circuit board. These filters are part of JPDB
module and no additional filters are required.
• JPDB delivers 10 A per ac input to both the DACA feed JAF1 and protected
branch circuit outputs for a total of 20 A per ac input.
System Monitoring
System monitoring is provided as follows:
• JPDB provides ac voltage magnitude feedback for both input circuits.

• JPDB provides on/off value system feedback for all switched or
fused branch circuit outputs.
• JPDA provides a visible LED indicator all four switched/fused branch circuit outputs.
• JPDB provides test point outputs from the two ac inputs for connection of external
test equipment. Each test point has a series current limiting 100 kΩ resistor.

Branch circuit protection for ac power distribution components is as follows:
• JPDB inputs must be protected by a maximum 30 A circuit breaker

with normal trip characteristics.
Note Using a slow trip circuit breaker or one rated more than 30 A could cause
damage to the board in the event the breaker must be opened.
• JPDB is designed for a grounded neutral ac connection. Voltage clearances

on the neutral circuit are the same as the line inputs. This prevents
board damage from incorrect connections.
• JPDB includes a 5 A fuse on the line side of each output. This fuse was selected
to coordinate with the output switch maximum current rating.
• Two un-switched fused outputs have a 5 A fuse while the board artwork and
connector list a 10 A fuse. This was done so all the board fuses have the same
value and reduces errors of replacing fuses with the wrong sizes.
• JPDB is designed to deliver 10 A continuously to two DACA modules
connected through JAC1 and JPDF.
• JPDA has four switched ac outputs with a fuse in the line side. The board is
powered from JPDB through one of the 5 A fused branch circuits. The switch used
on JPDA is the same as used on JPDB. Both switches use a 5 A fuse. JPDA uses
15 A fuses. JPDA is connected to JPDB and any occurring fault can open the
fuse on JPDB first. JPDB is connected to the system through PPDA. JPDAG2A
has empty fuse holders accepting 5 mm X 20 mm fuses and features a black fuse
holder cap. JPDAG3A has empty fuse holders accepting a ¼ in x 1- ¼ in fuse.
Both JPDAG2A and JPDAG3A allow the use of a JPDA board with custom fuse
rating that is coordinated with a load device limited to less than 5 A.
• JPDA should be used with a power feed of a fused 5 A JPDB feed. JPDA fusing
applications should be addressed if other power feeds are used.

125 V dc Power Protection
Characteristics for using a 125 V dc battery as a power source for the PDM are as follows:
• A nominal 125 V dc battery is used as a dc power source for the Mark VIe PDM system.
• The maximum voltage the dc battery can feed to the system is 145 V dc.
Note The Mark VIe control can go into over-voltage shutdown should the supplied dc
power exceed 145 V dc.
• The 125 V dc input to 28 V dc output supply, used to supply control electronics, can
function down to 70 V dc. Field devices must be reviewed on an individual basis.
• The 125 V dc battery must be floating with respect to earth. This arrangement
eliminates a hard ground on both the positive and negative bus. A single
ground fault applied to the system can pass current defined by the centering
resistor value and dc bus magnitude. Shift in bus voltage, in respect to
earth, can then be detected to indicate a ground fault.
• Ground fault current in a floating battery system is defined by the fixed centering
resistance value. The Mark VIe system is classified as Non-hazardous Live
because the ground fault current is below dangerous levels. JPDF is designed
so that when using provided centering resistors (JP1 in place), the resulting
ground resistance in within Non-hazardous Live requirements. When two
JPDF boards are wired in parallel for greater current capacity or branch circuit
count, only one set of centering resistors should be used.
• When JPDF centering resistors are not used and voltage centering is provided by other
means, calculation of centering impedance must allow for the fixed voltage attenuators,
1,500,000 Ω resistors, between the positive bus and earth and the negative bus and
earth on JPDF. The resistors provide attenuated bus voltage feedback to PPDA. All
other branch circuit feedback signals use isolating devices that do not a path to ground.
• JPDF applications with dc input filtering yield a transients known and controlled
environment for the board voltage clearance class. Required filtering is provided
as part of the JPDF module. No additional input filters are needed.
• The DACA module is designed to coordinate power delivery with a 125 V dc
battery. One or two DACA modules, powered by a reliable ac power source,
could be used to provide backup power in the event of battery failure.
System Monitoring
Monitoring for the 125 V dc power systems is as follows:
• JPDF provides voltage magnitude feedback through PPDA for positive and negative
dc voltage with respect to earth. The difference between the two signals equals
the bus magnitude. The difference between the two bus voltage magnitudes could
be used to detect a system ground fault in a floating system.
• JPDF includes additional circuitry on the bus voltage feedback that detects ac current.
PPDA can issue an alarm when a JPDF board shows more 30 V ac on the dc bus.
• JPDF has a visible LED for each switched and fused branch circuit outlet.

Branch circuit protection for the 125 V dc power system is as follows:
• The JPDF module has a 30 A dc circuit breaker in the input power feed
to ensure correct input power protection.
• JPDF has 5 A fuses on both sides of the J1 R, S, and T output branch circuits. The
fuses coordinate with the rating of the switches provided with these outputs.
• JPDF has 5 A fuses on both sides of the J7 X, Y, and Z output branch
circuits. The fuses coordinate with the rating of the switches provided with
these outputs. There is a series 1 Ω resistor in each leg, with the same
rating as the switches, provided with these outputs.
• JPDF has 12 A fuses on both sides of the J8A and J8B output branch
circuits. The connector uses 12 AWG wire.
• JPDF has 3 A fuses on both sides of the J12 output branch circuit. The J12 circuit
has 22 Ω resistors in series limiting fault current to [ ] V dc/44 A.
• JPDD has six switched and fused dc outputs. The board is powered by JPDF. The
fuses on JPDD are 15 A. The board is fed by a 5 A branch circuit from JPDF.
JPDF is visible to the system through PPDA. A fault on the JPDF circuit cannot
result in opening the 15 A fuses on JPDD. JPDDG2A has empty fuse holders
accepting 5 mm x 20 mm fuses with a black fuse holder cap. JPDDG3A has empty
fuse accepting ¼ in x 1- ¼ in fuses with a gray fuse holder cap.
24/48 V dc Power Protection

Characteristics of the 24 V dc power protection system is as follows:
• 24 V dc power distribution is a utility system using a 24 V nominal dc battery. A typical

ac system uses one or more dc power supplies for contact wetting and relay outputs.
• The maximum allowable battery voltage is 36 V dc. The Mark VIe
controller can initiate over-voltage shutdown when the battery output
voltage exceeds the allowable limit.
• The 24 V dc input to 28 V dc output powers Mark VIe control electronics.
• The 24 V dc battery has no hard ground on either the positive or the negative dc bus.
A high resistance from the positive and negative dc is applied to earth in order to
center the bus on earth. A single ground fault applied to this system can pass current
defined by centering resistor value and dc bus magnitude. The shift in voltage, with
respect to earth, can be detected and signal the presence of a ground fault.
• The JPDE board provides centering resistors selected by using J1. In the
event the battery has external centering resistors on the battery bus, J1 could
be eliminated to avoid higher ground fault currents.
• The JPDE board is designed application using dc input filtering.
Additional input filters are not needed.
Characteristics of the 48 V dc power protection system is as follows:
• The JPDE can be configured to operate correctly using 48 V dc

input power for power distribution.

PPDA Power Distribution System Feedback
The Power Distribution System Feedback (PPDA) pack accepts inputs from up to
six different power distribution boards. It conditions the board feedback signals and
provides a dual redundant Ethernet interface to the controllers. PPDA feedback
is structured to be plug and play uses electronic IDs to determine the power
distribution boards wired into it. This information is then used to populate the
IONet output providing correct feedback from connected boards.


Compatibility
The PPDA I/O pack is hosted by the JPDS, JPDM, JPDG, or JPDC 28 V dc control
power boards on the Mark* VIe Power Distribution Module (PDM). It is compatible
with the feedback signals created by JPDB, JPDE, and JPDF.

Installation
¾ To install the PPDA pack
2. Directly plug the PPDA I/O pack into the terminal board connectors. The PPDA I/O
pack mounts on a JPDS, JPDM, or JPDC 28 V dc control power terminal board.
6. Configure the I/O pack as necessary. See also the Auto-Reconfiguration section.
7. Connect ribbon cables from connector P2 on JPDS, JPDM, or JPDC to daisy
chain other core boards feeding information to PPDA.
Note Additional PDM feedback signals may be brought into the PPDA I/O pack
through the P2 connector on the host board. The P1 connector is never used on a
board that hosts the PPDA I/O pack, PPDA must always be at the end of the feedback
cable daisy chain.

Wizard again.

Signal Routing
The PPDA I/O pack is mounted to either a JPDS, JPDM, or a JPDC board. Additional
boards are connected using 50-pin ribbon cable jumpers that are wired pin 1 to pin 1.
Each board contributes one feedback group to PPDA. This connection passes through
up to five previous boards. The following drawing shows this hookup.
JPDR JPDB JPDF JPDS
PPDA
Local Local Local Local
Fdbk Fdbk Fdbk Fdbk
P1
P1
P1
P1
P2
P2
P2
P2
A A A A
B B B B
C C C C
D D D D
E E E E
F F F F
PPDA Basic Hookup Diagram
In the above figure, feedback groups are shown as bold lines and connectors
P1 and P2 of each board are shown. From right to left, the JPDS board hosts
the PPDA I/O pack and hookups are as follows:
• Local feedback from JDPS is on signal group A

• Feedback from JPDF is on signal group B
• Feedback from JPDB is on signal group C
• Feedback from JPDR is on signal group D
• An Additional board would use signal group E
JPDM uses two sets of feedback signals due to the large number of feedback
lines from that board. JDPM does support the use of two boards. The
arrangement would look like the following:
JPDB JPDF JPDM JPDM
PPDA
Local Local Local Local
Fdbk Fdbk Fdbk Fdbk
P1
P1
P1
P1
P2
P2
P2
P2
A A A A
B B B B
C C C C
D D D D
E E E E
F F F F
PPDA Wiring Using Two JPDM Boards

Operation


Status LEDs
Processor LEDs

present
LED Status

ATTN
or module.
ATTN
every 4 sec

Additional LEDs
LED Color Description Variable

Pb R Yellow Pbus R is in Regulation Pbus_R_LED
Pb S Yellow Pbus S is in Regulation Pbus_S_LED
Pb T Yellow Pbus T is in Regulation Pbus_T_LED
RSrc Yellow All R Pbus Sources OK Src_R_LED
SSrc Yellow All S Pbus Sources OK Src_S_LED
TSrc Yellow All T Pbus Sources OK Src_T_LED
Aux Yellow Aux 28 outputs OK Aux_LED
125V Yellow 125 V battery volts OK Batt_125V_LED
125G Yellow 125 V battery floating Batt_125G_LED
125D Yellow 125 V JPDD feeds OK JPDD_125D_LED
125P Yellow 125 V Pbus feeds OK Pbus_125P_LED
App1 Yellow Application driven App_1_LED
24V Yellow 24/48 V battery volts OK Batt_24V_LED
24G Yellow 24/48 V battery floating Batt_24G_LED
24D Yellow 24/48 V JPDD feeds OK JPDD_24D_LED
24P Yellow 24/48 V Pbus feeds OK Pbus_24P_LED
AC1 Yellow Ac input 1 OK AC_Input1_LED
AC2 Yellow Ac input 2 OK AC_Input2_LED
ACA Yellow Ac JPDA feeds OK AC_JPDA_LED
ACP Yellow Ac Pbus feeds OK AC_Pbus_LED
JPDR Yellow JPDR Src Select OK JPDR_LED
Fault Red Fault Led - Application driven Fault_LED

Diagnostics
The PPDA performs the following self-diagnostic tests:
• A power-up self-test including checks of RAM, flash memory, Ethernet

• A check of the electronic ID information from the terminal board, acquisition card, and
processor card confirming the hardware set matches, followed by a check confirming
the application code loaded from flash memory is correct for the hardware set
scan. Measured values are compared against expected values and are used
to confirm health of the A/D converter circuits.
• Details of the individual diagnostics are available from the ToolboxST*
application. The diagnostic signals are individually latched, and then reset
Configuration
The PPDA I/O pack uses configuration values for operation with desired
PDM boards. The ToolboxST* application provides the correct options for the
version of PDM hardware in use in a given system. A brief summary of the
types of configurations encountered are as follows:
• JPDB: The nominal voltage magnitude is selected, the magnitude tolerance specified,
and a correction factor for neutral voltage is provided for each of the two ac buses.
Each of the switched branch circuit fuse status can be turned on or off.
• JPDE: The 24 V bus magnitude and centering tolerance can be configured, and the
diagnostic associated with switched branch circuit fuse status can be turned on or off.
• JPDF: The 125 V bus magnitude and centering tolerance can be configured, and the
diagnostic associated with switched branch circuit fuse status can be turned on or off.
• JPDR: The expected voltage magnitude is specified.
• JPDS / JPDM: The PPDA needs to know if P28R, S, and T can be present
in a system. If it is indicated that one is not present, the low voltage
diagnostics for that power bus can be turned off.
• PPDA: The I/O pack needs to know what PDM boards are in the diagnostic daisy chain.

Variable Definitions

L3DIAG_PPDA_R I/O Diagnostic Indication Input Bool
L3DIAG_PPDA_S I/O Diagnostic Indication Input Bool
L3DIAG_PPDA_T I/O Diagnostic Indication Input Bool
LINK_OK_PPDA_R I/O Link Okay Indication Input Bool
LINK_OK_PPDA_S I/O Link Okay Indication Input Bool
LINK_OK_PPDA_T I/O Link Okay Indication Input Bool
ATTN_PPDA_R I/O Attention Indication Input Bool
ATTN_PPDA_S I/O Attention Indication Input Bool
ATTN_PPDA_T I/O Attention Indication Input Bool
PS18V_PPDA_R I/O 18 V Power Supply Indication Input Bool
PS18V_PPDA_S I/O 18 V Power Supply Indication Input Bool
PS18V_PPDA_T I/O 18 V Power Supply Indication Input Bool
PS28V_PPDA_R I/O 28 V Power Supply Indication Input Bool
PS28V_PPDA_S I/O 28 V Power Supply Indication Input Bool
PS28V_PPDA_T I/O 28 V Power Supply Indication Input Bool
IOPackTmpr_R I/O pack Temperature (deg °F) AnalogInput REAL
IOPackTmpr_S I/O pack Temperature (deg °F) AnalogInput REAL
IOPackTmpr_T I/O pack Temperature (deg °F) AnalogInput REAL
Pbus_R_LED Pbus R is in Regulation Input Bool
Pbus_S_LED Pbus S is in Regulation Input Bool
Pbus_T_LED Pbus T is in Regulation Input Bool
Src_R_LED All R Pbus Sources OK Input Bool
Src_S_LED All S Pbus Sources OK Input Bool
Src_T_LED All T Pbus Sources OK Input Bool
Aux_LED Aux 28 outputs OK Input Bool
Batt_125V_LED 125 V battery volts OK Input Bool
Batt_125G_LED 125 V battery floating Input Bool
JPDD_125D_LED 125 V JPDD feeds OK Input Bool
Pbus_125P_LED 125 V Pbus feeds OK Input Bool
Batt_24V_LED 24/48 V battery volts OK Input Bool
Batt_24G_LED 24/48 V battery floating Input Bool
JPDD_24D_LED 24/48 V JPDD feeds OK Input Bool
Pbus_24P_LED 24/48 V Pbus feeds OK Input Bool
AC_Input1_LED Ac input 1 OK Input Bool
AC_Input2_LED Ac input 2 OK Input Bool
AC_JPDA_LED Ac JPDA feeds OK Input Bool
AC_Pbus_LED Ac Pbus feeds OK Input Bool

JPDR_LED JPDR Src Select OK Input Bool
Accelerometer_X Vibration input, X-coordinate AnalogInput REAL
Accelerometer_Y Vibration input, Y-coordinate AnalogInput REAL
App_1_LED Application driven Output Bool
Fault_LED Fault Led - Application driven Output Bool
Board Type Description Selections

JPDC Terminal board connected to PPDA
JPDC Inputs Analog Inputs tab Variable Edit (Input float)
InputDiagEnab Disables all related diagnostics for the selected input (DC_125 Disable, Enable
VFdbkMag or ac_Fdbk1_Volt). This is typically set to Disable
when one of the inputs (125 V or ac) on the JPDC is not used.
AcFdbkInVoltage Ac input voltage threshold Range 100 – 250
AcFdbkInTol Ac input voltage feedback tolerance 0%, 5%, 10%, 20%
AcDiffVolOff Ac input voltage difference voltage offset Float value
PS28vEnable PS 28 V Feedback enable Disable, Enable
JPDC Fuse/DryContacts Fuse and Dry Contact status tab Variable Edit (Bool)
FuseDiag Enable fuse diagnostic alarm Disable, Enable

JPDS Terminal board connected to PPDA
JPDS Inputs Analog Inputs tab Variable Edit (Bool)

JPDM Terminal board connected to PPDA
JPDM Inputs Analog Inputs tab Variable Edit (Bool)

JPDE Auxiliary terminal Board Not used, 1 or 2
JPDE Inputs Analog Inputs tab Variable Edit (Input float)
InputDiagEnab Enables all diagnostic alarms for the JPDE. Should only be set Disable, Enable
to Disable if no voltage input is connected to the JPDE.
DC_24v_Trig_Volt Dc 24/48 V Input Magnitude trigger voltage configuration Range 0 – 60
JPDE Gnd Volts Variable Edit (Input float)
Gnd_Mag_Trig_Volt Ground Magnitude trigger voltage Range 1 – 30
JPDE Fuse Fuse status tab Variable Edit (Bool)

JPDB Auxiliary terminal Board Not used, 1 or 2
JPDB Inputs Analog Inputs tab Variable Edit (Input float)
InputDiagEnab Enables all diagnostic alarms for the specified input on the Disable, Enable
JPDB. Should only be set to Disable if the voltage input is not
connected to the JPDB.
AcFdbkInVoltage Ac input voltage threshold Range 100 – 250 float
AcFdbkInTol Ac input voltage feedback tolerance 0%, 5%, 10%, 20%
ACDiffVolOff Ac input voltage difference voltage offset Float value
JPDB Fuse Fuse status tab Variable Edit (Bool)

JPDF Auxiliary terminal Board Not used, 1 or 2
JPDF Inputs Analog Inputs tab Variable Edit (Input float)
InputDiagEnab Enables all diagnostic alarms for the JPDF. Should only be set to Disable, Enable
Disable if the voltage input is not connected to the JPDF.
DC_125v_Trig_Volt Dc 124 V Input Magnitude trigger voltage configuration Range 0 – 500
JPDF Gnd Volts Variable Edit (Input float)
Gnd_Mag_Trig_Volt Ground Magnitude trigger voltage
JPDF Fuse Fuse status tab Variable Edit (Bool)

DS2020DACAG2 ac-dc Power Conversion
The DS2020DACAG2 is a drop in replacement for the DS2020DACAG1. It is backward
compatible in systems that used the previous version and it should be used as a
replacement part for the previous model. The DACA converts 115/230 V ac input power
into 125 V dc output power, and the output power rating is approximately 1000 W.
A DACA is used when the primary power source for a control system is 125 V
dc with or without a battery. In addition to power conversion, DACA provides
additional local energy storage to extend the ride-through time whenever the
Mark VIe control has a complete loss of control power.
The DS2020DACAG2 model has a higher power rating than the previous
module. Also, this new model can be paralleled for greater output current,
whereas paralleling was not recommended for the previous model. The
DS2020DACAG2 is recommended for all new panel designs.
Installation
The DACA module has four mounting holes in its base. Ac power input and dc output
is through a single 12-position connector JZ that is wired into connector JZ2 or JZ3 of
the PDM. Selection of 115 V ac or 230 V ac input is made by plugging the DACA
internal cable into connector JTX1 for 115 V or JTX2 for 230 V.
Ensure the proper voltage is selected before power is

applied to the equipment.
Caution
JTX1 DACA
115 V Converter
Cable to
transformer JTX2
230 V JZ Cable to
inside DACA PDM JZ2
converter Or JZ3
DACA Module Wiring

DACA Filter Capacitor Wear Out
The electrolytic capacitors in the DACA module wear out over time due to the ambient
temperature of the environment where they are used. The following table shows the
calculated life expectancy and recommended replacement schedule for the DACA modules.
DACA Replacement Schedule
Calculated Life Expectancy of DACA Capacitor Recommended Replacement Schedule*

At 20°C (68 °F) ambient 100 years
*Due to wear out of Electrolytic Capacitor
¾ To replace a DACA power conversion module

1. Remove power from the DACA module. Allow 1 minute for the
output voltage to discharge.
2. Remove the power input/output cable (JZ) on the right side of the module top.
3. Remove the four bolts securing the DACA module to the floor of the cabinet.
4. Remove the DACA module.
5. Make note of which receptacle the capacitor power plug is in. This is on the left
side of the module top. JTX1 is for 115 V ac and JTX2 is for 230 V ac.
6. Ensure the capacitor power plug is in the same position as the one removed.
JTX1 is for 115 V ac and JTX2 is for 230 V ac.
7. Place the new DACA module in the same position as the one removed
8. Secure the DACA module to the cabinet floor with the four bolts
removed from the previous module.
9. Install the power input/output plug (JZ) on the right side of the module top
10. Restore power to the DACA module.

DACA Power Conversion Modules
Hole size for 1 / 4"

TAPTITE (4PL)
Drill Plan
Note: Keep out area is 8.65 in. x 13.9 in.

DACA Mounting Pattern

Operation
DACA receives ac power through the cable harness that is plugged into connector JZ.
DACA uses a full wave bridge rectifier and an output filter capacitor. If needed, the user
must provide an input filter to attenuate harmonic currents injected into the incoming line.
Single DACA Module, Maximum Output Current is 9.5 A dc
Input to DACA Input Current Output Voltage Output Voltage

V ac RMS at Max Load Load = 1 A dc Load = 9.5 A dc
115 V ac 11 A 119 V dc 107 V dc
230 V ac 6A
The DACAG2 can be paralleled for greater output current. In parallel operation,
current sharing between the two DACAs is critical. Uneven current sharing can
cause one of the DACAs to operate beyond its output current rating.
Two DACA Modules with Outputs Paralleled, Maximum Output Current is 16.5 A dc*
Input to DACA Input Current Output Voltage Output Voltage

V ac RMS at Max Load Load = 1 A dc Load = 15 A dc
115 V ac 20 A 120 V dc 110 V dc
230 V ac 11 A
* The two paralleled DACAs must be connected to one ac voltage source for even output current sharing.
For proper implementation of parallel DACAs, the following must be observed:
• The DACAs must be connected to the same ac source to ensure

equal input voltages to the DACAs.
• The maximum output current per DACA is derated for parallel operation. This
derating accounts for variance in DACA open circuit voltages and variance
in DACA output impedances. The following curve should be used. The
maximum recommended total panel current is 16.5 A dc.
Probability of overloading one DACA when two

DACAs are paralled; Plotted at various panel loads
exceeding 9.5 A dc rating
Probability of one DACA
Total panel Load, A dc

Specifications
Item Specification
Input Voltage 105-132 V ac or 210-265 V ac, 47 to 63 Hz
Output Voltage 90 to 145 V dc with a load of 1 to 9.5 A
Over the full range of input voltage
Output Current Rating 9.5 A dc, -30 to 45°C (-22 to 113 °F)
Linearly derate to 7.5 A dc at 60°C (140 °F)
Output Ripple Voltage 4 V p-p
Discharge Rate Nominal input of 115 or 230 V ac, no load, discharge to less than 50 V dc within 1 minute
of removal of input power.
Hold Up (time for output to V in (V ac) 105 115 132
discharge to 70 V dc with Initial Load (A dc) 9.5 9.5 9.5
constant power load) Pout (W) 882 974 1131
Hold Up Time (ms) 19.5 29.5 48.8
Temperature -30 to 60°C (-22 to +140 °F) free convection
Humidity 5 to 95%, non-condensing
UL 508C Safety Standard Industrial Control Equipment
EN 61010 Section 14.7.2 – Overload Tests
EN 61010 Section 14.7.1 – Short Circuit Test
EN 61000-4-2 Electrostatic Discharge Susceptibility
EN 61000-4-3 Radiated RF Immunity
EN 61000-4-4 Electrical Fast Transient Susceptibility
EN 61000 –4-5 Surge Immunity
EN61000-4-6 Conducted RF Immunity
EN 50082-2:1994 Generic Immunity Industrial Environment
ENV 55011:1991 - ISM equipment emissions
IEC 529 Intrusion Protection Codes/NEMA 1/IP 20
Diagnostics
Configuration
Input voltage selection is made on DACA by plugging the captive cable harness into
connector JTX1 for 115 V ac nominal input or connector JTX2 for 230 V ac nominal input.

JPDA Local ac Power Distribution
The Local ac Power Distribution (JPDA) board provides ac power distribution, power
isolation, and branch circuit protection for each control or I/O function requiring ac
power. Typical applications include ac relay and solenoid control power, ignition
transformer excitation, and contact wetting. Each output includes a fuse, a switch for
power isolation, and a lamp to indicate the presence of output voltage.
Board Versions
Terminal Board Fusing

JPDAG1 Each circuit provided with ¼ in x 1¼ in 15 A 250 V fuse
JPDAG2 Empty fuse holders with black caps accepting 5 x 20 mm fuses
JPDAG3 Empty fuse holders with grey caps accepting ¼ in x 1¼ in fuses
JPDAG1 provides fuses that are coordinated with the rating of the system
wiring and connectors. JPDAG2 and G3 are used when fuse ratings coordinated
with a specific application are required. Two different fuse sizes are provided
for to best accommodate local fuse preferences.

Installation
JPDA mounts in a plastic holder, which fits on a vertical DIN-rail.
JPDA Ac Power Distribution Board
3
Input power JAC1
120/240 V rms Indicator
3
JA1 To TRLY or
SW1
Ac load
FU1
Indicator
3
JA2 To TRLY or
SW2
Ac load
FU2
Indicator
3
JA3 To TRLY or
SW3
Ac load
FU3
Indicator
3
JA4 To TRLY or
SW4
Ac load
FU4
TB1
1
Output power Chassis

JAC2
120/240 V rms Ground
Plastic support tray for DIN-rail mounting

JPDA Cabling
Power input and output cables have three-position Mate-N-Lok connectors.

For cable destinations, refer to the circuit diagram.
TB1 is the chassis ground connection. When installing the JPDA it is

important to provide a ground lead from TB1 to the system PE. This creates
a ground path for the metal switch bodies.

Operation
The following figure shows how the 120/240 V rms power is distributed in
JPDA, and how it reaches the TRLY board or ac load.
JAC1
ACHi 15 A Fuse JA1
LED Indicator Ckt To TRLY or

Ac Load
ACLo
120/240 Vrms
From JPDx 15 A Fuse JA2

Ac Load
15 A Fuse JA3

Ac Load
JAC2
ACHi 15 A Fuse JA4
To TRLY or
LED Indicator Ckt
Ac Load
ACLo
JPDA Simplified Circuit Diagram
Inputs
Multiple JPDA boards receive power from a single JPDM Main Power Distribution
Module. This power input is either 120 V rms or 240 V rms, 50/60 Hz.
Two 3-Pin Mate-N-Lok connectors are provided. One connector receives ac input power
and the other can be used to distribute ac power to another JPDA board in daisy chain
fashion. It is expected that the low or neutral side of the input power is grounded.
Outputs
Four output circuits are provided with three-pin Mate-N-Lok connectors.
Each output circuit includes branch circuit protection, and a pair of isolation
contacts for the non-grounded line. There is also a green lamp to indicate
the presence of voltage across the output terminals.

Specifications
Item Description
Inputs One 3-pin connection for input power from JPDx 120 or 240 V rms, 15 A limit
Outputs Four 3-pin connections for TRLY and ac loads 120 or 240 V rms, fused 15 A
One 3-pin connection for output power to another JPDA board 120 or 240 V rms
Output fuses Four fuses, one per output, Bussmann® ABC-15 A typical. 250 V, 15 A
Board Size 15.875 cm high x 10.795 cm wide (6.25 in x 4.25 in)
Mounting DIN-rail, card carrier mounting
Base mounted steel bracket, 4 holes
Diagnostics
Configuration
There are no jumpers on JPDA. Check the position of the four output load switches.
It is possible to use other fuse ratings with this board to provide specific branch circuit
ratings. A typical series of fuses that work with this board are the Bussmann ABC
series of fuses with ratings from ¼ A through 15 A. Fuses above 15 A shall not be
used with this board. If alternate fuse ratings are used, configuration of the board
requires the insertion of the proper fuse in each branch circuit.

JPDB Ac Power Distribution
The ac Power Distribution (JPDB) board conditions, monitors, and distributes
ac power. The module contains two line filters and a IS200JPDB circuit board.
The module features two separate ac distribution circuits, each rated for 20 A at
115 or 230 V ac. The input circuits should be wired in parallel to avoid PPDA
alarms when a single source of ac power is provided.
For each circuit, one fused, and three fused and switched branch circuit outputs
are provided. Connection to an optional JPDF 125 V dc distribution module is
provided. The IS200JPDB includes passive monitoring circuits for both ac magnitudes
as well as status feedback for all fused circuits. The monitoring circuits are on
connector P1, compatible with cable connection to a board containing a power
diagnostic PPDA I/O pack. IS200JPDB also has a P2 connector for pass-through
of monitoring signals from other power distribution system cards.
Two JPDB modules could be cabled into a single PPDA I/O pack when needed.
IS2020JPDBG2 provides an additional connector when an ac source selector is required

in a system. The connector intercepts the two ac sources supplied to JPDB and routes
them to the JSS1 connector on the board edge. Output of the ac selector is then
wired to JSS1 and conducted to the individual branch circuit outputs.
Note Circuit breakers are not provided as part of the basic IS2020JPDB module.
Options exist to provide circuit breakers on a mounting plate that fastens to the JPDB
sheet metal support. Please refer to job specific documentation for information
regarding any circuit breakers attached to JPDB.
Compatibility
The IS2020JPDB is compatible with the feedback signal P1 / P2 connectors on
JPDE, JPDF, JPDS, and JPDM leading to a PPDA I/O pack. Connector JAF2 is
compatible with the ac input on the JPDF module of the same name.

Installation

The IS2020JPDB module is base-mounted vertically on a metal back base in a

cabinet used by the PDM. A connection must be made between the IS2020JPDB
sheet metal and the system Protective Earth.
Input power is applied to terminals AC1H (line) and AC1N (neutral) for the
first ac circuit, and AC2H (line) and AC2N (neutral) for the second ac circuit.
Both ac inputs are required to have grounded neutral connections. Output
circuits are connected as documented for the system.
If the power distribution system includes a PPDA power diagnostic I/O pack, a
50-pin ribbon cable is required from JPDB connector P1 to the P2 connector on
the board holding PPDA. It is permissible for this connection to pass through
other core PDM boards using the P2 connector.
Grounding
Mark* VIe systems divide ground into a protective earth (PE) and a functional
earth (FE). The PE ground must be connected to an appropriate earth connection
in accordance with all local standards. The minimum grounding must be capable
of carrying 60 A for 60 seconds with no more that a 10 volt drop. The FE ground
system must be bonded to the PE ground system at one point.
The JPDB is grounded through metal mounting supports fastened to the underlying
sheet metal of a metal module. The ground is applied to the metal switch bodies
on JPDB. Additionally, the ground is used as a local reference point when creating
the feedback signals appearing on P2. The sheet metal of the module is insulated to
the surface upon which it is mounted. This is done specifically to allow definition
of the JPDB ground independent of the mounting surface. Typically, JPDB is
mounted to a back base grounded to FE. JPDB would be located low in the cabinet
and a separate ground wire from the JPDB module would be provided to PE. The
minimum length of the ground wire is important to keep impedance low at radio
frequencies, this allow the input line filters to function properly.

Physical Arrangement
When JPDB is used with an optional source, the selector should be positioned above
the JPDB, thus allowing a short power connection between the two components using
the JSS1 connector. When JPDB is used with a JPDF (125 V dc) board, the JAF1
connector provides ac power to JPDF. The best location for JPDF in this arrangement
is below the JPDB, to minimize wiring lengths. The P1 and P2 ribbon cable headers
on all of the JPDB boards are positioned, so the JPDS or JPDM holding the PPDA I/O
pack is best located at the top of the board arrangement. This allows ribbon cables to
flow from one card to the next, exiting the top, and entering the bottom of the next
card until the PPDA host is reached. Connector P1 transmits feedback signals to a
board hosting a PPDA I/O pack. Connector P2 receives feedback from other power
distribution boards and passes the signals out of P1 to the PPDA.
Application Notes
When JPDB is used with a single ac input, the two ac inputs should be wired
in parallel to the source. All output branch circuits are now live and there can
be no diagnostics generated. If only one ac input is used, a diagnostic for loss
of ac on the un-switched branch circuit can appear.
Operation
Two sources of ac power are wired to a terminal board on the right side of the JPDB module.
The ac power goes to the ac line filter assemblies underneath the IS200JPDB circuit board.
A wire harness connects the filter assemblies to the JPDB circuit board J1 connector.
The IS2020JPDBG01 module uses the IS200JPDBH1A circuit board. This

board does not provide connection for an ac source selector and J1 ac power
is wired directly to the output branch circuits.
The IS2020JPDBG02 module uses the IS200JPDBH2A circuit board. The board is
designed for use with an ac source selector. It features the JSS1 connector mounted to
the board. External filtered ac from connector J1 is fed to JSS1. The source selector
output returns to the JSS1 to supply the branch circuit outputs.
JAF1 feeds power directly from input connector J1 to an adjacent optional JPDF board to
power two DACA power conversion modules. The DACA modules convert the ac power
to 125 V dc to be used as an ac backup for systems using a 125 V dc battery.
The figure below shows the JPDBG01 module with the JPDBH1A circuit board.

1- P1
Diagnostic
50 J1
Connector -50 pin
SW 1 AC INPUT
JAC 1 FU 1 LOAD LINE
1 FL1 AC 1H
1 MV 2
2 NC 250 V 10A 4 CORCOM
MV1
3 20ESK 6
MV 3
JAC3 SW 3 20A 250 V ac AC1N
FU 3
1 2
2 NC 250 V 10 A 3
3 5 NC
JAC5 SW 5
FU 5
1
2 NC 250 V 10 A
3
JA1 FU 7 LOAD LINE
1 9 FL2 MV5
AC2H
2 NC 250 V 10 A CORCOM
6 MV 4
3
20ESK 6
SW 2 8 MV 6
JAC 2 20A 250 V ac AC 2N
FU 2 7
1
2 NC 250 V 10 A TB1
3 AC1P
SW 4 TP1
JAC4 FU 4 AC1N
1 TP2
2 NC 250 V 10 A
AC2P
3 TP3
JAC6 SW 6 AC2N
FU 6 TP 4
1
2 NC 250 V 10 A AC 1P
1
3
AC1N
JA2 FU 8 2
1
2 NC 250 V 10 A NC 3
3 AC 2P
4
AC2N
5
JAF1 AC
1- P2 TO JPDF
ISO 200JPDBH 1A
Diagnostic
50
Connector -50 pin
JPDB Module for Use without the JPDR Source Selector

The figure below shows the JPDBG02 modules with the JPDBH2A circuit board.
1- P1 1 6 3 8 9 4 7 2 5 JSS1 TO
Diagnostic NC JPDR J1
50
Connector-50 pin LOAD LINE
1 FL1 AC1H
JAC1 SW1 MV2
FU1 CORCOM
1 4 MV1
20ESK6
2 NC 250 V 10 A 2 20A 250 V ac MV3
AC1N
3 3
JAC3 SW3
FU3
1
2 NC 250 V 10 A
5 NC
3
JAC5 SW5
FU5
1
2 NC 250 V 10 A
3
JA1 FU7 LOAD LINE
1 6 FL2 AC2H
250 V 10 A MV5
2 NC CORCOM
9 MV4
3 20ESK6
SW2 7 20A 250 V ac MV6
JAC2 AC2N
FU2 8
1
2 NC 250 V 10 A TB1
3 AC1P
SW4 TP1
JAC4 FU4 AC1N
1 TP2
2 NC 250 V 10 A
AC2P
3 TP3
JAC6 SW6 AC2N
FU6 TP4
1
2 NC 250 V 10 A AC1P
1
3
AC1N
JA2 2
FU8
1
2 NC 250 V 10 A NC 3
3 AC2P
4
AC2N
5
JAF1
1- P2 AC TO JPDF
Diagnostic
ISO200JPDBH 2A
50 Connector-50 pin
JPDB Module for Use with the JPDR Source Selector

The following figure shows the mechanical layout of the JPDB board.
JPDB Module Mechanical Layout

I/O Characteristics
• A terminal strip (TB1) mounted with the JPDB module has two ac input
screw terminal pairs. These terminals are rated at 20 A RMS. Branch circuit
protection can be no larger than a 30 A circuit breaker. The rating for the
ac circuits is 115/230 V ac, 20 A for each of the two circuits feeding JAF1.
The circuits use a grounded neutral connection.
• A nine-position Mate-N-Lok connector, J1, accepts power from line filters
into the JPDB board. Dual pins are used for each connection point to support
the current rating. J1 comes with a wire harness that is part of the module.
Refer to previous wiring diagrams for proper hookup.
• A five-position Mate-N-Lok connector, JAF1, provides direct ac power output.
This connector matches the one on the JPDF board. Ac current passes through
the JPDF board providing ac to dc conversion using DACA modules.
• A nine-position Mate-N-Lok connector, JSS1, is included on the JPDBH2A board and
provides a connection point for an external ac source selector. The JSSI connector is
not used on the JPDBH1A board and there is no connection for a source selector.
• Two un-switched ac outputs, JA1 and JA2, are provided with each ac circuit
using a three-pin Mate-N-Lok connector to feed optional JPDA branch circuit
boards. The circuits are fused and rated at 10 A/250 V.
• Six switched and fused output connectors, JAC1 through JAC6, are provided
with each using a three pin Mate-N-Lok connector. Fuses are rated at 10
A/250 V. Additionally these connectors could be used to feed ac/28 V dc
power converters making I/O pack control power.
• Two 50-pin diagnostic ribbon cable connectors, P1 and P2, are supplied on the
top and bottom of the board. Connector P1 transmits feedback signals to a board
hosting a PPDA I/O pack. Connector P2 receives feedback from other power

Specifications
Item Description
Board Rating 115/230 V ac either circuit
50/60 Hz
30 A circuit breaker protection
Total ac circuit loading 10 A on JAF1 AC1 plus 20 A total on JA1+JAC1+JAC3+JAC5
10 A on JAF1 AC2 plus 20 A total on JA2+JAC2+JAC4+JAC6
Fuse for connectors JAC1-JAC6 and 10 A on 250 V, Bussmann MDA-10 typical
JA1-JA2: FU1-FU8
Module size 26.41 cm High x 21.33 cm Wide x 16 cm Deep (10.4 in. x 8.4 in. x 6.3 in.)
Mounting Four mounting holes, #10 screws
Diagnostics
Diagnostic signals routed into PPDA through connector P1 include:
• An electronic ID identifying the board type, revision, and serial number

• Two 115/230 V ac analog feedbacks
• Six switched/fused ac supply indications yielding six Boolean values
after PPDA decodes the signals
• Two fused ac supply indications yielding two Boolean values after
PPDA decodes the signals
• A local ground signal for sensing analog signals
Additional core PDM board feedback passes through JPDB using the P2 connector. Test
points with 100 k series resistors are provided to allow connection of testing equipment:
• TP1 is the AC1 line

• TP2 is the AC1 neutral line
• TP3 is the AC2 line
• TP4 is the AC2 neutral line
Configuration

JPDC Power Distribution Module
The IS2020JPDC Power Distribution Module (JPDC) combines input and output
functions from several previous designs to provide distribution of 125 V dc, 115/230
V ac, and 28 V dc to other boards within a turbine control system.
Compatibility
JPDC can host a Power Distribution System Feedback (PPDA) pack used in the Mark*
VIe Power Distribution System. JPDC can also receive diagnostic feedback signals from
other distribution boards and route these signals to the PPDA I/O pack as well.
The intent is that the PPDA I/O pack should be mounted on the JPDC module. Therefore,
no provision is made to transmit diagnostic signals from JPDC to another distribution board.
Module Versions:
IS2020JPDCG01: Standard version for most applications.
IS2020JPDCG02: Special version which includes a wire jumper on the D1 diode assembly.
The jumper permits the JD2 Battery B input connector to be used as an output connector.
Installation
The JPDC module is typically mounted vertically with the 115/230 V ac input
connector (JAC) at the bottom. It is attached with four screws using the mounting
holes located at the top and bottom of the module base. Location within the control
cabinet is not critical, however, distribution boards are usually mounted low in the
cabinet to facilitate grounding. Refer to the section, Grounding.
The optional PPDA I/O pack is plugged into connector JA1. It is secured to the
JPDC base using an angle bracket, held in place with nuts threaded onto studs,
that are permanently attached to the base for that purpose.
Diagnostic feedback inputs from other distribution boards are routed to JPDC
through a 50-pin ribbon cable attached to connector P2.
Input power connections include:
• Either one or two 125 V dc battery input connections through connectors JD1 and JD2
• 125 V dc DACA module connection made using connector JZ2
• 115 or 230 V ac input applied to connector JAC

Up to three separate 28 V dc sources can be made to connectors JR, JS, and JT
respectively. The positive sides of these three inputs are isolated from each other and
designated as 28PR, 28PS, and 28PT power busses. If only one 28 V dc input is used, the
three power busses can be linked together if desired. Refer to the section, Operation.
To replace a JPDC, replace the entire module. Refer to

the section, Module Replacement. Do not remove the
board from its mounting plate.
Attention
Grounding
Mark VIe systems divide ground into a protective earth (PE) and a functional earth
(FE). The PE ground must be connected to an appropriate earth connection in
accordance with all local standards. The minimum grounding must be capable of
carrying 60 A for 60 seconds with no more that a 10 volt drop. The FE ground
The FE circuitry on the JPDC board is grounded through metal mounting supports
fastened to the underlying sheet metal of the module. The FE ground is used as a local
reference point when creating the feedback signals appearing on P2. Typically, the JPDC
module is mounted to a back base grounded to FE, completing the path to ground.
The metal switch bodies on the JPDC are tied to PE circuitry on the board.
Separate ground wires from the JPDC module, screw connections E5 and or
E6 must be connected to the enclosure PE bus.
When input line filters are inserted in line with the JPDC, the filters should be located
either on a PE grounded base or near the enclosure PE bus. When PE ground wires are run
from the filters to the PE bus, minimum length of the ground wire is important to keep
impedance low at radio frequencies, allowing the input line filters to function properly.
The IS2020JPDC module consists of a 6.75 x 19.0-inch IS200JPDC board, a
diode assembly, and two resistors mounted on a steel base.
Voltage levels on the JPDC board increase from top to bottom with 28 V dc circuits on the
top and left side, 125 V dc in the center and right side, and 115/230 V ac on the bottom.

Operation
Ac Power Distribution
An input of either 115 V ac or 230 V ac is supplied to JPDC through connector JAC.
The maximum allowable current is 12.5 amps rms. It is expected that the low or neutral
side of the input power is grounded. (Refer to the functional diagram)
Two ac outputs are provided. Both are protected by a 10 A time-delay fuse on

the high side only (Pin 1 of each connector). The output at JAC1 is controlled
by toggle switch SWAC1. The JAC2 output is not switched.
125 V dc Power Distribution

JPDC can accept two battery inputs through connectors JD1 and JD2. Provision is also
made for a third 125 V dc input from an ac/dc converter such as IS2020DACA through
connector JZ2. Each input is typically routed through an external filter.
Input voltage range 90 – 145 V dc.
The two battery inputs are OR’ed together by diode module D1 and are OR’ed
with 125 V dc from DACA by a diode on the DACA module. The OR’ed
125 V dc inputs combine on JPDC to form a 125 V dc bus labeled PDC. The
return paths of the 125 V dc inputs are connected together and labeled NDC.
Total 125 V dc current flow should not exceed 20 amps.
All three 125 V dc inputs are floating with respect to ground. When jumper JP2 is
installed, each side of the 125 V dc bus is connected to FE ground through approximately
84 k ohms of resistance in order to provide a means of ground fault detection.

JPDC Electrical One-line Diagram

Nine 125 V dc outputs are provided:
• Three outputs J1R, J1S, and J1T provide power to the inputs of three external 28
V dc power supplies which supply JPDC with 28 V dc power. These outputs are
fuse-protected and controlled by toggle switches SW1R, SW1S, and SW1T.
When SW1R, SW1S, and SW1T are switched OFF, wait

at least 30 seconds before turning them back ON. This
prevents damage to the input circuits of the 28 V dc
power supplies.
Caution
• Outputs J1R, J1S, and J1T can be powered from either the PDC bus or from
Battery A only. Refer to the section, Configuration.
• Three outputs J7A, J7B, and J7C are fuse-protected and controlled
by toggle switches. They provide output power to the Relay Output
(TRLY) terminal board and similar boards.
• Three outputs J8A, J8B, and J8C are only fuse-protected. A 22 W resistor is inserted
in series with each side to limit output power. These outputs supply power to
boards such as the Contact Input (TBCI) terminal board, which require a source
with limited short circuit capability to meet agency requirements.
28 V dc Power Distribution
JPDC provides for TMR or Simplex 28 V dc power distribution. Three separate
28 V input connectors; JR, JS, and JT are provided. On each connector, two pins
are connected in parallel to increase current-carrying capacity.
Eight output connectors do not have fuse protection: J1, JP1, JCR, JCS, JCT,
JRS, JSS, and JTS. Output current should not exceed 12.5 A.
Twenty-six outputs have 1.6 A polyfuse protection. In TMR configuration,

ten of these, JR1 through JR10, provide 28 PR power, eight provide 28
PS power, and eight provide 28 PT power.
One output, P4, has 0.5 A polyfuse protection and provides power to the PPDA I/O pack.
Diagnostic Feedback Signals

FDBK_A1: Attenuated voltage difference from PDC bus to ground.
V_A1/VPDC = 0.033316V/V.
FDBK_A2: Attenuated voltage difference from NDC bus to ground

V_A1/VPDC = -0.033316V/V.
FDBK_A3 and FDBK_A4: Multiplexed feedbacks from J1S-T and

J7A-C. (Requires PPDA I/O pack).
FDBK_A5: Attenuated AC input voltage: V_A5/VAC is approximately 0.01885V/V.
FDBK_B1: Multiplexed feedbacks from Battery 1 input, Battery 2 input, JAC1

output, and JAC2 output. (Requires PPDA I/O pack).

FDBK_B2 – FDBK_B4: Attenuated 28VDC R, S, and T inputs. Attenuation
ratio = Vfeedback/Vin = 0.143V/V.
Feedback_B5: Multiplexed feedbacks from external 28 V dc power

supplies. (Requires PPDA I/O pack).
To Diagnostic Signal Subset
TB2 TB3 TB4

TB1
123 1312
28 V dc Bus Tie 5 4 3 2 1
+ - LNGRST Diagnostics
N N T S R
P2 In
28 V dc Inputs 15
An per Connector JR JS JT
To
28 V dc Diagnostics
Controller Power JCR JCS JCT Pack
JA1
28 V dc
JRS JSS JTS
Switch Power
E5 PE
Ground
JR 1 JS1 JT 1
JR 2 JS2 JT 2
J1 T
JR 3 JS3 JT 3
JR 4 JS4 JT 4
J1 S 125 V dc POWER TO
dc/dc EXTERNAL
28 V dc CONVERTERS
PACK JR 5 JS5 JT 5
POWER
J1R
JR 6 JS6 JT 6
JR 7 JS7 JT 7 JDB JDA
JR 8 JS8 JT 8
J 7C
JR 9
125 V dc
J7 B POWER TO
JR 10 TRLY
28 V dc
POWER TO J1 J7 A
JPDP
28 V dc
POWER TO JP1
JPDL J8C
125 V dc
E1 E3 J 8B POWER TO
TBCI
D1 EXTERNAL
EXTERNAL 22 OHM J 8A
OR'ing RESISTORS
DIODES BATTERY A INPUT
JD 1
J
P
2 BATTERY B INPUT
E2 E4 JD 2
J
J
A
A JZ2 (DACA)
C
E 6 PE C
JAC 1 2
Ground
115/230 V ac 115/230 V ac 115/230 V ac

POWER OUTPUT POWER OUTPUT
POWER INPUT
JPDC Connector Locations

Specifications
Item Description
28 V dc inputs Three 9-pin Mate-N-Lok connectors for 28 V dc Power 19 A max each
Supply inputs: (JR, JS, JT)
One 50-pin ribbon cable with diagnostic data from upstream 15 V max
boards (P2)
One 5-screw terminal block for daisy chaining power 35 A max per screw
distribution boards
28 V dc outputs One 6-pin Mate-N-Lok connector for a JPDP board (J1) 13 A max per pin
One 5-pin Mate-N-Lok connector for a JPDL board (JP1) 13 A max per pin
Three 2-pin Mate-N-Lok connectors for CPCI control rack
power (JCR, JCS, JCT) 13 A max per pin
Three 2-pin Mate-N-Lok connectors for LAN switch power
(JRS, JSS, JTS) 13 A max per pin
Twenty six 2-pin mini-Mate-N-Lok connections fused, for
auxiliary devices (JR1-JR10), (JS1-JS-8), (JT1-JT8) 1.6 A polyfuse
One 5-screw terminal block for daisy chaining power
distribution boards (TP1) 35 A max per screw
One 2-pin connection for 28 V dc power to the PPDA I/O
pack (P4) 0.5 A polyfuse
One 62-pin D-shell connection for PPDA I/O pack (JA1)
15 V max
115/230 V Ac One 3-pin Mate-N-Lok connector (JAC) 13 A max.
input Board Rating 115/230 V ac
50/60 Hz
30 A circuit breaker protection
115/230 V Ac Two 3-pin Mate-N-Lok connectors (JAC1, JAC2) 10 A max. each
output Fuses for connectors JAC1-JAC2 and FUAC1-FUAC2: 10 A, 250 V, Littelfuse® 218010 is typical.
FU1-FU8
125 V dc Two 4-pin Mate-N-Lok connectors (JD1, JD2) 20 A max. total current
battery inputs
125 V dc One 12-pin Mate-N-Lok connector (JZ2) 10 A max.
DACA input Board Rating 125 V dc nominal, 145 V dc maximum, 30
A circuit breaker protection
Impedance to ground JP1 jumper in place >75 kΩ
JP1 jumper removed > 1500 kΩ
Fuses for connectors J1R: FU1R- FU2R, J1S: FU1S-FU2S, 10 A 250 V, Littelfuse® 218010 is typical
J1T: FU1T-FU2T
Fuses for connectors J7A: FU71-FU72, J7B: FU73-FU74, 10 A 250 V, Littelfuse 217010 is typical
J7C: FU75-FU76
Fuses for connectors J8A: FU81-FU82, J8B: FU83-FU84, 3.15 A 250 V, Littelfuse 2173.15 is typical
J8C: FU85-FU86 –30ºC to 65ºC (-22 to +149 ºF)
Temperature Range 17.2 cm Wide x 48.26 cm High (6.75 in x
Board Size 19.0 in)
17.78 cm Wide x 51.81 cm High x 7.62 cm
Module Size Deep (7.0 in. x 20.4 in. x 3 in.)
Back-panel mounting, adjacent to other
Mounting power distribution boards

Diagnostics
Diagnostic Feedbacks
JPDC provides for the connection of a PPDA I/O pack for power distribution
feedback to the IONet. The PPDA I/O pack mounts on the JPDC.
JPDC uses two feedback signal groups on the PPDA I/O pack connector
comprised of the following ten diagnostic signals:
Signal Description
A1 PDC bus volts to earth magnitude
A2 NDC bus volts to earth magnitude
A3 J7A, J7B, J7C (125 V dc outputs) feedback multiplexed
A4 J1R, J1S, J1T (125 V dc outputs) feedback multiplexed
A5 AC1 feedback magnitude
B1 JAC1, JAC2, BATT1, and BATT2 feedback multiplexed
B2 28 V dc R feedback magnitude
B3 28 V dc S feedback magnitude
B4 28 V dc T feedback magnitude
B5 28 V dc R, S, T P.S. contacts multiplexed
There are no feedback signals provided for the three fused TBCI terminal board outputs
(J8A, J8B, and J8C) since each TBCI terminal board has its own voltage monitoring circuit.
Feedbacks also include an electronic ID identifying the board type,

revision, and serial number.
A P1 connector is not provided A 50-pin ribbon cable connector (P2) is used to daisy chain the diagnostic
to feed JPDC diagnostic signals from other distribution boards to JPDC. Up to four additional boards
signals to another location. may be cabled into JPDC for PPDA I/O pack reception. In a JPDC-based PDM
system, the PPDA I/O pack must be mounted on JPDC.
Three terminal boards (TB2, TB3, and TB4) are mounted end to end at the
top of JPDC and permit access to the analog diagnostic feedback signals
without the need for a PPDA I/O pack.
Diagnostic Circuits
Test rings TP1 and TP2 are connected to ACH and ACL respectively of the ac input line
to allow monitoring ac bus voltage. Each has a 30.1 K buffer resistor in series. Test rings
TP3 and TP4 are connected to positive and negative sides respectively of the 125 V dc
bus. Each has a 30.1 K buffer resistor. Test ring TP5 is connected to the negative or return
side of all three 28 V dc inputs. (No buffer resistor is provided). Test rings TP6, TP7, and
TP8 are connected to 28PR, 28PS, and 28PT respectively. These are the positive lines
of the three 28 V dc TMR power inputs. (No buffer resistors are provided).

Configuration
28 V dc TMR Configuration
• Separate power inputs are received through connectors JR, JS, and JT.
• The positive sides of the three inputs are connected to separate power busses,
designated as 28PR, 28PS, and 28PT respectively. The return sides of the
three inputs are connected together and designated as 28N.
• Output power is distributed from the three busses through separate
R, S, and T output connectors.
28 V dc Simplex Configuration
• One, two, or three 28 V dc power inputs can be received through
connectors JR, JS, and JT.
• The three power busses can be connected into a single bus by inserting jumpers
between terminals 1, 2, and 3 of terminal board TB1.
• All output connectors are fed from the single 28 V dc bus.
125 V dc outputs to external 125 V dc/28 V dc power supplies

• Two options are provided for the selection of power outputs through
connectors J1R, J1S, and J1T.
• For normal operation, a shorting plug is inserted in connector JDB. This
configuration selects 125 V dc power from the entire P125 bus, which is
fed by both battery inputs and the DACA input.
• A second mode of operation allows the user to replace the DACA supply
with an ac/dc converter of lower power rating. In such a case the shorting
plug should be moved to connector JDA. This configuration selects power for
connectors J1R, J1S, and J1T from Battery A only and allows the lower-rated
ac/dc converter to supply power only to the other 125 V dc outputs.
Never jumper connectors JDA and JDB at the same time.
Caution

Handling Precautions
To prevent component damage caused by static
electricity, treat all boards with static sensitive handling
techniques. Wear a wrist grounding strap when
handling boards or components, but only after boards
or components have been removed from potentially
Caution energized equipment and are at a normally grounded
workstation.

shock, burn, or death. Ensure that all Lockout/Tagout
procedures are followed prior to replacing terminal
boards. Only personnel who are adequately trained
and thoroughly familiar with the equipment and the
Warning instructions should install, operate, or maintain this
equipment.
Module Replacement
¾ To replace the module
1. Lockout and/or tagout all energy sources to the module.
2. Check the voltage on each terminal to ensure no voltage is present.
3. Note the orientation of the module and the location of any jumpered
connections. Verify the label and unplug all connectors.
Note Do NOT remove any jumpers, if applicable.
4. Unscrew and remove the board grounding wires.

5. Remove the hardware used to fasten the module to the cabinet.
6. Inspect the new module for shipping damage.
7. Install the new module into the cabinet in the same orientation as the old module.
8. Verify all jumpered connections on the new module, are the same as
those jumpered on the old module.
9. Reconnect the board grounding wires.
10. Reconnect all wire and cable connectors.
11. Remove the Lockout and/or tagout and restore power to the module.
12. Test/verify that all switches, fuses, LEDs, and I/O packs function properly.

JPDD Dc Power Distribution
The dc Power Distribution (JPDD) board provides dc power distribution, power isolation,
and branch circuit protection for control or I/O functions requiring 125 V dc, 48 V dc,
or 24 V dc power. Typical applications include dc relay and solenoid control power, and
contact wetting. Each output includes a fuse, a switch, and a lamp to indicate the presence
of output voltage. JPDD is not intended for power distribution to the I/O packs.
Board Versions
Terminal Board Fusing

JPDDG1 Each circuit provided with ¼ in x 1¼ in 15 A 250 V fuse
JPDDG2 Empty fuse holders with black caps accepting 5 x 20 mm fuses
JPDDG3 Empty fuse holders with grey caps accepting ¼ in x 1¼ in fuses
JPDDG1 provides fuses that are coordinated with the rating of the system
wiring and connectors. JPDDG2 and G3 are used when fuse ratings coordinated
with a specific application are required. Two different fuse sizes are provided
to accommodate local fuse preferences.

Installation
JPDD is held in a plastic holder, which mounts on a vertical DIN-rail. When
installing the JPDD, it is important to provide a ground lead from TB1 to the system
ground. This creates a ground path for the metal switch bodies.
JPDD Dc Power Distribution Board
2
Input power Input power 125
J28 J125
24 V dc or 48 V dc V dc (alternate)
FU1P Indicator
2
SW1 JD1 To TRLY or TBCI
or equivalent
FU1N
FU2P Indicator
2
or equivalent
FU2N
FU3P Indicator
2
or equivalent
FU3N
FU4P Indicator
2
or equivalent
FU4N
FU5P Indicator
1
2
or equivalent
FU5N
FU6P Indicator
1

or equivalent
FU6N Chassis
Ground TB1
Output power Output power to

4
to another J28X J125X another JPDD 125

JPDD 24 V dc or 48 V dc V dc (alternate)
JPDD Cabling
Power input can be 24 V dc, 48 V dc, or 125 V dc, but only one voltage level at
any given time. Do not mix voltages. For cable destinations, refer to the circuit
diagram. TB1 should be connected to system ground.

Operation
The following figure shows how the 125 V dc, 48 V dc, or 24 V dc power is
distributed in JPDD, and how it reaches the TRLY and TBCI boards.
JPDD Local Dc Power Distribution Board

Auxiliary
Power
Unit
J28
+ 24/48 V dc
+ JD1 Dc Power to
input from + TRLY or
JPDX or TBCI or
another - LED Indicator Ckt
equivalent
JPDD -
J28X
+
.
+ 24/48 V dc +
.
output to
another - 6 Identical Switched Output Ckts
JPDD 24 V dc, 48 V dc, or 125 V dc
-
.
+125 V dc
J125 .
from JPDX +
or another - JD6 Dc Power to
JPDD
J125X TRLY or
+125 V dc LED Indicator Ckt TBCI or
output to + equivalent
another -
JPDD
JPDD Simplified Circuit Diagram
Inputs
Multiple JPDD boards can receive power from a single Main Power Distribution Module
branch circuit. Power input can be either 125 V dc, 48 V dc, or 24 V dc nominal.
Both inputs share a common electrical path. Only a

single voltage (24, 48, or 125) can be applied at one time
to both inputs.
Caution
Two 2-Pin Mate-N-Lok connectors are provided for 125 V dc power. One
connector receives input power and the other can be used to distribute 125 V
dc power to another JPDD board in daisy chain fashion.
Two 4-pin Mate-N-Lok connectors are provided for 24/48 V dc power. These perform
functions similar to those of the 2-pin connectors above. The 4-pin connector
permits parallel connection of two pin-pairs for increased current capacity. It is
expected that neither side of the dc power input is grounded.

Outputs
Six identical output circuits are provided. Each output circuit includes two fuses, a switch
with a pair of isolation contacts in each side of the output, and a green lamp to indicate
the presence of voltage across the output terminals. The provision of a fuse and switch
contact in each side of the dc path allows use of this board with floating power sources.
Specifications
Item Description
Inputs One 2-pin connection for input power from JPDx or another JPDD 125 V dc, 15 A
One 4-pin connection for input power from JPDx or another JPDD 24 or 48 V dc, 30 A
Outputs Six 2-pin connections for power to TRLY or TBCI 24 V dc or 125 V dc, fused
One 2-pin connection for output power to another JPDD 125 V dc
One 4-pin connection for output power to another JPDD 24 or 48 V dc
Output Fuses 12 fuses, two per output 250 V, 15 A
Mounting DIN-rail, card carrier mounting Base mounted steel bracket, 4 holes
Diagnostics
Configuration
There are no jumpers on JPDD. Check the position of the six output load switches.
It is possible to use other fuse ratings with this board to provide specific branch circuit
ratings. A typical series of fuses that work with this board are the Bussmann ABC
series of fuses with ratings from ¼ A through 15 A. Fuses above 15 A shall not be
used with this board. If alternate fuse ratings are used, configuration of the board
requires the insertion of the proper fuse in each branch circuit.

JPDE Dc Battery Power Distribution
The dc Battery Power Distribution (JPDE) board receives dc power from a battery or
power supplies and distributes it to terminal boards and other system loads. JPDE
supports a floating dc bus that is centered on earth using resistors and provides voltage
feedback through PPDA to detect system ground faults. It provides inputs for two
power supplies. JPDE is able to operate at either 24 V dc or 48 V dc. JPDE integrates
into the PDM system feedback offered through the PPDA I/O pack.
This board is limited by the current that can be passed through it using conventional
board construction. JPDE does not supply power to bulk 500 W - 24 V input/28
V output power supplies providing I/O pack control power.
Compatibility
The IS200JPDE board is compatible with the feedback signal P1/P2 connectors
on JPDB, JPDF, JPDS, and JPDM leading to a PPDA I/O pack.
Installation
JPDE is base-mounted vertically on a metal bracket in a cabinet used by the PDM.
Refer to the wiring diagrams for power input and output routing. There is a 50-pin
diagnostic connector mounted on the top and bottom of the board.
Grounding
The IS200JPDE board is grounded through the sheet metal bracket to the
underlying back base. In most cases, this is the system FE.
The location of JPDE is not critical in a panel. Connector P1 transmits feedback
signals to a board hosting a PPDA I/O pack. Connector P2 receives feedback
from other power distribution boards and passes the signals out of P1 to the
PPDA. If a cable connection from JPDE to a board containing PPDA is planned,
consideration should be given to the feedback cable routing between JPDE P1 and
the P2 connector on the board receiving the feedback cable.
Application Notes
JPDE can be used with one or two power supplies to create a dc power system for
terminal boards and other system loads. When this is done, float the dc power system
and use the grounding resistors on JPDE to center the bus on earth. This permits
detection of ground faults through the PPDA bus voltage feedback. Jumper JP1 is
required to be in place, connecting the centering resistors to earth.
When JPDE is used to distribute battery power, it is supplied with a dc

circuit breaker and a 30 A input filter.

Operation
JPDE 24/48 V P1 Diagnostic

Daisy Chain
JPS1
24v Pwr JS1
to J P D D
3 x 4 -p in
Supply
JS2
JPS2
24v Pwr
Supply JS3
7A
Battery
Input JFA
To JPD D
3 x 4 -P in
30 A JFB
JD1
6pos. JFC
Filter
15 A
JP 1
Note: Filter and P2 Diagnostic
Rectifier Daisy Chain
are supplied with
battery powered
systems .
JPDE Simplified Electrical Diagram
JPDE Mechanical Layout

I/O Characteristics
• JD1 is a 6-pin Mate-N-Lok connector that accepts power input from a
battery. Three connector pins each are used for positive and negative
connections to provide adequate current rating.
• JFA, JFB, and JFC are fused four-pin Mate-N-Lok output connectors. Positive power
is on pins 1 and 2, and negative power is on pins 3 and 4. This matches the pin use
on JPDD J28 and J28X. These connectors have a fuse rating of 15 A.
• JP1 is the ground reference jumper. The dc bus is normally operated without a
hard ground connection. The dc bus is centered on earth as part of the ground fault
detection scheme. Normally, the 24 V operation of the dc positive terminal would
measure ½ * 24 V above ground and the negative terminal has the same magnitude
below ground potential. Resistors to center the bus on earth are supplied externally
to the JPDE, or on-board resistors can be used by closing jumper JP1.
• JPS1 and JPS2 are nine-pin Mate-N-Lok connectors used for power supply input.
The connector uses pins 7 and 9 for positive 24/48 V dc and pins 1-3 for 24 V return
providing 24 A steady state capacity. Pin 4 provides positive 10 V dc wetting
to a supply status feedback switch and pin 5 provides the return.
• JS1, JS2, and JS3 are fused and switched four-pin Mate-N-Lok output connectors.
Positive power is on pins 1 and 2, and negative power is on pins 3 and 4. This matches
the pin use on JPDD J28 and J28X. The fuse rating for these switched connectors is 7 A.

Specifications
Item Description
Total board rating 30 A total dc current from all branch circuits
50 V maximum nominal voltage
Fuse for connectors JS1-JS3: FU11-12, FU21-22, FU31-32 7 A, 250 V, Bussmann ABC-7 typical
Fuse for connectors JFA, JFB, JFC: FUA1-2, FUB1-2, FUC1-2 15 A 250 V, Bussmann ABC-15 typical
Board Size 16.51 cm High x 17.8 cm Wide (6.5 in. x 7 in.)
Mounting six mounting holes
Diagnostics
• An electronic ID identifying the board type, revision number, and serial number
• Two analog battery voltage feedbacks. One is for positive bus and one is
for negative bus. Voltage feedback accuracy is ±1%.
• Three switched/fused dc branch circuit status signals
• Two dc power converter output status dry contact status signals
• Three fused branch circuit status signals
• Two test points with series 2.15 kΩ resistors are provided on the 24/48
V dc bus for external test equipment. HW1 is connected to the positive
bus and HW2 is connected to the negative bus.
Configuration
When jumper JP1 is in place, the JPDE provides 6 kΩ voltage-centering resistors from
positive and negative dc to the local earth connection. When JP1 is removed, the connection
to earth is opened. Insert JP1 when a floating dc bus needs to be centered on earth.

JPDF 125 V Power Distribution
The 125 V Power Distribution (JPDF) board accepts redundant 125 V dc power inputs
and distributes power to other system boards. JPDF works with a floating dc bus that
is centered on earth rather than with a grounded system. This permits detection of a
system ground fault and carries a non-hazardous live 125 V dc rating.
Input 125 V dc battery power is connected to a terminal board on the IS2020JPDF module.
The power is then routed through a 125 V dc 30 A circuit breaker and line filter before
being connected to the IS200JPDF board through the J1 connector. Dc voltage is then
routed to three fused, non-switched outputs and six fused, switched outputs.
Ac power is routed through the board to the DACA modules where it is converted to
dc power. Dc power returns to JPDF where it is combined with the battery power
input. JPDF can operate with any combination of one or more inputs active creating
a high-reliability source of 125 V dc power for the control system.
The IS2020JPDF module provides full status feedback using a connection to

a PPDA I/O pack. Feedback includes bus magnitude, ground fault detection,
and detection of excessive ac voltage on the dc bus. Each fused branch circuit
is monitored to indicate the presence of output power.
Compatibility
The IS2020JPDF is compatible with the feedback signal connectors, P1/P2, on JPDB,
JPDE, JPDS, and JPDM leading to a PPDA I/O pack. Connector JAF1 is compatible
with the ac power output on the IS2020JPDB module. Connectors JZ2 and JZ3 are
compatible with the connectors on the IS2020DACA module.

Installation

The IS2020JPDF module is base-mounted vertically on a metal back base in a

cabinet used by the PDM. A connection must be made between the IS2020JPDF
sheet metal and the system protective earth (PE).
Input battery power is applied to terminals DCHI and DCLO. If one or two DACA
modules are used, ac power is applied to JAF1, typically from an IS2020JPDB module.
DACA modules connect to JPDF through connectors JZ2 and JZ3.
Output circuits are connected as documented for the system.
A power distribution system featuring a PPDA power diagnostic I/O pack requires a
50-pin ribbon cable from JPDF connector P1 to the P2 connector on the board holding
PPDA. This connection can pass through other core PDM boards using the P2 connector.
Grounding
Mark* VIe systems divide ground into a protective earth (PE) and a functional
earth (FE). The PE ground must be connected to an appropriate earth connection
in accordance with all local standards. The minimum grounding must be capable
of carrying 60 A for 60 seconds with no more that a 10 volt drop. The FE ground
The JPDF is grounded through metal mounting supports fastened to the underlying sheet
metal of a metal module. The ground is applied to the metal switch bodies on JPDF.
Additionally, the ground is used as a local reference point when creating the feedback
signals appearing on P2. The sheet metal of the module is insulated to the surface upon
which it is mounted. This is done specifically to allow definition of the JPDF ground
independent of the mounting surface. Typically, JPDF is mounted to a back base grounded
to FE. JPDF would be located low in the cabinet and a separate ground wire from the JPDF
module would be provided to PE. The minimum length of the ground wire is important to
keep impedance low at radio frequencies allowing the input line filters to function properly.

JPDF accepts power input from the right side of the board and delivers power out of
the left side. When JPDB is used with JPDF, the JAF1 connector provides ac power
to JPDF. JPDF should be physically located beneath JPDB minimizing the length of
the JAF1 power wiring. JPDF is mounted to allow a minimum length of grounding
wire between the module sheet metal and the nearest PE connection point. Connector
P1 transmits feedback signals to a board hosting a PPDA I/O pack. Connector P2
receives feedback from other power distribution boards and passes the signals out of
P1 to the PPDA. The P1 and P2 ribbon cable headers on all of the core boards are
mounted so the JPDS or JPDM, holding the PPDA I/O pack, is located at the top of
the board arrangement. This allows ribbon cables to flow from the top of one board
and into the bottom of the next board until the PPDA host is reached.
Ground Fault Detection

The IS2020JPDF module supports the use of a dc bus that is centered on ground
potential by a high resistance. This arrangement allows the detection of a ground fault
when the positive bus or negative bus voltage goes to ground potential. In support
of this arrangement, the IS2020JPDF includes separate voltage feedback sensing for
positive and negative power with respect to ground. When the feedback is cabled into
a PPDA I/O pack detection of ground faults is provided to the system.
The resistance used centering the dc bus on ground sets the ground detection sensitivity
and ground fault currents that can flow. IS2020JPDF contains centering resistors selected
by jumper JP1. Should centering resistance be provided elsewhere, then the jumper on
JPDF should be open. JPDF is designed to then insert minimal centering resistance
in the system. If JPDF is providing the centering function, JP1 should be closed. If
two JPDF modules are used, only one should have a closed JP1 jumper.
Operation
Dc battery power is applied to terminals DCHI and DCLO. It then goes through a
30 A dc circuit breaker into a filter assembly located under the IS200JPDF circuit
board. Filtered output is then passed through a series diode to the JPDF circuit
board. Ac power is applied to the JAF1 connector. The 115/230 V ac is routed to
two connectors, JZ2 and JZ3, and out to two DACA modules. The DACA modules
convert the ac power to 125 V dc. The dc power returns to JPDF through the same
JZ2 and JZ3 connectors and combined with battery power if present.

D1: R1:
MV1-3:
104X125DC_ _014 323A2354P2
PDVR1000P001
1200 V 45 A 22 Ohm 40 W
250 V ac 1 2
(+) (+)
MV2 FL1 R2:
Corcom
LINE
323A2354P1
LOAD
CB1: MV1 20ESK6 1 Ohm 40 W
R4:
PDSB10A30P2HPNL 20 A 250 V ac
323A2354P1
DC INPUT 125 V dc 30 A MV3
TB1 1 Ohm 40 W
3 (-) (-)
DCHI
R3:
BATTERY 323A2354P2
4
DCLO 22 Ohm 40 W
1
DCHI
DIRECT 2
DCLO
NC
IS200JPDFG1A 3 4 9 7 5 1 2 6 8
J1 P1 1-
Diagnostic
Connector 50
50 pin
J12 FU12
1
To JPDD 125 V 3 A
(TBCI) 2
HW1 100k
FU13
J8A PDC Probe

1
FU81 PDC
To JPDD 250 V 12 A
JAF1
2 NDC
100k HW2 ACH2 1
FU82 ACL2 2
J8B NDC Probe NC
3 To JPDB
1
FU83 PDC ACH3 4
ACL3 5
To JPDD 2
250 V 12 A
NDC
FU84
J1R SW1R
1
FU1R
To DC-DC 250 V 10 A JZ3
2 ACH3 1
FU2R NC 2
ACL3 3
J1S SW1S 4
FU1S NC
1 NC 5
6
To DC-DC 2
250 V 10 A
NDC
NC
7 TO DACA
FU2S NC 8
PDC 9
J1T SW1T 10
1
FU1T 11
NC
12
To DC-DC 2
250 V 10 A
FU2T
SW7X
J7X FU71 JZ2
1 ACL2 1
250 V 5 A 2
To VPRO 2 ACH2
NC
3
FU72 NC 4
SW7Y NC 5
J7Y FU73 NC 6
1 NDC 7 TO DACA
To VPRO 250 V 5 A NC 8
2 PDC 9
FU74 10
SW7Z NC 11
J7Z FU75 12
1
To VPRO 2
250 V 5 A
PDC NDC
FU76 84.4k 84.4k
1/4 W 1/4 W
JP1
J7
1
To TRPX 2
P2 1-
Diagnostic 50
Connector
50 pin
CHASSIS PE
JPDF Electrical Diagram

JPDF Mechanical Board Layout

I/O Characteristics
• The JPDF module has a barrier terminal strip containing two battery input screw
terminals located on the right side of the circuit board. The dc input is rated at
30 A, and the voltage should never exceed 145 V dc. Protection of the Branch
circuit protection supplying power to this input is a 30 A circuit breaker, supplied
by default as part of the module. This is the primary power input.
• Two dc output screw terminals, located on the same barrier terminal strip, are not
normally used, but are provided to allow two JPDF boards to work in parallel.
• JD1 is a nine-pin Mate-N-Lok connector that accepts the power input from
the components that are mounted under the JPDF board. JD1 uses a wire
harness that is part of the JPDF module assembly.
• JAF1 is a five-pin Mate-N-Lok connector that accepts the 115/230 V ac input from
the JPDB board. The 115/230 V ac is routed to two connectors, JZ2 and JZ3, and out
to two DACA modules. The DACA modules convert the ac power to 125 V dc.
• Two 12-pin Mate-N-Lok connectors, JZ2 and JZ3, pass ac power to two
DACA modules. The DACA modules convert 115/230 V ac to 125 V dc.
Dc power returns through the JZ2 and JZ3 connectors.
• Three fused and switched two-pin Mate-N-Lok output connectors, J1R, J1S,
and J1T, are provided for powering 125 V dc/28 V dc converters The 28
V dc is the control power for I/O packs. Positive power is on pin 1 and
negative power is on pin 2. The fuses are rated at 5 A.
• Three fused and switched two-pin Mate-N-Lok output connectors, J7X, J7Y, and J7Z,
are provided for powering up to three Mate-N-Lok modules. Positive power is on
pin 1, negative power is on pin 2, and fuse rating is 5 A. Two 1 W resistors mounted
under the board define the minimum source impedance for these circuits.
• A two-pin Mate-N-Lok output connector, J7, is provided to supply power to
the system trip boards. Positive power is on pin 1 and negative power is on
pin 2. The output power comes from the circuits associated with J7X, J7Y,
and J7Z. The output power is combined through diodes and is only lost when
all three circuits have blown fuses or open switches.
• There are two 12 A fused two-pin, Mate-N-Lok output dc connectors on
both J8A and J8B. They feed remote JPDD boards to provide individual
switched/fused circuits to TRLY boards and other system loads. Positive
power is on pin 1 and negative power on pin 2.
• A two-pin Mate-N-Lok output connector, J12, is provided specifically to
operate TBCI contact input boards. Two 22 Ω resistors mounted under the
JPDF board define the minimum source impedance for this circuit. Positive
power is on pin 1 and negative power is on pin 2.
• The ground reference jumper is JP1. The dc bus is normally operated without a hard
ground connection, but it is desirable to center the dc on earth as part of the ground
fault detection scheme. In normal operation, the positive terminal would measure ½
*125 V above ground and the negative terminal would measure the same magnitude
below ground potential. The resistors used to center the bus on earth can be supplied
externally to the JPDF, or on-board resistors can be used by closing jumper JP1.

The following I/O characteristics apply to the IS2020JPDF module:
Specifications
Item Description
Board rating 125 V dc nominal, 145 V dc maximum 30 A circuit breaker
protection
Impedance to ground With JP1 jumper in place > 75 kΩ
With JP1 jumper removed > 1500 kΩ
Fuse for connectors J1R, J1S, J1T - FU1R, FU2R, FU1S, 10 A 250 V, Bussmann MDA-10 typical
FU2S, FU1T, FU2T
Fuse for connectors J7X, J7Y, J7Z - FU71-FU76 5 A 250 V, Bussmann ABC-5 typical
Fuse for connectors JBA, JBB - FU81-FU84 12 A 250 V, Bussmann ABC-12 typical
Fuse for connector J12: FU12 - FU13 3 A, 250 V, Bussmann ABC-3 typical
Physical
Modules Size 30.48 cm High x 21.33 cm Wide x 16 cm Deep (12 in. x 8.4
in. x 6.3 in.)
Mounting Four mounting holes, #10 screws
Diagnostics

• Two 125 V dc voltage feedbacks for voltage magnitude determination,
ground fault detection, and ac signal present detection
• Six switched/fused dc supply indications for J1R, J1S, J1T, J7X, J7Y, and J7Z
• Three fused dc supply indications for J8A, J8B, and J12
• Two hardware test rings, with series 100 kΩ resistors, are provided for attaching test
equipment. HW1 is labeled PDC Probe and HW2 is labeled NDC Probe.
Configuration
JP1 should be in place if JPDF is providing bus voltage centering resistors for ground
fault detection. JP1 should be omitted if another location is providing centering resistance.
TBCI boards, when powered by JPDF, should use connector J12 using a JPDD fan-out
board. The 44 Ω source impedance is coordinated with the circuit ratings on TBCI.
TRPG/TREG board pair, critical to system operation, should be

powered by the J7 connector.

JPDH High Density Power Distribution
The High Density Power Distribution (JPDH) board provides 28 V dc power
to 24 Mark* VIe I/O packs and 3 Ethernet switches from a 28 V dc supply.
Additional JPDHs can be connected in a daisy-chain arrangement to provide
power to more I/O packs as required. The circuit for each I/O pack connector is
protected with a positive temperature coefficient fuse device.
JPDH Power Distribution Board

Installation
Mount JPDH on a vertical surface by inserting #6 machine screws through the
mounting holes at each corner of the board. Insert Mate-N-Lok connectors as
described in the following figure. The 6-pin and larger 2-pin connectors have a
nominal rating of 600 V and 13 A, while the smaller two-pin connectors have a
nominal rating of 600 V and limited by fuse rating to 0.8 A max.
J1 J1X
28 V dc Input 28 V dc Output
to other JPDH
JRS JSS JTS

To Ethernet Switch R To Ethernet Switch S To Ethernet Switch T
JR1 JS1 JT1

To R I/O Pack 1 To S I/O Pack 1 To T I/O Pack 1
JR2 JS2 JT2

JR3 JS3 JT3

JR4 JS4 JT4

JR5 JS5 JT5

JR6 JS6 JT6

JR7 JS7 JT7

JR8 JS8 JT8

JPDH Connections

Operation
JPDH is designed to provide TMR I/O packs with adequate 28 V dc power distribution
while taking up as little space as possible. Additional JPDHs can be connected in
a daisy-chain arrangement through the unfused J1X connector.
Note The user must provide suitable branch circuit protection when connecting
multiple JPDHs. Each pin is rated at 13 A.
The 6-pin J1 connector brings in three separate 28 V dc feeds on three different pins for
triple redundancy. The return current is common among the TMR and daisy-chain feeds
and is brought in on the remaining three pins. The following figure shows how the R, S,
and T 28 V dc power is distributed by JPDH to the I/O packs and Ethernet switches.
J1 J1X
28Vdc Return
28V Daisy-
TMR Chain
Input 28R
Output
Power 28S
28T
JRS JSS JTS
Switch Switch Switch
Power Power Power
JR1 JS1 JT1
R
S T
Pack
Pack Pack
Pwr
Pwr Pwr
1-8
1-8 JT8 1-8
JR8 JS8
JPDH Power Flow
JPDH has 24 identical output circuits to provide power to the individual I/O packs. The
R, S, and T feeds each provide power to eight circuits. Each I/O pack circuit includes a
positive temperature coefficient fuse device for branch circuit protection. The board also
has three identical unfused output circuits to provide power to each Ethernet switch.

The following figure shows an example application with 72 I/O packs and nine
Ethernet switches powered through three daisy-chained JPDH boards.
LAN LAN LAN LAN LAN LAN LAN LAN LAN

Sw. Sw. Sw. Sw. Sw. Sw. Sw. Sw. Sw.
28Vdc
Supply JRS JSS JTS JRS JSS JTS JRS JSS JTS
"R"
IS200JPDH IS200JPDH IS200JPDH

28Vdc
Supply J1 J1X J1 J1X J1 J1X
"S"
28Vdc JR JS JT JR JS JT JR JS JT
Supply 1-8 1-8 1-8 1-8 1-8 1-8 1-8 1-8 1-8
"T"
8 8 8 8 8 8 8 8 8
P P P P P P P P P
a a a a a a a a a
c c c c c c c c c
k k k k k k k k k
s s s s s s s s s
JPDH Application Example
Specifications
Item Description
Inputs One 6-pin connection for 28 V dc power input Mate-N-Lok 600 V, 13 A
Outputs Three 2-pin connections for Ethernet switches Mate-N-Lok 600 V, 13 A
Twenty-four 2-pin connections for I/O packs Mate-N-Lok 600 V, 0.8 A
Output fuses 1.6 A positive temperature coefficient fuse or equivalent on each I/O pack output
Relative humidity 5 – 95% non-condensing
Safety standards UL 508A Safety Standard Industrial Control Equipment
EN 61010-1 Safety of Electrical Equipment, Industrial Machines (Low Voltage Directive)
Mounting DIN-Rail, card carrier mounting
Diagnostics
There are no diagnostic features on this board.
Configuration
There are no jumpers or hardware settings on this board.

JPDL Local Pack Dc Power Distribution
The Local Pack dc Power Distribution (JPDL) board provides dc power distribution
between the source of control power (possibly JPDP or JPDS) and multiple I/O
packs, as well as provides daisy chain style connections for multiple downstream
JPDL boards. Branch circuit protection is provided for each I/O pack connection
with positive temperature coefficient fuse devices.
The board is designed to make it easy to maintain up to three isolated control

power distribution circuits to complement control hardware redundancy. In a
TMR system, it will be common to have separate control power for R, S, and
T hardware. By providing for three separate power circuits on one board JPDL
allows organized separation of the control power.
Installation
JDPL mounts vertically on a metal bracket next to the I/O packs. Power input cables
come in from the back and the output cables come out of the front. All have Mate-N-Lok
connectors. For cable destinations, refer to the circuit diagram.
Output 1 Output 2 Output 1 Output 2 Output 1 Output 2

to R I/O to R I/O to S I/O to S I/O to T I/O to T I/O
Pack Pack Pack Pack Pack Pack
JL2 JL1
JR1 JR2 JS1 JS2 JT1 JT2
Output to next JPDL JPDL Local Pack Power Input from JPDP
28 V dc R, S, and T Distribution Board 28 V dc R, S, and T
JPDL Cabling

Operation
The following figure shows how the R, S, and T 28 V dc power is distributed
in JPDL, and how it reaches the I/O packs. Connector JL2 is used to daisy
chain power to multiple downstream JPDL boards.
JPDP
JP1 JP2 to JPDL JP3 to JPDL

5-pin Mate-N-Lok 5-pin Mate-N-Lok To Ethernet
Connectort Connectort Switches
JL1 5-pin JPDL

Mate-N-Lok JR1
CL
Connector I/O Pack R
JS1
CL I/O Pack S
CL JT1
I/O Pack T
JR2
CL
I/O Pack R
CL JS2
I/O Pack S
CL JT2
I/O Pack T
JL2 5-pin
Mate-N-Lok
Connector
To Next JPDL
JPDL Simplified Circuit Diagram with JPDP

Inputs
Input power is typically 28 V dc, received from JPDP or JPDS as up to three redundant
feeds. The 5-pin Mate-N-Lok input connector receives the three separate power
feeds on three different pins for triple redundancy. The feeds are designated Red,
Blue, and Black. The JP1, 2, and 3 connectors on JPDP provide this connection.
Return current is common among the three TMR feeds and is passed on the
remaining two pins of the 5-pin Mate-N-Lok connector.
Outputs
Six identical output circuits provide power feeds to individual I/O packs. Two
are sourced from each of the R, S, and T feeds (red, blue, and black). Each of
the six I/O pack feeds includes a re-setting positive temperature coefficient fuse
device, labeled CL (current limit) to provide branch circuit protection that is
coordinated with the wire between JPDL and the I/O pack.
Specifications
Item Description
Inputs One 5-pin connection with three separate 28 V dc power feeds red, blue, black, and return
Current Three power traces will each take 7.5 A continuous Each trace will take 15 A max. peak
Outputs Six 2-pin connections for I/O packs 2 red, 2 blue, 2 black
Each one with positive temperature coefficient fuse protection to 2 A
One 5-pin connection with three separate 28 V dc power feeds to red, blue, black, and return
downstream JPDLs.
Temperature -30 to +65ºC (-22 ºF to +149 ºF)
Safety UL 1604, for use in Class I, Division 2 potentially hazardous
Standards environments.
Mounting Three mounting holes
Diagnostics
Configuration

JPDM Power Distribution
The Power Distribution (JPDM) board receives 28 V dc input power from
external ac/dc or dc/dc converters and distributes power to the control system.
JPDM provides fuse protection for all outputs. JPDM integrates into the
PDM system feedback through the PPDA I/O pack.
JDPM is designed to maintain three separate power buses for R, S, and T

applications. Jumpers can be used to provide a single bus with redundant supplies.
Two adjacent JPDM boards can be wired together.
Compatibility
The IS200JPDM board is compatible with the feedback signal P1/P2 connectors
on JPDB, JPDF, and JPDE leading to a PPDA I/O pack. The DC-62 connector
on JPDM is compatible with the IS220PPDA I/O pack.
Installation
The JPDM is base-mounted vertically on a metal bracket in a cabinet used by the
PDM. Refer to the wiring diagrams for power input and output. There is a 50-pin
diagnostic connector, P1/P2, mounted on the top and bottom of the board.
Grounding
The IS200JPDM board is grounded through the sheet metal bracket to the
underlying back base. In most cases, this is the system FE.
JPDM accepts power from cables and distributes it to the JR, JS, and JT connectors.
JPDM, when hosting a PPDA I/O pack, will be mounted so indicator lights on the
pack are easily visible. Two JPDM boards, when used together, will be mounted
so that all terminal board connections are easily accessible. The location of JPDM
is not critical in a panel. Connector P1 transmits feedback signals to a board
hosting a PPDA I/O pack. Connector P2 optionally receives feedback from another
power distribution board and passes the signals out of P1 towards the PPDA. If a
feedback cable connection from JPDM P2 to another power distribution board is
used, consideration should be given to the feedback cable routing.

Application Notes
The internal wiring is designed so that three independent 28 V dc power buses can be
maintained, or all three can be combined into a single internal bus. Each bus is sized to
handle 25 A. They share a common ground sized for 75 A. With three supplies, it is
possible to operate R, S, and T controllers and their I/O from separate power supplies.
Failure of a supply can cause its controller and I/O to go offline while not affecting the
other two channels. There is a dedicated 28 V power output for the PPDA I/O pack
ensuring power system feedback is available in the event of a channel power failure.
A second method of operation has jumpers placed between the R, S, and T 28 V

bus connection screws on TB1 and TB2. The board then provides a single highly
reliable source of 28 V. Up to three supplies could power this bus with parallel
operation capability designed into the external supplies.
The screw terminals can be used to parallel the power buses from two adjacent
JPDM boards. Features offered by two boards include:
• Two sets of control rack output for Duplex or TMR applications using
redundant supplies in the control racks, or systems where more than
three supplies are to be paralleled
• Six JPDP outputs instead of three
• Separated R, S, and T power can have two input power supplies
providing supply redundancy on each bus.
In some applications, it could be desirable to apply a battery bus as a power backup. It is

possible to use a grounded battery system as input to this board using the screw terminals
on the end of the board. This requires diodes not on JPDM to provide isolation between the
battery and internal bus, because the JPDM is not designed to function as a battery charger.
During installation or repair, any configuration performed through the barrier

terminal strips must match system documentation.

Operation
The following I/O characteristics apply to the JPDM module:
• JDPM supplies three power supply inputs on JR, JS, and JT. Each connector uses
pins 8 and 9 for positive 28 V dc and pins 1-3 for 28 V dc return providing 24
A steady state capacity. These connectors include low-level signals capable of
monitoring status switches on each supply and sending feedback signals to PPDA.
Pin 4 provides +10 V dc wetting to the status switch and return is on pin 5.
• Terminal boards TB1 and TB2 at the bottom and top of the board provide access
to the three power buses. Jumpers can be used to parallel the bus between TB1
and TB2 when more than one JPDM board is used. Jumpers can also be used
between terminals PR, PS, and PT to tie the positive bus terminals together
when a single power bus is fed by redundant power supplies.
• Three fused two-pin Mate-N-Lok connectors, JCR, JCS, JCT power controllers, and
other loads. Pin 1 is +28 V dc and pin 2 is the return. A 10 A fuse protects the circuit.
• Three fused Mate-N-Lok connectors, J1, J2, and J3 have six pins each are provided to
supply R, S, and T power to remote JPDP boards. They can also supply JPDL boards
when using the proper wire harness. Pins 1 – 3 are 28 V dc return, pin 4 is +28R, pin 5
is +28S, and pin 6 is +28T. Each positive output is fused for 15 A to protect the circuits.
• A DC-62 connector, JA1, is for connecting to a PPDA I/O pack. The pack contains
status feedback signals for up to six core power distribution boards.
• P4 supplies power to the PPDA I/O pack. It uses R, S, and T power using a
diode-or arrangement in addition to a self-resetting fuse. This ensures the pack
receives power if any of the three power buses are active.
• Two 50-pin diagnostic ribbon cable connectors, P1 and P2, are supplied on the top
and bottom of the board. Connector P1 transmits feedback signals to a board hosting
a PPDA I/O pack. Connector P2, when connected, receives feedback from another
power distribution board and passes the signals out of P1 towards the PPDA.

JPDM Mechanical Board Layout

Ribbon cable,
R S T G 50-pin
Diagnostic
Daisy Chain
28 V Power Three 2-pin plugs
Supply Supply control power
Status
28 V Power
One 6-pin plug
Supply to JPDP
Supply .
Status .. Six plugs total
One 6-pin plug
28 V Power to JPDP
Supply Supply
Status
Three 2-pin plugs,
auxiliary outputs
JPDS 28 V dc
Power Distribution Board
PPDA
Power Diagnostic Diagnostic

Daisy Chain
Pack
R S T G Ribbon cable,
50-pin
JPDM Simplified Circuit Diagram
Specifications
Item Description
Inputs Three 9-pin connections for 28 V dc Power Supply inputs 25 A max each
5-screw terminal block for daisy chaining power distribution boards 35 A max per screw
Outputs J1-J3 connections for either JPDP or JPDL boards 10 A 250 V fuse per circuit,
JCR, JCS,JCT connections for controller power Bussmann MDA-10 typical.
JAR, JAS, JAT connections, filtered and fused, for auxiliary devices 10 A 250 V fuse per circuit,
P4 connection for PPDA I/O pack power Bussmann MDA-10 typical.
JA1 connection for PPDA power diagnostic pack 3.75 A self-resetting fuse per
circuit
0.25 A max
±5 V max
Agency Approval Class 1 Division 2 explosive atmosphere
Board Size 16.51 cm High x 17.8 cm Wide (6.5 in x 7.0 in)
Mounting DIN-rail mounting
Base mounted steel bracket

Diagnostics
The feedback wiring on JPDS and JPDM is different from the other PDM core boards.
One JPDS or JPDM can host the PPDA I/O pack using the JA1 connector. The
P1 connector is not used in this configuration because the output signals are going
directly to PPDA. When a second JPDS or JPDM board is used, the P1 connector
on the second board can be used for feedback into P2 of the board hosting PPDA.
In both configurations, the P2 connector provides feedback signals from other core
PDM boards. The following signals are created by JPDM:

• Three analog 28 V dc readings for the R, S, and T bus power supplies. Separate
analog feedback signals are used. Accuracy is specified at ±1% of full scale.
• Each power supply connector (JR1, JS1, JT1) has provisions for a dry
contact indicating power supply status. JPDS conditions these signals
and places them in the feedback signal set.
• Auxiliary Supply status feedback from downstream of the fuses
provides three feedback signals to PPDA.
• Three control output fuse status signals plus nine J1 – J3 fuse output
signals provide 12 feedback signals to PPDA
Due to a large signal count present on JDPM (15 fuses, 3 contacts and 3 bus voltages), a
single set of board feedback signals is not adequate to transmit the signals to a PPDA I/O
pack. Each JPDM consumes two sets of feedback signals out of the six available sets.
JPDS contains test rings for 28 V dc power from the three internal circuits, 28PR,
28PS, and 28PT. Each test ring has a series 10 k resistor to isolate the ring, and there
is a single grounded ring 28N for the return path. These can be used to measure
the 28 V dc power voltage using external test equipment.
Configuration

JPDP Local Power Distribution
The Local Power Distribution (JPDP) board provides intermediate 28 V dc power
distribution from the JPDM board to multiple JPDL boards for further distribution to
the I/O packs. JPDP also optionally provides power to Ethernet switches.
Installation
JPDP mounts in a plastic holder, which fits on a vertical DIN-rail next to other
power distribution boards. Power input and output cables have Mate-N-Lock
connectors. For cable destinations, refer to the circuit diagram.
JPDP Power Distribution Board
28 V dc 1
from J4
2
JPDM 4 JR1 To Ethernet
switch R
2
To JPDL To Ethernet
JP1 JR2
for I/O switch R
Packs
5
2
JS1 To Ethernet
To JPDL switch S
for I/O JP2
Packs
1
2
5
To Ethernet
JS2
switch S
To JPDL
JP3
1
for I/O To Ethernet

JT1 switch T
Packs
5
4 JT2 To Ethernet
28 V dc J4X switch T
1

JPDP Wiring and Cabling

Operation
The following figure shows how the 28 V dc power is distributed in JPDP, and
how it reaches the I/O packs and the Ethernet switches.
JPDP
JP1 JP2 to JPDL JP3 to JPDL

5-pin Mate-N-Lok 5-pin Mate-N-Lok To Ethernet
Connectort Connectort Switches
JL1 5-pin JPDL

Mate-N-Lok JR1
CL
Connector I/O Pack R
JS1
CL
I/O Pack S
CL JT1
I/O Pack T
JR2
CL
I/O Pack R
CL JS2
I/O Pack S
CL JT2
I/O Pack T
JL2 5-pin
Mate-N-Lok
Connector
To Next JPDL
JPDP Simplified Circuit Diagram with JPDL
Inputs
Input power is typically 28 V dc, received from the JPDM (referred to as Pbus). The
6-pin Mate-N-Lock input connector receives three separate Pbus feeds from JPDS
for triple redundancy. The feeds are designated Red, Blue, and Black.
Outputs
Three identical output circuits provide power feeds to JPDL boards. Each JPDL
output uses a 5-pin Mate-N-Lock connector. Three of the five pins are for Red,
Blue, and Black. The other two pins are for Pbus return.
Six identical outputs are provided for Ethernet switches. Two connectors are
dedicated to each of the three feeds (red, blue, and black).

Specifications
Item Description
Inputs One 6-pin connection with three separate 28 V dc Pbus feeds Red, Blue, Black, and Return
Outputs Six 2-pin connections for Ethernet Switches 2 Red, 2 Blue, 2 Black
Three 5-pin connections for JPDL boards, feeding I/O packs Each one Red, Blue, Black, and Return
One 6-pin connection with three separate 28 V dc Pbus feeds Red, Blue, Black, and Return
Temperature -30 to +65 ºC (-22 to +149 ºF)
Mounting DIN-rail, card carrier mounting
Diagnostics
Configuration

JPDS 28 V Power Distribution
The 28 V Power Distribution (JPDS) board receives 28 V dc input power from external
ac/dc or dc/dc converters and distributes power to the control system. JPDS integrates
into the PDM system feedback offered through the PPDA I/O pack.
Compatibility
The IS200JPDS board is compatible with the feedback signal P1/P2 connectors
on JPDB, JPDF, and JPDE leading to a PPDA I/O pack. The DC-62 connector
on JPDS is compatible with the IS220PPDA I/O pack.
Installation
JPDS mounts in a metal holder, which fits on a vertical DIN-rail next to other power
distribution boards. Optionally, JPDS is also available with a metal holder designed for
direct mounting. Refer to the wiring diagrams for power input and output routing. There
is a 50-pin diagnostic connector mounted on the top and bottom of the board.
Grounding
The IS200JPDS board is grounded through the sheet metal bracket to the underlying
back base. In most cases, this can be the system FE.
JPDS accepts power from cables and distributes it to the JR, JS, and JT connectors.
JPDS, when hosting a PPDA I/O pack, is mounted so indicator lights on the pack are
easily visible. Two JPDS boards, when used together, are mounted so that any terminal
board connections are easily accessible. The location of JPDS is not critical in a panel.
Connector P1 transmits feedback signals to a board hosting a PPDA I/O pack. Connector
P2 receives feedback from other power distribution boards and passes the signals out of P1
to the PPDA. If a feedback cable connection from JPDS P2 to another power distribution
board is planned, consideration should be given to the feedback cable routing.

Application Notes
The internal wiring permits either three independent 28 V dc power buses to be
maintained, or all three combined into a single internal bus. Each bus is sized to handle
25 A. They share a common ground that is sized for 75 A. With three supplies, it is
possible to operate R, S, and T controllers and their I/O from separate power supplies.
Failure of a supply can take one controller and I/O but not affect the other two channels.
There is a dedicated 28 V diode-OR power output for the PPDA I/O pack to avoid
loosing power system feedback in the event of a channel power failure.
A second method of operation has jumpers between the R, S, and T 28 V

bus connection screws on TB1 and TB2. The board provides a single highly
reliable source of 28 V. Up to three supplies could power this bus with parallel
operation capability designed into the external supplies.
The screw terminals could also be used to parallel the power buses from two
adjacent JPDS boards. Two boards offer the following features:
• Two sets of control rack output for Duplex or TMR applications using
redundant supplies in the control racks, or systems where more than
three supplies are to be paralleled
• Twelve JPDP outputs instead of six
• Separated R, S, and T power could now have two input power supplies
providing supply redundancy on each bus.
In some applications, a battery bus can be applied as a power backup. A

grounded battery system can also be used as input to this board using the
screw terminals on the end of the board. This requires diodes not on JPDS to
provide isolation between the battery and internal bus.
During installation or repair, any configuration performed through the barrier

terminal strips must match system documentation.

Operation
The JPDS is the power distribution board that receives 28 V dc power from the selected
supplies and distributes it to the JPDP boards (for power to the I/O packs) and to the
control racks. The normal 28 V power input to JPDS is through JR, JS, JT connectors.
Ribbon cable,
R S T G 50-pin
Diagnostic
Daisy Chain
28 V Power Three 2-pin plugs
Supply Supply control power
Status
28 V Power
One 6-pin plug
Supply to JPDP
Supply .
Status .. Six plugs total
One 6-pin plug
28 V Power to JPDP
Supply Supply
Status
Three 2-pin plugs,
auxiliary outputs
JPDS 28 V dc
Power Distribution Board
PPDA
Power Diagnostic Diagnostic

Daisy Chain
Pack
R S T G Ribbon cable,
50-pin
JPDS Simplified Circuit Diagram

Pbus Input/Output, 28 V dc Ribbon Cable, 50-pin, from upstream board
PR PS PT N N
P1
TB2
Outputs, 28 Vdc Pbus Inputs
to JPDP, JPDL for I/O Packs R,S,T, 28 V dc
JAT
2
1
PPDA Power
J5 J6 JT Diagnostic Pack
Auxiliary JAS
7
1
2
Outputs
1
R, S, T
JAR
1
1
J3 J4 JS P3
JCT 7
1
1
Outputs
to JCS
1
Control
1
Racks
J1 J2 JR 62-pin D-shell
R, S, T JCR
7 connector
1
1
JPDS Power Distribution Board 2 Power to
1 PPDA,
TB1 28 V dc
P4
P2
PR PS PT N N
Pbus Input/Output, 28 V dc Ribbon Cable, 50-pin, to downstream board
Sheet metal base mounting, or plastic support tray for DIN-rail mounting.
JPDS Mechanical Board Layout
The JPDS I/O characteristics are as follows:
• Three 28 V power input connectors, JR, JS, JT. The connectors on the power
supplies have two connections for positive and three connections for negative
power. In addition, there are three power supply health inputs each with two dry
contact inputs per power source, which become diagnostic signals.
• Three DC outputs, JCR, JCS, and JCT, to control rack CPCI power supplies
• Six outputs to JPDP cards through six-pin connectors J1, J2, J3, J4, J5, J6 (3x2
Mate-N-Lok). This is the same connector with the same pin assignments used on JPDP.
It is possible to directly connect up to six JPDL boards to JPDS to supply the I/O packs.
• Three outputs JAR, JAS, JAT, to auxiliary power connectors, each with
a positive temperature coefficient fuse for current limiting and containing
a common-mode choke for noise suppression
• Access to the internal 28 V bus at the board top and bottom using individual screw
terminals on TB1 and TB2. Screw terminals for R, S, and T are sized to handle
a maximum of 35 A continuous current. These terminals can be used to jumper
boards together The screw terminal for ground is sized for 75 A.
• DC-62 connector for PPDA power diagnostic I/O pack. The PPDA monitors
JPDS and up to five additional power distribution boards connected to
JPDS with a 50-pin diagnostic ribbon cable.
• P28 power output, P4, diode ORed for the PPDA power diagnostic pack

Specifications
Item Description
Inputs Three 9-pin connections for 28 V dc Power Supply inputs 25 A max each
One 50-pin ribbon cable with diagnostic data from upstream boards ±5 V max
One 5-screw terminal block for daisy chaining power distribution boards 35 A max per screw
Outputs Six 6-pin connections for either JPDP or JPDL boards 13 A max per pin
Three 2-pin connections for CPCI control rack power 12.5 A max per pin
Three 2-pin connections, filtered and fused, for auxiliary devices 1.6 A positive temperature
coefficient fuse
One 50-pin ribbon cable with diagnostic data to downstream boards ±5 V max
One 5-screw terminal block for daisy chaining power distribution boards 35 A max per screw
One 2-pin connection for 28 V dc power to the PPDA pack 0.25 A max
One 62-pin D-shell connection for PPDA power diagnostic pack ±5 V max
Agency approval Class 1 Division 2 explosive atmosphere
Mounting DIN-rail mounting
Base mounted steel bracket
Diagnostics
Diagnostic signals are obtained and routed into the PPDA pack as follows:

• Three analog P28 voltage readings for R, S, and T bus
• Each power supply connector (JR1, JS1, JT1) has provisions for a dry
contact indicating power supply status. JPDS conditions these signals
and places them in the feedback signal set.
• Auxiliary Supply status feedback from downstream of the fuses
provides three feedback signals to PPDA.
JPDS contains test rings for 28 V dc power from the three internal circuits, 28PR,
28PS, and 28PT. Each test ring has a series 10k resistor isolating the ring and a
single grounded ring, 28N, for the return path. These can be used to measure
the 28 V dc power voltage using external test equipment.
Configuration

JGND Shield Ground
The Shield Ground (JGND) terminal board mounts along side the terminal board and
provides convenient ground connections for the customer’s shield drain wires.
Installation
JGND mounts on a sheet metal bracket attached to the plate, which holds the terminal
board. JGND is grounded to the bracket with the two screws at each end of the terminal
board. The customer's shield wires connect to terminals in the Euro-type terminal block.
One or two JGND can be located on the side of the terminal board mounting
bracket, for a maximum of 48 ground connections.
JGND provides a path to sheet metal ground at the board mounting screw locations.
The default mechanical assembly of this board to its mount includes a nylon washer
between the board and the sheet metal. This isolates JGND from the sheet metal
and allows wiring of the board ground current into any desired grounding location.
Removal of the washer permits conduction of the ground currents into local sheet
metal and does not require any additional grounding leads.
At the time a JGND board is installed, a choice must be made to conduct ground currents
through a wire to designated ground (washer present) or to conduct directly to sheet metal
(washer absent). A direct connection to sheet metal is preferred. If a wire connection
is used, it should be as short as possible, not exceeding 5 cm (2 in).

Metal Mounting Plate
Terminal Board, top view
TB1
Customer wiring connections
Terminal board
Connection screws on
mounting plate
Euro terminal block Terminal board, side view
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
IS200JGNDG1
Shield wire connections Sheet metal

grounding bracket
Grounding screws at
each end of board
JGND Mounting

Operation
All 24 connectors on the Euro block are connected to ground through the two
grounding screws at the ends of JGND. These make contact with the metal mounting
bracket, which is connected to ground. If nylon washers are used to isolate the board,
ground currents must be wired into an alternate system location.
Specifications
Item Description
Terminals 24 terminals on Euro type terminal block
Mounting Held with three screws to sheet metal bracket on side of terminal board
Diagnostics
Configuration

Vendor Manufactured Control Power Supplies
The Mark* VIe control uses several Vendor Manufactured Control Power Supplies
(VMCPS). The features listed below are common to all the control power supplies:
• Convection cooling – no cooling fans used

• Ambient temperature range is -30ºC to +65ºC (-22 ºF to +149 ºF)
• 24, 28, and 48 V dc output has ±2% voltage regulation
• Compatible with Mark VIe vibration and contamination requirements
• All power supplies have a normally open dry contact for status feedback
• Support for parallel operation without extra components. Diode equivalent
is included on the output of each power supply
• Multiple supplies can load share when wired together
• Current limit and over-voltage protection of outputs
• Input filtering prevents sensitivity to input interference
• Supplies are CE marked

Operation
342A4917P150W28 and 342A4917P150W48 Power Supplies

The dc power supplies 342A4917P150W28 and 342A4917P150W48 provide bulk dc
power to electronic loads in the Mark VIe control. Power is supplied through a 3-position
terminal, Con1, mounted on the bottom of the supply. The inputs are, from left to right,
ground, neutral, and line. A switch selects the input voltage range of 93 to 132 V ac or
187 to 264 V ac. The nominal selected voltage is displayed on the switch. The full load
input current is rated 3 A at 115 V ac and 1.7 A at 230 V ac. The user must protect the
wiring with a slow blow fuse or Type C circuit breaker. The power supply is internally
protected by a 4 A, 250 V time delay fuse. In the event of ac line loss, the power supply
holdup feature will maintain the output for 25 ms for 115 V ac and 30 ms for 230 V ac.
Select the correct input voltage before applying power to

prevent damage to the power supply.
Caution
Power output is through a seven-position terminal, Con3, located on the top

of the supply. The terminal is clearly labeled on the side of the power supply
showing all its connection points. Con2 is not used.
Power supply status is a dry form C relay contact rated at 0.36 A at 60 V dc. The relay
indicates the output is within regulation, with no over-current and no over-temperature.
The relay contacts, wired to Con3, have normally open (NO) on pin 1, common on pin
2, and normally closed (NC) on pin 3. When the power supply status is OK, pin 1 to
pin 2 is closed and pin 3 to pin 2 is open. Pins 1 and 2 are typically wired to a JPDS or
JDPM power distribution board for feedback to the PPDM power diagnostic pack.
Con3
Relay
4 Current share line
3 Unit not OK (NC)
2 Common
1 Unit OK (NO)
Relay Contact
Rating
60 V dc / 0.36 A
Power Supply Relay Contacts on Con3

Two or more power supplies of the same design can be paralleled, sharing the
current equally to provide more output power. Pin 4 on Con3 provides an active
load sharing signal and must be wired between power supplies to enable sharing.
For accurate load sharing (within 10%), the negative outputs from all supplies
must be tied together within a few feet of the supplies.
The Vout Adjust potentiometer provides adjustment of the output voltage from 24
to 32 V on the 28 V model and from 48 to 52 V dc on the 48 V model. The power
supply has two indicator lamps, Bus Indicator OK and Unit OK. Bus Indicator
OK lights when input power is applied. Unit OK lights when the supply is within
regulation and has no over-current or over-temperature.
Input Select Con2 Con3

115 V / 230 V Not Used Signal I/O &
Output Power
1 Unit OK
2 Common
Pins 1 3 Unit not OK
4 Share
7 5 Share
6 Vout -
7 Vout +
Ac Input 150 W Power Supply Front View
Vout Adjust
Bus Indicator OK
Unit OK
Pins 1 2 3
Con1
Input Power
N L
Ac Input 150 W Power Supply Bottom View

34 mm 39.5 mm
(1.34") (1.56")
114.6 mm (4.51")
86.5 mm
(3.4")
5 mm
157 mm (6.18")
(0.2") 56.7 mm
(2.23")
38.5 mm 80 mm
(1.52") (3.15")
10 mm
(0.39")
Ac Input 150 W Power Supply Dimensions

342A4917P300W24 and 336A4940FEP01 Power Supplies
The dc power supplies 342A4917P300W24 and 336A4940FEP01 provide bulk
dc power to electronic loads in the Mark VIe control. Power is supplied through
the 3-position removable plug, Con1, mounted on the bottom of the supply. The
inputs are, from left to right, ground, neutral, and line. A switch, mounted on the
top of the supply, selects the input voltage range of 93 to 132 V ac or 187 to 264
V ac. The nominal selected voltage is displayed on the switch.

Caution
The full load input current is rated 5.4 A at 115 V ac and 3.3 A at 230 V ac. The
user must protect the input wiring using a slow blow fuse or a Type C circuit
breaker. The power supply is internally protected with a 6.3 A 250 V time delay
fuse. In the event of ac line loss, the power supply hold up feature will maintain
the output for 25 ms at 115 V ac and 30 ms at 230 V ac.
Power output is from Con2 and signal I/O is through the Con3 connector. Each connector
is a removable plug. The connectors are shown in the following figure.
indicates the output is within regulation, with no over-current and no over temperature.
The relay contacts, wired to Con3 have normally open (NO) on pin 1, common on pin 2,
and normally closed (NC) on pin 3. When the power supply status is OK, pin 1 to pin 2
is closed and pin 3 to pin 2 is open. Con3 is a removable plug, smaller than Con1 and
Con2. Con3 accepts 18G wire. Pins 1 and 2 are typically wired to a JPDS or JPDM
power distribution boards for feedback to the PPDM power diagnostic pack.
Two or more power supplies of the same design can be paralleled, sharing the
current equally to provide more output power. Pin 4 on Con3 provides a signal
for active load sharing. Pin 4 must be wired between power supplies for load
sharing. For accurate load sharing (within 10%), the negative outputs from all
supplies must be tied together within a few feet of the supplies.
The Vout Adjust potentiometer provides adjustment of the output voltage from 24-
32 V dc. The power supply has two indicator lamps, Bus Indicator and Unit OK.
Bus Indicator lights when input power is applied. Unit OK lights when the supply
is within regulation and has no over-current or over-temperature.

Con3
Signal I/O
1 Unit OK
2 Common
3 Unit not OK
Input Select 4 Share
115 V / 230 V
Pins 1 Con2
Output Power
4
Pins 1 1 Vout -
2 2 Vout -
3 3 Vout +
4 4 Vout +
Ac Input 300 W Power Supply Top View
Bus Indicator
Unit OK
Pins 1 2 3
Con1
Input Power
N L
Ac Input 300 W Power Supply Bottom View

342A4917P600W24, 342A4917P600W28, and 342A4917P600W48
Power Supplies
The dc power supplies 342A4917P600W24, 342A4917P600W28, and
342A4917P600W48 supply bulk dc power to electronic loads in the Mark VIe control.
Power input is through a 3-position terminal, Con1, mounted on the top left side. The
inputs are, from left to right, ground, neutral, and line. A switch selects the input
voltage range of 93 to 132 V ac or 187 to 264 V ac. The nominal selected voltage is
displayed on the switch. The full load input current is rated 10.5 A at 115 V ac and
6.4 A at 230 V ac. The user must protect the input wiring using a slow blow fuse
or Type C circuit breaker. The power supply is internally protected by a 12 A, 250
V time delay fuse. In the event of ac line loss, the power supply holdup feature will
maintain the output for 15 ms for 115 V ac, and 25 ms for 230 V ac.

Caution
Power output is through the Con2 connector. Positive dc output is on pins

3 and 4 and dc common is on pins 1 and 2.
indicates the output is within regulation, with no over-current, and no over-temperature.
The relay contacts, wired to Con3, have normally open (NO) on pin 1, common on
pin 2, and NC on pin 3. Con3 is a terminal that is smaller than Con1 and Con2.
It accepts 18G wire. Pins 1 and 2 are typically wired to a JPDS or JDPM power
distribution board for feedback to the PPDM power diagnostic pack.
Two or more power supplies can be paralleled, sharing the current equally to provide more
output power. Pin 4 on Con3 provides a signal for active load sharing. Pin 4 must be wired
between power supplies for load sharing. For accurate load sharing (within 10%), the
negative outputs from all supplies must be tied together within a few feet of the supplies.

The power supply has two indicator lamps, Bus Indicator and Unit OK. Bus
Indicator lights when input power is applied. Unit OK lights when the supply is
within regulation and has no over-current or over-temperature.
Con3
Signal I/O
Con1 1 Unit OK
Input Power Input Select 2 Common
N L 115 V / 230 V 3 Unit not OK
4 Share
Con2
Not Used Output Power
Pins 1
4 1 Vout -
Pins 1 2 Vout -
2 3 Vout +
3 4 Vout +
4
Ac Input 600 W Power Supply Top View

177.2 mm (6.98")
120.2 mm (4.73")
82.6 mm
243 mm (9.57")
(3.25")
32 (1.26) 179 mm (7.05")

82.8 mm
(3.26")
6.8 mm
(0.27")
Ac Input 600 W Power Supply Dimensions

342A4922P28V150DL and 342A4922P28V150DH Power Supplies
The dc power supplies 342A4922P28V150DL and 342A4922P28V150DH, built
specifically for the Mark VIe control, provide bulk 28 V dc power to electronic loads.
Power input is through the P1 connector, a pluggable box terminal. Positive dc input is
connected to pin 1, negative dc input to pin 2, and ground to pin 3. The input voltage
range is 18 to 36 V dc on the 24 V dc In supply and 70 to 145 V dc on the 125 V dc
In supply. The input current for the 24 V dc In power supply is 10 A at 18 V dc and 5
A at 36 V dc. This supply is internally protected with a 15 A, 125 V time delay fuse.
The input current for the 125 V dc In power supply is 3 A at 70 V dc and 1.2 A at 145
V dc. This supply is internally protected with a 4 A, 250 V time delay fuse. The user
must protect the input wiring using a time delay fuse or circuit breaker.
Power output is through the P2 connector, a pluggable box terminal. Positive dc output is
connected to pin 1 and dc common to pin 2. The supply meets the 150 W current rating
over the convection cooled temperature range of -30ºC to +65ºC (-22 ºF to +149 ºF).
indicates the output is within regulation, with no over-current and no over-temperature.
The relay contacts, wired to P2, have normally open (NO) on pin 6, common on pin 5,
and normally closed (NC) on pin 4. Pin 5 and pin 6 are typically wired to a JPDS or
JDPM power distribution board for feedback to the PPDM power diagnostic pack.
P2
Relay
4 Unit not OK(NC )
5 Common
6 Unit OK (NO)
Relay Contact
Rating
60 V dc / 0.5 A
Power Supply Relay Contacts on P2
Multiple power supplies can be paralleled, sharing current equally to provide more output
power. Pin 3 on P2 provides active load sharing. For accurate load sharing (within 10%),
the negative outputs from all supplies must be tied together within a few feet of the supplies.

The power supply has two indicator lamps, INP PWR and OUTP OK. INP PWR lights
when input power is applied. OUTP OK lights when the unit is within regulation and has
no over-current or over-temperature. The status output relay shows the same status.
152 .2 mm (5.99 ")

6 Unit OK
5 Common
4 Unit not OK
P2
3 Share
2 Vout -
1 Vout +
110 mm (4.33")
1
3 Ground
P1
2 Vin -
1 Vin +
90 mm (3.54")
Mounting Holes UNC #6-32 (11 places )
71 .6
63.01
62
45
26.99
25
0 1.6 PCB
9.86 76.92 116 .86
0 30 58.91 94 .93 121 .5
Dc Input 150 W 28 V dc Power Supply Dimensions

342A4922P28V500DL and 342A4922P28V500DH Power Supplies
The dc power supplies 342A4922P28V500DL and 342A4922P28V500DH, built
specifically for the Mark VIe control, supply bulk 28 V dc power to electronic loads.
Power is supplied through the P1 connector, a pluggable box terminal. Positive dc input
is connected to pins 3 and 4, negative dc input to pins 1 and 2, and ground to pin 5. A
ferrite filter is included in the input wiring to meet CE requirements. The input voltage
range is 18 to 36 V dc on the 24 V dc In supply and 70 to 145 V dc on the 125 V dc
In supply. The input current for the 24 V dc In power supply is 33 A at 18 V dc and
17 A at 36 V dc. This supply is internally protected with a 50 A, 300 V time delay
fuse. The input current for the 125 V dc In power supply is 8 A at 70 V dc and 4 A at
145 V dc. This supply is internally protected with a 15 A, 250 V time delay fuse. The
user must protect the input wiring using a time delay fuse or circuit breaker.
Power output is through the P2 connector, a pluggable box terminal. Positive dc input is
connected to pins 3 and 4 and dc common to pins 1 and 2. A ferrite filter is included in
the input wiring to meet CE requirements. The supply meets the 500 W current rating
over the convection cooled temperature range of -30ºC to +65ºC (-22 ºF to +149 ºF).
Power supply status is a dry form C relay contact rated at 0.5 A at 60 V dc.
The relay indicates the output is within regulation, with no over-current and no
over-temperature. The relay contacts, wired to P3, have normally open (NO) on
pin 1 and common on pin 2. P3, a removable plug smaller than P1 and P2, accepts
18G wire. Pins 1 and 2 are typically wired to a JPDS or JDPM power distribution
board for feedback to the PPDM power diagnostic pack.
P3
Relay
3 Unit not OK(N C )
2 Common
1 Unit OK (NO )
Relay Contact
Rating
60 V dc / 0.5 A
Power Supply Relay Contacts on P3
Multiple power supplies can be paralleled, sharing the current equally to provide more
output power. Pin 4 on P3 provides a signal for active load sharing. Pin 4 must be wired
between power supplies for load sharing. For accurate load sharing (within 10%), the
negative outputs from all supplies must be tied together within a few feet of the supplies.
The power supply has two indicator lamps, INP PWR and OUTP OK. INP PWR lights
when input power is applied. OUTP OK lights when the unit is within regulation and has
no over-current or over-temperature. The status output relay shows the same status.

P2
Input Power
1 Vin -
2 Vin -
3 Vin +
4 Vin + P2
5 Ground Output Power
1 Vout -
2 Vout -
3 Vout +
Pins 5 4 3 2 1 4 Vout +
Pins 1 Pins 4 3 2 1
P3
4 Signal I/O
1 Unit OK
2 Common
3 Unit not OK
4 Share
Dc Input 500 W Power Supply Top View
P1 Input Connector P3 Signal Connector
P2 Output
+ + Connector
+ + + +
5 1 4 1
26.5 (1.04)
190 mm (7.48")
64 (2.50)
115 mm (4.53") 5 (0.2)
4.6 (0.18) 97.5 mm (3.84")
90 mm (3.54")
R2.3 (0.09)
INP PWR
OUTP OK
220 mm (8.66")
200 mm (7.87")
230 mm (9.06")
243 mm (9.57")
Dc Input 500 W 28 V Power Supply Dimensions

PSFD Flame Detector Power Supply
335 VDC PS The Flame Detector Power Supply (PSFD) pack typically mounts above the primary
gas turbine trip protection (TRPG) terminal board. The source power is 28 V dc,
CURR LIM
from a power distribution board (JPDL). The output is rated for 335 V dc, 5 mA.
Three power supplies are connected to J3, J4, and J5 of the TRPG in a diode-ored,
TMR configuration to power up to eight flame detectors. Each supply can power all
P335 OUT
eight flame detectors should the other two power supplies fail.
The main features of the pack include:

P28 IN
• Convection cooling – no cooling fans used
IR PORT • Ambient temperature range is -30 to +65ºC (-22 to +149 ºF)

335 V dc • 28 V dc input ±5% (26.6 to 29.4 V dc)
336A4940CSP21
POS
Atten.
Test • Unregulated output varies with input ±5% (318 to 352 V dc)
Points NEG
IS220PSFDH1A • 1700 V dc isolation

• Output over voltage protection
• Test point pair to monitor Attenuated 335 V dc Output
• Three diagnostic LEDs
• Outputs can be diode-ored with external diode.
• Output current limit at 7 mA dc
• Soft start hot swap input limits inrush current to 550 mA peak.
• Input filtering limits emissions and reduces sensitivity to input interference

Compatibility
The PSFD provides power to the flame detector circuit on TRPG through TRPG
connectors J3, J4, and J5. The PSFD is typically mounted on sheet metal above the TRPG.
Installation
To prevent electric shock, turn off power to the pack,

then test to verify that no power exists on the module
before touching it or any connected circuits.
Warning
To prevent equipment damage, do not remove, insert,

or adjust any connections while power is applied to the
equipment.
Attention
¾ To install the PSFD pack

1. Securely mount the TRPG and install the mounting plate for the PSFD. Typically, this
mounting is on the upper level above the TRPG. To avoid risk of electrical shock, the
mounting plant must be connected to chassis ground, typically FE (Field Earth).
2. Mechanically secure the PSFD using the threaded studs on the housing. The
studs slide into a mounting brackets on the mounting plate.
3. Connect the 335 V dc cable between PSFD 2x2 connector P2 and
J3, J4, or J5 on the TRPG.
4. Apply 28 V dc power to the pack by plugging in the 1x3 connector P1 on the
side of the pack. It is not necessary to insert this connector with the power
removed from the cable as the I/O pack has inherent soft-start capability
that controls current inrush on power application.

Attention entire system, and then restart the ToolboxST Download
Wizard.

Operation
The PSFD produces 335 V dc from 28 V dc. The 28 V dc input is current limited
and hot swap compatible. The input is transformer isolated from the floating output.
The switching topology is an non-regulated fixed ratio push pull converter. The input
and output are current limited and the input is also hot swappable.
The output voltage can be monitored locally using a differential pair

of test points, attenuated 100:1.
P28IN P335
P1-1 Input Cap Bank Push Pull Transformer Bridge Output

UVLO 21 V dc Rectifier Cap Bank Series
Common Current P1-2
Circuit
Mode Filter Limiting P2-2
P1-2,3 Breaker Circuit
1.7 KV ISOL
PCOMIN N335
Primary Side Power

Controllers FETS
P28 IN LED Test Probes Output P335 OUT Current

for Output Common Mode LED Limit LED
Caps
Power Supply Block Diagram
This 25 kHz switching power supply topology is push-pull with no feedback, that is it
is open loop. The output increases and decreases proportionately to the input voltage.
The push pull transformer has a 1:12 turns ratio to raise the 28 V dc input to 336 V
dc. Diode drops reduce the output voltage another 1.5 V dc, resulting in 334 to 335 V
dc. The load regulation is good, even in this open loop design, because the current
capacity of the power stage is much greater than the required load current.
The input circuit breaker provides inrush current protection as well as over current
protection. During current limiting, the breaker modulates a series pass FET on and
off to limit power dissipation. The PSFD is hot pluggable and will not disturb other
sensitive loads if it is connected to an operating P28 V dc bus. If a circuit failure and short
circuit occur downstream of the circuit breaker, the fast acting circuit breaker prevents this
short from propagating onto the 28 V dc bus. An EMI filter reduces noise propagation
onto the 28 V dc bus. A 33 V transorb, immediately after the input connector, protects
the PSFD from voltage transients and momentary reverse bias connections.
The output limiter restricts the output current to 7 mA, even during a direct short.
The output can stay shorted indefinitely even in a 65°C (149 °F) ambient. A
385 V MOV provides transient protection at the output.

Status LEDs
The PSFD displays three status LEDs:
• Current Limit, Red, DS3 – activates at 6-7 mA.

• P335 Out, Green, DS2 – high voltage may be present at the output. A precise
voltage level cannot be discerned from this LED.
• P28 In, Green, DS1 – voltage is present at the input. A precise voltage
level cannot be discerned from this LED.
The input and output LEDs do not indicate any particular voltage level and
simply annunciate the presence of input or output voltage. Similarly, the current
limit LED is for indication only and does not provide a measurement of the over
current magnitude. The current limit LED is in series with the signal path for the
activation signal. In the event that the current limit LEDs fails open, a circuit
bypasses the LED and the limiter continues to function.
Specifications
Item PSFD Specification
Maximum Input Voltage 29.4 V dc
Under voltage lockout (UVLO) range 22.1 – 26.4 V dc
Inrush current limit 550 mA for 40 uS, 300 mA steady state
Start up time at full load, 28 V dc 34 mS
Input current at full load, 28 V dc 137 mA
Input current ripple at full load, 28 V dc 66 mA at 50 kHz
Power consumption at full load, 28 V dc 4.1 W
Maximum power consumption at full load, 29.4 V dc input 4.5 W
Full load output 5 mA
Output short circuit current limit with self recovery 7 mA
Minimum output voltage, full load, 26.6 V dc input 317 V dc
Output voltage at full load, 28 V dc input 333 V dc
Maximum output voltage, no load, 29.4 V dc input 355 V dc
Output over voltage protection 385 V MOV
Efficiency at full load 0.4
Load regulation -0.005
Typical output ripple at full load 520 m Vp-p at 50 kHz
Line regulation 0.11
Nominal switching frequency 25 ±6 kHz
Test point attenuation of 335 V dc 100:1 Referenced to case
Voltage isolation, output to input 1700 V dc
Size 8.26 cm high x 4.19 cm wide x 12.1 cm deep (3.25 in x 1.65
in x 4.78 in)
Temperature, operating -30 to +65ºC (-22 to +149 ºF)
Assembly technology Surface mount

Diagnostics
Test Points
The output voltage can be monitored locally using a differential pair of test points. The
positive and negative test points connect to the positive and negative outputs through
100:1 attenuators which are referenced to the chassis for safety. Each test point can be
touched without risk or electrical shock. Furthermore, each test point can be shorted to
the chassis indefinitely. The test points are designated TP_POS (inboard) and TP_NEG
(outboard). The test points are accessed by rotating the round plastic cover on the top.
Configuration
The output voltage from each PSFD is attenuated and sensed on the TRPG terminal
board. The sensed voltage is monitored by the PTUR or VTUR modules. In
a TMR configuration, if any of the three PSFD fails to provide 335 V dc, an
alarm is annunciated in the ToolboxST* application or HMI.

Notes

Replacement/Warranty
Replacement
Handling Precautions
To prevent component damage caused by static
electricity, treat all boards with static sensitive handling
techniques. Wear a wrist grounding strap when
handling boards or components, but only after boards
or components have been removed from potentially
Caution energized equipment and are at a normally grounded
workstation.

shock, burn, or death. Ensure that all Lockout/Tag Out
procedures are followed prior to replacing terminal
boards. Only personnel who are adequately trained
and thoroughly familiar with the equipment and the
Warning instructions should install, operate, or maintain this
equipment.
Printed wiring boards may contain static-sensitive components. Therefore,

GE ships all replacement boards in anti-static bags.
Use the following guidelines when handling boards:
• Store boards in anti-static bags or boxes.

• Use a grounding strap when handling boards or board components
(per previous Caution criteria).
GEH-6721L Replacement/Warranty System Guide 27-1

Replacement Procedures
The failed board should be System troubleshooting should be at the circuit board level. The failed pack/board
returned to GE for repair. Do should be removed and replaced with a spare. Replacement of the terminal board or
not attempt to repair it on site. full IS230 module requires full re-configuration of the changed component using the
ToolboxST application. For this reason, it is generally preferable to replace only the
I/O pack unless the terminal board is known to be the point of failure.
To prevent electric shock, turn off power to the turbine

control, then test to verify that no power exists in the
board before touching it or any connected circuits.
Warning
To prevent equipment damage, do not remove, insert, or

adjust board connections while power is applied to the
equipment.
Caution
Replacing I/O Packs

¾ To replace an I/O pack
1. Lockout and/or tagout the field equipment and isolate the power source.
2. Remove the power to the I/O pack.
a. For the PSVP, turn SW1 on the SSVP to the P28OFF position.
b. For other I/O packs, remove the power plug located in the
connector on the side of the I/O pack.
3. Unplug the Ethernet cables and mark the positions of the removed cables.
4. Loosen the two mounting nuts on the I/O pack threaded shafts.
5. Unplug the I/O pack.
6. Verify that the replacement I/O pack is compatible with one being replaced by
comparing the model numbers on their faceplates. The model number begins
with an IS220P prefix. Most times the numbers will match, but sometimes
newer revisions are used to replace older I/O packs.
7. Plug in the replacement I/O pack. Make sure it is fully inserted into the slots
on the mounting base, then properly tighten the mounting nuts.
8. Plug the Ethernet and power cables back into the I/O pack and
re-energize the equipment.
If the Auto-Reconfiguration feature is enabled and the

controller detects the I/O pack running with a different
configuration, a reconfiguration file is automatically
downloaded from the controller. Refer to the section,
Attention Auto-Reconfiguration.

Replacing D-type Boards
¾ To replace the board
1. Lockout and/or tag out the field equipment and isolate the power source.
2. Unplug the I/O cable (J-plugs).
3. Disconnect all field wire and thermocouples along with shield wire.
4. Remove the terminal board and install the new board.
5. Reconnect all field wire and thermocouples as before.
6. Plug the I/O cable (J-plug) back.
Replacing J-type Boards

1. Lockout and/or tag out the field equipment and isolate the power source.
2. Check the voltage on each terminal to ensure no voltage is present.
3. Verify the label and unplug all connectors.
4. Loosen the two screws on each of the terminal blocks and remove the top portion
leaving all field wiring in place. If necessary, tie the block to the side out of the way.
5. Remove the mounting screws and the terminal board.
6. Install a new terminal board. Check that all jumpers, if applicable, are in
the same position as the ones on the old board.
7. Tighten it securely to the cabinet.
8. Replace the top portion of the terminal blocks and secure it with the screws
on each end. Ensure all field wiring is secure.
9. Plug in all wiring connectors.

Replacing S-type Boards
2. Check the voltage on each terminal to ensure there is no voltage present.
3. Unplug the I/O cable (J-plugs)
4. If applicable, unplug JF1, JF2, and JG1.
5. If applicable, remove the TB3 power cables.
6. A S-type terminal board uses a Euro-style box terminal block. Gently pry
the segment of the terminal block, containing the field wiring, away from
the part attached to the terminal board, leaving the wiring in place. If
necessary, tie the block to the side out of the way.
7. Remove the mounting screws and terminal board.
8. Install a new terminal board. Check to ensure all jumpers, if applicable, are
in the same position as the ones on the old board.
9. Tighten it securely to the cabinet.
10. Slide the segments containing field wiring into the terminal block. Ensure the
numbers on the segment with the field wires match the numbers on the terminal
block. Press together firmly. Ensure all field wiring is secure.
Replacing T-type Boards

2. Check the voltage on each terminal and ensure no voltage is present.
3. Unplug the I/O cable (J-Plugs).
4. If applicable, unplug JF1, JF2, and JG1.
5. If applicable, remove TB3 power cables.
6. Loosen the two screws on the wiring terminal blocks and remove the
blocks, leaving the field wiring attached.
7. Remove the terminal board and replace it with a spare board, check that all
jumpers are set correctly (the same as in the old board).
8. Screw the terminal blocks back in place and plug in the J-plugs
and connect cable to TB3 as before.

Replacing a BAPA Module
¾ To replace the BAPA
2. Unplug the HSSL Ethernet cable from the module to be removed. Cut loose
any cord ties fastening the cable to the module.
3. Unscrew the retaining hardware on the BAPA module and remove the module.
4. Place the new module in the location of the old module and securely
tighten retaining hardware.
5. Plug the HSSL Ethernet cable into the module and secure the cable.
Replacing a SAMB
3. Disconnect the power cables from P28-1 and P28-2.
4. Remove the BAPA module(s).
5. Gently pry the segments of the terminal blocks, containing the field wiring,
away from the part attached to the terminal board, leaving the wiring in place.
If necessary, tie the blocks to the side out of the way.
6. Remove the screws securing the shield ground bus, leaving the shield grounds
in place. If necessary, tie the shield bus to the side out of the way.
7. Loosen the four mounting screws and remove the SAMB module.
8. Install a new IS210SAMB module. Check to ensure all jumpers are in
the same position as the ones on the old board. If the new module has an
attached shield ground bus, then remove the bus from the new module and
discard. Securely tighten the module to the panel.
9. Attach the shield ground bus to the SAMB module.
10. Slide the segments containing field wiring into the terminal block. Ensure the
numbers on the segment with the field wires match the numbers on the terminal
block. Press together firmly. Ensure all field wiring is secure.
11. Replace the BAPA modules and reconnect the power cables to P28-1 and P28-2.

Replacing a SSVP
3. Turn SW1 on the SSVP terminal board to the P28OFF position.
4. Remove both the WSVO servo driver module and the PSVP I/O pack.
5. Unplug Ethernet cables from connectors JUA, JLA, JUB and JLB when
the PSVP is configured for dual redundancy.
6. Unplug the 2-pin plug from the P28IN Mate-N-Lok® connector on the SSVP.
7. Remove the 24-point connector plug from the TB1 connector on the SSVP.
8. If the DIN-rail base needs to be removed, then remove the grounding
screws on the left side of the Din-rail base.
Replacing a SCLS
3. Remove the power from connector P1 on PCLA.
4. Unplug the Ethernet cables and mark the positions of the cables to remove.
5. Unplug SCLT connection-cable from J2 connector.
6. Unplug all field wires from the SCLS module and fold them back out of the way.
7. Loosen the two mounting screw-nuts on the pack sides.
8. Unplug the PCLA and install the new PCLA. Tighten the side screw-nuts back.
9. Remove the top and bottom-mounting screws from the SCLS base
sheet metal and remove the module.
10. For ease of access before mounting replacement module, copy all configuration
jumper positions from the module that has been removed to the replacement module.
11. Mount the replacement SCLS using the corner mounting screws. Check that
all jumpers are set correctly (the same as on the old board).
12. Install the pack on new SCLS. Tighten the side screw-nuts back.
13. Plug the field wire terminals into the new SCLS board. It is always a good idea to
quickly check that no wires became loose in a terminal due to flexing and movement.
14. Replace the cables from SCLT on J2 connector.
15. Replace the Ethernet connection(s) on the pack.
16. Complete the lockout and/or tagout procedure to re-establish power to the system.
17. Apply power to the module through the P1 connector on PCLA.

Replacing a SCLT
3. Unplug the 68 pin cables on JR/ JS / JT to one or more PCLA modules. Be sure to
pull the connector straight off of the board to avoid damaging a connector pin.
4. Unplug all field wires from the SCLT terminals and fold them back out of the way.
5. Remove the terminal board and replace it with a spare board. Check that all
jumpers are set correctly (the same as on the old board).
6. Plug the field wire terminals into the new SCLT terminal board.
Note It is always a good idea to quickly check that no wires became loose in a terminal
due to flexing and movement.
7. Replace the cables on JR/ JS / JT and the Ethernet connection(s). Be sure to insert
the connector straight into the board to avoid connector pin damage.
8. Complete the lockout and/or tagout procedure to re-establish power to the system
Replacing UCSA Modules

¾ To replace the module
1. Lockout or tagout the field equipment and isolate the power source.
2. Disconnect the power cable at the top of the UCSA.
3. Unplug the Ethernet cables from the UCSA to be removed. Cut any
cord ties fastening the cables to it.
4. Unscrew the retaining hardware on the UCSA, then remove it.
5. Remove the flash part from the top of the UCSA.
6. Place the removed flash part into the new UCSA.
7. Place the new UCSA in the old location and securely tighten the retaining hardware.
8. Plug the Ethernet cables into the UCSA, then secure the cables.
9. Connect the power cable to the top of the UCSA.
Replacing Controller Components

¾ To replace controller components
♦ Refer to the following sections: CPCI Component Replacement, Controller

Battery, Cooling Fan, Power Supply Replacement.

Renewal Warranty
How to Order a Board
When ordering a replacement board for a GE product, you need to know:
• How to accurately identify the part

• If the part is under warranty
• How to place the order
Board Identification
A printed wiring board is identified by an alphanumeric part (catalog) number
located near its edge. The board’s functional acronym, displayed below, is
normally based on the board description, or name.
IS 200 xxxx G# A A A
Artwork revision
Functional revision 1
Hardware form 2
Hardware form
Functional acronym
Assembly level 3
Manufacturer (DS & IS for GE in Salem, VA)

1
Backward compatible
2
Not backward compatible
3 200 = a base-level board
215 = a higher level assembly or added components

220 = pack specific assembly
230 = a higher level module
Board Part Number Conventions

Note I/O packs follow the same board part number convention except Functional revision is
listed after rev. on the label, and they do not have an Artwork revision.
I/O Pack Part Number Convention
Placing the Order

Renewals/spares (or those not under warranty) should be ordered by contacting the
nearest GE Sales or Service Office, or an authorized GE Sales Representative. Be
sure to include:
• Complete part number and description
• Serial number
• Material List (ML) number
Note All digits are important when ordering or replacing any board. The factory may
substitute newer board versions based on availability and design enhancements, however, GE
Energy ensures backward compatibility of replacement boards.

GE Energy
1501 Roanoke Blvd.
1 540 387 7000

GEH-6721 Vol II

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GE Energy GEH-6721L

Mark* VIe Control Vol. II

HE APPLIQUÉ IS TO BE PLACED ON EACH

© 2004 - 2010 General Electric Company, USA. All rights reserved.

* Trademark of General Electric Company

We welcome comments and suggestions to make this publication more useful.

Excellent Good Fair Poor Additional Comments

Superior Comparable Inferior Do not know Comments .............................................

........................................................................................Fold here first........................................................................................

Indicates a procedure, condition, or statement that, if not

Indicates a procedure, condition, or statement that,

Indicates a procedure, condition, or statement that

Note Indicates an essential or important procedure, condition, or statement.

A margin note is used to

This equipment contains a potential hazard of electric

Isolation of test equipment from the equipment under

Warning To minimize hazard of electrical shock or burn, approved

To prevent personal injury or equipment damage caused

In a simplex system, this includes process inputs/outputs to the I/O packs.

• Process inputs/outputs to the I/O packs

In a triple modular redundant (TMR) system:

• Process inputs/outputs to the I/O packs

1-2 Mark* VIe Control Vol. II System Hardware Guide

¾ To replace the controller battery

UCCx Controller Battery

1-4 Mark* VIe Control Vol. II System Hardware Guide

¾ To replace the cooling fan

Replacing CPCI Cooling Fan

The IS200EPMC contains specific controller hardware functions as follows:

• Power supply monitoring

STAT LED (Reserved ) M STAT ON

UCCA Front View

1-6 Mark* VIe Control Vol. II System Hardware Guide

Airflow requirements as measured at the output side of

JUMPER NAME JUMPER FUNCTION JUMPER POSITION

E206 BATTERY ENABLE 1 – 2 ***

NO JUMPER E207 E209

UCCA Controller Jumper Settings

1-8 Mark* VIe Control Vol. II System Hardware Guide

UCCC Front View

1-10 Mark* VIe Control Vol. II System Hardware Guide

Airflow requirements as measured at the output side of

UCCC Jumper Location and Settings

Power supply connector pin definitions

The plug connector is AMP# 350550-7 or equivalent with

Bulk Input power connector

1-12 Mark* VIe Control Vol. II System Hardware Guide

The following rack parts are available.

Catalog # # Power Supplies Ports Power Inputs

Bottom View Bottom View

Part 1 (Single Power Supply) Part 2 (Dual Power Supply)

CPCI Component Replacement

¾ To replace the CPCI controller

1-14 Mark* VIe Control Vol. II System Hardware Guide

Cooling fan compartment

¾ To install a new CPCI power supply(s)

Replacing CPCI Power Supply

1-16 Mark* VIe Control Vol. II System Hardware Guide

The following power supply is supported.

Catalog # Input Voltage

Replacing CPCI Power Supply

1-18 Mark* VIe Control Vol. II System Hardware Guide