Solid State Electronics 141 (2018) 65–68

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Solid State Electronics

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Enhanced transconductance in a double-gate graphene field-effect transistor T

a b c a a
Byeong-Woon Hwang , Hye-In Yeom , Daewon Kim , Choong-Ki Kim , Dongil Lee ,
⁎
Yang-Kyu Choia,
a
School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 34141, Republic of Korea
b
Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 34141, Republic of Korea
c
Department of Electronic Engineering, Kyung Hee University, 1732 Deogyeong-daero, Giheung-gu, Yongin 17104, Republic of Korea

A R T I C L E I N F O A B S T R A C T

The review of this paper was arranged by Dr. Y. Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si
Kuk transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally
Keywords: demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are
Double-gate electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both
Field-effect transistor the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also
Graphene fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were mea-
Transconductance sured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG
GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance
was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation
of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate
architecture for high-performance graphene transistor technology.

1. Introduction been developed for several-nanometer-thick Silicon channel can still be

Graphene has attracted considerable interest as a promising mate-
rial for high-performance electronic devices due to its unique physical
properties, such as atomically thin thickness [1], flexibility [2], high
carrier mobility [3,4], and high thermal conductivity [5]. Due to the
zero bandgap of graphene, the possible applications of graphene field-
effect transistors (GFETs) are considered to be more suitable for high-
frequency analog electronics [6–8], or detectors [9,10], rather than
digital logic technology which requires a definite switching capability
between an “on” and “off” state. One of the fundamental performance
metrics of a FET is the controllability of the gate over the channel re-
sistivity which is manifested as the transfer characteristics.
The transfer characteristics of GFETs have been extensively studied
with a variety of structural considerations including a hexagonal boron
nitride (hBN) substrate [11], a solution gate [12], a side gate [13], a
high-quality gate dielectric layer [14] and a folded graphene channel
[15]. Although it has been well-known in CMOS technology that a
multi-gate structure, the mainstream of state-of-the-art nanoscale
transistor design nowadays, greatly improves gate-to-channel control
efficiency of a transistor [16,17], few studies have been done on the
application of the multi-gate technique to GFETs. This raises the
question of whether the advantage of a multi-gate structure that has
effective for the one-atom-thick 2D channel. Furthermore, the pre-
viously reported double-gate structure of graphene transistors refers
only to a metallic top gate and silicon substrate gate that act as two
independent electrodes [18–22], not a pair of connected electrodes that
applies an electric field symmetrically and simultaneously to both sides
of the graphene channel. It should be noted that the aforementioned
GFET is not a genuine double-gate structure but a quasi double-gate
structure.
In this work, we report the fabrication of a double-gate graphene
field-effect transistor (DG GFET) that is capable of modulating the
graphene channel by the top and bottom gate simultaneously and
symmetrically. The transfer characteristics of the fabricated DG GFET
were compared to those of the single-gate graphene field-effect tran-
sistor (SG GFET) counterpart. The different characteristics between the
SG and DG GFETs were further examined with a compact model for
GFETs.
2. Experimental details
A highly doped (1–3 mΩ⋅cm) silicon wafer with a 90-nm-thick
thermal SiO2 was used as a substrate for the device fabrication. The
bottom gate for the DG structure was patterned on a SiO2 substrate with

⁎
Corresponding author.
E-mail address: ykchoi@ee.kaist.ac.kr (Y.-K. Choi).

https://doi.org/10.1016/j.sse.2017.12.008
Received 17 August 2017; Accepted 19 December 2017
Available online 20 December 2017
0038-1101/ © 2017 Elsevier Ltd. All rights reserved.
B.-W. Hwang et al. Solid State Electronics 141 (2018) 65–68

photolithography, and a Cr/Au (3/40 nm) stack was deposited with

thermal evaporation. The bottom-gate dielectric film consists of a high-
κ dielectric of 20-nm-thick Al2O3 film deposited by atomic layer de-
position (ALD). Subsequently, a CVD-grown monolayer graphene was
transferred onto the Al2O3 layer with polymethyl methacrylate
(PMMA)-assisted wet-transfer method [23]. The graphene channel was
defined by photolithography and followed by oxygen plasma etching
for removal of the graphene outside the channel. The source and drain
contacts were formed by evaporating Cr/Pd/Au (3/20/60 nm). An ad-
ditional Al2O3 film that is identical to the bottom-gate dielectric was
formed to act as the top-gate dielectric. Before the top-gate electrode
deposition, in order for the top gate to be electrically connected to the
bottom gate, a contact area was defined by photolithography, and the
dielectric layer of Al2O3 inside the contact area were etched with dilute
hydrofluoric acid. Finally, the top-gate electrode of Cr/Au (3/120 nm)
was thermally evaporated to complete the device fabrication. As a
control device, single-gate (SG) devices were also fabricated using the
exact same procedure described above except for the bottom gate for-
mation. DC electrical characterizations were carried out in a vacuum
chamber (3 mTorr) at room temperature, with the Agilent 4156C Fig. 2. (a) Transfer characteristics of a single-gate (SG) GFET (left) and a double-gate
Semiconductor Parameter Analyzer. (DG) GFET (right). Drain current (Id) is plotted as a function of the gate-to-source voltage
(Vg) for fixed values of the drain-to-source voltage (Vd) increasing from 0.5 to 2.0 V. (b)
3. Results and discussion Output characteristics of a SG GFET (left) and a DG GFET (right). Id is plotted as a
function of Vd for fixed values of Vg-VDirac increasing from 0.85 to 5.85 V. The devices
have a gate length of 4 μm and a channel width of 6.5 μm.
Fig. 1(a) shows a cross-sectional schematic of the DG GFET devel-
oped in this work. The graphene channel is encapsulated by the Al2O3
dielectric layers at the top and bottom interface. The cross-sectional characteristics with an electron conduction regime and hole conduction
transmission electron microscopy (TEM) images of the DG GFET in regime, and the regimes are demarcated by the minimum conductivity
Fig. 1(b) confirms that the double-gated structure and dielectric layers point [24]. The two regimes have their own maximum transconduc-
of Al2O3 were successfully fabricated as designed. The device used in tance which is frequently used as a figure of merit for the current
this study had a gate length of 4 μm and a channel width of 6.5 μm. The modulation of graphene FETs [2,11,14,15]. The fact that the maximum
gate underlap, which is the distance between the source/drain elec- transconductance point occurs only once throughout the voltage sweep
trode and gate controlled region, was 2.3 μm. in each regime [14,25,26] makes the comparison of the maximum
Fig. 2(a) shows the transfer characteristics of the two different transconductances of the GFETs a useful method for performance eva-
GFETs, one with a conventional single-gate (SG) structure (left) and the luation. The transconductances, gm = dId/dVg, of the fabricated SG
other with a double-gate (DG) structure (right). Drain current (Id) is GFET (left) and DG GFET (right) are shown in Fig. 3(a), showing the
plotted as a function of the gate-to-source voltage (Vg) for fixed values apparent improvement by adopting the double-gate structure. Fig. 3(b)
of the drain-to-source voltage (Vd) increasing from 0.5 to 2.0 V. It is compares the maximum transconductance (gm, max) between the SG and
shown that the slope of the transfer curve is increased. Fig. 2(b) shows DG GFETs for a drain-to-source voltage of 0.5 and 2.0 V. The maximum
the output characteristics of a SG GFET (left) and a DG GFET (right). Id transconductances were extracted from five different devices on the
is plotted as a function of Vd for fixed values of Vg-VDirac increasing from same wafer to examine possible device-to-device variations. At
0.85 to 5.85 V, where the Vg was chosen in such a way that the cross- Vd = 0.5 V, the SG GFETs have an average gm, max of 17.1 μS/μm,
over of Id-Vd curves can be shown. The drain conductance of the DG
GFET is slightly increased as well.
Typical graphene field-effect transistors exhibit ambipolar transfer

Fig. 1. (a) Cross-sectional schematic of the DG GFET used in this study. (b) Cross-sec-
tional TEM images of the fabricated DG GFET. Monolayer graphene is in between the
layers of Al2O3. Scale bar is 100 nm (left) and 10 nm (right).
Fig. 3. (a) Transconductance (gm) of the SG GFET (left) and the DG GFET (right). Id is
plotted as a function of the Vg for fixed Vd increasing from 0.5 to 2.0 V. (b) Comparison of
the maximum gm between SG and DG GFETs. Maximum gm values were extracted from
five different devices in the same wafer to check device-to-device variation. (c) Transfer
characteristics and transconductances of SG (line) and DG (symbol) GFETs obtained with
the compact model from [27] under Vd = 2.0 V.

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B.-W. Hwang et al.
whereas the DG GFETs have a value of 25.7 μS/μm which is about a
50% enhancement (46% at Vd = 2.0 V). The difference in transcon-
ductance between the SG and DG GFETs was also reproduced with the
aid of the compact model of GFETs from [27] shown in Fig. 3(c). The
enhanced percentage of the gm, max was 67.4% (SG: 15.3 μS/μm and
DG: 25.6 μS/μm) in accordance with the tendency that was experi-
mentally demonstrated. The simple relationship between the net mobile
carrier charge density, Qc, in the graphene channel and the gate voltage
is
1 1
− 2 Cq Ct − 2 Cq Cb
Qc = (Vtg−VtDirac ) + (Vbg−VtDirac)
1 1
Ct + Cb + C
2 q
Ct + Cb + 2 Cq
where Vtg–VtDirac and Vbg–VbDirac are the top and bottom-gate overdrive
voltage, Ct and Cb are the top and bottom dielectric capacitance and Cq
is the quantum capacitance of the graphene [27]. In (1), Vbg is a con-
stant for the SG structure, while Vbg is equal to Vtg when a GFET op-
erates with the DG structure, resulting in increased Qc compared with
SG structure at the same Vtg. However, the drain current in drift-dif-
fusion theory is approximately given by Id = −WQcv where v is the
carrier drift velocity at the source end, and v decreases with the in-
creased Qc in a GFET [28]. Thus, the enhanced transconductance of the
DG GFET can be attributed to the increased modulation of the carrier
concentration in the graphene channel by the gates, and this is valid
before Vg-VDirac is high enough, i.e., when the high carrier concentra-
tion starts to significantly reduce the concentration-dependent carrier
velocity and therefore the current modulation. Using the model, at the
maximum transconductance point, the calculated Qc was increased
from 2.52 × 10−7C/cm2 for the SG to 3.62 × 10−7C/cm2 for the DG
transistor, whereas the carrier drift velocity was decreased from
1.19 × 106 cm/s (SG) to 0.95 × 106 cm/s (DG). dQc/dVg was increased
from −3.58 × 10−7C/Vcm2 to −7.50 × 10−7C/Vcm2, and dv/dVg was
increased from 1.06 × 106 cm/Vs to 1.25 × 106 cm/Vs for SG and DG
respectively, indicating improved carrier modulation and faster velocity
decrease rate for DG GFETs. As a result, d(Qcv)/dVg was increased by
62.7% for DG, which quantitatively explains the amount of transcon-
ductance enhancement in terms of carrier concentration and velocity. It
should be noted that although some parameters such as RC delay are
not improved by DG structure, improved performance is expected in
sensor applications, of which the sensitivity or the responsivity is de-
pendent on the transconductance [9,10].
4. Conclusion
We have fabricated DG GFETs and investigated their transfer
characteristics in comparison with SG GFETs. The maximum trans-
conductance of the GFET showed a 50% improvement by introducing
an additional gate (double-gate). This improvement was also re-
produced with an analytical model for GFETs, and the contribution of
carrier density and velocity was calculated. This study showed experi-
mentally that the application of a double-gate structure to a graphene
transistor has an advantage in terms of electrostatic control by the gate.
The results of this study show the potential of a multi-gate GFET which
can be extended to the application of a fin or a gate-all-around structure
in other 2D material-based transistors.
Acknowledgement
This research was supported by the Pioneer Research Center
Program through the National Research Foundation of Korea, which is
funded by the Ministry of Science, ICT & Future Planning (Grant No.
2012-0009600). This work was also supported by the Center for
Integrated Smart Sensors funded by the Ministry of Science, ICT &
Future Planning as Global Frontier Project (CISS-2011-0031848).
Solid State Electronics 141 (2018) 65–68
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Yang-Kyu Choi received the B.S. and M.S. degrees from

Seoul National University, Seoul, South Korea, in 1989 and
1991, respectively, and the Ph.D. degree from the
University of California at Berkeley, Berkeley, CA, USA, in
2001. He is currently a professor with the School of
Electrical Engineering, Korea Advanced Institute of Science
and Technology, Daejeon, South Korea.

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