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TOPIC Page No.
1
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
CHAPTER-1
SEMICONDUCTOR
01. Consider two energy levels : E1, E ev above the mobility of carriers
Fermi level and E2, E ev below the Fermi level, (GATE (EC) - 1987) (2M)
P1 and P2 are respectively the Probabilities of E1
being occupied by an electron and E2 being (a) Depends upon the temperature of the
empty. Then semiconductor
(GATE (EC) - 1987) (2M) (b) Depends upon the type of the semiconductor
(a) P1 > P2 (c) Varies with life time of the semiconductor
(b) P1 = P2 (d) Is a universal constant.
(c) P1 < P2
(d) P1 and P2 depend on number of free elctrons 05. The diffusion capacitance of a p-n junction
(GATE (EC) - 1987) (2M)
02. In an intrinsic Semiconductor the free electron (a) Decreases with increasing current and
concentration depends on : increasing temperature
(GATE (EC) - 1987) (2M) (b) Decreases with decreasing current and
increasing temperature
(a) Effective mass of electrons only
(c) Increases with increasing current and
(b) Effective mass of holes only increasing temperature
(c) Temperature of the Semiconductor (d) Does not depend on current and
(d) Width of the forbidden energy band of the temperature
semiconductor
09. In a uniformly doped PN junction, doping level 12. Consider the semiconductors A and B. The figure
of the n side is four times the doping level of shows variation of ln p with 1/T, where p
the p side. The ratio of depletion width xn/xp is resistivity and T the temperature, for the
will be two semiconductors. Choose the correct
statements (s)
(GATE (EC) - 1990)
(GATE (EC) - 1993)
(a) 0.25 (b) 1.0
(c) 0.5 (d) 2
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ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
13. A small concentration of minority carries is 17. The depletion capacitance, CJ of an abrupt
injected into a homogeneous Semiconductor P-n junction with constant doping on either side
crystal at one point. An electric field of 10V/cm varies with reverse bias VR as
is applied across the crystal and this moves the (GATE (EC) - 1995) (1M)
minority carries a distance of 1cm in 20 sec.
The mobility (in cm²/v-sec) will be (a) CJ VR (b) CJ VR–1
(c) 560A / cm 2 (d) 1120 A / cm 2 24. n-type silicon is obtained by doping silicon with
(GATE (EC) - 2003)
(a) Germanium (b) Aluminium
20. The intrinsic carrier density at 300K is
1.5×1010/cm³, in silicon for n-type silicon doped (c) Boron (d) Phosphorus
to 2.25 × 1015 atoms/cm³, the equilibrium
electron and hole densities are
25. The longest wavelength that can be absorbed by
(GATE (EC) - 1997) (2M) silicon, which has the bandgap of 1.12 eV, is
(a) n = 1.5 × 1015/cm³, p = 1.5 × 1010/cm³ 1.1 m . If the longest wavelength that can be
absorbed by another material is 0.87 m , then
(b) n = 1.5 × 1010/cm³, p = 2.25 × 1015/cm³
the bandgap of this material is
(c) n = 2.25 × 1015/cm³, p = 1.0 × 105/cm³
(GATE (EC) - 2004)
(d) n = 1.5 × 1010/cm³, p = 1.5 × 1010/cm³
(a) 1.416 eV (b) 0.886 eV
(c) 0.854 eV (d) 0.706 eV
q
21. The unit of are
KT
26. Consider an abrupt p - junction. Let Vbi be the
(GATE (EC) - 1998) built-in potential of this junction and VR be the
(a) V (b) V–1 applied reverse bias. If the junction
(c) J (d) J/K cap acit ance C j is 1pF for Vbi VR 1V,
then for Vbi VR 4V, C j will be
22. The electron and hole concentration in a intrinsic (GATE (EC) - 2004)
semiconductor are ni and pi respectively. When
doped with a p-type material, these change to n (a) 4 pF (b) 2 pF
and p, respectively. Then (c) 0.25 pF (d) 0.5 pF
(GATE (EC) - 1998)
5
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
27. In an abrupt p - n junction, the doping impurity concentration (ND) in the sample is
concentrations on the p - side and n - side (GATE (EC) - 2004)
are N A 9 1016 / cm 3 and N D 1 1016 / cm 3
(a) 2 × 1016 / cm³ (b) 1 × 1016 / cm³
respectively. The p - n junction is reverse biased
(c) 2.5 × 1015 / cm³ (d) 5 × 1015 / cm³
and the total depletion width is 3m, The
depletion width on the p-side is
(GATE (EC) - 2004) 32. A Silicon sample A is doped with 1018atoms/cm³
of Boron. Another sample B of identical
(a) 2.7 m (b) 0.3 m dimensions is doped with 1018atoms/cm³ of
(c) 2.25 m (d) 0.75 m Phosphorus. The ratio of electron to hole mobility
is 3. The ratio of conductivity of the sample A to
B is
28. The intrinsic carrier concentration of silicon sample (GATE (EC) - 2005)
at 300 K is 1.5 × 1016 / m³. If after doping, the
number of majority carriers is 5 × 1020 / m³, the 1
minority carrier density is (a) 3 (b)
3
(GATE (EC) - 2003)
2 3
(a) 4.50 × 1011 / m³ (b) 3.33 × 104 / m³ (c) (d)
3 2
(c) 5.00 × 1020 / m³ (d) 3.00 × 10–5 / m³
35. The concentration of minority carriers in an 1.2 V is 2 m . For a reverse bias of 7.2 V, the
extrinsic semiconductor under equilibrium is depletion layer width will be
(GATE (EC) - 2006)(IES (EE) - 2011) (GATE (EC) - 2007)
(a) directly proportional to the doping (a) 4 μ m (b) 4.9 μ m
concentration
(c) 8 μ m (d) 12 μ m
(b) inversely proportional to the doping
concentration
(c) directly proportional to the intrinsic 39. The electron and hole concentrations in an
concentration intrinsic semiconductor are ni per cm³ at 300 K.
Now, if acceptor impurities are introduced if with
(d) inversely proportional to the intrinsic a concentration of NA per cm³(Where NA >> ni)
concentration the electron concentration per cm³ at 300 K will
be
36. A heavily doped n-type semiconductor has the (GATE (EC) - 2007)
following data : (a) ni (b) ni + NA
hole - electron mobility ratio : 0.4
18
n i2
Doping concentration : 4.2 × 10 atom /m³ (c) NA – ni (d)
NA
Intrinsic concentration : 1.5 × 1014 atom/m³
The ratio of conductance of the n-type
semiconduct or t o that o f the intrinsic 40. Which of the following is NOT associated with a
semiconductor of same material and at the same p-n junction ?
temperature is given by (GATE (EC) - 2008)
(GATE (EC) - 2006) (a) Junction
(a) 0.00005 (b) 2,000 (b) Charge Storage Capacitance
(c) 10,000 (d) 20,000 (c) Depletion Capacitance
(d) Channel Length Modulation
37. Under low level injection assumption, the injected
minority carrier current for an extrinsic
semiconductor is essentially the 41. A silicon wafer has 100 nm of a oxide on it and is
inserted in a furnace at a temperature above
(GATE (EC) - 2006) 1000°C for further oxidation in dry oxygen. The
(a) diffusion current oxidation rate
(b) drift current (GATE (EC) - 2008)
(c) recombination current (a) Is independent of current oxide thickness and
temperature
(d) induced current
(b) Is independent of current oxide thickness but
depends on temperature
38. A p+ n junction has a built-in potential of 0.8 V. (c) Slows down as the oxide grows
The depletion layer width at a reverse bias of
7
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(d) Is zero as the existing oxide prevents further (a) V–1 (b) cm . V–1
oxidation. (c) V . cm–1 (d) V . s
42. Silicon is doped with boron to a concentration Common Data for Question 46 and 47
of 4×1017 atoms/cm³. Assume the intrinsic carrier
concentration of silicon to be 1.5×1010/cm³ and Consider a silicon p-n junction at room
the value of kT/q to be 25 mV at 300 K. temperature having the following parameters :
Compared to undoped silicon, the Fermi level of Doping on the n - side = 1 × 1017 cm–3
doped silicon
Depletion width on the n-side = 0.1 m
(GATE (EC) - 2008)
Depletion width on the p-side = 0.1 m
(a) goes down by 0.13 eV
Intrinsic carrier concentration = 1.4 × 1010 cm–3
(b) goes up by 0.13 eV
Thermal voltage = 26 mV
(c) goes down by 0.427 eV
Permittivity of free space = 8.85 ×10–14 F cm–1
(d) goes up by 0.427 eV
Dielectric constant of silicon = 12.
following statements is TRUE for a p-n junction (c) 4.32 × 10³ A/cm² (d) 6.48 × 10² A/cm²
20 3
with N A N D 10 / cm
(GATE (EC) - 2010) 51. Drift current in semiconductors depends upon
(a) Reverse breakdown voltage is lower and (GATE (EC) - 2011)
depletion capacitance is lower (a) only the electric field
(b) Reverse breakdown voltage is higher and (b) only the carrier concentration gradient
depletion capacitance is lower
(c) both the electric field and the carrier
(c) Reverse breakdown voltage is lower and concentration
depletion capacitance is higher
(d) both the electric field and the carrier
(d) Reverse breakdown voltage is higher and concentration gradient
depletion capacitance is higher
61. Which one of the following equations represents 64. The depletion region or space charge region or
the energy gap (EG) variation of silicon with transition region in a semiconductor p-n junction
temperature (T)? diode has
(IES (EE) - 2006) (GATE (EC) - )
(a) EG T 2.11 3.60 104 T (a) electrons and holes
(b) positive ions and electrons
(b) EG T 1.21 3.60 104 T
(c) no ions, electrons or holes
(c) EG T 1.41 2.23 104 T (d) negative ions and holes
11
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
80. Consider the following statements regarding a 83. As the temperature of a ‘p’ type semicondutor is
semiconductor : gradually and continuously increased, the Fermi
1. Acceptor level lies close to the valence band level will move
2. Donor level lies close to the valence band (IES (EE) - 1997)
3. n-type semiconductor behaves as a conductor (a) into the valence band
at zero Kelvin. (b) into the conduction band
4. p-type semiconductor behaves as an insulator (c) towards the middle of the forbidden gap
at zero Kelvin.
(d) into the region between the acceptor level
Of these statements: and the valence band.
(IES (EC) - 1998)
(a) 2 and 3 are correct 84. Two initially identical samples A and B of pure
(b) 1 and 3 are correct germanium are doped wit h do nors to
concentrations of 1 × 1020 m–3 and 3 × 1020 m–3
(c) 1 and 4 are correct respectively. If the hole concentration in A is
(d) 3 and 4 are correct 9 × 1012 m–3 , then the hole concentration B at
the same temperature will be
81. In a p-n junction, the space charge capacitance (IES (EE) - 1997)
is proportional to V–n where V is the applied bias (a) 3 × 1012 m–3 (b) 7 × 1012 m–3
voltage and ‘n’ is a constant. The value of ‘n’ for
(c) 11 × 1012 m–3 (d) 27 × 1012 m–3
step linearly graded and diffused junctions would
be respectively.
(IES (EC) - 1998) 85. Consider the following statements :
Pure germanium and pure silicon are example of
1 1 1 1 1 1
(a) , , (b) , and 1. direct band-gap semiconductors
2 3 2.5 3 2 2.5
2. indirect band-gap semicondutor
1 1 1 1 1 1
(c) , and (d) , and 3. degenerate semiconductors
2 2.5 3 3 2.5 2
Of these statements
(IES (EE) - 1997)
82. In switching devices, gold doping is used to
(a) 1 alone is correct (b) 2 alone is correct
(IES (EC) - 1998)
(c) 3 alone is correct (d) 1 and 3 are correct
(a) improve bonding
(b) reduce storage time
86. Silicon carbide reinforced aluminium metal matrix
(c) increase the mobility of the carrier composites find application in
(d) protect the terminals against corrosion.
(IES (EE) - 1997)
(a) the manufacture of transformer cores
14
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
EF
A.
87. If an intrinsic semiconductor is doped with a very EV
small amount of boron, then in the extrinsic
semiconductor so formed, the number of electrons
and holes will
EC
(IES (EE) - 1997)
(a) decrease B.
EF
EV
(b) increase and decrease respectively
(c) increase
(d) decrease and increase respectively
EC
15
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
16
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
96. Match List-I (Semiconductor parameters) with 98. Consider the following statements : A tunnel
List-II (Physical processes) and select the diode is
correct answer using the codes given below 1. made of Ge or GaAs.
the lists:
2. an abrupt junction with both sides heavily
(IES (EE) - 2000) doped.
List-I 3. a hyper junction with both sides heavily
A. Impurity concentration doped.
B. Carrier mobility 4. a mojority carrier device.
C. Carrier life time Which of these statements are correct ?
D. Intrinsic carrier concentration (IES (EE) - 2000)
List-II (a) 1 and 2 (b) 3 and 4
1. Recombination (c) 1, 3 and 4 (d) 1, 2 and 4
2. Band to band transition
3. Scattering 99. The sensitivity of a photodiode depends upon
4. Ion implantation (IES (EE) - 2000)
Codes: (a) light intensity and depletion region width
A B C D (b) depletion region width and excess carrier
(a) 3 4 2 1 life time
17
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(c) The reverse saturation current 105. The Fermi energy EF of a metal is proportional
to (n is the number of free electrons per unit
(d) The transient current volume of the metal) as
(IES (EE) - 2011)
102. A structure obtained by lightly doped n-drift
1
region between the layers of pn junction a PIN (a) n² (b) n 2
diode is obtained. This structure is effective in:
2 3
(IES (EE) - 2011) (c) n 3 (d) n 2
(a) Making the diode support large reverse
blocking voltages
106. If w is the width of the depletion region in a
(b) Making reverse recovery process slow p-n junction, the transition capacitance is
(c) Making the diode have high on-state proportional to
voltage-drop (IES (EE) - 2011)
(d) Reducing the voltage spike during turn off (a) w (b) w²
due to stray inductance
(c) 1/w (d) 1/w²
104. Controlled addition of group III element to an 108. The current flow in a semiconductor is due to
elemental semiconductor results in the formation
of 1. Drift current
110. The concentration of hole-electron pairs in pure (b) concentration of electrons in conduction
silicon at T = 300 K is 7 × 1015 per cubic meter. band
Antimony is droped into silicon in a proportion (c) energy of electron concentration in
of 1 atom in 107 atoms. Assuming that half of conduction band
the impurity atoms contribute electrons in the
(d) conductivity of electrons in conduction
conduction band, the factor by which the
band
number of charge carries increases due to
doping (the number of silicon atoms per cubic
metre is 5 × 1028) is 114. Hall effect is usefull for the measurement of a
(IES (EC) - 2012) semiconductor’s
(a) 14 × 1015 (b) 0.5 × 1021 (IES (EC) - 2012)
(c) 2.5 × 1021 (d) 1.8 × 105 (a) mobility, carrier concentration and
temperature
(b) type (n - type or p - type), conductivity
111. A potential barrier of 0.50 V exists across a
and temperature
p-n junction. If the depletion region is
5.0 × 10–7 m wide, what is the intensity of the (c) type (n - type or p - type), mobility and
electric field in this region ? carrier concentration
(IES (EC) - 2012) (d) mobility, conductivity and temperature
(a) 1.0 × 106 V/m (b) 2.5 × 10–7 V/m
(c) 2.5 × 107 V/m (d) 2.5 × 108 V/m
20
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
per second, for this case. The hole lifetime and 09. How does conduction take place in intrinsic
electron lifetime are equal, and equal to 1 sec . semiconductor ?
(GATE (EC) - 1997) Explain with examples. What are the limitations
of intrinsic semiconductors and how are these
taken care of by extrinsic semiconductors ? Show
that the minimum value of conductivity of a
semiconductor with impurity is min 2neee
Where
ne – concentration of conduction electrons (m–3)
e – electronic charge (C),
– mobility of electrons (m2 V–1 s–1)
(IES (EE) - 1997)
Evaluate the hole and electron diffusion currents
at x = 34.6 m .
10. What is Hall effect in semi-conductors ? Explain
Following expressions and data can be used in
its origin and significance. Deduce on expression
this evaluation:
for Hall coefficient.
dp dn (IES (EE) - 1998)
J P qD p ; J n qDn
dx dx
Where 11. What do you understand by charge carriers ?
Dp = 12 cm²/sec; dn = 30 cm²/sec. Explain the phenomenon of conduction by free
electrons, ions and holes and classify materials
q = 1.6 × 10–19 coloumbs (kt/q) = 26 mV.
accordingly.
(IES (EE) - 1998)
07. Show that a semiconductor has minimum
conductivity at a given temperature when
12. Consider an abrupt p-n junction with donor
n ni h / e & p ni e / h density ND = 1017 atoms/cm³ and acceptor
density NA = 0.5 × 1016 atoms/cm³. Sketch
(IES (EC) - 1998) the charge distribution about the junction and
estimate the junction width when
08. A photocathode is illuminated with radiation of (IES (EE) - 1999)
wavelength 500 nm. The cathode has a work (i) no external voltage is applied, (assume the
function of 1.2 eV. Calculate the anode voltage junction barrier voltage to be 0.7 V)
required to produce zero anode current. When
the anode voltage is +90V, find the velocity of (ii) with an external voltage of – 10 V applied.
the electrons at the anode if the cathode is Assume uniform charge distribution on both
illuminated with radiation of wavelength 250 nm. sides of the junction in the space charge region.
(IES (EC) - 1997) Assume an r of 10 for the material and
0 = 8.85 × 10–12 F/m
21
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
13. (a) Distinguish between direct and indirect concentration of Si is 1.5 × 102.6.m³ and
bandgap materials with suitable E-k relative permittivity is 11.8.
diagrams.
(b) The bandgap of GaAs and AlAs are
How would you make an intrinsic (GaAs 1.43 ev and 2.16 ev respectively.
sample n-type or p-type ? What happens Assuming the bandgap of AlxGa1–x As to
when GaAs is dopen with Si ? What is vary linearly with x between the two
the nature of bonding in GaAs ? extreme values, find the value of x that
would result in the emission of 680 nm
(a) An n-type Ge sample is 2 mm wide and from Alx Ga1–x As.
0.2 mm thick. A current of 10mA is passed
through the sample (x-direction) and a (IES (EC) - 2011)
magnetic field of 0.1 web/m² is directed
perpendicular to the current flow (z-
direction). The developed Hall voltage is 16. Explain the Hall effect in semiconductors and
1.0 mV. Calculate the Hall coefficient and define Hall constant. What do you mean by
electron concentration negative Hall constant ?
(IES (EE) - 2011)
(IES (EC) - 2011)
23
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
ANSWER KEY
01. c 30. b 61. b 92. c
02. c 31. b 62. c 93. b
03. c 32. b 63. d 94. b
04. a 33. c 64. c 95. b
05. b 34. b 65. b 96. c
06. c 35. b 66. b 97. b
07. c 36. d 67. a 98. c
08. c 37. a 68. c 99. b
09. a 38. a 69. a 100. b
10. b 39. d 70. c 101. c
11. a 40. d 71. c 102. b
12. 41. c 72. b
103. a
13. c 42. c 73. d
104.
14. d 43. a 74. a
105.
15. b 44. c 75. c
16. d 45. a 76. d 106.
17. c 46. b 77. d 107.
18. c 47. b 78. b 108.
19. d 48. c 79. d 109.
20. a 49. c 80. c 110. c
19. b 50. a 81. a 111. a
20. c 51. c 82. b 112. a
21. b 52. d 83. b 113. b
22. d 53. d 84. a 114. c
23. b 54. d 85. a
24. d 55. b 86. d
25. a 56. c 87. d
26. d 57. c 88. a
27. b 58. a 89. b
28. a 59. c 90. c
29. c 60. b 91. d
24
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
CHAPTER-2
DIODES
01. For a p-n junction match the type of breakdown KT
with phenomenon (d) V = Exp I 1
q
(GATE (EC) - 1988) (2M)
(1) Avalanche breakdown
03. The switching speed of P+N junction (having a
(2) Zener breakdown heavily doped P region) depends primarily on:
(3) punch through (GATE (EC) - 1989) (2M)
(a) collision of carriers with crystal ions (a) The mobility of minority carriers in the
(b) Early effect P+ -region
(c) Rupture of covalent bond due to strong (b) The lifetime of minority carriers in the
electric field. P+ -region
(a) 1-b ; 2-a ; 3-c (b) 1-c ; 2-a ; 3-b (c) The mobility of majority carriers in the N-
region
(c) 1-a ; 2-b ; 3-c (d) 1-a ; 2-c ; 3-b
(d) The lifetime of majority carriers in the N-
region.
02. In the circuit shown the current voltage
relationship when D1 and D2 are identical is
given by (Assume Ge diodes) 04. In a zener diode.
(GATE (EC) - 1988) (2M) (GATE (EC) - 1989) (2M)
(a) only the P-region is heavily doped.
(b) only the N-region is heavily doped.
(c) both P and N-regions are heavily doped.
(d) both P and N-regions are lightly doped.
25
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
06. For the same a.c. voltage and load impedance, 100 mA flows. If the voltage across this
which of the following statements about rectifier combination is instantaneously reversed to
are correct ? 10 V at t = 0, the reverse current that flows
(GATE (EC) - 1990) through the diode at t = 0 is approximately given
by
(a) The average load current in a full-wave
rectifier is twice that in a half-wave rectifier (GATE (EC) - 1992)
08. The small signal capacitance of an abrupt P+n 11. In the circuit of Figure, the switch ‘S’ is closed at
junction is 1nf/Cm² at zero bias. If the built-in t = 0 with il (0) = 0 and vc (0) = 0. In the steady
voltage is 1 volt, the capacitance at a reverse state vc equals.
bias voltage of 99 volts is
(GATE (EE) - 1992)
(GATE (EC) - 1991) (2M)
(a) 10 (b) 0.1
(c) 0.01 (d) 100
26
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
13. The built-in potential (Diffusion Potential) in a 15. A zener diode works on the principle of
p-n junction
(GATE (EC) - 1995) (1M)
(GATE (EC) - 1993) (2M)
(a) tunneling of charge carriers across the
(a) is equal to the difference in the Fermi-level junction
of the two sides, expressed in volts
(b) thermionic emission
(b) Increases with the increase in the doping
(c) diffusion of charge carriers across the
levels of the two sides
junction
(c) Increases with the increase in temperature
(d) hopping of charge carriers across the
(d) is equal to the average of the Fermi levels junction.
of the two sides.
0. 8 0. 4
(c) A (d)
(b)
27
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
17. A zener diode in the circuit shown in Figure, (c) a resistance and an ideal diode in series
has a knee current of 5 mA, and a maximum (d) a resistance.
allowed power dissipation of 300 mW. What
are the minimum and maximum load currents
that can be drawn safely from the circuit, 20. The static characteristic of an adequately
keeping the outout voltage V0 constant at 6V ? forward biased p-n junction is a straight line, if
(GATE (EC) - 1996) the plot is of
(GATE (EC) - 1998) (1M)
(a) logI vs.logV (b) logI vs.V
(c) I vs logV (d) I vs V.
(c) 5 and16.7%
18. For full wave rectification, a four diode bridge
rectifier is claimed to have the following (d) 25 and16.7%
advantages over a two diode circuit :
1. less expensive transformer,
22. The RMS value of a half-wave rectified
2. smaller size transformer, and symmetrical square wave current of 2A is
3. suitability for higher voltage application. (GATE (EE) - 1999)
(GATE (EC) - 1998) (1M)
(a) 2A (b) 1 A
(a) only (1) and (2) are true
(b) only (1) and (3) are true (c) 1/ 2 A (d) 3A
(c) only (2) and (3) are true
(d) (1), (2) as well as (3) are true 23. For the circuit in Fig. the voltage v0 is
(GATE (EC) - 2000)
19. For small signal ac operation, a practical
forward biased diode can be modelled as
(GATE (EC) - 1998) (1M)
(a) a resistance and a capacitance in series
(b) an ideal diode and resistance in parallel.
28
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
R I =10 mA
L
27. The forward resistance of the diode shown in
+
400 0k figure is 5 and the remaining parameters are
same as those of an ideal diode. The dc
component of the source current is
Vin D
Z V 0
(GATE (EE) - 2002) (IES (EE) - 2009)
33. The circuit shown in the figure is best described 500 mA. Assuming that the Zener diode is ideal
as a (i.e, the Zener knee current is negligibily small
(GATE (EC) - 2003) (1M) and Zener resistance is zero in the breakdown
region), the value of R is
(GATE (EC) - 2004)
R
Output +
~ 12 V
-
5V
Variable Load
100 to 500 mA
34. A voltage signal 10 sin t is applied to the circuit 36. Assuming that the diodes are ideal in figure,
with ideal diodes, as shown in figure. The the current in diode D 1 is
maximum and minimum values of the output
waveform Vout of the circuit are respectively. (GATE (EE) - 2004) (2M)
1 K 1 K
(GATE (EE) - 2003) (2M)
10 K
+ D1 D 2
IZ
5V
+
V in Vout
8V
4V 4V
-
10 K
- (a) 8 mA (b) 5 mA
(b) + 4 V and -4 V
(c) + 7 V and -4 V 37. In a full-wave rectifier using two ideal diodes,
Vdc and Vm are the dc and peak values of the
(d) + 4 V and -7 V voltage respectively across a resistive load. If
PIV is the peak inverse voltage of the diode,
then the appropriate relationships for this rectifier
35. In the Voltage regulator shown in the figure, are
the load curent can vary from 100 mA to
(GATE (EC) - 2004)
31
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
Vm
(b) Vdc 2 , PIV 2Vm 40. A Silicon PN junction diode under reverse bias
has depletion region of width 10m .The relative
Vm
(c) Vdc 2 , PIV Vm permittivity of Silicon, r 11.7 and the
permittivity of free space 0 8.85 1012 F / m.
Vm The depletion capacitance of the diode per square
(d) Vdc , PIV Vm
meter is
(GATE (EC) - 2005)
38. The current through the Zener diode in figure is (a) 100F (b) 10F
(GATE (EE) - 2004) (1M)
(c) 1F (d) 20F
2.2 K
R = 0.1 K
Z
10 V
R 1 3.5 V (GATE (EE) - 2005) (1M)
-
V = 3.3 V
Z
D1
2 K
(a) 33 mA (b) 3.3 mA 1 mA
(DC)
(c) 2 mA (d) 0 mA I
2 K
D2
32
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
1 Codes:
+
E F G H
2
(a) 4 2 1 3
(b) 2 4 1 3
1K VR
5V 5V (c) 3 4 1 2
(d) 1 3 2 4
-
45. For the circuit shown below, assume that the
(a) VR 5 (b) VR 5 zener diode is ideal with a breakdown volatge
of 6 volts. The waveform observed across R is
(c) 0 VR 5 (d) 5 VR 0
(GATE (EC) - 2006)
6V
G. Zener diode
H. Schottky diode 12 V
Group 2 (c)
1. Voltage reference -6 V
33
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
1
V0
1
D2
D1 1 D3
(b) 5
5V
10 V 5 Vi
D1 V0 10
2 (d)
8
RL=
10 Vi
10 V 5V
34
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
49. Group I lists four types of p-n junction diodes. (c) 7.14 to 7.43 V (d) 7.29 to 7.43 V
Match each device in Group 1 with one of the
options in Group II to indicate the bias
condition of that device in its normal mode of 51. The correct full wave rectifier circuit is
operation. (GATE (EC) - 2007) (1M)
(GATE (EC) - 2007)
Group 1
P. Zener Diode
Q. Solar cell
(a) Input
R. LASER diode
Output
S. Avalanche photodiode
Group 2
1. Forward bias
2. Reverse bias
Codes:
In put
P Q R S
(b) Output
(a) 1 2 1 2
(b) 2 1 1 2
(c) 2 2 2 1
(d) 2 1 2 2
Input
50. For the Zener diode shown in the figure, the
Zener voltage at knee is 7 V, the knee current (c) Output
(d) In put
O utput
(a) + -
Vi 10 sin 100t is applied. Assume that the
diode drop is 0.7 V when it is forward biased.
The Zener breakdown voltage is 6.8 V.
10 k
10 sin out V 0
1K
D1
(b)
~ 5V
-1 0 V
36
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
+ V-
1 1
+5.7 V
(d) 0
t +
V i 1A
-
-1 0 V
55. In the voltage doubler circuit shown in the (a) min Vi ,1 (b) max Vi ,1
figure, the switch ‘S’ is closed at t = 0.
Assuming diodes D1 and D2 to be ideal, load (c) min Vi ,1 (d) max Vi ,1
resistance to be infinite and initial capacitor
voltages to be zero. The steady state voltage
across capacitors C1 and C2 will be 57. The following circuit has a source voltage Vs
as shown in the graph. The current through the
(GATE (EE) - 2008) (2M) cicuit is also shown
l a b
l
+ R 10 K
VS
-
5
(c) VC1 5V , VC2 10 V
VS(Volts)
-5
(d) VC1 5V , VC2 10 V
-10
-15
0 100 200 300 400
56. In the circuit below, the diode is ideal. The
voltage V is given by 1.5
0.5
-0.5
-1
-1.5
0 100 200 300 400
37
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(b) l a b
l
(c) l a b
l
38
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
Assuming forward voltage drops of the diodes 63. The diodes and capacitors in the circuit shown
to be 0.7 V, the input-output transfer are ideal. The voltage v(t) across the diode D1
characteristic is is
(GATE (EE) - 2011) (GATE (EC) - 2012) (1M)
(a)
v 0.7
A, v 0.7 V
i 500
0 A, v 0.7 V
(c)
39
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
66. In the circuit shown below, the knee current of 68. Match list I-V characteristics given below with
the ideal Zener diode is 10mA. To maintain 5V Gunn diode, Photo diode and Tunnel diode.
across RL. the minimum value of RL in and (IES (EE) - 2006)
the minimum power rating of the Zener diode
in mW respectively, are I
V
A.
Exponential
40
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
Select the correct answer using the code given 71. Intermediate (l) layer of PIN - diode imparts
below: which one of the following features to a pn
Gunn Photo Tunnel junction diode?
69. In a single phase full wave controlled bridge 72. In the circuit given below , D1 and D 2 are ideal.
rectifier, minimum output voltage and maximum Which one of the following represents the
output voltage are obtained at which conduction transfer characteristics of the circuit?
angles? (IES (EE) - 2007)
(IES (EE) - 2007)
D
1
6 K
(c) 0o , 0o respectively V in V
out
4 K
Vm (a)
(a) VDC I DC R f
10 V Vi
Vm
(b) VDC V 0
Vm
(c) VDC I DC R f
(b)
Vm
(d) VDC 0.707 I DC R f 5V
5V V
i
41
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
V 0
1 K
5V 10 V V
i
V 0
+
12 sin t ~ -
4V
10 V
(d)
(a) 4 mA (b) 8 mA
10 V Vi (c) 12 mA (d) 16 mA
73. Find the break region (Voltage range) over 76. For a rectifier circuit, percentage voltage
which the dynamic resistance of a diode is regulation is equal to which one of the following?
multiplied by a factor of 1000. Let this region
be contained between V 1 and V 2, then (IES (EE) - 2008)
42
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
Codes:
A B C D
(a) 3 4 5 2
(b) 2 5 1 3
(c) 3 5 1 2
(d) 2 4 5 3
(a) 25 A anticlockwise
+
(b) 25 A clockwise
(c) 50 A anticlockwise
C V (t)
0
(d) 50 A clockwise
~ V sin t
m
2. Voltage reference
3. Light detection
~ V sin t
m
4. Negative resistance
5. High frequency switching a) 0 (b) Vm /
43
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
83. In a centre tap full wave rectifier, 100V is the D. Schottky diode
peak voltage between the centre tap and one List - II
end of the secondary. What is the maximum
1. Reverse current varies directly with the
voltage across the reverse biased diode?
amount of light
(IES (EE) - 2005)
2. Exhibits negative resistance region in its
(a) 200V (b) 141 V I-V charcteristics
(c) 100V (d) 86 V 3. Uses only majority carriers and is intended
for high frequency operations
84. Consider the circuit given below where R1 is 4. Silicon p-n junction diode that is desgined
for limiting the volatge across the terminals
the diode forward resistance and R L the load
in reverse bias
resistance
Codes:
What is the average rectified current equal to?
A B C D
(IES (EE) - 2006)
(a) 2 3 1 4
Rf
(b) 1 4 2 3
(c) 2 4 1 3
V sin t R Output
m L
(d) 1 3 2 4
44
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
86. What is the reverse recovery time of a diode 89. Bridge rectifiers are preferred because
when switched from forward bias VF to reverse (IES (EE) - 2001)
bias VB ?
(a) they require small transformer
(IES (EE) - 2005)
(b) they have less peak inverse voltage
(a) Time taken to remove the stored minority
carriers (c) they need small transformer and also have
less peak inverse voltage
(b) Time taken by the diode voltage to attain
zero value (d) they have low ripple factor
(c) Time to remove stored minority carriers
plus the time to bring the diode voltage to 90. Consider the following statements in connection
reverse bias VR with the biasing of semi-conductor diodes:
(d) Time taken by the diode current to reverse 1. LEDs are used under forward-bias
condition
87. The reverse saturation current of a Si-biased 2. Photodiode are used under forward bias
p-n junction diode increases 32 times due to a condition
rise in ambient temperature. If th original 3. Zener diodes are used under reverse-bias
temperature was 40°C, what is the final condition
temperature?
4. Variable capacitance diodes are used
(IES (EE) - 2006) under reverse - bias condition
(a) 90°C (b) 72°C Which of these statements are correct?
(c) 45°C (d) 50°C (IES (EE) - 2002)
(a) 1, 2 and 3 (b) 1, 2 and 4
88. Consider the following statements about a (c) 2, 3 and 4 (d) 1, 3 and 4
Tunnel diode?
(IES (EE) - 2009)
91. In the single phase diode bridge rectifier shown
1. Tunnelling takes place at a speed decided in Figure, the load resistor is R=50 . The
by junction temperature
source voltage is v = 200 sin t , where
2. Concentration of impurities is of the order
of 1 part in 10³ 2 50 radians per second. The power
dissipated in the load resistor R is
3. Both tunneling curent and normal pn
junction injection current exist
4. Tunnel dio de exhibits resistance
characteristic only
Which of these statements is / are correct?
(a) 1 only (b) 1 and 2
(c) 2 and 3 (d) 3 and 4
45
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(a) D3 ; 1V (b) D1 ; 2V
93. In the circuit of Figure, the current ip through
the ideal diode (zero cut in voltage and forward (c) D2 ; 5V (d) D1 ; 5V
resistance) equals
46
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(a)
(d)
(a)
(b)
(c) 4 1,2,4 1 3
(d) 3 1,2,4 4 1
D 2
+ Pdc I rms
(a) Pac (b) 1
220 V C I dc
50Hz 12 V VDC
- 2
I dc I dc
(b) 1 (d) I rms
I rms
(a) 12V (b) 12 2V
50
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
3. provide discharge to capacitors so that (b) The diodes that are to be used in a full
output becomes zero when the circuit has wave rectifier should be rated Vm and in
been de-energised. bridge rectifier equal to 2 Vm
Which of these statements are correct ? (c) All diodes should be rated for Vm only
52
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(a) it cannot withstand high temperatures (a) 1 and 2 only (b) 1, 2 and 3
(b) its reverse saturation current is low (c) 3 only (d) 3 and 4 only
(c) its cut-in voltage is high
(d) its breakdown voltage is high 137. The output Vdc from the below circuit is
(IES (EC) - 2010)
134. Consider the following statements about a good
power supply :
1. The a.c. ripple should be high
2. SV (Voltage stability factor) should be low.
3. ST (Temperature stability factor) should
be low.
Which of the above statements are correct ? 12
(a) 12 2 (b)
(IES (EC) - 2009)
(a) 1, 2 and 3 (b) 2 only 24 12
(c) 3 only (d) 2 and 3 only (c) (d)
2
135. Which of the following does not show non- 138. A rectifier (without filter) with fundamental ripple
linear V-I characteristics ? frequency equal to twice the mains frequency
(IES (EC) - 2009) has ripple factor of 0.482 and power
conversion efficiency equal to 81.2%
(a) Schottky diode
The rectifier is
(b) Tunnel diode
(IES (EC) - 2010)
(c) Thermister, at a fixed temperature
1. Bridge rectifier
(d) p-n junction diode
2. Full-wave (non bridge) rectifier
3. Half-wave rectifier
136. Consider the following statements :
Which of these are correct ?
When compared with a bridge rectifier, a
centre-tapped full wave rectifier. (a) 2 and 3 only (b) 2 only
1. Has larger transformer utilization factor (c) 1 and 2 only (d) 1, 2 and 3
2. Can be used for floating output terminals
i.e. no input terminal is grounded 139. Consider the below circuit, for Vi = Vm sin ωt ,
3. Needs two diodes instead of four. the output voltage V0 for RL will be
4. Needs diodes of a lower PIV rating. (IES (EC) - 2010)
Which of these statements is/are correct ?
(IES (EC) - 2010)
54
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(c)
(a)
55
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
143. For a full-wave rectifier, with sinusoidal input 147. Consider the following statements:
and inductor as filter, ripple factor for maximum
1. A zener diode degrades the input signal
load current and minimum load current
at high frequencies due to its transition
conditions are respectively
capacitance.
(IES (EC) - 2012)
2. The zener voltage VZ does not vary with
(a) 0.1 and 1 (b) 0.1 and 0.47 temperature
(c) 0 and 0.47 (d) 0 and 0.22
3. Regulation of the zener diode is adversely
affected at the knee current IZ due to
144. The ripple factor in case of a full-wave rectifier limited power dissipation capacity.
is 4. In a simple zener diode regulated circuit,
(IES (EC) - 2013) amplification is not possible
(a) 1.21 (b) 0.50 Which of these statements are correct ?
(c) 0.48 (d) 1.0 (IES (EE) - 2011)
(a) 1, 2, 3 and 4 (b) 3 and 4
145. The maximum efficiency of half-wave rectifier
is (c) 2 and 3 (d) 1 and 4
146. Statement (I) : Centre tap transformer is (a) Maximum (b) Zero
essential for a centre-tapped rectifier (c) Positive (d) Negative
Statement (II) : In half wave rectification
minimum two diodes are required
149. Material used for fabrication of Tunnel diode is
(IES (EC) - 2013)
(IES (EE) - 2012)
(a) Both Statement (I) and Statement (II) are
individually true and Statement (II) is the (a) Ge or GaAs (b) Si and GaAs
correct explanation of Statement (I) (c) Si and InSb (d) Ge and InSb
(b) Both Statement (I) and Statement (II) are
individually true but Statement (II) is not
the correct explanation of Statement (I) 150. The relative values of the forward conduction
voltage for a p-n junction diode, a Red LED
(c) Statement (I) is true but Statement (II) is and a Schottky barrier diode are
false
(IES (EC) - 2012)
(d) Statement (I) is false but Statement (II) is
true (a) Schottky voltage drop > p-n junction
diode drop > Red LED drop
56
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
57
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
58
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
59
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(b) Determine the output waveform for the (b) A series type ohmmeter uses a 100 basic
network shown and calculate the output movement with full scale deflection for
dc level and the required PIV of each
100 A . The battery voltage in the ohmmeter
diode.
circuit is 9V. The desired scale marking for
half scale deflection is 50 k . Find the values
of required resistor R1 in shunt with the meter
and the resistor R2 in series with the battery.
Also find the maximum values of R1 that will
compensate for a 10% drop in the battery
voltage and the percentage error at half scale
12. The input voltage Vi to the two-level clipper mark when R1 is so adjusted for the 10%
shown below varies linearly from 0 to 150 V. drop in battery voltage.
Sketch the output voltage to the same scale as
the input voltage. Assume ideal diodes. 14. A germanium diode has reverse saturation current
(IES (EC) - 1997) of 30 A at 125°C. What are its dynamic
forward and reverse resistances for a bias 0.2V
at this temperature ?
(IES (EC) - 1997)
60
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
from 20 mA to 30 mA, the voltage across it 22. A particular diode circuit produces the output
changes from 5.6 V to 5.65 V. What is the shown in Fig. when the input Vi = 5 sin ωt .
voltage across the Zener when the current is Design the circuit. Draw and explain the transfer
35 mA characteristic of the circuit. Neglect the diode
(IES (EC) - 1997) voltage drop. Assume the forward resistance
of diode to be 100 and the reverse resistance
to be 1M.
18. A silicon single phase full wave bridge rectifier (IES (EC) - 2012)
circuit is shown. Explain what happens if the
transformer and the load positions are
interchanged.
(IES (EC) - 1998)
ANSWER KEY
62
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
CHAPTER-3
TRANSISTOR
01. Each transistor in Darlington pair (see fig. (GATE (EC) - 1988)
below) has hFE = 100. The overall hFE of the (a) gm will not be affected
composite transistor neglecting the leakage
currents is (b) gm will decrease
(GATE (EC) - 1988) (c) gm will increase
(d) gm will increase (or) decrease depending
upon bias stability.
(a) 20 K (b) 16 K
(c) 5 K (d) 4 K
63
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
RE RE
(c) h FE (d) h FE
RB RB 08. Figure shows a common emitter amplifier. The
quiescent collector voltage of the circuit is
approximately
06. Which of the following statements are correct (GATE (EE) - 1991)
for basic transistor Amplifer configurations ?
(GATE (EC) - 1990)
(a) CB Amplifiers has low input impedance
and low current gain
(b) CC Amplifiers has low input impedance
and high current gain
(c) CE Amplifiers has very poor voltage gain
but very high input impedance 20
(a) V (b) 10 V
(d) The current gain of CB Amplifier is higher 3
than the current gain of CC Amplifiers
(c) 14 V (d) 20 V
64
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
10. In an RC-coupled Common Emitter amplifier, (d) Increases with the decrease in the base
which of the following is true ? width
(GATE (EE) - 1992) (IES (EE) - 2003)
(a) Coupling capacitance affects the hf 13. Match the following
response and bypass capacitance affects (GATE (EC) - 1994) (2M)
the If response
List - I
(b) Both coupling and bypass capacitances
affect the If response only A. The current gain of a BJT will be increased
if
(c) Both coupling and bypass capacitances
affect the hf response only B. The current gain of a BJT will be reduced
if
(d) Coupling capacitance affects the I f
response and the bypass capacitance C. The break-down voltage of a BJT will be
affects the hf response . reduced if
List - II
11. For the Amplifier circuit of fig. The transistor 1. The collector doping concentration is
has a β of 800. The mid band voltage gain increased
V0 / V1 of the circuit will be. 2. The base width reduced
(GATE (EC) - 1993) 3. The emitter doping concentration to base
doping concentration ratio is reduced
4. The base doping concentration is
increased keeping the ratio of the emitter
doping concentration to base doping
concentration constant
5. The collector doping concentration is
reduced
Codes :
A B C
(a) 0 (b) < 1 (a) 2 3 1
(c) 1 (d) 800 (b) 1 5 3
(c) 2 4 5
12. -cut off frequency of a bipolar junction (d) 4 2 1
transistor
(GATE (EC) - 1993) (2M)
14. In the transistor circuit as shown below the
(a) Increases with the increase in base width collector to ground voltage is +20 V. The
(b) Increases with the increase in emitter width possible condition is
(c) Increases with the increase in collector (GATE (EE) - 1994) (IES (EE) - 2003)
width
65
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
20. In a bipolar transistor at room temperature, if 4. has very high input impedance and very
the emitter current is doubled, the voltage across high current gain
its base-emitter junction 5. Provides high common mode voltage
(GATE (EC) - 1996) Rejection
(b) halves A B C
frequency f respectively are 27. In the BJT amplifier shown in the figure is the
transistor is biased in the forward active region
(GATE (EC) - 1996) putting a capacitor across RE will
(a) 200 MHz, 201 MHz (GATE (EC) - 1997)
(b) 200 MHz, 199 MHz
(c) 199 MHz, 200 MHz
(d) 201 MHz, 200 MHz
(a) 1 (b) hfe 28. The Emitter coupled pair of BJT’s gives a linear
transfer relation between the differential o/p
1 h R
fe e 1 h R
fe e voltage and the differential input voltage Vid only
(c) (d) 1 when the magnitude of Vid is less ‘ ’ times the
hie hie
thermal voltage, where ‘ ’ is
(GATE (EC) - 1998)
26. From measurement of the rise of the o/p pulse
(a) 4 (b) 3
of anAmplifier whose input is a smallAmplitude
square wave, one can estimate the following (c) 2 (d) 1
parameter of the Amplifier
(GATE (EC) - 1998) 29. In a series Regulated power supply circuit the
voltage gain AV of the “pass”, transistor satisfies
(a) gain-bandwidth product
the condition
(b) Slew Rate
(GATE (EC) - 1998)
(c) Upper-3-dB frequency
(a) Av (b) 1 Av
(d) lower 3-dB frequency
(c) Av 1 (d) Av 1
68
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
30. The fT of a BJT is related to its gm, C π and Cμ (b) obtaining a very high current gain
as follows (c) current feedback
(GATE (EC) - 1998) (d) temperature stabilized biasing
C π Cμ
(a) f T 33. In the cascode amplifier shown in the figure, if
gm
the common - emitter stage (Q1) has a
transconductance gm1, and the common base
2 C π C μ stage (Q2) has a transconductance gm2, then the
(b) f T overall transconductance g (= i0 / Vi) of the
gm
cascode amplifier is
gm (GATE (EC) - 1999)
(c) f T
C π Cμ
Q 2
i 0
gm Vo
(d) f T 2 C C
π μ
R L
32. One of the applications of current mirror is 35. The Early effect in a bipolar junction transistor
is caused by
(GATE (EE) - 1998)
(GATE (EC) - 1999)
(a) output current limiting
69
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
10 K RC
IC
5 K
(d) IC is less than or equal to β dc IB 43. An npn BJT has gm = 38 mAV, C 10 14 F,
C 1013 F, and DC current gain β 0 90.
41. The current gain of a BJT is For this transistor f T and f β are
(GATE (EC) - 2001) (GATE (EC) - 2001)
20
IZ IC
VZ
V0 = 10V
Vin 20 - 30V +
V BE -
RB
(a) Increase (b) Decrease
(c) Is unaffected (d) Drops to zero
71
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
R1 R2
(a) [3.3/3.3] mA
(b) [3.3/(3.3+.33)] mA
(c) [3.3/.33] mA
(d) [3.3/33+3.3] mA
73
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
1k 5V
I C
4 K 2.2 K
IB
+
V CE
-
1 K
(GATE (EC) - 2004) (IES (EE) - 2012) (d) both the base-emitter and base-collector
(a) normal acitve mode junctions are forward biased
20 V
V out
2k
430k VC
=100
+
10F
V in
~ 1 mA
40F
(d) the early removal of stored base charge The capacitance CC can be assumed to be
during saturation - to - cutoff switching infinite.
76
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
Q
In the figure above, the ground has been shown 100k
by the symbol
-12V
69. Under the DC conditions, the collector - to - (a) saturation region
emitter voltage drop is
(b) active region
(GATE (EC) - 2006)
(c) breakdown region
(a) 4.8 volts (b) 5.3 volts
(d) cut- off region
(c) 6.0 volts (d) 6.6 Volts
74. In a common emitter BJT amplifier, the 76. The three - terminal linear voltage regulator is
maximum usable supply voltage is limited by connected to a 10 load resistor as shown in
(GATE (EC) - 2007) the figure. If Vin is 10 V, What is the power
dissipated in the transistor?
(a) Avalanche breakdown of Base-Emitter
junction (GATE (EE) - 2007) (1M)
(b) Collector-Base breakdown voltage with
emitter open (BVCBO)
(c) Collector-Emitter breakdown voltage
1 k
with base open (BVCBO) V in
R L=10
(d) Zener breakdown voltage of the Emitter-
6.6 V
Base junction Zener diode
0
75. The common emitter- forward current gain of
(a) 0.6 W (b) 2.4 W
the transistor shown is β F 100
(c) 4.2 W (d) 5.4 W
(GATE (EE) - 2007) (1M)
20 K 3K
270 K
Cc2
1 K
CC1
IE
The transistor is operating in 10 K 2.3 K 3K
(a) Saturation region
CE
(b) Cut - off region
(c) Reverse active region
(d) Forward active region
77. The Value of DC current I E is
78
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
-10 V
79. Two perfectly matched silicon transistor are
connected as shown in the figure .Assuming the (a) 46% (b) 55%
β of the transistors to be very high and the (c) 63 % (d) 92%
forward voltage drop in diodes to be 0.7 V,
the value of current I is
81. A small signal source Vi(t) = A cos 20t + B sin
(GATE (EE) - 2008) (2M) 106 t is applied to a transistor amplifier as shown
+5V below. The transistor has β 150 and
1k
h ie 3kΩ .Which expression best approxi-
I
mates v0(t) ?
(GATE (EC) - 2009)
Q1 Q2
12 V
-5V
100 k 3K
(a) 0 mA (b) 3.6 mA
V (t)
0
100 nF
80. The input signal Vin shown in the figure is a 1kHz
square wave voltage that alternates between 20 k 900 k
+7 V and -7 V with a 50% duty cycle. Both 10 F
transistor have the same current gain, which is
large. The circuit delivers power to the load
resistor RL. What is the efficiency of the circuit
for the given input? choose the closet answer. (a) Vo t 1500 A cos 20t Bsin106 t
79
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
82. In the silicon BJT circuit shown below, assume R S 1, R B 93k, R C 250 ,
that the emitter area of transistor Q1 is half that
of transistor Q2. R L 1, C1 and C 2 4.7 F.
I +10V
R=9.3K 0
RB RC
Q1 Q2
( =700)
1 ( =715)
C2
C1
RS +
V0 RL
-10 V + -
VS ~
The value of current I0 is approximately -
+10V
10 K 50 K
V0
(a) 4.65 V (b) 5 V 89. For the BJT Q1 in the circuit shown below,
(c) 6.3 V (d) 7.23 V , VBEon = 0.7V, VCEsat = 0.7V. The
switch is initially closed. At time t = 0, the switch
is opened. The time t at which Q1 levels the
87. For a BJT, the common-base current gain active region is
= 0.98 and the collector base junction
(GATE (EC) - 2011)
reverse bias saturation current ICO = 0.6 μA .
This BJT is connected in the common emitter
mode and operated in the active region with a
base drive current IB = 20 μA . The collector
current IC for this mode of operation is
(GATE (EC) - 2011)
(a) 0.98 mA (b) 0.99 mA
(c) 1.0 mA (d) 1.01 mA
81
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
RC
92. The voltage gain Av of the circuit shown below
is
(GATE (EC) (EE) - 2012)
200 K
+
5V -
(a) 4286 (b) 4667 (a) large current gain and high input resistance
(b) large voltage gain and low output
(c) 5000 (d) 1000
resistance
(c) small voltage gain and low input resistance
95. For the circuit shown in figure given below, (d) small current gain and high output
assume β h FE 100. The transistor is in resistance
(IES (EE) - 2004)
98. The gain of a bipolar transistor drops at high
frequencies. This is because of the
3K (IES (EE) - 2005)
(a) Active region and VCE = 5V 99. Match List - I (Type of Amplifier /
(b) Saturation region Configuration) with List - II (Characteristic
Property) and select the correct answer using
(c) Active region and VCE = 1.42V the codes given below the lists:
(d) Cut - off - region (IES (EE) - 2006)
List - I
96. Two p-n junction diodes are connected back A. Common emitter amplifier
to back to make a transistor. Which one of the
following is correct? B. Emitter follower
(IES (EE) - 2005) C. Common base amplifier
(a) The current gain of such a transitor will D. Darlington pair
be high List - II
(b) The current gain of such a transistor will 1. Very low output resistance
be moderate
2. Current gain ~ 1
(c) It cannot be used as a transistor due to
3. Beta multiplication
large base width
4. Very high power gain
(d) It can be used only for pnp transistor
Codes:
97. For common emitter configuration which one A B C D
of the following statements is correct? (a) 4 1 2 3
(IES (EE) - 2005)
83
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
100. In the circuit given below, if the output is taken (a) α F = α R (b) α F < α R
from point E instead of node C, what will be
the result? (c) F R (d) F R
(IES (EE) - 2006)
+VCC
C
B RB=R 1||R2 RL
+ E V0
VS
-
RE
(a) An increase in the output impedance
(b) A reduction in the output impedance IE
(c) An increase in the input impedance
(d) A reduction in the input impedance The current stabilization factor for
RB
R B β R E is Si 1
101. Which of the following are true for h- RE
parameters of transistors?
For R B R E , what is the voltage stabilization
(IES (EE) - 2007)
factor S0 ?
(1) They are real numbers at audio frequencies
(IES (EE) - 2007)
(2) They are easy to measure
RE
(3) They vary widely with temperature (a) (b) R B
RB RE RE
Select the correct answer using the code given
below: 1
(c) (d) RE
(a) 1 and 2 only (b) 2 and 3 only
RE RB RE
(c) 1 and 3 only (d) 1, 2 and 3 only
84
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
106. An emitter in a bipolar junction transistor is (b) The early effect starts as soon as punch -
doped much more heavily than the base as it through occurs in a transistor
increases the (c) The small signal current gain h fe large
(IES (EE) - 2005)
signal current gain h FE when
(a) Emitter efficiency
n FE / IC 0
(b) Base transport factor
(d) In the CE mode, a transistor can be cut
(c) Forward current gain
off by reducing IB to zero
(d) All the three given above
85
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
+5 V
The power gain is due to
0
(IES (EE) - 2003)
(a) 1 and 2 (b) 2 and 3
(c) 1 and 3 (d) 1 and 4
(a) rise time (b) fall time
(c) storage time (d) delay time
114. An amplifier of gain A is bridged by a
capacitance C as shown below.
111. A circuit using the BJT is shown in the below
figure, the value of β is
C
+10 V
5 k
A
VB=1V
VE=1.7V
100 k
5 k
The effective input capacitance is
-10 V (IES (EE) - 2002)
(a) 120 (b) 150 (a) C/A (b) C(1-A)
(c) 165 (d) 166 (c) C(1+A) (d) CA
112. Early effect in BJT refers to 115. Consider a silicon transistor connected as a
(IES (EE) - 2002) common emitter amplifier as shown below. The
quiescent collector voltage of the circuit is
(a) avalanche breakdown
approximately
(b) thermal runaway
(IES (EE) - 1997, 2003)
(c) base narrowing
(d) zener breakdown
86
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
In a transistor
+20V
(IES (EE) - 2005)
10 K 10K (a) ICBO is greater than ICEO and does not
depend upon temperature
+
=100 -V0 (b) ICBO is greater than ICO and doubles for
Vi
every ten degrees rise in temperature
(c) ICBO is equal to ICO and doubles for every
5K ten degrees rise in temperature
(d) ICEO is equal to ICO and doubles for every
0V ten degrees rise in temperature.
+VCC
V01 V02
RC V1 V2
V0
Vi
I0=10 mA
RE
+
Vo
V C2
VC1 for V1 5V, V2 0 V is
-
(a) 0 V (b) 5 V
(a) RC / RE (b) R E / R C (c) 10 V (d) 15 V
(c) R C / R E (d) R E / R C
119. When a transistor is used in switching mode
then what is the turn-on time?
117. Which one of the following statements is (IES (EE) - 2009)
correct?
87
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(a) Sum of delay time and rise time and IC corresponding to the opearating point?
(b) Sum of rise time and storage time
V CC= + 10 V
(c) Sum of delay time and storage time
(d) Sum of rise time and fall time 27 V
200 K
122. In the below circuit as shown β 99, 124. Match List - I (Hybrid parameter) with
List - II (Units/definitions) and select the correct
VBE 0.6V, then what are the values of VC answer using the codes given below the lists:
88
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(IES (EE) - 2001) 127. For the circuit shown in the below figure,
List - I assuming β 100 for the transistor, the transistor
will be in
A. hie
(IES (EE) - 2001)
B. hfe
C. hre +10 V
D. hoe 20 K 8K
List - II
Output
1. Forward current transfer ratio
2. Ohms Input
3. Ohms
10 K 2K
4. Reverse voltage transfer ratio
Codes :
A B C D (a) Cut off region
(a) 2 1 3 4 (b) inverse active region
(b) 1 2 4 3 (c) active region
(c) 1 2 3 4 (d) saturation region
(d) 2 1 4 3
128. Figure shows a composite switch consisting of
a power transistor (BJT) in series with a diode.
125. An amplifier having an output resistance
Assuming that the transistor switch and the diode
of 4 gives an open circuit output voltage of are ideal, the I-V characteristic of the composite
6V(rms). The maximum power that it can switch is
deliver to a load is
(IES (EE) - 2001) + V -
(a) 1.5 W (b) 2.25 W
(c) 2.4 W (d) 9W
3. Large size
I
4. Very high conductivity
Codes :
V
(b) A B C D
(a) 1 4 2 3
(b) 4 1 2 3
(c) 4 1 3 2
I
(d) 1 4 3 2
V
130. In the circuit shown in the given figure, assume
(c) that the capacitor C is almost shorted for the
frequency range of interest of the input signal.
Under this condition, the voltage gain of the
amplifier will be approximately
Given hfe = 100, hie = 1k
I
(IES (EC) - 1996)
(d) V
137. The ‘h’ parameters of the circuit shown in the C. ree 3. 100
figure are : hib= 25 W, hfb= 0.999 and
hob= 10–6W. The voltage gain is D. Cbe 4. 100 pF
(a) 0.999 (b) 1.98 140. The model of a transistor in the common emitter
(c) 2.0 (d) 400 connection is shown in the following figure:
(IES (EC) - 1998)
138. In the case of the circuit shown in the figure,
the collector current IC will be
(IES (EC) - 1997)
92
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
2. Coupled diode
3. Low frequency 144. A junction transistor operating at room
temperature with Ic= 2mA where kt/q = 25 mV
4. High frequency
has β = 100. The values of the parameters gm
Codes : in mhos and r in ohms will be respectively
A B C D (IES (EE) - 1997)
(a) 4 3 1 2 (a) 0.04 and 2500 (b) 0.08 and 1250
(b) 3 4 2 1 (c) 0.5 and 800 (d) 0.08 and 5000
(c) 3 4 1 2
(d) 4 3 2 1 145. In the case of a BJT amplifier, bias stability is
achieved by
(IES (EE) - 1998)
142. If = 0.98, Ico = 6 μA and Iβ = 100 μA for a
transistor, then the value of Ic will be (a) keeping the base current constant
(IES (EE) - 1997) (b) changing the base current in order to keep
the Ic and VCB constant
(a) 2.3 mA (b) 3.1 mA
(c) keeping the temperature constant
(c) 4.6 mA (d) 5.2 mA
(d) keeping the temperature and the base
current constant
143. A difference amplifier is shown in the figure.
Transistor Q1 and Q2 have identical parameters.
146. The best approximation for Vc in the circuit
Assuming that VBE = 0.7 V and β = 200 for
shown in the figure will be (assume β to be high)
each transistor and given that Vs1 = Vs2 = 0,
the value of the collector current ic will be (IES (EE) - 1998)
(IES (EE) - 1997)
93
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
Codes
A B C D
(a) 1 2 3 4
(b) 1 3 2 4
(c) 1 4 2 3
(d) 2 3 4 1
Select the correct answer using the codes given (IES (EC) - 1998)
below : (a) storage time (b) turn-off time
(a) 3, 4, 1, 2 (b) 4, 3, 1, 2 (c) turn-on time (d) delay time
(c) 3, 4, 2, 1 (d) 4, 3, 2, 1
hie Rs hie Rs
(a) 1 hf 0 (b) hf 0
1 1
(c) Rs (d)
hoe hoe
(a) 4.55 V (b) 2.4 V
(c) 1 V (d) zero
152. For a transistor amplifier with self-biasing
network, the following components are used:
R1 = 4 k , R2 = 4 k and Rc = 1 k 156. Assume VBE = 0.7V and 50 for the
transistor in the circuit shown in the figure. For
The approximate value of the stability factor
VCE = 2V, the value of RB is
‘S’ will be
(IES (EE) - 1999)
(IES (EC) - 1998)
(a) 4 (b) 3
(c) 2 (d) 1.5
The circuit in the figure is the high frequency 159. Consider the following features regarding an
equivalent of a CE amplifier. If the upper cut- amplifier:
1 1. Voltage gain being less than one.
off frequency ωH where T = RC, then
T 2. High input impedance.
1. R = R s + rπ 3. High output impedance
4. High current gain
2. R = R s parallel rπ
Which of these are the characteristic features
3. C = C + r of an emitter follower amplifier ?
(IES (EE) - 2000)
4. C = C + C 1 g m R1
(a) 1, 2 and 3 (b) 1, 2 and 3
Which of these statements are correct ? (c) 1 and 3 (d) 2, 3 and 4
(IES (EE) - 1999)
1 1 1
(a) R R (b) R R
L C L C
1 1
(c) R (d) RC
L
97
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
167. Consider the following statements regarding the (a) 50 k (b) 0.98 k
bootstrap biasing arrangement for a BJT emitter
follower: (c) 50 M (d) 0.98 M
1. The input impedance is very high.
2. The voltage gain is exactly equal to one 170. CE configuration is the most preferred transistor
configuration when used as a switch because it
3. The output impedance is equal to zero
(IES (EC) - 2000, 2008)
Which of these statements is correct ?
(a) requires only one power supply
(a) None (b) 2 alone
(b) requires low voltage or current
(c) 3 alone (d) 1 alone
(c) is easily understood by every one
(d) has small ICEO
168. In the circuit shown in the given figure, the
approximate voltages at the transistor
(IES (EC) - 2000) 171. In a single-stage RC coupled common emitter
amplifier, the phase shift at the lower 3dB
frequency is
(IES (EC) - 2001)
(a) zero (b) 135°
(c) 180° (d) 225°
98
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
Codes:
(c)
A B C D
(a) 3 4 1 2
(d) (b) 4 3 1 2
(c) 3 4 2 1
(d) 4 3 2 1
173. In the circuit shown
(IES (EC) - 2002)
175. The biasing shown in the below circuit is
(IES (EC) - 2003)
100
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
184. What is the phase shift between the input and 187. When used for amplification, the output port
output voltage in a common-base small signal side of a BJT behaves as controlled current
amplifier (assuming ideal coupling and bypass source. According to the above, the variation
capacitors)? of which one of the following does not change
(IES (EC) - 2006) the output current of an ideal BJT ? (The BJT
(a) 180° (b) –180° is being used in a common emitter amplifier
circuit)
(c) 0° (d) None of above
(IES (EC) - 2006)
(a) Load resistance
185. Consider the following parameters of a hybrid-
(b) Collector to base bias voltage
π equivalent circuit of BJT :
1. Transconductance (gm) (c) Both load resistance and collector to base
bias voltage
2. hfe
(d) Base-emitter bias voltage
3. hie
Which of the above parameters vary with
temperature in similar manner (all of them 188. Consider the following statements in respect
of a CC amplifier:
101
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
191. Operating point shift can occur in an amplifier 194. Match List-I (Electronic Circuit) with List-II
due to which one of the following ? (Characteristic) and select the correct answer
using the codes given below the lists:
(IES (EC) - 2007)
102
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(IES (EC) - 2007) 196. For BJT, early voltage VA is 100V. In common
List-I emitter configuration, quiescent VCE is 10V.
What percentage change in quiescent IC would
A. CE occur, if early voltage VA is made ?
B. CB (IES (EC) - 2008)
C. CC (a) 10% (b) 20%
D. Darlington Pair (c) 5% (d) 0%
List-II
1. The circuit introduces a phase inversion 197. The maximum power dissipation capacity of a
of 180° transistor is 50 mW. If the collector emitter
2. The circuit is rarely used voltage is 10V. What is the safe collector
current that can be allowed through the
3. The name, emitter follower is also used transistor ?
for the circuit
(IES (EC) - 2009)
4. The circuit consists of two circuits
connected in cascade (a) 5 mA (b) 2.5 mA
Codes: (c) 10 mA (d) 25 mA
A B C D
(a) 1 2 3 4 198. Why npn-transistors are preferred over pnp-
transistors ?
(b) 2 1 3 4
(IES (EC) - 2009)
(c) 2 1 4 3
(a) Leakage current in npn-transistors is less
(d) 1 2 4 3 than pnp-transistors
(b) Mobility of majority carriers in npn-
195. Consider the following statements: transistors is greater than the mobility of
Bias stabilization in a BJT circuit is very majority carriers in pnp-transistors
important, because it (c) Bias voltage required in npn is less than in
1. provides high voltage and current gain pnp-transistors
2. ensures large bandwidth of the amplifier (d) Bias voltage required in npn is greater than
in pnp-transistors
3. keeps the operating point unchanged with
change of temperature.
Which of the above statement(s) is/are correct? 199. Consider the following statements:
103
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
200. Consider the following statements: 203. Which of the following describe the correct
The bias stability of an emitter-bias amplifier properties of an emitter follower circuit ?
circuit improves by 1. It is a voltage series feedback circuit
1. decreasing the value of RB. 2. It is a current series feedback circuit
2. increasing the value of RE. 3. Its voltage gain is less than unity.
3. decreasing the value of RE. 4. Its output impedance is very low.
4. increasing the value of RB. Select the correct answer from the codes given
5. Increasing the value of RC. below :
(c) 3 and 4 (d) 4 and 5 (c) 2 and 3 only (d) 2 and 4 only
201. Which of the following will be true for a CE 204. Which of the following conditions must be
transistor amplifier if the emitter resistor value satisfied for a transistor to remain under
is made equal to zero ? saturation ?
104
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
205. For the transistor circuit shown in the figure, hi = 2 k (hre = hoe = 0), the voltage
e
when amplification of the amplifier is nearly equal to
(IES (EC) - 2011)
(a) 500 (b) 200
(c) 100 (d) 50
105
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
211. For common collector amplifier, the current gain 215. A CE amplifier has a resistor RF connected
(AI) is between collector and base RF = 40 k . RC
(IES (EC) - 2012) = 4 k . Given hfe = 50, rπ 1k the output
1 h fe resistance is
(a) 1 h fe (b) 1 h R (IES (EC) - 2012)
oe L
(a) 40 k (b) 20 k
1 h fe 1 h fe
(c) h oe h ie (d) 1+h R (c) 4 k (d) 0.66 k
ie L
212. For a transistor used as a switch, td is delay 216. If ICEO = 410 μ A, ICBO = 5 μ A and IB = 30 μ A,
time, tr is rise time, ts is storage time and tf is fall then the collector current is
time. Then turn-on time tON and turn-off time (IES (EC) - 2013)
tOFF are respectively
(a) 415 μ A (b) 440 μ A
(IES (EC) - 2012)
(c) 445 μ A (d) 2.64 μ A
(a) (td + ts) and (tr + tf)
(b) (td + tf) and (ts + tr)
217. The transistor as shown in the circuit is operating
(c) (tr + ts) and (td + tf)
in
(d) (td + tr) and (ts + tf)
(IES (EC) - 2013)
218. The transconductance gm of the transistor used 221. The common emitter current gain-bandwidth
in the CE amplifier shown in the below circuit, product of a transistor (fT) is defined as the
operating at room temperature is frequency at which
(IES (EC) - 2013) (IES (EC) - 2003)
(a) Alpha of the transistor falls by 3 dB
(b) Beta of the transistor falls by 3 dB
(c) Beta of the transistor falls to unity
(d) Power gain of the transistor falls to unity
PC 1 PC 1
(a) (b) T 229. A Bipolar Junction Transistor (BJT) works in
Tj A three regions:
1. Saturation
PC 1 PC 1
(c) T (d) T 2. Active
j A
3. Cut-off
If BJT is to be used in amplifier circuit, the
226. In a transistor biased in the active region, region it works in is/are
thermal runaway is due to
(IES (EE) - 2012)
(IES (EE) - 2006) (IES (EC) - 2012) (a) 1, 2 and 3 (b) 1 and 2 only
(a) Base emitter voltage V BE which (c) 2 only (d) 1 only
decreases with rise in temperature
(b) Change in reverse collector saturation
230. For a transistor, turn-off time is:
current due to rise in temperature.
(IES (EE) - 2011)
(c) Heating of the transistor
(a) Sum of storage time, and fall time
(d) Changes in β which increases with
temperature. (b) Maximum value of storage time
(c) Maximum value of fall time
227. An emitter follower regulator has the following (d) Sum of rise time and fall time
disadvantage
(IES (EE) - 2011)
231. In a common collector amplifier the voltage gain
(a) It does not provide high gain is :
(b) No provision exists for varying the output (IES (EE) - 2011)
voltage
(a) Constant
(c) Its output resistance is high
(b) Less than 1
(d) It cannot withstand high load current
(c) Varies with input voltage
(d) Varies with load impedance
228. Early effect is the modulation of effective base
width by
108
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
109
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
Conventional Problems 03. If the transistor in fig. has high value of and
01. In figure all transistors are identical and have a VBE of 0.65 the current I flowing through the 2
high value of beta. The voltage VDC is equal to kilo ohms resistance will be ____
___ (GATE (EC) - 1992)
(GATE (EC) - 1991)
110
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
111
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(a) WC = 20 m and
Collector doping = 5 × 1018/cm³
KT
q = 1.6 × 10–19 coloumbs; = 25 mV
q
For silicon at T = 300 K, Dn = 30 cm²/sec;
KS 0 = 10–12 F/em; ni = 1.5 × 1010/cm³]
113
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
20. An emitter-follower amplifier is shown in the 22. (a) Determine VCE and IE for the following
figure, Zi is the impedance looking into the base network
of the transistor and Z0 is the impedance looking
(IES (EC) - 1996)
into the emitter of the transistor
(GATE (EC) - 2001)
114
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
115
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
33..
116
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
117
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
ANSWER KEY
01. c 40. d 79. c 118. c 157. a 195. c
02. d 41. d 80. d 119. a 158. a 196. d
03. c 42. c 81. d 120. b 159. a 197. a
04. a 43. b 82. b 121. b 160. c 198. b
05. b 44. b 83. b 122. a 161. a 199. c
06. ab 45. c 84. b 123. b 162. c 200. a
07. c 46. a 85. b 124. d 163. a 201. d
08. b,d 47. b 86. a 125. b 164. c 202. d
09. b 48. b 87. d 126. b 165. a 203. a
10. d 49. c 88. a 127. b 166. a 204. d
11. c 50. a 89. c 128. c 167. d 205. c
12. d 51. a 90. d 129. c 168. a 206. c
13. a 52. a 91. c 130. d 169. b 207. a
14. b 53. b 92. d 131. d 170. b 208. a
15. c 54. d 93. c 132. a 171. d 209. a
16. d 55. a 94. b 133. b 172. d 210. a
17. a 56. b 95. b 134. a 173. c 211. b
18. a 57. c 96. c 135. b 174. d 212. d
19. c 58. c 97. a 136. a 175. d 213. d
20. c 59. d 98. c 137. d 176. b 214. c
21. a 60. a 99. a 138. a 177. a 215. c
22. a 61. c 100. b 139. b 178. a 216. d
23. c 62. d 101. d 140. a 179. b 217. d
24. d 63. c 102. d 141. b 180. b 218. a
25. d 64. c 103. c 142. d 181. c 219. a
26. c 65. b 104. c 143. b 182. b 220. b
27. b 66. b 105. c 144. b 183. d 221. c
28. d 67. b 106. d 145. b 184. c 222. a
29. c 68. b 107. b 146. d 185. d 223. b
30. d 69. c 108. c 147. c 186. d 224. b
31. a 70. b 109. a 148. d 187. c 225. c
32. d 71. b 110. b 149. c 188. d 226. c
33. a 72. b 111. c 150. d 189. b 227. b
34. a 73. b 112. c 151. a 190. b 228. c
35. c 74. c 113. c 152. b 191. d 229. c
36. d 75. d 114. b 153. a 192. a 230. a
37. c 76. b 115. c 154. b 193. b 231. b
38. a 77. a 116. c 155. b 194. a 232. d
39. b 78. d 117. c 156. c
118
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
CHAPTER-4
JFET
01. The pinch off voltage for a n-channel JFET is 05. The JFET in the below, circuit has an
4 V, when VGS = 1 V, the pinch off occurs for IDSS=10mA, Vp= 5V. The value of the resistance
VDS equal to: RS for a drain current of IDS= 6.4 mA is
(GATE (EC) - 1987) (2M) (GATE (EC) - 1992) (IES (EE) - 2010)
(a) 3 V (b) 5 V
(c) 4 V (d) 1 V
IDS
+
02. In an n-channel JFET, VGS is held constant. VDS 10V
-
is less than the breakdown voltage. As VDS is
increased
(GATE (EC) - 1988) (2M) RS
(a) Conducting cross sectional area of the
channel ‘S’ and the channel current
density ‘J’ both increase
(a) 1.06 k (b) 560
(b) ‘S’ decrease and ‘J’ decrease
(c) ‘S’ decreases and ‘J’ increase (c) 470 (d) 156
07. In a JFET
04. An n-channel JFET has a pinch off voltage
VP= –5 V, VDS(max) = 20 V, and gm = 2mA/V, (GATE (EC) - 1995) (2M)
the min ‘ON’ resistance is achieved in the JFET List - I
for _____
A. The pinch off voltage decreases
(GATE (EC) - 1992) (2M)
B. The drain conductance increases
(a) VGS = – 7V and VDS = 0 V
C. The transit time of the carriers in the
(b) VGS = 0 V and VDS = 0 V channel is reduced
(c) VGS = 0 V and VDS = 20 V List - II
(d) VGS = – 7V and VDS = 20 V 1. The channel doping is reduced
119
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
+
C1 Vo
08. Two identical FET, each having parmeters gm
and rd are connected in parallel. The composite + G
FET is characterized by the parameters
(GATE (EC) - 1998) RG
Vi (1M)
RS
gm gm r Cs
(a) and 2rd (b) and d (2.5K)
2 2 2
-
rd
(c) 2g m and (d) 2gm and 2 rd
2
2k
16. The cross section of a JFET is shown in the
D following figure. Let VG be -2V and let Vp be
the intial pinch -off voltage. If the width W is
G doubled (with other goemetrical parameters
S
and doping levels remaining the same), then the
2M ratio between the mutual transconductances of
Vi V0
the intial and the modified JFET is
-
2V (GATE (EC) - 2008)
+
Zi Z0
Gate VG
P+
13. Zi and Z0 of the circuit are respectively
Source n W Drain
(GATE (EC) - 2005)
(a) 2 M P+
Gate VG
20
(b) 2 M and k
(a) 4
11
(c) Infinity and 2M
1 1 2 / Vp
(b)
20 2 1 1/ 2V
(d) infinity and k p
11
1 2 / Vp
14. ID and VDS under DC condition are respectively (c)
1 1 / 2Vp
(GATE (EC) - 2005)
(a) 5.625 mA and 8.75 V
(b) 7.500 mA and 5.00 V
1 2 / Vp
(d)
1 1/ 2 V
p
(c) 4.500 mA and 11.00 V
(d) 6.250 mA and 7.50 V
Common Data Question 17 and 18
15. Transconductance in milli-siemens (mS) and The channel resistance of an N-channel JFET
voltage gain of the amplifier are respectively shown in the fig. below is 600 when the full
(GATE (EC) - 2005)
121
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(GATE (EC) - 2011) (2M) 21. Match List-I (Device) with List-II (Property/
17. The channel resistance when VGS = 0V is item associated with it) and select the correct
answer
(a) 480 (b) 600
(IES (EC) - 1996)
(c) 750 (d) 1000
List-I
A. BJT
18. The channel resistance when VGS = – 3V is B. FET
(a) 360 (b) 917 C. SCR
(c) 1000 (d) 3000 D. Tunnel diode
List-II
122
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
S
26. Consider following statements:
(a) Common drain
1. BJT is a current controlled device with
(b) Common gate high input impedance and high gain
(c) Common Source bandwidth
123
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
27. The zero gate bias channel resistance of a 30. An FET is a better chopper than a BJT because
junction field effect transistor is 750 ohms and it has
the pinch-off voltage is 3V. For a gate bias of (IES (EC) - 2000)
1.5V and very low drains voltage, device would
behave as a resistance of (a) lower offset voltage
(IES (EC) - 1998) (b) higher series ON resistance
(a) 320 ohms (b) 816 ohms (c) lower input current
(c) 1000 ohms (d) 1270 ohms (d) higher input impedance
28. An FET source follower circuit has gm of 31. The voltage gain of a given common source
2m mho and rd of 50 k . If the source JFET amplifier depends on its
124
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
34. The drain gate capacitance of a junction FET 38. Compared to the bipolar junction transistor, a
is 2 pF. Assuming a common source voltage JFET:
gain of 20. What is the input capacitance due
to Miller effect ? 1. Has a larger gain bandwidth product
125
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
41. Consider the following statements related to (a) 650 (b) 750
JFET :
(c) 775 (d) 800
1. Its operation depends on the flow of
minority carriers only
2. It is less noisy than BJT
3. It has poor thermal stability
4. It is relatively immune to rediation.
The correct statements are
(IES (EC) - 2012)
(a) 1, 2, 3 and 4 (b) 1 and 2 only
(c) 2 and 4 only (d) 3 and 4 only
126
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
CONVENTIONAL PROBLEMS
01. (a) Specify the type of the negative feedback
in the JFET amplifier shown in Fig.
V0
(b) Calculate the voltage gain , of the
V1
amplifier with no feedback (Rf = ).
(c) Determine the value of the resistance Rf,
(a) Determine ID, VDS and VGS Cgd = 2 pF, and Cds = 2pF. Determine the ac
(b) Check to confirm that the device is indeed small-signal midband voltage gain (V0/Vs) and
operating in saturation the upper - 3 dB frequency of the circuit.
ANSWER KEY
01. a 16. b 31. b
14. a 29. a
15. b 30. a
129
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
CHAPTER-5
MOSFET
01. In MOSFET devices the n-channel type is 04. Which of the following effects can be caused
better than the P-channel type in the following by a rise in the temprature ?
respects (GATE (EC) - 1990) (2M)
(GATE (EC) - 1988) (2M) (a) increase in MOSFET current (IDS)
(a) it has better immunity (b) increase in BJT current (IC)
(b) it is faster (c) decrease in MOSFET current (IDS)
(c) it is TTL compatible (d) Decrease in BJT current (IC)
(d) it has better drive capability
07. For a MOS capacitor fabricated on a p-type (a) current controlled capacitor
semiconductor, strong inversion occurs when (b) voltage controlled capacitor
(GATE (EC) - 1997) (c) Current controlled inductor
(a) surface potential is equal to Fermi (d) Voltage controlled inductor
potential
(b) surface potential is zero
11. The effective channel length of a MOSFET in
(c) surface potential is negative and equal to saturation decreases with increase in
Fermi potential in magnitude.
(GATE (EC) - 2001)
(d) surface potential is positive and equal to
twice the Fermi potential (a) gate voltage (b) drain voltage
(c) source voltage (d) body voltage
08. In the MOSFET amplifier of the figure, the
signal output V1 and V2 obey the Relationship 12. Consider the following statements in connection
(GATE (EC) - 1998) with the CMOS inverter in the figure, where
both the MOSFETs are of enhancement type
and both have a threshold voltage of 2V.
Statement 1: T1 conducts when Vi 2V.
Statement 2: T1 is always in saturation when
Vo 0V
+5V
T2
V V
(a) V1 2 (b) V1 2
2 2
Vi Vo
131
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
ID
0 Vir
0 VGS
132
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
1V VGS
21. The value of R for which the PMOS transistor
in figure will be biased in linear region is
(GATE (EE) - 2004) (2M)
133
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
VDD=25V
V=3V
G
G
R=10k
Vbd
S
V=1V
S
3V
1k 1k 3
2V
2
1V
1
10 V D
2k Vab
G
S
0
2V (V)
134
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
28. In the CMOS inverter circuit shown, if the (GATE (EC) - 2007)
transconductance parameters of the NMOS Group - I
and PMOS transistors are P. BJT
Wn
k n = k p = μ n C OX = μ p COX , Q. MOS capacitor
Ln
R. LASER diode
Wp S. JFET
=40μA/V 2 and their threshold voltages are
Lp
Group - II
VTHn VTHp 1V, the current I is 1. Population inversion
136
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
2
ID K VGS VT
(c) (d)
VGS VDS VGS
gm
VDD
Ibias RE
gm
Vout (b)
Va Ix
VG
M1 M2
Is
gm
The current Ix is related to Ibias as
(c)
(GATE (EC) - 2008)
(a) Ix Ibias Is VG
(b) I x Ibias
gm
(c) Ix Ibias Is
V
(d) I x I bias VDD out
RE (d)
137
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
37. Consider the following two statements about 38. For small increase in VG beyond 1V, which of
the internal conditions in an n-channel the following gives the correct description of
MOSFET operating in the active region the region of operation of each MOSFET?
S1: The inversion charge decreases from (GATE (EC) - 2009)
source to drain (a) Both the MOSFETs are in saturation
S2: The channel potential increases from region
source to drain (b) Both the MOSFETs are in triode region
Which of the following is correct? (c) n-MOSFET is in triode and p-MOSFET
(GATE (EC) - 2009) is in saturation region
(a) Only S2 is true (d) n-MOSFET is in saturation and p-
MOSFET is in triode region
(b) Both S1 and S2 are false
(c) Both S1 and S2 are true, but S2 is not a
reason for S1 39. Estimate the output voltage V0 for VG = 1.5V.
[Hints: use the appropriate current- voltage
(d) Both S1 and S2 are true, and S2 is a
equation for each MOSFET, based on the
reason for S1
answer to Q.no. 8]
(GATE (EC) - 2009)
Linked Answer Questions 38 and 39
1 1
Consider the CMOS circuit shown, where the (a) 4 V (b) 4 V
gate voltage VG of the n-MOSFET is increased 2 2
from Zero, while the gate voltage of the
p-MOSFET is kept constant at 3V. Assume that, 3 3
for both transistors, the magnitude of the (c) 4 V (d) 4 V
2 2
threshold voltage is 1V and the product of the
transconductance parameter and the (W/L)
ratio,i.e. the quantity μCox W / L , is1mA.V-2 40. This gate oxide in a CMOS process is
preferably grown using
5V (GATE (EC) - 2010)
(a) Wet oxidation
(b) dry oxidation
(c) epitaxial deposition
3V
(d) ion implantation
VC
138
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
140
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
53. What is the main difference between 56. Which one of the following is not a characteristic
MOSFETs and BJTs in terms of their I-V of CMOS configuration?
charcteristics? (a) CMOS devices dissipate much lower
(IES (EE) - 2006) static power than bipolar devices
(a) Current is quadratic with VGS for (b) CMOS devices have low input
MOSFETs and linear with VBE for BJTs impedances
(b) Current is linear with VGS for MOSFETs (c) CMOS devices have higher noise margins
and exponential with VBE for BJTs (d) CMOS devices have much lower trans-
(c) Current exponential with VGS/VBE in both conductance than bipolar devices
these devices, but rise is faster in
MOSFETs
57. Consider the following statements :
141
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(IES (EC) - 2006) (a) Are easy to parallel for higher current
(a) 3000 (b) 1000/3 (b) Leakage current is relatively high
144
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
C.
D.
List - II
1. N- Channel FET
2. Varactor
3. Tunnel Code
4. P channel MOSFET
Codes:
A B C D
(a) 3 2 1 4
(b) 1 4 3 2
(c) 3 4 1 2
(d) 1 2 3 4
145
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
CONVENTIONAL PROBLEMS
01. In Fig. the n-channel MOSFETs are identical
and their current voltage characteristics are
given to the following expressions :
V2
For VDS ID VGS 1 VDS DS mA
2
For VDS (VGS–1), (VGS – 1) = (VGS – 1)2 03. In the MOSFET amplifier shown in the fig.
mA below, the transistor has μ = 50, rd = 10K.
Where VGS and VDS are the gate-source and Cgs = 5 pF, Cgd = 1pF and Cds = 2 pF. Draw a
drain-source voltages respectively and I0 is the small signal equivalent circuit for the amplifier
drain current. for midband frequencies and calculate its
The current IDC flowing through the transistor midband voltage gain.
‘M’ is equal to ____ (GATE (EC) - 1994)
(GATE (EC) - 1991)
146
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
148
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
ANSWER KEY
149
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
CHAPTER-6
OPERATIONAL AMPLIFIER
01. The OP-AMP shown in Fig. below is ideal. 03. The CMRR of the differential Amplifier of the
fig is equal to
R L/C . The phase angle between V0 and
Vi, at 1 / LC is (GATE (EC) - 1990)
(a) (b) 0
(c) 900 (d) 1800
(a) / 2 (b)
(c) 3 / 2 (d) 2
04. If the input to the circuit of figure is a sine wave,
the output will be
02. Refer to Fig. (GATE (EC) - 1990)
(GATE (EC) - 1989)
150
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
06. An Op-Amp has an offset voltage of 1mV and (b) the input impedance of the OPAMP is
is ideal in all other respects. If this Op-Amp is infinity
used in the circuit shown in fig. The O/P voltage (c) the open loop gain of the OPAMP is infinity
will be (Select the nearest value). (d) CMRR is infinity
(GATE (EC) - 1992)
12. The output voltage Vo of the circuit shown in 14. From a measurement of the rise time of the
the figure is output pulse of an amplifier whose input is a
small amplitude square wave, one can estimate
(GATE (EC) - 1997) the following parameter of the amplifier:
(GATE (EC) - 1998)
(a) gain-bandwidth product
(b) slew rate
(c) upper 3-dB frequency
(d) lower 3-dB frequency
17. Match the following 18. The first dominant pole encountered in the
(GATE (EE) - 1998) frequency response of a compensated op-amp
is approximately at
List-I
(GATE (EE) - 1999)
(a) 5 Hz (b) 10 kHz
(c) 1 MHz (d) 100 MHz
(A)
19. In the differential amplifier of the figure, If the
source resistance of the current source IEE is
infinite, then the common-mode gain is
(GATE (EC) - 2000)
VC C
(B)
R R
V in1 Vin 2
(C)
IE E
-VE E
153
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
R1 R2 R
C
Vi -
- V0
V0 +
+
R
C
(a) Square wave (b) Triangular wave
R C
(c) Parabolic wave (d) Sine wave
(a) Precision integrator 23. If the Op-amp in the figure has an input offset
(b) Hartley oscillator voltage of 5 mV and an open-loop voltage gain
of 10,000 then V0 will be
(c) Butter worth high pass filter
(GATE (EC) - 2000)
(d) Wien-bridge oscillator
+ 15 V
21. If the Op-amp in the figure, is ideal then V0 is +
(GATE (EC) - 2000) V0
-
C
- 15 V
C
Sin t
V1 -
V0
V2 + (a) 0 V
Sin t
C (b) 5 mV
(c) +15 V or -15 V
(a) Zero
(d) +50 V or -50 V
(b) V1 V2 sin t
24. In the circuit of the figure, V0 is
(c) V1 V2 sin t
(GATE (EC) - 2000)
(d) V1 V2 sin t
+ 15 V
+
22. Assume that the Op-amp of the figure is ideal. V0
If Vi is a triangular wave then V0 will be +1 V -
R
(GATE (EC) - 2000) - 15 V
R
154
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(a) R i , A , R 0 0
(b) R i 0, A , R 0 0
(c) R i , A , R 0
(d) R i 0, A , R 0
8 20
(a) V (b) V
32. For the oscillator circuit shown in Figure, the 7 7
expression for the time period of oscillation can (c) – 10 V (d) None of these
be given by (where = RC)
(GATE (EE) - 2001)
Statements for Linked Questions 35 and
36
For the circuit shown in figure
(a) 1n 3 (b) 2 1n 3
(c) 1n 2 (d) 2 1n 2
156
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
35. The circuit shown is a 39. A amplifier using an op-amp with a slew-rate
(GATE (EE) - 2001) (2M) SR=1 V / μ sec has a gain of 40dB. If this
amplifier has to faithfully amplify sinusoidal
(a) Low pass filter
signals from dc to 20 KHz without introducing
(b) Band pass filter any slew-rate induced distortion then the input
(c) Band Reject filter signal level must not exceed.
(d) High pass filter (GATE (EC) - 2002)
(a) 795 mV (b) 395 mV
36. If the above filter has a 3 dB frequency of (c) 79.5 mV (d) 39.5 mV
1 kHz, a high frequency input resistance of
100 k and a high frequency gain of 40. The output voltage (v0) of the Schmitt trigger
magnitude 10. Then value of R1 , R2 and C shown in Figure swings between +15 V and
respectively are – –15 V. Assume that the operational amplifier is
(GATE (EE) - 2001) (2M) ideal. The output will change from + 15 V to
–15 V when the instantaneous value of the input
(a) 100 k , 100 k 0.159 nF sine wave is
(b) 10 k , 100 k 0.111 F (GATE (EE) - 2002)
1
(c) (d) None of these
4RC
+
Vy 1 K
41. The transfer function of the first network is
Vx
+
15 V DC VZ = 3 V
(GATE (EE) - 2002) (2M) -
Unregulated
Power source
j RC
(a) 40 K
1 R C 2 j3CR
2 2
20 K Regulated
DC Ouput
jCR -
(b) 1 R C 2 j 2CR
2 2
(a) 3 V (b) 6 V
1 K
-
1 K
Vout V in +
3V + V0ut
1 K -
8 K
V re f=2V -
+
R2
R2
RL
(a) 0° (b) –90° iL
(c) +90° (d) + 180°
Vs Vs
52. The circuit in the figure is a (a) R (b) R2
2
(GATE (EC) - 2004)
Vs Vs
(c) R (d) R1
L
-
V ou t
R R +
V in
55. The input resistance R IN Vx / i x of the
circuit in figure is
(a) low-pass filter (b) high-pass filter (GATE (EE) - 2004) (2M)
(c) band-pass filter (d) band-reject filter
160
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
R1=10k R 1=100k 1M
- eo
- +
Vy
+ 1M
10 K
-
Vi +
F
1K
161
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
0.5 k
-5 V
2 k
30 K
-8 V -5 V
(a) Vi
10 K
-
-10 V
+
Ideal operational amplifier
Ri
V0
+10 V
30
(a) k (b) 10k
4
-5 V +8 V (c) 40k (d) infinite
(b) Vi
-5 V +5 V Vi
(c)
-10 V V1 V2
RE
-V E E
162
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
V in
(d) t
l
t
l
RF
V out
R1
V in +
(a) V0ut
-
t
l
V ou t
163
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
164
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
6
(b) (a) -10
(c) 12 V -10
-0.7V
(b)
6
-0.7V
(d) 6
12 V
(c)
-10
C
-
+
69. In the OP-Amp circuit shown, assume that
2k
the diode current follows the equation
P I=ISexp(V/VT). For Vi 2V, V0 V01, for
10k
10 k
Vi 4V, V0 V02 . The relationship between
V01 and V02 is
165
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
1 sRC 1 sRC
Vi - (a) (b)
2 k 1 sRC 1 sRC
V0
+
1 1
(c) (d)
1 sRC 1 sRC
(c) V02 V01In2 (d) V01 V02 VT In2 72. If Vi V1 sin t and V0 V2 sin t ,
then the minimum and maximum values of
(in radians) are respectively
70. For the Op-amp circuit shown in the figure, V0
is (GATE (EC) - 2007)
(GATE (EC) - 2007) (a) π / 2 and π / 2 (b) 0 and π / 2
1k
- 73. IC 555 in the adjacent figure is configured as
1V V0
+ an astable multivibrator. It is enabled to oscillate
1k at t = 0 by applying a high input to pin 4. The
1k pin description is : 1 and 8 - supply; 2 - trigger;
4-reset ; 6-threshold, 7-discharge. The
waveform appearing across the capacitor
(a) -2V (b) -1 V starting from t = 0, as observed on a storage
CRO is
(c) -0.5 V (d) 0.5 V
(GATE (EE) - 2007) (2M)
166
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
+10 V
+10 V
1 K
-
(a) Vout
+ 5.0 V
0.01
-10 V +10 K
F
S 100 K
5.0 V
R1
(d)
+
-
V R2
+
LOAD
74. The switch S in the circuit of the figure is initially
closed, it is opened at time t = 0, you may F
neglect the Zener diode forward voltage drops.
What is the behaviour of Vout for t > 0?
(GATE (EE) - 2007) (2M) rV
(a) a voltage source with voltage R || R
1 2
r || R 2
(b) a voltage source with voltage .V
R1
167
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
Vi ) -
V0
For an input voltage Vi 1V , the output
+
voltageV0 is
10 K (GATE (EC) - 2008)
)
(a) 0 V (b) 0.1V
(c) 0.7 V (d) 1.1 V
10 K
-15 V
78. The OPAMP circuit shown represents a
A triangular wave which goes from -12 V to (GATE (EC) - 2008)
12 V is applied to the inverting input of the
OPAMP. Assume that the output of the C
OPAMP swings from +15 V to -15 V. The
voltage at the non-inverting input switches
between R2
(GATE (EC) - 2008)
Vi -
(a) – 12 V and + 12 V R1
L V0
+
(b) – 7.5 V and + 7.5 V
(c) – 5 V and + 5 V
(d) 0 V and 5 V
(a) high pass filter (b) low pass filter
(c) band pass filter (d) band reject filter
77. Consider the following circuit using an ideal
OPAMP. The I-V characteristics of the diode
79. An astable multivibrator circuit using IC 555
VV
is described by the relation I I0 e T 1 timer is shown below. Assume that the circuit
is oscillating steadly.
168
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
30 K 5
4 8 2.5
(Reset) (Su pply) (a)
0
6(Threshold )
(Outpu t)3
0
10 K
2.5
2(Tri gger) (Gnd) (b)
(Discharg e) 1 5
7
12 K 5V
VC .01 F
0 t(sec)
(c)
l
-5V
5V
The voltage VC across the capacitor varies
between 0 t(sec)
(d)
l
(a) 3V to 5V (b) 3V to 6V
(c) 3.6 V to 6V (d) 3.6V to 5V
Statement for Linked Questions 81 and 82
A general filter circuit is shown in the figure:
80. A wavetorm generator circuit using OPAMPs
is shown in the figure. It produces a triangular R2
wave at point ’P’ with a peak to peak voltage
of 5 V for Vi = 0 V
Vi R1 C
(GATE (EE) - 2008) -
+ V0
C R3 VA
R
- - ‘P’
R4
+ +
R1
V1
169
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
RA /2
83. The block diagrams of two of half wave rectifier
are shown in the figure. The transfer
characteristics of the rectifiers are also shown.
C
V in V0 P
V0
Vin Vo
0
V0
Vo Vo
0
Vi n
Gain
R
Gain
(b) R
Vi n
P -
V0
(a) R +
Q
Gain R
(c)
Vin R
P -
V0
(b) R +
Q
R
170
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
R
5 k
R R +
V
-
- 1.4 k
Vin R V0 5V
P +
(d) R
Q
(a) Positive feedback, V = 10 V
(b) Positive feedback, V=0V
84. In the following asatble multivibrator circuit, (c) Negative feeback , V=5V
which properties of V0(t) depend on R2 ? (d) Negative feedback, V=2V
(GATE (EC) - 2009)
R2 R4
Vs=10Vrms,50Hz
IS +
Opamp
~ -
10 k
R
(b) C
10F
(c)
88. The nature of feedback in the opamp circuit
shown is
(GATE (EE) - 2009) (1M)
1 K +6v
- 2 K
V0
+
Vi n -6 v
(d)
(a) Current - Current feedback
(b) Voltage - Voltage feedback
172
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(a)
89. Assuming the OP-AMP to be ideal, the voltage
Vl
gain of the amplifier shown below is -10 -5 0
R1
-
V0
(b) 5
+
+
Vi - R2 -10 -5 0
Vl
V0
R3
(c) 5
R2 R3 0 +5
Vl
(a) (b) R
R1 1
V0
R || R 3 R2 R3
(c) 2 (d) R
R1 1 10
(d)
Vl
0 +5
90. The transfer characteristic for the precision
rectifier circuit shown below is (assume ideal
OP-AMP and practical diodes)
91. Given that the OP-AMP is ideal, the output
(GATE (EC) - 2010)
voltage V0 is
2R
R
4R
D2
VI - R + 10 v
R -
V0
+ D1 V0
+
+2 V - 10 v
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ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(a) 4 V (b) 6 V
(c) 7.5 V (d) 12.12 V
(c)
(d)
1 (a) 4 (b) 6
(b) High pass filter with f 3dB = rad/s
R1 C (c) 8 (d) 10
1
(c) Low pass filter with f3dB = rad/s 97. In the feedback network shown below, if the
R1 C
feedback factor k is increased, then the
(d) High pass filter with (GATE (EE) - 2013)
1
f3dB = rad/s
R1 +R 2 C
1K
1V
1K
1V
175
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
2 50 K
50 K (c)
Va - T
+ tp
l
V0 +
50 K
V0
-
v
l
(a) + 12 V
10 K
+
)
T -
-12 V
47 K
V in
V out
1K
V 7= 0.7 V
v
l
ZL
R1
IL Vi +
R1 V0
- -
+
R0
VI
(a) increase gain
(b) reduce offset voltage
(a) V/ ZL (b) V / Z L IR 1 (c) reduce offset current
(c) Vi / R1 (d) Vi R1 ZL (d) increase CMRR
R2
-
+
+
(a) Vi (b) Vi
104. In the inverting op-amp circuit shown below 1. Unity gain and no phase shift
the resistance Rg is chosen as R1 || R2 in order 2. Infinite gain and 180°C phase shift
to
3. Very high input impedance and very low
(IES (EE) - 2002) output impedance
177
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
4. It is a buffer amplifier
Vou t
Which of these statements are correct?
(IES (EE) - 2003)
(a) 1 and 3 (b) 2 and 4 (d) t
l
Vou t RS
t
l
(b) RL
(a) Vs
RS RL RS
(b) VS / R S
Vou t
(c) VS / R L
(c) t
l
1 1
(d) VS
RS R L
178
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
R
vs2 113. The cut-in voltage of the diodes in the rectifier
- of Figure is 0.6 V
V0
Vs1 +
111. A sinusoidal waveform can be converted to a Identify the correct output input characteristic
square waveform by using a (V0 vs Vi )
(IES (EE) - 2001)
(a) two stage transistorized over driven
amplifier
(a)
(b) two stage diode detector circuit
(c) voltage comparator based on op-amp
(d) regenrative voltage comparator circuit
Vs +
V0 (c)
- I0 RL
RS
(d)
179
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
1
(a) 2 sin t (b) sin t
4 2 4
1
(c) sin t (d) 2 sin t
2 4 4
(a) 11 v1 (b) 10 v1
(c) v1 (d) zero
115. The output voltage V0 of the given circuit is
(a) 200 Hz (b) 200 MHz (a) equal to zero because the input is zero
(c) 200 kHz (d) 2 MHz (b) dependent on element values hence
nothing can be predicted without a
knowledge of element values
117. The v0 of the Op-Amp circuit shown in the given (c) a square wave varying between +VCC and
figure is –VCC
(d) a sinusoidal wave of amplifier VCC
180
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(a) – 5 mA (b) – 10 mA
The output voltage V0 for an input Vi = [2 + sin (c) + 25 mA (d) – 50 mA
(100 t)] V
(a) 3/2 sin (100 t)
123. Consider the following circuit :
(b) 3 sin (100 t)
(c) 2 sin (100 t)
(d) 3 sin (100 t) + 1/2
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ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(a) addition
(b) subtraction
(c) both addition and subtraction
(d) multiplication
(a) 9 (b) 11
(c) 10 (d) 21
(a) (b)
(c)
(b)
(d)
(c)
(a)
183
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(a) 60 mV dc (b) 110 mV dc where f0 is the zero frequency and fp is the pole
(c) 130 mV dc (d) 150 mV dc frequency. For a standard frequency response
of the amplifier.
(IES (EC) - 1997)
133. In order to obtain triangular pulses at the output
of the circuit shown in the figure the input should (a) fp >> fo (b) fp = fo
be (c) fp << fo (d) fo = 2fp
(IES (EC) - 1997)
136. The OP-AMP circuit shown in the figure is
(IES (EC) - 1997)
(a) grounded
(b) a square wave
(c) a triangular wave (a) a sample/hold circuit
(d) a trigger (b) a rectifier/amplifier circuit
(c) a peak detector circuit
134. The transfer function of an amplifier is given by (d) an antilog amplifier circuit
Vo 2810
Av 137. In the circuit shown, it is required that Vo = Vi
Vs f f
1 j 5
1 j 6 the values of l, m, n are, respectively (x
5.85 10 5.85 10
represents don’t care condition)
The high 3-db frequency of the amplifier will (IES (EC) - 1998)
be approximately
(IES (EC) - 1997)
(a) 5850 kHz (b) 585 kHz
(c) 5850 Hz (d) 585 Hz
R2 R3
R2 R3 R
4
(a) R1
3
(a) sin 100 t (b) sin 100 t R3 R4
2 R R R2
3 4
(c) 2 sin 100 t (d) 3 sin 100 t (b) R1
185
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
R2 R4
R R R3
2 4
(c) R1 (d)
R2 R3
(d) R
1 144. In the circuit shown in the given figure, the
output voltage will be
(IES (EE) - 1998)
142. If the differential and common mode gains of a
differential amplifier are 50 and 0.2
respectively, then the CMRR will be
(IES (EE) - 1998)
(a) 10 (b) 49.8
(c) 50.2 (d) 250
186
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(a) 4 3 1 2
(b) 3 5 2 1
T1
R2 R2
T2 (c) 4 5 2 1
(d) 5 4 1 2
-Ve
187
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(a) low-pass filter (b) high-pass filter 159. In the circuit shown in the figure, the value of
(c) band-pass filter (d) band-stop filter output ‘v0’ is
(IES (EE) - 1999)
(a) + 3V (b) – 3V
(c) – 7V (d) + 7V
189
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
190
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(a) 0.001 μF (b) 0.01 μF (b) Pulse modulator and astable multivibrator
(d) Decrease the discharging time of C (d) When it is used as input to a pulse
transformer
Statement (II) : Quasi stable state duration is (b) Capture range - Lock range = Free
decided by charging time of capacitor. running frequency
(IES (EC) - 2013) (c) Capture range > Lock range
(a) Both Statement (I) and Statement (II) are (d) Capture range < Lock range
individually true and Statement (II) is the
correct explanation of Statement (I).
(b) Both Statement (I) and Statement (II) are 185.
individually true but Statement (II) is not
the correct explanation of Statement (I).
(c) Statement (I) is true but Statement (II) is
false.
(d) Statement (I) is false but Statement (II) is
true.
184. In a PLL
(IES (EC) - 2011)
(a) Capture range - Lock range Free The circuit shown is
running frequency (IES (EE) - 2011)
194
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
5 5
(c) V (d) V
π 2π
196
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
CONVENTIONAL PROBLEMS
01. In Fig. if the CMRR of the operational amplifier
is 60 dB, then the magnitude of the output
voltage is :
197
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
198
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
199
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
200
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(c)
(d) A capacitor C is connected to the point A
in Figure (c) through a switch S1 at t = 0.
Draw the time response of the voltage
across the capacitor vc(t) for t > 0.
25. For the circuit shown in Figure, determine the
input impedance Z. Assume the op-amp to be
an ideal one.
201
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(a)
(b) If Y1 = sC1, Y4 = sC4, Y2 = G2, Y3 = G3,
what is the nature of the filter that will be
realized by the circuit ?
202
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
33. The input voltage Vi in the circuit shown in 35. Draw the circuit for precision half-wave and
Figure is a 1 kHz sine-wave of 1V amplitude. full-wave rectifiers, using Op-Amp. Explain
Assume ideal operational amplifiers with 15 their working with the help of waveforms and
VDC supply. Sketch on a single diagram the equations.
waveforms of the voltage Vi 1, Vo and V1
shown, indicating the peak value of V1 and the (IES (EC) - 1997)
203
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
ANSWER KEY
01. c 35. d 69. d 103. d 137. b 171. a
02. c 36. a 70. c 104. c 138. a 172. d
03. a 37. c 71. a 105. b 139. b 173. b
04. d 38. b 72. c 106. c 140. b 174. c
05. d 39. c 73. b 107. d 141. c 175. b
06. a 40. a 74. d 108. b 142. d 176. d
07. c 41. b 75. d 109 b 143. b 177. c
08. c,d 42. a 76. c 110. d 144. d 178. b
09. b 43. c 77. b 111. c 145. d 179. b
10. d 44. c 78. b 112. b 146. d 180. d
11. a 45. d 79. b 113. b 147. b 181. d
12. d 46. b 80. a 114. a 148. c 182. b
13. a 47. b 81. c 115. d 149. b 183. a
14. c 48. c 82. d 116. c 150. b 184. c
15. d 49. d 83. c 117. d 151. b 185. c
16. a 50. c 84. a 118. a 152. a 186. d
17. a 51. d 85. d 119. a 153. b 187. b
18. a 52. a 86. d 120. a 154. c 188. b
19. a 53. b 87. a 121. b 155. c 189. a
20. d 54. a 88. b 122. b 156. a 190. a
21. c 55. b 89. c 123. c 157. b 191. c
22. a 56. a 90. b 124. c 158. c 192. b
23. c 57. c 91. b 125. d 159. d 193. d
24. d 58. a 92. d 126. b 160. c 194. a
25. b 59. b 93. d 127. a 161. b 195. c
26. d 60. b 94. b 128. d 162. c
27. d 61. d 95. b 129. d 163. d
28. a 62. c 96. c 130. a 164. c
29. c 63. c 97. a 131. b 165. a
30. b 64. c 98. d 132. b 166. c
31. a 65. b 99. b 133. a 167. c
32. b 66. d 100. a 134. a 168. b
33. a 67. a 101. b 135. a 169. b
34. d 68. a 102. c 136. b 170. b
205
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
CHAPTER-7
FEEDBACK AMPLIFIER
01. The feedback amplifier shown in Fig. has : (a) improves the signal to noise ratio at the
(GATE (EC) - 1989) i/p.
(b) improves the signal to noise ratio at the
o/p.
(c) does not effect the signal to noise ratio at
the o/p.
(d) Reduces distortion
(c) increase in distortion, while the output (b) Increase frequency and phase distortions
resistance decreases (c) Reduces bandwidth
(d) decrease in input resistance, while the (d) Increases Noise
output resistance increases
207
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
12. An amplifier has an open-loop gain of 100, an 15. An amplifier without feedback has a voltage
input impedance of 1, and an output gain of 50, input resistance of 1K and output
impedance of 100 . A feedback network with
resistance of 2.5 K . The input resistance of
a feedback factor of 0.99 is connected to the
amplifier in a voltage series feedback mode. the current-shunt negative feedback amplifier
The new input and output impedances, using the above amplifier with a feedback factor
respectively, are of 0.2 is
208
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
210
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(c) 2 and 3 are correct (a) is greater than that for critical coupling and
(d) 1, 2 and 3 are correct the amplifier characteristic is double
peaked
(b) is less than that for critical coupling and
30. In the shunt series feedback amplifier, the basic the amplifier characteristic has a single
amplifier and the feedback network are parallel peak
connected at the input and series connected at
the output. The signal sampled and the summing (c) is same as that for critical coupling and
down will be respectively the amplifier characteristic is double
peaked
(IES (EE) - 1999)
(d) is less than that for critical coupling and
(a) current and current the amplifier characteristic is doubled
(b) current and voltage peaked
(c) voltage and current
(d) voltage and voltage 33. A tuned amplifier has a voltage gain of 100 and
a bandwidth of 10 kHz. It is required to
increase the bandwidth to 20 kHz. This can be
31. A transistor amplifier has a voltage gain of 50, achieved by which one of the following ways ?
input resistance of 1k and output resistance (IES (EC) - 2004)
of 40 k . The amplifier is now provided 10% (a) By doubling the gain
negative voltage feedback in series with the
(b) By doubling the resonant frequency
input. With feedback, the voltage gain, input
resistance and output resistance will be (c) By halving the Q of the coil
respectively (d) By halving the power supply voltage
(IES (EE) - 1999)
(a) 8.7 k and 3 k 34. For the amplifier shown in the figure given
below, the lower cut-off frequency depends on
(b) 8.33, 6 k and 6.66 k
which of the following ?
(c) 5.33, 8.33 k and 8.66 k (IES (EC) - 2007)
(d) 6.66, 8.86 k and 6.66 k
211
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(a) CS, CE, internal junction capacitances of (d) 100 kHz, 6.05 MHz and 5.95 MHz
transistor
(b) Strong wiring capacitance (CW), CC 38. The given circuit has a feedback factor of
(c) CS, CE, CC (IES (EC) - 1999)
(d) CS, CE only
41. Consider the following amplifier with negative (a) If the signal sampled is a voltage
feedback: (b) If the signal sampled is a current
(IES (EC) - 2002) (c) If the feedback signal is a voltage
(d) If the feedback signal is a current
213
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
47. The amplifier has gain A = 100 180°, upper (a) Current series feedback
cut off frequency of 100 kHz and lower cut off (b) Voltage series feedback
frequency of 1 kHz. A negative feedback of
(c) Current shunt feedback
β = 0.1 is added. Which one of the following
is not correct ? (d) Voltage shunt feedback
B2 B2
50. Which one of the following type of negative (c) (d)
β Aβ
feedback increases the input resistance and
decreases the output resistance of an amplifier?
(IES (EC) - 2009)
214
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
215
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
216
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
CHAPTER-8
MULTI-STAGE AMPLIFIER
01. The configuration of cascode amplifier is : (d) A common base stage followed by a
(GATE (EC) - 1987) common Emitter stage
(a) CE - CE (b) CE - CB
(c) CC - CB (d) CC - CC 05. A multistage Amplifier has a low-pass
Response with three Real poles at
s ω1 ω2 and ω3 .The approximate overall
02. The Bandwidth of an n-stage tuned Amplifier, bandwidth B of the Amplifier will be given by
with each stage having a bandwidth of B, is
given by (GATE (EC) - 1998)
B B 1 1 1 1
(a) (b)
n n (b) B
1 2 3
1 B (c) B 1 2 3
1/3
(c) B 2n 1 (d) 1
n
2 1
(d) B 12 22 33
fu A Max
(a) (b) f u 2 1 Av
2 1
(b)
(c) fu / 2 (d) 2f u
219
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
Av
A Max +VCC
(d)
f
l
220
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
(a) To increase the voltage gain and increase 23. The overall bandwidth of two identical voltage
the bandwidth amplifies connected in cascade will
(b) To increase the voltage gain and reduce (IES (EE) - 1998)
the bandwidth (a) remain the same as that of a single stage
(c) To decrease the voltage gain and increase (b) be worse than that of a single stage
the bandwidth
(c) be better than that of single stage
(d) To decrease the voltage gain and reduce
the bandwidth (d) be better if stage gain is low and worse if
stage gain is high
Frequency
B. Inductive coupling
Frequency
C. Transformer coupling
D. Direct coupling
22. A transformer coupled amplifier would give List-II
(IES (EE) - 1998) (Circuit/property)
(a) maximum voltage gain 1. Higher voltage gain and impedance
(b) impedance matching matching
(c) maximum current gain 2. Ability to amplify dc and low frequency
signals
(d) larger bandwidth
3. Minimum possible non-linear distortion
221
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
4. Low collector supply voltages can be used equivalent upper cut-off frequency of the
Codes cascaded amplifier would be
(c) 1 2 3 4
(d) 4 3 2 1 28. An amplifier using BJT has two identical stages
each having a lower cut-off (3 dB) frequency
of 64Hz due to coupling capacitor. The emitter
26. Match List -I (Circuit ) with List-II bypass capacitor also provides a lower cut-off
(Characteristic) and select the correct answer (3 dB) frequency due to emitter degeneration
using the codes given below the Lists : alone of 64 Hz. The lower (3 dB) frequency of
the overall amplifier is nearly
(IES (EC) - 1997)
(IES (EC) - 2000)
List-I
(a) 100 Hz (b) 128 Hz
A. RC-coupled amplifier
(c) 156 Hz (d) 244 Hz
B. Tuned amplifier
C. Chopper stablized amplifier
29. An RC amplifier stage has a bandwidth of
D. Direct coupled amplifer 500 kHz. What will be the rise time of this
List-II amplifer stage ?
1. Very low drift (IES (EC) - 2002)
2. Flat frequency response from zero (a) 0.35 μs (b) 0.7 μs
frequency on wards
(c) 1.0 μs (d) 2.0 μs
3. Flat frequency response with an upper and
a lower cut-off frequency
30. Consider the following statements in respect
4. Peak in gain frequency response
of a transistor R-C coupled amplifer
Codes
1. The low frequency response is determined
A B C D by the transistor junction capacitors.
(a) 4 3 1 2 2. The high frequency response is limited by
(b) 3 4 2 1 coupling capacitors.
(c) 3 4 1 2 3. The miller capacitance reduces the gain
at high frequencies.
(d) 4 3 2 1
4. As the gain is increased the bandwidth gets
reduced.
27. The upper cut-off frequencies f 21 and f22 of the Which of these statements are correct ?
two stages of a cascaded amplifier are
respectively 5 MHz and 4.4 MHz. The (IES (EC) - 2003)
222
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
Which of these components in a R-C coupled 41. Low frequency response of RC coupled
amplifier control the lower cut-off frequency amplifier can be improved by
of the amplifer ?
(IES (EC) - 2013)
(IES (EC) - 2009)
(a) increasing the value of the coupling
(a) 1 and 2 (b) 2 and 3 capacitor only
(c) 3 and 4 (d) 1 and 4 (b) increasing the values of the bypass
capacitor and coupling capacitor
38. In an RC coupled transistor amplifier (c) increasing the value of bypass capacitor
only
1. Low-frequency response is determined by
coupling capacitors (d) decreasing the value of the coupling
capacitor
2. High-frequency response is determined by
junction capacitance
3. Mid-frequency response is determined by 42. Three identical amplifiers, each having a gain
both coupling and junction capacitances. A0
of 600 are connected in cascade. The
(IES (EC) - 2011) 2
positive feedback loop has a gain of 0.008.
(a) 1 and 2 only (b) 1 and 3 only
The values of A0 that will render the cascaded
(c) 2 and 3 only (d) 1, 2 and 3 system oscillatory is
(IES (EE) - 2012)
39. The lower 3dB frequency of an n-stage amplifier (a) 10 (b) –10
with non-interacting stages is given by
(c) 250/3 (d) 250
(IES (EC) - 2012)
(a) 1 ωH (b) 2 ωH
224
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
225
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
CHAPTER-9
POWER AMPLIFIER
(b)
A 22 A 32 ..... (IES (EE) - 2009)
A1
226
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
List-II List-II
(Circuit/property) 1. Hi Fidelity
1. Requires PNP & NPN transistor pairs 2. Tuned amplifier
2. Prevents cross-over distortion 3. Power amplifier
3. Has maximum efficiency amongst these 4. Low distortion power amplifier
amplifiers Codes:
4. Has minimum efficiency amongst these A B C D
amplifiers
(a) 4 3 2 1
Codes:
(b) 1 2 3 4
A B C D
(c) 4 2 3 1
(a) 4 3 2 1
(d) 1 3 2 4
(b) 4 2 3 1
(c) 1 2 3 4
21. Consider the following statements:
(d) 3 2 1 4
in amplifiers,
1. a complementary symmetry amplifier has
19. Which one of the following is the advantage of 1 PNP and 1 NPN transistor
base modulation over collector modulation of
a transistor Class C amplifier ? 2. a boot strap incorporates emitter follower
3. the main function of transformer used in
(IES (EE) - 1997)
the output of a power amplifier is to
(a) Requires lower modulation power increase its voltage gain
(b) Higher power output per transistor 4. the harmonic distortion of the signal
(c) Better efficiency produced in a RC coupled tansistor
amplifier is due to transformer itself.
(d) Better linearity
Which of these statements are correct?
(a) 1, 2 and 3 (b) 2, 3 and 4
20. Match List-I with List-II and select the correct
answer using the codes given below the lists: (c) 1, 3 and 4 (d) 1, 2 and 4
Of these statements
(IES (EC) - 1998)
(a) 2 and 3 are correct
(b) 1 alone is correct
(c) 2 alone is correct
(d) 1 and 2 are correct
(c)
(d)
(a) 10 W (b) 16 W
23. The dissipation at the collector is in the
quiescent state and increases with excitation in (c) 20 W (d) 32 W
the case of a
(IES (EC) - 1997) 26. In an amplifier, the power output is 2 W at 5kHz,
(a) Class A series-fed amplifier and 0.5 W at 50 Hz. If the input power is
constant at 10 mW, what is the variation
(b) Class A transistor coupled amplifier (approximate) of power gain in dB at two
(c) Class AB amplifier frequencies ? (log10 2 = 0.30)
(d) Class B amplifier (IES (EC) - 2007)
(a) 6 dB (b) 8 dB
24. Consider the following statements : (c) 3 dB (d) 16 dB
A class-B amplifier
1. Is biased just at cut-off 27. An amplifier has a power gain of 200. What is
its gain in dB ? (log10 2 = 0.30)
2. has a high theoretical efficiency of 78.5%
because its quiescent current is low (IES (EC) - 2007)
3. Is based at the mid-point of load time. (a) 14 dB (b) 17 dB
(c) 20 dB (d) 23 dB
230
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
28. If a class C power amplifier has an input signal 32. An amplifier has a d.c. power supply of 15V
with frequency of 200 kHz and the width of and draws a current of 10mA. It produces
collector current pulses of 0.1 μ s, then the duty resistance of 600 for a signal frequency of
cycle of the amplifier will be 1 kHz. What will be its a.c. power output ?
(IES (EC) - 1999) (IES (EC) - 2004)
(a) 1% (b) 2% (a) 260 mW (b) 20.8 mW
(c) 10% (d) 20%
(c) 520 mW (d) 40.6 mW
30. Which one of the following power amplifiers 2. High efficiency with crossover distortion
has the maximum efficiency ?
3. Harmonic generator with highest possible
(IES (EC) - 2000) conversion efficiency
34. Where does the operating point of a class-B 2. The power output is low
power amplifier lie ?
3. Crossover distortion is present
(IES (EC) - 2006)
4. The standby power dissipation is absent
(a) At the middle of a.c. load line
Which of the above statements are correct ?
(b) Approximately at collector cut-off on both
(IES (EC) - 2009)
the d.c. and a.c. load lines
(a) 1, 2 and 3 (b) 1, 2 and 4
(c) Inside the collector cut-off region on
a.c. load line (b) 1, 3 and 4 (d) 2, 3 and 4
(d) At the middle point of d.c. load line
(b) They are used as the front end of multistage (c) 2, 3 and 4 (d) 4 and 5
amplifiers
(c) They are used near the end of the 39. Using transistors:
multistage amplifiers
1. Class-A power amplifier has a minimum
1 efficiency of 50%.
(d) They have a high power rating W
2 2. Class-B push-pull power amplifier gives
rise to crossover distortion.
3. Class-AB push-pull power amplifier has
37. Consider the following statements regarding the
higher efficiency than Class-B push-pull
class B power amplifiers (Complementry
amplifier
symmetry type)
4. Class-C power amplifier is generally used
1. The efficiency of the amplifier is higher than
with tuned load for RF amplifications.
that of class-A amplifier
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(a) Both Statement (I) and Statement (II) are 10. c 31. b
individually true and Statement (II) is the
11. b 32. b
correct explanation of Statement (I).
(b) Both Statement (I) and Statement (II) are 12. d 33. b
individually true but Statement (II) is not 13. b 34. b
the correct explanation of Statement (I).
14. c 35. c
(c) Statement (I) is true but Statement (II) is
false. 15. a 36. b
(d) Statement (I) is false but Statement (II) is 16. d 37. c
true.
17. b 38. a
18. a 39. b
41. An output signal of a power amplifier has
amplitudes of 2.5 V fundamental, 0.25 V 19. a 40. b
second harmonic and 0.1 V third harmonic. The
total percentage harmonic distortion of the signal 20. d 41. b
is 21. a
(IES (EC) - 2012)
(a) 12.6% (b) 10.8%
(c) 6.4% (d) 1.4%
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CONVENTIONAL PROBLEMS 9
01. In order to reduce the harmonic distortion in an
Amplifier its dynamic range has to be ____
(GATE (EC) - 1994)
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CHAPTER-10
OSCILLATOR
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R1
-V CC -
+ +
LC
L=10H
CC R1 + Network
V (f) V0 (f)
f
- B(f)
C1=2pF C2=2pF
R2
-
R0
CC
(a) R 2 5R 1 (b) R 2 6R 1
1 1
(a) 2 6RC (b) 2RC
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ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
1 List-I
1
(c) 6RC (d) 6 2RC (Oscillator)
A. Wien Bridge
B. Colpitts
07. The value of C required for sinusoidal
C. Hartley
oscillations of frequency 1 kHz in the circuit of
the figure is D. Clapp
(GATE (EC) - 2004) List-II
(Characteristics/Features)
1 k 2.1 k
1. RF oscillator : two inductance and one
capacitance on the reactance network
- 2. LC oscillator for RF Frequency : three
V out
+ C capacitances and one inductance in the
reactance network
1 k
3. RC oscillator for audio frequency
applications
C
4. RF oscillator : two capacitances and one
1 k
inductance as the reactance network
Codes:
1 A B C D
(a) μF (b) 2πμF
2π (a) 2 1 4 3
1 (b) 2 4 1 3
(c) μF (d) 2π 6μF
2π 6 (c) 3 4 1 2
(d) 3 1 4 2
08. A crystal oscillator is frequently used in digital
circuits for timing purpose because of its 10. An FET oscillator uses the given phase shift
(a) Low cost network as shown below. The minimum gain
required for oscillation is
(b) High frequency stability
(IES (EE) - 2003)
(c) simple circuitry
(d) ability to set the frequency at the desired
value
R
09. Match List-I with List-II and select the correct C R
answer using the codes given below the lists:
(IES (EC) - 1996)
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ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
16. A Hartley oscillator is used for generating Which of the above statements are correct ?
(IES (EC) - 1999) (IES (EC) - 2002)
(a) very low frequency oscillation (a) 1, 2, 3 and 4 (b) 1 and 2
(b) radio-frequency oscillation (c) 1, 3 and 4 (d) 3 and 4
(c) microwave oscillation
(d) audio-frequency oscillation 20. An amplifier will generate stable sinusoidal
oscillations if we provide feedback such that
17. In every practical oscillator, the loop gain is (IES (EC) - 2002)
slightly larger than unity and the amplitude of (a) its poles lie close to jω - axis in the right
the oscillations is limited by the half of s-plane
(IES (EC) - 2000)
(b) its poles lie close to jω - axis in the left
(a) magnitude of the loop gain half of s-plane
(b) onset of non-linearity (c) its poles lie on the +ve real axis in s-plane
(c) magnitude of the gain of the amplifier (d) its poles lie anywhere in s-plane
(d) feedback transmission factor
21. Consider the following circuit
23. Match List-I (Name of the oscillator) with 25. In a practical oscillator circuit, which one of
List-II (Characteristics) and select the correct the following limits the amplitude of the
answer using the codes below the lists oscillations ?
(IES (EC) - 2005) (IES (EC) - 2008)
List-I (a) Onset of non-linearily
A. Colpitts oscillator (b) Power supply voltage
B. Phase shift oscillator (c) Oscillation frequencies
C. Tuned diode oscillator (d) temperature of the active device
D. Relaxation oscillator
List-II 26. Which one of the following oscillators is used
1. RC oscillator for the generation of high frequencies ?
CONVENTIONAL PROBLEMS
01. Figure shows an RC-Phase oscillator. Solve
the network to find the minimum value of hfe for
the transistor for oscillations to be possible. Also
determine the frequency of such oscillations.
Take C = 0.01 F and hie = 2 K ohms
(GATE (EC) - 1990)
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ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT
05. A transistor LC oscillator circuit is shown in and Cp = 1.0 p.f. Determine the resonance fs
Fig. Assume that the transistor has very high and fp
(so that you may neglect rd). Derive an (IES (EE) - 1999)
equation governing the circuit operation, and
find the frequency of oscillation. Also, state the
gain condition required for oscillation to start. 10. Discuss where the sinusoidal oscillators are
used ? For phase shift oscillator why three
(GATE (EC) - 1999)
sections of ‘R-C’ circuits are cascaded. Draw
and explain a simple phase shift oscillator using
three sections of R-C circuit and a transistor.
Derive the formula for the frequency of
oscillation. Make comments on the transistor
current gain. Design the values of R-C to give
oscillation of say nearly 1 kHz.
(IES (EE) - 2000)
ANSWER KEY
02. a 17. b
03. a 18. d
04. b 19. b
05. a 20. a
06. a 21. a
07. a 22. b
08. b 23. b
09. c 24. d
10. c 25. a
11. c 26. c
12. b 27. b
13. b 28.
14. d
15. d
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ENGINEER’S CIRCLE
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CHAPTER-11
PRACTISE SHEET
COMMON DATA
* electron charge e = 1.6 × 10–19 C 04. In a forward biased diode with Na >> Nd, the
* Room temperature T = 300 k product of the diffusion capacitance Cd and the
dynamic resistance rd equals
kT
* Thermal voltage = 0.025 V 1
e (a) (b) Tp
Tp
* Free space permittivity 0 =8.85×10–14 F/cm
1
* relative permittivity of silicon r = 12 (c) 2TP (d) 2Tp
* relative permittivity of SiO2 r = 4 Where Tp – the life time of minority carrier holes
* intrinsic carrier concentration
ni = 1.5 × 1010 – 3 cm 05. In a PN diode, for a constant value of current
* ideality factor n = 1 dV
at room temperature, varies
dT
One Mark Questions approximately at the rate of
01. When a diode is forward biased, the (a) – 2.5 mV/°C (b) – 25 mV/°C
recombination of free electrons and holes may (c) 2.5 mV/°C (d) 25 mV/°C
produce
(a) heat (b) light
06. The ratio of current for forward bias voltage of
(c) radiation (d) all of the above 0.04 V to the current for the same magnitude
of reverse bias is
02. In a step graded Junction, the width ‘w’ of the (a) 38788 (b) 3878
depletion layer varies as (c) 5000 (d) 58788
2
(a) V (b) V
(c) V (d) V–1 07. For what voltage will the reverse current in PN
junction Ge diode reaches 90% of its saturation
points at room temperature
03. In a reverse biased PN diode, t he (a) – 0.016 V (b) 0.016 V
concentration of minority holes in the n-region
at the junction boundary equals (c) 0.16 V (d) None
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Conventional Problemsx
01. A pick-up signal N10 is power amplified using
a complementary symmetry pushpull amplifier
and fed to a 5-ohm loudspeaker as shown in
Fig. The specifications of the power transistor
are as follows :
(i) IC |max = Maximum collector current
= 2 Amps.
(ii) PC |max = Maximum Power disipassion
= 1 Watt.
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ENGINEER’S CIRCLE
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s
T s
R1C
2s 1
s2
R3C RR3C 2
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