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EDC & ANALOG CIRCUIT

C ON T E N T
TOPIC Page No.

 CHAPTER 1 SEMICONDUCTOR PHYSICS 2

 CHAPTER 2 DIODE CIRCUIT 25

 CHAPTER 3 TRANSISTOR (BJT) 63

 CHAPTER 4 JFET 119

 CHAPTER 5 MOSFET 130

 CHAPTER 6 OPERATIONAL AMPLIFIER 150

 CHAPTER 7 FEEDBACK AMPLIFIER 206

 CHAPTER 8 MULTISTAGE AMPLIFIER 217

 CHAPTER 9 POWER AMPLIFIER 226

 CHAPTER 10 OSCILLATOR 235

CHAPTER 11 PRACTICE SHEET 244

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CHAPTER-1
SEMICONDUCTOR
01. Consider two energy levels : E1, E ev above the mobility of carriers
Fermi level and E2, E ev below the Fermi level, (GATE (EC) - 1987) (2M)
P1 and P2 are respectively the Probabilities of E1
being occupied by an electron and E2 being (a) Depends upon the temperature of the
empty. Then semiconductor
(GATE (EC) - 1987) (2M) (b) Depends upon the type of the semiconductor
(a) P1 > P2 (c) Varies with life time of the semiconductor
(b) P1 = P2 (d) Is a universal constant.
(c) P1 < P2
(d) P1 and P2 depend on number of free elctrons 05. The diffusion capacitance of a p-n junction
(GATE (EC) - 1987) (2M)
02. In an intrinsic Semiconductor the free electron (a) Decreases with increasing current and
concentration depends on : increasing temperature
(GATE (EC) - 1987) (2M) (b) Decreases with decreasing current and
increasing temperature
(a) Effective mass of electrons only
(c) Increases with increasing current and
(b) Effective mass of holes only increasing temperature
(c) Temperature of the Semiconductor (d) Does not depend on current and
(d) Width of the forbidden energy band of the temperature
semiconductor

06. Due to illumination by light, the electron and hole


03. Direct band gap semiconductors: Concentrations in a heavily doped N type semi
(GATE (EC) - 1987) (2M) conductor increases by  n and  p respectively
if ni is the intrinsic concentration then,
(a) Exhibit short carrier life time and they are used
for fabricating BJTs (GATE (EC) - 1989) (2M)
(b) Exhibit long carrier life time and they are used (a) n < p (b) n > p
for fabricating BJTs
(c) n = p (d) n  p = n i2
(c) Exhibit short carrier life time and they are used
for fabricating Lasers
(a) Exhibit long carrier life time and they are used 07. The Concentration of ionized acceptors and
for fabricating BJTs donors in a Semiconductor are N A, N D
respectively. If NA > ND and ni is the intrinsic
Concentration, the position of the fermi level with
04. According to the Einstein relation, for any respect to the intrinsic level depends on
semiconductor the ratio of diffusion constant to
(GATE (EC) - 1989) (2M)
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ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) NA – ND (b) NA + ND Carriers are uniformly generated throughout its


volume. The Semiconductor in n-type with
NA ND N D = 10 19 /cm³. If the excess electron
(c) n i2 (d) ni
concentration in the steady state is n =1015/cm³
and if  p  10  sec. (minority carriers the life
08. Under high electric fields, in a semiconductor with time) the generation rate due to irradiation
increasing electric field, (GATE (EC) - 1992) (2M)
(GATE (EC) - 1990) (2M) (a) is 1020 e-h pairs / cm³/s
(a) The mobility of charge carriers decreases (b) is 1024 e-h pairs / cm³/s
(b) The mobility of the carriers increases (c) is 1010 e-h pairs / cm³/s
(c) The velocity of the charge carriers saturates. (d) Cannot be determined, as the given data is
(d) The velocity of the charge carriers increases. insufficient

09. In a uniformly doped PN junction, doping level 12. Consider the semiconductors A and B. The figure
of the n side is four times the doping level of shows variation of ln p with 1/T, where p
the p side. The ratio of depletion width xn/xp is resistivity and T the temperature, for the
will be two semiconductors. Choose the correct
statements (s)
(GATE (EC) - 1990)
(GATE (EC) - 1993)
(a) 0.25 (b) 1.0
(c) 0.5 (d) 2

10. A Silicon Sample is uniformly doped with 1016


phosphorus atoms / cm³ and 2 × 1016 boron
atoms / cm³ If all the dopants are fully ionized,
the material is
(GATE (EC) - 1991) (2M) (a) the bandgap energy of A is larger than that of
(a) n – type with carrier concentration of B
1016/cm³ (b) the bandgap energy of A is smaller than that
(b) p – type with carrier concentration of of B
1016/cm³ (c) the maximum wavelength of light needed to
(c) p – type with carrier concentration of create an electron hole pair is larger in A than
2×1016/cm³ in B.
(d) n – type with carrier concentration of (d) the maximum wavelength of light needed to
2×1016/cm³ create an electron hole pair is smaller in A
than in B.

11. A Semiconductor is irradiated with light such that

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EDC & ANALOG CIRCUIT

13. A small concentration of minority carries is 17. The depletion capacitance, CJ of an abrupt
injected into a homogeneous Semiconductor P-n junction with constant doping on either side
crystal at one point. An electric field of 10V/cm varies with reverse bias VR as
is applied across the crystal and this moves the (GATE (EC) - 1995) (1M)
minority carries a distance of 1cm in 20  sec.
The mobility (in cm²/v-sec) will be (a) CJ  VR (b) CJ  VR–1

(GATE (EC) - 1994) (1M) (c) CJ  VR–1/2 (d) CJ  VR–1/3


(a) 1,000 (b) 2,000
(c) 5,000 (d) 500,000 18. In a p-type silicon sample, the hole concentration
is 2.25  1015 / cm 3 . If the intrinsic carrier
concentration is 1.5 1010 / cm3 , what is the
14. The drift velocity of electrons, in silicon electron concentration in p-type silicon sample
(GATE (EC) - 1995) (1M) (GATE (EC) - 1995) (IES (EE) - 2005)
(a) is proportional to the elctric field for all values (a) zero (b) 1010/cm³
of electric field
(c) 105/cm³ (d) 1.5 × 1025/cm³
(b) is independent of the electric field
(c) Increases at low values of electric field and
decreases at high values of electric field 19. The p-type substrate in a conventional pN in
exhibiting negative differential resistance. isolated integrated circuit should be connected
to
(d) Increases linearly with electric field at low
values of electric field and gradually saturates (GATE (EC) - 1996)
at higher values of electric field. (a) however, i.e. left floating
(b) a DC ground potential
15. The Probability that an electron in a metal (c) the most positive potential available in the
occupies the fermilevel, at any temperature, circuit
(> 0K)
(d) the most negative potential available in the
(GATE (EC) - 1995) (1M) circuit
(a) 0 (b) 1
(c) 0.5 (d) 1.0 20. An n-type silicon bar 0.1 cm long and 100m 2
in cross-sectional area has a majority carrier
16. The diffusion potential across a P-N junction concentration of 5  10 20 / m 3 and the carrier
(GATE (EC) - 1995) (1M) mobility is 0.13m 2 / V  s at 300K. If the charge
(a) decreases with increasing doping of an electron is 1.6  10 19 Coulomb, then the
concentration resistance of the bar is
(b) increases with decreasing band gap. (GATE (EC) - 1997)
(c) does not depend on doping concentration (a) 105 ohm (b) 104 ohm
(d) increases with increase in doping (c) 10–1 ohm (d) 10–4 ohm
concentration
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EDC & ANALOG CIRCUIT

19. The electron concentration in a sample of (a) n + p = ni + pi (b) n + ni = p + pi


uniformly doped n-type silicon at 300 K varies (c) npi = nip (d) np = ni pi
linearly fro m 4  1019 cm 3 at x = 0 to
6  1016 / cm 3 at x  2 m. Assume a situation
23. A long specimen of p-type semiconductor
that electrons are supplied to keep this
material
concentration gradient constant with time. If
electronic charge is 1.6  10 19 Coulomb and the (GATE (EC) - 1998)

diffusion constant D n  35cm 2 / s, the current (a) is positively charged


density in the silicon, if no electric field is present, (b) is electrically neutral
is (c) has an electric field directed along its length
(GATE (EC) - 1997) (d) acts as a dipole
(a) Zero (b) 1120A / cm 2

(c) 560A / cm 2 (d) 1120 A / cm 2 24. n-type silicon is obtained by doping silicon with
(GATE (EC) - 2003)
(a) Germanium (b) Aluminium
20. The intrinsic carrier density at 300K is
1.5×1010/cm³, in silicon for n-type silicon doped (c) Boron (d) Phosphorus
to 2.25 × 1015 atoms/cm³, the equilibrium
electron and hole densities are
25. The longest wavelength that can be absorbed by
(GATE (EC) - 1997) (2M) silicon, which has the bandgap of 1.12 eV, is
(a) n = 1.5 × 1015/cm³, p = 1.5 × 1010/cm³ 1.1 m . If the longest wavelength that can be
absorbed by another material is 0.87 m , then
(b) n = 1.5 × 1010/cm³, p = 2.25 × 1015/cm³
the bandgap of this material is
(c) n = 2.25 × 1015/cm³, p = 1.0 × 105/cm³
(GATE (EC) - 2004)
(d) n = 1.5 × 1010/cm³, p = 1.5 × 1010/cm³
(a) 1.416 eV (b) 0.886 eV
(c) 0.854 eV (d) 0.706 eV
q
21. The unit of are
KT
26. Consider an abrupt p - junction. Let Vbi be the
(GATE (EC) - 1998) built-in potential of this junction and VR be the
(a) V (b) V–1 applied reverse bias. If the junction

(c) J (d) J/K cap acit ance  C j  is 1pF for Vbi  VR  1V,
then for Vbi  VR  4V, C j will be
22. The electron and hole concentration in a intrinsic (GATE (EC) - 2004)
semiconductor are ni and pi respectively. When
doped with a p-type material, these change to n (a) 4 pF (b) 2 pF
and p, respectively. Then (c) 0.25 pF (d) 0.5 pF
(GATE (EC) - 1998)
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ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

27. In an abrupt p - n junction, the doping impurity concentration (ND) in the sample is
concentrations on the p - side and n - side (GATE (EC) - 2004)
are N A  9  1016 / cm 3 and N D  1 1016 / cm 3
(a) 2 × 1016 / cm³ (b) 1 × 1016 / cm³
respectively. The p - n junction is reverse biased
(c) 2.5 × 1015 / cm³ (d) 5 × 1015 / cm³
and the total depletion width is 3m, The
depletion width on the p-side is
(GATE (EC) - 2004) 32. A Silicon sample A is doped with 1018atoms/cm³
of Boron. Another sample B of identical
(a) 2.7 m (b) 0.3 m dimensions is doped with 1018atoms/cm³ of
(c) 2.25 m (d) 0.75 m Phosphorus. The ratio of electron to hole mobility
is 3. The ratio of conductivity of the sample A to
B is
28. The intrinsic carrier concentration of silicon sample (GATE (EC) - 2005)
at 300 K is 1.5 × 1016 / m³. If after doping, the
number of majority carriers is 5 × 1020 / m³, the 1
minority carrier density is (a) 3 (b)
3
(GATE (EC) - 2003)
2 3
(a) 4.50 × 1011 / m³ (b) 3.33 × 104 / m³ (c) (d)
3 2
(c) 5.00 × 1020 / m³ (d) 3.00 × 10–5 / m³

33. The primary reason for the widespread use of


29. The bandgap of Silicon at room temperature is Silicon in semiconductor device technology is
(GATE (EC) - 2003, 2005) (GATE (EC) - 2005)
(a) 1.3 eV (b) 0.7 eV (a) Abundance of Silicon on the surface of the
(c) 1.1 eV (d) 1.4 eV earth .
(b) Larger bandgap of Silicon in comparison to
Germanium
30. A Silicon PN junction at a temperature of 20°C
has a reverse saturation current of 10 pico- (c) Favourable properties of Silicon-dioxide
Amperes (pA). The reverse saturation current at (SiO2)
40°C for the same bias is approximately (d) Lower melting point.
(GATE (EC) - 2004)
(a) 30 pA (b) 40 pA 34. The majority carriers in an n-type semiconductor
(c) 50 pA (d) 60 pA have an average drift velocity v in a direction
perpendicular to a uniform magnetic field B. The
electric field E induced due to Hall effect acts in
31. The resistivity of a uniformly doped n-type silicon the direction
sample is 0.5   cm . If the electron mobility (GATE (EC) - 2006)
 n  is 1250 cm²/V-sec and the charge of an (a) V × B (b) B × V
electron is 1.6 × 10–19 Coulomb, the donor (c) along V (d) opposite to V
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EDC & ANALOG CIRCUIT

35. The concentration of minority carriers in an 1.2 V is 2  m . For a reverse bias of 7.2 V, the
extrinsic semiconductor under equilibrium is depletion layer width will be
(GATE (EC) - 2006)(IES (EE) - 2011) (GATE (EC) - 2007)
(a) directly proportional to the doping (a) 4 μ m (b) 4.9 μ m
concentration
(c) 8 μ m (d) 12 μ m
(b) inversely proportional to the doping
concentration
(c) directly proportional to the intrinsic 39. The electron and hole concentrations in an
concentration intrinsic semiconductor are ni per cm³ at 300 K.
Now, if acceptor impurities are introduced if with
(d) inversely proportional to the intrinsic a concentration of NA per cm³(Where NA >> ni)
concentration the electron concentration per cm³ at 300 K will
be
36. A heavily doped n-type semiconductor has the (GATE (EC) - 2007)
following data : (a) ni (b) ni + NA
hole - electron mobility ratio : 0.4
18
n i2
Doping concentration : 4.2 × 10 atom /m³ (c) NA – ni (d)
NA
Intrinsic concentration : 1.5 × 1014 atom/m³
The ratio of conductance of the n-type
semiconduct or t o that o f the intrinsic 40. Which of the following is NOT associated with a
semiconductor of same material and at the same p-n junction ?
temperature is given by (GATE (EC) - 2008)
(GATE (EC) - 2006) (a) Junction
(a) 0.00005 (b) 2,000 (b) Charge Storage Capacitance
(c) 10,000 (d) 20,000 (c) Depletion Capacitance
(d) Channel Length Modulation
37. Under low level injection assumption, the injected
minority carrier current for an extrinsic
semiconductor is essentially the 41. A silicon wafer has 100 nm of a oxide on it and is
inserted in a furnace at a temperature above
(GATE (EC) - 2006) 1000°C for further oxidation in dry oxygen. The
(a) diffusion current oxidation rate
(b) drift current (GATE (EC) - 2008)
(c) recombination current (a) Is independent of current oxide thickness and
temperature
(d) induced current
(b) Is independent of current oxide thickness but
depends on temperature
38. A p+ n junction has a built-in potential of 0.8 V. (c) Slows down as the oxide grows
The depletion layer width at a reverse bias of
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EDC & ANALOG CIRCUIT

(d) Is zero as the existing oxide prevents further (a) V–1 (b) cm . V–1
oxidation. (c) V . cm–1 (d) V . s

42. Silicon is doped with boron to a concentration Common Data for Question 46 and 47
of 4×1017 atoms/cm³. Assume the intrinsic carrier
concentration of silicon to be 1.5×1010/cm³ and Consider a silicon p-n junction at room
the value of kT/q to be 25 mV at 300 K. temperature having the following parameters :
Compared to undoped silicon, the Fermi level of Doping on the n - side = 1 × 1017 cm–3
doped silicon
Depletion width on the n-side = 0.1  m
(GATE (EC) - 2008)
Depletion width on the p-side = 0.1  m
(a) goes down by 0.13 eV
Intrinsic carrier concentration = 1.4 × 1010 cm–3
(b) goes up by 0.13 eV
Thermal voltage = 26 mV
(c) goes down by 0.427 eV
Permittivity of free space = 8.85 ×10–14 F cm–1
(d) goes up by 0.427 eV
Dielectric constant of silicon = 12.

43. Which of the following is true?


46. The built-in potential of the junction
(GATE (EC) - 2008)
(GATE (EC) - 2009)
(a) A silicon wafer heavily doped with boron is
a P+ substrate (a) is 0.70 V

(b) A silicon wafer lightly doped with boron is a (b) is 0.76 V


P+ substrate (c) is 0.82 V
(c) A silicon wafer heavily doped with arsenic is (d) Cannot be estimated from the data given
a P+ substrate
(d) A Silicon wafer lightly doped with arsenic is
47. The peak electric field in the device is
a P+ substrate
(GATE (EC) - 2009)
(a) 0.15 MV.cm–1, directed from p-region to
44. In an n-type silicon crystal at room temperature,
n-region
which of the following can have a concentration
of 4  1019 cm 3 ? (b) 0.15 MV.cm–1, directed from n-region to
p-region
(GATE (EC) - 2009)
(c) 1.80 MV.cm–1, directed from p-region to
(a) Silicon atoms (b) Holes n-region
(c) Dopant atoms (d) Valence electrons (d) 1.80 MV.cm–1, directed from n-region to
p-region
45. The ratio of the mobility to the diffusion co-
efficient in a semiconductor has the unit 48. Co mpared t o a p-n junctio n with
(GATE (EC) - 2009) N A  N D  1014 / cm 3 which one of t he
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EDC & ANALOG CIRCUIT

following statements is TRUE for a p-n junction (c) 4.32 × 10³ A/cm² (d) 6.48 × 10² A/cm²
20 3
with N A  N D  10 / cm
(GATE (EC) - 2010) 51. Drift current in semiconductors depends upon
(a) Reverse breakdown voltage is lower and (GATE (EC) - 2011)
depletion capacitance is lower (a) only the electric field
(b) Reverse breakdown voltage is higher and (b) only the carrier concentration gradient
depletion capacitance is lower
(c) both the electric field and the carrier
(c) Reverse breakdown voltage is lower and concentration
depletion capacitance is higher
(d) both the electric field and the carrier
(d) Reverse breakdown voltage is higher and concentration gradient
depletion capacitance is higher

52. A silicon PN junction is forward biased with a


Statement for Linked Answer Questions constant current at room temperature . When the
49 and 50 temperature is increased by 10°C, the forward
The silicon sample with unit cross-sectional areas bias voltage across the PN junction
shown below is in thermal equilibrium. The (GATE (EC) - 2011)
following information is given : T = 300 K,
electronic charge = 1.6 × 10–19 C, thermal voltage (a) increases by 60 mV
= 26 mV and electron mobility = 1350 cm² / V.s (b) decreases by 60 mV
(c) increases by 25 mV
(d) decreases by 25 mV

53. In IC technology, dry oxidation (using dry


oxygen) as compared to wet oxidation (using
stem or water vapour) produces
(GATE (EC) - 2013)
49. The magnitude of the electric field at x = 0.5  m (a) superior quality oxide with a higher growth
is rate
(GATE (EC) - 2010) (b) inferior quality oxide with a higher growth rate
(a) 1 kV / cm (b) 5 kV / cm (c) inferior quality oxide with a lower growth rate
(c) 10 kV / cm (d) 26 kV / cm (d) superior quality oxide with a lower growth
rate

50. The magnitude of the electron drift current density


at x = 0.5  m is 54. If for intrinsic Silicon at 27°C, the charge
concentration and mobilities of free- electrons
(GATE (EC) - 2010)
4 4
and holes are 1.5 1016 per m3 , 0.13m3 /  Vs 
(a) 2.16 × 10 A/cm² (b) 1.08 × 10 A/cm²
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EDC & ANALOG CIRCUIT

58. In a p-n junction, to make the depletion- region


and 0.05m 2 /  Vs  respectively, its conductivity
extent predominantly into p-region, the
will be concentration of impurities in the p-region must
1 be
(a) 2.4  10 3    m 
(IES (EE) - 2003)
3 1
(b) 3.15  10   m (a) Much less than the concentration of impurities
in n-region
1
(c) 5  10 4    m  (b) Much higher than the concentration of
impurities in n-regipn
1
(d) 4.32  10 4    m  (c) Equal to the concentration of impurities in n-
region

55. A specimen of intrinsic germanium with the density (d) zero

of charge carriers of 2.5  1013 / cm 3 , is doped


with donor impurity atoms such that there is one 59. In a Hall effect experiment , a p-type.
donor impurity atom for every 106 germanium semiconductor sample with hole concentration
atoms. The density of germanium atoms is p1 is used. The measured value of the Hall voltage
4.4  1022 / cm 3 . The hole density would be is VH1. If the p-type sample is now replaced by
another p-type sample with hole concentration
(a) 4.4  1016 / cm 3 (b) 1.4  1010 / cm 3 p2 where p2 = 2p1, what is the new Hall voltage
VH2?
(c) 4.4  1010 / cm 3 (d) 1.4  1016 / cm 3
(IES (EE) - 2006)
(a) 2 VH1 (b) 4 VH1
56. The bonding forces in compound semiconductors,
such as GaAs, arise from (c) (1/2) VH1 (d) (1/4)VH1

(IES (EE) - 2002)


(a) ionic bonding 60. Match List - I (Semiconductor Property) with
List - II (Corresponding Unit) and select the
(b) metallic bonding correct answer using the codes, given below the
(c) covalent bonding lists:
(d) combination of ionic and covalent bonding (IES (EE) - 2007)
List - I
57. The junction capacitance of a graded junction A. Carrier mobility
varies with the applied reverse bias Vr as B. Diffusion length
(IES (EE) - 2002) C. Diffusion coefficient
(a) Vr1 (b) Vr1/ 2 D. Energy gap
List-II
(c) Vr1/3 (d) Vr1/ 2
1. eV(electron volt)
2. m²/V – sec
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EDC & ANALOG CIRCUIT

3. m 63. In an unbiased p-n junction, the junction current


4. m²/s at equilibrium is

Codes: (IES (EE) - 2006)

A B C D (a) due to diffusion of majority carriers only

(a) 4 2 3 1 (b) due to diffusion of minority carriers only

(b) 2 3 4 1 (c) zero, because equal and opposite drift and


diffusion currents for electrons and holes
(c) 2 3 1 4 cross the junction.
(d) 4 2 1 3 (d) zero because no charges cross the junction

61. Which one of the following equations represents 64. The depletion region or space charge region or
the energy gap (EG) variation of silicon with transition region in a semiconductor p-n junction
temperature (T)? diode has
(IES (EE) - 2006) (GATE (EC) - )
(a) EG  T   2.11  3.60 104 T (a) electrons and holes
(b) positive ions and electrons
(b) EG  T   1.21  3.60 104 T
(c) no ions, electrons or holes
(c) EG  T   1.41  2.23 104 T (d) negative ions and holes

(d) EG  T   0.785  2.23 104 T


65. Germanium and silicon photosensors have their
maximum spectral response in the
62. in a biased step-graded p-n junction, what is the (IES (EC) - 1996)
correct expression for the equilibrium contact
(a) infrared region (b) ultraviolet region
potential (V0)?
(c) visible region (d) X-ray region
(IES (EE) - 2006)

(a) V0  VT ln  N A / N D n i2  66. The allowed energies for the electro system of


an atom are determined using
(b) V0  VT ln  N D / N A n i2 
(IES (EC) - 1996)
(c) V0  VT ln  N D N A / n i2  (a) Einstein’s theory of relativity
(b) Plank’s theory
(d) V0  VT ln  n i2 / N A N D 
(c) Schrodinger’s equation
where VT  T / q. T being the temperature, q (d) Pauli exclustion principle
the electronic charge, NA and ND are the doping
levels of the p and n regions, respectively, and ni,
is the intrinsic carrier concentration 67. Hall effect is observed in a specimen when it

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EDC & ANALOG CIRCUIT

(metal or a semiconductor) is carrying current


(b) given by  i  eni   n   p 
and is placed in a magnetic field. The resultant
electric field inside the specimen will be in
(c) given by  i  eni   n   p 
(IES (EC) - 1996)
(a) a direction normal to both current and (d) given by  i  ni   n   p 
magnetic field
(b) the direction of current
71. The wavelength of light emitted by a GaAs laser
(c) a direction antiparallel to magnetic field is 8670 × 10–10 m. Given
(d) an arbitrary direction depending upon the Plank’s constant = 6.626 × 10–34 Js,
conductivity of the specimen velocity of light = 2.998 × 108 ms–1 and
1eV = 1.602 × 10–19 J, the energy gap in the
GaAs is
68. In a p-type semiconductor, the conductivity due
to holes (   p ) is equal to (e = charge of hole (IES (EC) - 1996)

 p = hole mobility, p = hole concentration) (a) 0.18 eV (b) 0.7 eV


(c) 1.43 eV (d) 2.39 eV
(IES (EC) - 1996)

p.e p 72. For an abrupt junction varactor diode, the


(a)  (b) dependence of device capacitance (C) on
p p.e
applied reverse bias (V) is given by
1
(c) p. e .  p (d) p. e .  (IES (EC) - 1996)
p
(a) C  V1/3 (b) C  V–1/3
(c) C  V1/2 (d) C  V–1/2
69. The minority carrier life-time and diffusion
constant in a semiconducting material are
respectively 100 microsecond and 100 cm²/s. 73. Measurement of Hall coefficient in a semicon-
The diffusion length of the carriers is ductor provides information on the

(IES (EC) - 1996) (IES (EC) - 1996)


(a) 0.1 cm (b) 0.01 cm (a) sign and mass of charge carriers
(c) 0.014 cm (d) 1 cm (b) mass and concentration of charge carriers
(c) sign of charge carriers alone
70. The conductivity of an intrinsic semiconductor is (d) sign and concentration of charge carriers
(symbols have the usual meanings)
(IES (EC) - 1996) 74. If the energy gap of a semiconductor is 1.1 eV,
(a) generally less than that of a doped then it would be :
semiconductor (IES (EC) - 1997)
12
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) opaque to the visible light (b) 4 3 1 2


(b) transparent to the visible light (c) 3 4 1 2
(c) transparent to the ultraviolet radiation (d) 4 3 2 1
(d) opaque to the infrared radiation
77. The carrier mobility in a semiconductor is
75. With increasing temperature, the electrical 0.4 m²/Vs. Its diffusion constant at 300 K will
conductivity would : be (in m²/s)

(IES (EC) - 1997) (IES (EC) - 1998)

(a) increase in metals as well as in intrinsic (a) 0.43 (b) 0.16


semiconductors (c) 0.04 (d) 0.01
(b) increase in metals but decrease in intrinsic
semiconductors 78. At very high temperatures, the extrinsic
(c) decrease in metals but increase in intrinsic semiconductors become intrinsic because
semiconductors
(IES (EC) - 1998)
(d) decrease in metals as well as in intrinsic
semiconductors (a) of drive-in diffusion of dopants and carriers
(b) band to band transition dominates over
impurity ionization
76. Match List-I (Crystal type) with List-II (Name
of the solid) and select the correct answer using (c) impurity ionization dominates over band to
the codes given below the Lists: band transition
(d) band to band transition is balanced by
(IES (EC) - 1998)
impurity ionization
List-I
A. Ionic 79. Which of the following elements act as donor
B. Covalent impurities ?
C. Metallic 1. Gold
D. Van der Wall’s 2. Phosphorus
List-II 3. Boron
1. Solid argon 4. Antimony
2. Copper 5. Arsenic
3. Silicon 6. Indium
4. Sodium chloride Select the correct using the codes given below:
Codes: (IES (EC) - 1998)
A B C D (a) 1, 2 and 3 (b) 1, 2, 4 and 6
(a) 3 4 2 1 (c) 3, 4, 5 and 6 (d) 2, 4 and 5
13
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

80. Consider the following statements regarding a 83. As the temperature of a ‘p’ type semicondutor is
semiconductor : gradually and continuously increased, the Fermi
1. Acceptor level lies close to the valence band level will move

2. Donor level lies close to the valence band (IES (EE) - 1997)
3. n-type semiconductor behaves as a conductor (a) into the valence band
at zero Kelvin. (b) into the conduction band
4. p-type semiconductor behaves as an insulator (c) towards the middle of the forbidden gap
at zero Kelvin.
(d) into the region between the acceptor level
Of these statements: and the valence band.
(IES (EC) - 1998)
(a) 2 and 3 are correct 84. Two initially identical samples A and B of pure
(b) 1 and 3 are correct germanium are doped wit h do nors to
concentrations of 1 × 1020 m–3 and 3 × 1020 m–3
(c) 1 and 4 are correct respectively. If the hole concentration in A is
(d) 3 and 4 are correct 9 × 1012 m–3 , then the hole concentration B at
the same temperature will be

81. In a p-n junction, the space charge capacitance (IES (EE) - 1997)
is proportional to V–n where V is the applied bias (a) 3 × 1012 m–3 (b) 7 × 1012 m–3
voltage and ‘n’ is a constant. The value of ‘n’ for
(c) 11 × 1012 m–3 (d) 27 × 1012 m–3
step linearly graded and diffused junctions would
be respectively.
(IES (EC) - 1998) 85. Consider the following statements :
Pure germanium and pure silicon are example of
1 1 1 1 1 1
(a) , , (b) , and 1. direct band-gap semiconductors
2 3 2.5 3 2 2.5
2. indirect band-gap semicondutor
1 1 1 1 1 1
(c) , and (d) , and 3. degenerate semiconductors
2 2.5 3 3 2.5 2
Of these statements
(IES (EE) - 1997)
82. In switching devices, gold doping is used to
(a) 1 alone is correct (b) 2 alone is correct
(IES (EC) - 1998)
(c) 3 alone is correct (d) 1 and 3 are correct
(a) improve bonding
(b) reduce storage time
86. Silicon carbide reinforced aluminium metal matrix
(c) increase the mobility of the carrier composites find application in
(d) protect the terminals against corrosion.
(IES (EE) - 1997)
(a) the manufacture of transformer cores

14
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(b) the manufacture of cutting tools List - I


(c) the manufacture of standard resistors
(d) aerospace industry EC

EF
A.
87. If an intrinsic semiconductor is doped with a very EV
small amount of boron, then in the extrinsic
semiconductor so formed, the number of electrons
and holes will
EC
(IES (EE) - 1997)
(a) decrease B.
EF
EV
(b) increase and decrease respectively
(c) increase
(d) decrease and increase respectively
EC

88. Consider the following functions :


EF
1. To mask against diffusion or ion implant. C. EV

2. To act as a component is MOS devices.


3. To provide low resistivity paths.
4. To facilitate the entry of dopants
EC
The function of an oxide layer on a silicon wafer EF
would include D. EV

(IES (EE) - 1998)


(a) 1 and 2 (b) 2 and 3 List - II
(c) 3 and 4 (d) 1 and 4 1. Rectifier to n-type
2. Ohmic to n-type
89. Match List - I (Metal - semiconductor band 3. rectifier to p-type
diagram under equilibrium) with list - II (type 4. ohmic to p-type
of contact) and select the correct answer using
codes given below the lists: Codes:

(IES (EE) - 2006) A B C D


(a) 1 4 2 3
(b) 1 4 3 2
(c) 4 1 3 2
(d) 4 1 2 3

15
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

90. The temperature coefficient of resistance of an (b) 4 3 1 2


insulator is (c) 3 4 1 2
(IES (EE) - 1999) (d) 4 3 2 1
(a) positive and independent of temperature
(b) negative and independent of temperature 93. The Hall coefficient of a sample of silicon having
(c) negative and dependent on temperature 1022 arsenic atoms per m³ is
(d) positive and dependent on temperature (IES (EE) - 1999)
(a) 3.49 × 10–3 m³/C
91. If E – EF= 2kT (EF is Fermi energy and ‘k’, the (b) 6.25 × 10–4 m³/C
Boltzmann’s constant is 8.614×10–eVK–1), (c) 1.37 × 10–4 m³/C
then the probability that an electron occupies
an energy level ‘E’ is (d) 2.44 × 10–5 m³/C
(IES (EE) - 1999)
(a) 0.63 (b) 0.5 94. Match List-I (Semiconductor) with List-II
(Band gap in eV) and select the correct answer
(c) 0.27 (d) 0.12 using the codes given below the lists:
(IES (EE) - 1999)
92. Match List-I (Semiconductor property) with List-I List-II
List-II (Type of semiconductor) and select the
correct answer using the codes given below A. Ga As 1. 1.8
the lists: B. In P 2. 1.43
(IES (EE) - 1999) C. In Ca As 3. 1.35
List-I D. Ga Al As 4. 0.75
–1 –1
A. Electron mobility of 0.13 m² V s Codes:
B. p-type A B C D
C. n-type (a) 2 3 1 4
D. Wide band gap (b) 2 3 4 1
List-II (c) 3 2 4 1
1. Germanium doped with arsenic (d) 3 2 1 4
2. Gallium arsenide
3. Silicon 95. The band-gap of a semiconductor is 1.43 eV.
4. Gallium doped silicon Its cut-off wavelength is
Codes: (IES (EE) - 2000)
A B C D (a) 1 μm (b) 0.81 μm
(a) 3 4 2 1 (c) 0.56 μm (d) 0.27 μm

16
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

96. Match List-I (Semiconductor parameters) with 98. Consider the following statements : A tunnel
List-II (Physical processes) and select the diode is
correct answer using the codes given below 1. made of Ge or GaAs.
the lists:
2. an abrupt junction with both sides heavily
(IES (EE) - 2000) doped.
List-I 3. a hyper junction with both sides heavily
A. Impurity concentration doped.
B. Carrier mobility 4. a mojority carrier device.
C. Carrier life time Which of these statements are correct ?
D. Intrinsic carrier concentration (IES (EE) - 2000)
List-II (a) 1 and 2 (b) 3 and 4
1. Recombination (c) 1, 3 and 4 (d) 1, 2 and 4
2. Band to band transition
3. Scattering 99. The sensitivity of a photodiode depends upon
4. Ion implantation (IES (EE) - 2000)
Codes: (a) light intensity and depletion region width
A B C D (b) depletion region width and excess carrier
(a) 3 4 2 1 life time

(b) 4 3 2 1 (c) excess carrier life time and forward bias


current
(c) 3 4 1 2
(d) forward bias current and light intensity.
(d) 4 3 1 2

100. The mobility of electrons in a material is


97. Consider the following types of semiconductors expressed in units of
1. n-type (IES (EE) - 2000)
2. p-type (a) V/s (b) m²/V-s
3. Intrinsic (c) m²/s (d) J/K
4. Extrinsic
Which of these types of semiconductors are
formed by doping germanium with gallium ? 101. Dark current in a semiconductor photo-diode
is
(IES (EE) - 2000)
(IES (EE) - 2011)
(a) 1 and 3 (b) 2 and 4
(a) The forward bias current
(c) 1 and 4 (d) 2 and 3
(b) The forward saturation current

17
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(c) The reverse saturation current 105. The Fermi energy EF of a metal is proportional
to (n is the number of free electrons per unit
(d) The transient current volume of the metal) as
(IES (EE) - 2011)
102. A structure obtained by lightly doped n-drift
1
region between the layers of pn junction a PIN (a) n² (b) n 2
diode is obtained. This structure is effective in:
2 3
(IES (EE) - 2011) (c) n 3 (d) n 2
(a) Making the diode support large reverse
blocking voltages
106. If w is the width of the depletion region in a
(b) Making reverse recovery process slow p-n junction, the transition capacitance is
(c) Making the diode have high on-state proportional to
voltage-drop (IES (EE) - 2011)
(d) Reducing the voltage spike during turn off (a) w (b) w²
due to stray inductance
(c) 1/w (d) 1/w²

103. The Fermi level in an n-type semiconductor at


zero degree Kelvin lies 107. The temperature coefficient of a resistance of
a doped semiconductor is
(IES (EE) - 2011)
(IES (EE) - 2011)
(a) Below the donor level
(a) Always positive
(b) Half-way between the conduction band
and the donor level (b) Always negative

(c) Half-way between the conduction band (c) Zero


and the valence level
(d) Positive or negative depending on the level
(d) Close to the valence band of doping

104. Controlled addition of group III element to an 108. The current flow in a semiconductor is due to
elemental semiconductor results in the formation
of 1. Drift current

(IES (EE) - 2011) 2. Displacement current

(a) Intrinsic semiconductor 3. Diffusion current

(b) n-type semiconductor (IES (EE) - 2011)

(c) p-type semiconductor (a) 1, 2 and 3 (b) 1 and 2 only

(d) Degenerate semiconductor (c) 1 and 3 only (d) 2 and 3 only


18
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

109. If n is the number of electrons per unit volume 113. Given


of the semiconductor and vd is the drift velocity N(E) : Density of states
of the electrons, then the current flowing
through a semiconductor is given by f (E) : Probability that a quantum state with
energy E is occupied by an electron
(IES (EE) - 2012)
Ec : Energy level of conduction band
n
(a) i  v (b) i = n vd 
d The expression  Ec
N(E) f(E) dE gives

vd (IES (EC) - 2012)


(c) i  (d) i  n v1/d 2
n (a) minimum number of electrons in
conduction band

110. The concentration of hole-electron pairs in pure (b) concentration of electrons in conduction
silicon at T = 300 K is 7 × 1015 per cubic meter. band
Antimony is droped into silicon in a proportion (c) energy of electron concentration in
of 1 atom in 107 atoms. Assuming that half of conduction band
the impurity atoms contribute electrons in the
(d) conductivity of electrons in conduction
conduction band, the factor by which the
band
number of charge carries increases due to
doping (the number of silicon atoms per cubic
metre is 5 × 1028) is 114. Hall effect is usefull for the measurement of a
(IES (EC) - 2012) semiconductor’s
(a) 14 × 1015 (b) 0.5 × 1021 (IES (EC) - 2012)
(c) 2.5 × 1021 (d) 1.8 × 105 (a) mobility, carrier concentration and
temperature
(b) type (n - type or p - type), conductivity
111. A potential barrier of 0.50 V exists across a
and temperature
p-n junction. If the depletion region is
5.0 × 10–7 m wide, what is the intensity of the (c) type (n - type or p - type), mobility and
electric field in this region ? carrier concentration
(IES (EC) - 2012) (d) mobility, conductivity and temperature
(a) 1.0 × 106 V/m (b) 2.5 × 10–7 V/m
(c) 2.5 × 107 V/m (d) 2.5 × 108 V/m

112. If the drift velocity of holes under a field gradient


of 200 V/m is 100m/s, their mobility in SI units
is
(IES (EC) - 2012)
(a) 0.5 (b) 0.05
(c) 50 (d) 500
19
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

CONVENTIONAL PROBLEMS Fig. (a)


01. In a semiconductor at room temperature
(300°K), the intrinsic Carrier concentration and
resistivity are 1.5 × 1016 / m³ and 2 × 10³   m
for the extrinsic semiconductor, calculate the
(GATE (EC) - 1990) (10M)
(a) Minority carrier concentration
Fig. (b)
(b) Resistivity of extrinsic semiconductor
03. An n-type silicon sample, having electron mobility
(c) Shift in fermilevel due to doping
 n twice the hole mobility  p , is subjected to a
(d) minority concentration if intrinsic carrier steady illumination such that the electron
concentration doubles concentration doubles from its thermal equilibrium
Assume: value. As a result, the conductivity of the sample
increases by a factor of ____
(i) The mobility of minority and majority carriers
to be the same. (GATE (EC) - 1991) (5M)
(ii) KT = 26mv at room temperature.
04. A P-type silicon sample has a higher conductivity
compared to an n-type silicon sample having the
02. The current I in a forward biased P+ N junction
same dopant concentration
shown in Fig. (a) is entirely due to diffusion of
holes from x = 0 to x = L. The injected hole (True/False)
concentration distribution in the m-region is linear (GATE (EC) - 1994) (1M)
12
10
as shown in Fig. (b), with P(0) = and
cm3
05. Show that the minimum conductivity of an
L = 10–3 cm. extrinsic silicon sample occurs when it is slightly
Determine: P type. Calculate the electron and hole
(a) The current density in the diode assuming that concentration when the conductivity is minimum
the diffusion coefficient of holes is 12 cm²/ Given that n = 1350 cm²/v-sec,
sec.  p = 450 cm²/v-sec, and the intrinsic carrier
(b) The velocity of holes in the n-region at Concentration, ni = 1.5 × 1010 cm–3
x=0
(GATE (EC) - 1994)
(GATE (EC) - 1991)

06. An n-type silicon bar is doped uniformly by


phosphorus ato ms t o a concent ration
4.5 × 1013/cm³. The bar has cross-section of 1
mm² and length of 10cm. It is illuminated uniformly
for region x < 0 as shown in Fig. Assume optical
generation rate 1021 Electron-Hole pairs per cm³

20
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

per second, for this case. The hole lifetime and 09. How does conduction take place in intrinsic
electron lifetime are equal, and equal to 1  sec . semiconductor ?
(GATE (EC) - 1997) Explain with examples. What are the limitations
of intrinsic semiconductors and how are these
taken care of by extrinsic semiconductors ? Show
that the minimum value of conductivity of a
semiconductor with impurity is  min  2neee
Where
ne – concentration of conduction electrons (m–3)
e – electronic charge (C),
 – mobility of electrons (m2 V–1 s–1)
(IES (EE) - 1997)
Evaluate the hole and electron diffusion currents
at x = 34.6  m .
10. What is Hall effect in semi-conductors ? Explain
Following expressions and data can be used in
its origin and significance. Deduce on expression
this evaluation:
for Hall coefficient.
dp dn (IES (EE) - 1998)
J P  qD p ; J n  qDn
dx dx
Where 11. What do you understand by charge carriers ?
Dp = 12 cm²/sec; dn = 30 cm²/sec. Explain the phenomenon of conduction by free
electrons, ions and holes and classify materials
q = 1.6 × 10–19 coloumbs (kt/q) = 26 mV.
accordingly.
(IES (EE) - 1998)
07. Show that a semiconductor has minimum
conductivity at a given temperature when
12. Consider an abrupt p-n junction with donor
n  ni h / e & p  ni e / h density ND = 1017 atoms/cm³ and acceptor
density NA = 0.5 × 1016 atoms/cm³. Sketch
(IES (EC) - 1998) the charge distribution about the junction and
estimate the junction width when
08. A photocathode is illuminated with radiation of (IES (EE) - 1999)
wavelength 500 nm. The cathode has a work (i) no external voltage is applied, (assume the
function of 1.2 eV. Calculate the anode voltage junction barrier voltage to be 0.7 V)
required to produce zero anode current. When
the anode voltage is +90V, find the velocity of (ii) with an external voltage of – 10 V applied.
the electrons at the anode if the cathode is Assume uniform charge distribution on both
illuminated with radiation of wavelength 250 nm. sides of the junction in the space charge region.
(IES (EC) - 1997) Assume an  r of 10 for the material and
 0 = 8.85 × 10–12 F/m
21
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

13. (a) Distinguish between direct and indirect concentration of Si is 1.5 × 102.6.m³ and
bandgap materials with suitable E-k relative permittivity is 11.8.
diagrams.
(b) The bandgap of GaAs and AlAs are
How would you make an intrinsic (GaAs 1.43 ev and 2.16 ev respectively.
sample n-type or p-type ? What happens Assuming the bandgap of AlxGa1–x As to
when GaAs is dopen with Si ? What is vary linearly with x between the two
the nature of bonding in GaAs ? extreme values, find the value of x that
would result in the emission of 680 nm
(a) An n-type Ge sample is 2 mm wide and from Alx Ga1–x As.
0.2 mm thick. A current of 10mA is passed
through the sample (x-direction) and a (IES (EC) - 2011)
magnetic field of 0.1 web/m² is directed
perpendicular to the current flow (z-
direction). The developed Hall voltage is 16. Explain the Hall effect in semiconductors and
1.0 mV. Calculate the Hall coefficient and define Hall constant. What do you mean by
electron concentration negative Hall constant ?
(IES (EE) - 2011)
(IES (EC) - 2011)

17. A semiconductor has a bandgap of 0.62 eV.


14. (a) Derive one-dimensional continuity Find the maximum wavelength for resistance
equation for holes in a semiconductor. change in the material by photon absorption.
Reduce this expression to the standard
diffusion equation by assuming that drift (Note : 1 eV = 1.6 × 10–19 Joules)
is negligible and there is no generation in (IES (EC) - 2012) (5M)
the region.
(b) Obtain expressions for short circuit current 18. Explain the following statement:
and open circuit voltage in an illuminated
p-n junction. Explain how an illuminated The temperature coefficient of resistance in
p-n junctio n can be used as a semiconductors is negative.
photodetector or a photo-cell. (IES (EC) - 2012)
(IES (EC) - 2011)
19. Differentiate between intrinsic and extrinsic
semiconductors, Explain doping
15. (a) An abrut Si p-n junction has (IES (EE) - 2012)
NA = 1023/m³ on p-side and
ND = 1021/m³ on n-side 20. The resistivity of pure germanium at room
temperature is 0.47 ohm-m. Find out the carrier
Calculate the value of the contact potential
density of germanium at room temperature for
and the total width of the depletion region
the electron mobility of 0.42 m²/volt-sec and
under unbiased condition at 300 K.
hole mobility of 0.20 m²/volt-sec. (electron
Derive the relatio ns used in t he
charge e = 1.6 × 10–19C)
computation. The intrinsic carrier
22
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(IES (EE) - 2012)

21. Find the mean velocity of electron flow in a


conductor having a cross-sectional area of
2.1 × 10–6 m² when a current of 20 amperes
flows through it. Assume that there are
8.5 × 1028 electrons/m³ of the material. Charge
on an electron is 1.6 × 10–19 coulombs.
(IES (EE) - 2012)

23
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

ANSWER KEY
01. c 30. b 61. b 92. c
02. c 31. b 62. c 93. b
03. c 32. b 63. d 94. b
04. a 33. c 64. c 95. b
05. b 34. b 65. b 96. c
06. c 35. b 66. b 97. b
07. c 36. d 67. a 98. c
08. c 37. a 68. c 99. b
09. a 38. a 69. a 100. b
10. b 39. d 70. c 101. c
11. a 40. d 71. c 102. b
12. 41. c 72. b
103. a
13. c 42. c 73. d
104.
14. d 43. a 74. a
105.
15. b 44. c 75. c
16. d 45. a 76. d 106.
17. c 46. b 77. d 107.
18. c 47. b 78. b 108.
19. d 48. c 79. d 109.
20. a 49. c 80. c 110. c
19. b 50. a 81. a 111. a
20. c 51. c 82. b 112. a
21. b 52. d 83. b 113. b
22. d 53. d 84. a 114. c
23. b 54. d 85. a
24. d 55. b 86. d
25. a 56. c 87. d
26. d 57. c 88. a
27. b 58. a 89. b
28. a 59. c 90. c
29. c 60. b 91. d

24
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

CHAPTER-2
DIODES
01. For a p-n junction match the type of breakdown KT
with phenomenon (d) V =  Exp  I   1
q 
(GATE (EC) - 1988) (2M)
(1) Avalanche breakdown
03. The switching speed of P+N junction (having a
(2) Zener breakdown heavily doped P region) depends primarily on:
(3) punch through (GATE (EC) - 1989) (2M)
(a) collision of carriers with crystal ions (a) The mobility of minority carriers in the
(b) Early effect P+ -region
(c) Rupture of covalent bond due to strong (b) The lifetime of minority carriers in the
electric field. P+ -region
(a) 1-b ; 2-a ; 3-c (b) 1-c ; 2-a ; 3-b (c) The mobility of majority carriers in the N-
region
(c) 1-a ; 2-b ; 3-c (d) 1-a ; 2-c ; 3-b
(d) The lifetime of majority carriers in the N-
region.
02. In the circuit shown the current voltage
relationship when D1 and D2 are identical is
given by (Assume Ge diodes) 04. In a zener diode.
(GATE (EC) - 1988) (2M) (GATE (EC) - 1989) (2M)
(a) only the P-region is heavily doped.
(b) only the N-region is heavily doped.
(c) both P and N-regions are heavily doped.
(d) both P and N-regions are lightly doped.

05. In a forward biased photo diode, an increase in


incident light intensity causes the diode current
to
KT 1
(a) V= sinh   (GATE (EC) - 1990)
q 2
(a) increase
KT  I  (b) remain constant
(b) V = q ln  I 
 0 (c) decrease
(d) remain constant while the voltage drop across
KT 1 the diode increases
(c) V= sinh 1  
q 2

25
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

06. For the same a.c. voltage and load impedance, 100 mA flows. If the voltage across this
which of the following statements about rectifier combination is instantaneously reversed to
are correct ? 10 V at t = 0, the reverse current that flows
(GATE (EC) - 1990) through the diode at t = 0 is approximately given
by
(a) The average load current in a full-wave
rectifier is twice that in a half-wave rectifier (GATE (EC) - 1992)

(b) The average load current in a full-wave (a) 0 mA (b) 100 mA


rectifier is n times that in a half-wave (c) 200 mA (d) 50 mA
rectifier
(c) Half wave rectifier will have a bigger sized 10. The 6 V zener diode as shown in the circuit
transformer compared to full wave rectifier below, has zero zener resistance and a knee
(d) Half wave rectifier will have a small sized current of 5 mA. Then what is the minimum
transformer compared to a full wave value of R so that the voltage across it does
rectifier. not fall below 6V?
(GATE (EC) - 1992) (IES (EE) - 2009, 2013)
07. In a junction diode
50 
(GATE (EC) - 1990) (1M)
(a) The depletion capacitance increases with
increase in the reverse bias
(b) The depletion capacitance decreases with +
10 V -
6V R

increase in the reverse bias


(c) The depletion capacitance increases with
increase in the forward bias
(d) The depletion capacitance is much higher
than the depletion capacitance when it is (a) 1200 ohms (b) 80 ohms
forward biased. (c) 50 ohms (d) 40 ohms

08. The small signal capacitance of an abrupt P+n 11. In the circuit of Figure, the switch ‘S’ is closed at
junction is 1nf/Cm² at zero bias. If the built-in t = 0 with il (0) = 0 and vc (0) = 0. In the steady
voltage is 1 volt, the capacitance at a reverse state vc equals.
bias voltage of 99 volts is
(GATE (EE) - 1992)
(GATE (EC) - 1991) (2M)
(a) 10 (b) 0.1
(c) 0.01 (d) 100

09. A P - N junction in series with a 100 ohms


resistor, is forward biased so that a current of

26
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) 200 V (b) 100 V


(c) zero (d) – 100 V
(c)

12. An infra-red LED is usually fabricated from


(GATE (EC) - 1992)
(a) Ge (b) Si (d)
(c) Ga As (d) Ga As P.

13. The built-in potential (Diffusion Potential) in a 15. A zener diode works on the principle of
p-n junction
(GATE (EC) - 1995) (1M)
(GATE (EC) - 1993) (2M)
(a) tunneling of charge carriers across the
(a) is equal to the difference in the Fermi-level junction
of the two sides, expressed in volts
(b) thermionic emission
(b) Increases with the increase in the doping
(c) diffusion of charge carriers across the
levels of the two sides
junction
(c) Increases with the increase in temperature
(d) hopping of charge carriers across the
(d) is equal to the average of the Fermi levels junction.
of the two sides.

16. In the circuit of Fig. assume that the diodes


14. The wave shape of V0 in Fig. is are ideal and the meter is an average indicating
ammeter. The ammeter will read
(GATE (EC) - 1996)

(GATE (EC) - 1993)

(a) (a) 0.4 2 A (b) 0.4 A

0. 8 0. 4
(c) A (d)
 

(b)

27
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

17. A zener diode in the circuit shown in Figure, (c) a resistance and an ideal diode in series
has a knee current of 5 mA, and a maximum (d) a resistance.
allowed power dissipation of 300 mW. What
are the minimum and maximum load currents
that can be drawn safely from the circuit, 20. The static characteristic of an adequately
keeping the outout voltage V0 constant at 6V ? forward biased p-n junction is a straight line, if
(GATE (EC) - 1996) the plot is of
(GATE (EC) - 1998) (1M)
(a) logI vs.logV (b) logI vs.V
(c) I vs logV (d) I vs V.

21. A dc power supply has a no-load voltage of


30 V, and a full-load voltage of 25 V at a full-
Load current of 1A. Its output resistance and
(a) 0 mA, 180 mA loads regulation, respectively are
(b) 5 mA, 110 mA (GATE (EC) - 1999)
(c) 10 mA, 55 mA (a) 5 and 20%
(d) 60 mA, 180 mA
(b) 25 and 20%

(c) 5 and16.7%
18. For full wave rectification, a four diode bridge
rectifier is claimed to have the following (d) 25 and16.7%
advantages over a two diode circuit :
1. less expensive transformer,
22. The RMS value of a half-wave rectified
2. smaller size transformer, and symmetrical square wave current of 2A is
3. suitability for higher voltage application. (GATE (EE) - 1999)
(GATE (EC) - 1998) (1M)
(a) 2A (b) 1 A
(a) only (1) and (2) are true
(b) only (1) and (3) are true (c) 1/ 2 A (d) 3A
(c) only (2) and (3) are true
(d) (1), (2) as well as (3) are true 23. For the circuit in Fig. the voltage v0 is
(GATE (EC) - 2000)
19. For small signal ac operation, a practical
forward biased diode can be modelled as
(GATE (EC) - 1998) (1M)
(a) a resistance and a capacitance in series
(b) an ideal diode and resistance in parallel.
28
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) 2V (b) 1 V 26. In the figure, silicon diode is carrying a constant


(c) – 1V (d) None of above current of 1 mA. When the temperature of the
diode is 20°C, VD is found to be 700 mV. If
the temperature rises to 40°C, VD becomes
24. A diode whose terminal characteristics are approximately equal to

V  (GATE (EC) - 2002)


related as ip = Is  V  , where Is is the reverse
 T +
saturation current and VT is the thermal voltage
(= 25 mV) is biased at ID = 2 mA. Its dynamic
resistance is
V0
(GATE (EE) - 2000)
(a) 25 ohms (b) 12.5 ohms
(c) 50 ohms (d) 100 ohms –

(a) 740 mV (b) 660 mV


25. A Zener diode regulator shown in the figure
given below is to be designed to meet the (c) 680 mV (d) 60 pA
following specifications:

R I =10 mA
L
27. The forward resistance of the diode shown in
+
400 0k figure is 5  and the remaining parameters are
same as those of an ideal diode. The dc
component of the source current is
Vin D
Z V 0
(GATE (EE) - 2002) (IES (EE) - 2009)

IL  10 mA, V0  10 V, Vin varies from 30 V


to 50 V. The zener diode has Vz  10V and
Izk (Knee current)=1 mA. For satisfactory
operation, which one of the following is correct? Vm Vm
(a) 50  (b) 50  2
(GATE (EC) - 2002) (IES (EE) - 2007)
(a) R  1800 Vm 2 Vm
(b) 2000  R  2200 (c) 100  2 (d) 50 

(c) 3700  R  4000


(d) R  4000 28. The cut in voltage of both zener diode Dz and
diode D shown in figure is 0.7 V, while break
29
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

down voltage of Dz is 3.3 V and reverse break- Codes:


down voltage of D is 50 V. The other P Q R S
parameters can be assumed to be the same as
those of an ideal diode. The values of the peak (a) 1 2 4 3
output voltage (V0) are (b) 2 3 1 4
(GATE (EE) - 2002) (IES (EE) - 2009) (c) 3 4 1 2
(d) 4 1 4 3

30. At 300 K, for a diode current of 1 mA, a certain


germanium diode requires a forward bias of
0.1435 V, whereas a certain silicon diode
requires a forward bias of 0.718 V. Under the
co ndit ions stated above, t he closest
approximation of the ratio of reverse saturation
(a) 3.3 V in the positive half cycle and 1.4 V current in germanium diode to that in silicon
in the negative half cycle diode is
(b) 4 V in the positive half cycle and 5 V in (GATE (EC) - 2003)
the negative half cycle
(a) 1 (b) 5
(c) 3.3 V in both positive and negative half
cycles (c) 4  103 (d) 8  103
(d) 4 V in both positive and negative half cycle.
31. Choose proper substitutes for X and Y to make
29. Match items in Group 1 with items in Group 2, the following statement correct Tunnel diode
most suitably. and Avalanche photodiode are operated in X
bias and Y bias respectively
(GATE (EC) - 2003)
(GATE (EC) - 2003)
Group1
(a) X: reverse, Y:reverse
P. LED
(b) X: reverse, Y:forward
Q. Avalanche photodiode
(c) X: forward, Y- reverse
R. Tunnel diode
(d) X: forward, Y- forward
S. LASER
Group 2
32. A particular green LED emits light of
1. Heavy doping wavelength 5490 A. The energy bandgap of
2. Coherent radiation the semiconductor material used there is
3. Spontaneous emission (Planck’s constant  6.626  1034 J-s)

4. Current gain (GATE (EC) - 2003)


(a) 2.26 eV (b) 1.98 eV
(c) 1.17 eV (d) 0.74 eV
30
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

33. The circuit shown in the figure is best described 500 mA. Assuming that the Zener diode is ideal
as a (i.e, the Zener knee current is negligibily small
(GATE (EC) - 2003) (1M) and Zener resistance is zero in the breakdown
region), the value of R is
(GATE (EC) - 2004)
R

Output +

~ 12 V

-
5V
Variable Load
100 to 500 mA

(a) Bridge rectifier


(b) ring modulator (a) 7 (b) 70
(c) frequency discriminator
70
(c)  (d) 14
(d) Voltage doubler 3

34. A voltage signal 10 sin t is applied to the circuit 36. Assuming that the diodes are ideal in figure,
with ideal diodes, as shown in figure. The the current in diode D 1 is
maximum and minimum values of the output
waveform Vout of the circuit are respectively. (GATE (EE) - 2004) (2M)
1 K 1 K
(GATE (EE) - 2003) (2M)
10 K
+ D1 D 2

IZ

5V
+
V in Vout
8V
4V 4V
-

10 K

- (a) 8 mA (b) 5 mA

(a) + 10 V and -10 V (c) 0 mA (d) -3 mA

(b) + 4 V and -4 V
(c) + 7 V and -4 V 37. In a full-wave rectifier using two ideal diodes,
Vdc and Vm are the dc and peak values of the
(d) + 4 V and -7 V voltage respectively across a resistive load. If
PIV is the peak inverse voltage of the diode,
then the appropriate relationships for this rectifier
35. In the Voltage regulator shown in the figure, are
the load curent can vary from 100 mA to
(GATE (EC) - 2004)
31
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Vm (a) 23.7 mA (b) 14.2 mA


(a) Vdc  , PIV  2Vm
 (c) 13.7 mA (d) 24.2 mA

Vm
(b) Vdc  2 , PIV  2Vm 40. A Silicon PN junction diode under reverse bias

has depletion region of width 10m .The relative
Vm
(c) Vdc  2 , PIV  Vm permittivity of Silicon,  r  11.7 and the

permittivity of free space 0  8.85  1012 F / m.
Vm The depletion capacitance of the diode per square
(d) Vdc  , PIV  Vm
 meter is
(GATE (EC) - 2005)
38. The current through the Zener diode in figure is (a) 100F (b) 10F
(GATE (EE) - 2004) (1M)
(c) 1F (d) 20F
2.2 K
R = 0.1 K
Z

41. Assume that D1 and D2 in figure are ideal


+
diodes. The value of current is
IZ

10 V
R 1 3.5 V (GATE (EE) - 2005) (1M)
-

V = 3.3 V
Z
D1

2 K
(a) 33 mA (b) 3.3 mA 1 mA
(DC)
(c) 2 mA (d) 0 mA I
2 K
D2

39. The zener diode in the regulator circuit shown


in the figure has a Zener voltage of 5.8 volts (a) 0 mA (b) 0.5 mA
and a Zener knee current of 0.5 mA. The
maximum load current drawn from this circuit (c) 1 mA (d) 2 mA
ensuring proper functioning over the input
voltage range between 20 and 30 volts, is
42. In the circuit shown below, the switch was
(GATE (EC) - 2005) connected to position 1 at t < 0 and at t = 0, it
is changed to position 2. Assume that the diode
1 K has zero voltage drop and a storage time ts.
For 0  t  t s , VR is given by (all in Volts)
Vi (GATE (EC) - 2006)
20-30 V1=5.8 V Load

32
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

1 Codes:
+
E F G H
2
(a) 4 2 1 3
(b) 2 4 1 3
1K VR

5V 5V (c) 3 4 1 2
(d) 1 3 2 4

-
45. For the circuit shown below, assume that the
(a) VR  5 (b) VR  5 zener diode is ideal with a breakdown volatge
of 6 volts. The waveform observed across R is
(c) 0  VR  5 (d) 5  VR  0
(GATE (EC) - 2006)

43. The value of voltage (V0) across a tunnel-diode +


corresponding to peak and valley currents are
Vp and Vv respectively. The range of tunnel-diode
voltage VD for which the slope of its I – VD
characteristics is negative would be R V R

(GATE (EC) - 2006) 12 sin  t

(a) VD < 0 (b) 0 < VD < Vp


-
(c) Vp < VD < Vv (d) VD > Vv

6V

44. Find the correct match between Group 1 and (a)


Group 2
Group 1 6V

E. Varactor diode (b)


F. PIN diode -1 2 V

G. Zener diode
H. Schottky diode 12 V

Group 2 (c)
1. Voltage reference -6 V

2. High - frequency switch


3. Tuned circuits
46. What are the states of the three ideal diodes of
4. Current controlled attenuator the circuit shown in figure?
(GATE (EC) - 2006)(IES (EC) - 2012) (GATE (EE) - 2006) (1M)

33
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

1
V0

1

D2

D1 1 D3
(b) 5
5V

10 V 5 Vi

(a) D1 ON, D 2 OFF, D3 OFF


V0
(b) D1 OFF, D2 ON, D3 OFF
(c) D1 ON, D 2 OFF, D3 ON
10
(d) D1 OFF, D 2 ON, D3 ON
(c) 5

47. Assuming the diodes D1 and D2 of the circuit 5


10 Vi

shown in figure to be ideal ones, the transfer


characteristics of the circuit will be
V0
(GATE (EE) - 2006) (2M)

D1 V0 10
2 (d)
8

RL=
10 Vi

10 V 5V

48. In a p+ n junction diode under reverse bias,


the magnitude of electric field is maximum at
V0 (GATE (EC) - 2007)
(a) the edge of the depletion region on the p-
side
(a) 10 (b) the edge of the depletion region on the n-
side
(c) the p+ n junction
10 Vi (d) the centre of the depletion region on the n-
side

34
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

49. Group I lists four types of p-n junction diodes. (c) 7.14 to 7.43 V (d) 7.29 to 7.43 V
Match each device in Group 1 with one of the
options in Group II to indicate the bias
condition of that device in its normal mode of 51. The correct full wave rectifier circuit is
operation. (GATE (EC) - 2007) (1M)
(GATE (EC) - 2007)
Group 1
P. Zener Diode
Q. Solar cell
(a) Input

R. LASER diode
Output

S. Avalanche photodiode
Group 2
1. Forward bias
2. Reverse bias
Codes:
In put

P Q R S
(b) Output

(a) 1 2 1 2
(b) 2 1 1 2
(c) 2 2 2 1
(d) 2 1 2 2

Input
50. For the Zener diode shown in the figure, the
Zener voltage at knee is 7 V, the knee current (c) Output

is negligible and the Zener dynamic resistance


is 10  . If the input voltage (Vi ) range is from
10 to 16 V, the output voltage (V0 ) ranges from

(d) In put

O utput

(GATE (EC) - 2007)


(a) 7.00 to 7.29 V (b) 7.14 to 7.29 V
35
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

52. In the following limiter circuit, an input voltage + - + -

(a) + -
Vi  10 sin 100t is applied. Assume that the
diode drop is 0.7 V when it is forward biased.
The Zener breakdown voltage is 6.8 V.
10 k
10 sin out V 0

1K
D1
(b)
~ 5V

If such a diode is used in clipper circuit of figure


V V
i 0
given above, the output voltage  V0  of the
circuit will be
Z 6.8 V
(GATE (EE) - 2008) (1M)

The maximum and minimum values of the output


voltage respectively are
(GATE (EC) - 2008) +5 V

(a) 6.1 V, -0.7 V (b) 0.7 V, -7.5 V


(a) 0  
t
(c) 7.5 V, - 0.7 V (d) 7.5 V, -7.5 V
-5 V

53. Consider the following assertions.


S1: For Zener effect to occur, a very abrupt
juncton is required
S2: For quantum tunneling to occur, a very 10 V
narrow energy barrier is required.
Which of the following is correct? (b) 0  
t

(GATE (EC) - 2008) -5 V

(a) only S2 is true


(b) S1 and S2 are both true but S2 is not a
reason for S1
(c) S1 and S2 are both true and S2 is a reason
for S1 +5.7 V

(d) Both S1 and S2 are false (c) 0  


t

-1 0 V

54. The equivalent circuits of a diode, during


forward biased and reverse biased conditions,
are shown in the figure

36
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

+ V-

1 1

+5.7 V

(d) 0  
t +
V i 1A
-
-1 0 V

55. In the voltage doubler circuit shown in the (a) min  Vi ,1 (b) max  Vi ,1
figure, the switch ‘S’ is closed at t = 0.
Assuming diodes D1 and D2 to be ideal, load (c) min  Vi ,1 (d) max  Vi ,1
resistance to be infinite and initial capacitor
voltages to be zero. The steady state voltage
across capacitors C1 and C2 will be 57. The following circuit has a source voltage Vs
as shown in the graph. The current through the
(GATE (EE) - 2008) (2M) cicuit is also shown

l a b
l

+ R 10 K
VS
-

(a) VC1  10V , VC2  5V


15
(b) VC1  10V , VC2  5V
10

5
(c) VC1  5V , VC2  10 V
VS(Volts)

-5
(d) VC1  5V , VC2  10 V
-10

-15
0 100 200 300 400
56. In the circuit below, the diode is ideal. The
voltage V is given by 1.5

(GATE (EC) - 2009) 1


Current (mA)

0.5

-0.5

-1

-1.5
0 100 200 300 400

37
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

The element connected between a and b could


be
(GATE (EE) - 2009) (1M)
(a) l a b
l

(b) l a b
l

(c) l a b
l

59. The bias current IDC through the diodes is


(d) l a b
l
(GATE (EC) - 2011)
(a) 1 mA (b) 1.28 mA
(c) 1.5 mA (d) 2 mA
58. Assuming that the diodes in the given circuit
are ideal, the voltage V0 is
(GATE (EE) - 2010) 60. The ac output voltage vac is
(GATE (EC) - 2011)
10 k  (a) 0.5 cos (  t ) mV (b) 1 cos (  t ) mV
(c) 2 cos (  t ) mV (d) 22 cos (  t ) mV
10 k

10 V V0 61. A Zener diode, when used in voltage


15 V stabilization circuit, is biased in
10 k (GATE (EC) - 2011)
(a) reverse bias region below the breakdown
voltage
(b) reverse breakdown region
(a) 4V (b) 3 V
(c) forward bias region
(c) 7.5 V (d) 12.12 V
(d) forward bias constant current mode

Statement for Linked Answer 59 and 60


62. A clipper circuit is shown below.
In the circuit shown below, assume that the
voltage drop across a forward biased diode is
kT
0.7 V. The thermal voltage VT   25 mV .
q
The small signal input vi = Vp cos (  t ) where
Vp = 100 mV.

38
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Assuming forward voltage drops of the diodes 63. The diodes and capacitors in the circuit shown
to be 0.7 V, the input-output transfer are ideal. The voltage v(t) across the diode D1
characteristic is is
(GATE (EE) - 2011) (GATE (EC) - 2012) (1M)

(a)

(a) cos   t   1 (b) sin  t 

(c) 1  cos  t  (d) 1  sin   t 


(b)

64. The i-v characteristic of the diode in the circuit


given below are

 v  0.7
 A, v  0.7 V
i   500
 0 A, v  0.7 V

(c)

(d) The current in the circuit is


(GATE (EE) (EC) - 2012)
(a) 10 mA (b) 9.3 mA
(c) 6.67 mA (d) 6.2 mA

39
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

65. In a forward biased pn junction, the sequence


of events that best describes the mechanism of
current flow is
(GATE (EC) - 2013)
(a) injection, and subsequent diffusion and
recombination of minority carriers
(a) sint
(b) injection and subsequent drift and
generation of minority carriers
(b)  sin t  sin t  / 2
(c) extraction, and subsequent diffusion and
generation of minority carriers (c)  sin t  sin t  / 2
(d) extraction, and subsequent drift and
recombination of minority carriers (d) 0 for all t

66. In the circuit shown below, the knee current of 68. Match list I-V characteristics given below with
the ideal Zener diode is 10mA. To maintain 5V Gunn diode, Photo diode and Tunnel diode.
across RL. the minimum value of RL in  and (IES (EE) - 2006)
the minimum power rating of the Zener diode
in mW respectively, are I

(GATE (EC) - 2013) Non -exponential

V
A.

Exponential

(a) 125 and 125 (b) 125 and 250 V


B.
(c) 250 and 125 (d) 250 and 250

67. A voltage 1000 sin t volts is applied across


YZ. Assuming ideal diodes, the voltage I
measured across WX in volts, is
Ex ponential
(GATE (EC) - 2013)
V
C.

40
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Select the correct answer using the code given 71. Intermediate (l) layer of PIN - diode imparts
below: which one of the following features to a pn
Gunn Photo Tunnel junction diode?

diode diode diode (IES (EE) - 2007)

(a) A B C (a) High reverse blocking capability

(b) B A C (b) High forward current rating

(c) A C B (c) Inverting capability

(d) B C A (d) Poor turn off performance

69. In a single phase full wave controlled bridge 72. In the circuit given below , D1 and D 2 are ideal.
rectifier, minimum output voltage and maximum Which one of the following represents the
output voltage are obtained at which conduction transfer characteristics of the circuit?
angles? (IES (EE) - 2007)
(IES (EE) - 2007)
D
1

(a) 0o , 180o respectively

(b) 180o ,0o respectively D 2

6 K

(c) 0o , 0o respectively V in V
out
4 K

(d) 180o ,180o respectively 10 V 5V

70. For a half-wave rectifier, what is the output dc


voltage? (with peak voltage = Vm, dc current V0

= IDC and forward resistance of diode = Rf)


10 V
(IES (EE) - 2007)

Vm (a)
(a) VDC   I DC R f

10 V Vi

Vm
(b) VDC  V 0

Vm
(c) VDC   I DC R f

(b)
Vm
(d) VDC  0.707  I DC R f 5V

 5V V
i

41
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

V 0

75. What is the peak current through the resistor in


the circuit given below assuming the diode to
10 V be ideal?
(IES (EE) - 2008)
(c) 5V

1 K

5V 10 V V
i

V 0

+
12 sin t ~ -
4V
10 V

(d)
(a) 4 mA (b) 8 mA
10 V Vi (c) 12 mA (d) 16 mA

73. Find the break region (Voltage range) over 76. For a rectifier circuit, percentage voltage
which the dynamic resistance of a diode is regulation is equal to which one of the following?
multiplied by a factor of 1000. Let this region
be contained between V 1 and V 2, then (IES (EE) - 2008)

V1  V2 is given by Vno load  Vfull load


(a) 100
(IES (EE) - 2005) Vno load

(a) log C 1000VT  Vno load  Vfull load


(b) 100
Vfull load
(b) 1000VT

(c)  log 10  V3 Vno load  Vfull load


e T
(c) 100
Vno load  Vfull load
(d) The value cannot be computed with the
given data
Vfull load
(d) 100
Vno load
74. In a bridge a.c. to d.c. converter using p-n
diodes, if the input voltage is V sin t, What is
peak inverse voltage across diode? 77. In the circuit given below the Zener diode D1
(IES (EE) - 2006) has a reverse breakdown voltage of 100 V and
(a) V (b) 2 V reverse saturation current of 25A . The
corresponding values for D2 are 50 V and
(c) V/2 (d) V / 2 50A . What is the current in the circuit?
(IES (EE) - 2008)

42
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Codes:
A B C D
(a) 3 4 5 2
(b) 2 5 1 3
(c) 3 5 1 2
(d) 2 4 5 3

79. In the circuit shown below, the average value


of V0 (t) will be
+ -
(IES (EE) - 2002)
40 V

(a) 25 A anticlockwise
+
(b) 25 A clockwise

(c) 50 A anticlockwise
C V (t)
0

(d) 50 A clockwise
~ V sin t
m

78. Match List - I (Type of device) with List - II -


(Characteristics / Application) and select the
correct answer using the codes given below
(a) 0 (b) Vm / 
the lists:
(IES (EE) - 2005) (c) Vm / 2 (d) Vm
List - I
A. Zener diode 80. In the circuit shown below, the average value
B. Tunnel diode of V0(t) will be
C. Schottky diode (IES (EE) - 2002)
D. Photo diode
List - II
1. Display panel V (t)
0

2. Voltage reference
3. Light detection
~ V sin t
m

4. Negative resistance
5. High frequency switching a) 0 (b) Vm / 

(c) Vm / 2 (d) Vm

43
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

81. Which one of the following statements is (a) Vm /  R L  R f 


correct?
An ideal regulated power supply should have (b) Vm /  R f  R L 
(IES (EE) - 2004)
(c) 2Vm / 
(a) 100% regulation (b) 50 % regulation
(c) 0% regulation (d) 75 % regulation (d) Vm /  2 RL  Rf  
82. Which one of the following statements is
85. Match List - I (Type of Diode) with List - II
correct?
(Characteristic / Applications) and select the
A photodiode works on the principle of correct answer using he code given below the
(IES (EE) - 2004) lists:

(a) photo-voltaic effect (IES (EE) - 2006)

(b) photo-conductive effect List -I

(c) photo-electric effect A. Tunnel diode

(d) photo-electric effect B. Zener diode


C. Photodiode

83. In a centre tap full wave rectifier, 100V is the D. Schottky diode
peak voltage between the centre tap and one List - II
end of the secondary. What is the maximum
1. Reverse current varies directly with the
voltage across the reverse biased diode?
amount of light
(IES (EE) - 2005)
2. Exhibits negative resistance region in its
(a) 200V (b) 141 V I-V charcteristics
(c) 100V (d) 86 V 3. Uses only majority carriers and is intended
for high frequency operations

84. Consider the circuit given below where R1 is 4. Silicon p-n junction diode that is desgined
for limiting the volatge across the terminals
the diode forward resistance and R L the load
in reverse bias
resistance
Codes:
What is the average rectified current equal to?
A B C D
(IES (EE) - 2006)
(a) 2 3 1 4
Rf
(b) 1 4 2 3
(c) 2 4 1 3
V sin t R Output
m L
(d) 1 3 2 4

44
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

86. What is the reverse recovery time of a diode 89. Bridge rectifiers are preferred because
when switched from forward bias VF to reverse (IES (EE) - 2001)
bias VB ?
(a) they require small transformer
(IES (EE) - 2005)
(b) they have less peak inverse voltage
(a) Time taken to remove the stored minority
carriers (c) they need small transformer and also have
less peak inverse voltage
(b) Time taken by the diode voltage to attain
zero value (d) they have low ripple factor
(c) Time to remove stored minority carriers
plus the time to bring the diode voltage to 90. Consider the following statements in connection
reverse bias VR with the biasing of semi-conductor diodes:
(d) Time taken by the diode current to reverse 1. LEDs are used under forward-bias
condition
87. The reverse saturation current of a Si-biased 2. Photodiode are used under forward bias
p-n junction diode increases 32 times due to a condition
rise in ambient temperature. If th original 3. Zener diodes are used under reverse-bias
temperature was 40°C, what is the final condition
temperature?
4. Variable capacitance diodes are used
(IES (EE) - 2006) under reverse - bias condition
(a) 90°C (b) 72°C Which of these statements are correct?
(c) 45°C (d) 50°C (IES (EE) - 2002)
(a) 1, 2 and 3 (b) 1, 2 and 4
88. Consider the following statements about a (c) 2, 3 and 4 (d) 1, 3 and 4
Tunnel diode?
(IES (EE) - 2009)
91. In the single phase diode bridge rectifier shown
1. Tunnelling takes place at a speed decided in Figure, the load resistor is R=50  . The
by junction temperature
source voltage is v = 200 sin t  , where
2. Concentration of impurities is of the order
of 1 part in 10³   2  50 radians per second. The power
dissipated in the load resistor R is
3. Both tunneling curent and normal pn
junction injection current exist
4. Tunnel dio de exhibits resistance
characteristic only
Which of these statements is / are correct?
(a) 1 only (b) 1 and 2
(c) 2 and 3 (d) 3 and 4

45
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

3200 400 (a) Zero (b) –E + E sin t


(a) W (b) W
  (c) E – E sin t (d) Half sinusoids
(c) 400 W (d) 800 W
95. In the circuit shown in the figure, if e1 = 2V,
e2 = 1V and e3 = 1V and E = 2V, then which
92. The diode “D” is ideal in the network shown in
one of the diodes will be conducting and what
the figure below. The current “I” will be
will be the e0
(IES (EC) - 1998)

(a) – 5 mA (b) zero


(c) 2 mA (d) 4 mA

(a) D3 ; 1V (b) D1 ; 2V
93. In the circuit of Figure, the current ip through
the ideal diode (zero cut in voltage and forward (c) D2 ; 5V (d) D1 ; 5V
resistance) equals

96. The circuit shown in the figure has a Zener


regulated dc power supply. Assuming that the
Zener diode is ideal, the MINIMUM value of
Rl down to which the output voltage would
remain constant is

(a) 0 A (b) 4 A (IES (EE) - 1997)


(c) 1 A (d) None of above

94. In the circuit given, the voltage across the diode


(assumed to be an ideal one) is : (a) 15 ohms (b) 24 ohms
(IES (EC) - 1998) (c) 27 ohms (d) 45 ohms

97. For the given input, the ouput waveform across


the diode shown in the figure will be:
(IES (EE) - 1997)

46
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(IES (EE) - 1998)

(a)

(b) (a) 28.28 V (b) 20 V


(c) 17.98 V (d) 14.12 V

100. A cliping circuit is shown in the given figure. Its


(c)
transfer characteristic will be shown in
(IES (EE) - 1998)

(d)

98. The voltage at V1 and V2 of the arrangement


shown in the figure will be respectively
(IES (EE) - 1998)

(a)

(b)

(a) 6 V and 5.4 V (b) 5.4 V and 6 V


(c) 3 V and 5.4 V (d) 6 V and 3 V

99. For the full-wave rectifier shown in the figure,


the rms voltage across each diode will be (c)
(assume the diodes and the transformer to be
ideal)
47
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(c) 4 1,2,4 1 3
(d) 3 1,2,4 4 1

(d) 103. The piece-wise linear V-I characteristic of a diode


is shown in the given figure. When the applied
voltage is 6 V, the current through the diode will
be

101. The diffusion capacitance of a forward biased (IES (EC) - 1996)


p+ n junction diode with a steady current I depends
on
(IES (EE) - 2002)
(a) width of the depletion region
(b) mean lifetime of the holes
(c) mean lifetime of the electrons
(a) 42 mA (b) 48 mA
(d) junction area
(c) 51 mA (d) 54 mA

102. Match List-I (Device) with List-II (Property/use)


104. Which of the following characteristic of a silicon
and select the correct answer using the codes
p-n junction diode make it suitable for use as an
given below the lists:
ideal diode ?
(IES (EC) - 1996) 1. It has very low saturation current.
List-I 2. It has a high value of forward cut-in voltage
A. Zener diode 3. It can withstand large reverse voltage
B. Tunnel diode 4. When compared with germanium diodes,
C. Gunn diode silicon diodes show a lower degree of
temperature dependence under reverse bias
D. PIN diode conditions.
List-II Select the correct answer using the codes given
1. High speed switching below :
2. Multivibrator circuits (IES (EC) - 1997)
3. Voltage stabilizer (a) 1 and 2 (b) 1, 2, 3 and 4
4. Microwave oscillator (c) 2, 3 and 4 (d) 1 and 3
Codes:
A B C D 105. In the rectifier circuit shown above, what should
(a) 3 1,2 4 1 be minimum peak-inverse-voltage (PIV ) rating
of the diode?
(b) 4 2,4 4 1
(IES (EE) - 2005)
48
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

D 2
+ Pdc  I rms 
(a) Pac (b)   1
220 V C  I dc 
50Hz 12 V VDC

- 2
 I dc  I dc
(b)   1 (d) I rms
 I rms 
(a) 12V (b) 12 2V

(c) 24 V (d) 24 2V 109. Consider the following statements:


A clamper circuit
106. For an input of Vs = 5 sin ωt , (assuming ideal 1. adds or subtracts a dc voltage to or from
diode) circuit shonw in the figure will behave a waveform
as a 2. does not change the shape of the
(IES (EC) - 1997) waveform
3. amplifies the waveform
Of these statements
(IES (EC) - 1996)
(a) 1 and 2 are correct
(b) 1 and 3 are correct
(c) 2 and 3 are correct
(a) clipper, sine wave clipped at – 2V (d) 1, 2 and 3 are correct
(b) clamper, sine wave clamped at – 2V
(c) clamper, sine wave clamped at zero volt 110. A 5V reference is drawn from the circuit shown
in the figure. If the zener diode is of 5 mW and
(d) clipper, sine wave clipped at 2 V
5V, then RZ will be
(IES (EE) - 1999)
107. If the input ac is 10V rms, the maximum voltage
that will appear across the diode of a half-wave
rectifier with a capacitor input filter will be
(IES (EC) - 1997)
(a) 10 V (b) 14 V
(c) 20 V (d) 28 V

108. The ripple factor of a power supply is given by


(symbols have the usual meaning) (a) 50  (b) 500 
(IES (EC) - 1998) (c) 5000  (d) 50000 
49
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

111. A voltage of 200cos100t is applied to half-


wave rectifier with a load resistance of 5 k .
The rectifier is represented by an ideal diode in
series with a resistance of 1k . The maximum (a)
value of current, dc component of current and
rms value of current will be respectively
(IES (EE) - 1999)
(a) 33.33 mA, 10.61 mA and 16.67 mA
(b) 22.22 mA, 8.61 mA and 12.38 mA
(b)
(c) 28.33 mA, 14.61 mA and 13.33 mA
(d) 40 mA, 20 mA and 25 mA

112. The transition capacitance of a diode is 1nF


and it can withstand reverse potential of
400 V. A capacitance of 2nF which can
withstand a reverse potential of 1 kV is
obtained by connecting (c)

(IES (EE) - 1999)


(a) two 1 nF diodes in parallel
(b) six parallel branches with each branch
comprising three 1 nF diodes in series
(c) two 1 nF diodes in series
(d) three parallel branches with each branch (d)
comprising six 1 nF diodes in series

113. If a sinusoidal input is applied to the circuit


shown in the given figure, the output waveform 114. If Vm is peak value of an applied voltage in a
of V0 will be half-wave rectifier with a large capacitor across
(IES (EE) - 2000) the load, then the peak inverse voltage will be
(IES (EE) - 2000)
(a) Vm / 2 (b) Vm
(c) 2 Vm (d) 2 Vm

115. The ratio of available power from the dc


component of a full-wave rectified sinusoid to
the available power of the rectified sinusoid is

50
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(IES (EC) - 1999) 2. Full-wave rectifier without filter.


(a) 8 /  (b) 2 3. Full-wave rectifier with series inductance
filter.
(c) 4 /  (d) 8 /  2
4. Full-wave rectifier with capacitance filter.
The sequence of these rectifier circuits in
116. Consider the following statements in relation decreasing order of their ripple factor is
to a large value of capacitor filter used in a full-
(IES (EC) - 2001)
wave rectifier.
(a) 1, 2, 3, 4 (b) 3, 4, 1, 2
It gives the
(c) 1, 4, 3, 2 (d) 3, 2, 1, 4
1. low conduction period for the diode
rectifier
2. increased peak current rating of the diode 119. The use of a rectifier filter in a capacitor circuit
gives satisfactory performance only when the
3. large peak inverse voltage rating of the
load
diode.
(IES (EC) - 2001)
Which of these statements are correct ?
(a) current is high (b) current is low
(IES (EC) - 2000)
(c) voltage is high (d) voltage is low
(a) 1, 2 and 3 (b) 2 and 3
(c) 1 and 2 (d) 1 and 3
120. The PIV rating of the diodes used in power
supply circuits are chosen by which one of the
117. Consider the following statements : following creteria ? (Vm is the peak input supply
The function of bleeder resistance in filter circuit voltage to the rectifier circuit used in the power
is to supply)

1. maintain minimum current necessary for (IES (EC) - 2002)


optimum inductor filter operation. (a) The diodes that are to be used in a full
2. work as voltage divider in order to wave rectifier should be rated 2 Vm and
provide variable output from the supply. in bridge rectifier equal to Vm

3. provide discharge to capacitors so that (b) The diodes that are to be used in a full
output becomes zero when the circuit has wave rectifier should be rated Vm and in
been de-energised. bridge rectifier equal to 2 Vm

Which of these statements are correct ? (c) All diodes should be rated for Vm only

(IES (EC) - 2001) (d) All diodes should be rated for 2 Vm

(a) 1 and 2 (b) 2 and 3


(c) 1 and 3 (d) 1, 2 and 3 121. For a full-wave rectifier with shunt capacitor
filter, the peak to peak ripple voltage is
(IES (EC) - 2003)
118. Consider the following rectifier circuits :
1. Half-wave rectifier without filter.
51
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

125. Select the correct output (Vo) wave-shape for


2I DC IDC
(a) (b) a given input (Vi) in the clamping network given
fC fC below :
IDC IDC (IES (EC) - 2005)
(c) 2f C (d) 4f C

(where f = fundamental power line frequency.


IDC = DC current)

122. The average value of the full-wave rectified sine


wave with period π , and a peak value of Vm is
(IES (EC) - 2003)
(a) 0.707 Vm (b) 0.500 Vm (a) (b)
(c) 0.637 Vm (d) 0.318 Vm

123. Consider the following circuit:


(c) (d)

126. A half-wave rectifier having a resistance load


For the circuit shown above, which one of the of 1k rectifies an a.c. voltage of 325 V peak
following is a correct statement ? value and the diode has a forward resistance
(IES (EC) - 2004) of 100  . What is the RMS value of the
current?
(a) D2 does not conduct for any value of Vi
(IES (EC) - 2005)
(b) Vo = 10 V for all values of Vi > 10 V
(a) 295.4 mA (b) 94.0 mA
(c) Vo = 0 V for all values of Vi > 0 V
(c) 147.7 mA (d) 208.0 mA
(d) Vo = 10 V for all values of Vi > 0 V

127. In the given circuit D1 is an ideal germanium


124. In a half-wave rectifier, if an a.c. supply is
diode and D2 is a silicon diode having its cut-in
60 Hz, then what is the a.c. ripple at output ?
voltage as 0.7 V, forward resistance as 20 
(IES (EC) - 2005)
and reverse saturation current (Is) as 10 nA.
(a) 30 Hz (b) 60 Hz What are the values of I and V for this circuit,
(c) 120 Hz (d) 15 Hz respectively ?
(IES (EC) - 2006)

52
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) 60 mA and 0 V (a) Bridge rectifier (b) Voltage doubler


(b) 50 mA and 0 V (c) Rectifer with filter (d) Comparator
(c) 53 mA and 0.7 V
(d) 44 mA and 1.58 V 131. The figure given below shows the transfer
characteristics of which of the following

128. A power supply has a full-load voltage of (IES (EC) - 2008)


24 V. What is its no-load voltage for 5%
regulation (rounded to the nearest integer) ?
(IES (EC) - 2007)
(a) 12 V (b) 23 V
(c) 25 V (d) 6 V

(a) Peak clipper (b) Bottom clipper


129. Which of the following components are chosen
to construct a d.c. power supply to supply 6 V (c) Clamper (d) Two level clipper
d.c. voltage from 230 V a.c. to operate a tape
recorder ?
132. When a junction diode is used as a half-wave
(IES (EC) - 2008) rectifier with purely resistive load and sinusoidal
1. Step down transformer input voltage. what is the value of diode
conduction angle (where  , is the ignition angle
2. Diodes
corresponding to the cut-in voltage)?
3. Resistors and capacitors
(IES (EC) - 2008)
4. Three-pin voltage stabilizer
(a) π
Select the correct answer using the code given
below : (b) π - i
(a) 1, 2 and 3 only (b) 1 and 4 only
(c) π - 2i
(c) 3 and 4 only (d) 1, 2, 3 and 4
(d) Slightly greater than π

130. The figure shown is a circuit of which one of


the following ? 133. Silicon diodes are less suited for low voltage
rectifier operation because
(IES (EC) - 2008)
(IES (EC) - 2008)
53
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) it cannot withstand high temperatures (a) 1 and 2 only (b) 1, 2 and 3
(b) its reverse saturation current is low (c) 3 only (d) 3 and 4 only
(c) its cut-in voltage is high
(d) its breakdown voltage is high 137. The output Vdc from the below circuit is
(IES (EC) - 2010)
134. Consider the following statements about a good
power supply :
1. The a.c. ripple should be high
2. SV (Voltage stability factor) should be low.
3. ST (Temperature stability factor) should
be low.
Which of the above statements are correct ? 12
(a) 12 2 (b)
(IES (EC) - 2009) 
(a) 1, 2 and 3 (b) 2 only 24 12
(c) 3 only (d) 2 and 3 only (c) (d)
 2

135. Which of the following does not show non- 138. A rectifier (without filter) with fundamental ripple
linear V-I characteristics ? frequency equal to twice the mains frequency
(IES (EC) - 2009) has ripple factor of 0.482 and power
conversion efficiency equal to 81.2%
(a) Schottky diode
The rectifier is
(b) Tunnel diode
(IES (EC) - 2010)
(c) Thermister, at a fixed temperature
1. Bridge rectifier
(d) p-n junction diode
2. Full-wave (non bridge) rectifier
3. Half-wave rectifier
136. Consider the following statements :
Which of these are correct ?
When compared with a bridge rectifier, a
centre-tapped full wave rectifier. (a) 2 and 3 only (b) 2 only
1. Has larger transformer utilization factor (c) 1 and 2 only (d) 1, 2 and 3
2. Can be used for floating output terminals
i.e. no input terminal is grounded 139. Consider the below circuit, for Vi = Vm sin ωt ,
3. Needs two diodes instead of four. the output voltage V0 for RL   will be
4. Needs diodes of a lower PIV rating. (IES (EC) - 2010)
Which of these statements is/are correct ?
(IES (EC) - 2010)
54
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(c)

(a) Zero (b) Vm


(c) 2 Vm (d) –Vm
(d)
140. The correct waveform for output (V0) for below
network is
(IES (EC) - 2010)
141. A half-wave rectifier has an input voltage of
250 V rms. If the step-down transformer has
turns ratio of 8 : 1, what is the peak load voltage?
ignore diode drop.
(IES (EC) - 2011)
(a) 27.5 V (b) 86.5 V
(c) 30.0 V (d) 42.5 V

142. A 40 V dc supply is connected across the


network comprising of Zener and silicon diodes
as shown. The regulated voltages V01, V02 and
source current Is are
(IES (EC) - 2012)

(a)

(a) 2.4 V, 5.1 V and 21.7 mA


(b) 3 V, 6 V and 22.7 mA
(b) (c) 3.3 V, 9.3 V and 20.5 mA
(d) 4 V, 10 V and 20 mA

55
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

143. For a full-wave rectifier, with sinusoidal input 147. Consider the following statements:
and inductor as filter, ripple factor for maximum
1. A zener diode degrades the input signal
load current and minimum load current
at high frequencies due to its transition
conditions are respectively
capacitance.
(IES (EC) - 2012)
2. The zener voltage VZ does not vary with
(a) 0.1 and 1 (b) 0.1 and 0.47 temperature
(c) 0 and 0.47 (d) 0 and 0.22
3. Regulation of the zener diode is adversely
affected at the knee current IZ due to
144. The ripple factor in case of a full-wave rectifier limited power dissipation capacity.
is 4. In a simple zener diode regulated circuit,
(IES (EC) - 2013) amplification is not possible
(a) 1.21 (b) 0.50 Which of these statements are correct ?
(c) 0.48 (d) 1.0 (IES (EE) - 2011)
(a) 1, 2, 3 and 4 (b) 3 and 4
145. The maximum efficiency of half-wave rectifier
is (c) 2 and 3 (d) 1 and 4

(IES (EC) - 2013)


(a) 33.33% (b) 40.60% 148. In an open circuited p-n junction diode space
charge density at the junction is
(c) 50.00% (d) 66.00%
(IES (EE) - 2012)

146. Statement (I) : Centre tap transformer is (a) Maximum (b) Zero
essential for a centre-tapped rectifier (c) Positive (d) Negative
Statement (II) : In half wave rectification
minimum two diodes are required
149. Material used for fabrication of Tunnel diode is
(IES (EC) - 2013)
(IES (EE) - 2012)
(a) Both Statement (I) and Statement (II) are
individually true and Statement (II) is the (a) Ge or GaAs (b) Si and GaAs
correct explanation of Statement (I) (c) Si and InSb (d) Ge and InSb
(b) Both Statement (I) and Statement (II) are
individually true but Statement (II) is not
the correct explanation of Statement (I) 150. The relative values of the forward conduction
voltage for a p-n junction diode, a Red LED
(c) Statement (I) is true but Statement (II) is and a Schottky barrier diode are
false
(IES (EC) - 2012)
(d) Statement (I) is false but Statement (II) is
true (a) Schottky voltage drop > p-n junction
diode drop > Red LED drop

56
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(b) Red LED drop > p-n junction diode


drop > Schottky voltage drop
(c) p-n junction diode drop > Schottky
voltage drop > Red LED drop
(d) Schottky voltage drop > Red LED
drop > p-n junction diode drop

151. The I-V characteristics of a tunnel diode exhibit


(IES (EC) - 2012)
(a) current-controlled negative resistance
(b) voltage-controlled negative resistance
(c) temperature-controlled positive resistance
(d) current-controlled positive resistance

57
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

CONVENTIONAL PROBLEMS 03. In Fig. the input Vt is a 100 HZ triangular wave


having a peak to peak amptitude of 2 volts and
01. (a) Two ideal and identical (idality factor
an average value of zero volt. Given that the
  1 ) function diodes are connected in diode is ideal, the average value of the output
series as shown in fig. show that V0 is ------
 ev1   ev 2  (GATE (EC) - 1991)
exp    exp  2
 KT   KT 
where V1 and V2 are the voltage drops
across the diodes

04. Figure shows an electronic voltage regulator. The


zener diode may be assumed to require a
(b) Assuming that the current through the minimum current of 25 mA for satisfactory
reverse biased diode is saturated at I0, operation. The value of R required for satisfactory
calculate the voltage drop across the voltage regulation of the circuit is
forward biased diode (Assume KT = 26
mv).
(GATE (EC) - 1990) (10M)

02. Refferring to the below figure the switch S is in


position 1 initially and steady state condition
exist from time t = 0 to t = t0. the switch is (GATE (EE) - 1991)
suddenly thrown into position 2. The current I
through the 10K resistor as a function of time
t, from t = 0 is ? (give the sketch showing the 05. In the circuit shown in Fig. calculate and sketch
magnitudes of the current at t = 0, t = t0 and the waveform of current i over one period of
t= ) the input voltages. Assume the diodes to be
ideal.
(GATE (EC) - 1991)
(GATE (EE) - 1992)

58
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

06. The forward dynamic resistance of a junction reverse resistance of infinity ?


diode varies _______ as the forward current (GATE (EC) - 1998)
increases.
(GATE (EC) - 1994)

07. Design the Zener voltage regulator, shown in


Figure below, to meet the following specifications.
Load voltage = 6.8 V, Source Voltage Vs is 20
V  20% and Load current is 30 mA.  50%.
The Zener requires a minimum current of 1 mA
to break down. The diode D has a forward 10. For the circuit shown in the figure, D1 and D2
conducting voltage of 0.6 V. are identical diodes with idality factor of unity.
The thermal voltage VT = 2.5 mV
(GATE (EE) - 1994)
(GATE (EC) - 2001) (5M)

(a) Calculate VT and Vr


08. Two identical silicon junction diodes, D1 and
D2 are connected back to back as shown in (b) If the reverse saturation current of D1 and
Fig. The reverse saturation current, IS of each D2 are 1 PA then compute the current I
diode is 10–8 Amps and the breakdown voltage, through the circuit
VBr , is 50V. Evaluate the voltage VD1 and VD2
dropped across the diode D1 and D2 assuming
kT/q to be 25 mV. 11. (a) Determine V0 for the following network
for the indicated input
(GATE (EC) - 1995)
(IES (EC) - 1996)

09. (a) Draw the transfer characteristic of the


circuit of Fig., assuming both D1 and D2
to be ideal.
(b) How would the characteristic change if
D2 is ideal, but D1 is non-ideal in that it
has forward resistance of 10  and a

59
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(b) Determine the output waveform for the (b) A series type ohmmeter uses a 100  basic
network shown and calculate the output movement with full scale deflection for
dc level and the required PIV of each
100  A . The battery voltage in the ohmmeter
diode.
circuit is 9V. The desired scale marking for
half scale deflection is 50 k . Find the values
of required resistor R1 in shunt with the meter
and the resistor R2 in series with the battery.
Also find the maximum values of R1 that will
compensate for a 10% drop in the battery
voltage and the percentage error at half scale
12. The input voltage Vi to the two-level clipper mark when R1 is so adjusted for the 10%
shown below varies linearly from 0 to 150 V. drop in battery voltage.
Sketch the output voltage to the same scale as
the input voltage. Assume ideal diodes. 14. A germanium diode has reverse saturation current
(IES (EC) - 1997) of 30  A at 125°C. What are its dynamic
forward and reverse resistances for a bias 0.2V
at this temperature ?
(IES (EC) - 1997)

15. An LED with minimum and maximum voltage


drops of 1.8V and 3V respectively is connected
13. (a) Sketch the output waveform for the circuit
to a 24V supply in series with a 820  resistor..
of Fig. Also draw the variation of energy
stored in the capacitor as a function of time. An identical LED is connected to a 10V supply
Mark appropriate values. Take the diode to in series with a resistor of 120  . Determine
be ideal which arrangement is preferable from the point
(IES (EC) - 1996) of view of constant brightness from the LED.
(IES (EC) - 1997)

16. Explan the two valley model of GaAs Gunn


diode.
If the electron density and mobility in the lower
velley are 1014 m–3 and 0.8 m²/V sec respectively
and those in the upper valley are 1016 m–3 and
180 × 10–4 m²/V sec respectively, calculate
conductivity of the diode.
(IES (EC) - 1997)

17. When the current through a Zener diode increases

60
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

from 20 mA to 30 mA, the voltage across it 22. A particular diode circuit produces the output
changes from 5.6 V to 5.65 V. What is the shown in Fig. when the input Vi = 5 sin ωt .
voltage across the Zener when the current is Design the circuit. Draw and explain the transfer
35 mA characteristic of the circuit. Neglect the diode
(IES (EC) - 1997) voltage drop. Assume the forward resistance
of diode to be 100  and the reverse resistance
to be 1M.
18. A silicon single phase full wave bridge rectifier (IES (EC) - 2012)
circuit is shown. Explain what happens if the
transformer and the load positions are
interchanged.
(IES (EC) - 1998)

23. In the circuit shown, calculate and sketch the


current i(t) over the period 0    2 .
19. Avalanche breakdown can occur at large Assume the diodes to be ideal.
reverse voltage whereas Zener breakdown
occurs at low voltage. Give reasons.
A 15 V Zener diode is connected in series with
a forward-biased silicon diode for constructing
a zero-temperature-coefficient. voltage
reference. The temperature coefficient of the
silicon diode is –1.7 mV/°C. Find the required
temperature coefficient of the Zener diode in (IES (EE) - 2012)
percent per degree.
(IES (EC) - 2012) (10M) 24. In a full wave rectifier circuit with centre-tap
transformer, independently of the filter used, the
20. Draw E-K diagram of GaAs with two peak inverse voltage across each diode is equal
conduction band minima. Hence explain the to
negative resistance characteristics of Gunn (i) Vm (ii) 2 Vm
diode.
Vm Vm
(IES (EC) - 2012) (iii) (iv)
2 2
Where Vm is the maximum transformer voltage
21. Discuss the capacitance-voltage characteristics measured from the midpoint (centre-tap) to
of varactor diodes with their applications. either end.
(IES (EC) - 2012) (IES (EE) - 2011)
61
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

ANSWER KEY

01. d 27. a 53. a 79. d 105. d 131. a


02. b 28. b 54. a 80. b 106. b 132. c
03. d 29. c 55. d 81. c 107. b 133. c
04. c 30. c 56. a 82. b 108. b 134. d
05. b 31. c 57. a 83. a 109. a 135. c
06. a,c 32. a 84. b 110. d 136. c
58. c
07. b 33. d 85. c 111. a 137. c
59. a
08. b 34. d 86. a 112. b 138. c
60. b
09. b 35. d 87. a 113. d 139. c
61. b
10. b 36. c 88. c 114. d 140. a
62. c
11. b 37. b 89. c 115. d 141. d
63. a
12. c 38. c 90. d 116. c 142. d
64. d
13. abc 39. a 91. 117. d 143. c
65. a
14. a 40. b 92. 118. a 144. c
66. b
15. a 41. a 93. c 119. b 145. b
67. d
16. d 42. a 94. b 120. a 146. c
68. c
17. c 43. c 95. c 121. c 147. d
69. b
18. d 44. c 96. d 122. c 148. b
70. c
19. d 45. b 97. d 123. c 149. a
71. a
20. b 46. a 98. d 124. b 150. b
72. b
21. b 47. a 99. b 125. d 151. b
73. c
22. c 48. c 100. b 126. c
74. a
23. d 49. b 101. b 127. a
75. b
24. b 50. c 102. a 128. c
76. b
25. a 51. c 103. d 129. d
77. d
26. b 52. c 104. b 130. b
78. b

62
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

CHAPTER-3
TRANSISTOR
01. Each transistor in Darlington pair (see fig. (GATE (EC) - 1988)
below) has hFE = 100. The overall hFE of the (a) gm will not be affected
composite transistor neglecting the leakage
currents is (b) gm will decrease
(GATE (EC) - 1988) (c) gm will increase
(d) gm will increase (or) decrease depending
upon bias stability.

04. Of the four biasing circuits shown in Fig. For a


BJT, indicate the one which can have maximum
(a) 10000 (b) 10001 bias stability :

(c) 10100 (d) 10200 (GATE (EC) - 1989)

02. The transistor in the amplifier shown below has


following parameters: hfe = 100, hie = 2K ,
hre = 0, hoe = 0.05 mmhos, C is very large. The
output impedance is
(GATE (EC) - 1988)
(a) (b)

(a) 20 K (b) 16 K

(c) 5 K (d) 4 K

03. The quiescent collector current IC, of a transistor


is increased by changing the biasing resistance. (c) (d)
As a result.

63
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

05. For good stabilized biasing of the transistor of


the CE Amplifier of fig. We should have
(GATE (EC) - 1990)

(a) both T1 and T2 get damaged


(b) both T1 and T2 will be safe
RE RE (c) T1 will get damaged and T2 will be safe
(a)  1 (b)  1
RB RB (d) T2 will get damaged and T1 will be safe.

RE RE
(c)  h FE (d)  h FE
RB RB 08. Figure shows a common emitter amplifier. The
quiescent collector voltage of the circuit is
approximately
06. Which of the following statements are correct (GATE (EE) - 1991)
for basic transistor Amplifer configurations ?
(GATE (EC) - 1990)
(a) CB Amplifiers has low input impedance
and low current gain
(b) CC Amplifiers has low input impedance
and high current gain
(c) CE Amplifiers has very poor voltage gain
but very high input impedance 20
(a) V (b) 10 V
(d) The current gain of CB Amplifier is higher 3
than the current gain of CC Amplifiers
(c) 14 V (d) 20 V

07. Discrete transistor T1 and T2 having maximum


09. In a Common Emitter amplifier, the unbypassed
collector current rating of 0.75 amps are
emitter resistance provides
connected in parallel as shown in the Fig. The
combination is treated as a single transistor to (GATE (EE) - 1992)
carry a total current of 1 ampere, when biased (a) Voltage-shunt feedback
with self bias circuit. When the circuit is switched
on T1 draws 0.55 amps and T2 draws 0.45 (b) Current - series feedback
amps. If the supply is kept on continuously, (c) Negative-voltage feedback
ultimately it is very likely that
(d) Positive - current feedback
(GATE (EC) - 1991)

64
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

10. In an RC-coupled Common Emitter amplifier, (d) Increases with the decrease in the base
which of the following is true ? width
(GATE (EE) - 1992) (IES (EE) - 2003)
(a) Coupling capacitance affects the hf 13. Match the following
response and bypass capacitance affects (GATE (EC) - 1994) (2M)
the If response
List - I
(b) Both coupling and bypass capacitances
affect the If response only A. The current gain of a BJT will be increased
if
(c) Both coupling and bypass capacitances
affect the hf response only B. The current gain of a BJT will be reduced
if
(d) Coupling capacitance affects the I f
response and the bypass capacitance C. The break-down voltage of a BJT will be
affects the hf response . reduced if
List - II
11. For the Amplifier circuit of fig. The transistor 1. The collector doping concentration is
has a β of 800. The mid band voltage gain increased
V0 / V1 of the circuit will be. 2. The base width reduced
(GATE (EC) - 1993) 3. The emitter doping concentration to base
doping concentration ratio is reduced
4. The base doping concentration is
increased keeping the ratio of the emitter
doping concentration to base doping
concentration constant
5. The collector doping concentration is
reduced
Codes :
A B C
(a) 0 (b) < 1 (a) 2 3 1
(c) 1 (d) 800 (b) 1 5 3
(c) 2 4 5
12.  -cut off frequency of a bipolar junction (d) 4 2 1
transistor
(GATE (EC) - 1993) (2M)
14. In the transistor circuit as shown below the
(a) Increases with the increase in base width collector to ground voltage is +20 V. The
(b) Increases with the increase in emitter width possible condition is
(c) Increases with the increase in collector (GATE (EE) - 1994) (IES (EE) - 2003)
width

65
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

17. The Ebers-Moll model is applicable to


+20 V
(GATE (EC) - 1995) (1M)
(a) Bipolar junction transistors
10k
(b) NMOS transistors
(c) Unipolar junction transistors
47k
(d) Junction field-effect transistors
+10 V

18. In a bipolar junction transistor (Match the


following)
(GATE (EC) - 1995) (2M)
(a) Collector - emitter terminals shorted List-I
(b) Emitter to ground connection open A. The current gain increases
(c) 10 kilo- ohms resistor open B. The collector breakdown voltage
increases
(d) Collector - base terminals shorted
C. The cut-off frequency increases
List-II
15. The break down voltage of a transistor with its
base open is BVCEO and that with emitter open 1. The base doping is increased and the base
is VBCBO, then width is reduced
(GATE (EC) - 1995) (1M) 2. The base doping is reduced and the base
width is increased
(a) BVCEO = BVCBO
3. The base doping and the base width are
(b) BVCEO > BVCBO
reduced
(c) BVCEO < BVCBO
4. The emitter area is increased and the
(d) BVCEO is not related to BVCBO collector area is reduced
5. The base doping and the base width are
16. A BJT is said to be operating in the saturation increased
region if Codes :
(GATE (EC) - 1995) (1M) A B C
(a) Both junctions are reverse biased (a) 3 1 1
(b) Base-emitter junction is R.B and base (b) 1 5 3
collector junction is forward biased
(c) 2 4 5
(c) Base-emitter junction is forward biased
(d) 4 2 1
and base collector junction reverse biased
(d) both the junctions are forward biased
19. If a transistor is operating with both of its
junctions forward biased, but with the collector
66
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

base forward bias greater than the emitter-base A. Cascade Amplifier


forward bias, then it is operating in the B. Differential Amplifier
(GATE (EC) - 1996) (2M) C. Darlington pair common Collector
(a) forward active mode Amplifer
(b) reverse saturation mode 1. does not provide current gain
(c) reverse active mode 2. is a wide band Amplifier
(d) forward saturation mode 3. has very low input impedance and very
high current gain

20. In a bipolar transistor at room temperature, if 4. has very high input impedance and very
the emitter current is doubled, the voltage across high current gain
its base-emitter junction 5. Provides high common mode voltage
(GATE (EC) - 1996) Rejection

(a) doubles Codes :

(b) halves A B C

(c) increases by about 20 mV (a) 2 5 4

(d) decreases by about 20 mV (b) 1 2 5


(c) 1 3 4

21. A Darlington stage is shown in the fig, if the (d) 2 5 3


transconductance of Q1 is gm1 and Q2 is gm2,
 icc  23. The common-emitter short-circuit current gain
then the overall transconductance gm  v c  is  of a transistor
 be 
given by (GATE (EC) - 1996)
(a) is a monotonically increasing function of
the collector current IC
(b) is a monotonically decreasing function of
IC
(c) increases with IC, for low IC reaches a
maximum and then decreases with further
increase in IC
(GATE (EC) - 1996)
(d) is not a function of IC
(a) gm1 (b) 0.5 gm1
(c) gm2 (d) 0.5 gm2
24. An npn transistor has a beta cut-off frequency
f  of 1 MHz and Common Emitter short circuit
22. Match the following
low frequency current gain  0 of 200 at unity
(GATE (EC) - 1996)
gain frequency fT and the alpha cut-off
67
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

frequency f respectively are 27. In the BJT amplifier shown in the figure is the
transistor is biased in the forward active region
(GATE (EC) - 1996) putting a capacitor across RE will
(a) 200 MHz, 201 MHz (GATE (EC) - 1997)
(b) 200 MHz, 199 MHz
(c) 199 MHz, 200 MHz
(d) 201 MHz, 200 MHz

25. In the transistor amplifier shown in Figure, the


ratio of small signal voltage gain, when the
emitter resistor Re is bypassed by the capacitor
Ce to when it is not bypassed, (assuming
simplified approximate h-parameter model for
transistor, is
(GATE (EE) - 1996) (a) decrease the voltage gain and decrease
the i/p impedance
(b) increase the voltage gain and decrease the
i/p impedance
(c) decrease the voltage gain and increase the
i/p impedance
(d) increase the voltage gain and increase the
i/p impedance

(a) 1 (b) hfe 28. The Emitter coupled pair of BJT’s gives a linear
transfer relation between the differential o/p
1  h  R
fe e 1  h  R
fe e voltage and the differential input voltage Vid only
(c) (d) 1  when the magnitude of Vid is less ‘  ’ times the
hie hie
thermal voltage, where ‘  ’ is
(GATE (EC) - 1998)
26. From measurement of the rise of the o/p pulse
(a) 4 (b) 3
of anAmplifier whose input is a smallAmplitude
square wave, one can estimate the following (c) 2 (d) 1
parameter of the Amplifier
(GATE (EC) - 1998) 29. In a series Regulated power supply circuit the
voltage gain AV of the “pass”, transistor satisfies
(a) gain-bandwidth product
the condition
(b) Slew Rate
(GATE (EC) - 1998)
(c) Upper-3-dB frequency
(a) Av   (b) 1  Av  
(d) lower 3-dB frequency
(c) Av  1 (d) Av  1
68
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

30. The fT of a BJT is related to its gm, C π and Cμ (b) obtaining a very high current gain
as follows (c) current feedback
(GATE (EC) - 1998) (d) temperature stabilized biasing

C π  Cμ
(a) f T  33. In the cascode amplifier shown in the figure, if
gm
the common - emitter stage (Q1) has a
transconductance gm1, and the common base
2  C π  C μ  stage (Q2) has a transconductance gm2, then the
(b) f T  overall transconductance g (= i0 / Vi) of the
gm
cascode amplifier is
gm (GATE (EC) - 1999)
(c) f T 
 C π  Cμ 
Q 2
i 0

gm Vo

(d) f T  2  C  C 
π μ

R L

31. A NPN, silicon transistor is meant for low-


V Q
current audio amplification. Match its following i 1

characteristics against their values :


(GATE (EE) - 1998)
Characteristics Values (a) gm1 (b) gm2

(A) VEB, max (P) 0.7 V g m1 g m2


(c) (d)
(B) VCB, max (Q) 0.2 V 2 2
(C) VCE, sat (R) 6 V
(S) 50 V 34. An npn transistor (with C = 0.3 pF) has a unity
- gain cut off freguency fT of 400 MHz at a dc
Codes
bias current IC = 1 mA. The value of its C μ
A B C
(a) P R Q (in pF) is approximately  VT  26mV 

(b) P R S (GATE (EC) - 1999)


(c) R P Q (a) 15 (b) 30
(d) S P Q (c) 50 (d) 96

32. One of the applications of current mirror is 35. The Early effect in a bipolar junction transistor
is caused by
(GATE (EE) - 1998)
(GATE (EC) - 1999)
(a) output current limiting
69
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) fast turn - on at high frequencies because of


(b) fast turn - off (GATE (EC) - 2000)
(c) large collector - base reverse bias (a) transistor capacitances
(d) large emitter - base forward bias (b) high current effects in the base
(c) parasitic inductive elements
36. In the circuit of the figure, assuming that the (d) the Early effect
transistor is in the active region. It has a large
β and its base - emitter voltage is 0.7V. The
39. In the circuit of Fig. the value of the base
value of IC is
current IB will be
(GATE (EC) - 2000)
(GATE (EE) - 2000)
15 V

10 K RC
IC

5 K 

(a) Indeterminate since RC is not given


(a) 0.0 micro amperes
(b) 1 mA
(b) 18.2 micro amperes
(c) 5 mA
(c) 2.7 micro amperes
(d) 10 mA
(d) 40.0 micro amperes

37. Introducing a resistor in the emitter of a


40. If the transistor in the figure is in saturation ,
common amplifier stablizes the dc operating
then
against variations in
(GATE (EC) - 2001)
(GATE (EC) - 2000)
(a) only the temperature
C I C

(b) only the  of the transistor


(c) both temperature and  I B

(d) none of the above B

38. The current gain of a bipolar transistor drops


E
70
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) IC is always equal to β dc IB (c) PZ  95mW, PT  9.9W

(b) IC is always equal to β dc IB (d) PZ  115mW, PT  11.9W

(c) IC is greater than or equal to β dc IB

(d) IC is less than or equal to β dc IB 43. An npn BJT has gm = 38 mAV, C  10 14 F,
C  1013 F, and DC current gain β 0  90.

41. The current gain of a BJT is For this transistor f T and f β are
(GATE (EC) - 2001) (GATE (EC) - 2001)

gm (a) fT  1.64 108 Hz and f  1.47 1010 Hz


(a) g m ro (b) ro
(b) fT  1.47 1010 Hz and f  1.64 108 Hz
gm
(c) g m r (d) r (c) f T  1.33  1012 Hz and fβ  1.47  1010 Hz

(d) fT  1.47 1010 Hz and f  1.331012 Hz


42. The transistor shunt regulator shown in the figure
has a regulated output voltage of 10 V, when
the input varies from 20 V to 30 V. The relevant 44. In the single-stage transistor amplifier circuit
parameters for the zener diode and the transistor shown in Figure, the capacitor CE is removed.
are: VZ  9.5, VBE  0.3V,β  99. Neglect Then, the ac small-signal midband voltage gain
of the amplifier.
the current through R B . Then the maximum
(GATE (EE) - 2001)
power dissipated in the zener diode (PZ) and
the transistor (PT) are
(GATE (EC) - 2001)

20
IZ IC
VZ

V0 = 10V
Vin 20 - 30V +
V BE -
RB
(a) Increase (b) Decrease
(c) Is unaffected (d) Drops to zero

(a) PZ  75mW, PT  7.9W


Statement for Linked Questions : 45-46
(b) PZ  85mW, PT  8.9W
The transistor in the amplifier circuit shown in

71
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Figure is biased at IC = 1mA (c) CB-MO, CC-HI, CE-LO

Use VT = kT/q = 26 mV,  0 = 200, rb = 0, and (d) CB-HI, CC-LO, CE-MO


r0  
Statement for Linked Questions : 48, 49 & 50
For the circuit shown in Figure, IE = 1mA,
β = 99 and VBE = 0.7 V

45. Small-signal mid-band voltage gain v0 / v1 is


(GATE (EE) - 2001)
(a) –8 (b) 38.46
(c) –6.62 (d) –1 48. The current through RC is
(GATE (EE) - 2002)
46. What is the required value of CE for the circuit (a) 0.99 mA (b) 1.1 mA
to have a lower cut-off frequency of 10 Hz (c) 1.20 mA (d) 1 mA
(GATE (EE) - 2001)
(a) 0.159 mF (b) 1.59 mF 49. Output voltage Vo will be
(c) 5  F (d) 10  F (GATE (EE) - 2002)
(a) 16.1 Volt (b) 14 Volt
47. Choose the correct match for input resistance (c) 13.9 Volt (d) None of these
of various amplifier configuration shown below
Configuration Input resistance 50. Value of resistance RC is
CB: Common Base LO: LOW (GATE (EE) - 2002)
CC: Common collector MO: Moderate
(a) 110.9 k (b) 124.5 k
CE: Common emitter HI: High
(c) 130.90 k (d) None of these
(GATE (EC) - 2003)
(a) CB-LO, CC-MO, CE-HI
51. In the amplifier circuit shown in the figure, the
(b) CB-LO, CC-HI, CE-MO
values of R1 and R2 are such that the transistor
72
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

is operating at VCE  3V and IC  1.5mA


when its β is 150. For a transistor with  of IC 3.3 K
33K
200, the operating point  VCE , IC  is
12 V
(GATE (EC) - 2003)
4V
VCC=6V 3.3 K

R1 R2
(a) [3.3/3.3] mA
(b) [3.3/(3.3+.33)] mA
(c) [3.3/.33] mA
(d) [3.3/33+3.3] mA

54. A bipolar transistor is operating in the active


region with a collector current of 1mA.
Assuming that the  of the transistor is 100
(a) (2V, 2mA) (b) (3V, 2mA)
and the thermal voltage (V T) is 25mV, the
(c) (4V, 2mA) (d) (4V, 1mA) transconductance (gm) and the input resistance
 r  of the transistor in the common emitter
52. Generally the gain of a transistor amplifier falls configuration are
at high freguencies due to the
(GATE (EC) - 2004)
(GATE (EC) - 2003) (IES (EE) - 2012)
(a) g m  25mA / V and r  15.625k
(a) internal capacitances of the devices
(b) coupling capacitor at the input (b) g m  40mA / V and r  4.0k
(c) skin effect (c) g m  25mA / V and r  2.5k
(d) coupling capacitor at the output
(d) g m = 40mA/V and rπ = 2.5kΩ/2

53. In the circuit of figure, assume that the transistor


has hFE = 99 and VBE = 0.7V. The value of 55. Assuming VCEsat = 0.2V and β = 50, the min
collector current I C of the transistor is
base current (IB) required to drive the transistor
approximately
in the figure to saturation is
(GATE (EE) - 2003) (1M)
(GATE (EC) - 2004)

73
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(GATE (EC) - 2004)


3V
IC

1k 5V
I C

4 K 2.2 K
IB
+

V CE

-
1 K 

(a) 56  A (b) 140mA


(a) IC  1mA, VCE  4.7V
(c) 60mA (d) 3mA
(b) IC  0.5 mA, VCE  3.75 V
56. The neutral base width of a bipolar transistor , (c) IC  1mA, VCE  2.5V
biased in the acitve region, is 0.5m. The
maximum electron concentration and the (d) IC  0.5mA, VCE  3.9V
diffusion constant in the base are 1014 / cm 3
and Dn  25cm 2 / sec respectively. Assuming 59. Conside the following statements S1 and S2
negligible recombination in the base, the
S1: The β of a bipolar transistor reduces if
collector current density is (the electron charge
the base width is increased.
is 1.6  10 19 coulomb)
S2: The β of a bipolar transistor increases if
(GATE (EC) - 2004)
the doping concentration in the base is
(a) 800A / cm 2 (b) 8A / cm 2 increased.

(c) 200 A / cm 2 (d) 2 A / cm 2 Which one of the following is correct?


(GATE (EC) - 2004)
(a) S1 is FALSE and S2 is TRUE
57. The impurity commonly used for realizing the
base region of a silicon n-p-n transistor is (b) Both S1 and S2 are TRUE
(GATE (EC) - 2004) (c) Both S1 and S2 are FALSE
(a) Gallium (b) Indium (d) S1 and TRUE and S2 is FALSE
(c) Boron (d) Phosphorus
60. If for a silicon n-p-n transistor, the base - to -
emitter voltage (VBE) is 0.7 V and the collector
58. Assuming that the β of the transistor is - to - base voltage (VCB) is 0.2 V, then the
extremely large and VBE = 0.7 V, IC and VCE in transistor is operating in the
the circuit shown in the figure are
74
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(GATE (EC) - 2004) (IES (EE) - 2012) (d) both the base-emitter and base-collector
(a) normal acitve mode junctions are forward biased

(b) saturation mode


(c) inverse active mode 63. The transconductance gm of the transistor shown
in figure is 10 mS. The value of the input
(d) cutoff mode resistance RIN is
(GATE (EE) - 2004) (2M)
61. Two perfectly matched silicon transistor are
connected as shown in figure. The value of the VCC
current I is
(GATE (EE) - 2004 (1M), 2008) (2M) 10 k RC
V0
+3 V C= C=
VS =50
1 K
I

=1000 =1000 10 k 1 k C=


+
0.7 V

(a) 10.0 k (b) 8.3 K

(c) 5.0 k (d) 2.5 k


-5V

(a) 0 mA (b) 2.3 mA 64. For an npn transistor connected as shown in


(c) 4.3 mA (d) 7.3 mA the figure, VBE = 0.7 volts. Given that reverse
saturation current of the junction at room
temperature 300K is 1013 A, the emitter
62. A bipolar junction transistor (BJT) is used as a
current is
power control switch by biasing it in the cut-
off region (OFF state or in the saturation region (GATE (EC) - 2005)
in (ON state). In the ON state, for the BJT
(GATE (EE) - 2004)
IC
(a) both the base-emitter and base-collector
junctions are reverse biased
(b) the base-emitter junctions is reverse
biased, and the base-collector junctions
is forward biased
VBE
(c) the base-emitter junctions is forward
biased, and the base-collector junctions
is reverse biased
75
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) 30 mA (b) 39 mA 67. The common emitter amplifier shown in the


(c) 49 mA (d) 20 mA figure is biased using a 1mA ideal current
source. The approximate base current value is
(GATE (EE) - 2005) (2M)
65. The circuit using a BJT with   50 and
VBE = 0.7 V is shown in the figure. The base V CC=5 V
current IB and collector voltage VC are
respectively
(GATE (EC) - 2005) RC=1k

20 V
V out
2k
430k VC
=100
+
10F
V in
~ 1 mA

40F

(a) 0 μA (b) 10μA

(a) 43μA and 11.4 volts (c) 100μA (d) 1000μA

(b) 40μA and 16 volts


68. The DC current gain  β  of a BJT is 50.
(c) 45μA and 11 volts
Assuming that the emitter injection efficiency is
(d) 50μA and 10 volts 0.995, the base transport factor is
(GATE (EC) - 2007)
66. The phenomenon known as “Early Effect” in a (a) 0.980 (b) 0.985
bipolar transistor refers to a reduction of the (c) 0.990 (d) 0.995
effective base-width caused by
(GATE (EC) - 2006)
Common Data for Questions 69 and 70
(a) electron-hole recombination at the base
In the transistor amplifier circuit shown in the
(b) the reverse biasing of the base - collector figure below, the transistor has the following
junction parameters:
(c) the forward biasing of emitter - base
junction β DC  60, VBE  0.7V, h ie  , h fe  

(d) the early removal of stored base charge The capacitance CC can be assumed to be
during saturation - to - cutoff switching infinite.
76
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

20 nA and the the input voltage is +5 V, the


12 V transistor would be operating in
(GATE (EE) - 2006) (2M)
1K
53K +12V
+
5.3K
2.2 k
VC
CC
~ VS -
15k

Q
In the figure above, the ground has been shown 100k
by the symbol 
-12V
69. Under the DC conditions, the collector - to - (a) saturation region
emitter voltage drop is
(b) active region
(GATE (EC) - 2006)
(c) breakdown region
(a) 4.8 volts (b) 5.3 volts
(d) cut- off region
(c) 6.0 volts (d) 6.6 Volts

73. For the BJT circuit shown, assume that the 


70. If β DC is increased by 10%, the collector - to of the transistor is very large and VBE = 0.7 V.
- emitter voltage drop The mode of operation of the BJT is
(GATE (EC) - 2006) (GATE (EC) - 2007)
(a) increases by less than or equal to 10 %
10 K
(b) decreases by less than or equal to 10%
(c) increases by more than 10%
(d) decreases by more than 10%
+ 10 V
-

71. The small-signal gain of the amplifier VC / Vs is 1 K


2V +
-
(GATE (EC) - 2006)
(a) -10 (b) -5.3
(c) 5.3 (d) 10
(a) cut-off (b) saturation
(c) normal active (d) reverse active
72. Consider the circuit shown in the figure. If the
β (beta) of the transistor is 30 and ICBO is
77
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

74. In a common emitter BJT amplifier, the 76. The three - terminal linear voltage regulator is
maximum usable supply voltage is limited by connected to a 10  load resistor as shown in
(GATE (EC) - 2007) the figure. If Vin is 10 V, What is the power
dissipated in the transistor?
(a) Avalanche breakdown of Base-Emitter
junction (GATE (EE) - 2007) (1M)
(b) Collector-Base breakdown voltage with
emitter open (BVCBO)
(c) Collector-Emitter breakdown voltage
1 k
with base open (BVCBO) V in
R L=10 
(d) Zener breakdown voltage of the Emitter-
6.6 V
Base junction Zener diode

0
75. The common emitter- forward current gain of
(a) 0.6 W (b) 2.4 W
the transistor shown is β F  100
(c) 4.2 W (d) 5.4 W
(GATE (EE) - 2007) (1M)

+10 V Statement for linked Answer Questions 77


and 78

1K In the following t ransist or circuit


VBE = 0.7 V, re = 25 mV/I E , and β and all the
capacitances are very large

20 K 3K
270 K

Cc2
1 K

CC1
IE
The transistor is operating in 10 K 2.3 K 3K
(a) Saturation region
CE
(b) Cut - off region
(c) Reverse active region
(d) Forward active region
77. The Value of DC current I E is

78
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(GATE (EC) - 2008)


+10 V
(a) 1 mA (b) 2 mA
(c) 5 mA (d) 10 mA

78. The mid - band voltage gain of the amplifier is


approximately V in

(GATE (EC) - 2008) RL=10 


(a) -180 (b) -120
(c) -90 (d) -60

-10 V
79. Two perfectly matched silicon transistor are
connected as shown in the figure .Assuming the (a) 46% (b) 55%
β of the transistors to be very high and the (c) 63 % (d) 92%
forward voltage drop in diodes to be 0.7 V,
the value of current I is
81. A small signal source Vi(t) = A cos 20t + B sin
(GATE (EE) - 2008) (2M) 106 t is applied to a transistor amplifier as shown
+5V below. The transistor has β  150 and
1k
h ie  3kΩ .Which expression best approxi-
I
mates v0(t) ?
(GATE (EC) - 2009)
Q1 Q2
12 V

-5V
100 k 3K
(a) 0 mA (b) 3.6 mA
V (t)
0

(c) 4.3 mA (d) 5.7 mA 100 nF


V (t)
0

100 nF
80. The input signal Vin shown in the figure is a 1kHz
square wave voltage that alternates between 20 k 900 k
+7 V and -7 V with a 50% duty cycle. Both 10 F
transistor have the same current gain, which is
large. The circuit delivers power to the load
resistor RL. What is the efficiency of the circuit
for the given input? choose the closet answer. (a) Vo  t   1500  A cos 20t  Bsin106 t 

(GATE (EE) - 2008) (2M)


(b) Vo  t   150  A cos 20t  Bsin10 6 t 

(c) Vo  t   1500 Bsin106 t

79
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

below with the following circuit parameters:


(d) Vo  t   150 Bsin106 t
β  100, g m  0.3861 A / V, ro  , r  259

82. In the silicon BJT circuit shown below, assume R S  1, R B  93k, R C  250 ,
that the emitter area of transistor Q1 is half that
of transistor Q2. R L  1, C1   and C 2  4.7 F.

I +10V
R=9.3K 0

RB RC

Q1 Q2
( =700)
1 ( =715)
 C2

C1
RS +
V0 RL
-10 V + -
VS ~
The value of current I0 is approximately -

(GATE (EC) - 2010)


(a) 0.5 mA (b) 2 mA 84. The resistance seen by the source VS is
(c) 9.3 mA (d) 15 mA (GATE (EC) - 2010)
(a) 250  (b) 1258
83. In a uniformly doped BJT, assume that
(c) 93 (d) 
N E , N B and N C are the emitter, base and
collector dopings in atoms/cm³, respectively.
If the emitter injection efficiency of the BJT is 85. The lower cut- off frequency due to is
close to unity, which one of the following
(GATE (EC) - 2010)
conditions is TRUE?
(a) 33.9 Hz (b) 27.1 Hz
(GATE (EC) - 2010)
(c) 13.6 Hz (d) 16.9 Hz
(a) NE  NB  NC

(b) N E  N B and N B  N C 86. The transistor circuit shown uses a silicon


transistor with VBE= 0, IC  I E and a dc current
(c) N E  N B and N B  N C
gain of 100. The value of V0 is
(d) N E  N B  N C (GATE (EE) - 2010) (2M)

Common Data for Questions 84 and 85


Consider the common emitter amplifier shown
80
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

+10V

10 K 50 K

V0

100 K (a) Maximum (b) Minimum


(c) Unity (d) Zero

(a) 4.65 V (b) 5 V 89. For the BJT Q1 in the circuit shown below,
(c) 6.3 V (d) 7.23 V    , VBEon = 0.7V, VCEsat = 0.7V. The
switch is initially closed. At time t = 0, the switch
is opened. The time t at which Q1 levels the
87. For a BJT, the common-base current gain active region is
 = 0.98 and the collector base junction
(GATE (EC) - 2011)
reverse bias saturation current ICO = 0.6 μA .
This BJT is connected in the common emitter
mode and operated in the active region with a
base drive current IB = 20 μA . The collector
current IC for this mode of operation is
(GATE (EC) - 2011)
(a) 0.98 mA (b) 0.99 mA
(c) 1.0 mA (d) 1.01 mA

88. In circuit shown below, capacitors C1 and C2 (a) 10 ms (b) 25 ms


are very large and are short at the input
(c) 50 ms (d) 100 ms
frequency. Vi is a small signal input. The gain
magnitude [v0 / vi] at 10 M rad/s is
(GATE (EC) - 2011) 90. The transistor used in the circuit shown below
has a β of 30 and ICBO is negligible
(GATE (EE) - 2011)
If the forward voltage drop of diode is 0.7 V,
then the current through collector will be

81
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) |Av|  200 (b) |Av|  100


(c) |Av|  20 (d) |Av|  10

93. In the circuit shown below, the silicon npn


transistor Q has a very high value of β . The
required value of R2 in k to produce IC= 1mA
is

(a) 168 mA (b) 108 mA (GATE (EC) - 2013)

(c) 20.54 mA (d) 5.36 mA

91. The current ib through the base of a silicon npn


transistor is 1 + 0.1 cos (10000  t ) mA. At
300K, the r in the small signal model of the
transistor is
(GATE (EC) - 2012)
(a) 20 (b) 30
(c) 40 (d) 50

94. A silicon transistor with

VBEsat  0.8V,β dc  100 and VCEsat  0.2V


(a) 250  (b) 27.5  is used in the circuit shown below:
(c) 25  (d) 22.5  +10 V

RC
92. The voltage gain Av of the circuit shown below
is
(GATE (EC) (EE) - 2012)
200 K
+
5V -

What is the minimum value of RC for which


transistor is in saturation?
(IES (EC) - 1998) (IES (EE) - 2004)
82
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) 4286  (b) 4667  (a) large current gain and high input resistance
(b) large voltage gain and low output
(c) 5000  (d) 1000 
resistance
(c) small voltage gain and low input resistance
95. For the circuit shown in figure given below, (d) small current gain and high output
assume β  h FE  100. The transistor is in resistance
(IES (EE) - 2004)
98. The gain of a bipolar transistor drops at high
frequencies. This is because of the
3K (IES (EE) - 2005)

50 K (a) Coupling and bypass capacitors


(b) Early effect
(c) Inter-electrode transistor capacitances
10 V
2K (d) Coupling and bypass capacitors, and inter
- electrode transistor capacitances
5V

(a) Active region and VCE = 5V 99. Match List - I (Type of Amplifier /
(b) Saturation region Configuration) with List - II (Characteristic
Property) and select the correct answer using
(c) Active region and VCE = 1.42V the codes given below the lists:
(d) Cut - off - region (IES (EE) - 2006)
List - I
96. Two p-n junction diodes are connected back A. Common emitter amplifier
to back to make a transistor. Which one of the
following is correct? B. Emitter follower
(IES (EE) - 2005) C. Common base amplifier
(a) The current gain of such a transitor will D. Darlington pair
be high List - II
(b) The current gain of such a transistor will 1. Very low output resistance
be moderate
2. Current gain ~ 1
(c) It cannot be used as a transistor due to
3. Beta multiplication
large base width
4. Very high power gain
(d) It can be used only for pnp transistor
Codes:
97. For common emitter configuration which one A B C D
of the following statements is correct? (a) 4 1 2 3
(IES (EE) - 2005)
83
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(b) 2 3 4 1 102. If α F and α R denote the forward and inverted


(c) 4 3 2 1 mode current gains of a BJT, which one of the
(d) 2 1 4 3 following is correct?
(IES (EE) - 2007)

100. In the circuit given below, if the output is taken (a) α F = α R (b) α F < α R
from point E instead of node C, what will be
the result? (c)  F   R (d)  F   R
(IES (EE) - 2006)

VCC 103. Fixed biasing of CE configuration is shown in


the figure given below

+VCC
C
B RB=R 1||R2 RL

+ E V0
VS
-

RE
(a) An increase in the output impedance
(b) A reduction in the output impedance IE
(c) An increase in the input impedance
(d) A reduction in the input impedance The current stabilization factor for

RB
R B  β R E is Si  1 
101. Which of the following are true for h- RE
parameters of transistors?
For R B  R E , what is the voltage stabilization
(IES (EE) - 2007)
factor S0 ?
(1) They are real numbers at audio frequencies
(IES (EE) - 2007)
(2) They are easy to measure
RE
(3) They vary widely with temperature (a)  (b)  R B
RB  RE RE
Select the correct answer using the code given
below: 1
(c)  (d) RE
(a) 1 and 2 only (b) 2 and 3 only 
RE RB  RE
(c) 1 and 3 only (d) 1, 2 and 3 only

84
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

104. Following transistor parameters were measured (IES (EE) - 2009)


at IC  5 mA , VCE  10V , (a) 120 mW (b) 240 mW
(c) 300 mW (d) 360 mW
h fe  100. A1   10 at10M rad / s. What is

the value for  Ce  Cc  , if the unity - gain


108. A resistance R 1 is connected across the
gm
frequency T  ? collector and base of a BJT amplifier of gain -
Ce  Cc A(A > 0). The input impedance of the amplifier
(IES (EE) - 2007) will consist of transistor internal resistance rb'e
(a) 20 nF (b) 2 nF shunted by which one of the following?

(c) 5 pF (d) 5 nF (IES (EE) - 2008)


(a) Rf (1 + A) (b) Rf (1 – A)

105. The maximum junction - temperature of a (c) Rf / (1 + A) (d) Rf / (1 – A)


transistor is150 o C and the amount temperature
is 25o C . If the total thermal impedance is 109. Which one of the following statements is correct
in respect of BJT?
1o C / W , what is the maximum power
dissipation? (IES (EE) - 2006)
(IES (EE) - 2008) (a) Avalanche multiplication starts when the
reverse biased collector - base voltage
(a) 1 / 175 W (b) 175 W
VCB equals the avalanche breakdown
(c) 125 W (d) 1/125 W
voltage BVCBO

106. An emitter in a bipolar junction transistor is (b) The early effect starts as soon as punch -
doped much more heavily than the base as it through occurs in a transistor
increases the (c) The small signal current gain h fe  large
(IES (EE) - 2005)
signal current gain h FE when
(a) Emitter efficiency
n FE / IC  0
(b) Base transport factor
(d) In the CE mode, a transistor can be cut
(c) Forward current gain
off by reducing IB to zero
(d) All the three given above

110. A switch circuit using the transistor is shown in


107. A transistor has a maximum power dissipation
the figure below. The most dominant speed
limit of 300 mW for ambient temperature up to
limitation is brought by
25o C . If the maximum allowable junction
(IES (EE) - 2001)
temperature is 175o C then what is the limit of
the device in an ambient temperature of 55o C ?

85
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

113. Consider the following with reference to a CE


+5 V transistor amplifier.

2 K 1. The use of negative feedback


2. The conversion of d.c power to a.c
100 K V out 3. High voltage and current gains
V in
4. The use of a step - up transformer

+5 V
The power gain is due to
0
(IES (EE) - 2003)
(a) 1 and 2 (b) 2 and 3
(c) 1 and 3 (d) 1 and 4
(a) rise time (b) fall time
(c) storage time (d) delay time
114. An amplifier of gain A is bridged by a
capacitance C as shown below.
111. A circuit using the BJT is shown in the below
figure, the value of β is
C

+10 V

5 k
A
VB=1V
VE=1.7V
100 k
5 k
The effective input capacitance is
-10 V (IES (EE) - 2002)
(a) 120 (b) 150 (a) C/A (b) C(1-A)
(c) 165 (d) 166 (c) C(1+A) (d) CA

112. Early effect in BJT refers to 115. Consider a silicon transistor connected as a
(IES (EE) - 2002) common emitter amplifier as shown below. The
quiescent collector voltage of the circuit is
(a) avalanche breakdown
approximately
(b) thermal runaway
(IES (EE) - 1997, 2003)
(c) base narrowing
(d) zener breakdown
86
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

In a transistor
+20V
(IES (EE) - 2005)
10 K 10K (a) ICBO is greater than ICEO and does not
depend upon temperature
+
=100 -V0 (b) ICBO is greater than ICO and doubles for
Vi
every ten degrees rise in temperature
(c) ICBO is equal to ICO and doubles for every
5K  ten degrees rise in temperature
(d) ICEO is equal to ICO and doubles for every
0V ten degrees rise in temperature.

(a) 6.67 (b) 10 V


118. In the difference amplifier as shown below, the
(c) 14 (d) 20 V differential output
(IES (EE) - 2010)
116. In the circuit as shown below, the ratio of
25 V
V0 to  V2  V1  would approximately (neglecting
constant due to VCC ) be
1K 1K
(IES (EE) - 2003)

+VCC
V01 V02

RC V1 V2

V0

Vi
I0=10 mA

RE
+
Vo
V C2 
 VC1 for V1  5V, V2  0 V is
-

(a) 0 V (b) 5 V
(a) RC / RE (b) R E / R C (c) 10 V (d) 15 V

(c) R C / R E (d)  R E / R C
119. When a transistor is used in switching mode
then what is the turn-on time?
117. Which one of the following statements is (IES (EE) - 2009)
correct?

87
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) Sum of delay time and rise time and IC corresponding to the opearating point?
(b) Sum of rise time and storage time
V CC= + 10 V
(c) Sum of delay time and storage time
(d) Sum of rise time and fall time 27 V
200 K

120. The Si transistor as shown in the circuit below


has   50 and negligible leakage current. If
VCC  18V, VEE  4V, R E  200,
R C  4k, R B  72k , what is the value of
the quiescent collector current
(IES (EE) - 2009)
(IES (EE) - 2009)
(a) 4.6 V and 1.98 mA

V CC (b) 4.7 V and 2.00 mA


(c) 5.4 V and 1.56 mA

RC (d) 4.2 V and 2.1 mA

123. β of a BJT varies from 15 to 65. RL =10 Ω ,


VCC = 120V and VBB = 8V. if VCE(sat) = 1.5V
and VBE(sat) = 1.75V, then what is the value of
RB RE RE RB that will result in saturation with an overdrive
factor of 10?
-V EE
(IES (EE) - 2009)

(a) 1.1 mA (b) 2 mA


(c) 5 mA (d) 3.6 mA RL

121. In a certain self biased Si npn transistor the d.c.


RB VCE
base voltage is 3.2 V then what is the d.c emitter VCC
voltage? (Assume the transistor is in linear - IB VBE
V BB
active mode)
(IES (EE) - 2009)
(a) 7.9  (b) 0.79 
(a) 0.7 V (b) 2.5 V
(c) 3.2 V (d) 3.9 V (c) 79  (d) 7.9 k

122. In the below circuit as shown β  99, 124. Match List - I (Hybrid parameter) with
List - II (Units/definitions) and select the correct
VBE  0.6V, then what are the values of VC answer using the codes given below the lists:
88
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(IES (EE) - 2001) 127. For the circuit shown in the below figure,
List - I assuming β  100 for the transistor, the transistor
will be in
A. hie
(IES (EE) - 2001)
B. hfe
C. hre +10 V
D. hoe 20 K 8K
List - II
Output
1. Forward current transfer ratio
2. Ohms Input
3. Ohms
10 K 2K
4. Reverse voltage transfer ratio
Codes :
A B C D (a) Cut off region
(a) 2 1 3 4 (b) inverse active region
(b) 1 2 4 3 (c) active region
(c) 1 2 3 4 (d) saturation region
(d) 2 1 4 3
128. Figure shows a composite switch consisting of
a power transistor (BJT) in series with a diode.
125. An amplifier having an output resistance
Assuming that the transistor switch and the diode
of 4 gives an open circuit output voltage of are ideal, the I-V characteristic of the composite
6V(rms). The maximum power that it can switch is
deliver to a load is
(IES (EE) - 2001) + V -
(a) 1.5 W (b) 2.25 W
(c) 2.4 W (d) 9W

126. Active load is used in the collector of the


differential amplifier of an op-amp to
(IES (EE) - 2001) I

(a) increase the output resistance


(b) increase the differential gain Ad
(a) V
(c) increase maximum peak to peak output
voltage
(d) eliminate load resistance from the circuit
89
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

3. Large size
I
4. Very high conductivity
Codes :
V
(b) A B C D
(a) 1 4 2 3
(b) 4 1 2 3
(c) 4 1 3 2
I
(d) 1 4 3 2

V
130. In the circuit shown in the given figure, assume
(c) that the capacitor C is almost shorted for the
frequency range of interest of the input signal.
Under this condition, the voltage gain of the
amplifier will be approximately
Given hfe = 100, hie = 1k
I
(IES (EC) - 1996)

(d) V

129. Match List-I (Regions of bipolar transistor in a


(a) 0.33 (b) 0.5
monolithic IC) with List-II (Physical properties)
and select the correct answer using the codes (c) 0.66 (d) 1
given below the lists :
(IES (EC) - 1996) 131. Match List-I with List-II and select the correct
List-I answer using the codes given below the lists:
A. Emitter (IES (EC) - 1996)
B. Base List-I
(Name of the electronic circuit)
C. Collector
A. Darlington amplifier
D. Substrate
B. Cascade amplifier (FET)
List-II
C. Common gate amplifer
1. Moderate resistivity
D. Differential amplifier
2. Very high resistivity
90
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

List-II 134. The circuit shown in the given figure is a


(Special characteristic) (IES (EC) - 1996)
1. Low input impedance
2. Low output impedance
3. Low input capacitance but high Rin
4. Large common mode rejection
Codes :
A B C D
(a) 1 2 3 4
(b) 1 2 4 3
(c) 2 1 3 4
(d) 2 3 1 4 (a) monostable multivibrator
(b) frequency division circuit
132. Consider the following statements : (c) Miller sweep circuit
In a series transistor regulator the regulation (d) bootstrap sweep circuit
factor and output resistance can be improved
by
135. The approximate value of input impedance of
1. increasing hfe of the series transistor a common emitter amplifier with emitter
2. increasing hfe of the shunt transistor resistance Re is given by

3. increasing the external resistance R (IES (EC) - 1997)


connected between the collector and base (a) hie + A1 Re (b) hie + (1+hfe) Re
of the series transistor
(c) hie (d) (1 + hfe) Re
Of these statements
(IES (EC) - 1996) 136. The circuit diagram shown in the figure consists
of transistors in :
(a) 1 and 2 are correct
(IES (EC) - 1997)
(b) 2 and 3 are correct
(c) 1 and 3 are correct
(d) 1, 2 and 3 are correct

133. If α = 0.995, IE = 10mA and Ico = 0.5 mA,


then Iceo will be
(a) Parallel connection
(IES (EC) - 1997)
(b) Cascode connection
(a) 100  A (b) 25  A
(c) Darlington connection
(c) 10.1 mA (d) 10.5 mA
(d) Cascade connection
91
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

137. The ‘h’ parameters of the circuit shown in the C. ree 3. 100 
figure are : hib= 25 W, hfb= 0.999 and
hob= 10–6W. The voltage gain is D. Cbe 4. 100 pF

(IES (EC) - 1997) 5. 3 pF


Codes :
A B C D
(a) 3 2 1 4
(b) 3 2 1 5
(c) 1 3 2 4
(d) 1 3 2 5

(a) 0.999 (b) 1.98 140. The model of a transistor in the common emitter
(c) 2.0 (d) 400 connection is shown in the following figure:
(IES (EC) - 1998)
138. In the case of the circuit shown in the figure,
the collector current IC will be
(IES (EC) - 1997)

Match List-I (Parameters) with List-II (Values)


and select the correct answer using the codes
given below the lists:
List-I List-II
A. h22 1. rb + re
(a) 2.26 mA (b) 1.85 mA
B. h11 2.  cb
(c) 0.375 mA (d) 0.185 mA
1
C. h21 3. re  rd
139. Match List-I (Transistor parameter) with
List-II (Typical value) and select the correct Codes :
answer using the codes given below the lists :
A B C
(IES (EC) - 1997)
(a) 3 2 1
List-I List-II
(b) 1 3 2
A. rbb 1. 80 k (c) 2 3 1
B. rbe 2. 1 k (d) 3 2 1

92
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

141. Match List-I (Models of BJT) with List-II


(Applications) and select the correct answer
using the codes given below the lists:
(IES (EC) - 1998)
List-I
A. Hybrid model
B. Hybrid pi-model
C. S-parameter
D. Ebers-Moll model
(a) 2 mA (b) 1 mA
List-II
1. Microwave measurements (c) 0.5 mA (d) 2.5  A

2. Coupled diode
3. Low frequency 144. A junction transistor operating at room
temperature with Ic= 2mA where kt/q = 25 mV
4. High frequency
has β = 100. The values of the parameters gm
Codes : in mhos and r in ohms will be respectively
A B C D (IES (EE) - 1997)
(a) 4 3 1 2 (a) 0.04 and 2500 (b) 0.08 and 1250
(b) 3 4 2 1 (c) 0.5 and 800 (d) 0.08 and 5000
(c) 3 4 1 2
(d) 4 3 2 1 145. In the case of a BJT amplifier, bias stability is
achieved by
(IES (EE) - 1998)
142. If  = 0.98, Ico = 6 μA and Iβ = 100 μA for a
transistor, then the value of Ic will be (a) keeping the base current constant

(IES (EE) - 1997) (b) changing the base current in order to keep
the Ic and VCB constant
(a) 2.3 mA (b) 3.1 mA
(c) keeping the temperature constant
(c) 4.6 mA (d) 5.2 mA
(d) keeping the temperature and the base
current constant
143. A difference amplifier is shown in the figure.
Transistor Q1 and Q2 have identical parameters.
146. The best approximation for Vc in the circuit
Assuming that VBE = 0.7 V and β = 200 for
shown in the figure will be (assume β to be high)
each transistor and given that Vs1 = Vs2 = 0,
the value of the collector current ic will be (IES (EE) - 1998)
(IES (EE) - 1997)

93
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Codes
A B C D
(a) 1 2 3 4
(b) 1 3 2 4
(c) 1 4 2 3
(d) 2 3 4 1

(a) 4 V (b) 6.8 V


148. Of the various capacitances associated with a
(c) 8.7 V (d) 10.7 V junction transistor, the gain bandwidth product
is affected to a maximum extent by
147. With reference to the equivalent circuit of a (IES (EC) - 1996)
transistor shown in the given figure, match List- (a) base-collector parasitic capacitance
I with List-II and select the correct answer
using codes given below the lists : (b) base-collector space charge layer
capacitance
(IES (EC) - 1996)
(c) base-emitt er space charge layer
capacitance
(d) base-emitter diffusion capacitance

149. The modulation of effective base width by


collector voltage is known as early Effect,
List - I
Hence reverse collector voltage
(a) h11
(IES (EC) - 1996)
(b) h12
(a) increases both alpha and beta
(c) h21
(b) decreases both alpha and beta
(d) h22
(c) increases alpha but decreases beta
List - II
(d) decreases beta but increases alpha
 rc  rb
1.  re  rb   rb
rc  rb
150. Which is the correct sequence of the following
steps in the fabrication of a monolithic, bipolar
rb   rc junction transistor ?
2. rc  rb
(IES (EC) - 1998)
1 1. Emitter diffusion
3. rc  rb 2. Base diffusion
3. Buried layer formation
rb
4. rc  rb 4. Epi-layer formation
94
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Select the correct answer using the codes given (IES (EC) - 1998)
below : (a) storage time (b) turn-off time
(a) 3, 4, 1, 2 (b) 4, 3, 1, 2 (c) turn-on time (d) delay time
(c) 3, 4, 2, 1 (d) 4, 3, 2, 1

155. In the circuit shown in the figure, if


151. If Rs is the source resistance, the output
RL = RC = 1 k , then the values of Vo will be
resistance of an emitter-follower using the
simplified hybrid model would be (IES (EC) - 1998)
(IES (EC) - 1998)

hie  Rs hie  Rs
(a) 1  hf 0 (b) hf 0

1 1
(c) Rs  (d)
hoe hoe
(a) 4.55 V (b) 2.4 V
(c) 1 V (d) zero
152. For a transistor amplifier with self-biasing
network, the following components are used:
R1 = 4 k , R2 = 4 k and Rc = 1 k 156. Assume VBE = 0.7V and   50 for the
transistor in the circuit shown in the figure. For
The approximate value of the stability factor
VCE = 2V, the value of RB is
‘S’ will be
(IES (EE) - 1999)
(IES (EC) - 1998)
(a) 4 (b) 3
(c) 2 (d) 1.5

153. In a transistor amplifier, the reverse saturation


current ICO
(IES (EC) - 1998)
(a) doubles for every 10°C rise in
temperature
(a) 200 k (b) 242 k
(b) doubles for every 1°C rise in temperature
(c) increases linearly with temperature (c) 283 k (d) 300 k

(d) doubles for every 5°C rise in temperature


157. Consider the following statements:

154. A transistor is operated as a non-saturated


switch to eliminate
95
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

The circuit in the figure is the high frequency 159. Consider the following features regarding an
equivalent of a CE amplifier. If the upper cut- amplifier:
1 1. Voltage gain being less than one.
off frequency ωH  where T = RC, then
T 2. High input impedance.
1. R = R s + rπ 3. High output impedance
4. High current gain
2. R = R s parallel rπ
Which of these are the characteristic features
3. C = C + r of an emitter follower amplifier ?
(IES (EE) - 2000)
4. C = C + C 1  g m R1 
(a) 1, 2 and 3 (b) 1, 2 and 3
Which of these statements are correct ? (c) 1 and 3 (d) 2, 3 and 4
(IES (EE) - 1999)

160. An amplifier circuit has an overall current gain


of-100 and an input resistance of 10 k with
a load resistance of 1kW. The overall gain of
the amplifier is
(IES (EE) - 2000, 2013)
(a) 5 dB (b) 10 dB
(c) 20 dB (d) 40 dB
(a) 1 and 3 (b) 1 and 4
(c) 2 and 3 (d) 2 and 4
161. The input resistance of a common emitter stage
can be increased by
158. In the pnp transistor circuit shown in the given 1. unbypassing emitter resistance
figure, the transistor is in saturation with values
2. bootstrapping
of Vbe = 0.7V, Vce(sat) = 0.3 V and  min = 20.
3. biasing it at low quiescent current
The value of IC will be
4. using compounded BJTs
(IES (EE) - 2000)
The correct sequence in descending order of
the effectiveness of these methods is
(IES (EC) - 1999)
(a) 2, 4, 1, 3 (b) 4, 3, 2, 1
(c) 2, 4, 3, 1 (d) 4, 2, 3, 1

162. The collector voltage V C of the circuit shown


(a) 4.7 mA (b) 5.3 mA in the given figure is approximately
(c) 8.6 mA (d) 10 mA
96
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(IES (EC) - 1999) (a) 2, 1, 4, 3 (b) 1, 2, 4, 3


(c) 2, 1, 3, 4 (d) 1, 2, 3, 4

165. A common emitter amplifier circuit is shown in


the given figure
(IES (EC) - 2000)

(a) 2 V (b) 4.6 V


(c) 8 V (d) 8.6 V

163. The voltage V0 of the circuit shown in the given


figure is
(IES (EC) - 1999)
The slope of AC load line is

 1 1   1 
(a)   R  R  (b)   R  R 
 L C   L C 

1 1
(c)  R (d) RC
L

166. An amplifier circuit is shown in the given figure:


(IES (EC) - 2000)
(a) 5 V (b) 3.1 V
(c) 2.5 V (d) zero

164. Consider the following circuit configurations


1. Common emitter
2. Common base
3. Emitter follower
4. Emitter follower using Darlington pair
The correct sequence in increasing order of the The voltage gain (V0 / Vs) is
input resistance of these configurations is (a) 4/3.33 (b) 100
(IES (EC) - 2000) (c) 150 (d) 160

97
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

167. Consider the following statements regarding the (a) 50 k (b) 0.98 k
bootstrap biasing arrangement for a BJT emitter
follower: (c) 50 M (d) 0.98 M
1. The input impedance is very high.
2. The voltage gain is exactly equal to one 170. CE configuration is the most preferred transistor
configuration when used as a switch because it
3. The output impedance is equal to zero
(IES (EC) - 2000, 2008)
Which of these statements is correct ?
(a) requires only one power supply
(a) None (b) 2 alone
(b) requires low voltage or current
(c) 3 alone (d) 1 alone
(c) is easily understood by every one
(d) has small ICEO
168. In the circuit shown in the given figure, the
approximate voltages at the transistor
(IES (EC) - 2000) 171. In a single-stage RC coupled common emitter
amplifier, the phase shift at the lower 3dB
frequency is
(IES (EC) - 2001)
(a) zero (b) 135°
(c) 180° (d) 225°

172. In the circuit shown below, If R1 >> RP and the


impulses can completely saturate transistor Q1,
then the output voltage V0 will be
(a) base and emitter respectively are –8V and
–7.3 V (IES (EC) - 2002)
(b) base and collector respectively are –8V
and –5 V
(c) collector and emitter respectively are
–8V and –7.3 V
(d) base, emitter and collector respectively
are –8V , –7.3 V and –5V

169. If a common emitter amplifer with an emitter


resistance Re has an overall transconductance (a)
gain of –1 mA/V, a voltage gain of –4 and
desensitivity of 50, then the value of the emitter
resistance Rs would be (b)

(IES (EC) - 2000)

98
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Codes:
(c)
A B C D
(a) 3 4 1 2
(d) (b) 4 3 1 2
(c) 3 4 2 1
(d) 4 3 2 1
173. In the circuit shown
(IES (EC) - 2002)
175. The biasing shown in the below circuit is
(IES (EC) - 2003)

the transistor is biased at


(a) 0 mA (b) 6 mA
(c) 3.9 mA (d)  (a) Emitter bias
(b) Self bias
174. Match List-I (Circuit) with List-II (Property) (c) Potential divider bias
and select the correct answer using the codes
(d) Bootstrap bias
given below the lists :
(IES (EC) - 2003)
176. Which of the following main properties of a
List-I
bipolar junction transistor make it necessary for
A. R-C coupled single-stage amplifier the transistor to have bias stabilization ?
B. Emitter follower 1. Variation of VBE with temperature
C. Common base amplifier 2. Variation of hFE with temperature
D. Darlington amplifier 3. Variation of ICO with temperature
List-II 4. Variat ion of h FE with transist or
1. Beta multiplier replacement
2. Constant current source 5. Variatio n of V BE with transistors
replacement
3. Very high input impedance
6. Variat ion of I CO with transist or
4. Phase inverter with voltage gain replacement
Select the correct answer using the codes given
below :
99
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(IES (EC) - 2003)


(a) 1, 2 and 6 (b) 1, 3 and 4
(c) 2, 3 and 5 (d) 3, 4, 5 and 6

177. The internal resistance of a current source used


in the model of a BJT while analyzing a circuit
using BJT is (IES (EC) - 2004)
(IES (EC) - 2003) Which one of the following statements is
(a) Very high correct?

(b) Very low (a) Circuit 1 is parallel connection and Circuit


2 is Darlington connection
(c) Zero
(b) Circuit 1 is cascode connection and
(d) Of the order of a few mega-ohms Circuit 2 is Darlington connection
(c) Circuit 1 is Darlington connection and
178. For a BJT in common emitter mode, base to Circuit 2 is cascode connection
emitter capacitance  Cπ  is ten times the (d) Circuit 1 is cascode connection and
Circuit 2 is parallel connection
collector to base capacitance  Cμ  . Transistor
is biased at quiescent collector current ICD =
181. Consider the following circuit.
1mA and its short circuit unity gain frequency
is 0.909 M (rad/s). What is the C π value ? (IES (EC) - 2004)

(IES (EC) - 2003)


(a) 6.45 nF (b) 44 nF
(c) 40 nF (d) 7.1 nF

179. a bipolar junction transistor is in saturation


region. Given VCC = 10 V.RC = 1 k , hFE =
100 and VCE sat = 0.3 V. What is the collector
current in saturation ?
What is voltage difference between collector
(IES (EC) - 2004)
and emitter (VCE) in the above circuit ?
(a) 10 mA (b) 9.7 mA
(a) 10/3 V (b) 0V
(c) 0 mA (d) 1 mA
(c) 5V (d) 3V

180. Consider the following circuits :


182. Consider the NPN transistor circuit shown
below:

100
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(IES (EC) - 2004) decrease or all of them increase) ? Select the


correct answer using the code given below:
(IES (EC) - 2006)
(a) only 1 and 2 (b) only 2 and 3
(c) only 1 and 3 (d) 1, 2 and 3

186. The transistor circuit shown in the figure given


below is to function as an amplifier. If ICQ =
What is the output voltage V0 in the above
3mA, what is the value of VCC (approximate)?
circuit
(a) 0 V (b) 12 V
(c) 9 V (d) 5 V

183. When a voltage divider biased amplifer has its


Q-point near to the middle of the dc-load line,
What is the maximum unclipped peak-to-peak
output voltage ?
(IES (EC) - 2005) (IES (EC) - 2006)
(a) VCEQ (b) ICQrL (a) 15 V (b) –15 V
(c) 2ICQrL (d) 2VCEQ (c) –10 V (d) –13.5 V

184. What is the phase shift between the input and 187. When used for amplification, the output port
output voltage in a common-base small signal side of a BJT behaves as controlled current
amplifier (assuming ideal coupling and bypass source. According to the above, the variation
capacitors)? of which one of the following does not change
(IES (EC) - 2006) the output current of an ideal BJT ? (The BJT
(a) 180° (b) –180° is being used in a common emitter amplifier
circuit)
(c) 0° (d) None of above
(IES (EC) - 2006)
(a) Load resistance
185. Consider the following parameters of a hybrid-
(b) Collector to base bias voltage
π equivalent circuit of BJT :
1. Transconductance (gm) (c) Both load resistance and collector to base
bias voltage
2. hfe
(d) Base-emitter bias voltage
3. hie
Which of the above parameters vary with
temperature in similar manner (all of them 188. Consider the following statements in respect
of a CC amplifier:
101
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

1. It performs a resistance transformation (a) Input frequency variation


from low to high resistance (b) Noise at the input
2. Its current gain is close to unity (c) Parasitic capacitances
3. Its voltage gain is close to unity (d) Power supply fluctution
4. Its frequency range is higher than that of a
CE-stage
192. For a CE amplifier, d.c. load line is which one
Which of the statements given above are of the following points ?
correct?
(IES (EC) - 2007)
(IES (EC) - 2006)
(a) IC versus VCE for a given value of (RC +
(a) 1, 2 and 4 (b) 1 and 3 RE) and VCC
(c) Only 2 and 4 (d) 3 and 4 (b) IB versus VEE for a given value of (RC +
RE) and VCC
189. A CE-amplifier has RL = 10 k . Given hie = (c) IB versus VCE for a given value of IB
1 k , hfe = 50, hre = 0 and 1/hoe = 40 k (d) IC versus VCB for a given value of IE
What is the voltage gain ?
(IES (EC) - 2006) 193. Consider the following statements.
(a) –500 (b) –400 The basic purpose of bias stabilization in a
(c) –50 (d) –40 transistor circuit is to
1. Increase the voltage and current gain of
the amplifier.
190. Which of the following features are offered by
a bipolar junction transistor amplifier in 2. make the operating point of the transistor
Darlington connection ? independent of temperature variation of
the transistor
1. High voltage gain
3. make the operating point independent of
2. High input impedance the replacement of the same type, Ge or
3. High current gain Si.
Select the correct answer using the codes given Which of the statements given above are
below: correct?
(IES (EC) - 2007) (IES (EC) - 2007)
(a) 1 and 2 only (b) 2 and 3 only (a) 1 and 2 only (b) 2 and 3 only
(c) 1 and 3 only (d) 1, 2 and 3 (c) 1 and 3 only (d) 1, 2 and 3

191. Operating point shift can occur in an amplifier 194. Match List-I (Electronic Circuit) with List-II
due to which one of the following ? (Characteristic) and select the correct answer
using the codes given below the lists:
(IES (EC) - 2007)

102
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(IES (EC) - 2007) 196. For BJT, early voltage VA is 100V. In common
List-I emitter configuration, quiescent VCE is 10V.
What percentage change in quiescent IC would
A. CE occur, if early voltage VA is made  ?
B. CB (IES (EC) - 2008)
C. CC (a) 10% (b) 20%
D. Darlington Pair (c) 5% (d) 0%
List-II
1. The circuit introduces a phase inversion 197. The maximum power dissipation capacity of a
of 180° transistor is 50 mW. If the collector emitter
2. The circuit is rarely used voltage is 10V. What is the safe collector
current that can be allowed through the
3. The name, emitter follower is also used transistor ?
for the circuit
(IES (EC) - 2009)
4. The circuit consists of two circuits
connected in cascade (a) 5 mA (b) 2.5 mA
Codes: (c) 10 mA (d) 25 mA
A B C D
(a) 1 2 3 4 198. Why npn-transistors are preferred over pnp-
transistors ?
(b) 2 1 3 4
(IES (EC) - 2009)
(c) 2 1 4 3
(a) Leakage current in npn-transistors is less
(d) 1 2 4 3 than pnp-transistors
(b) Mobility of majority carriers in npn-
195. Consider the following statements: transistors is greater than the mobility of
Bias stabilization in a BJT circuit is very majority carriers in pnp-transistors
important, because it (c) Bias voltage required in npn is less than in
1. provides high voltage and current gain pnp-transistors

2. ensures large bandwidth of the amplifier (d) Bias voltage required in npn is greater than
in pnp-transistors
3. keeps the operating point unchanged with
change of temperature.
Which of the above statement(s) is/are correct? 199. Consider the following statements:

(IES (EC) - 2008) To draw a.c. equivalent circuit of a transistor,


all
(a) 1 and 2 (b) 2 and 3
1. d.c. sources are shorted
(c) 3 only (d) 1 and 3
2. a.c. sources are shorted
3. d.c. sources are opened

103
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

4. a.c. sources are connected to d.c. sources (IES (EC) - 2009)


Which of the above statements is/are correct? (a) h-parameter model
(IES (EC) - 2009) (b) y-parameter model
(a) 2 and 4 (b) 1 and 2 (c) s-parameter model
(c) 1 only (d) 3 and 4 (d) hybrid- π model

200. Consider the following statements: 203. Which of the following describe the correct
The bias stability of an emitter-bias amplifier properties of an emitter follower circuit ?
circuit improves by 1. It is a voltage series feedback circuit
1. decreasing the value of RB. 2. It is a current series feedback circuit
2. increasing the value of RE. 3. Its voltage gain is less than unity.
3. decreasing the value of RE. 4. Its output impedance is very low.
4. increasing the value of RB. Select the correct answer from the codes given
5. Increasing the value of RC. below :

Which of the above statements are correct ? (IES (EC) - 2009)

(a) 1 and 2 (b) 2 and 3 (a) 1, 3 and 4 (b) 2, 3 and 4

(c) 3 and 4 (d) 4 and 5 (c) 2 and 3 only (d) 2 and 4 only

201. Which of the following will be true for a CE 204. Which of the following conditions must be
transistor amplifier if the emitter resistor value satisfied for a transistor to remain under
is made equal to zero ? saturation ?

1. Its gain will increase. 1. Its collector to base junction should be


under forward bias.
2. Its stability will increase
2. Its collector to base junction should be
3. Its gain will decrease under reverse bias.
4. Its stability will decrease 3. Its emitter to base junction should be under
Select the correct answer from the codes given reverse bias.
below: 4. Its emitter to base junction should be under
(IES (EC) - 2009) forward bias.
(a) 1 and 2 (b) 2 and 3 Select the correct answer from the codes given
below :
(c) 3 and 4 (d) 1 and 4
(IES (EC) - 2009)
(a) 1 and 2 (b) 1 and 3
202. Which of the transistor models is most preferred
for the analysis of a transistor circuit both at (c) 2 and 3 (d) 1 and 4
mid-band and at high frequencies ?

104
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

205. For the transistor circuit shown in the figure, hi = 2 k (hre = hoe = 0), the voltage
e
when amplification of the amplifier is nearly equal to
(IES (EC) - 2011)
(a) 500 (b) 200
(c) 100 (d) 50

208. For smooth and reliable operation of an amplifier


using BJT, it is necessary that the circuit must
be properly designed from the point of view of
bias stabilization, because
1. Reverse saturation current ICO increases
1. Vin > 0, transistor is OFF
with rise in temperature
2. Vin < 0, transistor is OFF
2. VBE decreases with rise in temperature
IC 3. hFE or  changes with change of
3. IB 
h FE , transistor is ON temperature and replacement of the
transistor
IC
4. IB 
h FE , transistor is ON 4. hFE or  changes with change in collector
supply voltage
Which of these statements are correct ?
Which of these statements are correct ?
(IES (EC) - 2011)
(IES (EC) - 2011)
(a) 1, 2, 3 and 4 (b) 1 and 2 only
(a) 1, 2 and 3 only (b) 1, 2 and 4 only
(c) 2 and 3 only (d) 3 and 4 only
(c) 2, 3 and 4 only (d) 1, 2, 3 and 4

206. A CE amplifier has an unbypassed emitter


209. Diodes are used to compensate which of the
resistance of 0.5 k and a collector load of following transistor circuit parameters ?
5 k . The  of the transistor is 100 and it is 1. ICO
operating at 1 mA. The voltage gain of the stage
at mid band will be of the order of 2. VBE

(IES (EC) - 2011) 3. 


(a) 200 (b) 100 (IES (EC) - 2012)
(c) 10 (d) 50 (a) 1 and 2 only (b) 2 and 3 only
(c) 1 and 3 only (d) 1, 2 and 3
207. A common emitter transistor amplifier has a
collector load of 10 k . If its hf = 100 and 210. The output impedance of a BJT under common
e
collector configuration is

105
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(IES (EC) - 2012) (IES (EC) - 2012)


(a) low (b) high (a) 98 (b) 0.02
(c) medium (d) very high (c) 49 (d) 0.49

211. For common collector amplifier, the current gain 215. A CE amplifier has a resistor RF connected
(AI) is between collector and base RF = 40 k . RC
(IES (EC) - 2012) = 4 k . Given hfe = 50, rπ  1k the output
1  h fe resistance is
(a) 1  h fe (b) 1  h R (IES (EC) - 2012)
oe L

(a) 40 k (b) 20 k
1  h fe 1  h fe
(c) h oe h ie (d) 1+h R (c) 4 k (d) 0.66 k
ie L

212. For a transistor used as a switch, td is delay 216. If ICEO = 410 μ A, ICBO = 5 μ A and IB = 30 μ A,
time, tr is rise time, ts is storage time and tf is fall then the collector current is
time. Then turn-on time tON and turn-off time (IES (EC) - 2013)
tOFF are respectively
(a) 415 μ A (b) 440 μ A
(IES (EC) - 2012)
(c) 445 μ A (d) 2.64 μ A
(a) (td + ts) and (tr + tf)
(b) (td + tf) and (ts + tr)
217. The transistor as shown in the circuit is operating
(c) (tr + ts) and (td + tf)
in
(d) (td + tr) and (ts + tf)
(IES (EC) - 2013)

213. A transistor is said to be usefull to be configured


as an amplifer when its  is
(IES (EC) - 2012)
(a) Less than 0
(b) Between 0 and 1
(c) Between 1 and 50
(d) > 50 (a) Cut-off region
(b) Saturation region
214. A bipolar junction transistor with forward (c) Active region
current transfer ratio   0.98 , when working (d) Either in active or saturation region
in CE mode, provides current transfer ratio 
as
106
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

218. The transconductance gm of the transistor used 221. The common emitter current gain-bandwidth
in the CE amplifier shown in the below circuit, product of a transistor (fT) is defined as the
operating at room temperature is frequency at which
(IES (EC) - 2013) (IES (EC) - 2003)
(a) Alpha of the transistor falls by 3 dB
(b) Beta of the transistor falls by 3 dB
(c) Beta of the transistor falls to unity
(d) Power gain of the transistor falls to unity

222. Thermal runaway will take place if the quiescent


point is such that
(IES (EC) - 1999)
(a) 92 mA/V (b) 46 mA/V
(c) 184 mA/V (d) 25 mA/V 1
(a) VCE > VCC (b) VCE < VCC
2

219. Which of the following are essentials of a 1


(c) VCE < 2 VCC (d) VCE < VCC
transistor biasing circuit ? 2
(IES (EC) - 2013)
1. Proper zero signal collector current flow 223. To avoid thermal runaway in the design of an
2. VCE should not fall below 0.5 V for analog circuit, the operating point in the BJT
Germanium and 1V for silicon. should be such that it satisfies the condition
3. Ensure stabilization of operating point (IES (EC) - 1999)
4. Loading to the source.
(a) VCE  VCC / 2 (b) VCE  VCC / 2
(a) 1, 2 and 3 only (b) 1, 2 and 4 only
(c) 3 and 4 only (d) 1, 2, 3 and 4 (c) VCE  VCC / 2 (d) VCE  0.78 VCC

220. If an npn silicon transistor is operated at


224. The thermal run-away in a CE transistor
VCE = 5V and IC = 100 μ A and has a current
amplifier can be prevented by biasing the
gain of 100 in the CE connection, then the input
transistor in such a manner that
resistance of this circuit will be
(IES (EC) - 2013) (IES (EC) - 2000)

(a) 250  (b) 25 k VCC VCC


(a) VCE  (b) VCE 
2 2
(c) 250 k (d) 2500 k
VCC
(c) VCE  (d) VCE  0
2
107
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

225. The condition to be satisfied to prevent thermal (IES (EE) - 2012)


runaway in a transistor amplifier where (PC = (a) Emitter voltage
Power dissipated at Collector), TJ = Junction
temperature, TA = Ambient temperature,  = (b) Emitter current
Thermal resistance) is (c) Collector voltage
(IES (EC) - 2001) (d) Junction temperature

 PC 1  PC 1
(a)  (b)  T   229. A Bipolar Junction Transistor (BJT) works in
 Tj  A three regions:
1. Saturation
 PC 1  PC 1
(c)  T   (d)  T   2. Active
j A
3. Cut-off
If BJT is to be used in amplifier circuit, the
226. In a transistor biased in the active region, region it works in is/are
thermal runaway is due to
(IES (EE) - 2012)
(IES (EE) - 2006) (IES (EC) - 2012) (a) 1, 2 and 3 (b) 1 and 2 only
(a) Base emitter voltage V BE which (c) 2 only (d) 1 only
decreases with rise in temperature
(b) Change in reverse collector saturation
230. For a transistor, turn-off time is:
current due to rise in temperature.
(IES (EE) - 2011)
(c) Heating of the transistor
(a) Sum of storage time, and fall time
(d) Changes in β which increases with
temperature. (b) Maximum value of storage time
(c) Maximum value of fall time
227. An emitter follower regulator has the following (d) Sum of rise time and fall time
disadvantage
(IES (EE) - 2011)
231. In a common collector amplifier the voltage gain
(a) It does not provide high gain is :
(b) No provision exists for varying the output (IES (EE) - 2011)
voltage
(a) Constant
(c) Its output resistance is high
(b) Less than 1
(d) It cannot withstand high load current
(c) Varies with input voltage
(d) Varies with load impedance
228. Early effect is the modulation of effective base
width by
108
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

232. In a BJT, I CO = I CBO = 2 μ A. Given


α = 0.99, the value of ICEO is
(IES (EE) - 2013)
(a) 2 μ A (b) 99 μ A

(c) 198 μ A (d) 200 μ A

109
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Conventional Problems 03. If the transistor in fig. has high value of  and
01. In figure all transistors are identical and have a VBE of 0.65 the current I flowing through the 2
high value of beta. The voltage VDC is equal to kilo ohms resistance will be ____
___ (GATE (EC) - 1992)
(GATE (EC) - 1991)

04. In a transistor having finite β , the forward bias


across the base emitter junction is kept constant
02. Figure shows a common emitter amplifier.
and the reverse bias across the collector base
(GATE (EE) - 1991) junction is increased. Neglecting the leakage
across the collector base junction and the
depletion region generating current, the base
current will ____ (increase / decrease / remains
constant)
(GATE (EC) - 1992) (2M)

05. Emitter, base and collector regions, where in the


(a) Simplify the circuit by applying Thevenin’s doping concentrations are 1019/cm³, 1017/cm³ and
theorem to the biasing network R1 , R2 at 1015/cm³ respectively. The minority carrier
the base of the transistor. diffusion lengths in the emitter and the base regions
(b) Assuming Cs to be short for the frequency are 5 microns and 100 microns respectively.
range considered. Draw the small signal Assuming low level injection conditions and using
a.c. model of the circuit obtained in (a) the law of the junction, calculate the collector
by using the simple model for the transistor current density and the base current density due
shown in Figure. to base recombination. [Suitable approximations
may be made if required]. In all the regions of the
 V0  transistor
(c) Evaluate the small signal gain  V  of the
 i Dp=8cm² /sec, Dn=16cm²/sec, ni=1.5×1010/cm³,
amplifier. kT/q = 26 mV, q = 1.6 × 10–19C

110
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

09. In the common emitter amplifier shown in the


figure below, the transistor has a forward
current gain of 100 and a base-emitter voltage,
VBE = 0.6 volt. Assume ICO to be negligible.
Choose values of R1 and R2 such that the
transistor has a collector current of 1 mA and a
collector to emitter voltage of 2.5 V.
(GATE (EC) - 1994)

(GATE (EC) - 1992) (10M)

06. The two-port Darlington impedance booster


of Fig. uses identical transistors (hie = 1K, hfe =
100, hre = hoe = 0). Calculate the z - parameters 10. An npn transistor under forward-active mode
of the network (Use relevant approximations) of operation is biased at IC = 1 mA and has a
total emitter-base capacitance CK of 12 pF,
(GATE (EC) - 1992)
and the base transit time  F of 260 psec. Under
this condition, the depetion capacitance of the
emitter-base junction is __. [use VT = 26 mV]
(GATE (EC) - 1995)

11. A transistor having  = 0.99 and VBE = 0.7 V, is


used in the circuit of the figure is the value of the
07. The reverse saturation current of the collector collector current will be
base junction (ICBO) of a BJT is found to be 10nA (GATE (EC) - 1995)
at lower collector voltages. The low voltage
current amplification factor (  ) is 0.98. Find
reverse saturation current with base open (ICEO).
(GATE (EC) - 1993) (10M)

08. A Common Emitter transistor Amplifier has a


collector current of 1.0 mA when its base current
is 25  A at the room temperature. Its input
resistance is approximately equal to ___
(GATE (EC) - 1994)

111
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

12. A common-emitter amplifier with an external


capacitor CC connected across the base and
the collector of the transistor is shown in Fig.

Transistor data gm = 5mA/V, rπ  20K ,


C π = 1.5 pF and Cμ = 0.5 pF determine the
upper cutoff frequency fH of the amplifier
(GATE (EC) - 1996)
14. The transistor in the circuit shown in the figure is
so biased (dc biasing N/W is not shown) that the
dc collector current IC= 1mA. Supply is Vcc= 5V.
(GATE (EC) - 1997)

13. Figure shows a self bias transistor amplifier


using a silicon transistor with VCC = 20 V,
hFE = 400 and VBE = 0.65 V. The transistor
should be biased at V CE = 10 V and
The N/W components have following values,
ic = 0.6 mA. Find the values of resistances
Rc, Re, R1 and R2 such that it meets the following RC = 2 K , RS = 1.4 K , RE = 100  . The
specifications over the temperature range transistor has specifications, β  100 and base
25° C to 145°C.
spreading resistance r'bb  100 
Ys = Gs
KT
I C Assume = 25 mV
 10% q
IC
Evaluate input Resistance R1 for two cases. At a
VBE at 25°C = 650  50 mV frequency of 10KHz
ICO at 25°C = 5  A max.
(a) CE, the bypass capacitor across RE is
ICO at 145°C = 3.0  A max. 25 μF
Assume that the percentage change in IC due
to VBE and ICO is same (5 percent) (b) The bypass capacitor CE is removed
leaving RE unbypassed.
(GATE (EE) - 1996)

15. For a typical n-p-n transistor, as shown in Fig.


we have the following data available :
112
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) WC = 20 m and
Collector doping = 5 × 1018/cm³

(b) WE = 1 m and Emitter doping = 1019/cm³


(c) Base doping = 5 × 1015/cm³
(d) Minority carrier life time in the Base region is
 n = 5  sec
(GATE (EC) - 1997)
(GATE (EC) - 1998)

17. A bipolar junction transistor amplifier circuit is


shown in the figure. Assume that the current
source I bias is ideal, and the transistor has very

Under Punch-through condition the large β , rb = 0, and r0   .


VBC = 10V + Vbi volts. Determine the ac small-signal midband voltage
Here Vbi is the built in potential of Base-collector gain (V0 / Vs), input resistance (Ri), and output
junction. Emitter Injection efficiency can be resistance (R0) of the circuit.
assumed as 1 for this transistor.
Assume VT = 26 mV
Evaluate Base Width WB and the current gain 
[Standard data for this question is :

KT
q = 1.6 × 10–19 coloumbs; = 25 mV
q
For silicon at T = 300 K, Dn = 30 cm²/sec;
KS 0 = 10–12 F/em; ni = 1.5 × 1010/cm³]

16. In the circuit of fig. Determine the resistance Ro


seen by the output terminals ignore the effects of (GATE (EC) - 1999)
R1 and R2.

18. For the small signal BJT amplifier shown in


Figure, determine at 1 kHz, the following :
(GATE (EE) - 1999)
(a) quiescent collector current, Ic Q
(b) small signal voltage gain, (v0 / vi) ;

113
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(c) maximum possible swing of the collector


current.

(a) Draw the small signal equivalent circuit of


the amplifier
(b) Obtain an expression for Zi.
19. For the amplifier of given figure, IC = 1.3 mA, (c) Obtain an expression for Z0.
RC= 2 k , RE = 500  , VT = 26 mV, β  100 ,
VCC = 15V, Vs = 0.01sin(ωt)V and
21. A given NPN transistor has normal and inverse
Cb= Ce= 10 μF alpha values of 0.96 and 0.15 respectively. Its
(GATE (EC) - 2000) parasitic collector bulk resistance is 0  . The
transistor is connected in a circuit shown in fig.
find the resistance RB required to bring the
transistor to the threshold saturation (VCB = 0),
assuming the VBE = 0.7 V.

(a) What is the small-signal voltage gain,


Av = V0 / Vs ?
(b) What is the approximate Av if Ce is
removed ?
(c) What will V0 be if Cb is short circuited ? (GATE (EC) - ) (10M)

20. An emitter-follower amplifier is shown in the 22. (a) Determine VCE and IE for the following
figure, Zi is the impedance looking into the base network
of the transistor and Z0 is the impedance looking
(IES (EC) - 1996)
into the emitter of the transistor
(GATE (EC) - 2001)
114
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(b) For the network shown determine the


following parameters using the complete
hybrid equivalent model and compare
with the results obtained using the 24. In the transistor circuit shown below ICBO= 2μA
approximate model in which the effects at 20°C and doubles for every 10°C increase in
of hre and hoe are neglected. temperature.
(i) Z i and Z'i (IES (EC) - 1997)

(ii) Av (i) Find maximum allowable value of RB if


the transistor is to remain cut off at 75°C.
I0 l0 Assume VBE(cut off) = – 0.1 V.
(iii) Ai = I and Ai = l
i i (ii) If VBB= 1.0 V and RB= 50 KΩ , how high
(iv) Z0 may the temperature increase before the
transistor comes out of cut off ?
The h-parameters of the transistor are :
hfe = 110, hie = 1.6 K
hre = 2× 10–4, hoe = 20μΩ

25. Derive the expression for the voltage gain Av and


the resistance Rin of the amplifier shown. Find
the values of Av and Rin for the following values
of h parameters for the transistors:
hie = 1000W;
23. For the transistor circuit shown below determine
hfe = 100;
the voltage transfer charecteristic assuming
VCE,Sat= 0.2 V and VEE,on= 0.7 V hre = hoe = 0
(IES (EC) - 1996) (IES (EC) - 1997)

115
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

29. Describe the realisation of transistor type


monostable multivibrator
(IES (EE) - 1999)

30. For the monostable multivibrator calculate the


output pulse width for the design values of
RC = 2 k , RB = 20 k ; C = 0.1 μF and
26. Draw h-parameter equivalent circuit of a loaded VCC = 12V.
amplifier in common configuration and derive the
(IES (EE) - 1999)
expression for circuit gain, voltage gain, input
impedance, output impedance, overall voltage
gain and current gain. 31. For the circuit shown in Fig. VBE = 0.7V,
(IES (EE) - 1997)  = 50 and VCEQ = 4 V. Determine RE and the
stability factor S.
27. What are the main purpose for which a common
collector amplifier may be used ?
(IES (EE) - 1997)

28. In the circuit given in figure 2 below, the Si


transistor used has β  30 and ICBO= 10nA.
Determine
(i) the value of Vo for Vi= 12 V and R= 20K;
and show that the transistor is in saturation
(ii) the minimum value of R for the transistor
to remain in the active region for Vi= 12V
(IES (EC) - 2012)
(iii) the value of Vo for Vi= 1V and R= 15K
(IES (EE) - 1998) 32. Explain the following statement:
In the active region, as temperature increases
the current in BJT increases.
(IES (EC) - 2012)

33..

116
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

The switching waveforms of collector current


IC and collector to emitter voltage VCE of a
power BJT operating at 10 kHz are shown in
the above figure.
(IES (EC) - 2012)
If VCC = 200V; ICSat = 10A,
turn-on time tON = 2 microsecond,
turn-off time tOFF = 5 microsecond. Determine,
(i) looking at the diagram, the point at which
the peak power loss will occur.
(ii) average power loss during tON and tOFF.
(iii) total average switching power loss of the
device.
Neglect VCE(sat), collector to emitter leakage
current ICEO and power loss due to base
current.

117
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

ANSWER KEY
01. c 40. d 79. c 118. c 157. a 195. c
02. d 41. d 80. d 119. a 158. a 196. d
03. c 42. c 81. d 120. b 159. a 197. a
04. a 43. b 82. b 121. b 160. c 198. b
05. b 44. b 83. b 122. a 161. a 199. c
06. ab 45. c 84. b 123. b 162. c 200. a
07. c 46. a 85. b 124. d 163. a 201. d
08. b,d 47. b 86. a 125. b 164. c 202. d
09. b 48. b 87. d 126. b 165. a 203. a
10. d 49. c 88. a 127. b 166. a 204. d
11. c 50. a 89. c 128. c 167. d 205. c
12. d 51. a 90. d 129. c 168. a 206. c
13. a 52. a 91. c 130. d 169. b 207. a
14. b 53. b 92. d 131. d 170. b 208. a
15. c 54. d 93. c 132. a 171. d 209. a
16. d 55. a 94. b 133. b 172. d 210. a
17. a 56. b 95. b 134. a 173. c 211. b
18. a 57. c 96. c 135. b 174. d 212. d
19. c 58. c 97. a 136. a 175. d 213. d
20. c 59. d 98. c 137. d 176. b 214. c
21. a 60. a 99. a 138. a 177. a 215. c
22. a 61. c 100. b 139. b 178. a 216. d
23. c 62. d 101. d 140. a 179. b 217. d
24. d 63. c 102. d 141. b 180. b 218. a
25. d 64. c 103. c 142. d 181. c 219. a
26. c 65. b 104. c 143. b 182. b 220. b
27. b 66. b 105. c 144. b 183. d 221. c
28. d 67. b 106. d 145. b 184. c 222. a
29. c 68. b 107. b 146. d 185. d 223. b
30. d 69. c 108. c 147. c 186. d 224. b
31. a 70. b 109. a 148. d 187. c 225. c
32. d 71. b 110. b 149. c 188. d 226. c
33. a 72. b 111. c 150. d 189. b 227. b
34. a 73. b 112. c 151. a 190. b 228. c
35. c 74. c 113. c 152. b 191. d 229. c
36. d 75. d 114. b 153. a 192. a 230. a
37. c 76. b 115. c 154. b 193. b 231. b
38. a 77. a 116. c 155. b 194. a 232. d
39. b 78. d 117. c 156. c
118
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

CHAPTER-4
JFET
01. The pinch off voltage for a n-channel JFET is 05. The JFET in the below, circuit has an
4 V, when VGS = 1 V, the pinch off occurs for IDSS=10mA, Vp= 5V. The value of the resistance
VDS equal to: RS for a drain current of IDS= 6.4 mA is
(GATE (EC) - 1987) (2M) (GATE (EC) - 1992) (IES (EE) - 2010)
(a) 3 V (b) 5 V
(c) 4 V (d) 1 V
IDS
+
02. In an n-channel JFET, VGS is held constant. VDS 10V
-
is less than the breakdown voltage. As VDS is
increased
(GATE (EC) - 1988) (2M) RS
(a) Conducting cross sectional area of the
channel ‘S’ and the channel current
density ‘J’ both increase
(a) 1.06 k (b) 560 
(b) ‘S’ decrease and ‘J’ decrease
(c) ‘S’ decreases and ‘J’ increase (c) 470  (d) 156 

(d) ‘S’ increases and ‘J’ decreases


06. The transit time of the current carriers through
the channel of a JFET decides its __
03. The ‘Pinch off’ voltage of a JFET is 5.0 Volts. characteristic
Its ‘cut off’ voltage is
(GATE (EC) - 1994) (1M)
(GATE (EC) - 1990) (2M)
(a) Source (b) Drain
(a) (5.0)1/2 V (b) 2.5 V
(c) Gate (d) Source and drain
(c) 5.0 V (d) (5.0)3/2 V

07. In a JFET
04. An n-channel JFET has a pinch off voltage
VP= –5 V, VDS(max) = 20 V, and gm = 2mA/V, (GATE (EC) - 1995) (2M)
the min ‘ON’ resistance is achieved in the JFET List - I
for _____
A. The pinch off voltage decreases
(GATE (EC) - 1992) (2M)
B. The drain conductance increases
(a) VGS = – 7V and VDS = 0 V
C. The transit time of the carriers in the
(b) VGS = 0 V and VDS = 0 V channel is reduced
(c) VGS = 0 V and VDS = 20 V List - II
(d) VGS = – 7V and VDS = 20 V 1. The channel doping is reduced
119
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

2. The channel length is increased (a) 1.5 (b) 2.0


3. The conductivity of the channel is (c) 2.5 (d) 3.0
increased
4. The channel length is reduced
V0
5. The gate area is reduced 11. The voltage gain A V  of the JFET
Vi
Codes :
amplifier shown in the figure
A B C
V DD=+10V
(a) 1 3 4
ID=1mA
(b) 1 5 3
RD
(3K )
(c) 2 4 5
(d) 4 2 1 C2

+
C1 Vo
08. Two identical FET, each having parmeters gm
and rd are connected in parallel. The composite + G
FET is characterized by the parameters
(GATE (EC) - 1998) RG
Vi (1M)
RS
gm gm r Cs
(a) and 2rd (b) and d (2.5K)
2 2 2
-
rd
(c) 2g m and (d) 2gm and 2 rd
2

IDSS = 10mA Vp  5V


09. An n- channel JEFT has IDSS=2 mA and (Assume C1, C2 and Cs to be very large)
Vp  4V. Its transconductance gm(in mA/V) (GATE (EC) - 2002)
for an applied gate to source voltage VGS of -2V
(a) +18 (b) -18
is
(GATE (EC) - 1999) (c) +6 (d) -6

(a) 0.25 (b) 0.5


12. The action of a JFET in its equivalent circuit
(c) 0.75 (d) 1.0
can best be represented as a
(GATE (EC) - 2003)
10. An n-channel JFET, having a pinch off voltage
(VP) of –5V, shows a transconductance (gm) (a) Current Controlled Current Source
of 1mA/V when the applied gate-to-source (b) Current Controlled Voltage Cource
voltage (VGS) is –3V. Its maximum transconduc (c) Voltage Controlled Voltage Source
tance (in mA/V) is
(d) Voltage Controlled Current Source
(GATE (EE) - 2001)
120
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Common Data Questions 13, 14 and 15 (a) 1.875 mS and 3.41

Given rd  20k, I DSS  10mA, Vp  8V (b) 1.875 ms and -3.41


(c) 3.3 mS and -6
20V (d) 3.3 mS and 6

2k
16. The cross section of a JFET is shown in the
D following figure. Let VG be -2V and let Vp be
the intial pinch -off voltage. If the width W is
G doubled (with other goemetrical parameters
S
and doping levels remaining the same), then the
2M ratio between the mutual transconductances of
Vi V0
the intial and the modified JFET is
-
2V (GATE (EC) - 2008)
+

Zi Z0
Gate VG
P+
13. Zi and Z0 of the circuit are respectively
Source n W Drain
(GATE (EC) - 2005)
(a) 2 M P+
Gate VG
20
(b) 2 M and k
(a) 4
11
(c) Infinity and 2M  
1  1  2 / Vp 
(b)
20 2  1  1/  2V  
(d) infinity and k  p 
11

1  2 / Vp
14. ID and VDS under DC condition are respectively (c)
1  1 /  2Vp 
(GATE (EC) - 2005)
(a) 5.625 mA and 8.75 V
(b) 7.500 mA and 5.00 V

1  2 / Vp 
(d)
1  1/  2 V  
p
(c) 4.500 mA and 11.00 V
(d) 6.250 mA and 7.50 V
Common Data Question 17 and 18
15. Transconductance in milli-siemens (mS) and The channel resistance of an N-channel JFET
voltage gain of the amplifier are respectively shown in the fig. below is 600  when the full
(GATE (EC) - 2005)
121
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

channel thickness (tch) of 10  A is available (b) 2 and 3 are correct


for conduction. The built-in voltage of the gate (c) 1 and 3 are correct
P+N junction (Vbi) is –1V. When the gate to
source voltage (VGS) is 0V, the channel is (d) 1 and 2 are correct
deplected by 1  m on each side due to the
built-in voltage and hence the thickness available
20. The drain source voltage at which the drain
for conduction is only 8  m. current becomes nearly constant is called
(IES (EE) - 1998)
(a) barrier voltage
(b) breakdown voltage
(c) pick-off voltage
(d) pinch-off voltage

(GATE (EC) - 2011) (2M) 21. Match List-I (Device) with List-II (Property/
17. The channel resistance when VGS = 0V is item associated with it) and select the correct
answer
(a) 480  (b) 600 
(IES (EC) - 1996)
(c) 750  (d) 1000 
List-I
A. BJT
18. The channel resistance when VGS = – 3V is B. FET
(a) 360  (b) 917  C. SCR
(c) 1000  (d) 3000  D. Tunnel diode
List-II

19. Consider the following statements: 1. Pinch-off effect

In a differential amplifier using a FET pair, the 2. Controlled rectification


differential output offset voltage is due to 3. Negative resistance characteristics
1. mismatch between FET parameters. 4. Punch-through effect
2. difference between the values of resistors Codes :
used in the circuit even though they are
A B C D
marked nominally equal.
(a) 1 3 2 4
3. variation in the operating voltage of the
circuit. (b) 1 2 3 4
Of these statements (c) 4 1 2 3
(IES (EC) - 1996) (d) 1 4 3 2
(a) 1, 2 and 3 are correct

122
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

22. Thermal runaway is not encountered in FETs (IES (EE) - 2005)


because List - I
(IES (EE) - 2010) A. p-n junction diode
(a) IDS has a zero temperature coefficient B. tunnel diode
(b) IDS has a negative temperature coefficient C. JFET
(c) IDS has a positive temperature coefficient D. Schottky barrier diode
(d) The mobility of the carriers increases with List - II
increase in temperature
1. Microwave generator
2. Low frequency rectifier
23. The FET shown in the figure belows as
3. High frequency rectifier
(IES (EE) - 2010)
4. Voltage variable resistor
D Output Codes:
A B C D
(a) 2 3 4 1
(b) 4 1 2 3
(c) 2 1 4 3
(d) 4 3 2 1

S
26. Consider following statements:
(a) Common drain
1. BJT is a current controlled device with
(b) Common gate high input impedance and high gain
(c) Common Source bandwidth

(d) Common source follower 2. FET is a voltage controlled device with


high input impedance and low gain
bandwidth
24. A JEET is set up as a follower, with μ  200 , 3. UJT is a negative resistamce device and
rd =100 and source load resistor RL=1K. The can be used as an oscillator
output resistance R0 is 4. BJT, FET and UJT can all be used for
(a) 1000  (b) 500  amplification
Which of these statements are correct?
(c) 333  (d) 666 
(IES (EE) - 2005)
(a) 1 and 2 (b) 2 and 3
25. Match List - I (Device) with List - II
(Application ) and select the correct answer (c) 3 and 4 (d) 1 and 4
using the codes given below the lists:

123
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

27. The zero gate bias channel resistance of a 30. An FET is a better chopper than a BJT because
junction field effect transistor is 750 ohms and it has
the pinch-off voltage is 3V. For a gate bias of (IES (EC) - 2000)
1.5V and very low drains voltage, device would
behave as a resistance of (a) lower offset voltage
(IES (EC) - 1998) (b) higher series ON resistance
(a) 320 ohms (b) 816 ohms (c) lower input current
(c) 1000 ohms (d) 1270 ohms (d) higher input impedance

28. An FET source follower circuit has gm of 31. The voltage gain of a given common source
2m mho and rd of 50 k . If the source JFET amplifier depends on its

resistance Rs is 1k , the output resistance of (IES (EC) - 2004)


the amplifier will be (a) input impedance
(IES (EE) - 1999) (b) amplification factor
(a) 330  (b) 450  (c) dynamic drain resistance
(d) drain load resistance
(c) 500  (d) 1k

32. What is the main advantage of a JFET-cascade


29. FET voltage divider bias circuit is shown in the amplifier ?
given figure. If ID = 4 mA, then VGS and VDS
will be respectively (IES (EC) - 2006)

(IES (EE) - 2000) (a) High voltage gain


(b) Low output impedance
(c) Very low input capacitance
(d) High input impedance

33. In an FET common source high frequency


amplifier, which one of the following is the
correct expression for input capacitance Ci ?
(IES (EC) - 2006)
(a) – 3.78 V and 4 V (a) Ci = Cgs + (1 – Av) Cgd
(b) 4 V and – 3.78 V (b) Ci = Cgs + (1 – 1/Av) Cgd
(c) – 3.78 V and – 4 V (c) Ci = Cgd + (1 – Av) Cgs
(d) – 4V and – 3.78 V (d) Ci = Cgd + (1 – 1/Av) Cgs

124
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

34. The drain gate capacitance of a junction FET 38. Compared to the bipolar junction transistor, a
is 2 pF. Assuming a common source voltage JFET:
gain of 20. What is the input capacitance due
to Miller effect ? 1. Has a larger gain bandwidth product

(IES (EC) - 2006) 2. Is less noisy


(a) 21 pF (b) 40 pF 3. Has less input resistance
(c) 42 pF (d) 10 pF 4. Has current flow due to only majority
carriers
35. The pinch-off voltage Vp = + 6 V for a P- (IES (EE) - 2011)
channel JFET. If VGS = + 2 V, what is the value
(a) 1, 2, 3 and 4 are correct
of VDS at which it will enter into saturation
region? (b) 1 and 2 are correct
(IES (EC) - 2007) (c) 2 and 4 are correct
(a) –6 V (b) –4 V
(d) 3 and 4 are correct
(c) +8 V (d) +4 V

39. For a trans-conductance amplifier, input and


36. Which of the following are the characteristics
output resistances are respectively
of a Junction Field Effect Transistor ?
1. High input resistance (IES (EE) - 2011)

2. Good thermal stability (a)  and 0 (b) 0 and 


3. High current gain (c) 0 and 0 (d)  and 
4. More noisy than bipolar junction transistor
(IES (EC) - 2013)
40. A field effect transistor with an anti-parallel
(a) 1 and 3 (b) 1 and 2 body diode blocks
(c) 2 and 3 (d) 3 and 4 (IES (EE) - 2011)
(a) Bidirectio nal volt age and passes
37. Thermal runaway is not possible in FET unidirectional current
because as the temperature of FET increases
(b) Bidirectio nal volt age and passes
(IES (EC) - 2001, 2012) bidirectional current

(a) the mobility decreases (c) Unidirectional voltage and passes


unidirectional current
(b) the transconductance increases
(d) Unidirectional voltage and passes
(c) the drain current increases bidirectional current
(d) the mobility increases

125
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

41. Consider the following statements related to (a) 650  (b) 750 
JFET :
(c) 775  (d) 800 
1. Its operation depends on the flow of
minority carriers only
2. It is less noisy than BJT
3. It has poor thermal stability
4. It is relatively immune to rediation.
The correct statements are
(IES (EC) - 2012)
(a) 1, 2, 3 and 4 (b) 1 and 2 only
(c) 2 and 4 only (d) 3 and 4 only

42. The following statements refer to an n channel


FET operated in the active region
1. The gate voltage VGS reverse biases the
junction.
2. The drain voltage VDD is negative with
respect to the source
3. The current in the n channel is due to
electrons
4. Increasing the reverse bias VGS increases
the cross section for conduction
Which of these statements are correct ?
(IES (EE) - 2013)
(a) 1 and 2 (b) 1 and 3
(c) 2 and 3 (d) 3 and 4

43. The value of the capacity reactance obtainable


from a reactance FET whose gm is 12 ms when
1
the gate-to-source resistnace of the
9
reactance of the gate-to drain capacitor at
frequency 5 MHz is
(IES (EE) - 2013)

126
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

CONVENTIONAL PROBLEMS
01. (a) Specify the type of the negative feedback
in the JFET amplifier shown in Fig.

V0
(b) Calculate the voltage gain , of the
V1
amplifier with no feedback (Rf = ).
(c) Determine the value of the resistance Rf,

required to give a voltage gain V0 , or


V1 03. The built in potential of the gate junction of a
n-channel JFET is 0.5 volts. The drain current
–10.
saturates at VGS = 4 volts. When VGS = 0. The
pinch off voltage is
(GATE (EC) - 1991)

04. A n-channel JFET has IDSS = 1 mA, VP = –5V.


Its maximum transconductance is ____
(GATE (EC) - 1995)

05. In the JFET circuit shown in Fig. assume that


R1||R2 = 1 M and the total stray capacitance
at the output to be 20 pF. The JFET used has
(GATE (EC) - 1987) gm = 2mA/V, Cgs = 20pF and Cgd = 2pF.
Determine the upper cut-off frequency of the
02. It is required to use a JFET of Fig. as linear amplifier.
resistor. The parameters of the JFET are as (GATE (EC) - 1995)
follows :
W = 100  m , L = 10  m , a = 2.5  m .
The doping in the n-layer is N0 = 1016/cm² and
the electron mobility is 1500 cm²/V– sec. The
depletion layer width of each junction due to the
built-in potential is 0.25  m . The two P+ – gate
regions are connected together externally. The
resistance of the regions outside the gate are
negligible. Determine the minimum value of the
linear resistor which can be realized using the
JFET without forward biasing the gate junctions. 06. A JFET with VP = – 4V and IDSS = 12mA is
(GATE (EC) - 1991) used in the circuit shown in Fig. Assuming the
device to be operating in saturation,
127
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) Determine ID, VDS and VGS Cgd = 2 pF, and Cds = 2pF. Determine the ac
(b) Check to confirm that the device is indeed small-signal midband voltage gain (V0/Vs) and
operating in saturation the upper - 3 dB frequency of the circuit.

(GATE (EC) - 1996) (GATE (EC) - 1998)

09. A JFET with the following parameters is used


in a single stage common source amplifier with
a load resistance of 100 k . Calculate the high
07. The JFET in the circuit of Fig. is characterised frequency cut off (upper 3 dB cut off frequency)
by the parameters IDSS = 4 mA and Vp = 4V. of the amplifier.
Find Gm = 2.0 mA/V
(a) V0 if Vi = 0, and C gd = 2.0 pF
(b) Vi if V0 = 0 rd = 100 k
(GATE (EC) - 1998)
C gd = 2.0 pF
C gd = 1.0 pF
(GATE (EC) - 2003)

08. A JFET having μ = 50 and rd = 10K is used


in a common-source configuration as shown in
Fig. The JFET capacitances are Cgs = 5pF,
128
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

ANSWER KEY
01. a 16. b 31. b

02. c 17. c 32. a

03. c 18. d 33. a

04. c 19. d 34. c

05. d 20. d 35. c

06. b 21. c 36. b

07. a 22. d 37. a

08. c 23. b 38. c

09. b 24. c 39. d

10. c 25. c 40. d

11. d 26. b 41. c

12. d 27. c 42. b

13. b 28. b 43. b

14. a 29. a

15. b 30. a

129
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

CHAPTER-5
MOSFET
01. In MOSFET devices the n-channel type is 04. Which of the following effects can be caused
better than the P-channel type in the following by a rise in the temprature ?
respects (GATE (EC) - 1990) (2M)
(GATE (EC) - 1988) (2M) (a) increase in MOSFET current (IDS)
(a) it has better immunity (b) increase in BJT current (IC)
(b) it is faster (c) decrease in MOSFET current (IDS)
(c) it is TTL compatible (d) Decrease in BJT current (IC)
(d) it has better drive capability

05. The threshold voltage of an n-channel


02. The amplifier circuit shown below uses a MOSFET can be increased by
composite transistor of a MOSFET and
BIPOLAR in cascade. All capacitance are large (GATE (EC) - 1994) (1M)
gm of the MOSFET = 2 mA/V, and hfe of the (a) Increasing the channel dopant
BIPOLAR= 99. The overall Transconductance concentration
gm of the composite transistor is
(b) Reducing t he channel dopant
(GATE (EC) - 1988) (IES (EC) - 1999) concentration
(c) Reducing the gate-oxide thickness
(d) Reducing the channel length

06. A silicon n-MOSFET has a threshold voltage


of 1V and oxide thickness of 40000A°.
[ ε r (SiO 2)=3.9,  o =8.854 × 10–14 F/cm,
q=1.6 × 10–19C]. The region under the gate is
ion implanted for threshold voltage tailoring. The
(a) 198 mA/V (b) 9.9 mA/V dose and type of the implant (assumed to be a
(c) 4.95 mA/V (d) 1.98 mA/V sheet charge at the interface) required to shift
the threshold voltage to –1V are
(GATE (EC) - 1996)
03. In a MOSFET, the polarity of the inversion
layer is the same as that of the (a) 1.08 × 1012/cm², p-type
(GATE (EC) - 1989) (2M) (b) 1.08 × 1012/cm², n-type
(a) charge on the GATE - EC - electrode (c) 5.4 × 1011/cm², p-type
(b) minority carriers in the drain (d) 5.4 × 1011/cm², n-type
(c) majority carriers in the substrate
(d) majority carriers in the source
130
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

07. For a MOS capacitor fabricated on a p-type (a) current controlled capacitor
semiconductor, strong inversion occurs when (b) voltage controlled capacitor
(GATE (EC) - 1997) (c) Current controlled inductor
(a) surface potential is equal to Fermi (d) Voltage controlled inductor
potential
(b) surface potential is zero
11. The effective channel length of a MOSFET in
(c) surface potential is negative and equal to saturation decreases with increase in
Fermi potential in magnitude.
(GATE (EC) - 2001)
(d) surface potential is positive and equal to
twice the Fermi potential (a) gate voltage (b) drain voltage
(c) source voltage (d) body voltage
08. In the MOSFET amplifier of the figure, the
signal output V1 and V2 obey the Relationship 12. Consider the following statements in connection
(GATE (EC) - 1998) with the CMOS inverter in the figure, where
both the MOSFETs are of enhancement type
and both have a threshold voltage of 2V.
Statement 1: T1 conducts when Vi  2V.
Statement 2: T1 is always in saturation when
Vo  0V

+5V

T2
V V
(a) V1  2 (b) V1   2
2 2
Vi Vo

(c) V1  2V2 (d) V1  2V2


T1

09. The MOSFET switch in its on-state may be


considered equivalent to
(GATE (EE) - 1998) Which of the following is correct?
(a) resistor (b) inductor (GATE (EC) - 2002)
(c) capacitor (d) battery (a) Only statement 1 is TRUE
(b) Only statement 2 is TRUE
10. MOSFET can be used as a (c) Both the statements are TRUE
(GATE (EC) - 2001) (d) Both the statements are FALSE

131
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

13. If P is Passivation, Q is n-well implant, R is (a) An n-channel depletion mode device


metallization and S is source/ drain diffusion, (b) An n-channel enhancement mode device
then the order in which they are carried out in a
standard n-well CMOS fabrication process is (c) A p-channel depletion mode device
(GATE (EC) - 2003) (d) A p-channel enhancement mode device
(a) P-Q-R-S (b) Q-S-R-P
(c) R-P-S-Q (d) S-R-Q-P 17. For the n- channel enhancement MOSFET
shown in the figure, the threshold voltage
Vth=2V. The drain current ID of the MOSFET
14. For an n-channel enhancement type MOSFET,
is 4 mA when the drain resistance RD is 1k. if
if the source is connected at a higher potential
than that of the bulk (i.e.VSB > 0), the threshold the value of RD is increased to 4k, drain
voltage VT of the MOSFET will current ID will become
(GATE (EC) - 2003) (GATE (EE) - 2003) (2M)
(a) remain unchanged (b) decrease
10V
(c) change polarity (d) increase
ID RD
15. When the gate-to-source voltage(VGS) of a
MOSFET with threshold voltage of 400mV,
working in saturation is 900mV, the drain
current is observed to be 1mA. Neglecting the
channel width modulation effect and assuming
that the MOSFET is operating at saturation,
the drain current for an applied VGS of 1400mV
is (a) 2.8 mA (b) 2.0 mA
(GATE (EC) - 2003) (c) 1.4 mA (d) 1.0 mA
(a) 0.5 mA (b) 2.0 mA
(c) 3.5 mA (d) 4.0 mA 18. Given figure is the voltage transfer characteristic
of
16. The variation of drain current with gate-to-
source voltage (ID-VGS characteristic) of a Vout
MOSFET is shown in figure, The MOSFET is
(GATE (EE) - 2003) (1M)

ID

0 Vir

0 VGS

132
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(GATE (EC) - 2004)


+4V
(a) an NMOS inverter with enhancement
mode transistor as load VT=-1V
(b) an NMOS inverter with depletion mode
transistor as loas
(c) a CMOS inverter 1 mA
(d) a BJT inverter

(a) 220  (b) 470 


19. Consider the following statements S1 and S2.
S1: The threshold voltage (VT) of a MOS (c) 680  (d) 1200 
capacitor decreases with increases in gate
oxide thickness
22. A MOS capacitor made using p type substrate
S2: The threshold voltage (VT) of a MOS
is in the accumulation mode. The dominant
capacitor decreases with increase in
charge in the channel is due to the presence of
substrate doping concentration
(GATE (EC) - 2005)
Which one of the following is correct?
(a) holes
(GATE (EC) - 2004)
(b) electrons
(a) S1 is FALSE and S2 is TRUE
(c) positively charged ions
(b) Both S1 and S2 are TRUE
(d) negatively charged ions
(c) Both S1 and S2 are FALSE
(d) S1 is TRUE and S2 is FALSE
23. For an n-channel MOSFET and its transfer
curve shown in the figure the threshold voltage
20. The drain of an n-channel MOSFET is shorted is
to the gate so that VGS = VDS. The threshold
(GATE (EC) - 2005)
voltage (VT) of MOSFET is 1V. If the drain
current (ID) is 1mA for VGS= 2V then for
VGS = 3V, ID is ID

(GATE (EC) - 2004)


Transfer
(a) 2 mA (b) 3 mA characteristics

(c) 9 mA (d) 4mA

1V VGS
21. The value of R for which the PMOS transistor
in figure will be biased in linear region is
(GATE (EE) - 2004) (2M)

133
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Data for 25 and 26 are given below


V=5V
D

Assume that the threshold voltage of the


D
N-channel MOSFET shown in figure is
+0.75V. The output characteristics of the
MOSFET are also shown

VDD=25V
V=3V
G

G
R=10k

Vbd
S
V=1V
S

(a) 1V and the device is in active region


(b) -1V and the device is in saturation region
(c) 1 V and the device is in saturation region
+
(d) -1 V and the device is in active region Vm=2mV ~

24. Assume that the N-channel MOSFET shown 2V


in the figure is ideal, and that its threshold
voltage is +1.0V, the voltage Vab between
nodes a and b is
(GATE (EE) - 2005) (1M) 4
4V

3V
1k 1k 3

2V
2

1V
1
10 V D
2k Vab
G
S
0
2V (V)

25. The transconductance of the MOSFET is


(a) 5V (b) 2V (GATE (EE) - 2005) (2M)
(c) 1V (d) 0V (a) 0.75 ms (b) 1 ms
(c) 2 ms (d) 10 ms

134
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

26. The voltage gain of the amplifier is


5V
(GATE (EE) - 2005) (2M)
(a) +5 (b) -7.5
(c) +10 (d) -10 PMOS

27. An n-channel depletion MOSFET has


2.5 V
following two points on its ID  VGS curve:
NMOS
(i) VGS  0 at I D  12mA and

(ii) VGS  6 Volts at Zo  


Which of the following Q-points will give the
highest transconductance gain for small signals? (a) 0 A (b) 25A

(GATE (EC) - 2006) (c) 45A (d) 90A

(a) VGS   6Volts (b) VGS  3Volts


29. Group I lists four different semiconductor
(c) VGS  0volts (d) VGS  3volts devices. Match each devices in Group I with
its characteristics property in Group II.

28. In the CMOS inverter circuit shown, if the (GATE (EC) - 2007)
transconductance parameters of the NMOS Group - I
and PMOS transistors are P. BJT
Wn
k n = k p = μ n C OX = μ p COX , Q. MOS capacitor
Ln
R. LASER diode
Wp S. JFET
=40μA/V 2 and their threshold voltages are
Lp
Group - II
VTHn  VTHp  1V, the current I is 1. Population inversion

(GATE (EC) - 2007) 2. Pinch - off voltage


3. Early-band voltage
4. Flat- band volatge
Codes:
P Q R S
(a) 3 1 4 2
(b) 1 4 3 2
(c) 3 4 1 2
(d) 3 2 1 4
135
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Common data question 30, 31 and 32 (GATE (EC) - 2007)


The figure shows the high - frequency (a) Both S1 and S2 are true
capacitance - voltage (C-V) characteristics of (b) S1 is true and S2 is false
a metal/SiO2/silicon (MOS) capacitor having
(c) S1 is flase and S2 is true
an area of 1 104 cm 2. Assume that the
(d) Both S1 and S2 are false
permittivities   0 r  of silicon and SiO2 are
1 1012F/cm and 3.5  1013F/cm respectively..
33. Two identical NMOS transistors M1 and M2
C are connected as shown below Vbias is chosen
so that both tansistors are in saturation. The
7pF
Iout
equivalent gm of the pair is defined to be
Vi
at constant Vout.
Iout
Vout
1pF
V
0
M2
30. The gate oxide thickness in the MOS capacitor V bias
is
(GATE (EC) - 2007)
(a) 50 nm (b) 143 nm Vi M1

(c) 350 nm (d) 1μm


The equivalent gm of the pair is
31. The maximum depletion layer width in silicon (GATE (EC) - 2008)
is
(a) the sum of individual gm’s of the transistors
(GATE (EC) - 2007)
(b) the product of individual gm’s of the
(a) 0.143μm (b) 0.857 μm transistors
(c) nearly equal to the gm of M1
(c) 1μm (d) 1.143μm
gm
(d) nearly equal to of M2
go
32. Consider the following statements about the
C-V characteristics plot:
S1: The MOS Capacitor has as n-type 34. The drain current of a MOSFET in saturation
substrate 2
is given by I D  K  VGS  VT  where K is a
S2: If positive charges are introduced in the
oxide, the C-V plot will shift to the left. constant.The magnitude of the transconduct -
ance gm is
Then which of the following is true?

136
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(GATE (EC) - 2008) constant drain voltage VD. Which of the


following figures represents the expected
2
K  VGS  VT  dependence of gm on VG?
(a) (b) 2K  VGS  VT 
VDS (GATE (EC) - 2008)

2
ID K  VGS  VT 
(c) (d)
VGS  VDS VGS

gm

35. For the circuit shown in the following figure, (a)


transistors M1 and M2 are identical NMOS
transistors. Assume that M2 is in saturation and
VG
the output is unloaded.

VDD

Ibias RE
gm

Vout (b)

Va Ix
VG
M1 M2

Is

gm
The current Ix is related to Ibias as
(c)
(GATE (EC) - 2008)

(a) Ix  Ibias  Is VG

(b) I x  Ibias
gm
(c) Ix  Ibias  Is

 V 
(d) I x  I bias   VDD  out 
 RE  (d)

36. The measured transconductance gm of an VG

NMOS transistor operating in the linear region


is plotted against the gate voltage VG at a

137
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

37. Consider the following two statements about 38. For small increase in VG beyond 1V, which of
the internal conditions in an n-channel the following gives the correct description of
MOSFET operating in the active region the region of operation of each MOSFET?
S1: The inversion charge decreases from (GATE (EC) - 2009)
source to drain (a) Both the MOSFETs are in saturation
S2: The channel potential increases from region
source to drain (b) Both the MOSFETs are in triode region
Which of the following is correct? (c) n-MOSFET is in triode and p-MOSFET
(GATE (EC) - 2009) is in saturation region
(a) Only S2 is true (d) n-MOSFET is in saturation and p-
MOSFET is in triode region
(b) Both S1 and S2 are false
(c) Both S1 and S2 are true, but S2 is not a
reason for S1 39. Estimate the output voltage V0 for VG = 1.5V.
[Hints: use the appropriate current- voltage
(d) Both S1 and S2 are true, and S2 is a
equation for each MOSFET, based on the
reason for S1
answer to Q.no. 8]
(GATE (EC) - 2009)
Linked Answer Questions 38 and 39
1 1
Consider the CMOS circuit shown, where the (a) 4  V (b) 4  V
gate voltage VG of the n-MOSFET is increased  2 2
from Zero, while the gate voltage of the
p-MOSFET is kept constant at 3V. Assume that, 3 3
for both transistors, the magnitude of the (c) 4  V (d) 4  V
2 2
threshold voltage is 1V and the product of the
transconductance parameter and the (W/L)
ratio,i.e. the quantity μCox  W / L , is1mA.V-2 40. This gate oxide in a CMOS process is
preferably grown using
5V (GATE (EC) - 2010)
(a) Wet oxidation
(b) dry oxidation
(c) epitaxial deposition
3V
(d) ion implantation
VC

VG 41. At room temperature, a possible value for the


mobility of electrons in the inversion layer of a
silicon n-channel MOSFET is
(GATE (EC) - 2010)

138
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) 450cm 2 / V  s (b) 1350cm 2 / V  s (a) Vin < 1.875 V


(b) 1.875 V < Vin < 3.125 V
(c) 1800cm 2 / V  s (d) 3600cm 2 / V  s
(c) Vin > 3.125 V
(d) 0 < Vin < 5 V
42. In the circuit shown below, for the MOS
transistor, μ n C ox  100 μA/V 2 and the threshold
voltage VT= 1V. The voltage Vx at the source 44. The source of a silicon (ni = 1010 per cm³)
of the upper transistor is n-channel MOS transistor has an area of
(GATE (EC) - 2011) (1M) 1 sqμm and a depth of 1μm. If the dopant
density in the source is 1019/cm³, the number
of holes in the source region with the above
volume is approximately
(GATE (EC) - 2012) (2M)
(a) 107 (b) 100
(c) 10 (d) 0

Common Data for Questions 45 and 46


In the three dimensional view of a silicon
n-channel MOS transistor shown below,
δ  20nm. The transistor is of width 1μm. The
depletion width formed at every p-n junction is
10 nm. The relative permittivities of Si and
SiO2, respectively, are 11.7 and 3.9, and
(a) 1 V (b) 2 V
 0 = 8.9 × 10–12 F/m.
(c) 3 V (d) 3.67 V
(GATE (EC) - 2012) (2M)

43. In the CMOS circuit shown, electron and hole


mobilities are equal, and M1 and M2 are
equally sized. The device M1 is in the linear
region if
(GATE (EC) - 2012) (2M)

45. The source-body junction capacitance is


approximately
(a) 2 f F (b) 7 f F
(c) 2 pF (d) 7 pF
139
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

46. The gate-source overlap capacitance is


approximately
(a) 0.7 fF (b) 0.7 pF
(c) 0.35 fF (d) 0.24 pF

47. The small-signal resistance (i.e., dVB/dlD) in


k offered by the n-channel MOSFET M
shown in the figure below, at a bias point of (a) 8 (b) 32
VB=2V is (device data for M: device transcon (c) 50 (d) 200
ductance parameter

kN  μ C'OX  W/L   40μA/V 2 , 49. In a MOSFET operating in the saturation


threshold voltage VTN= 1V, and neglect body region, the channel length modulation effect
effect and channel length modulation effects) causes
(GATE (EC) - 2013) (GATE (EC) - 2013)
(a) an increase in the gate-source capacitance
(b) a decrease in the transconductance
(c) a decrease in the unity-gain cut-off
frequency
(d) a decreases in the output resistance

50. Both transistors T1 and T2 shown in the figure


have a threshold voltage of 1 Volts. The device
(a) 12.5 (b) 25 parameters K1 and K2 of T 1 and T 2 are,

(c) 50 (d) 100 respectively 36μAW 2 and 9μAW 2 . The output


voltage V0 is

48. The ac schematic of an NMOS common 5V


source stage is shown in the figure below, where
part of the biasing circuit has been omitted for
simplicity. For the n-channel MOSFET M, the
transconductance gm = 1 mA/V, and body effect T1
and channel length modulation effect are to be
neglected. The lower cut-off frequency in Hz
V0
of the circuit is approximately at
(GATE (EC) - 2013)
T2

140
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(GATE (EE)) (d) Current is quadratic with VGS for


(a) 1 V (b) 2V MOSFETs and exponential with VBE for
BJTs.
(c) 3V (d) 4V

54. The lower turn off time of MOSFET when


51. Two MOSFETS M1 and M2 are connected in compared to BJT can be attributed to which
parallel to carry a total current of 20A. The one of the following?
drain to source voltage of M1 is 2.5 V and that
of M2 is 3V. What are the drain currents of M1 (IES (EE) - 2007)
and M2 when the current sharing series (a) Input impedance
resistances are each of 0.5 ? (b) Positive temperature coefficient
(IES (EE) - 2009) (c) Absence of minority carriers
(a) 10.5 A and 9.5 A (d) On-state resistance
(b) 9.5 A and 10.5 A
(c) 10.5 A and 10.5 A 55. In a source follower, consider the following
(d) 9.5 A and 9.5 A statements:
1. The voltage gain of a source follower is
52. The modified work function of an n-channel always less than one
MOSFET is -0.85 V. If the interface charge is 2. It has some current gain and power gain
4 2
3  10 C / m and the oxide capacitance is 3. Its ouput resistance can be made low
2
300μF / m , the flat band voltage is which of these statements are correct?
(IES (EE) - 2002) (IES (EE) - 2007)
(a) -1.85V (b) -0.15V (a) 1 and 2 only (b) 2 and 3 only
(c) +0.15V (d) +1.85V (c) 1 and 3 only (d) 1, 2 and 3

53. What is the main difference between 56. Which one of the following is not a characteristic
MOSFETs and BJTs in terms of their I-V of CMOS configuration?
charcteristics? (a) CMOS devices dissipate much lower
(IES (EE) - 2006) static power than bipolar devices
(a) Current is quadratic with VGS for (b) CMOS devices have low input
MOSFETs and linear with VBE for BJTs impedances
(b) Current is linear with VGS for MOSFETs (c) CMOS devices have higher noise margins
and exponential with VBE for BJTs (d) CMOS devices have much lower trans-
(c) Current exponential with VGS/VBE in both conductance than bipolar devices
these devices, but rise is faster in
MOSFETs
57. Consider the following statements :

141
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

The threshold voltage of a MOSFET can be List-I


lowered by
1. using a thinner gate oxide.
2. reducing the substrate concentration A. B.
3. increasing the substrate concentration
Of these statements
(IES (EC) - 1997)
C. D.
(a) 3 alone is correct
(b) 1 and 2 are correct
List-II
(c) 1 and 3 are correct
1. Depletion mode MOSFET
(d) 2 alone is correct
2. p-channel JFET
3. n-channel JFET
58. The threshold voltage of an n-channel
enhancement mode MOSFET is 0.5V. When 4. Enhancement mode MOSFET
the device is biased at a gate voltage of 3V. Codes:
Pinch-off would occur at a drain voltage of
A B C D
(IES (EC) - 1998)
(a) 2 1 4 3
(a) 1.5 V (b) 2.5 V
(b) 4 3 2 1
(c) 3.5 V (d) 4.5 V
(c) 2 3 4 1
(d) 4 1 2 3
59. Consider the following devices.
1. BJT in CB mode
61. Match List-I (Circuit name) with List-II (Circuit
2. BJT in CE mode diagram) and select the correct answer using
3. JFET the codes given below the lists:
4. MOSFET (IES (EC) - 2001)
The correct sequence of these devices in List-I
increasing order of their input impedance is A. Cascade connection
(IES (EC) - 1999) B. Cascode connection
(a) 1, 2, 3, 4 (b) 2, 1, 3, 4 C. Darlington connection
(c) 2, 1, 4, 3 (d) 1, 3, 2, 4 D. Parallel connection
List-II
60. Match List-I (Symbols) with List-II (Devices)
and select the correct answer using the codes
given below the lists: 1.

(IES (EE) - 2000)


142
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(c) Higher current gain

2. (d) Lower current gain from the power supply,


thereby less dissipation

64. Consider the following statements related to a


3. CMOS (Complementary metal oxide
semiconductor) inverter.
1. It combines an n-channel and a p-channel
MOS transistor
4. 2. For binary 1 input, both transistors are
OFF.

Codes: 3. For binary 0 input, both transistors are


ON.
A B C D
4. Whatever is the state of input, one
(a) 1 2 3 4 transistor is ON while the other is OFF.
(b) 2 1 3 4 Which of the statements given above are
(c) 1 2 4 3 correct?
(d) 2 1 4 3 (IES (EC) - 2005)
(a) 1, 2, 3 and 4 (b) 1 and 4
62. In a MOS transistor, the gate source input (c) 1, 2 and 3 (d) 3 and 4
impedance is
1. lower than the input impedance of a BJT 65. What is the value of Rs required to self bias an
2. higher than the input impedance of a BJT N channel JFET with Vp = – 10V, IDSS =
40 mA and VGSQ = – 5V ?
3. lower than the input impedance of a JFET
(IES (EC) - 2005)
4. higher than the input impedance of a JFET
Select the correct answer using the codes given (a) 250  (b) 500 
below:
(c) 750  (d) 1500 
(IES (EC) - 2001)
(a) 1 alone (b) 2 and 3
66. For the circuit shown below if gm = 3 × 10–3 &
(c) 4 alone (d) 2 and 4 Rs = 3000  ,then what is the value of R0 ?

63. A CMOS amplifier when compared to an N-


channel MOSFET, has the advantage of
(IES (EC) - 2003)
(a) Higher cut-off frequency
(b) Higher voltage gain
143
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(IES (EC) - 2006) (a) Are easy to parallel for higher current
(a) 3000  (b) 1000/3  (b) Leakage current is relatively high

(c) 300  (d) 100  (c) Have more linear characteristic


(d) Overload and peak current handling
capability are high
67. Which one of the following gain equations is
correct for a MOSFET common-source
amplifier ? (gm is mutual conductance, and RD
71. A gate to drain-connected enhancement mode
is load resistance at the drain)
MOSFET is an example of
(IES (EC) - 2007)
(IES (EC) - 2012)
(a) Av = gm / RD
(a) an active load
(b) Av = gm RD
(b) a switching device
(c) Av = gm / (1 + RD)
(c) a three-terminal device
(d) Av = RD / gm
(d) a diode

68. In a CMOS CS amplifier the active load is


72. Body effect in MOSFETs results in
obtained by connecting a
(IES (EC) - 2012)
(IES (EC) - 2009)
(a) increase in the value of transconductance
(a) p channel current mirror circuit
(b) change in the value of threshold voltage
(b) n channel transistor
(c) decrease in the value of transconductance
(c) p channel transistor
(d) increase in the value of output resistance
(d) BJT current mirror

73. Match List - I (Circuit Symbol) with List -II


69. In a transconductance, the device output
(Device) and selct the correct answer using the
(IES (EC) - 2012) codes given below the lists:
(a) voltage depends upon the input voltage (IES (EE) - 2005)
(b) voltage depends upon the input current List - I
(c) current depends upon the input voltage
(d) current depends upon the input current A .

70. Which one of the following statements is NOT B.


correct for a MOSFET ?
(IES (EE) - 2011)

144
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

C.

D.

List - II
1. N- Channel FET
2. Varactor
3. Tunnel Code
4. P channel MOSFET
Codes:
A B C D
(a) 3 2 1 4
(b) 1 4 3 2
(c) 3 4 1 2
(d) 1 2 3 4

74.. The regions of operation of a MOSFET to


work as a times resistor and linears amplifier
are
(IES (EE) - 2013)
(a) Cut-off and saturation respectively
(b) Triode and Cut-off respectively
(c) Triode and saturation respectively
(d) Saturation and Triode respectively

75.. Statement (I) : MOSFETs aer intrinsically


faster than bipolar devices
Statement (II) : MOSFETs have excess
minority carrier

145
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

CONVENTIONAL PROBLEMS
01. In Fig. the n-channel MOSFETs are identical
and their current voltage characteristics are
given to the following expressions :

 V2 
For VDS ID   VGS  1 VDS  DS  mA
 2 

For VDS  (VGS–1), (VGS – 1) = (VGS – 1)2 03. In the MOSFET amplifier shown in the fig.
mA below, the transistor has μ = 50, rd = 10K.
Where VGS and VDS are the gate-source and Cgs = 5 pF, Cgd = 1pF and Cds = 2 pF. Draw a
drain-source voltages respectively and I0 is the small signal equivalent circuit for the amplifier
drain current. for midband frequencies and calculate its
The current IDC flowing through the transistor midband voltage gain.
‘M’ is equal to ____ (GATE (EC) - 1994)
(GATE (EC) - 1991)

04. Channel current is reduced on application of a


more positive voltage to the gate of the depletion
mode n-channel MOSFET. (True/False)
(GATE (EC) - 1994) (1M)
02. An n-channel MOSFET (T) hanving a VT of
2V [Threshold voltage] is used in the circuit 05. Calculate the capacitance of a circular MOS
shown in Fig. Initially T is off and in steady state. capacitor, of 0.5 mm dia and having a SiO2
At time t = 0, a step voltage of magnitude 4V layer of 80 mm thickness, under strong
is applied to the input so that the MOSFET
accumulation. Assume the relative dielectric  r
turns ‘ON’ instantaneously. Draw the
equivalent circuit and calculate the time taken of SiO2 to be 4,  0 to be 8.854 × 10–14 F/cm.
for the ouput V0 to fall to 5V. The device Calculate the break down voltage of the
constant of the MOSFET, K=5mA/V², capacitor if the dielectric strength of SiO2 film
RDS= , CDS= 0; CDG= 0. is 107 V/cm.
(GATE (EC) - 1992) (GATE (EC) - 1995)

146
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

06. The n-MOSFET shown in Fig. is used as a used is VDD = 5V


voltage variable resistor. determine the (GATE (EC) - 1997)
expression for the resistance and compute its
value for Vi = 2V. Neglect body effect.
MOSFET data:
Threshold voltage, VT = 1V,
Channel length modulation parameter,
λ =0.3V–1
Transconductance parameter,
2
kN = (W/L) μ nCox = 40 μA / V
(GATE (EC) - 1996) Fig. (a)

Two non-overlapping clocks 1 and 2 are as


shown in Fig. (b) and have large pulse widths.

07. Given an NMOS circuit as shown in Fig. The


specifications of the circuit are : Fig. (b)
VDD = 10 V,  = K =  n Cox (W/L) = All capacitors are initially discharged and the
10–4 Amp/V², VT = 1V and IDS = 0.5 mA. input Vin = 0 volts is applied. If values of
capacitors are C1 = 2pf and C2=1pf, find out
Evaluate VDS and RD for the circuit.
voltage VC2 on capacitor C2 after 2 goes low..
Neglect body – effect for VT
Neglect body-effect onVT in your evaluation.
(GATE (EC) - 1997)

09. Explain the difference between the


enhancement mode and depletion mode
MOSFETs.
(GATE (EE) - 1997)

10. The MOSFETs having drain resistances of rd1


and rd2 and amplification factors of μ1 and μ 2
respectively are connected in parallel. Show
08. Circuit shown in Fig. (a) is an NMOS shift that:
register. All transistors are NMOS enhancement (i) I/rd = I/rd1 + 1/rd2 and
type with threshold voltage VT = 1V. Supply
147
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(ii) μ = (μ1rd2 + μ 2rd1) / (rd1 + rd2)


where rd and μ are equivalent resistance and
amplification factor respectively.
(IES (EE) - 1998)

11. Sketch the cross sectional view of an


enhancement mode MOSFET. Explain its
operation and characteristics.
(IES (EE) - 1998)
12. Sketch the energy-band diagram of an ideal
MOS capacitor at equilibrium. Explain with
energy band diagram the following modes of
operation of a MOS capacitor.
(i) accumulation
(ii) depletion
(iii) inversion
(IES (EC) - 2011)
13. Obtain an expression for the drain current (ID)
as a function of drain voltage (VD) for an n-
channel MOSFET. Hence find the expression
for the transconductance of the device in the
saturation region.
(IES (EC) - 2011)

14. Explain the following statement:


In the linear region operation of MOSFET drain
current decreases as the temperature increases.
(IES (EC) - 2012)

148
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

ANSWER KEY

01. b 21. d 41. b 60. c


02. d 22. a 42. c 61. a
03. d 23. c 43. a 62. d
04. bc 24. b 44. d 63. d
05. c 25. b 45. a 64. b
06. a 26. d 46. a 65. b
07. d 27. d 47. b 66. c
08. c 28. c 48. a 67. b
09. c 29. c 49. d 68. a
10. b 30. a 50. c 69. c
11. b 31. c 51. a 70. a
12. c 32. d 52. d 71. a
13. b 33. c 53. d 72. b
14. d 34. b 54. c 73. a
15. d 35. b 55. c 74. c
16. d 36. a 56. b 75. c
17. a 37. d 57. c
18. c 38. d 58. b
19. d 39. b 59. a
20. d 40. b

149
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

CHAPTER-6
OPERATIONAL AMPLIFIER
01. The OP-AMP shown in Fig. below is ideal. 03. The CMRR of the differential Amplifier of the
fig is equal to
R  L/C . The phase angle between V0 and
Vi, at   1 / LC is (GATE (EC) - 1990)

(GATE (EC) - 1988)

(a)  (b) 0
(c) 900 (d) 1800
(a)  / 2 (b) 
(c) 3 / 2 (d) 2
04. If the input to the circuit of figure is a sine wave,
the output will be
02. Refer to Fig. (GATE (EC) - 1990)
(GATE (EC) - 1989)

(a) A half-wave rectified sine wave


(b) A full-wave rectified sine wave
(c) A triangular wave
(d) A square wave.

R2 05. The OP AMP of Fig. has a very poor open


(a) For Vi > 0, V0 = – R Vi
1 loop voltage gain of 45 but is otherwise ideal.
The gain of the amplifier equals
(b) For Vi > 0, V0 = 0
(GATE (EC) - 1990)
R2
(c) For Vi < 0, V0 = – R Vi
1

(d) For Vi < 0, V0 = 0

150
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) 5 (b) 20 (GATE (EE) - 1992)


(c) 4 (d) 4.5 (a) the two input terminals are directly shorted
internally

06. An Op-Amp has an offset voltage of 1mV and (b) the input impedance of the OPAMP is
is ideal in all other respects. If this Op-Amp is infinity
used in the circuit shown in fig. The O/P voltage (c) the open loop gain of the OPAMP is infinity
will be (Select the nearest value). (d) CMRR is infinity
(GATE (EC) - 1992)

09. A change in the value of the Emitter resistance


(Re) in a difference Amplifier.
(GATE (EC) - 1995) (IES (EC) - 2012)
(a) Affects the difference mode gain Ad
(b) Affects the common mode gain Ac
(c) Affects both Ad and Ac
(a) 1 mV (b) 1 V (d) Does not affect either Ad (or) Ac.
(c)  1V (d) 0 V
10. The circuit shown in the figure is that of
07. The circuit of fig. uses an ideal OP-Amp for (GATE (EC) - 1996)
small positive values of Vin, the circuit works
as
(GATE (EC) - 1992)

(a) a non-inverting Amplifiers


(a) a half wave rectifier (b) an inverting Amplifier
(b) a differentiator (c) an oscillator
(c) a logarithmic amplifier (d) a Schmitt trigger
(d) an exponential Amplifier
11. Let the magnitude of the gain in the inverting
08. An ideal OPAMP is used to make an inverting Op-Amp amplifier circuit shown in Figure be x
amplifier. The two input terminals of the with switch S1 open. When the switch S1 is
OPAMP are at the same potential because closed, the magnitude of gain becomes
151
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(GATE (EE) - 1996)

(a) x/2 (b) – x (a) 6 dB (b) 8 dB

(c) 2x (d) – 2x (c) 12 dB (d) none of above

12. The output voltage Vo of the circuit shown in 14. From a measurement of the rise time of the
the figure is output pulse of an amplifier whose input is a
small amplitude square wave, one can estimate
(GATE (EC) - 1997) the following parameter of the amplifier:
(GATE (EC) - 1998)
(a) gain-bandwidth product
(b) slew rate
(c) upper 3-dB frequency
(d) lower 3-dB frequency

15. One input terminal of high gain comparator


circuit is connected to ground and a sinusoidal
(a) –4 V (b) 6 V voltage is applied to the other input. The output
of comparator will be
(c) 5 V (d) – 5.5 V
(GATE (EC) - 1998)
(a) a sinusoid
13. An Amplifier A has 6 dB gain and 50  input
(b) a full rectified sinusoid
and output impedances. The noise figure of this
Amplifier as shown in the figure is 3 dB. A (c) a half rectified sinusoid
cascade of two such Amplifiers as in the figure (d) a square wave
will have a noise figure of
(GATE (EC) - 1997)
16. I n a differential A mplifier, CM RR can be
improved by using an increased
(GATE (EC) - 1998)
(a) Emitter resistance
(b) Collector resistance
(c) Power supply voltage
(d) Source resistance
152
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

17. Match the following 18. The first dominant pole encountered in the
(GATE (EE) - 1998) frequency response of a compensated op-amp
is approximately at
List-I
(GATE (EE) - 1999)
(a) 5 Hz (b) 10 kHz
(c) 1 MHz (d) 100 MHz

(A)
19. In the differential amplifier of the figure, If the
source resistance of the current source IEE is
infinite, then the common-mode gain is
(GATE (EC) - 2000)

VC C

(B)

R R

V in1 Vin 2

(C)
IE E

-VE E

List-II (a) zero (b) infinite


(P) High-pass filter Vin1  Vin 2
(Q) Amplifier (c) indeterminate (d) 2VT
(R) Comparator
(S) Low-pass filter
20. The configuration of the figure is a
Codes
(GATE (EC) - 2000)
A B C
(a) R S P
(b) P R S
(c) S P R
(d) S R P

153
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

R1 R2 R

C
Vi -
- V0
V0 +
+
R

C
(a) Square wave (b) Triangular wave
R C
(c) Parabolic wave (d) Sine wave

(a) Precision integrator 23. If the Op-amp in the figure has an input offset
(b) Hartley oscillator voltage of 5 mV and an open-loop voltage gain
of 10,000 then V0 will be
(c) Butter worth high pass filter
(GATE (EC) - 2000)
(d) Wien-bridge oscillator
+ 15 V
21. If the Op-amp in the figure, is ideal then V0 is +
(GATE (EC) - 2000) V0
-
C
- 15 V
C
Sin t
V1 -
V0
V2 + (a) 0 V
Sin t
C (b) 5 mV
(c) +15 V or -15 V
(a) Zero
(d) +50 V or -50 V
(b)  V1  V2  sin t
24. In the circuit of the figure, V0 is
(c)   V1  V2  sin t
(GATE (EC) - 2000)
(d)  V1  V2  sin t
+ 15 V
+
22. Assume that the Op-amp of the figure is ideal. V0
If Vi is a triangular wave then V0 will be +1 V -
R
(GATE (EC) - 2000) - 15 V

R
154
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) -1 V (b) 2V 28. In the figure assume the OP-AMPs to be ideal.


(c) +1V (d) +15 V The output V0 of the circuit is:
(GATE (EC) - 2001)
25. The most commonly used amplifier in sample and 10m H
10 F
hold circuits is
10 
(GATE (EC) - 2000) -
Vs 1
=10 cos(100t) -
+ 2 3
(a) a uniy gain inverting amplifier + V0
(b) a unity gain non-inverting amplifier
(c) an inverting amplifier with a gain of 10
(d) an inverting amplifier with a gain of 100 (a) 10 cos (100t)
t

(b) 10  cos 100  d


26. The circuit shown in Figure uses an ideal opamp 0

working with + 5V and – 5V power supplies. t

(c) 10  cos 100  d


4
The output voltage V0 is equal to
0
(GATE (EE) - 2000)
4 d
(d) 10 cos 100  d
dt

29. Consider the following two statements:


Statements 1:
A Stable multivibrator can be used for generating
square wave
(a) + 5 V (b) – 5 V Statement 2:
(c) + 1 V (d) – 1 V Bistable multivibrator can be used for storing binary
information
27. The feedback factor for the circuit shown in Figure (GATE (EC) - 2001)
is (a) Only statement 1 is correct
(GATE (EE) - 2000) (b) Only statement 2 is correct
(c) Both the statement 1 and 2 are correct
(d) Both the statement 1 and 2 are incorrect

30. The inverting OP-AMP shown in the figure has an


open - loop gain of 100. The closed - loop gain
(a) 9/100 (b) 9/10 V0 / Vs is
(c) 1/9 (d) 1/10 (GATE (EC) - 2001)
155
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

33. An op-amp, having a slew rate of 62.8 V/


R 2 =10 K
 sec, is connected in a voltage follower
configuration. If the maximum amplitude of the
R 1=10 K input sinusoidal is 10 V, then the minimum
-
VS + frequency at which the slew rate limited
Vl
- + V0 distortion would set in at the output is
(GATE (EE) - 2001) (2M)
(a) 1.0 MHz (b) 6.28 MHz
(c) 10.0 MHz (d) 62.8 MHz
(a) -8 (b) -9
34. For the op-amp circuit shown in Figure,
(c) -10 (d) -11
determine the output voltage v0, Assume that
the op-amps are ideal.
31. The ideal OP-AMP has the following (GATE (EE) - 2001)
characteristics
(GATE (EC) - 2001)

(a) R i  , A  , R 0  0

(b) R i  0, A  , R 0  0

(c) R i  , A  , R 0  

(d) R i  0, A  , R 0  
8 20
(a)  V (b)  V
32. For the oscillator circuit shown in Figure, the 7 7
expression for the time period of oscillation can (c) – 10 V (d) None of these
be given by (where  = RC)
(GATE (EE) - 2001)
Statements for Linked Questions 35 and
36
For the circuit shown in figure

(a)  1n 3 (b) 2  1n 3
(c)  1n 2 (d) 2  1n 2
156
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

35. The circuit shown is a 39. A amplifier using an op-amp with a slew-rate
(GATE (EE) - 2001) (2M) SR=1 V / μ sec has a gain of 40dB. If this
amplifier has to faithfully amplify sinusoidal
(a) Low pass filter
signals from dc to 20 KHz without introducing
(b) Band pass filter any slew-rate induced distortion then the input
(c) Band Reject filter signal level must not exceed.
(d) High pass filter (GATE (EC) - 2002)
(a) 795 mV (b) 395 mV

36. If the above filter has a 3 dB frequency of (c) 79.5 mV (d) 39.5 mV
1 kHz, a high frequency input resistance of
100 k  and a high frequency gain of 40. The output voltage (v0) of the Schmitt trigger
magnitude 10. Then value of R1 , R2 and C shown in Figure swings between +15 V and
respectively are – –15 V. Assume that the operational amplifier is
(GATE (EE) - 2001) (2M) ideal. The output will change from + 15 V to
–15 V when the instantaneous value of the input
(a) 100 k  , 100 k  0.159 nF sine wave is
(b) 10 k  , 100 k  0.111  F (GATE (EE) - 2002)

(c) 100 k  , 1000 k  , 15.9 nF


(d) None of these

37. An op-amp has an open-loop gain of 105 and


an open-loop upper cut-off frequency of
10Hz. If this op-amp is connected as an amplifier
with a closed-loop gain of 100, then the new
upper cut-off frequency is
(GATE (EE) - 2001)
(a) 5 V in the positive slope only
(a) 10 Hz (b) 100 Hz
(b) 5 V in the negative slope only
(c) 10 kHz (d) 100 kHz
(c) 5 V in the positive and negative slopes
(d) 3 V in the positive and negative slopes
38. A 741-type op-amp has a gain - bandwidth
product of 1 MHz. A non- inverting amplifier
using this opamp and having a voltage gain of Statement for Linked Questions : 41 and
20 dB will exhibit a –3 dB bandwidth of 42
(GATE (EC) - 2002) The following network is used as a feedback
(a) 50 KHz (b) 100 KHz circuit in an oscillator shown in figure to generate
sinusoidal oscillations. Assuming that the
1000 1000 operation amplifier is ideal
(c) KHz (d) KHz
17 7.07
157
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Given that R = 10 k  and C = 100 pF 1 1


(a) (b)
RC 2RC

1
(c) (d) None of these
4RC

43. A first order, low pass filter is given with


R=50  and C = 5  F .
What is the frequency at which the gain of the
voltage transfer function of the filter is 0.25 ?
(GATE (EE) - 2002)
(a) 4.92 kHz (b) 0.49 kHz
(c) 2.46 kHz (d) 24.6 kHz

44. The output voltage of the regulated power


supply shown in the figure is
(GATE (EC) - 2003)

+
Vy 1 K
41. The transfer function of the first network is
Vx
+
15 V DC VZ = 3 V
(GATE (EE) - 2002) (2M) -
Unregulated
Power source
j RC
(a) 40 K
1   R C 2   j3CR
2 2
20 K Regulated
DC Ouput
jCR -
(b) 1   R C 2   j 2CR
2 2
(a) 3 V (b) 6 V

jCR (c) 9 V (d) 12 V


(c)
1  j3CR
j CR 45. An ideal sawtooth voltage waveform of
(d) frequency 500Hz and amplitude 3V is
1  j 2CR
generated by charging a capacitor of 2F in
every cycle. The charging requires
42. The frequency of oscillation will be (GATE (EC) - 2003)
(GATE (EE) - 2002) (2M) (a) Constant voltage source of 3 V for 1 ms
(b) Constant voltage source of 3 V for 2 ms
158
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(c) Constant current source of mA ofr 1 ms (a) 23 dB (b) 25 dB


(d) Constant current source of 3 mA for (c) 46 dB (d) 50 dB
2 ms

49. Assuming the operational amplifier to be ideal,


46. If the Op-amp in the figure is ideal, the output the gain Vout / Vin for the circuit shown in figure
voltage Vout will be equal to
is
(GATE (EC) - 2003)
(GATE (EE) - 2003) (2M)
1 K 5 K
2V
10 K 10 K

1 K
-
1 K
Vout V in +
3V + V0ut
1 K -

8 K

(a) -1 (b) -20


(a) 1 V (b) 6 V
(b) -100 (d) -120
(c) 14 V (d) 17 V

50. The circuit of figure shows a 555 Timer IC


47. If the input to the ideal comparator shown in connected as an astable multivibrator. The value
the figure is sinusoidal signal of 8 V (Peak to of the capacitor C is 10 nF. The values of the
peak) without any DC component, then the resistors RA and RB for a frequency of 10 KHz
output of the comparator has a duty cycle of and a duty cycle of 0.75 for the output voltage
(GATE (EC) - 2003) waveform are
(GATE (EE) - 2003) (2M)
Input +
Output VC C

V re f=2V -

(a) 1/2 (b) 1/3 Vout


RA
(c) 1/6 (d) 1/12
Th
R1
RB
48. If the differential voltage gain and the common Tr
mode voltage gain of a differential amplifier are C 555
Timer
48 db and 2 db respectively, then its common IC
mode rejection ratio is
(GATE (EC) - 2003)
159
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) R A  3.62K, R B  3.62k (a) Voltage controlled current source


(b) Voltage controlled voltage source
(b) R A  3.62K, R B  7.25k
(c) Current controlled current source
(c) R A  7.25K, R B  3.62k (d) Current controlled voltage source

(d) R A  7.25K, R B  7.25k


54. In the Op-amp circuit given in the figure, the
load current iL is
51. For the circuit of figure with an ideal operational (GATE (EC) - 2004)
amplifier, the maximum phase shift of the output
Vout with reference to the input Vin is
R1 R1
(GATE (EE) - 2003)
VS

+
R2

R2

RL
(a) 0° (b) –90° iL
(c) +90° (d) + 180°

Vs Vs
52. The circuit in the figure is a (a)  R (b) R2
2
(GATE (EC) - 2004)
Vs Vs
(c)  R (d) R1
L
-
V ou t
R R +
V in
55. The input resistance R IN   Vx / i x  of the
circuit in figure is
(a) low-pass filter (b) high-pass filter (GATE (EE) - 2004) (2M)
(c) band-pass filter (d) band-reject filter

53. An ideal op-amp is an ideal


(GATE (EC) - 2004)

160
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

R1=10k R 1=100k  1M

- eo
- +
Vy
+ 1M

Vx (a) Bias current of the inverting input only


IA R 3=1M
(b) Bias current of the inverting and non-
inverting inputs only
(a) 100k (b) 100k
(c) Input offset current only
(c) 1M (d) 1M
(d) Both the bias current and the input offset
current
56. In the active filter shown in figure, if Q=1, a
pair of poles will be realized with 0 equal to
58. The Op-amp circuit shown in the figure is a
(GATE (EE) - 2004) filter. The type of filter and its cut-off frequency
are respectively
(GATE (EC) - 2005)
10 K

10 K
-

Vi +
F
1K

(a) high pass, 1000 rad/sec


(a) 10,000 rad/s (b) 1,000 rad/s
(b) low pass, 1000 rad/sec.
(c) 100 rad/s (d) 10 rad/s
(c) high pass, 10000 rad/sec
(d) low pass, 10000 rad/sec.
57. The voltage e0 indicated in the figure has been
measured by an ideal voltmeter. Which of the
following can be calculated? 59. Given the ideal operational amplifier circuit
shown in the figure indicate the correct transfer
(GATE (EC) - 2005) characteristics assuming ideal diodes with zero
cut - in voltage

161
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(GATE (EC) - 2005)


V0
+10 V +10 V
Vi -
V0
+
-10 V -5 V +5 V
Vi
2 k (d)

0.5 k
-5 V

2 k

60. The input resistance R i of the amplifier shown


V0 in the figure is
+10 V (GATE (EC) - 2005)

30 K
-8 V -5 V
(a) Vi

10 K
-
-10 V
+
Ideal operational amplifier
Ri
V0
+10 V
30
(a) k (b) 10k
4
-5 V +8 V (c) 40k (d) infinite
(b) Vi

61. In an ideal differential amplifier shown in the


-10 V figure, a large value of (RE).
(GATE (EC) - 2005)
V0 VC C
+10 V
RC RC

-5 V +5 V Vi
(c)

-10 V V1 V2
RE
-V E E

162
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) Increases both the differential and


common-mode gains Vo ut

(b) Increases the common-mode gain only


t
(c) decreases the differential-mode gain only (c) t
l
l

(d) decreases the common-mode gain only

62. In the given figure, if the input is a sinusoidal


signal, the output will appear as shown in
(GATE (EE) - 2005) (2M) V o ut

V in
(d) t
l

t
l

63. Consider the inverting amplifier, using an ideal


operational amplifier shown in the figure. The
R designer wishes to realize the input resistance
+V
- seen by the small - signal source to be as large
as possible, while keeping the voltage gain
+ between -10 and -25. The upper limit on RF is
+
-V 1M . The value of R1 should be
R
RL Vou t
(GATE (EE) - 2005) (2M)

RF

V out
R1
V in +
(a) V0ut
-
t
l

V ou t

(a) Infinity (b) 1M


(b) t
l

(c) 100k (d) 40k

163
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Statement for linked Answer Questions 64


and 65 S C=1 F
A regulated power supply, shown in figure
below, has an unregulated input (UR) of 15 -VC +
Volts and generates a regulated output Vout. Use
the component values shown in the figure. -
1K
+
10V

In the figure shown above, the Op AMP is


supplied with  15 V..
(GATE (EC) - 2006)
(a) 0 Volts (b) 6.3 Volts
(c) 9.45 Volts (d) 10 Volts
In the figure above, the ground has been shown
by the symbol 
67. For a given sinusoidal input voltage, the voltage
waveform at point P of the clamper circuit
64. The power dissipation across the transistor Q1 shown in the figure will be
shown in the figure is
(GATE (EE) - 2006) (1M) (IES (EE) - 2010)
(GATE (EC) - 2006)
(a) 4.8 Watts (b) 5.0 Watts
(c) 5.4 Watts (d) 6.0 Watts +12 V
-
RL
65. If the unregulated voltage increase by 20%, the C
+ P
-
power dissipation across the transistor Q1
(GATE (EC) - 2006) ~+ Vi n -12 V

(a) increases by 20%


(b) increases by 50%
(c) remains unchanged
(d) decreases by 20%

66. For the circuit shown in the following figure,


the capacitor C is initially uncharged, At t = 0,
the switch S is closed. The voltage VC across (a)
the capacitor at t = 1 millisecond is

164
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

6
(b) (a) -10

(c) 12 V -10

-0.7V
(b)
6

-0.7V
(d) 6
12 V
(c)
-10

68. A relaxation oscillator is made using OPAMP


as shown in figure. The supply voltages of the
OPAMP are 12V. The voltage waveform at
point P will be
(GATE (EE) - 2006) (2M)
10
R1
(d)
R2 -6

C
-

+
69. In the OP-Amp circuit shown, assume that
2k
the diode current follows the equation
P I=ISexp(V/VT). For Vi  2V, V0  V01, for
10k
10 k
Vi  4V, V0  V02 . The relationship between
V01 and V02 is
165
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(GATE (EC) - 2007) 71. The transfer function V0  S / Vi  S is

(GATE (EC) - 2007)

1  sRC 1  sRC
Vi - (a) (b)
2 k 1  sRC 1  sRC
V0
+
1 1
(c) (d)
1  sRC 1  sRC

(a) V02  2V01 (b) V02  e 2 V01

(c) V02  V01In2 (d) V01  V02  VT In2 72. If Vi  V1 sin  t  and V0  V2 sin  t   ,
then the minimum and maximum values of 
(in radians) are respectively
70. For the Op-amp circuit shown in the figure, V0
is (GATE (EC) - 2007)
(GATE (EC) - 2007) (a)  π / 2 and π / 2 (b) 0 and π / 2

2k (c)  π and 0 (d)  π / 2 and 0

1k
- 73. IC 555 in the adjacent figure is configured as
1V V0
+ an astable multivibrator. It is enabled to oscillate
1k at t = 0 by applying a high input to pin 4. The
1k pin description is : 1 and 8 - supply; 2 - trigger;
4-reset ; 6-threshold, 7-discharge. The
waveform appearing across the capacitor
(a) -2V (b) -1 V starting from t = 0, as observed on a storage
CRO is
(c) -0.5 V (d) 0.5 V
(GATE (EE) - 2007) (2M)

Statement for Linked Questions 71 and 72 +

Consider the Op-Amp circuit shown in the


figure
8
10 K
R1
7
R2
- 10 K IC 555 3
Vi V0
+ 2,6
R
C 4 1

166
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

+10 V

+10 V
1 K
-
(a) Vout
+ 5.0 V
0.01
-10 V +10 K
F
S 100 K
5.0 V

(b) (a) It makes a transition from -5 V to +5 V at


t = 12.98 μs
(b) It makes a transition from -5 V to +5 V at
t = 2.57 μs
(c) It makes a transition from +5 V to –5 V at
t = 12.98 μs
(d) It makes a transition from +5 V to –5 V at
(c) t = 2.57 μs

75. The circuit shown in the figure is


(GATE (EE) - 2007) (1M)

R1
(d)
+
-
V R2
+
LOAD
74. The switch S in the circuit of the figure is initially
closed, it is opened at time t = 0, you may F
neglect the Zener diode forward voltage drops.
What is the behaviour of Vout for t > 0?
(GATE (EE) - 2007) (2M) rV
(a) a voltage source with voltage R || R
1 2

r || R 2
(b) a voltage source with voltage .V
R1

167
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

r || R 2 V where VT  25mV, I0  1μA and V is the


(c) a current source with current R  R . r voltage across the diode (taken as positive for
1 2
forward bias)
R2 V
(d) a current source with current R  R . r
1 2 D 4K

76. Consider the Schmitt trigger circuit shown Vi=1 V


below -
100 K
V0
+
+15 V
10 K

Vi ) -
V0
For an input voltage Vi  1V , the output
+
voltageV0 is
10 K (GATE (EC) - 2008)
)
(a) 0 V (b) 0.1V
(c) 0.7 V (d) 1.1 V
10 K
-15 V
78. The OPAMP circuit shown represents a
A triangular wave which goes from -12 V to (GATE (EC) - 2008)
12 V is applied to the inverting input of the
OPAMP. Assume that the output of the C
OPAMP swings from +15 V to -15 V. The
voltage at the non-inverting input switches
between R2
(GATE (EC) - 2008)
Vi -
(a) – 12 V and + 12 V R1
L V0
+
(b) – 7.5 V and + 7.5 V
(c) – 5 V and + 5 V
(d) 0 V and 5 V
(a) high pass filter (b) low pass filter
(c) band pass filter (d) band reject filter
77. Consider the following circuit using an ideal
OPAMP. The I-V characteristics of the diode
79. An astable multivibrator circuit using IC 555
 VV 
is described by the relation I  I0  e T  1 timer is shown below. Assume that the circuit
  is oscillating steadly.
 

168
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

If the voltage Vi is made +2.5 V, the voltage


waveform at point ‘P’ will become
9K

30 K 5

4 8 2.5
(Reset) (Su pply) (a)
0
6(Threshold )
(Outpu t)3
0
10 K
2.5
2(Tri gger) (Gnd) (b)
(Discharg e) 1 5
7

12 K 5V

VC .01 F
0 t(sec)
(c)
l

-5V

5V
The voltage VC across the capacitor varies
between 0 t(sec)
(d)
l

(GATE (EC) - 2008) -5V

(a) 3V to 5V (b) 3V to 6V
(c) 3.6 V to 6V (d) 3.6V to 5V
Statement for Linked Questions 81 and 82
A general filter circuit is shown in the figure:
80. A wavetorm generator circuit using OPAMPs
is shown in the figure. It produces a triangular R2
wave at point ’P’ with a peak to peak voltage
of 5 V for Vi = 0 V
Vi R1 C
(GATE (EE) - 2008) -

+ V0
C R3 VA

R
- - ‘P’
R4
+ +
R1
V1

+12 V -12 V 81. If R1  R 2  R A , R 3  R 4  R B , the circuit


R1 acts as a
(GATE (EE) - 2008) (2M)

169
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) all p ass filter (b) band pass filter


(c) high pass filter (d) low pass filter

82. The output of the filter in above question is given (d)


to the circuit shown in figure:

RA /2
83. The block diagrams of two of half wave rectifier
are shown in the figure. The transfer
characteristics of the rectifiers are also shown.
C
V in V0 P

V0

Vin Vo
0

The gain VS frequency characteristics of the


output (V0) will be
(GATE (EE) - 2008) (2M) Q

V0

Vo Vo

0
Vi n
Gain

(a) It is desired to make full wave rectifier using


 above two half - wave rectifiers. The resultant
circuit will be
(GATE (EE) - 2008) (2M)

R
Gain
(b) R
Vi n
P -
V0
 (a) R +
Q

Gain R

(c)
Vin R
P -
 V0
(b) R +
Q
R

170
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

circuit is positive or negative and determine the


R
voltage V at the output of the op-amp.
Vi n R
-
(GATE (EC) - 2009)
P
V0
(c) Q
R
+

R
5 k

R R +
V
-

- 1.4 k
Vin R V0 5V
P +
(d) R
Q
(a) Positive feedback, V = 10 V
(b) Positive feedback, V=0V
84. In the following asatble multivibrator circuit, (c) Negative feeback , V=5V
which properties of V0(t) depend on R2 ? (d) Negative feedback, V=2V
(GATE (EC) - 2009)

86. An ideal opamp circuit and its input wave form


R1
are shown in the figures. The output waveform
of this circuit will be
(GATE (EE) - 2009) (2M)
-
V0 (t)
C + R3

R2 R4

(a) Only the frequency


(b) Only the amplitude
(c) Both the amplitude and the frequency
(d) Neither the amplitude nor the frequency

85. In the circuit shown below, the Op-amp is


ideal, the transistor has VBE  0.6V and
β  150 . Decide whether the feedback in the
171
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

87. The following circuit has R  10k ,


C  10μF . The input voltage is a sinusoid at
50 Hz with an rms value of 10 V. Under ideal
conditions the current from the source is
(GATE (EE) - 2009) (2M)
(a)
R
10 k

Vs=10Vrms,50Hz
IS +
Opamp
~ -

10 k
R
(b) C
10F

(a) 10mA leading by 90o

(b) 20mA leading by 90o

(c) 10A leading by 90o

(d) 10mA lagging by 90o

(c)
88. The nature of feedback in the opamp circuit
shown is
(GATE (EE) - 2009) (1M)

1 K +6v
- 2 K
V0
+
Vi n -6 v

(d)
(a) Current - Current feedback
(b) Voltage - Voltage feedback

172
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(c) Current - Voltage feedback


V0
(d) Voltage - Current feedback
10

(a)
89. Assuming the OP-AMP to be ideal, the voltage
Vl
gain of the amplifier shown below is -10 -5 0

(GATE (EC) - 2010)


V0

R1
-
V0
(b) 5
+
+
Vi - R2 -10 -5 0
Vl

V0
R3

(c) 5

R2 R3 0 +5
Vl
(a)  (b)  R
R1 1

V0
 R || R 3   R2  R3 
(c)  2  (d)   R 
 R1   1  10
(d)
Vl
0 +5
90. The transfer characteristic for the precision
rectifier circuit shown below is (assume ideal
OP-AMP and practical diodes)
91. Given that the OP-AMP is ideal, the output
(GATE (EC) - 2010)
voltage V0 is

+20 V (GATE (EE) - 2010)

2R
R
4R

D2
VI - R + 10 v
R -
V0
+ D1 V0
+
+2 V - 10 v

173
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) 4 V (b) 6 V
(c) 7.5 V (d) 12.12 V

92. The circuit below implements a filter between


the input current ii and the output voltage v0. (b)
Assume that the opamp is ideal. The filter
implemented is a
(GATE (EC) - 2011)

(c)

(a) low pass filter (b) band pass filter


(c) band stop filter (d) high pass filter

93. For the circuit shown below,

(d)

94. The circuit shown is a


(GATE (EE) (EC) - 2012)
the CORRECT transfer characteristic is
(GATE (EE) - 2011)

(a) (a) Low pass filter with


1
f3dB = rad/s
 R1 + R 2  C
174
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

1 (a) 4 (b) 6
(b) High pass filter with f 3dB = rad/s
R1 C (c) 8 (d) 10

1
(c) Low pass filter with f3dB = rad/s 97. In the feedback network shown below, if the
R1 C
feedback factor k is increased, then the
(d) High pass filter with (GATE (EE) - 2013)
1
f3dB = rad/s
 R1 +R 2  C

95. In the circuit shown below what is the output


voltage (Vout) if a silicon transistor Q and an
ideal op-amp are used ?
(GATE (EC) - 2013) (a) input impedance increases and output
impedance decreases.
(b) input impedance increases and output
impedance also increases.
(c) input impedance decreases and output
impedance also decreases.
(d) input impedance decreases and output
impedance increases.

(a) –15 V (b) –0.7 V


98. Consider the following circuit:
(c) +0.7 V (d) +15 V
1K 1K
1V

96. In the circuit shown below the op-amps are 2K


1V
ideal. Then Vout in volts is
3K
1V
(GATE (EC) - 2013) +
V0
1K -
1V

1K
1V
1K
1V

What is the output voltage V0 in the above


circuit?
(a) 9.5 V (b) 3 V
(c) 32.2 V (d) 1 V

175
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

99. What is the output voltage V0 of the given


circuit? v
l

(IES (EE) - 2008)


V

2 50 K

50 K (c)
Va - T
+ tp
l

V0 +
50 K
V0

-
v
l

(a) 5Va  25Vb (b) 5Va  3Vb

(c) 2.5Va  2.5Vb (d) 2.5Va  3Vb


(d)
T
tp
l

100. Which one of the following is the output of the


high pass filter to a step input?

101. The Schmitt trigger circuit is shown in the below


v
l

figure. If Vsat  10V , the tripping point for the


increasing input voltage will be
V
(IES (EE) - 2001)

(a) + 12 V

10 K

+
)

T -
-12 V
47 K

V in
V out
1K

V 7= 0.7 V
v
l

V (a) 1 V (b) 0.893 V


(b)
(c) 0.477 V (d) 0.416V

T 102. In the op-amp circuit shown below. The current


I L is
176
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(IES (EE) - 2003)


R2

ZL
R1
IL Vi +
R1 V0
- -

+
R0

VI
(a) increase gain
(b) reduce offset voltage
(a) V/ ZL (b) V / Z L IR 1 (c) reduce offset current
(c) Vi / R1 (d) Vi  R1  ZL  (d) increase CMRR

105. An op-amp has a differential gain of 10³ and a


103. In the op-amp circuit shown below Vi  0 and CMRR of 100. The output voltage of the op-
i  I 0 eaV . The output V0 will be proportional amp with inputs of 120μV and 80μV will be
to (IES (EE) - 2003)
(IES (EE) - 2002) (a) 26 mV (b) 41 mV
(c) 100 mV (d) 200 m V
V
+ -
i
i

R1 106. Consider the following statements with


Vi - reference to an ideal voltage follower circuit as
V0 shown below:
+

R2

-
+
+
(a) Vi (b) Vi

(c) e KVi (d) In  kVi  -

104. In the inverting op-amp circuit shown below 1. Unity gain and no phase shift
the resistance Rg is chosen as R1 || R2 in order 2. Infinite gain and 180°C phase shift
to
3. Very high input impedance and very low
(IES (EE) - 2002) output impedance
177
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

4. It is a buffer amplifier
Vou t
Which of these statements are correct?
(IES (EE) - 2003)
(a) 1 and 3 (b) 2 and 4 (d) t
l

(c) 1, 3 and 4 (d) 1, 2, 3 and 4

107. For the below circuit what will be the output


for the sinusoidal input shown at the input 108. The slew rate of an op-amp is 0.5 V/microsec.
terminal? The maximum frequency of a sinusoidal input
of 2V rms that can be handled without
(IES (EE) - 2009)
excessive distortion is
R +V (IES (EE) - 2001)
V in - +
(a) 3 kHz (b) 30 kHz
+
-V (c) 200 kHz (d) 2 MHZ
R
RL V ou t
109 . An op-amp is used in the circuit as shown in
- the below figure, Current I0 is
(IES (EE) - 2001)
V o ut
vs -
(a)
+ I0
t
l
RL

Vou t RS

t
l

(b) RL
(a) Vs 
RS RL  RS 

(b) VS / R S
Vou t
(c) VS / R L

(c) t
l

 1 1 
(d) VS   
 RS R L 

178
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

110. A circuit with op-amp is shown in the below


VS R L VS
figure. The voltage V0 is (a) b)
RS  R L  R S  RS
(IES (EE) - 2001)
VS  1 1 
2R (c) RL (d) VS  R  R 
 L S 

R
vs2 113. The cut-in voltage of the diodes in the rectifier
- of Figure is 0.6 V
V0
Vs1 +

(a) VS1  6VS2 (b) 2VS1  3VS2

(c) 2VS1  2VS2 (d) 3VS1  2VS2

111. A sinusoidal waveform can be converted to a Identify the correct output input characteristic
square waveform by using a (V0 vs Vi )
(IES (EE) - 2001)
(a) two stage transistorized over driven
amplifier
(a)
(b) two stage diode detector circuit
(c) voltage comparator based on op-amp
(d) regenrative voltage comparator circuit

112. Which one of the following is the correct (b)


expression for the current I0 ?
(IES (EE) - 2004)

Vs +
V0 (c)
- I0 RL

RS
(d)

179
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

114. In the circuit shown in Figure , if ei = sin t, the


voltage e0 is

  1  
(a) 2 sin  t   (b) sin  t  
 4 2  4

1    
(c) sin  t   (d) 2 sin  t  
2  4  4
(a) 11 v1 (b) 10 v1
(c) v1 (d) zero
115. The output voltage V0 of the given circuit is

118. In the circuit shown in the given figure, V0 is


given by

(a) – 100 V (b) – 100 mV


(c) 10 V (d) – 10 mV
(a) sin (t –  /4) (b) sin (t +  /4)
(c) sin t (d) cos t
116. The voltage gain versus frequency curve of an
Op-Amp is shown in the given figure
119. An op-amp circuit is shown in the figure

The gain-bandwidth product of the Op-Amp


is The output V0 will be (assume ideal op-amp)

(a) 200 Hz (b) 200 MHz (a) equal to zero because the input is zero

(c) 200 kHz (d) 2 MHz (b) dependent on element values hence
nothing can be predicted without a
knowledge of element values
117. The v0 of the Op-Amp circuit shown in the given (c) a square wave varying between +VCC and
figure is –VCC
(d) a sinusoidal wave of amplifier VCC

180
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

120. A non-inverting op-amp is shown below


(assume ideal op-amp)

(a) – 5 mA (b) – 10 mA
The output voltage V0 for an input Vi = [2 + sin (c) + 25 mA (d) – 50 mA
(100 t)] V
(a) 3/2 sin (100 t)
123. Consider the following circuit :
(b) 3 sin (100 t)
(c) 2 sin (100 t)
(d) 3 sin (100 t) + 1/2

121. Consider the following circuit

How does the above circuit work


(a) As a logarithmic amplifier
(b) As a negative clipper
(c) As a positive clipper
(d) As a half-wave rectifier
Which is the function of diode D2 in the above
circuit ?
124. The circuit shown in the given figure is
(a) To avoid saturation of the Op-Amp
(IES (EC) - 1996)
(b) To provide negative feedback when the
input is negative
(c) To reduce reverse breakdown voltage of
D1
(d) As a buffer

122. What is the load current IL in the circuit


below ? (a) an amplifier
(b) an oscillator

181
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(c) a high pass filter


(d) a saw tooth generator

125. The op-amp circuit shown in the given figure


can be used for
(IES (EC) - 1996) (a) low pass filter (b) high pass filter
(c) band pass filter (d) band stop filter

128. By proper selection of Rf and R1 , the circuit


shown in the given figure can be used as a
(IES (EC) - 1996)

(a) addition
(b) subtraction
(c) both addition and subtraction
(d) multiplication

126. The circuit diagram of an op-amp based


amplifier is shown in the given figure. The ratio (a) ramp generator

Vout (b) square wave generator


Vin is equal to (c) saw tooth generator
(d) sine wave generator
(IES (EC) - 1996)

129. For the circuit shown in the given figure,


assuming ideal diodes the output waveform Vo
will be
(IES (EC) - 1996)

(a) 9 (b) 11
(c) 10 (d) 21

127. The filter shown in the figure uses an ideal op-


amp. It represents a
(IES (EC) - 1996)
182
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) (b)

(c)
(b)

(d)
(c)

131. In active filter circuits inductances are avoided


mainly because they

(d) (IES (EC) - 1997)


(a) are always associated with some
resistance
(b) are bulky and unsuitable for miniaturisation
130. For the circuit shown in the given figure,
assuming ideal op-amps, the out put (c) are non-linear in nature
corresponding to the given input will as in (d) saturate quickly
(IES (EC) - 1996)
132. In the case of the circuit shown in the figure,
Vio = 10 mV dc maximum, the maximum
possible output offset voltage V00 caused by
the input offset voltage Vio with respect to
ground is :
(IES (EC) - 1997)

(a)

183
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) 60 mV dc (b) 110 mV dc where f0 is the zero frequency and fp is the pole
(c) 130 mV dc (d) 150 mV dc frequency. For a standard frequency response
of the amplifier.
(IES (EC) - 1997)
133. In order to obtain triangular pulses at the output
of the circuit shown in the figure the input should (a) fp >> fo (b) fp = fo
be (c) fp << fo (d) fo = 2fp
(IES (EC) - 1997)
136. The OP-AMP circuit shown in the figure is
(IES (EC) - 1997)

(a) grounded
(b) a square wave
(c) a triangular wave (a) a sample/hold circuit
(d) a trigger (b) a rectifier/amplifier circuit
(c) a peak detector circuit
134. The transfer function of an amplifier is given by (d) an antilog amplifier circuit

Vo 2810
Av   137. In the circuit shown, it is required that Vo = Vi
Vs  f  f 
1  j 5 
1 j 6  the values of l, m, n are, respectively (x
 5.85  10   5.85  10 
represents don’t care condition)
The high 3-db frequency of the amplifier will (IES (EC) - 1998)
be approximately
(IES (EC) - 1997)
(a) 5850 kHz (b) 585 kHz
(c) 5850 Hz (d) 585 Hz

135. In the case of an amplifier, the normalised


voltage gain is given by (a) 0, 1, 1 (b) , x, x
f (b) x, , x (d) 0, x, 
1 j
Av 1 fo
 .
Ao 1  R 1  j f
138. Consider the following statements in respect
R fp
of the circuit shown in the given figure (assume
184
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

ideal OP-AMP) : 140. The expression for the output voltage Vo in


terms of the input voltage V1 and V2 in the circuit
(IES (EC) - 1998) shown in the figure, assuming the operational
amplifier to be ideal is :
Vo = A1 V1 + A2 V2
The values of A1 and A2 would be respectively
(IES (EE) - 1997)

1. The common mode input impedance is


1/2 M 
2. The differential mode input impedance is
2M
3. The differential mode gain is 50
(a) 9 and –10 (b) 9.9 and –10
4. The common mode gain is zero
(c) –9 and 10 (d) –9.9 and 10
Of these statements
(a) 1, 2, 3 and 4 are correct
141. The transfer gain for the circuit shown in the
(b) 1, 2 and 3 are correct
figure is given by
(c) 2, 3 and 4 are correct
(IES (EE) - 1997)
(d) 1 and 4 are correct

139. A non-inverting OP-AMP summer is shown in


the figure. The output voltage V0 is
(IES (EE) - 1997)

 R2 R3 
 R2  R3  R 
4
 
(a)  R1 
 

3
(a) sin 100 t (b) sin 100 t  R3 R4 
2  R  R  R2 
 3 4

(c) 2 sin 100 t (d) 3 sin 100 t (b)  R1 
 

185
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

 R2 R4 
 R  R  R3 
 2 4

(c)  R1  (d)
 

 R2  R3 
(d)   R 
 1  144. In the circuit shown in the given figure, the
output voltage will be
(IES (EE) - 1998)
142. If the differential and common mode gains of a
differential amplifier are 50 and 0.2
respectively, then the CMRR will be
(IES (EE) - 1998)
(a) 10 (b) 49.8
(c) 50.2 (d) 250

143. An operational amplifier can be connected as


a non-inverting voltage comparater as shown (a) 9 V (b) 10 V
in
(c) 11 V (d) 12 V
(IES (EE) - 1998)
145. The open-loop gain of an operational amplifier
is 105. An input signal of 1m V is applied to the
inverting input with the noninverting connected
(a) to the ground. The supply voltage is  10V..
The output of the amplifier will be
(IES (EE) - 1998)
(a) + 100 V
(b) (b) – 100 V
(c) + 10 V (approximately)
(d) – 10 V (approximately)

146. A unit positive step is applied at the input of the


(c) circuit shown in the figure. After 20 seconds,
the output Vo will be
(IES (EE) - 1998)

186
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Which one of the following statements is


correct?
In the above circuit condensars C1 and C 2 are
used
(IES (EE) - 2004)
(a) + 20 V (b) + 10 V (a) for passing the noise
(c) – 10 V (d) – 20 V (b) to compensate the collector - emitter
capacitance
(c) to speed up the switching action
147. The output voltage of the circuit shown in the
given figure is (d) to provide negative feedback path

(IES (EE) - 1998)


149. Match list - I (Circuit) with List - II
(Application) and select the correct answer
using the codes given below:
(IES (EE) - 2004)
List - I
A. Monostable mutlivibrator
B. Bistable multivibrator translator
C. Clamping circuit
(a) 1.0 V (b) 1.5 V
D. Schmitt trigger
(c) 2.0 V (d) 2.5 V
List - II
1. Comparator
148. Consider the following bistable multi-vibrator
2. d.c level
circuit?
3. Delay
+Ve 4. Voltage controlled oscillator
5. Counter
RC C1 C2 Re
Codes:
A B C D
R1 R1
)

(a) 4 3 1 2
(b) 3 5 2 1
T1
R2 R2
T2 (c) 4 5 2 1
(d) 5 4 1 2
-Ve

187
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

150. Consider the following statements: (c) I is true but II is false


The 555 timer can be employed in (d) I is false but II is true
1. a monostable multivibrator
2. a bistable multivibrator. 153. The output of the circuit shown in the figure
3. an astable multivibrator will be

Of these statements: (IES (EC) - 1997)

(IES (EC) - 1996)


(a) 1 and 2 are correct
(b) 1 and 3 are correct
(c) 2 and 3 are correct
(d) 1, 2 and 3 are correct
(a) Delayed pulses
151. For a sinusoidal input, the circuit shown in the (b) Square waves
figure will act as a (c) Triangular waves
(IES (EC) - 1997) (d) Trapezoidal waves

154. In order to rectify sinusoidal signals of millivolt


range (< 0.6 V).
(IES (EC) - 1998)
(a) bridge rectifier using diodes can be
employed
(a) pulse generator (b) full wave rectifier
(b) full-wave diode rectifier can be used
(c) ramp generator (d) voltage doubler
(c) a diode is to be inserted in the feedback
loop of an OP-AMP
152. Consider the following statements : (d) a diode is to be inserted in the input of an
I: A differential amplifier is used at the input OP-AMP
stage of an operational amplifier
II : Differential amplifiers have very high 155. The circuit shown in the figure represents a
CMRR
(IES (EC) - 1997)
Of these statements
(IES (EC) - 1997)
(a) both I and II are true and II is the correct
explanation of I
(b) both I and II are true but II is not the
ONLY explanation of I
188
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) low-pass filter (b) high-pass filter 159. In the circuit shown in the figure, the value of
(c) band-pass filter (d) band-stop filter output ‘v0’ is
(IES (EE) - 1999)

156. In the circuit shown in the figure.


(IES (EC) - 1998)

(a) + 3V (b) – 3V
(c) – 7V (d) + 7V

160. The Op-amp shown has a unity-gain bandwidth


(a) only red will glow of 1 MHz and a dominant pole at 10 Hz. The
bandwidth of the non-inverting amplifier will be
(b) only green will glow
(IES (EE) - 1999)
(c) both red and green will glow
(d) neither red nor green will glow

157. For the high-pass circuit to act as a


differentiator, the time constant must be
(IES (EC) - 1998)
(a) small
(b) very small in comparison to the time period
of the input signal (a) 10 MHz (b) 1 MHz
(c) very high in comparison to the time period (c) 250 kHz (d) 200 kHz
of the input signal (that is low pass circuit)
(d) of moderate value. 161. An Op-amp with open-loop gain of 10,000,
Rin = 2 k and R0 = 500  is used in the
non-inverting configuration as shown in the
158. In a bistable multivibrator, commutating figure. The output resistance Rof is
capacitors are used to
(IES (EE) - 1999)
(IES (EC) - 1998)
(a) increase the base storage charge
(b) provide ac coupling
(c) increase the speed of response
(d) alter the frequency of the output

189
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) 250.5  (b) 21  (a) zero (b) 6 mA


(c) 10 mA (d) 12 mA
(c) 2  (d) 0.998 

165. Match List -I (Circuits) with List-II


162. In an amplifier, the increase in gain is 12 dB if (Applications) and select the correct answer
the frequency doubled. If the frequency is using the codes given below the lists :
increased by 10 times, then the increase in gain
will be (IES (EE) - 2000)
(IES (EE) - 2000) List-I
(a) 2.4 dB (b) 20 dB A. Astable multivibrator
(c) 40 dB (d) 60 dB B. Schmitt trigger
C. Bistable multivibrator
163. An op-amp has a common mode gain of 0.01 List-II
and a differential mode gain of 105 . Its common 1. Counter
mode rejection ratio would be
2. Sweep generator
(IES (EE) - 2000, 2013)
3. Voltage to frequency converter
(a) 10–7 (b) 10–3
4. Comparator
(c) 103 (d) 107
Codes:
A B C
164. An op-amp circuit is shown in the given figure.
(a) 3 4 1
The current ‘I’ is
(b) 3 2 1
(IES (EE) - 2000)
(c) 1 4 3
(d) 1 2 3

166. A monostable multivibrator circuit is shown in


the given figure. The value of C would be nearly
(IES (EE) - 2000)

190
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) 0.001 μF (b) 0.01 μF (b) Pulse modulator and astable multivibrator

(c) 0.1 μF (d) 1 μF (c) Amplitude demodulator and AC to DC


converter
(d) AC to DC converter and astable
167. Circuit shown in the given figure represents multivibrator

170. Consider the following statements:


In order to generate square wave from a
sinusoidal input signal one can use
1. Schmitt trigger circuit
2. Clippers and amplifiers
3. Monostable multivibrators
(IES (EC) - 1999) (IES (EC) - 2004) Which of the above statements is/are correct?
(a) an astable multivibrator (IES (EC) - 2002)
(b) a monostable multivibrator (a) 1 alone (b) 1 and 2
(c) voltage-controlled oscillator (c) 2 and 3 (d) 1, 2 and 3
(d) ramp generator

171. Match List-I (Circuit Name) with List-II


168. A 1ms pulse can be stretched to 1s pulse by (Characteristics) and select the correct answer
using using the codes given below the lists:

(IES (EC) - 1999) (IES (EC) - 2003)

(a) an astable multivibrator List-I

(b) a monostable multivibrator A. Schmitt trigger

(c) a bistable multivibrator B. Monostable multivibrator

(d) a Schmitt trigger circuit C. Astable multivibrator


D. Blocking oscillator

169. Which one of the following sets of circuits can List-II


be obtained by using a 555 timer ? 1. It needs a pulse transformer
(IES (EC) - 2000) 2. It is used to generate gating pulse whose
(a) Pulse modulator and amplitude width can be controlled
demodulator 3. It is a bistable circuit
191
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

4. It has no stable state C. Square wave generator

Codes: D. Narrow current pulse generator


List-II
A B C D
1. Astable multivibrator
(a) 3 2 4 1
2. Schmitt trigger
(b) 2 3 1 4
3. Bistable multivibrator
(c) 3 2 1 4 4. Blocking oscillator
(d) 2 3 4 1 Codes:
A B C D
172. The function of the diode D in the timer circuit (a) 4 2 1 3
shown below is to (b) 3 2 1 4
(IES (EC) - 2003) (c) 4 1 2 3
(d) 3 1 2 4

174. Pulses of definite width can be obtained from


irregular shaped pulses.
(IES (EC) - 2005)
(a) When it is given as input to a monostable
multivibrator
(b) When it is given as triggering signal to
(a) Increase the charging time of C bistable multivibrator
(b) Decrease the charging time of C (c) When it is used as input to a Schmitt
(c) Increase the discharging time of C trigger

(d) Decrease the discharging time of C (d) When it is used as input to a pulse
transformer

173. Match List-I (Application of the Circuit) with


List-II (Circuit Name) and select the correct 175. Narrow pulses with adjustable mark to space
answer using the codes given below the lists: ratio can be obtained from square wave input
signal by using which of the following ?
(IES (EC) - 2004) 1. Schmitt trigger
List-I 2. Monostable multivibrator
A. Divider 3. Clippers
B. Clips input voltage at two predetermined Select the correct answer using the codes given
levels below:
192
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(IES (EC) - 2006) (a) Bistable multivibrator


(a) Only 1 (b) Only 2 (b) Monostable multivibrator
(c) 1 and 2 (d) 2 and 3 (c) Free running multivibrator
(d) Ramp generator
176. Which one of the following circuits is used for
converting a sine wave into a square wave ?
179. Consider the following statements:
(IES (EC) - 2009)
1. A Schmitt trigger circuit can be emitter-
(a) Astable multivibration coupled bi-stable circuit.
(b) Monostable multivibration 2. Schmitt trigger circuit exhibits hysteresis
phenomenon.
(c) Bistable multivibration
3. The output of a Schmitt trigger will be
(d) Schmitt trigger triangular if the input is square wave.
Which of these statements are correct ?
177. Consider a 565 PL L with RT = 10 k and (IES (EC) - 2011)
CT = 0.01 μF . What is the output frequency
(a) 1, 2 and 3 (b) 1 and 2 only
of the VCO ?
(c) 2 and 3 only (d) 1 and 3 only
(IES (EC) - 2009)
(a) 10 kHz (b) 5 kHz
180. In order to obtain repetitive pulses of unequal
(c) 2.5 kHz (d) 1.25 kHz mark space one can use.
1. A voltage comparator fed with a triangular
178. The circuit shown below is a wave signal and dc voltage
2. An astable multivibrator.
3. A mono-stable multivibrator fed with a
square wave input.
Which of these statements are correct ?
(IES (EC) - 2011)
(a) 1 and 3 only (b) 1 and 2 only
(c) 2 and 3 only (d) 1, 2 and 3

181. Statement (I) : A monostable multivibrator


(IES (EC) - 2010) when switched on remains in a quasi stable
state.
193
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Statement (II) : Quasi stable state duration is (b) Capture range - Lock range = Free
decided by charging time of capacitor. running frequency
(IES (EC) - 2013) (c) Capture range > Lock range
(a) Both Statement (I) and Statement (II) are (d) Capture range < Lock range
individually true and Statement (II) is the
correct explanation of Statement (I).
(b) Both Statement (I) and Statement (II) are 185.
individually true but Statement (II) is not
the correct explanation of Statement (I).
(c) Statement (I) is true but Statement (II) is
false.
(d) Statement (I) is false but Statement (II) is
true.

182. A monostable multivibrator is frequently used


(IES (EC) - 2013)
The circuit shown is :
(a) in memory and timing circuits
(IES (EE) - 2011)
(b) for regeneration of distorted waves
(a) A low pass filter
(c) in counting circuits
(b) A clamper
(d) for producing triangular waves
(c) A lag compensated inverting amplifier
(d) A narrow band video amplifier
183. The frequency of oscillation of a stable
multivibrator with component values
R1 = 2 k , R2 = 20 k , C1 = 0.01 μF and 186.
C2 = 0.05 μF is

(IES (EC) - 2013)


(a) 1428.5 Hz (b) 142.85 Hz
(c) 14.285 Hz (d) 1.4285 Hz

184. In a PLL
(IES (EC) - 2011)
(a) Capture range - Lock range  Free The circuit shown is
running frequency (IES (EE) - 2011)
194
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) A low pass filter 190. In a typical IC monostable multivibrator circuit,


at the falling edge of the trigger input, the output
(b) A high pass filter
switches HIGH for a period of time determined
(c) A comparator by the

(d) An all-pass filter (IES (EE) - 2012)


(a) Value of the RC timing components
(b) Amplitude of the input trigger
187. One shot multivibrator, with a pulse input gives
an output (c) Frequency of the input trigger
(d) Magnitude of the dc supply voltage
(IES (EE) - 2011)
(a) A single triangular pulse
191. A signal Vmsin( ωt   ) is applied to an amplifier
(b) A square pulse
whose gain. A is independent of frequency. The
(c) An impulse amplifier will preserve the form of the input
signal (through with a delay) if the phase shift
(d) A single sinusoid pulse
 is
(IES (EE) - 2013)
188. Virtual ground property of operational amplifier (a) Constant
indicates that
(b) Inversely proportional to frequency
(IES (EE) - 2012)
(c) Proportional to frequency
(a) Inverting and non-inverting terminals are
connected to ground (d) Proportional to the square of the
frequency
(b) Inverting and non-inverting terminals are
at the same potential
(c) System is at rest 192. An operational amplifier is connected in voltage
follower configuration. Input given to this circuit
(d) Any one terminal is connected to ground
is 3sin10³ πt . Compute the slew rate of
operational amplifier
189. A comparator circuit is used to (IES (EE) - 2013)
(IES (EE) - 2012) (a) 6π  103 V / μ sec
(a) Mark the instant when an arbitrary (b) 3π  103 V / μ sec
waveform attains some reference level
(b) Switch off a circuit when output becomes (c) 15π  103 V / μ sec
zero (d) π  103 V / μ sec
(c) Switch on and off a circuit alternately at a
particular rate
(d) Mark the instant when the input voltage 193. An OPAMP has slew rate of 5V/ μs . The
becomes constant. largest sine wave output voltage possible at a
frequency of 1 MHz is
195
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(IES (EE) - 2013)


(a) 10 π V (b) 5V

5 5
(c) V (d) V
π 2π

194. In any function where microphone amplifier and


speakers are used often one would hear a
hamming sound, which increases in volume
gradually. This is due to
(IES (EE) - 2013)
(a) Positive feedback between microphone
and speaker
(b) Negative feedback between microphone
and speaker
(c) Inadequate frequency response of
amplifier
(d) Noise pickup (50 Hz) from power supply

195. Consider the following statements :


1. Astable multivibrator can be used for
generating square wave
2. Bistable multivibrator can be used for
storing binary information
Which of these statement(s) is/are correct ?
(IES (EE) - 2013)
(a) only (b) 2 only
(c) Both 1 and 2 (d) Neither 1 nor 2

196
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

CONVENTIONAL PROBLEMS
01. In Fig. if the CMRR of the operational amplifier
is 60 dB, then the magnitude of the output
voltage is :

04. In Fig. the operational amplifiers are ideal and


their output can swing between –15 and +15
volts. Sketch on same diagrams, the waveform
(GATE (EC) - 1987) of voltages V1 and V2 as a function of time.
You must give the values of important
parameters of this sketch.
02. The Op-Amp in the Fig below is ideal. Find (GATE (EC) - 1991)
the output when Vi = (1 – exp (–  t )) u(t).
Assume the capacitor to be uncharged when
the input is applied and  = 1/CR1. [u(t) is the
unit step function].

05. In order that the circuit of Fig. works properly


(GATE (EC) - 1988) as differentiator, it should be modified to ____
(draw the modified circuit).
(GATE (EC) - 1991)
03. In Fig. the operational amplifier is ideal and its
output can swing between –15 and + 15 volts.
The input vp which is zero for t < 0, is switched
to 5 volts at the instant t = 0. Given that the
output v0 is + 15 volts for t < 0. sketch on the
same diagram the waveforms of v0 and v1. You
must give the values of important parameters
of this sketch.
(GATE (EC) - 1991)

197
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

06. With ideal operational amplifiers, the circuit in


Figure simulates the equation
(GATE (EE) - 1991)

(a) when Ra = Rb = Rc = Rd = 100 ohms.


(b) when Ra = Rb = Rc = 100 ohms and
Rd = 120 ohms.
07. In Figure shown, assume the zener diode and
the operational amplifier to be ideal.
09. Assume that the operational amplifier in figure
(GATE (EE) - 1991) is ideal the current I through the 1K ohm
resistor is _____
(GATE (EC) - 1992)

(a) Draw the equivalent circuit and evaluate


the gain (V0 vs Vi ) of the circuit for
(i) Vi < 0
(ii) 0 < Vi < 5 V
(iii) 5 V < Vi 10. The circuit shown in Fig. is excited by the input
vi as shown. Sketch the wave for m of the
(b) Sketch the gain (V0 vs V) characteristics output v0 , indicating the salient values. Assume
of the above circuit and lable the salient all components to be ideal.
features.
(GATE (EE) - 1992)

08. Consider the circuit shown in Fig. The circuit


uses an ideal operational amplifier. Assuming
that the impedances at nodes A and B do not
load the preceding bridge circuit, calculate the
output voltage Vo.
(GATE (EC) - 1992)

198
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

13. Find the output voltage V0, in the following


circuit assumming that the OP-Amps are ideal.

11. In the following circuit (Figure), the output V


fo llows an equation o f the fo rm
(GATE (EC) - 1993)
d2 v dv
2
+ a + bv = f t  . Find a, b and f(t) .
dt dt
14. A Schmitt trigger is shown in Figure (a) and its
(GATE (EE) - 1992) characteristic is shown in Figure (b). Here VOH
= 10 V, VOL = – 10 V, VIH = 5V, VIL = – 5V.
(GATE (EE) - 1993)
(i) If the input is Vin = (1 + 7 sin  t ) volts,
where ,  = 200  radians/sec calculate
the time duration in each cycle for which
the output of the Schmitt trigger remains
at – 10 V level.
(ii) Draw the circuit diagram of an astable
multivibrator using the Schmitt trigger in
Figure (a), a resistor (R) and a capacitor
(C). If the period of this astable
multivibrats is now to be doubled, what
12. For the ideal Op-Amp circuit of fig. Determine
should be the new values of resistances.
the output voltage V0
(GATE (EC) - 1993)

15. Find the output voltage of the following circuit


assuming ideal op-amp behaviour.

199
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(GATE (EC) - 1994)


(GATE (EC) - 1995)
16. The frequency compensation is used in OP-
Amps to increase its _____ 20. An op-amp is used as a zero-crossing detector.
(GATE (EC) - 1994) If maximum output available from the OP-Amp
is  12 Vp–p and the slew rate of the Op-Amp
is 12 V/  sec then the maximum frequency of
17. Figure below, shows a non-inverting op-amp
the input signal that can be applied without
summer with V1 = 2V and V2 = – 1V. The
causing a reduction in the P–P output is
output voltage V0 = ___________
(GATE (EC) - 1995)
(GATE (EE) - 1994)

21. Sketch the output as a function of the input


voltage (for negative values) for circuit shown
in Fig. show all the OP-AMP, and forward
drop of the diode D1 = 0.
(GATE (EC) - 1995)

18. An analog comparator is a high-gain amplifier


whose output is always either in positive or in
negative saturation.
(TRUE / FLASE)
(GATE (EE) - 1994) 22. Show that the system shown in Figure is a
double integrator. In other words, prove that
the transfer gain is given by
19. In the given circuit of the given figure, if the
voltage inputs V– and V+ are to be Amplified V0  s  1

by the same Amplification factor, the value of  CRs  , assume ideal OP-AMP
2
Vs  s 
‘R’ should be
(GATE (EC) - 1995)

200
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(GATE (EE) - 1995)

26. (a) Figure (a) shows an OP-Amp impedance


23. The common mode voltage of a unity gain converter. Find the input impedance
(voltage follower) op-amp buffer in terms of Ri
its output voltage V0 is _________
(GATE (EE) - 1996)
(GATE (EE) - 1995)

24. For the circuit shown in Figure, determine


V0  s 
Vi  s  and hence write the equations for the
(a)
V0 (b) Draw the V-I characteristic of the
magnitude and phase response of V , If the
i impedance Ri computed in (a)
value of R1 is 100 k Ohm and of R is 10 k (c) The impedance converter is connected to
Ohm, determine the value of C to obtain a a voltage source E 1 in series with a
phase shift of 270° between Vo and Vi for an resistance R as shown in Fig. (c). Draw
input frequecy of 1000 rad/s. the Norton’s equivalent circuit looking into
(GATE (EE) - 1995) point A.

(c)
(d) A capacitor C is connected to the point A
in Figure (c) through a switch S1 at t = 0.
Draw the time response of the voltage
across the capacitor vc(t) for t > 0.
25. For the circuit shown in Figure, determine the
input impedance Z. Assume the op-amp to be
an ideal one.

201
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Vo  s  (b) If R = 100 K , Is = 1  A and


27. (a) Obtain the transfer function V s for
in   KT
= 25mV
the circuit shown in Figure. Assume the Op- q
Amp to be ideal. Yi represents the admittance
Find the input Vi for which V0 = 0
of branch i.
(GATE (EE) - 1996)
29. An IC 555 chip has been used to construct a
pulse generator. Typical pin connections with
components is shown below in fig. for such an
application. However it is desired to generate
a square pulse of 10 KHz.
(GATE (EC) - 1997)

(a)
(b) If Y1 = sC1, Y4 = sC4, Y2 = G2, Y3 = G3,
what is the nature of the filter that will be
realized by the circuit ?

28. Consider the circuit given in fig. using an ideal


operational Amplifier.

Evaluate values of RA and RB if the capacitor


has the values of 0.01  F for the configuration
chosen. If necessary you can suggest
modifications in the external circuit configuration

30. The circuit shown in Figure acts as a ... and for


(GATE (EC) - 1997)
the given inputs, its output voltage is ... V
The characteristics of the diode are given by
(GATE (EE) - 1997)
qV
 
the Relation I  Is e
KT
 1
 
Where V is the forward voltage across the
diode
(a) Express V0 as a function of V1 assuming
Vi > 0

202
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

31. Implement a monostable multivibrator using the average value V0.


timer circuit shown in fig. Also determine an (GATE (EE) - 1999)
expression for ON time T of the o/p pulse.
(GATE (EC) - 1998)

34. Assume that the OP-AMP in the figure, ideal


(GATE (EC) - 2001)

32. In the circuit of Figure, Rs  2k  and


(a) Obtain an expression for V0 in terms of
RL  5k  . For the OP-Amp A = 10 5 , Vs, R and the reverse saturation current
Is of the transistor.
Ri = 100 k  , and R0  50  .
(b) If R = 1  , IS = 1pA and the thermal
For V0 = 10 V, calculate vs and V0 / Vs and
estimate the input resistance of the circuit. voltage VT = 25 mV, then what is the value
of the output voltage V0 for an input
(GATE (EE) - 1998) voltage Vs = 1V ?
(c) Suppose that the transistor in the
feedback path is replaced by a p-n junction
diode with a reverse saturation current of
Is the p-side of the diode is connected to
node A and the n-side to node B. Then
what is the expression for V0 in terms Vs,
R and Is ?

33. The input voltage Vi in the circuit shown in 35. Draw the circuit for precision half-wave and
Figure is a 1 kHz sine-wave of 1V amplitude. full-wave rectifiers, using Op-Amp. Explain
Assume ideal operational amplifiers with 15  their working with the help of waveforms and
VDC supply. Sketch on a single diagram the equations.
waveforms of the voltage Vi 1, Vo and V1
shown, indicating the peak value of V1 and the (IES (EC) - 1997)

203
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

36. A regenerative comparator (Schmitt Trigger)


circuit is shown below.
(IES (EC) - 1997)
(i) Derive expressions for upper threshold
and lower threshold voltages, VUT and VLT
respectively and hence the value of
hysteresis voltage VH . Calculate VUT , VLT
VH for the given values of R1 and R2.
(ii) A sine wave with 2V peak-to-peak
amplitude and 1 kHz frequency is applied
at the input of the circuit. Plot the input (IES (EC) - 2012)
and output waveforms.
40.

A Piezoelectric accelerometer is used with the


signal conditioning circuit shown above. The
accelerometer provides an output of 2.5 mV
per m/s²
37. What are Astable, Monostable and Bistable
multivibrators ? Determine the values of R1, C1, R2 and R3 such
that the system translates this accelerometer
(IES (EE) - 1999)
output to a velocity output V0 of 0.25 volt per
m/s.
38. What should be the ideal characteristics of an (IES (EC) - 2012)
operational amplifier ? Name them. Distinguish
between virtual ground and actual ground.
Define the term “Common mode rejection 41. Determine the output voltage V0 of the circuit
ratio”. How will you measure it ? shown in the figure.
(IES (EE) - 2000)

39. Calculate the output V0 of the circuit shown in


Fig. Calculate the value of R for which the output
of the circuit becomes 0V.

(IES (EE) - 2012)


204
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

ANSWER KEY
01. c 35. d 69. d 103. d 137. b 171. a
02. c 36. a 70. c 104. c 138. a 172. d
03. a 37. c 71. a 105. b 139. b 173. b
04. d 38. b 72. c 106. c 140. b 174. c
05. d 39. c 73. b 107. d 141. c 175. b
06. a 40. a 74. d 108. b 142. d 176. d
07. c 41. b 75. d 109 b 143. b 177. c
08. c,d 42. a 76. c 110. d 144. d 178. b
09. b 43. c 77. b 111. c 145. d 179. b
10. d 44. c 78. b 112. b 146. d 180. d
11. a 45. d 79. b 113. b 147. b 181. d
12. d 46. b 80. a 114. a 148. c 182. b
13. a 47. b 81. c 115. d 149. b 183. a
14. c 48. c 82. d 116. c 150. b 184. c
15. d 49. d 83. c 117. d 151. b 185. c
16. a 50. c 84. a 118. a 152. a 186. d
17. a 51. d 85. d 119. a 153. b 187. b
18. a 52. a 86. d 120. a 154. c 188. b
19. a 53. b 87. a 121. b 155. c 189. a
20. d 54. a 88. b 122. b 156. a 190. a
21. c 55. b 89. c 123. c 157. b 191. c
22. a 56. a 90. b 124. c 158. c 192. b
23. c 57. c 91. b 125. d 159. d 193. d
24. d 58. a 92. d 126. b 160. c 194. a
25. b 59. b 93. d 127. a 161. b 195. c
26. d 60. b 94. b 128. d 162. c
27. d 61. d 95. b 129. d 163. d
28. a 62. c 96. c 130. a 164. c
29. c 63. c 97. a 131. b 165. a
30. b 64. c 98. d 132. b 166. c
31. a 65. b 99. b 133. a 167. c
32. b 66. d 100. a 134. a 168. b
33. a 67. a 101. b 135. a 169. b
34. d 68. a 102. c 136. b 170. b

205
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

CHAPTER-7
FEEDBACK AMPLIFIER
01. The feedback amplifier shown in Fig. has : (a) improves the signal to noise ratio at the
(GATE (EC) - 1989) i/p.
(b) improves the signal to noise ratio at the
o/p.
(c) does not effect the signal to noise ratio at
the o/p.
(d) Reduces distortion

04. To obtain very high input and output impedance


in a feedback Amplifier, the mostly used is
(GATE (EC) - 1995)
(a) Voltage - series (b) Current - series
(a) current - series feedback with large input (c) Voltage - shunt (d) Current - shunt
impedance and large output impedance.
(b) voltage - series feedback with large input
05. In the circuit shown in Figure N is a finite gain
impedance and low output impedance.
amplifier with a gain of k, a very large input
(c) voltage - shunt feedback with low input impedence, and a very low output impedance.
impedance and low output impedance. The input impedance of the feedback amplifier
(d) current - shunt feedback with low input with the feedback impedance Z connected as
impedance and output impedance. shown will be
(GATE (EC) - 1996)
02. Two non-inverting amplifiers, one having a unity
gain and the other having a gain of twenty, are
made using identical operational amplifiers. As
compared to the unity gain amplifier, the
amplifier with gain twenty has
(GATE (EC) - 1991)
(a) less negative feedback
(b) greater input impedance
 1
(c) less bandwidth (a) Z  1   (b) Z (1 – k)
 k
(d) none of the above
Z Z
(c) (d)
 k  1 1  k 
03. Negative feed back in Amplifiers.
(GATE (EC) - 1993)
206
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

06. Negative feed back in


(GATE (EC) - 1997)
1. Voltage series configuration
2. current shunt configuration
A. increases input impedance
B. decreases input impedance (a) current series (b) current shunt
C. increases closed loop gain (c) voltage series (d) voltage shunt
D. leads to oscillation
Codes: 09. In a shunt-shunt negative feedback Amplifier,
1 2 as compared to the basic Amplifier.

(a) A B (GATE (EC) - 1998)

(b) B A (a) both input and output impedance


decreases
(c) A A
(b) input impedance decreases but output
(d) B B impedance increases
(c) input impedance increases but output
07. The voltage series feedback in a feedback impedance decreases
amplifier leads to (d) both input and output impedance
(GATE (EE) - 1997) increases
(a) increase in band width, while the voltage
gain becomes less sensitive to variations 10. Negative feedback in an amplifier
in components and device characteristics
(GATE (EC) - 1999)
(b) decrease in overall gain, while the input
resistance decreases (a) Reduces gain

(c) increase in distortion, while the output (b) Increase frequency and phase distortions
resistance decreases (c) Reduces bandwidth
(d) decrease in input resistance, while the (d) Increases Noise
output resistance increases

11. Negative feedback in an amplifier


08. The circuit of the figure is an example of (GATE (EC) - 1999)
feedback of the following type
(a) reduces gain
(GATE (EC) - 1998)
(b) increases frequency and phase distortions
(c) reduces bandwidth
(d) increases noise

207
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

12. An amplifier has an open-loop gain of 100, an 15. An amplifier without feedback has a voltage
input impedance of 1, and an output gain of 50, input resistance of 1K and output
impedance of 100 . A feedback network with
resistance of 2.5 K . The input resistance of
a feedback factor of 0.99 is connected to the
amplifier in a voltage series feedback mode. the current-shunt negative feedback amplifier
The new input and output impedances, using the above amplifier with a feedback factor
respectively, are of 0.2 is

(GATE (EC) - 1999) (IES (EC) - 2013) (GATE (EC) - 2003)

(a) 10  and 1 (a) 1/11 K (b) 1/5 K

(b) 10  and 10  (c) 5 K (d) 11 K

(c) 100 K and 1


16. Three identical amplifiers with each one having
(d) 100 K and 1K a voltage gain of 50, input resistance of 1 K
and output resistance of 250  , are cascaded.
13. An amplifer with resistance negative feedback The open circuit voltage gain of the combined
has two left half plane poles in its open-loop amplifier is
transfer function. The amplifier
(GATE (EC) - 2003)
(GATE (EC) - 2000), (IES (EC) - 2013)
(a) 49 dB (b) 51 dB
(a) will always be unstable at high frequencies
(c) 98 dB (d) 102 dB
(b) will be stable for all frequencies
(c) may be unstable, depending on the
feedback factor 17. Voltage series feedback (also called series-
shunt feedback) results in
(d) will oscillate at low frequencies
(GATE (EC) - 2004)
(a) increase in both input and output
14. In a negative feedback amplifier using voltage- impedances
series (i.e. voltage-sampling, series mixing)
feedback. (b) decrease in both input and output
impedances
(GATE (EC) - 2002)
(c) increase in input impedance and decrease
(a) Ri decreases and R0 decreases in output impedance
(b) Ri decreases and R0 increases (d) decrease in input impedance and increase
(c) Ri increases and R0 decreases in output impedance
(d) Ri increases and R0 increases
(Ri and R 0 denote the input and output 18. The feedback used in the circuit shown in figure
resistances respectively) can be classified as
(GATE (EE) - 2004) (1M)

208
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) a large input resistance and a large output


VCC
resistance
RC (b) a large input resistance and a small output
C=x
RF resistance
C=x
Rl
(c) a small input resistance and a large output
resistance
(d) a small input resistance and a small output
Rs RB
resistance
RE
C=x

22. The amplifier circuit shown below uses a silicon


transistor. The capacitors CC and CE can be
(a) Shunt - series feedback assumed to be short at signal frequency and
the effect of output resistance r0 can be ignored.
(b) Shunt- shunt feedback If CE is disconnected from the circuit, which
(c) Series - shunt feedback one of the following statements is TRUE?
(d) Series- series feedback (GATE (EC) - 2010)
VCC=9V

19. The effect of current shunt feedback in an


amplifier is to
RB=800k RC=2.7k
(GATE (EC) - 2005) (IES (EE) - 2013) CC
V0
CC
(a) increase the input resistance and decrease =100
V1
the output resistance
(b) increase both input and output resistance VS ~
CE
RE=0.3k
(c) decrease both input and output resistances Rl
R0

(d) decrease the input resistance and increase


the output resistance
(a) The input resistance Ri increases and the
magnitude of voltage gain AVdecreases
20. The input impedance (Zi) and the output (b) The input resistance Ridecreases and the
impedance (Z0) of an ideal transconductance magnitude of voltage gain AVincreases
(voltage controlled current source) amplifier are
(c) Both input resistance Ri and the magnitude
(GATE (EC) - 2006) of voltage gain AV decrease
(a) Zi  0, Z0  0 (b) Zi  0, Z0   (d) Both input resistance Ri and the magnitude
of voltage gain AV increase
(c) Zi  , Z0  0 (d) Zi  , Z 0  
23. In a voltage-voltage feedback as shown below,
21. In a transconductance amplifier, it is desirable which one of the following statements is TRUE
to have if the gain k is increased ?
(GATE (EC) - 2007) (GATE (EC) - 2013)
209
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

26. The input resistance Ri and output resistance R0


of an ideal current amplifier, in ohms, are
(IES (EE) - 2010)
(a) 0 and 0 (b) 0 and 
(c)  and 0 (d)  and 

27. The open - loop voltage gain of an amplifier is


240. The noise level in the output without
feedback is 100mV. if a negative feedback with
(a) The input impedance increases and output   1 / 60 is used. the noise level in the ouput
impedance decreases will be
(b) The input impedance increases and output (IES (EE) - 2003)
impedance also increases (a) 1.66 mV (b) 2.4 mV
(c) The input impedance decreases and output (c) 4.0 mV (d) 20 mV
impedance also decreases
(d) The input impedance decreases and output
28. An amplifier without feedback has a gain of 1000
impedance increases
what is the gain with a negative feedbak of 0.009?
(IES (EE) - 2007)
24. An amplifier with mid-band gain |A| = 500 has
(a) 900 (b) 125
1
negative feedback   . If the upper cut- (c) 100 (d) 10
100
off without feedback were at 60 kHz,then with
feedback it would become 29. Consider the following statements :
(IES (EE) - 1997) In order to increase the bandwidth of tuned
(a) 10 kHz (b) 12 kHz amplifiers, one can use
(c) 300 kHz (d) 360 kHz 1. tuned circuit with inductance having high
Q factor.
2. double-tuned amplifier with two tuned
25. Negative feedback in an amplifier leads to which circuits coupled by mutual inductance
one of the following?
3. staggered tuned amplifier in which different
(IES (EE) - 2007) tuned circuits which are cascaded are
(a) Decrease in bandwidth tuned to slightly different frequencies.
(b) Increase in current gain Of these statements
(c) Increase in voltage gain (IES (EC) - 1997, 2013)
(d) Decrease in voltage gain (a) 1 alone is correct
(b) 1 and 3 are correct

210
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(c) 2 and 3 are correct (a) is greater than that for critical coupling and
(d) 1, 2 and 3 are correct the amplifier characteristic is double
peaked
(b) is less than that for critical coupling and
30. In the shunt series feedback amplifier, the basic the amplifier characteristic has a single
amplifier and the feedback network are parallel peak
connected at the input and series connected at
the output. The signal sampled and the summing (c) is same as that for critical coupling and
down will be respectively the amplifier characteristic is double
peaked
(IES (EE) - 1999)
(d) is less than that for critical coupling and
(a) current and current the amplifier characteristic is doubled
(b) current and voltage peaked
(c) voltage and current
(d) voltage and voltage 33. A tuned amplifier has a voltage gain of 100 and
a bandwidth of 10 kHz. It is required to
increase the bandwidth to 20 kHz. This can be
31. A transistor amplifier has a voltage gain of 50, achieved by which one of the following ways ?
input resistance of 1k and output resistance (IES (EC) - 2004)
of 40 k . The amplifier is now provided 10% (a) By doubling the gain
negative voltage feedback in series with the
(b) By doubling the resonant frequency
input. With feedback, the voltage gain, input
resistance and output resistance will be (c) By halving the Q of the coil
respectively (d) By halving the power supply voltage
(IES (EE) - 1999)
(a) 8.7 k and 3 k 34. For the amplifier shown in the figure given
below, the lower cut-off frequency depends on
(b) 8.33, 6 k and 6.66 k
which of the following ?
(c) 5.33, 8.33 k and 8.66 k (IES (EC) - 2007)
(d) 6.66, 8.86 k and 6.66 k

32. Which one of the following statements is


correct?
If in a double-tuned voltage amplifier, the
mutually coupled secondary and primary are
synchronously tuned with equal Q-values then
for the over-coupled case the maximum voltage
amplification.
(IES (EC) - 2004)

211
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) CS, CE, internal junction capacitances of (d) 100 kHz, 6.05 MHz and 5.95 MHz
transistor
(b) Strong wiring capacitance (CW), CC 38. The given circuit has a feedback factor of
(c) CS, CE, CC (IES (EC) - 1999)
(d) CS, CE only

35. A tuned amplifier has peak output at 2MHz


and quality factor 50. The bandwidth and
3-dB frequencies shall be at what values
respectively ?
(IES (EC) - 2007)
(a) 40 kHz, 2.02 MHz, 1.98 MHz
(b) 40 kHz, 2.04 MHz, 1.96 MHz (a) –RC / RS (b) –RE / RC
(c) 80 kHz, 2.04 MHz, 1.96 MHz (c) –RE / RS (d) –RC / RE
(d) 80 kHz, 2.08 MHz, 1.92 MHz
39. The voltage gain of an amplifier without
feedback and with negative feedback
36. Consider the following statements:
respectively are 100 and 20. The percentage
Tuned amplifier of negative feedback (  ) would be
1. are wide band amplifier (IES (EC) - 2000)
2. are used in radio transmitters and receivers (a) 4% (b) 5%
3. performance is determined by Q of the (c) 20% (d) 80%
circuit
Which of the statements given above are
40. The feedback amplifier shown in the figure
correct?
below
(IES (EC) - 2008)
(IES (EC) - 2002)
(a) 1 and 2 only (b) 2 and 3 only
(c) 1 and 3 only (d) 1, 2 and 3

37. The peak output of a tuned amplifier is at


6 MHz and has quality factor of 60. The
bandwidth and 3 dB frequencies shall be
(IES (EC) - 2011) (a) is stable for all values of R and C
(a) 100 MHz, 6.05 MHz and 5.95 MHz (b) is stable only for R1 R2 = R3
(b) 6 MHz, 9 MHz and 3 MHz (c) is stable only for R1 C = R2 R3
(c) 600 kHz, 6.6 MHz and 5.4 MHz (d) is stable for R1 / R2 = C/R3
212
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

41. Consider the following amplifier with negative (a) If the signal sampled is a voltage
feedback: (b) If the signal sampled is a current
(IES (EC) - 2002) (c) If the feedback signal is a voltage
(d) If the feedback signal is a current

45. A feed back amplifier has an open-loop gain


of –100. If 4% of the output is fed back in a
degenerative loop, what is the closed loop gain
of the amplifier ?
(IES (EC) - 2008)
(a) –33.3 (b) –25
If the closed-loop gain of the above amplifier
is + 100, the value of β will be (c) –20 (d) +25

(a) –9 × 10–3 (b) +9 × 10–3


(c) –11 × 10–3 (d) +11 × 10–3 46. Match List-I (type of Feedback) with List-II
(Effect on Rin and Rout) and select the correct
answer using the codes given below the lists
42. In a BJT amplifier with the introduction of (IES (EC) - 2008)
feedback, the input impedance is reduced,
output impedance is increased, bandwidth is List-I
increased and distortion is reduced. The A. Voltage series
feedback is
B. Voltage Shunt
(IES (EC) - 2003)
C. Current Series
(a) Voltage series (b) Current series D. Current shunt
(c) Voltage shunt (d) Current shunt List-II
1. Rin increases and Rout decreases
43. An amplifier has an open loop gain of
2. Rin and Rout decrease
1000 +10. Negative feedback is provided such
that the gain variation remains within 0.1%. What 3. Rin and Rout increase
is the amount of feedback β F ? 4. Rin decreases and Rout increases

(IES (EC) - 2006) Codes:

(a) 1/10 (b) 1/9 A B C D

(c) 9/100 (d) 9/1000 (a) 1 4 3 2


(b) 3 2 1 4

44. In a negative feedback amplifier, when is the (c) 3 4 1 2


input impedance increased ? (d) 1 2 3 4
(IES (EC) - 2007)

213
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

47. The amplifier has gain A = 100  180°, upper (a) Current series feedback
cut off frequency of 100 kHz and lower cut off (b) Voltage series feedback
frequency of 1 kHz. A negative feedback of
(c) Current shunt feedback
β = 0.1 is added. Which one of the following
is not correct ? (d) Voltage shunt feedback

(IES (EC) - 2008)


(a) Gain becomes 100/11 51. The amplifier circuit shown in the figure is an
example of
(b) Lower cut off frequency becomes
(100/11) kHz (IES (EC) - 2011)

(c) Upper cut off frequency becomes


1.1 MHz
(d) dB of feedback is 20 log10 11

48. A negative-feedback closed-loop system is


supplied to an input of 5V. The system has a
forward gain of 1 and a feedback gain of 1.
What is the output voltage ?
(IES (EC) - 2009)
(a) voltage series feedback
(a) 1.0 V (b) 1.5 V
(b) voltage shunt feedback
(c) 2.0 V (d) 2.5 V
(c) current series feedback
(d) current shunt feedback
49. Consider the following
1. Oscillator
52. The second-harmonic component in the output
2. Emitter follower
of a transistor amplifier, without feedback, is
3. Cascaded amplifier B2. The second harmonic component, with
4. Power amplifier negative feedback B2, is equal to (where A =
Amplifier gain and β = feedback factor).
Which of these use feedback amplifiers ?
(IES (EC) - 2011)
(IES (EC) - 2009)
(a) 1 and 2 (b) 1 and 3 B2
(a) (b) B2 1  Aβ 
(c) 2 and 4 (d) 3 and 4 1  Aβ

B2 B2
50. Which one of the following type of negative (c) (d)
β Aβ
feedback increases the input resistance and
decreases the output resistance of an amplifier?
(IES (EC) - 2009)

214
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

53. The voltage gain of an amplifier is 100A ANSWER KEY


negative feedback is applied with β = 0.03. The
overall gain of the amplifier is
01. b,c 29. c
(IES (EC) - 2013)
02. c 30. b
(a) 70 (b) 25
03. d 31. b
(c) 99.97 (d) 3
04. b 32. d
05. d 33. c
54. If an amplifier with gain of – 1000 and feed
back of b = – 0.1 had a gain change of 20% 06. a 34. c
due to temperature , the change in gain of the 07. a 35. a
feedback amplifier would be
08. d 36. b
(IES (EC) - 1997)
09. a 37. d
(a) 10% (b) 5% 10. a 38. d
(c) 0.2% (d) 0.01% 11. a 39. a
12. c 40. a
55. A feedback amplifier is designed with an 13. b 41. b
amplifier gain of – 1000 and feedback of
β = – 0.1. If the amplifier had a gain change of 14. c 42. d
20% due to temperature, the change in gain of 15. a 43. d
the feedback amplifier is 16. c 44. c
(IES (EE) - 2013) 17. c 45. c
(a) 10% (b) 5% 18. b 46. d
(c) 0.2% (d) 0.01% 19. c 47. d
20. d 48. d
21. a 49. a
22. a 50. b
23. a 51. b
24. d 52. a
25. d 53. b
26. b 54. c
27. d 55. c
28. c

215
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

CONVENTIONAL PROBLEMS of 4 MHz. The midband gain reduces to 150


when a negative feedback is applied. Determine
01. An Amplifier has an open-loop gain of 100 and
the value of feedback factor and the bandwidth
its lower and upper-cut-off frequency of
100 Hz and 100 KHz respectively, a feedback (IES (EE) - 1998)
network with a feedback factor of 0.99 is
connected to the amplifier. The new lower-and
upper-cut-off frequencys are at .......
(GATE (EC) - 1995)

02. For a feedback amplifier, the open loop transfer


function has three poles at 100 k rad/s,
1M rad/s and 10M rad/s. The low frequency
open loop gain is 1000 and the feedback factor
(  ) is 1. Use Bode plots to determine the
phase margin of the amplifier. Is the amplifier
stable ?
(GATE (EC) - 2000)

03. For the feedback amplifier shown


(i) draw the circuit without feedback but
taking the loading of feedback network
into account.
(ii) find the feedback factor β .
(iii) assuming loop gain to be much larger than
unity, find the voltage gain with feedback.
(IES (EC) - 1997)

04. Derive an expression for the overall gain of a


voltage series feedback amplifier. An amplifier
has the midband gain of 1500 and a bandwidth

216
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

CHAPTER-8
MULTI-STAGE AMPLIFIER
01. The configuration of cascode amplifier is : (d) A common base stage followed by a
(GATE (EC) - 1987) common Emitter stage

(a) CE - CE (b) CE - CB
(c) CC - CB (d) CC - CC 05. A multistage Amplifier has a low-pass
Response with three Real poles at
s  ω1  ω2 and ω3 .The approximate overall
02. The Bandwidth of an n-stage tuned Amplifier, bandwidth B of the Amplifier will be given by
with each stage having a bandwidth of B, is
given by (GATE (EC) - 1998)

(GATE (EC) - 1993) (a) B  1  2  3

B B 1 1 1 1
(a) (b)
n n (b) B      
1 2 3

1 B (c) B   1  2  3 
1/3
(c) B 2n 1 (d) 1
n
2 1
(d) B  12  22  33

03. In a multi-stage RC-Coupled Amplifier the


coupling capacitor. 06. An amplifier is assumed to have a single-pole high-
frequency transfer function. The rise time of its
(GATE (EC) - 1993)
output response to a step function input is 35 nsec.
(a) limits the low frequency response The upper -3 dB frequency (in MHz) for the
(b) limits the high frequency response amplifier to a sinusoidal inputs approximately
at
(c) Does not effect the frequency response
(GATE (EC) - 1999)
(d) blocks the dc components without
effecting the frequency response. (a) 4.55 (b) 10
(c) 20 (d) 28.6
04. A cascode Amplifier stage is equivalent to
(GATE (EC) - 1997) 07. Three identical RC - Coupled transistor
amplifiers are cascaded. If each of the
(a) A common emitter stage followed by a amplifiers has a frequency response as shown
common base stage in the figure, the overall frequency response is
(b) A common base stage followed by an as
Emitter follower (GATE (EC) - 2002)
(c) An Emitter follower stage followed by a
common base stage
217
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

09. If the amplification of a single stage is not


sufficient or the input or output impedance is
not of the correct magnitude for the intended
application. How may two stages be connected
to achieve desired result?
(IES (EE) - 2009)
(a) Cascode connection
(b) Complementary symmetry connection
(c) Cascade connection
(d) Totem pole connection
(a)

10. Consider the following statements :


When Darlington circuit and normal single stage
emitter followers are compared
1. Both have near unity voltage gain.
2. Both have equal current gain.
(b)
3. Darlington circuit has higher output
resistance.
4. Emitter follower has lower-input
resistance
Which of these statements is/are correct?
(IES (EE) - 2010)
(c)
(a) 1 only (b) l and 4 only
(c) 2 and 4 only (d) 1, 2, 3 and 4

11. In an RC coupled amplifier, the gain decreases


in the frequency response due to the
(IES (EE) - 2001)
(d)
(a) coupling capacitor at low frequency and
bypass capacitor at high frequency
(b) coupling capacitor at high frequency and
08. The cascode amplifier is a multistage bypass capacitor at low frequency
configuration of (c) coupling junction capacitance at low
(GATE (EC) - 2005) frequency and coupling capacitor at high
frequency
(a) CC-CB (b) CE-CB
(d) device junction capacitor at high frequency
(c) CB-CC (d) CE-CC and coupling capacitor at low frequency
218
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

12. The Darlington pair has a current gain of f1


approximately β 2 , the voltage gain AV, the input (a) (b) f l 2 1
2 1
resistance Ri and the output resitance R0. When
the Darlington pair is used in the emitter- (c) fl / 2 (d) 2f l
follower configuration, AV, Ri and R0 are
respectively
(IES (EE) - 2001) 16. If the coupling capacitors of a CE transistor,
amplifier is shorted, which one of the following
(a) very large, very large and very small graphs will represent the frequency response
(b) unity, very large and very small curve of the amplifier? (AV = voltage gain,
(c) unity, very small and very large f = frequency in Hertz, Amax = maximum value
of AV)
(d) very large, very small and very large
(IES (EE) - 2004)

13. The Darlington pair is mainly used for


(IES (EE) - 2002) A Max
Av
(a) impedance matching
(b) wideband voltage amplification
(c) power amplification (a)

(d) reducing distortion

14. Two identical RC coupled amplifiers, each


having an upper cut-off frequency fu, are f
l

cascaded with negligible loading. What is the


upper cut-off frequency of the overall amplifier?
(IES (EE) - 2004)

fu A Max
(a) (b) f u 2 1 Av
2 1
(b)
(c) fu / 2 (d) 2f u

15. Two identical RC coupled amplifiers, each


having a lower cut-off frequency fl, are
cascaded with negligible loading. What is the
lower cut-off frequency of the overall amplifier?
(IES (EE) - 2004)
f
l

219
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

3. lower cut-off frequency is 21/ n  1 times


that of a single stage
A Max
Av 4. upper cut-off frequency is 21/ n  1 times
that of a single stage
(c)
Which of these statements are correct?
(IES (EE) - 2006)
(a) 1 and 2 (b) 1and 3
(c) 2 and 4 (d) 3 and 4
f
l

19. What is the transistor combination shown in the


figure given below?

Av
A Max +VCC

(d)

f
l

17. In a single stage RC-coupled amplifier stage,


what are the phase shifts introduced at lower
and upper 3-dBfrequencies, respectively?
(IES (EE) - 2005)
(IES (EE) - 2008)
(a) 45o , 225o (b) 45°,135°
(a) A Darlington pair
(c) 90°, 180° (d) 45°, 180 o
(b) complementary pair
(c) It effectively acts as a single p-n-p
18. Consider the following statements: transistor

In frequency response of n-stage amplifiers (d) It effectively acts as a single n-p-n


transistor
1. upper cut-off frequency is 21/ n  1 times
that of a single stage
20. What is the effect of cascading the amplifier
2. lower cut-off frequency is 21/ n  1 times stages?
that of a single stage (IES (EE) - 2008)

220
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) To increase the voltage gain and increase 23. The overall bandwidth of two identical voltage
the bandwidth amplifies connected in cascade will
(b) To increase the voltage gain and reduce (IES (EE) - 1998)
the bandwidth (a) remain the same as that of a single stage
(c) To decrease the voltage gain and increase (b) be worse than that of a single stage
the bandwidth
(c) be better than that of single stage
(d) To decrease the voltage gain and reduce
the bandwidth (d) be better if stage gain is low and worse if
stage gain is high

21. The typical frequency response of a two -stage


directed coupled voltage amplifier is as shown 24. What is the purpose of impedance matching
in between the output of previous stage and input
of next stage in a cascaded amplifier?
(IES (EE) - 2006)
(a) Gain
(a) To achieve high efficiency
Frequency
(b) To achieve maximum power transfer
(c) To achieve reduced distortion
(b) Gain (d) To achieve reduced noise

Frequency

25. Match List-I with List-II and select the correct


answer using the codes given below the lists:
(c) Gain
(IES (EC) - 1996)
Frequency List-I
(Amplifier type)
A. RC coupling
(d) Gain

B. Inductive coupling
Frequency
C. Transformer coupling
D. Direct coupling
22. A transformer coupled amplifier would give List-II
(IES (EE) - 1998) (Circuit/property)
(a) maximum voltage gain 1. Higher voltage gain and impedance
(b) impedance matching matching
(c) maximum current gain 2. Ability to amplify dc and low frequency
signals
(d) larger bandwidth
3. Minimum possible non-linear distortion

221
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

4. Low collector supply voltages can be used equivalent upper cut-off frequency of the
Codes cascaded amplifier would be

A B C D (IES (EE) - 2000)

(a) 4 1 3 2 (a) 4.16 MHz (b) 3.33 MHz

(b) 3 4 1 2 (c) 2 MHz (d) 5 MHz

(c) 1 2 3 4
(d) 4 3 2 1 28. An amplifier using BJT has two identical stages
each having a lower cut-off (3 dB) frequency
of 64Hz due to coupling capacitor. The emitter
26. Match List -I (Circuit ) with List-II bypass capacitor also provides a lower cut-off
(Characteristic) and select the correct answer (3 dB) frequency due to emitter degeneration
using the codes given below the Lists : alone of 64 Hz. The lower (3 dB) frequency of
the overall amplifier is nearly
(IES (EC) - 1997)
(IES (EC) - 2000)
List-I
(a) 100 Hz (b) 128 Hz
A. RC-coupled amplifier
(c) 156 Hz (d) 244 Hz
B. Tuned amplifier
C. Chopper stablized amplifier
29. An RC amplifier stage has a bandwidth of
D. Direct coupled amplifer 500 kHz. What will be the rise time of this
List-II amplifer stage ?
1. Very low drift (IES (EC) - 2002)
2. Flat frequency response from zero (a) 0.35 μs (b) 0.7 μs
frequency on wards
(c) 1.0 μs (d) 2.0 μs
3. Flat frequency response with an upper and
a lower cut-off frequency
30. Consider the following statements in respect
4. Peak in gain frequency response
of a transistor R-C coupled amplifer
Codes
1. The low frequency response is determined
A B C D by the transistor junction capacitors.
(a) 4 3 1 2 2. The high frequency response is limited by
(b) 3 4 2 1 coupling capacitors.
(c) 3 4 1 2 3. The miller capacitance reduces the gain
at high frequencies.
(d) 4 3 2 1
4. As the gain is increased the bandwidth gets
reduced.
27. The upper cut-off frequencies f 21 and f22 of the Which of these statements are correct ?
two stages of a cascaded amplifier are
respectively 5 MHz and 4.4 MHz. The (IES (EC) - 2003)

222
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) 1 and 2 (b) 2 and 3 (IES (EC) - 2006)


(c) 3 and 4 (d) 1 and 4 (a) 4.15 MHz (b) 3.33 MHz
(c) 2.5 MHz (d) 5.00 MHz
31. An amplifier has two identical cascaded stages.
Each stage has a bandwidth of 20 kHz. The 35. Cascode amplifiers when compared with a
overall bandwidth shall approximately be equal simple common-emitter amplifier provide which
to of the following ?
(IES (EC) - 2003) (IES (EC) - 2007)
(a) 10 kHz (b) 12.9 kHz (a) Higher voltage gain and same bandwidth
(c) 20 kHz (d) 28.3 kHz (b) Same voltage gain but higher bandwidth
(c) No change in either voltage gain or
32. A transistor RC coupled amplifier is designed bandwidth.
for a voltage and band gain of 20. But a (d) Voltage gain less than one but bandwidth
measurement at a particular frequency shows equal to fT
the gain to be only 14. What is the likely phase
shift at this frequency ?
(IES (EC) - 2005) 36. Which of the following components control the
high frequency response of the R-C coupled
(a) 180° (b) 135° amplifier ?
(c) 90° (d) 45° 1. Parasitic capacitances of the transistor
2. Coupling capacitance
33. A cascaded amplifier comprises N identical 3. Stray capacitances
non-interacting stages, each having a lower
3 dB frequency of fL. If fL* is the lower 3 dB 4. Wiring capacitance
frequency of the cascaded amplifier, then which Select the correct answer using the codes given
one of the following is correct ? below:
(IES (EC) - 2005) (IES (EC) - 2008)
(a) fL* = fL (a) 1 and 2 only (b) 2 and 3 only
(b) fL* = fL 21/ N  1 (c) 3 and 4 only (d) 1, 3 and 4

(c) fL* = fL / 21/ N  1


37. Consider the following :
(d) fL* = fL / N
1. Coupling capacitor
2. Emitter bypass capacitor
34. The two stages of a cascade amplifier have
3. Emitter to base diffusion capacitance of
individual upper cut-off frequencies f1 = 5 MHz
the BJT
and f2 = 3.33 MHz. What is the best
approximation for the upper cut-off frequency 4. Stray capacitance of the circuit.
of the cascade combination ?
223
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Which of these components in a R-C coupled 41. Low frequency response of RC coupled
amplifier control the lower cut-off frequency amplifier can be improved by
of the amplifer ?
(IES (EC) - 2013)
(IES (EC) - 2009)
(a) increasing the value of the coupling
(a) 1 and 2 (b) 2 and 3 capacitor only
(c) 3 and 4 (d) 1 and 4 (b) increasing the values of the bypass
capacitor and coupling capacitor

38. In an RC coupled transistor amplifier (c) increasing the value of bypass capacitor
only
1. Low-frequency response is determined by
coupling capacitors (d) decreasing the value of the coupling
capacitor
2. High-frequency response is determined by
junction capacitance
3. Mid-frequency response is determined by 42. Three identical amplifiers, each having a gain
both coupling and junction capacitances. A0
of  600 are connected in cascade. The
(IES (EC) - 2011) 2
positive feedback loop has a gain of 0.008.
(a) 1 and 2 only (b) 1 and 3 only
The values of A0 that will render the cascaded
(c) 2 and 3 only (d) 1, 2 and 3 system oscillatory is
(IES (EE) - 2012)
39. The lower 3dB frequency of an n-stage amplifier (a) 10 (b) –10
with non-interacting stages is given by
(c) 250/3 (d) 250
(IES (EC) - 2012)

fL 43. A signal may have frequency components which


(a) (b) f L  21/ n  1 
21/ n
1   lie in the range of 0.001 Hz to 10 Hz. Which
one of the following types of couplings should
fL be chosen in a multistage amplifier designed to
(c) (d) f L  21/ n  n  amplify the signal.
21/ n
n  
(IES (EE) - 2013)
Where fL is the 3 dB frequency of a single stage.
(a) RC coupling
(b) Direct coupling
40. When two identical stages with upper cut-off
(c) Transformer coupling
frequency ωH are cascaded, overall cut-off
frequency is at (d) Double tuned transformer
(IES (EC) - 2013)

(a) 1 ωH (b) 2 ωH

(c) 0.5 ωH (d) 0.64 ωH

224
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Conventional Problems ANSWER KEY


01. An RC-Coupled Amplifer is assumed to have
a single-pole low frequency transfer function. 01. b 23. b
The maximum lower-cutoff frequency allowed 02. a 24. d
for the Amplifier to pass 50 Hz. Square wave
with no more than 10% tilt is ___. 03. a 25. b
(GATE (EC) - 1995) 04. c 26. c
05. a 27. c
02. In the cascade Amplifier circuit shown below, 06. b 28. a
determine the values of R1, R2 and RL Such that
07. a 29. b
the quiescent current through the transistors is 1mA
and the collector voltage Vc1 = 3V, and Vc2 = 6V. 08. b 30. c
Take VBE = 0.7 V. Transistor β to be high and
09. c 31. b
base currents to be negligible
10. b 32. b
11. d 33. c
12. b 34. c
13. a 35. b
14. b 36. d
15. a 37. a
16. b 38. a
17. a 39. a
18. b 40. d
19. b 41. b
20. b 42. a
(GATE (EC) - 1997)
21. b 43. b
22. c

225
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

CHAPTER-9
POWER AMPLIFIER

01. In case of class A amplifiers the ratio (efficiency


of transformer coupled amplifier) / (efficiency A 22  A32  .....
(c)
of a transformer less amplifier) is : A12  A 22  A 32 .....
(GATE (EC) - 1987)
(a) 2.9 (b) 1.36 A 2
2  A32  .....
(d)
(c) 1.0 (d) 0.5 A1

02. In a transistor push-pull Amplifier 05. Crossover distortion behaviour is characteristic


of
(GATE (EC) - 1993)
(GATE (EC) - 1999)
(a) there is no d.c. present in the o/p
(a) Class A output stage
(b) there is no distortion in the o/p
(b) Class B output stage
(c) there is no even harmonics in the o/p
(c) Class AB output stage
(d) there is no odd harmonics in the o/p
(d) Common-base output stage

03. A Class-A transformer coupled, transistor


power Amplifier is required to deliver a power 06. The type of power amplifier which exhibits
output of 10 watts. The maximum power Rating crossover distortion in its output is
of the transistor should not be less than (GATE (EE) - 2000)
(GATE (EC) - 1994) (a) Class A (b) Class B
(a) 5 W (b) 10 W (c) Class AB (d) Class C
(c) 20 W (d) 40 W

07. Consider the following statements: -


04. A distorted sinusoid has the Amplifier, A1, A2, 1. Only even harmonics are present in the
A3, ...... of the fundamental, second harmonic, output
third harmonic, ...... respectively. The total
harmonic distortion is 2. Provides more output per device for a
given amount of distortion.
(GATE (EC) - 1998)
3. Core saturation of transformer is avoided.
A 2  A 3  ...... 4. Power supply hum is absent in the output.
(a) A1
Which of the above statements is/are correct
for a push-pull amplifier?

(b)
 A 22  A 32  .....  (IES (EE) - 2009)
A1

226
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) 1 only (b) l and 2 only C. Class C


(c) 1, 2 and 3 (c) 2, 3 and 4 D. Class D
List - II
08. What is the main source of distortion in a push- 1. Clips off half a cycle
pull amplifier? 2. Leads to most stable biasing circuit
(IES (EE) - 2009) 3. Transistor acts as switch
(a) Fundamental component 4 Amplification of the resonant frequency
(b) Second harmonic only
(c) third harmonic Codes:
(d) All even harmonics A B C D
(a) 1 2 3 4
(b) 2 1 4 3
09. The efficiency of a class B amplifier is 72% (c) 1 2 4 3
when the supply voltage is 24 V. The peak to
peak output-voltage is (d) 2 1 3 4

(IES (EE) - 2010)


(a) 20V (b) 22V 12. Which one of the following statements is
correct?
(c) 25V (d) 16V
The efficiency of class B push-pull amplifiers is
much higher than that of class A amplifiers
10. High power efficiency of the push-pull amplifier primarily because
is due to the fact that ? (IES (EE) - 2004)
(IES (EE) - 2001) (a) the distortion is kept within acceptable
(a) each transistor conducts on different cycle limits
of the input (b) one half of the input signal is amplified using
(b) transistors are placed in CE configuration one transistor and the other half is phase-
inverted and fed to the other transistor
(c) there is no quiescent collector current
(c) matched pair transistors are used in class
(d) low forward biasing voltage is required B push-pull operation
(d) the quiescent d.c. current is avoided
11. Match List - I (Amplifier’s mode of operation)
with List - II (Properties/characteristics) and
select the correct answer using the codes given 13. A transistorised transformer coupled class-A
below the lists: amplifier supplies 0.94 W to a 4 K load. The
(IES (EE) - 2002) zero signal dc-collector current is 31 mA, and
the dc collector current with signal is 34 mA.
List - I What is the percent-second-harmonic
A. Class A distortion?
B. Class B (IES (EE) - 2007)
227
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) ~ 50% 16. The dynamic transfer characteristics of a


(b) 0% transistor is represented by i C  A1i b  A 2 i 2b
(c) ~20% Where A1 and A2 are constants. If input signal
(d) Cannot be computed with the available i b  l1 cos 1 t  l2 cos 2 t the output will
information contain
(IES (EE) - 2005)
14. Which of the following characteristics are (a) ω1 , ω2 , 2ω1 , 2ω2
possessed by a transformer-coupled class B
push-pull power amplifier? (b) dc term, ω1 , ω2 , ω1 + ω2 , ω1 – ω2
(IES (EE) - 2007)
(c) dc term, ω1 , ω2 , 2ω1 , 2ω2 ,
1. It eliminates even harmonic distortion
2ω1 + 2ω2 , 2ω1 – 2ω2
2. It suffers from cross over distortion
3. Its device ratings are higher than those of (d) dc term, ω1 , ω2 , 2ω1 , 2ω2 ,
class-A power amplifier ω1 + ω2 , ω1 – ω2
4. Its collector circuit efficiency is more than
that of class-C power amplifier
17. A sinusoidal signal of 100 Hz is applied to an
Select the correct answer using the code given
amplifier. The output current is
below:
(a) 1, 3 and 4 (b) 2 and 4 i 0  20sin  628  t  2sin 1256t 
(c) 1 and 2 (d) 3 and 4 1sin  2512t 

What is the approximate percentage increase


15. Which of the following are the main advantages in power due to distortion?
of class-B push-pull power amplifier (using
(IES (EE) - 2008)
BJTs)?
(a) 1.15 (b) 25
1. Even harmonics tend to cancel out at the
output. (c) 1.30 (d) 1.50
2. More power output per transistor.
18. Match List-I with List-II and select the correct
3. Conversion efficiency can be as high as
answer using the codes given below the lists:
78%.
4. Absence of cross-over distortion. (IES (EC) - 1996)

Select the correct answer using the code given List-I


below: (Amplifier type)
(IES (EE) - 2007) A. Class A single ended
(a) 3, 2 and 3 (b) 1 , 2 and 4 B. Class B pushpull transformer coupled
(c) 1, 3 and 4 (d) 2, 3 and 4 C. Class AB push-pull
D. Class AB complenentary symmetry
228
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

List-II List-II
(Circuit/property) 1. Hi Fidelity
1. Requires PNP & NPN transistor pairs 2. Tuned amplifier
2. Prevents cross-over distortion 3. Power amplifier
3. Has maximum efficiency amongst these 4. Low distortion power amplifier
amplifiers Codes:
4. Has minimum efficiency amongst these A B C D
amplifiers
(a) 4 3 2 1
Codes:
(b) 1 2 3 4
A B C D
(c) 4 2 3 1
(a) 4 3 2 1
(d) 1 3 2 4
(b) 4 2 3 1
(c) 1 2 3 4
21. Consider the following statements:
(d) 3 2 1 4
in amplifiers,
1. a complementary symmetry amplifier has
19. Which one of the following is the advantage of 1 PNP and 1 NPN transistor
base modulation over collector modulation of
a transistor Class C amplifier ? 2. a boot strap incorporates emitter follower
3. the main function of transformer used in
(IES (EE) - 1997)
the output of a power amplifier is to
(a) Requires lower modulation power increase its voltage gain
(b) Higher power output per transistor 4. the harmonic distortion of the signal
(c) Better efficiency produced in a RC coupled tansistor
amplifier is due to transformer itself.
(d) Better linearity
Which of these statements are correct?
(a) 1, 2 and 3 (b) 2, 3 and 4
20. Match List-I with List-II and select the correct
answer using the codes given below the lists: (c) 1, 3 and 4 (d) 1, 2 and 4

(IES (EE) - 1998)


22. In the circuit shown in the given figure, the
List-I transistors Q 2 and Q 3 form a push-pull
A. Class A amplifier amplifier. Assuming that the input signal level is
large enough to drive both Q2 and Q3 to
B. Class B amplifier
L
C. Class C amplifier saturation and that the constant is large, the
R
D. Class AB amplifier waveform of the current ‘i’ can be represented
as
(IES (EC) - 1996)
229
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Of these statements
(IES (EC) - 1998)
(a) 2 and 3 are correct
(b) 1 alone is correct
(c) 2 alone is correct
(d) 1 and 2 are correct

25. The circuit of a class B push-pull amplifier is


(a) shown in the figure. If the peak output voltage
V0 is 16 V, the power drawn from the dc source
would be
(b) (IES (EE) - 1999)

(c)

(d)

(a) 10 W (b) 16 W
23. The dissipation at the collector is in the
quiescent state and increases with excitation in (c) 20 W (d) 32 W
the case of a
(IES (EC) - 1997) 26. In an amplifier, the power output is 2 W at 5kHz,
(a) Class A series-fed amplifier and 0.5 W at 50 Hz. If the input power is
constant at 10 mW, what is the variation
(b) Class A transistor coupled amplifier (approximate) of power gain in dB at two
(c) Class AB amplifier frequencies ? (log10 2 = 0.30)
(d) Class B amplifier (IES (EC) - 2007)
(a) 6 dB (b) 8 dB
24. Consider the following statements : (c) 3 dB (d) 16 dB
A class-B amplifier
1. Is biased just at cut-off 27. An amplifier has a power gain of 200. What is
its gain in dB ? (log10 2 = 0.30)
2. has a high theoretical efficiency of 78.5%
because its quiescent current is low (IES (EC) - 2007)
3. Is based at the mid-point of load time. (a) 14 dB (b) 17 dB
(c) 20 dB (d) 23 dB
230
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

28. If a class C power amplifier has an input signal 32. An amplifier has a d.c. power supply of 15V
with frequency of 200 kHz and the width of and draws a current of 10mA. It produces
collector current pulses of 0.1 μ s, then the duty resistance of 600  for a signal frequency of
cycle of the amplifier will be 1 kHz. What will be its a.c. power output ?
(IES (EC) - 1999) (IES (EC) - 2004)
(a) 1% (b) 2% (a) 260 mW (b) 20.8 mW
(c) 10% (d) 20%
(c) 520 mW (d) 40.6 mW

29. Consider the following statements :


33. Match List - I (Type of Amplifier) with
Sziklai pair List - II (Property) and select the correct
1. is also called complementary Darlington. answer using the codes given below the lists :
List - I
2. acts like a single p-n-p transistor with a
very high current gain A. Single ended class A
3. can be used in class B push-pull power B. Class AB push-pull
(IES (EC) - 2000) C. Class B push-pull
Which of these statements are correct ? D. Class C
(a) 1 and 2 (b) 1 and 3 List - II
(c) 2 and 3 (d) 1, 2 and 3 1. Medium efficiency with minimum
distortion

30. Which one of the following power amplifiers 2. High efficiency with crossover distortion
has the maximum efficiency ?
3. Harmonic generator with highest possible
(IES (EC) - 2000) conversion efficiency

(a) Class A (b) Class B 4. Poor conversion efficiency with minimum


distortion
(c) Class AB (d) Class C
(IES (EC) - 2005)

31. A class-B push-pull type amplifier with Codes :


transformer coupled load uses two transistors
A B C D
rated 10W each. What is the maximum power
output one can obtain at the load from this (a) 2 3 4 1
circuit?
(b) 4 1 2 3
(IES (EC) - 2002)
(c) 2 1 4 3
(a) 40 W (b) 50 W
(d) 4 3 2 1
(c) 60 W (d) 70 W
231
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

34. Where does the operating point of a class-B 2. The power output is low
power amplifier lie ?
3. Crossover distortion is present
(IES (EC) - 2006)
4. The standby power dissipation is absent
(a) At the middle of a.c. load line
Which of the above statements are correct ?
(b) Approximately at collector cut-off on both
(IES (EC) - 2009)
the d.c. and a.c. load lines
(a) 1, 2 and 3 (b) 1, 2 and 4
(c) Inside the collector cut-off region on
a.c. load line (b) 1, 3 and 4 (d) 2, 3 and 4
(d) At the middle point of d.c. load line

38. Consider the following:


35. In a class-B push-pull operation, the d.c. 1. Distortion
power drawn is 28 W. What is the power
delivered by the amplifier at the ideal maximum 2. Gain
efficiency of power conversion ? 3. Bias stabilization
(a) 28 W (b) 14 W 4. Sensitivity
(c) 22 W (d) 7 W 5. Frequency response
Which of these properties of the power amplifier
36. Which one of the following statements is not one should concentrate upon while designing a
correct with regard to power amplifiers ? good power amplifier circuit ?

(IES (EC) - 2009) (IES (EC) - 2009)

(a) The collector current is large (a) 1, 2 and 3 (b) 1, 3 and 5

(b) They are used as the front end of multistage (c) 2, 3 and 4 (d) 4 and 5
amplifiers
(c) They are used near the end of the 39. Using transistors:
multistage amplifiers
1. Class-A power amplifier has a minimum
 1  efficiency of 50%.
(d) They have a high power rating   W 
 2  2. Class-B push-pull power amplifier gives
rise to crossover distortion.
3. Class-AB push-pull power amplifier has
37. Consider the following statements regarding the
higher efficiency than Class-B push-pull
class B power amplifiers (Complementry
amplifier
symmetry type)
4. Class-C power amplifier is generally used
1. The efficiency of the amplifier is higher than
with tuned load for RF amplifications.
that of class-A amplifier
232
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Which of these statements are correct ? ANSWER KEY


(IES (EC) - 20011)
01. b 22. c
(a) 1, 2, 3 and 4 (b) 2 and 4 only
02. a,c 23. d
(c) 3 and 4 only (d) 1 and 2 only
03. c 24. d
04. b 25. d
40. Statement (I): In a transistor designed to be
05. b 26. a
used for power amplification, the collector size
is largest relative to the emitter and base. 06. b 27. d
Statement (II): The collector is connected to 07. d 28. b
the body of the transistor and hence to a heat
sink for heat dissipation to be effective. 08. d 29. b

(IES (EC) - 2012) 09. d 30. d

(a) Both Statement (I) and Statement (II) are 10. c 31. b
individually true and Statement (II) is the
11. b 32. b
correct explanation of Statement (I).
(b) Both Statement (I) and Statement (II) are 12. d 33. b
individually true but Statement (II) is not 13. b 34. b
the correct explanation of Statement (I).
14. c 35. c
(c) Statement (I) is true but Statement (II) is
false. 15. a 36. b
(d) Statement (I) is false but Statement (II) is 16. d 37. c
true.
17. b 38. a
18. a 39. b
41. An output signal of a power amplifier has
amplitudes of 2.5 V fundamental, 0.25 V 19. a 40. b
second harmonic and 0.1 V third harmonic. The
total percentage harmonic distortion of the signal 20. d 41. b
is 21. a
(IES (EC) - 2012)
(a) 12.6% (b) 10.8%
(c) 6.4% (d) 1.4%

233
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

CONVENTIONAL PROBLEMS 9
01. In order to reduce the harmonic distortion in an
Amplifier its dynamic range has to be ____
(GATE (EC) - 1994)

02. The circuit shown in the figure supplies power


to one 8  speaker, LS, The values of IC and
VCE for this circuit will be IC = ___ and
VCE=___
(GATE (EC) - 1995)

03. A power Amplifier delivers 50 W output at


50% efficiency. The ambient temperature is
25°C. If the maximum allowable junction
temperature is 150°C, then the maximum
thermal resistance θ Jc that can be tolerated is
______
(GATE (EC) - 1995)

234
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

CHAPTER-10
OSCILLATOR

01. A Wien bridge oscillator is shown in Figure. 4. Relaxation oscillator


Which of the following statements are true, if f 5. Negative Resistance oscillator
is frequency of oscillation.
Codes:
(GATE (EE) - 1993) (IES (EE) - 2008)
A B C
(a) 2 1 3
(b) 3 1 2
(c) 1 2 3
(d) 3 2 1

03. Value of R in the oscillator shown in the given


figure is chosen that it just oscillates at an angular
frequencies of ‘  ’. The value of ‘  ’ and the
1 required value of R will respectively be
(a) For R = 1 K, C   F , f  1 kHz
2
(GATE (EC) - 1996)
1
(b) For R = 3 K, C   F , f  3 kHz
18 

(c) The gain of the op-amp stage should be


less than two for proper operation.
(d) The gain of the op-amp stage should be
three for proper operation.

02. Match the following


(GATE (EC) - 1994)
List-I
A. Hartley
B. Wein-bridge
(a) 105 rad/sec, 2 ×104 
C. Crystal
(b) 2 × 104 rad/sec, 2 ×104 
List-II
1. low frequency oscillator (c) 2 × 104 rad/sec, 105 
2. High frequency oscillator (d) 105 rad/sec, 105 
3. Stable frequency oscillator

235
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

04. The oscillator circuit shown in the figure is R2

(GATE (EC) - 2001)

R1
-V CC -

+ +
LC

L=10H
CC R1 + Network
V (f) V0 (f)
f

- B(f)
C1=2pF C2=2pF

R2
-
R0
CC

(a) R 2  5R 1 (b) R 2  6R 1

(a) Hartley oscillator with R1 R1


(c) R 2  (d) R 2 
f oscillation  79.6MHz 6 5

(b) Colpitts oscillator with


06. The oscillator circuit shown in the figure has an
f oscillation  50.3MHz
ideal inverting amplifier its frequency of
(c) Hartley oscillator with oscillation (in Hz) is
f oscillation  159.2MHz (GATE (EC) - 2003)
(d) Colpitts oscillator with
f oscillation  159.2MHz

05. The circuit in the figure employs positive


feedback and is intended to generate sinusoidal
oscillation. if at a frequency f0 , B(f) =
Vf  f  1
  0o then to sustain oscillation at
V0  f  6 C C C
this frequency
(GATE (EC) - 2002)
R R R

1 1
(a)  2 6RC  (b)  2RC 

236
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

1 List-I
1
(c)  6RC  (d) 6  2RC  (Oscillator)
A. Wien Bridge
B. Colpitts
07. The value of C required for sinusoidal
C. Hartley
oscillations of frequency 1 kHz in the circuit of
the figure is D. Clapp
(GATE (EC) - 2004) List-II
(Characteristics/Features)
1 k 2.1 k
1. RF oscillator : two inductance and one
capacitance on the reactance network
- 2. LC oscillator for RF Frequency : three
V out
+ C capacitances and one inductance in the
reactance network
1 k
3. RC oscillator for audio frequency
applications

C
4. RF oscillator : two capacitances and one
1 k
inductance as the reactance network
Codes:
1 A B C D
(a) μF (b) 2πμF
2π (a) 2 1 4 3
1 (b) 2 4 1 3
(c) μF (d) 2π 6μF
2π 6 (c) 3 4 1 2
(d) 3 1 4 2
08. A crystal oscillator is frequently used in digital
circuits for timing purpose because of its 10. An FET oscillator uses the given phase shift
(a) Low cost network as shown below. The minimum gain
required for oscillation is
(b) High frequency stability
(IES (EE) - 2003)
(c) simple circuitry
(d) ability to set the frequency at the desired
value
R
09. Match List-I with List-II and select the correct C R
answer using the codes given below the lists:
(IES (EC) - 1996)

237
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) -29 (b) 1 Which of these statements are correct?


(c) 3 (d) 29 (IES (EE) - 2005)
(a) 1, 2 and 3 (b) 1 and 2
11. Consider the following statements: (c) 2 and 3 (d) 1 and 3
1. Wein bridge oscillator is suitable for
generating 1 KHz 14. Match List-I with List-II and select the correct
2. Colpitts oscillator is suitable for generating answer using the codes given below the lists :
1MHz (IES (EE) - 2000)
Which of these statements is / are correct? List-I
(IES (EE) - 2008) A. Wien bridge oscillator
(a) 1 only (b) 2 only B. Voltage shunt feedback amplifier
(c) Both 1 and 2 (d) Neither 1 nor 2 C. Crystal oscillator
D. Current shunt feedback amplifier
12. Consider the following statements regarding an List-II
RC phase-shift oscillator :
1. Low output impedance
1. The amplifier gain is positive.
2. RF frequency range
2. The amplifier gain is negative.
3. Audio frequency range
3. The phase shift introduced by the
feedback network is 180°. 4. High input impedance
4. The phase shift introduced by the 5. High output impedance
feedback network is 360°. Codes:
Of these statements A B C D
(IES (EE) - 1997) (a) 2 1 3 5
(a) 1 and 3 are correct (b) 3 4 2 1
(b) 2 and 3 are correct (c) 5 4 2 1
(c) 2 and 4 are correct (d) 3 1 2 5
(d) 1 and 4 are correct
15. The Barkhausen criterion for sustained
oscillation is given by
13. Consider the following statements:
(IES (EE) - 2000)
1. A hartley oscillator circuit uses a tapped
inductor for inductive feedback (a) Aβ  1 (b) Aβ  1
2. Oscillator circuit can be operated in
class A condition for better wave shape (c) Aβ  1 (d)  Aβ  180
3. Frequency stabilization is obtained by use
of automatic biasing
238
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EDC & ANALOG CIRCUIT

16. A Hartley oscillator is used for generating Which of the above statements are correct ?
(IES (EC) - 1999) (IES (EC) - 2002)
(a) very low frequency oscillation (a) 1, 2, 3 and 4 (b) 1 and 2
(b) radio-frequency oscillation (c) 1, 3 and 4 (d) 3 and 4
(c) microwave oscillation
(d) audio-frequency oscillation 20. An amplifier will generate stable sinusoidal
oscillations if we provide feedback such that

17. In every practical oscillator, the loop gain is (IES (EC) - 2002)
slightly larger than unity and the amplitude of (a) its poles lie close to jω - axis in the right
the oscillations is limited by the half of s-plane
(IES (EC) - 2000)
(b) its poles lie close to jω - axis in the left
(a) magnitude of the loop gain half of s-plane
(b) onset of non-linearity (c) its poles lie on the +ve real axis in s-plane
(c) magnitude of the gain of the amplifier (d) its poles lie anywhere in s-plane
(d) feedback transmission factor
21. Consider the following circuit

18. A relaxation oscillator is one which


(IES (EC) - 2001)
(a) has two stable states
(b) oscillates continuously
(c) relaxes indefinitely
(d) produces non-sinusoidal output
What is the circuit shown above ?
19. Consider the following statement regarding a (IES (EC) - 2004, 2011)
common emitter amplifier. (a) Miller sweep
It can be converted into an oscillator by: (b) Bootstrap sweep
1. providing adequate positive feedback (c) Schmitt trigger
2. phase shifting the output by 180° and (d) Triangular wave generator
feeding this phase-shifted output to the
input
22. Three amplifiers each of gain (A0 / 2) and
3. using only a series tuned circuit as a load producing a phase of 60° are connected in
on the amplifier tandem. The feedback loop is closed through
4. using a negative resistance device as a a positive gain of 0.008. What should be the
load on the amplifier value of A0 for the system to be oscillatory ?
(IES (EC) - 2005)
239
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) +10 (b) –10 (a) 1, 2 and 3 (b) Only 1 and 2


(c) +250 (d) +83.3 (b) Only 2 and 3 (d) Only 1 and 3

23. Match List-I (Name of the oscillator) with 25. In a practical oscillator circuit, which one of
List-II (Characteristics) and select the correct the following limits the amplitude of the
answer using the codes below the lists oscillations ?
(IES (EC) - 2005) (IES (EC) - 2008)
List-I (a) Onset of non-linearily
A. Colpitts oscillator (b) Power supply voltage
B. Phase shift oscillator (c) Oscillation frequencies
C. Tuned diode oscillator (d) temperature of the active device
D. Relaxation oscillator
List-II 26. Which one of the following oscillators is used
1. RC oscillator for the generation of high frequencies ?

2. LC oscillator (IES (EC) - 2009)


3. Negative resistance oscillator (a) R-C phase shift oscillator
4. Sweep circuits (b) Wien bridge oscillator
Codes: (c) L-C oscillator
A B C D (d) Blocking oscillator
(a) 1 2 3 4
(b) 2 1 3 4 27. Which one of the following oscillators is well
(c) 1 2 4 3 suited for the generation of wide range audio-
(d) 2 1 4 3 frequency sine waves ?
(IES (EC) - 2009)
24. Consider the following statements related to a (a) RC phase shift oscillator
shunt generator:
(b) Wien-bridge oscillator
1. The full load voltage is lower than no load
(c) Colpitts oscillator
voltage
(d) Hartley oscillator
2. The above lowering is partly due to voltage
drop in armature resistance.
28. The highest frequency stabiliby is achieved by
3. The field current does not change with load
using an oscillator of the type:
and has no effect on generated voltage.
Which of the statements given above are (IES (EE) - 2011)
correct? (a) Colpitts (b) Crystal controlled
(IES (EC) - 2006) (c) Hartley (d) RC oscillator
240
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

CONVENTIONAL PROBLEMS
01. Figure shows an RC-Phase oscillator. Solve
the network to find the minimum value of hfe for
the transistor for oscillations to be possible. Also
determine the frequency of such oscillations.
Take C = 0.01  F and hie = 2 K ohms
(GATE (EC) - 1990)

03. Find the value of R1 in the circuit of fig. For


generating sinusoidal Oscillations. Find the
frequency of oscillations.

(GATE (EC) - 1998)

04. Show that the circuit given in Figure will work


02. Determine the frequency of oscillation of the 1
circuit shown in Figure. Assume the op-amp to as an oscillator at f  , if R1 = 2R2
2 RC
be ideal.
(GATE (EE) - 1997) (GATE (EE) - 1998)

241
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

05. A transistor LC oscillator circuit is shown in and Cp = 1.0 p.f. Determine the resonance fs
Fig. Assume that the transistor has very high and fp
 (so that you may neglect rd). Derive an (IES (EE) - 1999)
equation governing the circuit operation, and
find the frequency of oscillation. Also, state the
gain condition required for oscillation to start. 10. Discuss where the sinusoidal oscillators are
used ? For phase shift oscillator why three
(GATE (EC) - 1999)
sections of ‘R-C’ circuits are cascaded. Draw
and explain a simple phase shift oscillator using
three sections of R-C circuit and a transistor.
Derive the formula for the frequency of
oscillation. Make comments on the transistor
current gain. Design the values of R-C to give
oscillation of say nearly 1 kHz.
(IES (EE) - 2000)

11. Explain, with a diagram, how Wien’s bridge can


be used for experimental determination of
frequency. Derive the expression for frequency
in terms of bridge parameters.
06. Discuss the operation of a generalized resonant
circuit oscillator with impedance Z1 Z2 and Z3. (IES (EE) - 2011)
Derive the conditions of oscillation and explain
under what circumst ances do es t he
configuration reduce to Hartley oscillator.
(IES (EE) - 1997)

07. What is Wien Bridge ? What are its uses ?


Show how variable frequency oscillator can be
built using an operational amplifier with a Bridge.
Derive an expression for the frequency of
oscillation of the circuit.
(IES (EE) - 1999)

08. Explain with figure the working of a typical


inductance type high frequency oscillator.
(IES (EE) - 1999)

09. The parameters of a crystal oscillator equivalent


circuit are Ls = 0.8 H; Cs = 0.08 pf; Rs = 5 k
242
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

ANSWER KEY

01. abd 16. b

02. a 17. b

03. a 18. d

04. b 19. b

05. a 20. a

06. a 21. a

07. a 22. b

08. b 23. b

09. c 24. d

10. c 25. a

11. c 26. c

12. b 27. b

13. b 28.

14. d

15. d

243
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

CHAPTER-11
PRACTISE SHEET
COMMON DATA
* electron charge e = 1.6 × 10–19 C 04. In a forward biased diode with Na >> Nd, the
* Room temperature T = 300 k product of the diffusion capacitance Cd and the
dynamic resistance rd equals
kT
* Thermal voltage = 0.025 V 1
e (a) (b) Tp
Tp
* Free space permittivity 0 =8.85×10–14 F/cm
1
* relative permittivity of silicon r = 12 (c) 2TP (d) 2Tp
* relative permittivity of SiO2 r = 4 Where Tp – the life time of minority carrier holes
* intrinsic carrier concentration
ni = 1.5 × 1010 – 3 cm 05. In a PN diode, for a constant value of current
* ideality factor n = 1 dV
at room temperature, varies
dT
One Mark Questions approximately at the rate of
01. When a diode is forward biased, the (a) – 2.5 mV/°C (b) – 25 mV/°C
recombination of free electrons and holes may (c) 2.5 mV/°C (d) 25 mV/°C
produce
(a) heat (b) light
06. The ratio of current for forward bias voltage of
(c) radiation (d) all of the above 0.04 V to the current for the same magnitude
of reverse bias is
02. In a step graded Junction, the width ‘w’ of the (a) 38788 (b) 3878
depletion layer varies as (c) 5000 (d) 58788
2
(a) V (b) V

(c) V (d) V–1 07. For what voltage will the reverse current in PN
junction Ge diode reaches 90% of its saturation
points at room temperature
03. In a reverse biased PN diode, t he (a) – 0.016 V (b) 0.016 V
concentration of minority holes in the n-region
at the junction boundary equals (c) 0.16 V (d) None

(a) Pno (b) Pno eV / VT


08. A Si diode has a saturation current of 0.1 pA
(c) Pno e V / VT
(d) Zero at 20°C. Find the current when it is forward
biased by 0.55 V
244
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) 0.6 mA (b) 0.3 mA 2. Output resistance


(c) 0.5 mA (d) None 3. Temperature coefficient
4. Input resistance
Two Marks Question Select the correct answer using the codes given
09. Consider an abrupt PN junction. Let the diode below:
be kept reverse biased. At a reverse bias of (IES (EE) - 2007)
1.2 V, the junction capacitance is 5 pF. What (a) 1 and 4 only (b) 1, 3 and 4
will be the bias voltage required to get a junction
(c) 2 and 3 only (4) 1, 2 and 3
capacitor of 2.5 pF. 0  0.8V (barrier
potential)
(a) 7.2 V (b) 5 V 13. Match List -I (Circuits) with List-II
(Characteristic / Applications) and select the
(c) 8 V (d) 2 V correct answer:
(IES (EE) - 2003)
10. If an input periodic signal wih non-sero d.c List - I
components is impressed upon a high- pass RC
circuit, what will be the d.c component in the A. High-pass RC circuit
output waveform? B. Low - pass RC circut
(IES (EE) - 2006) C. Clamping circuit
(a) Zero D. Clipping circuit
(b) It depends on the value of the capacitor List - II
(c) It depends on the value of the resistor 1. Comparator
(d) Same as that in input 2. DC Restorer
3. Integrator
11. The shunt type regulator is suitable for which 4. Differentiator
of the following?
5. Compensated Attenuator
(IES (EE) - 2007)
Codes:
(a) Low current, high voltage
A B C D
(b) Low current, low voltage
(a) 5 4 2 1
(c) High current, low voltage
(b) 4 3 1 2
(d) High current, high voltage
(c) 5 4 1 2
(d) 4 3 2 1
12. Which of the following are coefficients for a
regulated power supply (In the expression for
change in output voltage)? 14. Which one of the following statments is correct?
In the case of load regulation
1. Stability factor
(IES (EE) - 2005)
245
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(a) When the temperature changes, the output Codes:


voltage remains constant A B C D
(b) When the input voltage changes the load (a) 3 1 2 4
current remains constant
(b) 3 2 1 4
(c) When the load changes, the load current
remains constant (c) 4 2 1 3
(d) When the load changes, the output voltage (d) 4 1 2 3
remains constant.
17. Which one of the following statements
15. Why is an external pass resistor used in a regarding the two-transistor model of the
voltage regulator? p-n-p-n four-layer device is correct ?
(IES (EE) - 2006) (IES (EC) - 1997)
(a) For short circuit protection (a) It explains only the turn ON portion of
the device characteristic
(b) For increasing the current that regulator
can handle (b) It explains only the turn OFF portion of
the device characteristic
(c) For increasing the output voltage
(c) It explains only the negative region portion
(d) For improving the regulation of the device characteristic
(d) It explains all the regions of the device
16. Match List - I (Sections of a service Voltage characteristics
Regulator) with List - II (Elements used in these
sections) and select the correct answer using
the codes given below the lists: 18. A transistor amplifier has poles at
(IES (EE) - 2004) (IES (EC) - 1998)
List -I S1 = – 0.000245 × 109 rad/s
A. Reference source S2 = – 0.0748 × 109 rad/s
B. Error detector S3 = – 0.0670 × 109 rad/s and
C. Control device S4 = – 4.38 × 109 rad/s
D. Current limit The upper 3 dB frequency of the amplifier will
be
List - II
(a) S 1
1. Op-Amp
(b) S1 + S2 + S3 + S4
2. BJT
(c) S1 + S4
3. Zener diode
(d) S 4
4. Short - circuit protection

246
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

Conventional Problemsx
01. A pick-up signal N10 is power amplified using
a complementary symmetry pushpull amplifier
and fed to a 5-ohm loudspeaker as shown in
Fig. The specifications of the power transistor
are as follows :
(i) IC |max = Maximum collector current
= 2 Amps.
(ii) PC |max = Maximum Power disipassion
= 1 Watt.

03. The transistors in the differential amplifier shown


in Fig. are identical with hfe=100 and re=25ohms
at 1 mA collector current. The circuit has a
Common Mode Rejection Ratio (CMRR) of
100.
(GATE (EC) - 1992)
(a) What is the differential gain v0 / (v1 – v2) of
the circuit ?
(b) What is the common mode gain of the
Find the maximum power delivered to the circuit ?
loudspeaker if the maximum output voltage (c) If d.c. voltage of 1010 mV and 990 mV
subject to OP AMP voltage limitations is are applied to inputs 1 and 2 respectively
15 volts. If the transistors are manuted on a with reference to ground, what will be the
heat sink so that Pcmax changes to 3 Watts, what output voltage V0 ?
will be the new value of the maximum power
delivered ?
(GATE (EC) - 1990)

02. In Fig. both transistors are identical and have a


high value of beta. Take the dc base-emitter
voltage drop as 0.7 volt and KT/q = 25mV.
The small signal low frequency voltage gain
(Vo/Vi) is equal to ____
(GATE (EC) - 1990)

247
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

04.(a) For the circuit shown in Figure (a).


(i) Calculate the transfer function Vo / Vi .
(ii) Plot the amplitude and phase response as
a function of frequency for R = R1.
(b) For the JFET amplifier shown in Fig.(b)  =
100 and rd = 50 k 
(i) Draw the a.c. equivalent circuit
(ii) Find the voltage gain of the amplifier.
(GATE (EE) - 1992)
(b) Figure below shows an op-amp amplifier.
Find the output voltage in steady state
condition where
(i) switch S is open
(ii) switch S is closed
(GATE (EE) - 1994)

05. For the 2N 338 transistor, the manufacturer


specifies Pmax = 100 mW at 25°C free air
temperature and the maximum junction
temperature, T jmax= 125°C. Its thermal
resistance is ______
(GATE (EC) - 1994)

07. The waveform input to the sweep generator


06. (a) The circuit in Figure below, shows a circuit shown in the Fig. S, is a square wave of
feedback amplifier, Let Rs = Re = 1 k  , period 2m sec and an amplitude varying
between 0 and 12 volts.
Rc = 4 k  . The transistor parameters
are hie= 2 k  , hfe= 200 and hre= hoe = 0. (a) Draw the waveform V0(t) in relation to
the input
Assume that the inverting amplifier input
resistance is infinite and gain AV = – 2000. (b) Specify V0(t) determine the voltage levels
and the time-constants involved.
1
Let the feedback factor   . Find
159 (GATE (EC) - 1995)
V0
the gain of the amplifier A fv  .
Vs

248
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

(b) Determine the minimum values of VCC and


VEE such that the transistors remain in the
forward active region under zero-signal
condition. Assume that the dc common
mode input voltage is zero.
(GATE (EC) - 1996)

08. In the amplifier circuit shown in Fig. determine


the value of R such that Q2 is biased at
VCE2 = 7.5 V. Assume Q1 and Q2 to be
identical, VBE = 0.7 V and neglect base
currents. Also, determine the small signal input
impedance of Q1 and Q2 if both of them have
 = 200, Use VT = 26 mV.
(GATE (EC) - 1995)
10. Assuming ideal op-amps, show that the circuit
shown in Fig. simulates an inductor, i.e. show
Vi  s 
that I s is inductive and write the expression
i 

for the effective inductance.


(GATE (EC) - 1996)

09. A resistively loaded and resistively biased


differential amplifier circuit is shown in Fig.
Neglect base current and assume matched
transistors with VA   and  = 100.
Use VT = 26 mV, VBE(on) = 0.7 V, and
VCE(sat) = 0.1 V.
(a) Determine the values of RC and RE to meet
11. In the circuit shown in Fig. assume that the
the following specification :
operational amplifier is ideal and that Vo = 0V
Differential mode gain (double ended) initially. The switch is connected first to ‘A’
= –500. charging C2 to the voltage V. It is then connected
Common-mode rejection ratio = 500 to the point ‘B’. This process is repeated f
times per second.
Differential mode input resistance
(GATE (EC) - 1997)
= 2M 
249
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

13. For an input signal of 4 sin 10t, the voltage


across the resistance R in the circuit shown in
Figure is ... V.
(GATE (EE) - 1997)

(a) Calculate the charge transferred per


second from node A to node B.
(b) Derive the average rate of change of the
output voltage Vo.
(c) If the capacitor and the switch are
removed and a resistor is connected
between points A and B find the value of
the resistor to get the same average rate 14. For the differential amplifier circuit shown in
of change of the output voltage ? Figure determine the differential gain, the
(d) If the repetition rate of the switching action common-mode gain and the common mode
is104 times per second, C1 = 100 pF, C2 rejection ratio.
= 10pF and V = 10 mV, what is the (GATE (EE) - 1997)
average rate of change of the output
voltage ?

12. Find Static Noise-Margine for a BJT inverter


shown in Fig. Transistor used is an n-p-n type
with specifications as follows :

 F  70 , VBEON = 0.7 V, VBESAT = 0.8 V,


VCESAT = 0.1 V.
Also RL = 1 k , RB = 10 k and
supply VCC = 5V.
15. Determine the input impedance of the circuit of
(GATE (EC) - 1997) Fig. and investigate if it can be inductive.
(GATE (EC) - 1998)

250
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

16. Neatly sketch and label the dc transfer Where R=R1||R2


characteristic (i.e., V0 vs Vin) of the circuit
If R1 = 2 k , R2 = 2/3 k , R3 = 200 k and
shown in Fig. as Vin varies from –2 V to + 2V.
Assume ideal op-amp, and the diodes have a C = 0. 1  F , determine the centre frequency
forward voltage of 0.6 V and zero incremental 0 , gain A0 and the Q of the filter.
resistance.
(GATE (EE) - 2000)
(GATE (EC) - 1999)

20. For the circuit shown in Fig. 1  0.98 ,


 2  0.96 , V cc = 24 V, R c =120  and
IE =– 100 mA. Calculate the currents IC1, IB1,
IE1, IB2, IC2 and IC, the voltage VCE and the ratios
IC / IB and IC / IE. Neglect reverse saturation
currents.
(IES (EC) - 1998)
17. Fig. shows a common base amplifier.
(GATE (EC) - 2000)
(a) Write expressions for the time-constants
associated with the capacitors, CB and CS
(b) What is the approximate lower cut-off
frequecy of the amplifer

18. A current amplifier has an input resistance of


10  , an output resistance of 10 k and a
current gain of 1000. It is feed by a current Vo -Io
source having a sorce resistance of 10 k and 21. Calculate Ri, Av = V , AI = I for the circuit
s i
its output is connected to a 10  load shown. Use hie = 1000 ohms; hfe = 99;
resistance. Find the voltage gain and the power hre = hoe = 0
gain. (IES (EC) - 1998)
(GATE (EE) - 2000)

19. An active filter consisting of an op-amp,


resistors R1, R2, R3 and two capacitors of value
C each, has a transfer function

s

T s 
 R1C 
2s 1
s2  
 R3C   RR3C 2 
251
ENGINEER’S CIRCLE
EDC & ANALOG CIRCUIT

22. An amplifier with open loop voltage gain ANSWER KEY


Av = 1000  100 is available. It is required to
have an amplifier whose gain varies by no more 01. 10. a
than  0.2%. Find
02. 11. c
(IES (EC) - 1998) 03. 12. d
(i) reverse transmission factor  of the 04. 13. d
feedback network 05. 14. d
(ii) gain with feedback. Derive the formula 06. 15. a
you used.
07. 16. a
08. 17. d
Vo
23. Develop the voltage transfer function V for 09. 18. a
s

the amplifier shown


(IES (EC) - 1998)

24. Explain the current feedback characteristics of


voltage regulators .
Draw a circuit to realise the current feedback
characteristic in a low voltage regulator using
723 IC chip. Explain the working of the circuit.
(IES (EC) - 1998)

252
ENGINEER’S CIRCLE

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