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2kW Telecom SMPS

Design Guidelines

IFAT PMM Application & Systems 20.09.2012


Francesco Di Domenico
Vladimir Scarpa
Juan Sanchez
Table of contents

 Telecom Systems and Switch Mode Power Supplies

 48V 2kW Telecom Rectifier technical specification

 Design procedure

 Design of HV DC/DC Converter: ZVS Phase Shift Full Bridge

 Conclusions

9/27/2012 Page 2
Typical DC power supply system for Telecom
equipment

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 3


Typical hybrid solar DC power supply
system for Telecom equipment

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 4


Focus of the workshop:
AC/DC Telecom Rectifier

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 5


Key Features
 High and Flat Efficiency Curve

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Key Feautures

 Highest efficiency in minimum space

 Digital Control & Communication

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 7


Key Feautures

 Modular approach (power shelf)

 High MTBF requirements: >300.000hours at Tamb=25°C


(according to SR-332 calculation methodology)

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 8


Key features
 Accurate control of the charge curve

SCR BC SMR BC

CONTROL &
MONITORING
UNITS

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 9


Table of contents

 Telecom Systems and Switch Mode Power Supplies

 48V 2kW Telecom Rectifier technical specification

 Design procedure

 Design of HV DC/DC Converter: ZVS Phase Shift Full Bridge

 Conclusions

9/27/2012 Page 10
Typical Technical Specification Requirements
for a 48V /2kW Telecom Rectifier: AC input

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 11


Typical Technical Specification Requirements
for a 48V /2kW Telecom Rectifier: DC output

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 12


Other typical requirements

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Safety & EMC Standards

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 14


Table of contents

 Telecom Systems and Switch Mode Power Supplies

 48V 2kW Telecom Rectifier main requirements

 Design Procedure

 Design of HV DC/DC Converter: ZVS Phase Shift Full Bridge

 Conclusions

9/27/2012 Page 15
Principle Block Schematic of a
Switch Mode Telecom Rectifier
Isolated HV DC/DC Stage
85…3000V
SR-IC
Driver
53.5V
AC

HBr- SR-IC
Driver Driver

PFC PWM Controller


Controller

PFC stage PWM or resonant stage Secondary rectification


  
P
PAv

I
V

9/27/2012 Page 16
Inside a Telecom Rectifier

9/27/2012
Designing a 2kW CCM PFC
for Telecom Applications
85…3000V

SR-IC
Driver
53.5V
AC

HBr- SR-IC
Driver Driver

PFC PWM Controller


Controller
PFC – Design in 6 Steps
6
1
5
2 3

1 – Rectifying Bridge
2 – Filter Inductor
3 – Output Capacitor
4 – Boost Switch
5 – SiC Diode
6 – Bypass Diode
9/27/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 19
Input Parameters
Parameter Value

Input voltage 90-275Vac

Pmax High Line 2 kW


(185-275V)

Max Input Current 10.7 Arms

Bulk voltage 300-410 Vdc

Switching frequency 65 kHz

Output Voltage Ripple 5%

Current Ripple 20%

Max. Ambient Temp. 70°C

Max. Junction Temp. 125°C

9/27/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 20


Table of contents

 Circuit Design

 Calculated Efficiency Curve

 Experimental Results

9/27/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 21


1 - Bridge Rectifier

Average current=avg. input current:

2 2
I BR = I in.avg = I in..rms ⋅ 10.7A
π
Power dissipation:

PBR = 2 ⋅ V f . BR ⋅ I BR 21.4W

9/27/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 22


2 - Filter Inductor:

Peak input current: Peak Current


Max. Current
I PK = 2 I in..rms 16A

Current ripple:
I HF = 20% ⋅ I PK 3.2A

Peak Current + ripple: Ripple


I
I L.MAX = I PK + HF 17.6A
2

9/27/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 23


Filter Inductor:

At peak current, ripple=20%:


δ∙Tsw
I HF = 20% ⋅ 2 I in..rms 3.2A

Duty cycle, for Uin.min:


U
∂ = 1− in.min 0.62
U out
Minimum Inductance: 20%Ipeak
VL ⋅ ∆t Vin ⋅ ∂TSW
L1 = = 450µH
∆I I HF

9/27/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 24


3 - Output Capacitor

Minimum capacitance value:


Hold up time:
Pout .max
⋅ Tac
 No Vin for 20ms I ⋅ ∆t U out . min 6.7 A ⋅ 20ms C > 1.3mF
Cout = = = out
∆U U out − U out . min 100V
 Po=Po.max
 Uout>Uout.min 2*fac voltage ripple in output:

Pout . max
Uout.min=300V ⋅
U in.min ∆Uout =4%
∆U out = = 15V
2π ⋅ f ac ⋅ Cout
9/27/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 25
4 - Boost Switch

For Rds.on Optimization: Iin


Pin Icon.sw
I cond .sw = ⋅ δ avg
230V 4.7A
∂ avg = 0.53 @ U in = 230V

Conduction losses estimation: Voltage class:


2
Pcond .sw = Rds.on _125°C ⋅ I cond U sw = 1.30 xU out 535V
. sw

9/27/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 26


4.1 - CoolMOS™ P6 vs. CoolMOS™ C6

 Lower Qg  less driver losses

 Higher threshold voltage  less turn-off losses

 Smaller internal Rg  faster commutation

190 mΩ parts, Rg=5Ω

CoolMOS™ C6 CoolMOS™ C6

CoolMOS™ P6 CoolMOS™ P6 ∆E=20µJ

∆Ex65kHz=1.3W

9/27/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 27


4.2 – Rds_on Optimization

Due to power level  2 switches in parallel!

Tj=125°C

Optimum
Rds_on~200mΩ
For each switch

Switching losses

9/27/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 28


4.3 - Thermal Design

Switch losses @ Vin=230Vac: Plosses = 4.4 W per part

Switch losses @ Vin=185Vac: Plosses = 7.2 W per part

Rth,JC of each part: RTH,JC = 2.6 °C/W

RTH,JC RTH,CA
Tj<125°C
Tamb=70°C
Case
RTH,CA < 5 °C/W
9/27/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 29
5 - Boost Diode

Si Diode SiC Shottky Diode

 Price  No switching losses


 Surge current capability  Less losses in the switch

9/27/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 30


5.1 - ThinQ™ Gen 5 SiC Diodes

650V SiC Diode

Sw. Losses
Thin-wafer technology G2

QC
Wire bond G3

bond metal
G5 Cond. Losses
Schottky contact
Drift layer
Vf
SiC Substrate R bulk

η% Comparative Efficiency
Backside metal

Simplified schematic, with no merged pn junction.


Gen 5
Gen 3
Gen 2

VF = Vth + Rdiff ⋅ I F Load [W]

9/27/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 31


5.3 – Choice of the Current Class

Average current RMS Current Dissipated power

P Pdi = Vth I di.avg + Rdiff ⋅ I 2 di .rms


I di .avg = out = 5 A I di .rms = 2 ⋅ I in.rms ⋅ (1 − D ) = 7.5 A
U out

Junction Temp. [C]


9/27/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 32
6 - Bypass diode

Output capacitor is fully charged during 1 semi-cycle=10ms:

U out ⋅ C out 400 V ⋅ 1 . 3 mF


I surge = = 53A
Tac / 2 10 ms

9/27/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 33


Table of contents

 Losses Calculation

 Calculated Efficiency Curve

 Experimental Results

9/27/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 34


Losses and Circuit Efficiency

@Vin=230Vac Pbr=15.4W

Pind=10.1W
Psw=8.7W
Pdi=8.6W

@Vin=230Vac
η10%= 97.9%
η20%= 98.2%
@Vin=90Vac
P.max=850W η50%= 98.1%
η100%= 97.9%

9/27/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 35


Table of contents

 2kW PFC Circuit Design

 Losses Calculation

 Experimental Results

9/27/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 36


Efficiency Measurement
1kW, 1x190mΩ CoolMOS™, 1x6A Gen 5  same semiconductor effort

CoolMOS™ P6

CoolMOS™ C6 CoolMOS™ P6

CoolMOS™ C6

THS  60°C
fsw  65kHz
Rg,ext  10Ω

9/27/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 37


Efficiency Measurement
Low Line (up to 350W)

CoolMOS™ P6
CoolMOS™ C6

CoolMOS™ P6
CoolMOS™ C6

THS  60°C
fsw  65kHz
Rg,ext  10Ω

9/27/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 38


Table of contents

 Telecom Systems and Switch Mode Power Supplies

 48V 2kW Telecom Rectifier main requirements

 Design procedure

 Design of HV DC/DC Converter: ZVS Phase Shift Full Bridge

 Conclusions

9/27/2012 Page 39
Principle Block Schematic of a
Switch Mode Telecom Rectifier

85…3000V
SR-IC
Driver
53.5V
AC

HBr- SR-IC
Driver Driver

PFC PWM Controller


Controller

9/27/2012 Page 40
HV DC/DC Stage: choice of the topology
Figure of merit ZVS PF FB vs. HB LLC

10

4
Phase Shift FB
3 LLC HB

9/27/2012
ZVS Phase Shift Full Bridge

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 42


ZV PS FB - principle of operation

 power transfer phase over A/D IPRIM


 discharge Coss of C and charge Coss of D

 commutation to body diode of C

 free-wheeling phase
0A
 charge Coss of A and discharge Coss of B primary current
changes direction
 commutation to body diode of B

 power transfer phase over C/B

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 43


ZVS PS FB: main components dimensioning
and inherent topics

 Main Transformer
 FB HV MOSFETs
 Resonant Choke
 Output Choke
 Output Capacitance
 Synchronous Rectification
 Topology
 Power MOSFETs

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 44


2kW ZVS PS FB Reference Design

 board description

 DC/DC converter with 300V-420V input

 45V-56V output voltage

 Fsw=100kHz

 up to 2000W output power

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 45


Schematic
Output filter

Main trafo

Synchronous rectification

Lr=res. inductance
Full Bridge

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 46


HV DC/DC Converter:
Main Design Specifications

Description Minimum Typical Maximum


Input Voltage 300Vdc 400Vdc 410Vdc
Output Voltage 45Vdc 54Vdc 56Vdc
Output Power 2000W
Full Load Efficiency 95%
Switching Frequency 200kHz
“seen” by Lout choke
δcycle 70%
Dynamic Output Vtrans=
Voltage regulation ±5%Vout_MAX=2.8V
(0-90% Load step)
Voutripple 100mVpk-pk

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 47


Main Transformer Design:
Center Tap vs. Current Doubler

30

Center Tap

25
Current Doubler_1

20 Current Doubler_2

15

10

0
Pcu_sec Ptr_tot Pcu_Lout Pcore_Lout Ptotal_Lout Ptotal_magnetics

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 48


Main Transformer Design:
core selection
 Area Product Formula

 Applying this “rule of thumb” formula Ae≥200mm2

Ae=201mm²
PQ/40/40 core Ve=20500mm³

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 49


Main Transformer Design:
turn ratio, Np, Ns

 Turn Ratio α1=Np/Ns

 Primary turns Np

20

 Secondary Turns Ns=Np/α1 4

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 50


Kaschke main transformer

 core type: PQ40/40

 core material: 3C96

 nominal inductance: 1mH ±15%

 ratio of turns: 20 : 4 : 4

 dielectric strength (50Hz/1s): 3kV

 operating temperature: -25°C till +125°C

 storage temperature: -25°C till +85°C

Kaschke Components GmbH

Rudolf-Winkel-Str. 6

37079 Göttingen

Germany

dimensions in [mm]

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 51


Choice of the power devices:
650V 80mOhm CFD2

9/27/2012 Page 52
Losses spread on HV MOSFETs in a Soft
Switching topology (fsw=100Khz & 200Khz)
Primary mosfets losses
Primary mosfets @Pmax
losses @10%Pmax 100Khz (P=10.52W)
100Khz (P=0.589W)
16% 3.8%
(0.09W) 13.7% (0.4W)
13.1% Conduction Losses Conduction Losses
(1.44W)
(0.07W) Turn on losses Turn on losses
68.4%
Turn off losses 80% Turn off losses
(0..4W)
Driving losses
(8.4W) Driving losses

Primary mosfets
Qg Primary mosfets
losses @Pmax
Rds,on
losses @10% Pmax 200Khz (P=12.64W)
200Khz (P=1.05W)
6.4%
8.2% 5.4% (0,056W) (0.8W)
22.8%
(0,09W 9.7%
Conduction Losses
(2.88W) Conduction Losses
(0,1W)
76.7% Turn on losses
66.4% Turn on losses
(0.8W) 4.4% (8.4W) Turn off losses
Turn off losses (0.88W)
Driving losses
Driving losses

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 53


The transition time: the “ZVS window”

Vgs high side Qg


90% VDS
Vds low side
Qoss

10% VDS

t1 t2 t3

 td_off = t1 -> t2
 td_Vdstrans = t2 -> t3
 td_total = t1 -> t3

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 54


MOSFET key parameters in ZVS design:
Body diode

 Vf involved in conduction losses at turn-on


 Qrr/trr involved in reliability issues on the leg with less
resonant energy available.

Reverse
recovery
current

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 55


Typical hard commutation on body diode
still not fully recovered
Short-through like, but it is a current flows through HS
MOSFET and reverse recovery current for body diode of LS MOSFET
VGS,1

VGS,2
Q1

IDS,1
Cr Lr

IDS2
Id,2XRds,on=0 Reverse recovery
Body diode can’t turn off completely current Lm
VDS,2 Q2

•Over-shoot of VDS
VDS,1 •Extremely high dv/dt and di/dt

9/27/2012 Page 56
Completely Reverse Recovery MOSFET

No voltage, no current ringing

Above specified current level, the body diode is completely reverse recovered

9/27/2012 Page 57
Un-Completely Reverse Recovery MOSFET

Voltage/current ringing

Under specified current level, the body


diode is un-completely reverse recovery
9/27/2012 Page 58
Choice of the FB power MOSFET: why CFD2?
Qg benefits

about 30% reduction of Qg over whole


RDS(on) range
BENEFITS:
• lower driving losses
• faster switching

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 59


Choice of the FB power MOSFET: why CFD2?
Qrr benefits

• CFD2 shows less Qrr in comparison to CFD and comparable competitor products

BENEFITS:
• less stress on MOSFET during commutation
• makes device suitable for soft switching application

9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 60


The resonant tank
 Total resonant capacitance

 Energy stored in the resonant capacitance

 Energy which must be provided by the resonant inductance:

 In the case of CFD2, with the goal to achieve ZVS down to


20%Pmax:
Lr=30µH

9/27/2012 Page 61
Kool-mu 77894 resonant choke

9/27/2012 Page 62
Output Choke

 Minimum needed Lout

where

9/27/2012 Page 63
MPP 55083 Output choke

9/27/2012 Page 64
Output Capacitance

 Total Cout selected according to load transient requirement


 Time needed by Lout to change 90% of its full load current:

 Selected capacitors 470µF KZE miniaturized (ESR=0.028Ω,


Iripple=2.3A)

 Final choice:
N=6 470µF, 63V, KZE capacitors

9/27/2012 Page 65
Synchronous Rectification

85…3000V
SR-IC
Driver
53.5V
AC

HBr- SR-IC
Driver Driver

PFC PWM Controller


Controller

9/27/2012 Page 66
Synchronous Rectification Possible Applications

 12V systems: Computing (PC Silver box, Server SMPS, Gaming)

- 40V, 60V, 75V, 80V MOSFETs

 12V-24V systems: Notebook adapter, industrial SMPS


- 100V, 120V MOSFETs

 24V-48V systems: Telecom, industrial SMPS

- 150V, 200V , 250V MOSFETs

 60V-100V systems: LCD


- 150V, 200V , 250V MOSFETs

11/03/2010
SMPS - What is be the trend for the future?
Server Power supply example

Up to now

EFFICIENCY

5 years ago Now 5 years in the future


Future
trend

EFFICIENCY
&
POWER
DENSITY 10W / inch³ 30W / inch³

Set date Page 68


How to achieve?
Technology improvement
Reduction of FOM=RDS(on) x Qg

Higher efficiency

Lower power losses

Smaller heatsinks

Package Shrink

TO220 SuperSO8 Blade

Set date Page 69


Principle of Synchronous Rectification

Copyright ©
Infineon
Set date Page 70
Technologies 2011.
All rights reserved.
What is synchronous rectification???
Replacement of the diodes by MOSFETs on the
secondary side of a SMPS

• a MOSFET (sync. FET) replaces a diode in its electrical functionality


• the sync. FET has NO control function  no active switching of current 
(gate) switching speed has no influence on efficiency!
• no additional function compared to the diode is realized
• with a gate-source short on the sync. FET, the system stays electrically
functional
June 2010
Optimized device selection for
Synchronous Rectification

Copyright ©
Infineon
Set date Page 72
Technologies 2011.
All rights reserved.
Analyzing the SR turn-off behavior
UDSpeak dv I C (t )
VDS =
reverse
Gate
recovery dt Coss
turn-on
behavior
VT
Iinit VDS
IDS
VG
Free
oszillation
VGS
VD
Vind
Qrr* VGS

MOSFET body diode on- Qoss IDS


time time
Vind

Irev_peak
di VDS (t ) − VT
=
tD tQrr*+Qoss dt L
tramp
Calculation of power losses in SR (I)

 Conducting losses
2
Pv _ cond = I RMS ⋅ RDS ( on )

 Gate losses

Pv _ gate = Qg ⋅ U g ⋅ f sw

 Body diode conduction loss

PV _ BD _ cond = U D ⋅ I D ⋅ t BD _ on ⋅ f sw

27.09.2012
Development of a power-loss model

 Assumptions for following model

− Fast primary side switches

− Current commutation on sec. side is inductively limited

Upeak
EC = 1 ⋅ C ⋅ V 2
I comm
UDS
2
Utrafo

Qoss ID time
di/dt=const Qrr*
Irev_ peak
EL = 1 ⋅ L ⋅ I 2
tIpeak tUpeak 2
trev
Synchronous Rectification Losses
Summary

 Conducting losses

Conduction
2
Pv _ cond = I RMS ⋅ RDS ( on )
 Body diode conduction loss

PV _ BD _ cond = VD ⋅ I D ⋅ t BD _ on ⋅ f sw
 Gate losses

Pv _ gate = Qg ⋅Vg ⋅ f sw

Switching
 Turn-off – reverse recovery losses

Psw = VT ⋅ (1 2 ⋅ Qoss + Q *rr ) ⋅ f sw


27.09.2012
Power Loss Distribution

Distribution of power losses in SR


BSC031N06NS3 G, switching frequency = 125kHz, transformer voltage = 30V,
Vout=12V
2.50
output capacitance losses
power losses per MOSFET [W]

2.00 gate drive losses


conduction losses

1.50

1.00

0.50

0.00
10 30 50
output currrent [A]

Switching losses dominate at low loads


Conduction losses dominate at high loads

Set date
The key for further performance improvement

Power Losses vs Rds(on)


V_Transformer=135V; Vgate=10V; Fsw=100KHz; Iout=45A
60
Pswitching
switching losses Pconduction
balanced operation
50 dominated P_Total
Power Loss [W]

40
Optimum Rds(on) ~ 4.5 mΩ  2xIPP110N20N3 G
(Rds(on)max = 11 mΩ)
30

20 conduction losses
dominated
10

0
0 2 4 6 8 10 12 14 16 18 20

Total SR Rds(on) [mOhm]

FOM Qg ⋅ f sw ⋅ Vg + 1 ⋅ FOM Qoss ⋅ VT ⋅ f sw


RDS ( on ) _ opt = 2
2
I RMS
Set date Page 78
Design considerations

Copyright ©
Infineon
Set date Page 79
Technologies 2011.
All rights reserved.
Turn-off voltage overshoot

VDS overshoot

VDS
VGS
di/dt

Set date Page 80


Qrr impact - measurement
Qrr & Overshoot vs. Body Diode On Time
IPP05CN10N

60 nC Device not fully off 120 V


Shoot through
50 nC 100 V

40 nC 80 V

Overshoot
Qrr

30 nC 60 V

20 nC Qrr 40 V
Overshoot
10 nC Poly. (Qrr) 20 V
Poly. (Overshoot)
0 nC 0V
0 ns 20 ns 40 ns 60 ns 80 ns 100 ns 120 ns 140 ns 160 ns
Body Diode On Time

 Lower body diode on time -> lower Qrr -> lower overshoot
-> lower losses -> better efficiency
 Qrr dependencies are complex: Qrr increases with tBody and di/dt
 Parallel schottky diode will reduce Qrr but increase leakage current
 Infineon new 40V introduce Schottky-like diode technologies

27.09.2012
Impact of the package

Copyright ©
Infineon
Set date Page 82
Technologies 2011.
All rights reserved.
Highest Efficiency
package contribution

The lower the product resistance the higher the package contribution

Set date
Highest Efficiency
Reduction of FOM

Immense reduction of FOM for SuperSO8 packaging

Comparison - Figure of Merit (FOM)


Current 60V OptiMOS™ technology
500

450 -45% reduction


400

350
FOM [mOhm x nC]

300

250

200

150

100 TO220
50 SuperSO8
0
FOM(Qg) FOM(Qoss)

Set date
Highest Efficiency

Measurement in Server DC/DC


94
SuperSO8
solutions
allow: 93

-Lower
92
package
efficiency [%]

resistance
91 Higher efficiency through
lower power losses
90
-Less
parasitics
BSC047N08NS3
89
IPP057N08N3

-Lower turn- 88
10 20 30 40 50
off losses
output current [A]

Conditions: 12V - 600W server PSU, 100kHz switching frequency, half bridge, current doubler rect.
Set date
Outstanding Switching Behavior
LOUT
High side switch

Transformer
COUT

GND

power-commutation loop
Low side switch

• SuperSO8 layouts minimize parasitic loop inductances


• turn-off losses are minimized
• ringing is minimized
• efficiency of snubber circuit is maximized
Set date
Outstanding Switching Behavior

90

80
10V reduction
UDS
VDS
voltage overshoot
overshoot [V]

70 voltage overshoot

60

50

40
10 20 30 40 50
output current [A]

Conditions: Half Bridge DC/DC converter 12V, fsw=100khz, 100V MOSFETs

Set date
Summary
 Synchronous Rectification brings out outstanding power savings.

 Newest Optimos MOSFETs technologies widens the range of


applications and conditions where SR is advantegeous.

 The most important loss contributions are coming from the


Rds(on) of the device and Eoss and Qrr.

 For a given technology, the right MOSFET Rds(on) working at a


balanced operation (tradeoff between switching and conduction
losses) will offer the best performance.

 Qrr is a parameter with complex dependencies that hardly can


be characterized by one simple value in the specifications.

 Adoption of new Leadless packages like TO-220 makes possible


to extract the benefits from the advances in silicon technology
27.09.2012
Table of contents

 Telecom Systems and Switch Mode Power Supplies

 48V 2kW Telecom Rectifier main requirements

 Design procedure

 Design of HV DC/DC Converter: ZVS Phase Shift Full Bridge

 Conclusions

9/27/2012 Page 89
PFC

85…3000V
SR-IC
Driver
53.5V
AC

HBr- SR-IC
Driver Driver

PFC PWM Controller


Controller

9/27/2012 Page 90
PFC efficiency plots

@Vin=230Vac

η10%= 97.9%
η20%= 98.2%

@Vin=90Vac η50%= 98.1%


P.max=850W η100%= 97.9%

9/27/2012 Page 91
ZVS Phase Shift Full Bridge with Synchronous
Rectification

85…3000V
SR-IC
Driver
53.5V
AC

HBr- SR-IC
Driver Driver

PFC PWM Controller


Controller

9/27/2012 Page 92
ZVS Phase Shift Full Bridge
IFX reference design

 main components
 full bridge MOSFETs: IFX CoolMOSTM IPW65R080CFD

 synchronous rectification MOSFETs: IFX OptiMOSTM IPP110N20N3

 auxiliary converter: Infineon ICE3A0365

 controller: Texas Instruments UCC28950

 gate driver: Texas Instruments UCC27324

 main transformer: Kaschke Components GmbH PQ40/40 ferrite core (center tap)

 resonant choke: Magnetics Inc. Kool-Mµ

 output choke: Magnetics Inc. Molypermalloy


9/27/2012 Copyright © Infineon Technologies 2012. All rights reserved. Page 93
CFD2 80mOhm in 2kW ZVS PS FB board –
efficiency measurements

Efficiency -CFD2 80mOhm in 54V/37A ZVS Phase Shift Full Bridge

98 CFD2 80mOhm 100Khz

97.5

97

96.5
EFFICIENCY [%]

96

95.5

95

94.5

94
0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200
OUTPUT POWER [W]

9/27/2012 Page 94
Target Efficiency achieved!

9/27/2012 Page 95

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