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ESE 568: Mixed Signal Design and

Modeling Opamp

Lec 5: September 17th, 2018


Basic 2-stage Opamp Design

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Ideal Opamp Opamp Practical Circuits


!  The ideal opamp characterized by seven properties !  Voltage comparator 
"  Knowledge of these properties is sufficient to design and
analyze a large number of useful circuits
!  Basic opamp properties
"  Infinite open-loop voltage gain
"  Infinite input impedance
"  Zero output impedance !  Voltage follower 
"  Zero noise contribution
"  Zero DC output offset
"  Infinite bandwidth
"  Differential inputs that stick together
"  Zero input differential voltage
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Opamp Practical Circuits


!  Integrating amplifier 
Opamp Design

!  Differentiating amplifier

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Ideal Opamp Steps in Designing a CMOS Opamp
!  1) Choosing or creating the basic structure of the
opamp
"  This step results in a schematic showing the transistors
and their interconnections 
"  This diagram does not change throughout the remainder
of the design unless the specifications cannot be met,
then a new or modified structure must be developed 
!  2) Selection of the dc currents and transistor sizes
"  a.k.a Biasing and sizing 
"  Most of the effort of design is in this category
"  Simulators are used to aid the designer in this phase

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Steps in Designing a CMOS Opamp Design Variables


!  3) Physical implementation of the design !  Boundary conditions (constraints): 
"  Layout of the transistors  "  1. Process specification (VT, μ, Cox, etc.) 
"  Floorplanning the connections, pin-outs, power supply "  2. Supply voltage and range 
buses and grounds  "  3. Supply current and range 
"  Extraction of the physical parasitics and re-simulation  "  4. Operating temperature and range 
"  Verification that the layout is a physical representation of
the circuit
!  4) Fabrication 
!  5) Measurement 
"  Verification of the specifications 
"  Modification of the design as necessary
"  Make sure it’s not necessary!
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Design Variables Specifications


!  Specifications:  !  1. Open-loop Gain 
"  1. Open-loop Gain  "  Typically an op-amp may have a maximal open-loop gain
2. Gain bandwidth 
" 
of around 105
"  3. Settling time 
V
"  4. Slew rate  AOL = + out −
Vin −Vin
"  5. Input common-mode range, ICMR 
"  6. Common-mode rejection ratio, CMRR 
"  7. Power-supply rejection ratio, PSRR 
"  8. Output-voltage swing 
"  9. Output resistance 
"  10. Offset 
"  11. Noise 
"  12. Layout area

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Specifications Specifications
!  1. Open-loop Gain  !  3. Settling time 
"  Typically an op-amp may have a maximal open-loop gain !  4. Slew rate 
of around 105
V ! dv (t) $
AOL = + out − SR = max # out &
Vin −Vin " dt %

!  2. Gain bandwidth 

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Specifications Specifications
!  5. Input common-mode range, ICMR  !  6. Common-mode rejection ratio, CMRR
"  The input common-mode range is the range of common- "  CMRR is a measure of how well the differential amplifier
mode voltages over which the differential amplifier rejects the common-mode input voltage in favor of the
continues to sense and amplify the difference signal with differential-input voltage.
the same gain. 
avd
"  Typically, the ICMR is defined by the common-mode CMRR =
avc
voltage range over which all MOSFETs remain in the
saturation region. !  7. Power-supply rejection ratio, PSRR 
avd
PSRR+ =
a+
avd
PSRR− =
a−

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Specifications Specifications
!  8. Output-voltage swing  !  8. Output-voltage swing 
"  Expected output swing "  Expected output swing
!  9. Output resistance  !  9. Output resistance 
"  Resistance seen into the output "  Resistance seen into the output
!  10. Offset  !  10. Offset 
"  Output offset voltage (VOS(out))  "  Output offset voltage (VOS(out)) 
"  The output offset voltage is the voltage which appears at the "  The output offset voltage is the voltage which appears at the
output of the differential amplifier when the input terminals are output of the differential amplifier when the input terminals are
connected together.  connected together. 
"  Input referred offset voltage (VOS(in) = VOS) 
"  The input referred offset voltage is equal to the output
offset voltage divided by the differential voltage gain. 
"  VOS = VOS(out)/AVD
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Opamp Design Output Opamp Design Practical Advice
!  1) The topology  !  1) Decide upon a suitable topology
"  The topology should be the one capable of meeting most of the
!  2) The dc currents  specifications
Try to avoid “inventing” a new topology but start with an existing
!  3) The W and L values of transistors  " 

topology
!  4) The values of components !  2) Determine the type of compensation needed to meet the specifications
"  Consider the load and stability requirements
"  Use some form of Miller compensation or a self-compensated approach
!  I.e Schematic and biasing !  3) Design dc currents and device sizes for proper dc, ac, and transient
performance
"  This begins with hand calculations based upon approximate design
equations.
"  Compensation components are also sized in this step of the procedure.
"  After each device is sized by hand, a circuit simulator is used to fine tune
the design

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Opamp Design Practical Advice


!  Two basic steps of design:
"  1) “First-cut” - this step is to use hand calculations to
Basic 2-stage Opamp
propose a design that has potential of satisfying the
specifications. Design robustness is developed in this
step.
"  2) Optimization - this step uses the computer to refine
and optimize the design.

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2-Stage Opamp 2-Stage Opamp

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Design Variables
!  Specifications: 
"  1. Open-loop Gain  Basic 2-stage Opamp
"  2. Gain bandwidth 
"  3. Settling time 
"  4. Slew rate 
"  5. Input common-mode range, ICMR 
"  6. Common-mode rejection ratio, CMRR 
"  7. Power-supply rejection ratio, PSRR 
"  8. Output-voltage swing 
"  9. Output resistance 
"  10. Offset 
"  11. Noise 
"  12. Layout area

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2-Stage Opamp Differential DC Gain

!  Inputs are equal in magnitude but opposite in sign


to each other
!  By linearity and symmetry, is1 must equal -is2
"  This implies iR is zero, so that voltage drop across ro4 is zero
"  The sources of M1 and M2 are therefore at incremental ground and
decoupled from each other!
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2-Stage Opamp 2-Stage Opamp


!  1. Open-loop Gain  !  2. Frequency Response
RC=0

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2-Stage Opamp 2-Stage Opamp
!  2a. Frequency Response – no compensation CC=0 !  2a. Frequency Response – no compensation CC=0

1 1
p1 = − p2 = −
Ro1C1 Ro2C2

A0
A(s) =
"  Two poles: " s %" s %
$1− '$1− '
# p1 &# p2 &
1 1
p1 = − p2 = −
Ro1C1 Ro2C2

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2-Stage Opamp Transfer Functions 2-Stage Opamp Transfer Functions

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Phase Margin Stability


!  Find phase at unity-gain
frequency (ω0)
!  Add 180o for phase margin

!  Red
"  Phase at ω0 = -81.3
ο

"  PM=98.7
ο

!  Blue
"  Phase at ω0 = -231
ο

"  PM=-50
ο

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Stability vs. Phase Margin Phase Margin
!  Find phase at unity-gain
frequency (ω0)
!  Add 180o for phase margin

!  Want phase margin >45o


(~60o)
"  Problem: Hard to do

with 2-stage opamp with


high gain
"  Solution: Split the poles

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Impact of Pole Splitting with Compensation Cap 2-Stage Opamp


!  2b. Frequency Response – with compensation CC>0

"  Two poles:


!  Pole splitting allows the dominant pole frequency to be
dramatically decreased and the main parasitic pole to be 1 gm 7CC −g
dramatically increased p1 ≈ −
Ro1 (gm 7 Ro2CC ) p2 ≈ − ≈ m7
C1C2 + C1CC + CC C2 C2
"  We can achieve higher unity gain frequency with improved phase margin

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2-Stage Opamp Nulling Resistor


!  2b. Frequency Response – with compensation CC>0 z1 =
1
" 1 %
CC $ − RZ '
1 # Gm2 &
p1 ≈ −
Ro1 (gm 7 Ro2CC )

gm 7CC −g
p2 ≈ − ≈ m7
C1C2 + C1CC + CC C2 C2

gm 7
z1 =
CC

" s%
A0 $1− '
# z2 &
A(s) =
" s %" s %
$1− '$1− '
# p1 &# p2 &

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Transistor for RZ 2-Stage Opamp – Unity Gain Freq
!  Equivalent capacitance at node v1

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2-Stage Opamp – Unity Gain Freq 2-Stage Opamp – Unity Gain Freq
!  Equivalent capacitance at node v1: Ceq = CC (1+ Av2 ) ≈ CC Av2 !  Equivalent capacitance at node v1: Ceq = CC (1+ Av2 ) ≈ CC Av2

v1 " 1 %
Av1 = = −gm1Z out1 = −gm1 $$ rds2 || rds 4 || '
vin # sCeq '&

1 1
Av1 ≅ −gm1 ≅ −gm1
sCeq sCC Av2

vout −gm1 −g
Av (s) = = Av2 Av1 ≅ Av2 = m1
vin sCC Av2 sCC

g m1
Av ( jω 0 ) = 1 for ω 0 =
CC
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2-Stage Opamp 2-Stage Opamp – Slew Rate


!  3/4. Settling Time/Slew Rate

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2-Stage Opamp 2-Stage Opamp
!  3/4. Settling Time/Slew Rate !  3/4. Settling Time/Slew Rate

dvout I CC I D5
max
SR ≡ = =
dt max CC CC

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Finite Slew Rate Effect 2-Stage Opamp


!  Ex. Unity-gain Follower !  3/4. Settling Time/Slew Rate

dvout I CC I D5
max
SR ≡ = =
dt max CC CC

g m1
vI = Asin(ω t) ω0 =
CC
dvo
= Aω
dt MAX

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Unity Gain Freq and Slew Rate Unity Gain Freq and Slew Rate
!  Relationship between unity gain frequency and slew !  Relationship between unity gain frequency and slew
rate: rate:
g m1 I D5 I D5 g m1 I D5 I D5
ω0 = SR = SR = ω ω0 = SR = SR = ω
CC CC
g m1 0 CC CC
g m1 0

!  For 45° phase margin: ω o = p2 !  For 45° phase margin: ω 0 = p2

I D5 I D5
SR = p2 SR = p2
gm1 gm1
gm 7CC −g
p2 ≈ − ≈ m7
C1C2 + C1CC + CC C2 C2
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Design Variables Admin
!  Specifications:  !  HW 2 and 3 due Su
"  1. Open-loop Gain  "  Want to make sure every has Cadence set up and running
"  2. Gain bandwidth 
"  3. Settling time 
"  4. Slew rate 
"  5. Input common-mode range, ICMR 
"  6. Common-mode rejection ratio, CMRR 
"  7. Power-supply rejection ratio, PSRR 
"  8. Output-voltage swing 
"  9. Output resistance 
"  10. Offset 
"  11. Noise 
"  12. Layout area

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