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Modeling Opamp
Penn ESE 568 Fall 2018 - Khanna Penn ESE 568 Fall 2018 - Khanna 2
! Differentiating amplifier
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Ideal Opamp Steps in Designing a CMOS Opamp
! 1) Choosing or creating the basic structure of the
opamp
" This step results in a schematic showing the transistors
and their interconnections
" This diagram does not change throughout the remainder
of the design unless the specifications cannot be met,
then a new or modified structure must be developed
! 2) Selection of the dc currents and transistor sizes
" a.k.a Biasing and sizing
" Most of the effort of design is in this category
" Simulators are used to aid the designer in this phase
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Specifications Specifications
! 1. Open-loop Gain ! 3. Settling time
" Typically an op-amp may have a maximal open-loop gain ! 4. Slew rate
of around 105
V ! dv (t) $
AOL = + out − SR = max # out &
Vin −Vin " dt %
! 2. Gain bandwidth
Penn ESE 568 Fall 2018 - Khanna 13 Penn ESE 568 Fall 2018 - Khanna 14
Specifications Specifications
! 5. Input common-mode range, ICMR ! 6. Common-mode rejection ratio, CMRR
" The input common-mode range is the range of common- " CMRR is a measure of how well the differential amplifier
mode voltages over which the differential amplifier rejects the common-mode input voltage in favor of the
continues to sense and amplify the difference signal with differential-input voltage.
the same gain.
avd
" Typically, the ICMR is defined by the common-mode CMRR =
avc
voltage range over which all MOSFETs remain in the
saturation region. ! 7. Power-supply rejection ratio, PSRR
avd
PSRR+ =
a+
avd
PSRR− =
a−
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Specifications Specifications
! 8. Output-voltage swing ! 8. Output-voltage swing
" Expected output swing " Expected output swing
! 9. Output resistance ! 9. Output resistance
" Resistance seen into the output " Resistance seen into the output
! 10. Offset ! 10. Offset
" Output offset voltage (VOS(out)) " Output offset voltage (VOS(out))
" The output offset voltage is the voltage which appears at the " The output offset voltage is the voltage which appears at the
output of the differential amplifier when the input terminals are output of the differential amplifier when the input terminals are
connected together. connected together.
" Input referred offset voltage (VOS(in) = VOS)
" The input referred offset voltage is equal to the output
offset voltage divided by the differential voltage gain.
" VOS = VOS(out)/AVD
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Opamp Design Output Opamp Design Practical Advice
! 1) The topology ! 1) Decide upon a suitable topology
" The topology should be the one capable of meeting most of the
! 2) The dc currents specifications
Try to avoid “inventing” a new topology but start with an existing
! 3) The W and L values of transistors "
topology
! 4) The values of components ! 2) Determine the type of compensation needed to meet the specifications
" Consider the load and stability requirements
" Use some form of Miller compensation or a self-compensated approach
! I.e Schematic and biasing ! 3) Design dc currents and device sizes for proper dc, ac, and transient
performance
" This begins with hand calculations based upon approximate design
equations.
" Compensation components are also sized in this step of the procedure.
" After each device is sized by hand, a circuit simulator is used to fine tune
the design
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Design Variables
! Specifications:
" 1. Open-loop Gain Basic 2-stage Opamp
" 2. Gain bandwidth
" 3. Settling time
" 4. Slew rate
" 5. Input common-mode range, ICMR
" 6. Common-mode rejection ratio, CMRR
" 7. Power-supply rejection ratio, PSRR
" 8. Output-voltage swing
" 9. Output resistance
" 10. Offset
" 11. Noise
" 12. Layout area
Penn ESE 568 Fall 2018 - Khanna 29 Penn ESE 568 Fall 2018 - Khanna 30
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2-Stage Opamp 2-Stage Opamp
! 2a. Frequency Response – no compensation CC=0 ! 2a. Frequency Response – no compensation CC=0
1 1
p1 = − p2 = −
Ro1C1 Ro2C2
A0
A(s) =
" Two poles: " s %" s %
$1− '$1− '
# p1 &# p2 &
1 1
p1 = − p2 = −
Ro1C1 Ro2C2
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! Red
" Phase at ω0 = -81.3
ο
" PM=98.7
ο
! Blue
" Phase at ω0 = -231
ο
" PM=-50
ο
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Stability vs. Phase Margin Phase Margin
! Find phase at unity-gain
frequency (ω0)
! Add 180o for phase margin
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gm 7CC −g
p2 ≈ − ≈ m7
C1C2 + C1CC + CC C2 C2
gm 7
z1 =
CC
" s%
A0 $1− '
# z2 &
A(s) =
" s %" s %
$1− '$1− '
# p1 &# p2 &
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Transistor for RZ 2-Stage Opamp – Unity Gain Freq
! Equivalent capacitance at node v1
Penn ESE 568 Fall 2018 - Khanna 43 Penn ESE 568 Fall 2018 - Khanna 44
2-Stage Opamp – Unity Gain Freq 2-Stage Opamp – Unity Gain Freq
! Equivalent capacitance at node v1: Ceq = CC (1+ Av2 ) ≈ CC Av2 ! Equivalent capacitance at node v1: Ceq = CC (1+ Av2 ) ≈ CC Av2
v1 " 1 %
Av1 = = −gm1Z out1 = −gm1 $$ rds2 || rds 4 || '
vin # sCeq '&
1 1
Av1 ≅ −gm1 ≅ −gm1
sCeq sCC Av2
vout −gm1 −g
Av (s) = = Av2 Av1 ≅ Av2 = m1
vin sCC Av2 sCC
g m1
Av ( jω 0 ) = 1 for ω 0 =
CC
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2-Stage Opamp 2-Stage Opamp
! 3/4. Settling Time/Slew Rate ! 3/4. Settling Time/Slew Rate
dvout I CC I D5
max
SR ≡ = =
dt max CC CC
Penn ESE 568 Fall 2018 - Khanna 49 Penn ESE 568 Fall 2018 - Khanna 50
dvout I CC I D5
max
SR ≡ = =
dt max CC CC
g m1
vI = Asin(ω t) ω0 =
CC
dvo
= Aω
dt MAX
Penn ESE 568 Fall 2018 - Khanna 51 Penn ESE 568 Fall 2018 - Khanna 52
Unity Gain Freq and Slew Rate Unity Gain Freq and Slew Rate
! Relationship between unity gain frequency and slew ! Relationship between unity gain frequency and slew
rate: rate:
g m1 I D5 I D5 g m1 I D5 I D5
ω0 = SR = SR = ω ω0 = SR = SR = ω
CC CC
g m1 0 CC CC
g m1 0
I D5 I D5
SR = p2 SR = p2
gm1 gm1
gm 7CC −g
p2 ≈ − ≈ m7
C1C2 + C1CC + CC C2 C2
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Design Variables Admin
! Specifications: ! HW 2 and 3 due Su
" 1. Open-loop Gain " Want to make sure every has Cadence set up and running
" 2. Gain bandwidth
" 3. Settling time
" 4. Slew rate
" 5. Input common-mode range, ICMR
" 6. Common-mode rejection ratio, CMRR
" 7. Power-supply rejection ratio, PSRR
" 8. Output-voltage swing
" 9. Output resistance
" 10. Offset
" 11. Noise
" 12. Layout area
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