Professional Documents
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MC80F0504/0604
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http://www.Datasheet4U.com
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Version 1.47
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Published by
FAE Team
©2006 ABOV semiconductor Ltd. All right reserved.
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Additional information of this manual may be served by ABOV semiconductor offices in Korea or Distributors and Representatives.
ABOV semiconductor reserves the right to make changes to any information here in at any time without notice.
The information, diagrams and other data in this manual are correct and reliable; however, ABOV semiconductor is in no way responsible
for any violations of patents or other rights of the third party generated by the use of this manual.
MC80F0504/0604
REVISION HISTORY
VERSION 1.47 (NOV.2011) This book
Logo is changed.
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Add POR characteristic on chapter ‘7.Electrical Characteristics’.
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VERSION 1.44 (FEB.2008)
Repalce ‘TBD’ with real data in ‘7.Electrical Characteristics’.
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Amend the contents of ‘21.Device Configuration Area’ chapter.
VERSION 1.43 (DEC.2007)
Add 20 SSOP package info
VERSION 1.42 (NOV.2007)
Add ‘16 SOP( 153 mil)’ package info
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VERSION 1.41 (APL.2007)
Add TVDD parameter specification and change TPOR in DC Electrical Characteristics.
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Note for configuration option is added and fix some errata.
VERSION 1.4 (MAR.2007)
Add TVDD parameter specification and change TPOR in DC Electrical Characteristics.
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Correct direction symble in Chapter 3. Pin Assignment.(RESET pin as Input, XOUT pin as Input/Output)
Fix some font error in chapter 22. Emulator EVA. Board Setting.
VERSION 1.0 (APR. 2006)
Update Electrical Characteristics
VERSION 0.4 (APR. 2006)
Change Flash Endurance 1000 times to 100 times.
VERSION 0.3 (MAR. 2006)
The company name, MagnaChip Semiconductor Ltd. changed to ABOV Semiconductor Co.,Ltd..
Fix some errata.
VERSION 0.2 (NOV. 2005)
Fix some errata.
VERSION 0.1 (OCT. 2005)
First Edition
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Table of Contents
1. OVERVIEW .........................................................1 13. TIMER/EVENT COUNTER ............................ 47
Description .. .......................................................1 8-bit Timer / Counter Mode ............................. 49
Features .............................................................1 16-bit Timer / Counter Mode ........................... 53
Development Tools ............................................2 8-bit (16-bit) Compare Output .. ....................... 53
Ordering Information ........................................3 8-bit Capture Mode ......................................... 54
2. BLOCK DIAGRAM .............................................4 16-bit Capture Mode ....................................... 57
PWM Mode ..................................................... 58
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3. PIN ASSIGNMENT .............................................5
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14. ANALOG TO DIGITAL CONVERTER ........... 61
4. PACKAGE DRAWING ........................................6
15. BUZZER FUNCTION ..................................... 64
5. PIN FUNCTION .................................................10
16. INTERRUPTS ................................................ 66
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6. PORT STRUCTURES .......................................12
Interrupt Sequence .......................................... 68
7. ELECTRICAL CHARACTERISTICS ................15 BRK Interrupt .................................................. 70
Absolute Maximum Ratings .............................15 Multi Interrupt .................................................. 70
Recommended Operating Conditions ..............15 External Interrupt ............................................. 72
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A/D Converter Characteristics .........................15
DC Electrical Characteristics ...........................16
AC Characteristics ...........................................17
17. POWER SAVING OPERATION ..................... 74
Sleep Mode ..................................................... 74
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Stop Mode ....................................................... 75
Typical Characteristics .....................................18
Stop Mode at Internal RC-Oscillated Watchdog
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10. CLOCK GENERATOR ...................................40 22. EMULATOR EVA. BOARD SETTING .......... 89
Oscillation Circuit ............................................40 A. INSTRUCTION .................................................. ii
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MC80F0504/0604
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 10-BIT A/D CONVERTER
1. OVERVIEW
1.1 Description
The MC80F0504/0604 is advanced CMOS 8-bit microcontroller with 4K bytes of FLASH. This is a powerful microcontrol-
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ler which provides a hig hly flexible and cost effective solution to many embedded control applications. This provides the
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following features : 4K bytes of FLASH (MTP), 256 bytes of RAM, 8/16-bit timer/counter, watchdog timer, on-chip POR,
10-bit A/D converter, buzzer driv ing port, 10-bit PWM output and on-chip os cillator and clock circuitr y. It also has ONP,
noise filter, PFD for improving noise immunity. In addition, the MC80F0504/0604 supports power saving modes to reduce
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power consumption.
This document explains the base MC80F0604, the other’s eliminated functions are same as below table.
Device Name
MC80F0604
FLASH (ROM)
Size
ce. 8 RAM ADC
10 channel
I/O PORT
18 port
Package
Note : The DAA, DAS decimal adjust instructions are not provided in these devices.
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1.2 Features
• 4K Bytes On-chip FLASH (MTP) • Two External Interrupt input ports
- Endurance : 100 times
• On-chip POR (Power on Reset)
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Please contact sales part of abov semiconductor.
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- MS-Windows based assembler
Software - MS-Windows based Debugger
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- HMS800 C compiler
Hardware - CHOICE-Dr.
(Emulator) - CHOICE-Dr. EVA80C0x B/D
- CHPOD80C01D-16PD
Pod Name
FLASH Writer
- CHPOD80C02D-20PD
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- CHOICE - SIGMA I/II (Single writer)
- PGM Plus III (Single writer) PGMplus III ( Single Writer )
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- Standalone GANG4 I/II (Gang writer)
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Choice-Dr. (Emulator)
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Pb free package :
The “P” suffix will be added at the original part number.
For example; MC80F0604B (Normal package), MC80F0604B P (Pb free package)
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2. BLOCK DIAGRAM
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Data
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Memory
Program
RESET System controller Memory
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System 8-bit Basic
Clock Controller Interval Interrupt Controller Data Table
Timer
Timing generator
Clock Generator
Watch-dog
Timer
ce. 8 10-bit
A/D
Converter
8-bit
Timer/
Counter
High
Speed
PWM
Buzzer
Driver
Instruction
Decoder
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VDD
R3 R0 R1
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VSS
Power
Supply
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R06 / AN6
R07 / AN7
PD
3. PIN ASSIGNMENT
MC80F0604B/0604D
20 PDIP
20 SOP
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R06 / AN6 3 18 R01 / AN1
MC80F0604B/D
R07 / AN7 4 17 R00
VDD 5 16 VSS
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R10 / AN0 / AVREF / PWM1O 6 15 RESET / R35
R11 / INT0 7 14 XOUT / R34
R12 / INT1 / BUZO 8 13 XIN / R33
R13 9 12 R32 / AN15
R14 10 11 R31 / AN14
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MC80F0504B/0504D/0504R
16 PDIP
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16 SOP
16 TSSOP
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VDD 5 12 VSS
R10 / AN0 / AVREF / PWM1O 6 11 RESET / R35
PD
4. PACKAGE DRAWING
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1.043
1.010 TYP 0.300
0.270
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MIN 0.015
0.245
MAX 0.180
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0.120
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4
0.01
0.021 . 00 8
0
0.015 0.065 TYP 0.100 0 ~ 15°
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0.050
20 SOP
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F
0.299
0.291
0.419
0.398
PD
0.5118
0.4961
0.0118
0.004
0.104
0.093
0.020 0 ~ 8°
0.042
0.0125
0.0091
0.177
0.169
0.260
0.244
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0.264
0.248
0.002
0.008
0.057
0.013 0 ~ 8°
0.008
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TYP 0.026
0.008
0.004
0.030
0.018
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TYP 0.300
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0.765
0.745 0.260
MIN 0.015
0.240
MAX 0.180
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0.140
0.120
4
0.01
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0.022 08
0.0
0.065 0 ~ 15°
0.015 TYP 0.100
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0.050
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16 SOP
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0.299
0.292
0.416
0.398
PD
0.412
0.402
0.0118
0.004
0.104
0.094
0.019 0 ~ 8°
0.040
0.0125
0.0091
unit: inch
16 SOP (153 mil)
MAX
MIN
0.158
0.149
0.244
0.228
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0.394
0.0039
0.0098
0.385
0.069
0.053
0.019
0.014
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0.032
0.017
0 ~ 8°
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16 TSSOP
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0.177
0.169
0.258
0.246
PD
0.201
0.193
0.002
0.006
0.047MAX
0 ~ 8°
0.012 0.030
0.007 0.026BSC 0.020
5. PIN FUNCTION
VDD: Supply voltage. R1 serves the functions of the various following special
features in Table 5-2
VSS: Circuit ground.
RESET: Reset the MCU.
Port pin Alternate function
XIN: Input to the inverting oscillator amplifier and input to
R10 AN0 ( Analog Input Port 0 )
the internal main clock operating circuit. AVref ( External Analog Reference Pin )
XOUT: Output from the inverting oscillator amplifier. PWM1O ( PWM1 Output )
R11 INT0 ( External Interrupt Input Port 0 )
R00~R07: R0 is an 8-bit , CMOS, bidirectio nal I/O port. R12 INT1 ( External Interrupt Input Port 1 )
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RA pins can be used as outputs or inputs according to “1”
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BUZ ( Buzzer Driving Output Port )
or “0” written the their Port Direction Register(R0IO). R13
R14
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Port pin Alternate function
Table 5-2 R1 Port
R00
R01 AN1 ( Analog Input Port 1 ) R31~R35: R3 is an 5-bit, CMOS, bidirectional I/O port.
R02 AN2 ( Analog Input Port 2 ) R3 pins can be used as outpu ts or inputs according to “1”
R03 AN3 ( Analog Input Port 3 )
R04
R05
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AN4 ( Analog Input Port 4 )
EC0 ( Event Counter Input Source 0 )
AN5 ( Analog Input Port 5 )
or “0” written the their Port Direction Register (R3IO). In
R3 pins, R35 pin can be used as input port only.
R3 serves the functions of the following special features in
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T0O (Timer0 Clock Output ) Table 5-3 .
R06 AN6 ( Analog Input Port 6 )
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R07 AN7 ( Analog Input Port 7 )
Port pin Alternate function
Table 5-1 R0 Port R31 AN14 ( Analog Input Port 14 )
AN15 ( Analog Input Port 15 )
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R32
In addition, R0 serves the functions of the various special R33 XIN ( Oscillation Input )
features in Table 5-1 . R34 XOUT ( Oscillation Output )
R35 RESET ( Reset input port )
R10~R14: R1 is a 5-bit, CMOS, bidirectional I/O port. R1
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pins can be used as output s or inputs according to “1” or Table 5-3 R3 Port
“0” written the their Port Direction Register (R1IO).
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Pin No.
PIN NAME In/Out Function
(20PDIP)
VDD 5 - Supply voltage
VSS 16 - Circuit ground
RESET (R35) 15 I(I) Reset signal input Input only port
XIN (R33) 13 I (I/O) Oscillation Input Normal I/O Port
XOUT (R34) 14 O (I/O) Oscillation Output Normal I/O Port
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R00 17 I/O -
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R01 (AN1) 18 I/O (Input) Analog Input Port 1
R02 (AN2) 19 I/O (Input) Analog Input Port 2
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R03 (AN3) 20 I/O (Input) Analog Input Port 3
R04 (AN4 / EC0) 1 I/O (Input/Input/Input) Analog Input Port 4 / Event Counter Input 0
R05 (AN5 / T0O) 2 I/O (Input/Output) Analog Input Port 5 / Timer0 Output
R06 (AN6) 3 I/O (Input) Analog Input Port 6
R07 (AN7)
R10 (AN0 / AVREF /
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6
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I/O (Input)
I/O (Input/Input/Output)
Normal I/O Ports
Analog Input Port 7
Analog Input Port 0 / Analog Reference / PWM 1
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PWM1O) output
R11 (INT0) 7 I/O (Input) External Interrupt Input 0
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R12 (INT1 / BUZO) 8 I/O (Input/Output) External Interrupt Input 1 / Buzzer Driving Output
R13 9 I/O -
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R14 10 I/O -
R31 (AN14) 11 I/O (Input) Analog Input Port 14
R32 (AN15) 12 I/O (Input) Analog Input Port 15
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6. PORT STRUCTURES
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Data Reg.
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Direction Pin
Reg.
Direction Pin
Reg.
Data Bus VSS
VSS
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MUX
VSS
VSS
RD
Data Bus
MUX
AN[1]
RD
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(ADCM)
EC0
Noise
Filter
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EC0E (PSR0)
VDD
Pull-up
Pull-up Tr. Pull-up
Reg. Pull-up Tr.
Reg.
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Open Drain
Reg. VDD Open Drain
VDD Reg. VDD
VDD
Data Reg.
Data Reg.
F
Direction Pin
Reg. Direction Pin
Reg.
PD
VSS
VSS Data Bus VSS
MUX VSS
RD
Data Bus
MUX
RD Noise
INT0
Filter
AN[15:14]
AN[7:6] INT0E (PSR0)
AN[3:1]
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BUZOE(PSR1.2)
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VSS
VSS VSS
VSS Direction
Direction Reg.
Reg.
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Data Bus
Data Bus MUX
MUX
RD
RD
INT1
Noise
Filter
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RESET(R35)
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Tr. Reg.
Reg. VDD
Open Drain RD
Reg. VDD
VDD Mask only
F
Data Reg.
MUX Data Bus
PWM1O Internal Reset Pin
PD
Pin
PWM1OE(PSR0.6)
VSS Reset Disable VSS
VSS (Configuration option bit)
Direction
Reg.
Data Bus
MUX
RD
AN[0]
ADEN & ADS[3:0]
(ADCM) VDD
ADC Reference
Voltage Input
MUX
AVREFS(PSR1.3)
VDD
VDD
VDD Pull-up
Pull-up Tr.
Reg.
Open Drain
Reg. VDD
XIN VDD
STOP
Data Reg.
VSS
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Reg. / R33
VDD
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VSS
VSS
MAIN
CLOCK
XOUT
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Data Bus MUX
VSS
IN4MCLK RD
IN2MCLK
IN4MCLKXO
IN2MCLKXO
Reg.
XIN
STOP
Open Drain
Reg. VDD
VSS VDD
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fXIN ÷ 16
XOUT VSS
VSS
PD
VSS
Data Bus MUX
RD
System Clock ÷ 4
IN4MCLKXO
IN2MCLKCO
EXRCXO
CLOCK option
(Configuration option bit)
7. ELECTRICAL CHARACTERISTICS
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Maximum current into VDD pin ............................ 100 mA stress rating only and functional operation of the device at any oth-
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er conditions above thos e indicated in the oper ational sections of
Maximum current sunk by (IOL per I/O Pin) .......... 20 mA this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Maximum output current sourced by (IOH per I/O Pin)
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7.2 Recommended Operating Conditions
Specifications
Parameter Symbol Pin Condition Unit
Min. Typ. Max.
VIH1 XIN, RESET 0.8 VDD - VDD
Input High Voltage VIH2 Hysteresis Input1 0.8 VDD - VDD V
VIH3 Normal Input 0.7 VDD - VDD
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VIL1 XIN, RESET 0 - 0.2 VDD
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Input Low Voltage VIL2 Hysteresis Input1 0 - 0.2 VDD V
VIL3 Normal Input 0 - 0.3 VDD
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Output High Voltage VOH All Output Port VDD=5V, IOH=-5mA VDD -1 -- V
Output Low Voltage VOL All Output Port VDD=5V, IOL=10mA - -1 V
Input Pull-up Current IP Normal Input VDD=5V -60 - -150 μA
Input High
Leakage Current
IIH1
IIH2 XIN
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All Pins (except XIN)V DD=5V
VDD=5V
--
-1 2
5
20
μA
μA
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Input Low IIL1 All Pins (except XIN)V DD=5V -5 - - μA
Leakage Current IIL2 XIN VDD=5V -20 -12 - μA
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7.5 AC Characteristics
(TA=-40~85°C, VDD=5V±10%, VSS=0V)
Specifications
Parameter Symbol Pins Unit
Min. Typ. Max.
Operating Frequency fXIN XIN 1- 12 MHz
System Clock Cycle
tSYS - 166 - 5000 nS
Time
Oscillation Stabilizing
tST XIN, XOUT -- 20 mS
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Time (4MHz)
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External Clock Pulse
tCPW XIN 35 - - nS
Width
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External Clock Transi-
tRCP,tFCP XIN -- 20 nS
tion Time
Interrupt Pulse Width tIW INT0, INT1 2 - - tSYS
RESET Input Width tRST RESET 8 - - tSYS
Event Counter Input
Pulse Width
Event Counter Transi-
tECW
tREC,tFEC
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EC0
2
-
-
-
-
20
tSYS
nS
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tion Time
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VDD-0.5V
XIN 0.5V
tRCP tFCP
F
tIW tIW
PD
0.8VDD
INT0, INT1 0.2VDD
tRST
RESET
0.2VDD
tECW tECW
0.8VDD
EC0 0.2VDD
tREC tFEC
Operating Area
fXIN Normal Operation
(MHz)
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Ta=25°C
IDD−VDD
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16
IDD
14 (mA) Ta=25°C
12
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12
10 10
8 8
fXIN=12MHz
4
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4
4MHz
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2 2
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0 0 VDD
VDD
23 4 5 6 (V) 23 45 6 (V)
ISTOP−VDD ISLEEP−VDD
IDD IDD
(μA) Ta=25°C (mA) Ta=25°C
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2 2.0
fXIN = 12MHz
1.5 1.5
F
1 1.0
0.5 0.5
PD
0 VDD 0 VDD
23 45 (V) 23 45 6 (V)
15
TRCWDT = 50uS
10
0 VDD
23 45 6 (V)
15 -15
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-10
10
-5
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5
0 0 VOH
VOL
3.5 4 4.5 5 (V)
0.5 1 1.5 2 (V)
VDD−VIH1
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XIN, RESET Hysteresis input Normal input
VIH1 VIH2 VIH3
fXIN=4MHz (V) fXIN=4kHz (V) fXIN=4kHz
(V)
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Ta=25°C Ta=25°C Ta=25°C
4 4 4
3 3 3
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2 2 2
1 1 1
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3 3 3
2 2 2
1 1 1
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R = 4.7K
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R = 4.7K
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R = 10K
6 6
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5 5 R = 10K
4 4
R = 20K
3 3
R = 20K
1
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R = 30K
2
1
R = 30K
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0 VDD 0 VDD
2.5 3.0 3.5 4.0 4.5 5.0 5.5 (V) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 (V)
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(MHz) (MHz)
CEXT = 20pF CEXT = 30pF
7 Ta = 25°C 7 Ta = 25°C
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6 6
R = 4.7K R = 4.7K
5 5
F
4 4
R = 10K
3 3 R = 10K
PD
R = 20K
2 2 R = 20K
1 R = 30K 1
R = 30K
0 VDD 0 VDD
2.5 3.0 3.5 4.0 4.5 5.0 5.5 (V) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 (V)
Note: The external RC oscillation frequencies shown in Note: There may be the differe nce b etween package
above are provided for design guidance only and not tested types(PDIP, SOP, TSSOP). The user sho uld modify the
or guaranteed. The user needs to take into account that the value of R an d C components to get th e proper frequency
external RC oscillation frequencies generated by the same in exchanging MC80F0104/0204 to MC80F0504/0604 or
circuit design may be not the same. Because there are vari- one package type to another package type.
ations in the resistance and capacitance due to the toler-
ance of external R and C components. T he parasitic
capacitance difference due to the different wiring length
and layout may change the external RC oscillation frequen-
cies.
8. MEMORY ORGANIZATION
The MC80F050 4/0604 has separate address spaces for Data memory can be read and written to up to 256 bytes in-
Program m emory and Data Memor y. 4K by tes p rogram cluding the stack area.
memory can only be read, not written to.
8.1 Registers
This device has six registers that are the Program Counter call is executed or an interrupt is accepted. However, if it
(PC), a Accumulator (A), two index registers (X, Y), the is used in excess of the sta ck area pe rmitted by the data
Stack Pointer (SP), and the Program Status Word (PSW). memory allocating configuration, the us er-processed data
The Program Counter consists of 16-bit register. may be lost.
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The stack can be located at any position within 1C0H to
A ACCUMULATOR 1FFH of the internal data memory. The SP is not initialized
by hardware, requiring to write the ini tial value (the loca-
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X X REGISTER
tion with which the use of the stack starts) by using the ini-
Y Y REGISTER tialization routine. Normally , the initial value of “FF H” is
SP STACK POINTER used.
PCH PCL PROGRAM COUNTER
Stack Address (1C0H ~ 1FFH)
PSW
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PROGRAM STATUS WORD Bit 15
01H
8 7
SP
Bit 0
C0H~FFH
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Hardware fixed
Figure 8-1 Configuration of Registers
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Accumulator: The Accumulator is t he 8-bit general pur-
pose register, used for data operation such as transfer, tem- Note: The Stack Pointer must be initialized by software because
its value is undefined after Reset.
porary saving, and conditional judgement, etc.
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The Accumulator can be used as a 16-bit register with Y Example: To initialize the SP
LDX #0FFH
Register as shown below.
TXSP ; SP ← FFH
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MSB LSB
PSW N V G B H I Z C RESET VALUE: 00H
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CARRY OUT FROM BIT 1 OF
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ADDITION OPERLANDS
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Figure 8-3 PSW (Program Status Word) Register
[Interrupt disable flag I] This flag assigns RAM page for direct addressing mode. In
the direct a ddressing mode, addres sing area is from zero
This f lag enables/di sables al l int errupts except in terrupt
page 00 H to 0FFH when this flag is "0". If it is set to "1",
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caused by Reset or software BRK in struction. All inter-
rupts are disabled when cleared to “0”. This flag immedi-
ately becomes “0” when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.
addre ssing area is assigned 100 H to 1FF H. It is set by
SETG instruction and cleared by CLRG.
[Overflow flag V]
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[Half carry flag H] This flag is set to “1” when an overflow occurs as the result
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of an arithmetic operat ion invol ving signs. An overflow
After operation, this is set when there is a carry from bit 3
occurs when t he resu lt of an ad dition or subt raction ex-
of ALU or there is no borrow from bit 4 of ALU. This bit
ceeds +127(7F H) or -1 28(80 H). The CLRV instruction
can not be set or cleared except CLRV instruction with
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Overflow flag (V). clears the overflow flag. There is no set instruction. When
the BIT instruction is executed, bit 6 of memory is copied
[Break flag B] to this flag.
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01FF Push
PCH 01FF PCH 01FF PCH 01FF PCH
down Push Pop Pop
01FE PCL 01FE PCL 01FE PCL 01FE PCL
down up up
01FD 01FD PSW 01FD 01FD PSW
01FC 01FC 01FC 01FC
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SP before
execution 01FF 01FF 01FD 01FC
SP after
execution 01FD 01FC 01FF 01FF
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At execution At execution
of PUSH instruction of POP instruction
PUSH A (X,Y,PSW) POP A (X,Y,PSW)
01FF
01FE
01FD
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A Push
down
01FF
01FE
01FD
A Pop
up
01C0H
Stack
depth
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01FC 01FC
01FFH
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SP before
execution 01FF 01FE
SP after
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cation in Program Memory. Program Memory area con-
;
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tains the user program FUNC_B: LDA LRG1 2 1
RET
;
;TABLE CALL ADD. AREA
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;
F000H ORG 0FFC0H ;TCALL ADDRESS AREA
DW FUNC_A
DW FUNC_B
MC80F0504/0604, 4K FLASH
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interval: 0 FFFA H and 0FFFB H for Ex ternal Int errupt 1,
FFC0H
TCALL area 0FFFCH and 0FFFDH for External Interrupt 0, etc.
FFDFH
FFE0H Interrupt
Vector Area Any area from 0FF00H to 0FFFFH, if it is not going to be
FFFFH
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CC
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TCALL 9
CD
CE TCALL 8
PCALL Area
CF
(256 Bytes) D0 TCALL 7
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D1
D2 TCALL 6
D3
D4 TCALL 5
D5
D6 TCALL 4
D7
ce. 8 D8
D9
DA
DB
DC
TCALL 3
TCALL 2
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TCALL 1
DD
DE TCALL 0 / BRK *
0FFFFH DF
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NOTE:
* means that the BRK software interrupt is using
same address with TCALL0.
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4F 4A 01001010
35 Reverse
~ ~ 1
~ ~
~
~ ~
~ NEXT PC: 11111111 11010110
0D125H
FH FH DH 6H
0FF00H
0FFFFH 0FFFFH
Example: The usage soft ware example of Vecto r address for MC80F0604.
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DW Noticed ;
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DW Noticed ;
DW Noticed ;
DW INT1 ; Ext. Int.1
DW INT0 ; Ext. Int.0
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DW RESET ; Reset
RAM_Clear0:
LDX #0
ce. 8
;Disable All Interrupt
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LDA #0 ;Page0 RAM Clear(0000h ~ 00BFh)
STA {X}+
CMPX #0C0h
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BNE RAM_Clear0
LDX #0C0h
RAM_Clear1:
LDA #0
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STA {X}+
CMPX #00h
BNE RAM_Clear1
RAM_Clear_Finish:
F
:
:
;Initialize IO
LDM R0, #0 ;Normal Port R0
LDM R0IO,#0FFH ;Normal Port R0 Direction
:
:
PAGE0
More detailed informations of each register are explained
00BFH
in each peripheral section.
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00C0H (When “G-flag=0”,
Control this page0 is selected)
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Registers
00FFH Note: Write only registers can not be accessed by bit manipula-
0100H tion instruction. Do not use read-modify-write instruction. Use byte
manipulation instruction, for example “LDM”.
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Not Available
PAGE1
01BFH
01C0H Example; To write at CKCTLR
LDM CKCTLR,#0AH ;Divide ratio(÷32)
User Memory
or Stack Area
01FFH
(64Bytes)
ce. 8 Stack Area
The stack provides the area where the return a ddress is
an e
Figure 8-8 Data Memory Map saved before a jump is perfo rmed during the processing
routine at the execution of a subrout ine call instruction or
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ory (RAM). RAM pages are selected by RPR (See Figure subroutine return instruction [RET] restores the contents of
8-9 ). the program counter from the stack; executing the interrupt
return instruction [RETI] restores the contents of the pro-
gram counter and flags.
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Control Registers means the value of the SP indicates the stack location
The control registers are us ed by the CPU and Peripheral number for the next save. Refer to Figure 8-4 .
PD
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00C6 R3 port data register R3 R/W - - 0 0 0 0 0 - byte, bit
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00C7 R3 port I/O direction register R3IO W 0 0 0 0 0 0 0 - byte
00C8 Port 0 Open Drain Selection Register R0OD W 0 000 0000 byte
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00C9 Port 1 Open Drain Selection Register R1OD W - - - 0 0000 byte
00CB Port 3 Open Drain Selection Register R3OD W - - - 0 0 0 0 - byte
00D0 Timer 0 mode control register TM0 R/W - - 00 0000 byte, bit
00D1
Timer 0 register
Timer 0 data register
ce. 8 T0
TDR0 W
R 0 000
1 111
0000
1111 byte
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Timer 0 capture data register CDR0 R 0 0 0 0 0000
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00D2 Timer 1 mode control register TM1 R/W 0 000 0000 byte, bit
Timer 1 data register TDR1 W 1 111 1111 byte
00D3
Timer 1 PWM period register T1PPR W 1 111 1111 byte
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00EA Interrupt enable register high IENH R/W 0 0 - ---- 0 byte, bit
00EB Interrupt enable register low IENL R/W 0 - - - 0 0 - 0 byte, bit
00EC Interrupt request register high IRQH R/W 0 0 - ---- 0 byte, bit
00ED Interrupt request register low IRQL R/W 0 - - - 0 0 - 0 byte, bit
00EE Interrupt edge selection register IEDS R/W - - - - 0000 byte, bit
00EF A/D converter mode control register ADCM R/W 0 000 0001 byte, bit
00F0 A/D converter result high register ADCRH R(W) 0 1 0 Undefined byte
00F1 A/D converter result low register ADCRL R Undefined byte
Basic interval timer register BITR R Undefined
00F2 byte
Clock control register CKCTLR W 0 - 01 0111
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00FC Pull-up selection register 0 PU0 W 0 000 0000 byte
00FD Pull-up selection register 1 PU1 W - - - 0 0000 byte
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00FF Pull-up selection register 3 PU3 W - - 0 0 0 0 0 - byte
1.
2.
ce. 8
The ‘byte, bit’ means registers are controlled by both bit and byte manipulation instruction.
Caution) The R/W registers except T1PDR are both can be byte and bit manipulated.
The ‘byte’ means registers are controlled by only byte manipulation instruction. Do not use bit manipulation
an e
instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers,
content of other seven bits are may varied to unwanted value.
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*The mark of ‘-’ means this bit location is reserved.
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F
PD
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0C0H R0 R0 Port Data Register
0C1H R0IO R0 Port Direction Register
0C2H R1 R1 Port Data Register
0C3H R1IO R1 Port Direction Register
0C6H R3 R3 Port Data Register
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0C7H R3IO R3 Port Direction Register
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0C8H R0OD R0 Open Drain Selection Register
0C9H R1OD R1 Open Drain Selection Register
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0CBH R3OD R3 Open Drain Selection Register
0D0H TM0 - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST
T0/TDR0/
0D1H Timer0 Register / Timer0 Data Register / Timer0 Capture Data Register
CDR0
0D2H
0D3H
TM1
TDR1/
T1PPR
POL
ce. 8
16BIT PWM1E CAP1
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0FDH PU1 R1 Pull-up Selection Register
0FFH PU3 R3 Pull-up Selection Register
Caution) The registers of dark-shaded area can not be accessed by bit manipulation instruction such as "SET1, CLR1", but should be
accessed by register operation instruction such as "LDM dp,#imm".
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ce. 8
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F
PD
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2
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~
~ ~
~ data → A
1
8.4.1 Register Addressing 0E550H C5
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Register addressing accesses the A, X, Y, C and PSW. 0E551H 35
MEMORY lower level address and thir d byte (Operand II) becom es
upper level address.
With 3 bytes comm and, it is possible to access to whole
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04
A+35H+C → A memory area.
35
ADC, AND, CMP, CMPX, CMPY, EOR, LDA , LDX,
LDY, OR, SBC, STA, STX, STY
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Example;
0735F0 ADC !0F035H ;A ←ROM[0F035H]
When G-flag is 1, then RAM address is defined by 16-bit
F
~
~ ~
~
1 2 The operation within data memory (RAM)
0F100H E4 ASL, BIT, DEC, INC, LSR, ROL, ROR
0F101H 55
Example; Addressing accesses the address 0135 H regard-
0F102H 35
less of G-flag.
35H data 2
135H data
3 ~
~ ~
~
data → A
~ ~ 2 1 36H → X
~ ~
data+1 → data DB
0F100H 98 1
0F101H 35 address: 0135
0F102H 01
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X indexed direct page (8 bit offset) → dp+X
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8.4.5 Indexed Addressing This address value is the second byte (Operand) of com-
mand plus the data of X-register. And it assigns the mem-
X indexed direct page (no offset) → {X} ory in Direct page.
In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA , LDY , OR, SBC, STA
ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA
Example; X=15H, G=1
ce. 8 STY, XMA, ASL, DEC, INC, LSR, ROL, ROR
Example; G=0, X=0F5H
an e
C645 LDA 45H+X
D4 LDA {X} ;ACC←RAM[X].
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3
~ ~ data → A
~ ~ ~
~ ~
~ 2 data → A
1
0E550H 1
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C6
0E550H D4 0E551H 45
45H+0F5H=13AH
F
In this mode, a address i s specified within direct page by Y indexed direct page (8 bit offset) → dp+Y
the X register and the content of X is increased by 1. This address value is the second byte (Operand) of com-
LDA, STA mand plus the data of Y-register, which assigns Memory in
Direct page.
Example; G=0, X=35H
DB LDA {X}+ This is same with above (2). Use Y register instead of X.
35H 05
0F100H D5 36H E0
0F101H 00
1
~ ~ 2 0E005H
0F102H FA 0FA00H+55H=0FA55H ~ ~
0E005H data 1 25 + X(10) = 35H
~
~ ~
~ 2
~
~ ~
~
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0FA55H data data → A
3
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0FA00H 16
25
3 A + data + C → A
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8.4.6 Indirect Addressing
Y indexed indirect → [dp]+Y
Direct page indirect → [dp]
Processes memo ry data as Data, assign ed by th e d ata
Assigns data address to use for accomplishing command
35H 0A 25H 05
36H E3 26H E0
~ ~ 2 2
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~ ~ ~
~ ~
~
1 1
0E30AH NEXT jump to 0E015H data 0E005H + Y(10)
address 0E30AH = 0E015H
~
~ ~
~ ~ ~
~ ~
F
0FA00H 3F 0FA00H 17
PD
35 25
3
A + data + C → A
PROGRAM MEMORY
0E025H 25
0E026H E7
~
~ ~
~
2
jump to
address 0E30AH
1 0E725H NEXT
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~
~ ~
~
0FA00H 1F
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25
E0
ce. 8
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F
PD
9. I/O PORTS
The MC80F0504/0604 has three ports (R0, R1 and R3). its initial status is input.
These ports pins may be multip lexed with an alternat e
function for the peripheral features on the device. All port
can drive maximum 20mA of high current in output low
WRITE “55H” TO PORT R0 DIRECTION REGISTER
state, so it can directly drive LED device.
0C0H R0 data 0 1 0 1 0 1 0 1 BIT
All p ins h ave dat a directi on regist ers wh ich can define 76 54 32 1 0
0C1H R0 direction
these ports as output or i nput. A “1” in the port direction
0C2H R1 data
register configure the co rresponding po rt pi n as ou tput.
0C3H R1 direction I O I O I O I O PORT
Conversely, write “0” to the corresponding bit to specify it
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76 54 32 10
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as input pin. For example, to use the even numbered bit of
I: INPUT PORT
R0 as out put port s and the odd numbered bits as inp ut O: OUTPUT PORT
ports, write “55H” to address 0C1H (R0 port direction reg-
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ister) during initial setting as shown in Figure 9-1 . Figure 9-1 Example of port I/O assignment
All th e p ort direction regi sters in t he MC80F050 4/0604
have 0 written to them by reset function. On the other hand,
R0 R07 R06 R05 R04 R03 R02 R01 R00 PSR0 - PWM1OE - EC0E - - INT1E INT0E
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0: R04
1: EC0
Port Direction
PD
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by sett ing A DCM(00EF H) re gister to en able the co rre- EC0 (Event counter input 0)
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R05 AN5 (ADC Input channel 5)
sponding peripheral operation and select operation mode.
T0O (Timer output 0)
R06 AN6 (ADC Input channel 6)
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R07 AN7 (ADC Input channel 7)
can be used to open drain output port by setting the corre- R10 AN0 (ADC input channel 0)
AVREF (Analog reference voltage)
sponding bit of the open drain selection register 1 (R1OD).
PWM1O (PWM 1 output)
In addition, Port R1 is m ultiplexed with various alternate
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1: EC0
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Port Direction
0: Input Port / PWM Selection
1: Output 0: R10
1: PWM1O
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R1 Pull-up ADDRESS: 0FDH
Selection Register RESET VALUE: ---0 0000B
ADDRESS: 0F9H
PU1 - - - RESET VALUE: ---- 0000B
ce. 8
Pull-up Resister Selection
0: Disable
1: Enable
Port / TO Selection
0: R05
1: Timer0 output
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R1 Open Drain ADDRESS: 0C9H R12/BUZO Selection
Selection Register RESET VALUE: ---0 0000B 0: R12 port (Turn off buzzer)
1: BUZO port (Turn on buzzer)
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R1OD - - -
R10 / AVREF Selection
0: R10 port
Open Drain Resister Selection
1: AVREF port
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0: Disable
1: Enable
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R3 Direction Register ADDRESS: 0C7H
In ad dition, Port R3 is multi plexed with alternate func- RESET VALUE: ---0 000-B
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tions. R31 and R32 can be used as ADC input channel 14 R3IO - - - -
and 15 by setting ADCM to enable ADC and select chan-
nel 14 and 15.
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Port Direction
0: Input
1: Output
Port Pin Alternate Function
R3 Pull-up ADDRESS: 0FFH
R31 AN14 (ADC input channel 14) Selection Register RESET VALUE: --00 000-B
R32 AN15 (ADC input channel 15)
ce. 8
R33, R3 4 an d R35 is mu ltiplexed wi th X IN, X OUT, and
RESET pin. These pins can be used as general I/O pins by
PU3 -- -
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There are no requirements on the duty cycle of the external
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clock signal, since the input tothe internal clocking circuit-
STOP
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INOSC
INOSC SLEEP
Main OSC
Stop
XIN
XOUT
OSC
Circuit
ONP
Circuitce. 8 fXIN
MUX
fEX
Clock Pulse
Generator
(÷2)
Internal
system clock
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Int OSC INCLK
Circuit
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INOSC
PRESCALER
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INOSC (IN4MCLK/IN2MCLK/ PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12
IN4MCLKXO/IN2MCLKXO)
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fEX (Hz) PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12
F
Frequency 4M 2M 1M 500K 250K 125K 62.5K 31.25K 15.63K 7.183K 3.906K 1.953K 976
4M
period 250n 500n 1u 2u 4u 8u 16u 32u 64u 128u 256u 512u 1.024m
PD
n addition, see Figure 10-3 for the layout of the crystal. omitted for more cost saving. However, the characteristics
of external R only oscillation are more variable than exter-
nal RC oscillation.
Vdd
XOUT
REXT XIN
XIN
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fXIN÷4 XOUT
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Figure 10-3 Layout of Oscillator PCB circuit
Figure 10-5 RC Oscillator Connections
To drive the device from an external cl ock source, X out
should be left unconnected while Xin is driven as shown in
ce. 8
Figure 10-4 . There are no requirements on the duty cycle
of the external clock signal, since the input to the internal
clocking circuitry is through a divide-by-two flip-flop, but
minimum and maximum high and low times specified on
VDD
REXT XIN
an e
the data sheet must be observed.
CINT ≈ 6pF
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Oscillation circuit is designed to be used either with a ce-
ramic resonator or crystal oscillator. Since each crystal and
fXIN÷4 XOUT
ceramic resonator have their own characteristics, the user
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Source
Vss
The oscillator frequency, divided by 4, is out put from the
Xout pin, and can be used for test purpose or to synchro-
PD
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count overflow from FFH to 00H, this overflow causes the dress 0F2H is read as a BITR, and written to CKCTLR.
interrupt to be generated.
The Basic Interval Timer is controlled by the clock control Note: All control bits of Basic interval timer are in CKCTLR reg-
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ister which is located at same address of BITR (address ECH). Ad-
register (CKCTLR) shown in Figure 11-2. If the RCWDT dress E CH is read as BITR, written to CK CTLR. T herefore, the
bit is set to “1”, the clock source of the BITR is changed to CKCTLR can not be accessed by bit manipulation instruction.
the internal RC oscillation.
When write "1" to bit BTCL of CKCTLR, BITR register is
ce. 8
cleared to "0" and restart to count-up. The bit BTCL be-
comes "0" after one machine cycle by hardware.
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Internal RC OSC
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RCWDT
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÷8
8-bit up-counter Basic Interval
÷16 1 source
clock overflow Timer Interrupt
÷32 BITIF
BITR
Prescaler
÷64
XIN PIN 0
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÷128 MUX
[0F2H]
÷256 To Watchdog timer (WDTCK)
÷512 clear
÷1024
F
[0F2H] CKCTLR
Basic Interval Timer Read
clock control register
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110 fXIN÷512 16.384
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111 fXIN÷1024 32.768
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7 6 5 4 3 2 1 0 ADDRESS: 0F2H
CKCTLR ADRST - RCWDT WDTONBTCL
BTCL BTS2 BTS1 BTS0 INITIAL VALUE: 0-01 0111B
7 6 5 4 3 2 1 0
ADDRESS: 0F2H
BITR BTCL
INITIAL VALUE: Undefined
8-BIT FREE-RUN BINARY COUNTER
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The watchdog timer has two types of clock source. The
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first ty pe is an on -chip RC oscil lator which does no t re- The RC-WDT oscillation period is vary with temperature,
quire any external components. This RC oscillator is sepa- VDD and p rocess variati ons from part t o part (approxi -
rate from the ex ternal oscillator of t he X IN pin. It means
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mately, 33~100uS). The following equation shows the
that the wat chdog timer will run, even if the clock on the
RCWDT oscillated watchdog timer time-out.
XIN pin of the device has been stopped, for example, by en-
tering the STOP mode . The other type is a prescaled sys- TRCWDT=CLKRCWDT×28×WDTR + (CLKRCWDT×28)/2
tem clock.
where, CLKRCWDT = 33~100uS
ce. 8
The wat chdog timer con sists of 7 -bit bin ary co unter and
the watchdog timer data register. When the value of 7-bit
binary counter is equal to the lower 7 bits of W DTR, the
In addition, this watchdog timer can be used as a simple 7-
bit timer by interrupt WDTIF. The in terval of watchdog
an e
interrupt request flag i s g enerated. This can be u sed as timer interrupt is decided by Basic Interval Timer. Interval
Watchdog timer interrupt or reset the C PU in accordance equation is as below.
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with the bit WDTON. TWDT = (WDTR+1) × Interval of BIT
ing Basic Interval Timer, after the bit WDTON set to "1", maximum
error of timer is depend on prescaler ratio of Basic Interval Timer.
The 7-bit binary cou nter is clear ed by setting WDT CL(bit7 of
WDTR) and the WDTC L is cleared automatically after 1 mach ine
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cycle.
F
clear
Watchdog clear
PD
“0”
to reset CPU
comparator “1”
enable
WDTON in CKCTLR [0F2H]
WDTCL 7-bit compare data
7 WDTIF
Watchdog Timer interrupt
Watchdog Timer Control er outpu t will becom e active at the rising overflow from
the binary counters unless the binary counter is cleared. At
Figure 12 -2 shows the watchdog timer control register.
this time, when WDTON=1, a reset is gen erated, which
The watchdog timer is automatically disabled after reset.
drives the RESET pin to low to reset the internal hardware.
The CPU malfunction is detected during setting of the de- When WDTON=0, a watchdog timer interrupt (WDTIF) is
tection time, selecting of output, and clearing of the binary generated. The WDTON bit is in register CLKCTLR.
counter. Clearing the binary counter is repeated within the
The watchdog timer temporarily stops counting in the
detection time.
STOP mode, and when the STOP mode is released, it au-
If the malfunction occurs for any cause, the watchdog tim- tomatically restarts (continues counting).
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W WWW W W W W
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7 6 5 4 3 2 1 0
ADDRESS: 0F4H
WDTR WDTCL
INITIAL VALUE: 0111 1111B
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Clear count flag
0: Free-run count
1: When the WDTCL is set to “1”, binary counter
is cleared to “0”. And the WDTCL becomes “0” automatically
after one machine cycle. Counter count up again.
ce. 8
Figure 12-2 WDTR: Watchdog Timer Control Register
Example: Sets the watchdog timer detection time to 1 sec. at 4.194304MHz
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LDM CKCTLR,#3FH ;Select 1/1024 clock source, WDTON ← 1, Clear Counter
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LDM WDTR,#08FH
Within WDT :
detection time :
:
LDM WDTR,#08FH ;Clear counter
:
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Within WDT :
:
detection time :
LDM WDTR,#08FH ;Clear counter
F
PD
Source clock
BIT overflow
Binary-counter 1 2 3 0 1 2 3 0
Counter Counter
Clear Clear
WDTR n 3
Match
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Detect
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WDTIF interrupt
WDTR ← “1000_0011B”
WDT reset reset
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Figure 12-3 Watchdog timer Timing
If the watchdog timer output becomes active, a reset is gen- The main clock oscillator al so turns on w hen a watchdog
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ternal clock input. Since a leas t c lock consists of 2 and "Compare output" function. It has six operating modes: "8-
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most clock consists of 204 8 oscill ator perio ds, the count bit timer/counter", "16-bit timer/counter", "8-bit capture",
rate is 1/2 to 1/2048 of the oscillator frequency. "16-bit capture", "8-bit co mpare output", and "10-bit
PWM" which are sel ected by b it in Timer m ode register
In the “counter” function, the re gister is increased in re-
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TM0 and TM1 as shown in Table 13-1, Figure 13-1 .
sponse to a 0-to-1 (rising edge) transition at its correspond-
T0CK T1CK
16BIT
0
CAP0
0
CAP1
0
PWM1E
0
ce. 8
[2:0]
XXX
[1:0]
XX
PWM1O
0
TIMER 0
8-bit Timer
TIMER 1
8-bit Timer
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0 0 1 0 111 XX 0 8-bit Event counter 8-bit Capture
0 1 0 0 XXX XX 1 8-bit Capture (internal clock) 8-bit Compare Output
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T0CK1 TM0.3 001: 8-bit Timer, Clock source is fXIN ÷ 4
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T0CK0 TM0.2 010: 8-bit Timer, Clock source is fXIN ÷ 8
011: 8-bit Timer, Clock source is fXIN ÷ 32
100: 8-bit Timer, Clock source is fXIN ÷ 128
101: 8-bit Timer, Clock source is fXIN ÷ 512
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110: 8-bit Timer, Clock source is fXIN ÷ 2048
111: EC0 (External clock)
T0CN TM0.1 0: Timer count pause
1: Timer count start
T0ST TM0.0 0: When cleared, stop the counting.
1: Enable PWM
CAP1 TM1.4 0: Timer/Counter mode
1: Capture mode selection flag
T1CK1 TM1.3 00: 8-bit Timer, Clock source is fXIN
F
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7 6 5 4 3 2 1 0
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ADDRESS: 0D0H
TM0 - - CAP0 T0CK2 T0CK1
BTCL T0CK0 T0CN T0ST INITIAL VALUE: --00 0000B
-- 0 X X X X X
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X means don’t care
7 6 5 4 3 2 1 0
ADDRESS: 0D2H
TM1 POL 16BIT PWM1E CAP1 T1CK1
BTCL T1CK0 T1CN T1ST INITIAL VALUE: 00H
X 0 0 0 X X X X
T0ST
÷2 000
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0: Stop
÷4
001 1: Clear and start
÷8
010 T0 (8-bit)
Prescaler
÷ 32 clear
011
XIN PIN
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÷ 128
100 TIMER 0
÷ 512 T0CN T0IF
101 INTERRUPT
÷ 2048 Comparator
110
TIMER 0
F
R05 / T0O
PD
T1CK[1:0]
T1ST
11 0: Stop
÷1 1: Clear and start
00
÷2 T1 (8-bit)
01 clear
÷8
10
TIMER 1
T1CN T1IF
MUX INTERRUPT
Comparator
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Example 2: by pin EC0 input, but Timer 1 can not.
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Timer0 = 8-bit event counter mode
Timer1 = 0.5ms 8-bit timer mode at 4MHz 13.1.1 8-bit Timer Mode
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LDM TDR0,#249 In the timer mode, the internal clock is used for counting
LDM TDR1,#249 up. Thus, you can think of it as counting internal clock in-
LDM TM0,#0001_1111B put. The contents of TDRn are compared with the contents
LDM TM1,#0000_1011B
SET1 T0E of up-coun ter, Tn. If match is fou nd, a t imer n interrupt
(TnIF) is generat ed and the up-coun ter is cleared to 0.
SET1
EI
T1E
ce. 8
These timers have each 8-bit count register and data regis-
ter. The count register is increased by every internal or ex-
Counting up is resumed after the up-counter is cleared.
As the value of TDRn is changeable by software, time in-
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terval is set as you want.
ternal clock input. The internal clock has a prescaler divide
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Start count
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Source clock
~
~
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~
~
TDR1 n
~
~
F
Match Counter
T1IF interrupt Detect Clear
~
~
PD
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TDR0 MATCH
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(TDR0 = T0) Count Pulse
Period
7C 7C
7B
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7A
nt
8 μs
ou
-c
up
~~
~~
6
5
4
3
0
ce. 8
0
1
2
TIME
an e
Interrupt period
= 8 μs x (124+1)
Timer 0 (T0IF)
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Interrupt Occur interrupt Occur interrupt Occur interrupt
13.1.2 8-bit Event Counter Mode In order to use event counter function, the bit 4 of the Port
Selection Register PSR0(address 0F8 H) is required to be
In this mode, counting up is started by an external trigger.
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set to “1”.
This trigger means rising edge of the EC0 pin input. Source
clock is used as an internal clock selected with timer mode After reset, the value of timer data register TDRn is initial-
register TM0. The contents of timer data register TDR0 are ized to "0", The interval period of Timer is calculated as
compared with the c ontents of the up-counter T1. I f a below equation.
F
f XIN
start and count up continuously by every rising edge of the
EC0 pin input. The maxim um frequency applied to the
EC0 pin is fXIN/2 [Hz].
Start count
~
~
Up-counter 0 1 2 n-1 n 0 1 2
~
~
~
~
TDR0 n
~
~
T0IF interrupt
~
~
TDR1
disable enable
~~
stop
t
oun
l -c
up
ia
~~
TIME
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Timer 1 (T1IF)
Interrupt
Occur interrupt Occur interrupt
T1ST
Start & Stop
T1CN
Control count
ce. 8 T1ST = 0
T1ST = 1
T1CN = 1
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T1CN = 0
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7 6 5 4 3 2 1 0
ADDRESS: 0D0H
TM0 - - CAP0 T0CK2 T0CK1
BTCL T0CK0 T0CN T0ST INITIAL VALUE: --00 0000B
- - 0X X X X X
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X means don’t care
76 543 210
ADDRESS: 0D2H
TM1
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POL 16BIT PWM1E CAP1 T1CK1
BTCL T1CK0 T1CN T1ST INITIAL VALUE: 00H
X1 00 1 1 X X
T0CK[2:0]
EC0 PIN
EDGE
DETECTOR ce. 8111
an e
T0ST
÷2 000 0: Stop
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÷4 1: Clear and start
XIN PIN 001
÷8 T1 + T0
010
Prescaler
÷ 32 (16-bit) clear
011
÷ 128
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100
÷ 512 T0CN TIMER 0
101 T0IF
INTERRUPT
÷ 2048 Comparator
110 (Not Timer 1 interrupt)
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l
This timer interrupt in capture mode is very useful when
edge selection register IEDS. Refer to “16.4 External Inter-
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the pulse width of captured signal is more wider than the
rupt” on page 72 . In ad dition, the transition at INT n pin
maximum period of Timer.
generate an interrupt.
For example, in Figure 13-10 , the pulse width of captured
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signal i s wider th an th e tim er data v alue (FF H) over 2 Note: The CDRn and TDRn are in same address.In the capture
times. When external interrupt is occurred, the captu red mode, reading operation is read the CDRn, not TDRn becau se
value (13H) is more little than wanted value. It can be ob- path is opened to the CDRn.
ce. 8
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F
PD
7 6 5 4 3 2 1 0
ADDRESS: 0D0H
TM0 - - CAP0 T0CK2 T0CK1
BTCL T0CK0 T0CN T0ST INITIAL VALUE: --00 0000B
- - 1X X X X X
765 432 10
ADDRESS: 0D2H
TM1 POL 16BIT PWM1E CAP1 T1CK1
BTCL T1CK0 T1CN T1ST INITIAL VALUE: 00H
l
X 0 0 1 X X X X
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X means don’t care
T0CK[2:0]
Edge
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Detector
÷ 32
011
÷ 128 clear
100
an e
÷ 512 T0CN
101 Capture
÷ 2048
110
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CDR0 (8-bit)
MUX
IEDS[1:0]
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“01”
“10” INT0
INT0 PIN INT0IF
INTERRUPT
T1CK[1:0]
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“11”
T1ST
11 0: Stop
÷1 1: Clear and start
00
F
÷2 T1 (8-bit)
01
÷8
10 clear
PD
T1CN
MUX Capture
CDR1 (8-bit)
IEDS[3:2]
“01”
“10” INT1
INT1 PIN INT1IF
INTERRUPT
“11”
~~
~~
9
n t
8
ou
-c
7
up
6
5
4
3
~~
l
1
ia
0
TIME
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Ext. INT0 Pin
Interrupt Request
( INT0IF )
Interrupt Request
( INT0IF )
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Interrupt Request
( INT0IF )
Interrupt Interval Period=01H+FFH +01H+FFH +01H+13H=214H
Interrupt Request
( T0IF )
FFH FFH
T0
13H
00H 00H
7 6 5 4 3 2 1 0
ADDRESS: 0D0H
TM0 - - CAP0 T0CK2 T0CK1
BTCL T0CK0 T0CN T0ST INITIAL VALUE: --00 0000B
-- 1X X X X X
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765 432 10
ADDRESS: 0D2H
TM1 POL 16BIT PWM1E CAP1 T1CK1
BTCL T1CK0 T1CN T1ST INITIAL VALUE: 00H
X 1 0 1 1 1 X X
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X means don’t care
T0CK[2:0]
Edge
Detector
XIN PIN
÷2
÷4
ce. 8 000
001
T0ST
0: Stop
1: Clear and start
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÷8 TDR1 + TDR0
010 (16-bit)
Prescaler
÷ 32
011
clear
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÷ 128
100
÷ 512 T0CN
101 Capture
÷ 2048
110
CDR1 + CDR0
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MUX (16-bit)
IEDS[1:0] Higher byte Lower byte
CAPTURE DATA
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“01”
“10” INT0
INT0 PIN INT0IF
INTERRUPT
“11”
F
PD
l
(bit3,2 o f T1 PWM Hi gh Register) and the du ty of th e
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PWM output is determined by the T1PDR (T1 PWM Duty 7-bit 31.2kHz 7.81kHz 3.90kHz
Register) and T3PWHR[1:0] (bit1,0 of T 1 PWM High
Register). Table 13-2 PWM Frequency vs. Resolution at 4MHz
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The user writes the lower 8-bit period value to the T1PPR The bit POL of TM1 decides the polarity of duty cycle.
and th e hi gher 2-b it peri od valu e to the T1PWHR[3:2].
An d writ es d u ty valu e to t h e T1PDR and the If the duty value is set same to the period value, the PWM
T1PWHR[1:0] same way. output is determined by the bit POL (1: High, 0: Low). And
ce. 8
The T1PDR is configured as a double buffering for glitch-
less PWM output. In Figure 13-12 , the duty data is trans-
ferred from the master to the slave when the pe riod da ta
if the duty value is set to "00H", the PWM output is deter-
mined by the bit POL (1: Low, 0: High).
It can be changed duty value when the PWM output. How-
an e
matched to the counted value. (i.e. at the beginning of next ever the changed duty value is output after the current pe-
duty cycle) riod is over. And it can be maintained the duty value at
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present output when changed only period value shown as
PW M1 Per iod = [PWM1HR[3:2]T1PPR + 1] X
Figure 1 3-14 . A s it were, t he ab solute d uty ti me i s no t
Source Clock changed in varying frequency. But the changed period val-
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the timer clock firstly, and then set period and duty register value.
If user writes register values while timer is in operation, these reg-
The relation of frequency and resolution is in inverse pro-
ister could be set with certain values.
portion. Table 13-2 shows the relation of PWM frequency
vs. resolution. Ex) Sample Program @4MHz 2uS
F
If it needed more higher frequency of PWM, it should be LDM TM1,#1010_1000b ; Set Clock & PWM1E
LDM T1PPR,#199 ; Period :400uS=2uSX(199+1)
PD
- - -- W W W W
7 654 321 0
ADDRESS: 0D5H
T1PWHR - - - - BTCL T1PWHR2 T1PWHR1 T1PWHR0
T1PWHR3
INITIAL VALUE: ---- 0000B
l
- - - - X X X X Bit Manipulation Not Available
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X:The value "0" or "1" corresponding your operation.
Period High Duty High
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W W W W W W W W
7 6 5 4 3 2 1 0
ADDRESS: 0D3H
T1PPR BTCL INITIAL VALUE: 0FFH
R/W
7
R/W R/W
654
ce. 8 R/W R/W R/W
3210
R/W R/W
ADDRESS: 0D4H
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T1PDR BTCL INITIAL VALUE: 00H
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T1PWHR[3:2]
T1ST [PSR0.6]
[T0CK]
0 : Stop
1 : Clear and Start
Comparator S Q
11
÷1 Clear
00
F Prescaler
÷2
R R10 / PWM1O PIN
XIN PIN 01 2-bit T1(8-bit)
÷8
10 POL
PD
T1CN Comparator
MUX
Slave T1PDR(8-bit)
T1PWHR[1:0]
Master T1PDR(8-bit)
~
~
~
~
Source
clock
~
~ ~
~ ~
~
T1 00 01 02 03 04 7E 7F 80 3FF 00 01 02
~
~ ~
~
PWM1E
~
~
T1ST
~
~
T1CN
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PWM1O
[POL=1] ~
~
~
~
~
~
PWM1O
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[POL=0]
~
~
T1CK[1:0] = 00 ( XIN )
T1PWHR = 0CH
ce. 8
Period T1PWHR3 T1PWHR2 T1PPR (8-bit)
an e
1 1 FFH
T1PPR = FFH
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Duty T1PWHR1 T1PWHR0 T1PDR (8-bit)
T1PDR = 7FH
00 7FH
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T1CK[1:0] = 10 ( 1us )
PWM1HR = 00H
T1PPR = 0DH
F
Source
clock
T1 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 00 01 02 03 04 05 06 07 08 09 00 01 02 03 04
PWM1O
POL=1
Period Cycle [ (1+0Dh) x 2uS = 28uS, 35.5KHz ] Period Cycle [ (1+09h) x 2uS = 20uS, 50KHz ]
Figure 13-14 Example of Changing the PWM1 Period in Absolute Duty Cycle (@4MHz)
l
analog reference AVref is selected, the analog input chan-
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The block diagram of the A/D module is shown in Figure
nel 0 (AN0) should not be selected to use. Because this pin 14-3 . The A/D status bit ADSF is set automatically when
is used to an analog reference of A/D converter. A/D conversion is completed, cleared when A/D c onver-
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The A/D module has three registers which are the control sion is in process. The co nversion time takes 13 t imes of
register ADCM and A/D result register ADCRH and AD- convers ion source clock. The conversion source clock
CRL. The ADCRH[7:6] is used as ADC clock source se- should selected for the con version time bein g more th an
lection bits too. The register ADCM, shown in Figure 14- 25μs.
4 , controls the operation of the A/D converter module. The
ce. 8
port pins can be configured as analog inputs or digital I/O.
It is selected for the corresponding channel to be converted
A/D Converter Cautions
(1) Input range of AN0 ~ AN7, AN14 and AN15
an e
by setting ADS[3:0]. The A/ D port is set to analog input
The input voltage of A/D input pins should be within the
port by ADEN and ADS[3:0] regardless of port I/O direc-
specification range. In particular, if a voltage above V DD
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tion register. The port unselected by ADS[3:0] operates as
(or AVref) or below VSS is input (even if within the abso-
normal port.
lute maximum rating range), the conversion value for that
channel can not be determinate. The conversion values of
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paid to noise on pins VDD (or AVref) and analog input pins
A/D Input Channel Select (AN0 ~ AN7, AN14, AN15). Since the effect increases in
proportion to the output impedance of the analog input
F
Analog
NOP Input AN0~AN7
AN14, AN15
0~1000pF
User Selectable
ADSF = 1
NO
YES
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noise. Therefore, avoid applying pulses to pins adjacent to
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AVREFS (PSR1.3)
ADEN
VDD
0
an e
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AN0 / AVREF
AN1
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Successive
ADC
MUX Approximation ADCIF INTERRUPT
Sample & Hold
Circuit
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AN7
AN14
F
ADC8 0 1
AN15
PD
ADS[3:0] (ADCM[5:2])
98 98 32
ADCR (10-bit)
10-bit ADCR 10-bit ADCR
0 0
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Analog input channel select
0000: Channel 0 (AN0) 0110: Channel 6 (AN6)
0001: Channel 1 (AN1) 0111: Channel 7 (AN7)
0010: Channel 2 (AN2) 1000 ~ 1101: Not available
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0011: Channel 3 (AN3) 1110: Channel 14 (AN14)
0100: Channel 4 (AN4) 1111: Channel 15 (AN15)
0101: Channel 5 (AN5)
7 6 5 4 3 2 1 0
ADCRL BTCL ADDRESS: 0F1H
INITIAL VALUE: Undefined
PD
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. fXIN: Oscillator frequency
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Divide Ratio: Prescaler divide ratio by BUCK[1:0]
Example: 5kHz output at 4MHz. BUR: Lower 6-bit value of BUZR. Buzzer period value.
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LDM PSR1,#XXXX_X1XXB
control register BUZR. The bit 0 to bit 5 of BUZR deter-
X means don’t care mine output frequency for buzzer driving.
÷8
÷ 16
ce. 8
00 6-BIT BINARY
COUNTER
Prescaler
01 MUX
an e
XIN PIN ÷ 32
10 0
R12/BUZO PIN
÷ 64 F/F 1
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11
MUX Comparator
2
Compare data
BUZO
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[0E0H]
ADDRESS: 0E0H
RESET VALUE: 0FFH ADDRESS: 0F9H
W W W W W W W W RESET VALUE: ---- 0000B
The 6-bit counter is cleared and starts the counting by writ- When main-frequency is 4MHz, buzzer frequency is
ing signal at BUZR register. It is incremental from 00H un- shown as below Table 15-1.
til it matches 6-bit BUR value.
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04 50.000 25.000 12.500 6.250 24 6.757 3.378 1.689 0.845
ia
05 41.667 20.833 10.417 5.208 25 6.579 3.289 1.645 0.822
06 35.714 17.857 8.929 4.464 26 6.410 3.205 1.603 0.801
07 31.250 15.625 7.813 3.906 27 6.250 3.125 1.563 0.781
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08 27.778 13.889 6.944 3.472 28 6.098 3.049 1.524 0.762
09 25.000 12.500 6.250 3.125 29 5.952 2.976 1.488 0.744
0A 22.727 11.364 5.682 2.841 2A 5.814 2.907 1.453 0.727
0B 20.833 10.417 5.208 2.604 2B 5.682 2.841 1.420 0.710
0C
0D
0E
0F
19.231
17.857
16.667
15.625
9.615
8.929
8.333
7.813
ce. 8
4.808
4.464
4.167
3.906
2.404
2.232
2.083
1.953
2C
2D
2E
2F
5.556
5.435
5.319
5.208
2.778
2.717
2.660
2.604
1.389
1.359
1.330
1.302
0.694
0.679
0.665
0.651
an e
10 14.706 7.353 3.676 1.838 30 5.102 2.551 1.276 0.638
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11 13.889 6.944 3.472 1.736 31 5.000 2.500 1.250 0.625
12 13.158 6.579 3.289 1.645 32 4.902 2.451 1.225 0.613
13 12.500 6.250 3.125 1.563 33 4.808 2.404 1.202 0.601
14 11.905 5.952 2.976 1.488 34 4.717 2.358 1.179 0.590
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16. INTERRUPTS
TheMC80F0504/0604 interrupt circuits consist of Inter- interrupt was transition-activated.
rupt enable register (IENH, IENL), Interrupt request flags The Timer 0 and Timer 1 Interrupts are generated by T0IF,
of IRQH, IRQL, Priority circuit, a nd Master enable flag T1IF and T1IF which is set by a match in their respective
(“I” flag of PS W). Fifteen interrupt sources are pro vided. timer/counter register.
The configuration o f interrupt circu it is shown i n Figure
16-1 and interrupt priority is shown in Table 16-1. The Basic Interval Timer Interrupt is generated by BITIF
which is set by an overflow in the timer register.
The External Interrupts INT0 and INT1 each can be transi-
tion-activ ated (1-to -0 or 0-to-1 transitio n) by selecti on The AD converter Interrupt is generated by ADCIF which
IEDS register. is set by finishing the analog to digital conversion.
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The flags that a ctually genera te th ese in terrupts ar e b it The Wat chdog timer is gen erated by WDTIF and WTI F
INT0IF and INT1IF in register IRQH. When an external which is set by a match in Watchdog timer register.
interrupt is generated, the generated fl ag is cleared by the
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hardware when the service routine is vectored to only if the
IRQH
ce. 8 [0EAH]
To CPU
Timer 0 T0IF
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I-flag
Interrupt Master
IRQL Enable Flag
[0EDH]
Timer 1 T1IF Interrupt
F
Vector
Address
PD
Generator
BIT BITIF
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composed of interrupt enable flags of each interrupt source
ia
and these flags determines whether an interrupt will be ac- Table 16-1 Interrupt Priority
cepted or not. When enable flag is “0”, a corresponding in-
terrupt source is prohibited. Note that PSW contains also a
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master enable bit, I-fl ag, which disables all interrupts at
once.
IENH
R/W
INT0E
MSB
R/W
INT1E ce. 8
- - - - -
R/W
T0E
LSB
ADDRESS: 0EAH
INITIAL VALUE: 0000 0000B
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Timer/Counter 0 interrupt enable flag
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R/W R/W R/W - R/W
ADDRESS: 0EDH
IRQL T1IF - - - ADCIF WDTIF - BITIF
INITIAL VALUE: 0--- 00-0B
MSB LSB
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Basic Interval Timer interrupt request flag
System clock
Instruction Fetch
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Data Bus Not used PCH PCL PSW V.L. ADL ADH OP code
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Internal Read
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Internal Write
ce. 8
V.L. and V.H. are vector addresses.
ADL and ADH are start addresses of interrupt service routine as vector contents.
Figure 16-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction
an e
A interrupt request is not accepte d until the I-flag is set to
“1” even if a requested interrupt has higher priori ty than
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Basic Interval Timer
Vector Table Address Entry Address
that of the current interrupt being serviced.
012H
When nested interrupt service is required, the I-flag should
0FFE0H
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0E312H 0EH
0FFE1H 0E3H 2EH
be se t to “1” by “E I” ins truction in the int errupt service
0E313H
program. In this case, acceptabl e interrupt sources are se-
lectively enabled by the individual interrupt enable flags.
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interrupt processing
Note: The MC80F0504 and HM S87C1102A is very
similar in function, but the interrupt processing meth- RETI ;RETURN
od is different. When replacing the HMS87C1102A to
MC80F0504, clearing interrupt request flag should
be added.
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General-purpose register save/restore using push andpop instruc-
tions;
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16.2 BRK Interrupt
Software interrupt can be invok ed by BRK instructio n,
which has the lowest priority order.
ce. 8
Interrupt vector address of BRK is shared with the vector
of TCALL 0 (Refer to Program Memory Section). W hen
BRK interrupt is generated, B-flag of PSW is set to distin- B-FLAG
=0
an e
guish BRK from TCALL 0.
=1
BRK or
Each processing step is determined by B-flag as shown in TCALL0
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BRK TCALL0
Figure 16-5 . INTERRUPT ROUTINE
ROUTINE
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RETI RET
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multaneously, th e request of higher priority level is ser- possible. Generally when an interrupt is acc epted, the I-
viced. If requests of the interrupt are received at the same flag is cleared to disable any further interrupt. But as user
time simu ltaneously, an internal polling sequence deter- sets I-flag in interrupt routine, some further interrupt can
mines by hardware which requ est is serviced. However, be serviced even if certain interrupt is in progress.
Main Program
service TIMER 1
service
INT0
service
enable INT0
disable other
EI
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Occur Occur In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
ia
TIMER1 interrupt INT0
Because of re-setting the interrupt enable registers IENH,IENL
and master enable “EI” in the TIMER1 routine.
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enable INT0
enable other
PUSH Y
LDM IENH,#80H ;Enable INT0 only LDM IENL,#0FFH
LDM IENL,#0 ;Disable other int. POP Y
EI ;Enable Interrupt POP X
: POP A
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: RETI
F
PD
01
INT0 pin 10 INT0IF INT0 INTERRUPT
11
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01
INT1 pin 10 INT1IF INT1 INTERRUPT
11
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2 2
ce. 8
[0EEH]
IEDS
Edge selection
Register
an e
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Figure 16-7 External Interrupt Block Diagram
INT0 an d IN T1 are multiplexed wi th g eneral I/ O po rts Response Time
(R11, R12). To use as an external in terrupt pin, the bit of
The INT0 and INT1 edge are latched into INT0IF and
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;
;**** Set port as an external interrupt port external interrupt request and the beginning of execution
LDM PSR0,#0000_0011B of the first instruction of the service routine.
PD
;
;**** Set Falling-edge Detection Figure 16-8 shows interrupt response timings.
LDM IEDS,#0000_0101B
:
MSB LSB
- - - - W W W W
ADDRESS: 0EEH
IEDS - - - -I IED1H
BTCL IED1L IED0H ED0L INITIAL VALUE: ---- 0000B
INT1 INT0
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11: Both (Rising & Falling)
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- W - W - - W W
ADDRESS: 0F8H
PSR0 - PWM1O - EC0E BTCL
- - INT1E INT0E INITIAL VALUE: -0-0 --00B
MSB LSB
0: R10 0: R11
1: PWM1O
0: R04
ce. 8 1: INT0
0: R12
1: INT1
an e
1: EC0
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Oscillation continues and peripherals are operate normally SLEEP mode.
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but CPU sto ps. Movement of all peri pherals is shown in
Table 17-1. SLEEP mode is entered by setting the SS CR
register to “0Fh”. It is released by Reset or interrupt. To be
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W W W W W W W W
7 6 5 4 3 2 1 0
SSCR
ce. 8 ADDRESS: 0F5H
INITIAL VALUE: 0000 0000B
NOTE : To get into STOP mode, SSCR must be set to 5AH just before STOP instruction execution.
At STOP mode, Stop & Sleep Control Register (SSCR) value is cleared automatically when released.
To get into SLEEP mode, SSCR must be set to 0FH.
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F
Release the SLEEP mode stabilizing time is required to normal operation. Figure 17-
The exit from SLEEP mode is hardware reset or all inter- 3 sh ows the timing d iagram. When released from the
rupts. Reset re-defines all the Control registers but does not SLEEP mode, the Basic inter val tim er is activated on
change the on-chip RAM. Interrupts allow both on-chip wake-up. It is increased from 00 H unti l FF H. The count
RAM and Control registers to retain their values. overflow is set to start normal operation. Therefore, before
SLEEP instruction, user must be set its relevant prescaler
If I-flag = 1, the normal interrupt response takes place. If I-
divide ratio to have long enough time (more than 20msec).
flag = 0, the chip will resu me execution starting with the
This guarantees that oscillator has started and stabilized.
instruction following the SLEEP in struction. It wi ll not
By interrupts, exit from SLEEP m ode is shown in Figure
vector to interrupt service routine. (refer to Figure 17-4 )
17-2 . By reset, exit from SLEEP mode is shown in Figure
When exit from SLEEP mode by reset, enough oscillation 17-3 .
Oscillator
~ ~
~
~ ~
~
(XIN pin)
~
Internal Clock
~
~
~ ~
~ ~
External Interrupt
~
~
SLEEP Instruction
Executed
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Normal Operation SLEEP Operation Normal Operation
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Figure 17-2 SLEEP Mode Release Timing by External Interrupt
ce. 8
~
~
Oscillator
an e
(XIN pin)
~
~
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CPU
Clock
~
~
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~
~
~
RESET
Internal
~
~
RESET
~
~
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The reset should not be activated before VDD is restored to pin interface (depending on the external circuitry and pro-
its normal operat ing level, and must be held active long gram) is not directly determined by the hardware operation
enough to allow the oscillator to restart and stabilize. of the STOP feat ure. This p oint sho uld be li ttle current
flows when the input level is stable at the pow er voltage
Note: After STOP instruction, at least two or more NOP instruc- level (VDD/VSS); however, when the input level gets high-
tion should be written. er than the power voltage level (by approximately 0.3 to
Ex) LDM CKCTLR,#0FH ;more than 20ms 0.5V), a current begins to flow. Therefore, if cutting off the
LDM SSCR,#5AH
output transistor at an I/O port puts the pin signal into the
STOP
NOP ;for stabilization time high-impedance state, a current flow across the ports input
NOP ;for stabilization time transistor, requiring to fi x the level by pull-up or ot her
means.
ia l
In the STOP operation, the dissipation of the power asso-
ciated with the oscillator and the internal hardware is low-
ered; however, the power dissipation associated with the
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Peripheral STOP Mode SLEEP Mode
CPU Stop Stop
RAM Retain Retain
Basic Interval Timer
Watchdog Timer
ce. 8 Halted
Stop (Only operates in RC-WDT mode)
Operates Continuously
Operates Continuously
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Halted (Only when the event counter mode
Timer/Counter Operates Continuously
is enabled, timer operates normally)
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Release the STOP mode When exit from Stop mode by external interrupt, enough
The source for exit from STOP mode is hardware reset, ex- oscillation stabilizing time is required to normal operation.
ternal interr upt, Timer(EC0), Watch Timer, WDT. Reset Figure 17-5 shows th e timing di agram. When released
re-defines all the Control registers but does not change the from the Stop mode, the Basic interval timer is activated on
on-chip RA M. Ex ternal in terrupts al low bo th o n-chip wake-up. It is increased from 00 H unti l FF H. The count
RAM and Control registers to retain their values. overflow is set to start normal operation. Therefore, before
STOP instruction, user must be set its relevant prescaler di-
If I-flag = 1, the normal interrupt response takes place. If I-
vide ratio to have long enough time (more t han 20msec).
flag = 0, the chip will resu me execution starting with the
This guarantees that oscillator has started and stabilized.
instruction following the STOP instruction. It will not vec-
tor to interrupt service routine. (refer to Figure 17-4 ) By reset, exit from Stop mode is shown in Figure 17-6 .
STOP
INSTRUCTION
STOP Mode
Interrupt Request
l
Corresponding Interrupt =0
IENH or IENL ?
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Enable Bit (IENH, IENL)
=1
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Master Interrupt =0
Enable Bit PSW[2] I-FLAG
=1
ce. 8
Next
Interrupt Service Routine
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INSTRUCTION
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.
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Oscillator
~ ~
~
(XIN pin)
~
~
~
~
~
Internal Clock
F
~
~
~
~
External Interrupt
PD
~
~
STOP Instruction
Executed
~ ~
~
~ ~
~
Clear
Normal Operation Stop Operation Stabilization Time Normal Operation
tST > 20ms
by software
STOP Mode
~
~
Oscillator
(XI pin)
~
~
~ ~
~ ~
Internal
Clock
~ ~
~
~
~
~
RESET
l
Internal
~
~
ia
RESET
~
~
STOP Instruction Execution
Stabilization Time
Time can not be control by software tST = 65.5mS @4MHz
com Tr
Figure 17-6 Timing of STOP Mode Release by Reset
ce. 8
In the Internal RC-Oscillated Watchdog Timer mode, the
on-chip oscillator is stopped. But internal RC oscillation
circuit is oscillated in th is mo de. The on- chip RAM and
fines all the Control registers but does not change the on-
chip RAM. Ext ernal interrupts allow bo th on-chip RAM
and Control registers to retain their values.
an e
Control registers are held. The port pins out the values held
If I-flag = 1, the normal in terrupt response takes place. In
by their respective port data register, port direction re gis-
this case, if the bit WDTON of CKCTLR is set to "0" and
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ters.
the bit WDTE of IENH is set to "1", the device will execute
The Internal RC-Oscillated Watchdog Timer mode is acti- the watchdog timer interrupt service routine(Figure 8-6 ).
vated by execution of STOP instruction after setting the bit However, if the bit WDTON of CKCTLR is set to "1", the
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RCWDT of CKCTLR to "1". (This register should be writ- device will generate the internal Reset signal and execute
ten by byte operation. If this register is set by bit manipu- the reset processing(Figure 17 -8 ). If I-flag = 0 , the chip
lation instruction, for example "set1" or "clr1" instruction, will resume execution starting with the instruction follow-
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it may be undesired operation) ing the STOP instruction. It will not vector to interrupt ser-
vice routine.(refer to Figure 17-4 )
When exi t from St op mod e at Intern al RC-Oscillated
Note: Caution: After STOP instruction, at least two or more NOP
F
LDM CKCTLR,#0010_1110B
LDM SSCR,#0101_1010B Internal RC-Oscillated Watchdog Timer m ode, the basic
STOP interval timer is activated on wake-up. It is increased from
NOP ;for stabilization time 00H until FFH. The count overflow is set to start normal op-
NOP ;for stabilization time
eration. Therefore, before STOP instruction, user must be
set its relevant prescaler divide ratio to have long enough
time (m ore than 20msec). This guarantees that oscill ator
The exit from Internal RC-Oscillated Watchdog Timer has started and stabilized. By reset, exit from internal RC-
mode is hardware reset o r external interrupt or watchdog Oscillated Watchdog Timer mode is shown in Figure 17-8
timer interrupt (at RC-watchdog timer mode). Reset re-de- .
~
~
Oscillator
(XIN pin)
~
~
~
~
Internal
RC Clock
~
~
Internal
Clock
~
~
External
l
~
~
Interrupt
ia ~
~
( or WDT Interrupt )
STOP Instruction Execution Clear Basic Interval Timer
com Tr ~
~
BIT
N-2 N-1 N N+1 N+2 00 01 FE FF 00 00
Counter
~
~
Normal Operation STOP mode Stabilization Time Normal Operation
at RC-WDT Mode tST > 20mS
ce. 8
Figure 17-7 Stop Mode Release at Internal RC-WDT Mode by External Interrupt or WDT Interrupt
an e
RCWDT Mode
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~
~
Oscillator
(XIN pin)
~
~
~
~
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Internal
RC Clock
~
~
Internal
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Clock
~
~
RESET
~
~
~
~
RESET by WDT
F
Internal
~
~
RESET
~
~
Stabilization Time
Time can not be control by software tST = 65.5mS @4MHz
VDD
INPUT PIN
INPUT PIN VDD VDD
internal
pull-up i=0
O
VDD
OPEN
l
O
ia
i
i
Very weak current flows
com Tr
VDD
GND
X i=0
X
GND
OFF ON OFF
ON
OFF
O OFF i ON i=0
i
F
ON
X X O
PD
OFF
O In the left case, Tr. base current flows from port to GND.
To avoid power consumption, there should be low output
to the port .
O port puts the pin signal into the high-impedance state, a current
Note: In the STOP operation, the power dissipation associated flow across the ports input transistor, requiring it to fix the level by
with the oscillator and the inter nal hardware is lowered; however, pull-up or other means.
the power dissipation associated with the pin interface (depending
on the external circuitry and program) is not directly determined by
It should be set properly in order that current flow through
the hardware operation of the STOP feature. This point should be
little current flows when the input le vel is stable at the power volt- port doesn't exist.
age level (VDD/VSS); however, when the input level becomes high- First consider the port setting to input mode. Be sure that
er than the power voltage level (by approximately 0.3V), a current
begins to flow. Therefore, if cutting off the output transistor at an I/
there is no current flow after considering its relationship
with external circuit. In input mode, the pin impedance
viewing from external MCU i s very high that the current output mode considering there is no current flow. The port
doesn’t flow. setting to High or Low is decided by considering its rela-
tionship with external circuit. For example, if there is ex-
But input voltage level should be V SS or VDD. Be careful
ternal pull-up resistor then it is set to ou tput mode, i.e. to
that if unspecified voltage, i. e. if uncertain voltage le vel
High, and if there is external pull-down register, it is set to
(not VSS or VDD) is applied to input pin, there can be little
low.
current (max. 1mA at around 2V) flow.
If it is not appropriate to set as an input mode, then set to
ia l
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ce. 8
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F
PD
18. RESET
The MC80F0504/0604 supports various kinds of reset as • Watchdog Timer Timeout Reset
below. • Power-Fail Detection (PFD) Reset
RESET
Noise Canceller
l
On-chip POR
ia
(Power-On Reset)
Internal
Address Fail reset S Q
com Tr
RESET
Overflow
R
PFD
(Power-Fail Detection)
WDT
(WDT Timeout Reset) ce. 8 Clear
BIT
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Figure 18-1 RESET Block Diagram
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The on-chip POR circuit holds down the device in RESET uration Area(20FFH) in the Flash programming. When the
until V DD has reached a high enough level for proper op- device starts normal operation, its operating parmeters
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eration. It will eliminate external components such as reset (voltage, frequency, temperature...etc) must be met.
IC or external resistor and capacitor for external reset cir-
.Table 18-1 shows on-chip hardware initialization by reset
cuit. In addition that the RESET pin can be used to normal
action.
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VCC
10kΩ
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Figure 18-1 Simple External Reset Circuit
ia
~ 1 2 3 4 5 6 7
~
Oscillator
com Tr
(XIN pin)
~
~
RESET
ce. 8
~
~
ADDRESS
? ? ? ? FFFE FFFF Start
BUS
~
~ ~
~
DATA
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? ? ? ? FE ADL ADH OP
BUS
~
~
MAIN PROGRAM
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Stabilization Time Reset Process Step
tST =65.5mS at 4MHz
1
tST = x 256
fXIN ÷1024
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by checking code access of abnormal and unwished ad- address fail reset is occurred. Please refer to Figure 11-2
dress caused by erroneous program code itself or external for setting address fail option.
noise, which could not be returned to normal operation and
would become malfunction state. If the CPU tries to fetch
F
PD
l
7 6 5 4 3 2 1 0
ia
PFDR - - - - - ADDRESS: 0F7H
PFDEN PFDM PFDS
INITIAL VALUE: ---- -000B
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0: Normal operate
1: Set to “1” if power fail is detected
* Cautions :
ce. 8
Be sure to set bits 3 through 7 to “0”.
PFD Enable Bit
0: Power fail detection disable
1: Power fail detection enable
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RESET VECTOR
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YES
PFDS =1
NO
RAM Clear
F
Skip the
PD
Function
Execution
VDD
VPFDMAX
VPFDMIN
65.5mS
Internal
RESET
VDD VPFDMAX
When PFDM = 1 VPFDMIN
Internal 65.5mS
l
t < 65.5mS
RESET
ia
VDD
VPFDMAX
VPFDMIN
com Tr
65.5mS
Internal
RESET
ce. 8
Figure 19-3 Power Fail Processor Situations (at 4MHz operation)
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F
PD
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The ONP function is like below.
ia
- Recovery the oscillation wave crushed or loss caused
XIN OFP
1
com Tr
XIN_NF
Mux 0
HF Noise CLK
HF Noise Canceller 0S
Internal Changer FINTERNAL
Observer OSC 1 S
en
ce. 8 INT_CLK
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LF Noise
CLK_CHG
ONP Observer ONP
OFP
en
IN4(2)MCLK(XO)
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en
o/f
CK
OFP
PS10
ONPb = 0 (8-Bit counter)
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LF_on = 1
IN_CLK = 0
INT_CLK 8 periods PS10(INT_CLK/512) 256 periods
High Frq. Noise (250ns × 8 =2us) (250ns × 512 × 256 =33 ms)
~
~
F
XIN
~
~
~
~
Oscillation Fail
XIN_NF
~
~
INT_CLK reset
~
~
~
~
~
~
INT_CLK
~
~ ~
~
OFP_EN
CHG_END
~
~ ~
~
CLK_CHG
Clock Change Start(XIN to INT_CLK) Clock Change End(INT_CLK to XIN))
fINTERNAL
~
~
~
Figure 20-1 Block Diagram of ONP & OFP and Respective Wave Forms
l
tem clock sour ce in timi ng insensitive appli cations. The XOUT pin can be used as R33 and R34 I/O ports.
ia
“IN4MCLK(XO)”, “IN 2MCLK(XO)” bit of the Device
Configuration Area enables the function to operate the de-
com Tr
ce. 8
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F
PD
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7 6 5 4 3 2 1 0
ONP OFP LOCK POR R35EN CLK2 CLK1 CLK0 ADDRESS: 20FFH
Configuration Option Bits
INITIAL VALUE: 00H
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Oscillation configuration
000 : IN4MCLK (Internal 4MHz Oscillation & R33/R34 Enable)
001 : IN2MCLK (Internal 2MHz Oscillation & R33/R34 Enable)
010 : EXRC (External R/RC Oscillation & R34 Enable)
011 : X-tal (Crystal or Resonator Oscillation)
100 : IN4MCLKXO (internal 4MHz Oscillation & R33 Enable
& XOUT = fSYS ÷ 4)
POR Use
0 : Disable POR Reset
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Security Bit
0 : Enable reading User Code
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OFP use
0 : Disable OFP (Clock Changer)
1 : Enable OFP (Clock Changer)
F
ONP disable
0 : Enable ONP (Enable OFP, Internal 4MHz/2MHz oscillation)
1 : Disable ONP (Disable OFP, Internal 4MHz/2MHz oscillation)
PD
These various options shown in Figure 21-1 can be select- SIGMA or GANG4) software after selecting device name.
ed by checking optio n field listed in wr iter (PG M Plu s,
l
6
com Tr
ia J_USER
ce. 8
NC 1 2 NC
VDD 3 4 VDD
GND 5 6 GND
R00 7 8 R10
R01 9 10 R11
R02 11 12 R12
an e R03
R04
R05
13
15
17
14
16
18
R13
R14
R15
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R06 19 20 R16
R07 21 22 R17
GND 23 24 GND
1
R20 25 26 R30
R21 27 28 R31
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R22 29 30 R32
22. EMULATOR EVA. BOARD SETTING
R23 31 32 R33/XIN
R24 33 34 R34/XOUT
R25 35 36 R35/RST
R26 37 38 R36
5
R27 39 40 R37
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GND
NC
NC
NC
NC
41
43
45
47
49
42
44
46
48
50
GND
NC
NC
NC
NC
F
4
MC80F0504/0604
1 - This connector is only used for a device under 32 PIN. For the MC80F0504/0504
Device select switch Low pin .
l
Low Pin : For the MC80F0504/0604.
ia
High Pin
com Tr
These switches select the AVDD source for
ON
high pin devices and should be set to use
1 OFF Eva. VDD.
2
Use Eva. VDD
ce. 8
AVDD select switch to Eva. VDD.
ON & OFF : Use Eva. VDD
Normally OFF.
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EVA. chip can be reset by external user tar-
3 get board.
ON : Reset is available by either user target
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SW2 3 This switch select the /Reset source.
system board or Emulator RESET switch.
OFF : Reset the MCU by Emulator RESET
switch. Does not work from user target
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board.
Normally OFF.
MCU XOUT pin is disconnected internally
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4 Normally MDS.
SW3 1 This switch select Eva. B/D Power supply
source.
USER USER
l
SW5 OFF ON
4 ON & OFF : R34 Port selected.
ia
OFF & ON : XOUT selected.
Select R34 port Select XOUT
com Tr
These switches select the R35 or XOUT
This switch select the Normal I/O port (off)
ON OFF
5 or /Reset select (on).
6 OFF ON ON & OFF : R35 Port selected.
OFF & ON : /Reset selected.
7 -
ce. 8
Select R35 port Select /Reset
l ia
com Tr
ce. 8
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F
PD
A. INSTRUCTION
Terminology Description
A Accumulator
X X - register
Y Y - register
PSW Program Status Word
l
#imm 8-bit Immediate data
ia
dp Direct Page Offset Address
!abs Absolute Address
com Tr
[] Indirect expression
{} Register Indirect expression
{ }+ Register Indirect expression, after that, Register auto-increment
.bit Bit Position
A.bit
dp.bit
M.bit
ce. 8
Bit Position of Accumulator
Bit Position of Direct Page Memory
Bit Position of Memory Data (000H~0FFFH)
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rel Relative Addressing Data
upage U-page (0FF00H~0FFFFH) Offset Address
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0
Upper Nibble Expression in Opcode
x
Bit Position
1
y
Bit Position
− Subtraction
× Multiplication
F
/ Division
() Contents Expression
PD
∧ AND
∨ OR
⊕ Exclusive OR
~N OT
← Assignment / Transfer / Shift Left
→ Shift Right
↔ Exchange
= Equal
≠ Not Equal
LOW 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111
HIGH 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
SET1 BBS BBS ADC ADC ADC ADC ASL ASL TCALL SETA1 BIT POP PUSH
000 - BRK
dp.bit A.bit,rel dp.bit,rel #imm dp dp+X !abs A dp 0 .bit dp A A
SBC SBC SBC SBC ROL ROL TCALL CLRA1 COM POP PUSH BRA
001 CLRC “ “ “
#imm dp dp+X !abs A dp 2 .bit dp X X rel
CMP CMP CMP CMP LSR LSR TCALL NOT1 TST POP PUSH PCALL
010 CLRG “ “ “
#imm dp dp+X !abs A dp 4 M.bit dp Y Y Upage
OR OR OR OR ROR ROR TCALL OR1 CMPX POP PUSH
011 DI “““ RET
#imm dp dp+X !abs A dp 6 OR1B dp PSW PSW
l
AND AND AND AND INC INC TCALL AND1 CMPY CBNE INC
ia
100 CLRV “ “ “ TXSP
#imm dp dp+X !abs A dp 8 AND1B dp dp+X X
EOR EOR EOR EOR DEC DEC TCALL EOR1 DBNE XMA DEC
101 SETC “““ TSPX
#imm dp dp+X !abs A dp 10 EOR1B dp dp+X X
com Tr
LDA LDA LDA LDA LDY TCALL LDC LDX LDX DAS
110 SETG “ “ “ TXA XCN
#imm dp dp+X !abs dp 12 LDCB dp dp+Y (N/A)
LDM STA STA STA STY TCALL STC STX STX
111 EI “““ TAX XAX STOP
dp,#imm dp dp+X !abs dp 14 M.bit dp dp+Y
LOW 10000
HIGH
000
10
BPL
10001
11
CLR1
10010
12
BBC
10011
13
BBC
ce. 8
10100
14
ADC
10101
15
ADC
10110
16
ADC
10111
17
ADC
11000
18
ASL
11001
19
ASL
11010
1A
TCALL
11011
1B
JMP
11100
1C
BIT
11101
1D
ADDW
11110
1E
LDX
11111
1F
JMP
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rel dp.bit A.bit,rel dp.bit,rel {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 1 !abs !abs dp #imm [!abs]
BVC SBC SBC SBC SBC ROL ROL TCALL CALL TEST SUBW LDY JMP
001 “““
rel {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 3 !abs !abs dp #imm [dp]
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BCC CMP CMP CMP CMP LSR LSR TCALL TCLR1 CMPW CMPX CALL
010 “““ MUL
rel {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 5 !abs dp #imm [dp]
BNE OR OR OR OR ROR ROR TCALL DBNE CMPX LDYA CMPY
011 “““ RETI
rel {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 7 Y !abs dp #imm
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BMI AND AND AND AND INC INC TCALL CMPY INCW INC
100 “““ DIV TAY
rel {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 9 !abs dp Y
BVS EOR EOR EOR EOR DEC DEC TCALL XMA XMA DECW DEC
101 “““ TYA
rel {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 11 {X} dp dp Y
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BCS LDA LDA LDA LDA LDY LDY TCALL LDA LDX STYA DAA
110 “““ XAY
rel {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 13 {X}+ !abs dp (N/A)
BEQ STA STA STA STA STY STY TCALL STA STX CBNE
111 “““ XYX NOP
rel {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 15 {X}+ !abs dp
F
PD
l
6 ADC [ dp + X ] 16 2 6
ia
7 ADC [ dp ] + Y 17 2 6
8A DC { X } 14 1 3
9 AND #imm 84 2 2
com Tr
10 AND dp 85 2 3
11 AND dp + X 86 2 4
12 AND !abs 87 3 4 Logical AND N-----Z-
13 AND !abs + Y 95 3 5 A← (A)∧(M)
14
15
16
AND [ dp + X ]
AND [ dp ] + Y
AND { X }
96
97
94
ce. 8
2
2
1
6
6
3
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17 ASL A 08 1 2 Arithmetic shift left
18 ASL dp 09 2 4 C 7 6 5 4 3 2 1 0 N-----ZC
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19 ASL dp + X 19 2 5
“0”
20 ASL !abs 18 3 5
21 CMP #imm 44 2 2
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22 CMP dp 45 2 3
23 CMP dp + X 46 2 4
24 CMP !abs 47 3 4 Compare accumulator contents with memory contents
N-----ZC
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29 CMPX #imm 5E 2 2
Compare X contents with memory contents
30 CMPX dp 6C 2 3 N-----ZC
PD
(X)-(M)
31 CMPX !abs 7C 3 4
32 CMPY #imm 7E 2 2
Compare Y contents with memory contents
33 CMPY dp 8C 2 3 N-----ZC
(Y)-(M)
34 CMPY !abs 9C 3 4
35 COM dp 2C 2 4 1’S Complement : ( dp ) ← ~( dp ) N-----Z-
36 DAA - - - Unsupported -
37 DAS - - - Unsupported -
38 DEC A A8 1 2
39 DEC dp A9 2 4
40 DEC dp + X B9 2 5 Decrement
N-----Z-
41 DEC !abs B8 3 5 M← (M)-1
42 DEC X AF 1 2
43 DEC Y BE 1 2
44 DIV 9B 1 12 Divide : YA / X Q: A, R: Y NV--H-Z-
l
54 INC dp 89 2 4
ia
55 INC dp + X 99 2 5 Increment
N-----Z-
56 INC !abs 98 3 5 M← (M)+1
com Tr
57 INC X 8F 1 2
58 INC Y 9E 1 2
59 LSR A 48 1 2 Logical shift right
60 LSR dp 49 2 4 7 6 5 4 3 2 1 0 C
N-----ZC
61 LSR dp + X 59 2 5
62
63
LSR !abs
MUL
58
5B
ce. 8
3
1
5
9
“0”
Multiply : YA ← Y × A N-----Z-
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64 OR #imm 64 2 2
65 OR dp 65 2 3
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66 OR dp + X 66 2 4
67 OR !abs 67 3 4 Logical OR
N-----Z-
68 OR !abs + Y 75 3 5 A ← (A)∨(M)
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69 OR [ dp + X ] 76 2 6
70 OR [ dp ] + Y 77 2 6
71 OR { X } 74 1 3
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78 ROR dp + X 79 2 5 N-----ZC
79 ROR !abs 78 3 5
80 SBC #imm 24 2 2
81 SBC dp 25 2 3
82 SBC dp + X 26 2 4
83 SBC !abs 27 3 4 Subtract with carry
NV--HZC
84 SBC !abs + Y 35 3 5 A ← ( A ) - ( M ) - ~( C )
85 SBC [ dp + X ] 36 2 6
86 SBC [ dp ] + Y 37 2 6
87 SBC { X } 34 1 3
l
8L DA { X } D4 1 3
ia
9 LDA { X }+ DB 1 4 X- register auto-increment : A ← ( M ) , X ← X + 1
10 LDM dp,#imm E4 3 5 Load memory with immediate data : ( M ) ← imm --------
11 LDX #imm 1E 2 2
com Tr
12 LDX dp CC 2 3 Load X-register
N-----Z-
13 LDX dp + Y CD 2 4 X ←(M)
14 LDX !abs DC 3 4
15 LDY #imm 3E 2 2
16
17
18
LDY dp
LDY dp + X
LDY !abs
C9
D9
D8
ce. 8
2
2
3
3
4
4
Load Y-register
Y←(M)
N-----Z-
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19 STA dp E5 2 4
20 STA dp + X E6 2 5
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21 STA !abs E7 3 5
Store accumulator contents in memory
22 STA !abs + Y F5 3 6
(M)←A --------
23 STA [ dp + X ] F6 2 7
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24 STA [ dp ] + Y F7 2 7
25 STA { X } F4 1 4
26 STA { X }+ FB 1 4 X- register auto-increment : ( M ) ← A, X ← X + 1
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27 STX dp EC 2 4
Store X-register contents in memory
28 STX dp + Y ED 2 5 --------
(M)← X
29 STX !abs FC 3 5
30 STY dp E9 2 4
F
16-BIT Operation
OP BYTE CYCLE FLAG
NO. MNEMONIC OPERATION NVGBHIZC
CODE NO NO
1 ADDW dp 1D 2 5 16-Bits add without carry NV--H-ZC
YA ← ( YA ) + ( dp +1 ) ( dp )
l
5L DYA dp 7D 2 5 N-----Z-
YA ← ( dp +1 ) ( dp )
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Store YA
6S TYA dp DD 2 5 --------
( dp +1 ) ( dp ) ← YA
com Tr
16-Bits substact without carry
7S UBW dp 3D 2 5 NV--H-ZC
YA ← ( YA ) - ( dp +1) ( dp)
Bit Manipulation
OP BYTE CYCLE FLAG
NO. MNEMONIC OPERATION
1
2
AND1 M.bit
AND1B M.bit
CODE
8B
8B
ce. 8
NO
3
3
NO
4
4
Bit AND C-flag : C ← ( C ) ∧ ( M .bit )
Bit AND C-flag and NOT : C ← ( C ) ∧ ~( M .bit )
NVGBHIZC
-------C
-------C
an e
3 BIT dp 0C 2 4 Bit test A with memory :
Z ← ( A ) ∧ ( M ) , N ← ( M7 ) , V ← ( M 6 ) MM----Z-
4 BIT !abs 1C 3 5
.nu at
5 CLR1 dp.bit y1 2 4 Clear bit : ( M.bit ) ← “0” --------
6 CLRA1 A.bit 2B 2 2 Clear A bit : ( A.bit )← “0” --------
7 CLRC 20 1 2 Clear C-flag : C ← “0” -------0
ww re
11 EOR1B M.bit AB 3 5 Bit exclusive-OR C-flag and NOT : C ← ( C ) ⊕ ~(M .bit) -------C
12 LDC M.bit CB 3 4 Load C-flag : C ← ( M .bit ) -------C
13 LDCB M.bit CB 3 4 Load C-flag with NOT : C ← ~( M .bit ) -------C
14 NOT1 M.bit 4B 3 5 Bit complement : ( M .bit ) ← ~( M .bit ) --------
F
l
Branch if equal
ia
7 BEQ rel F0 2 2/4 --------
if ( Z ) = 1 , then pc ← ( pc ) + rel
Branch if minus
8 BMI rel 9022 /4 --------
if ( N ) = 1 , then pc ← ( pc ) + rel
com Tr
Branch if not equal
9 BNE rel 7022 /4 --------
if ( Z ) = 0 , then pc ← ( pc ) + rel
Branch if minus
10 BPL rel 1022 /4 --------
if ( N ) = 0 , then pc ← ( pc ) + rel
11
12
BRA rel
BVC rel
2F
3022
ce. 8
2 4
/4
Branch always
pc ← ( pc ) + rel
Branch if overflow bit clear
if (V) = 0 , then pc ← ( pc) + rel
--------
--------
an e
Branch if overflow bit set
13 BVS rel B0 2 2/4 --------
if (V) = 1 , then pc ← ( pc ) + rel
.nu at
14 CALL !abs 3B 3 8 Subroutine call
M( sp)←( pcH ), sp←sp - 1, M(sp)← (pcL), sp ←sp - 1, --------
15 CALL [dp] 5F 2 8
if !abs, pc← abs ; if [dp], pcL← ( dp ), pcH← ( dp+1 ) .
ww re
U-page call
23 PCALL upage 4F 2 6 M(sp) ←( pcH ), sp ←sp - 1, M(sp) ← ( pcL ), --------
PD
l
7 POP Y 4D 1 4 sp ← sp + 1, Y ← M( sp )
ia
8 POP PSW 6D 1 4 sp ← sp + 1, PSW ← M( sp ) restored
9 PUSH A 0E 1 4 M( sp ) ← A , sp ← sp - 1
10 2E 1 4
com Tr
PUSH X M( sp ) ← X , sp ← sp - 1
--------
11 PUSH Y 4E 1 4 M( sp ) ← Y , sp ← sp - 1
12 PUSH PSW 6E 1 4 M( sp ) ← PSW , sp ← sp - 1
14 RETI 7F ce. 8
1 6
Return from interrupt
sp ← sp +1, PSW ← M( sp ), sp ← sp + 1,
pcL ← M( sp ), sp ← sp + 1, pcH ← M( sp )
restored
an e
15 STOP EF 1 3 Stop mode ( halt CPU, stop oscillator ) --------
.nu at
w C ww re
F
PD
l ia
com Tr
ce. 8
an e
.nu at
w C ww re
F
PD