Lenovo G410 G510 (Compal LA-9641P)

A B C D E
1 1
2
Compal Confidential 2
DIS M/B Schematics Document

Haswell with DDRIII + Lynx Point PCH
MARS XT / SUN PRO
2013-04-18
3 3
LA-9641P
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9641P
Date: Friday, April 19, 2013 Sheet 1 of 61
A B C D E
A B C D E
Compal confidential
File Name :
1 AMD MARS XT M2 128 bits

Shark Bay 1
/ SUN PRO M2 64 bits

PEG 8x Intel Memory Bus 204pin DDRIII-SO-DIMM X2
　
VRAM 512MB/1GB/2GB Gen2 / Gen3 Processor Dual Channel BANK 0, 1, 2 page 12,13
　1600MHz
MARS XT : DDR3 x 8
DDR3L
SUN PRO : DDR3 x 4
page 23~32
Haswell DDR3L 1333MHz
LVDS Conn. LVDS Translator rPGA946

RTD2132R(Single)
page 34
page 33
37.5mm x 37.5mm
HDMI Conn. page 5,~11
page 36
FDI *2 DMI2 *4
2.7GT/s 5GT/s
2 2
Left USB3.0 x2 Right USB2.0 Int. Camera

USB30 x2 USB30 Port 0,1 USB20 Port 9 USB20 Port 3
page 46 page 46 page 33
USB20 x6 Touch Screen Card Reader

Realtek RTS5170
USB20 Port 2
USB20 Port 11
page 44
CRT Conn. Intel
page 35
PCH
LAN Lynx Point SATA Gen3 HDD Conn.
RJ45 Conn. Atheros PCIe x1 SATA Port 4
page 39 AR8162/QCA8172(10/100) page 41
page 38
FCBGA 695Balls
20mm x 20mm SATA ODD Conn.
SATA Port 5
page 41
3 PCIe Mini Card 3
WLAN PCIe x1
PCIe Port 0 page 28 Audio Codec
AZALIA CONEXANT
PCIe Mini Card USB20 x1 CX20757
USB20 Port 10 page 42
page 28
Sub-borad
Int. MIC Conn. Int. Speaker Conn. Audio Combo Jacks
page 42 page 42
HP & MIC
page 42
SPI ROM EC
15" ODD/B 2MB + 4MB ENE KB9012
LSXXXP page 17 page 44
page 44
14"
Power/B LED/B
4
LSXXXP 4
LSXXXP
page 44 page 44
Thermal Sensor Touch Pad Int. KBD
page 40 page 44 page 44
USB/B CR/B
LSXXXP
LSXXXP Security Classification Compal Secret Data Compal Electronics, Inc.
page 44 page 44
Block Diagram
Size Document Number
Rev
Custom 0.3
LA-9641P
A B C D E
A B C D E
SIGNAL
Voltage Rails BOARD ID Table STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Board ID PCB Revision Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+5VS
0 0.1 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+3VS
1
power 2 S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
plane
3
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+5VALW +1.35V +VCC_CORE

4
5 S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+B +VGA_CORE
+3VALW
6
+1.5VS
7 Vcc 3.3V +/- 5% Board ID / SKU ID Table for AD channel
State +0.675VS
Ra/Rc/Re 100K +/- 5%
Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max Porject Phase
+1.05VS
G-series
0 0 0 V 0 V 0 V MP
G-series
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V PVT
G-series
2 18K +/- 5% 0.436 V 0.503 V 0.538 V DVT
G-series
3 33K +/- 5% 0.712 V 0.819 V 0.875 V EVT
S0
O O O O
USB Port Table

S3
O O O X 3 External
USB 2.0 Port BOM Structure Table
2
USB Port 2
S5 S4/AC BTO Item BOM Structure

O O X X 0 Left USB3.0
UHCI0 DIS PX@
S5 S4/ Battery only
1 Left USB3.0
O X X X MARS XT MARS@
2 Touch screen
UHCI1 SUN PRO SUN@
S5 S4/AC & Battery
3 Camera
X X X X EHCI1 HDMI HDMI@
don't exist 4
UHCI2 Deep S3 DS3@
5
NO Deep S3 NODS3@
6
EC SM Bus1 address EC SM Bus2 address UHCI3 8162 LAN 8162@
7
8172 LAN 8172@
8
Device Device Address UHCI4 LAN LDO MODE LDO@
9 Right USB2.0
Smart Battery 0001 011X b Thermal Sensor 1001_100xb LAN SWR MODE SWR@
10 WLAN
EHCI2 UHCI5 LAN Surge GAS@
11 Card reader
PCH SM Bus address AMD-GPU SM Bus address USB30 USB30@
12
UHCI6 Cameara CMOS@
13
Device Address Device Address LAN Switch mode SWR@
DDR DIMM1 ChannelA 0xA0 Internal thermal sensor 1000_001xb Touch screen TS@
3 3
DDR DIMM2 ChannelB 0xA4 Righ side USB RUSB@
Zero ODD circuit ZODD@ R_USB@
Share ROM SROM@
Device Address
Non-share ROM NOSROM@
RTD2132R 1101 010Xb 14" 14@
15" 15@
45 LEVEL 45@
SMBUS Control Table X76 LEVEL
Unpop
X76@
@
Thermal
WLAN Sensor AUDIO PART MIC@
SOURCE VGA BATT KB9012 SODIMM WWAN PCH RTD2132
Connector ME@
SMB_EC_CK1
SMB_EC_DA1
KB9012
+3VALW
X V
+3VALW
X X X X X X
SMB_EC_CK2
SMB_EC_DA2
KB9012
+3VALW
X X X X X X V
+3VS
V
+3VS
SMBCLK
X X X V V X X
4 4
SMBDATA
PCH
+3VALW +3VS +3VS X VRAM BOM STRUCTURE Refer P4. VGA NOTE
SML0CLK
SML0DATA
PCH
+3VALW
X X X X X X X X
Compal Electronics, Inc.
V X V X X V X V
Compal Secret Data
SML1CLK
Security Classification
PCH Issued Date 2011/06/15 2012/07/11 Title
SML1DATA +3VS +3VS +3VS +3VS
Deciphered Date
+3VALW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size
Document Number Rev
B 0.3
LA-9641P
A B C D E
5 4 3 2 1
Mars XT VRAM STRAP Power-Up/Down Sequence

X76@ X76@ "Mars" has the following requirements with regards to power-supply
Vendor
UV5, UV6, UV7, UV8
UV9, UV10, UV11, UV12
PS_3[ 3 ] PS_3[ 2 ] PS_3[ 1 ]
R_pu
RV20
R_pd
RV27 ‧
sequencing to avoid damaging the ASIC:
All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
Samsung 2048Mbits
ZZZ4
MS2G@
SA000068U00
128Mx16 K4W2G1646E-BC1A 0 0 0 NC 4.75K ‧
preferred. The maximum slew rate on all rails is 50 mV/µs.
The external pull ups on the DDC/AUX signals (if applicable) should ramp up
D
ZZZ5
Micron 2048Mbits
SA000067500 ‧
before or after both VDDC and VDD_CT have ramped up.
VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
D
‧
2GBytes MM2G@ 128Mx16 MT41J128M16JT-093G:K 0 0 1 8.45K 2K should reach 90% before VDD_CT starts to ramp up (or vice versa).
Hynix 2048Mbits For power down, reversing the ramp-up sequence is recommended.
ZZZ6 SA000065300
MH2G@ H5TQ2G63DFR-N0C 0 1 0 4.53K 2K
Samsung 1028Mbits
ZZZ7 SA00004GS00
MS1G@ 64Mx16 K4W1G1646G-BC11 0 1 1 6.98K 4.99K
1GBytes Hynix 1024Mbits
ZZZ8 SA000041SB0
MH1G@ 64Mx16 H5TQ1G63EFR-11C 1 1 1 4.75K NC
VDDR3(3.3VGS)
Hynix 2048Mbits
ZZZ15 SA00006H400
2GBytes MH2GN@ 128Mx16 H5TC2G63FFR-11C 1 0 0 4.53K 4.99K PCIE_VDDC(0.95VGSV)
2GBytes 1GBytes VDDR1(1.5VGS)

ZZZ4 ZZZ5 ZZZ6 ZZZ15 ZZZ7 ZZZ8
C C
VDDC/VDDCI(1.12V)
Samsung_2G Micron_2G Hynix_2G Hynix_2G Samsung_1G Hynix_1G
MS2G@ MM2G@ MH2G@ MH2GN@ MS1G@ MH1G@
X7646738L01 X7646738L02 X7646738L09 X7646738L10 X7646738L03 X7646738L04 VDD_CT(1.8V)
PERSTb
REFCLK
Sun PRO VRAM STRAP
X76@ X76@ Straps Reset
Vendor R_pu R_pd
UV9, UV10, UV11, UV12 PS_3[ 3 ] PS_3[ 2 ] PS_3[ 1 ]
RV20 RV27
Samsung 4096Mbits Straps Valid
ZZZ9 SA000068R00
SS2G@ 256Mx16 K4W4G1646B-HC11 0 0 0 NC 4.75K
B
Micron 4096Mbits Global ASIC Reset B
ZZZ10 SA000065D00
2GBytes SM2G@ 256Mx16/1866 MT41K256M16HA-107G:E
0 0 1 8.45K 2K
T4+16clock
Hynix 4096Mbits
ZZZ11 SA00006DG00
SH2G@ 256MX16 H5TQ4G63MFR-11C 0 1 0 4.53K 2K
Samsung 2048Mbits
ZZZ12 SA000068U00
SS1G@ 128Mx16 K4W2G1646E-BC1A 0 1 1 6.98K 4.99K
Micron 2048Mbits
ZZZ13 SA000067500
1GBytes SM1G@ 128Mx16 MT41J128M16JT-093G:K 1 1 0 3.4K 10K
Hynix 2048Mbits
ZZZ14 SA000065300
SH1G@ H5TQ2G63DFR-N0C 1 1 1 4.75K NC
Hynix 2048Mbits
ZZZ16 SA00006H400
1GBytes SH1GN@ H5TC2G63FFR-11C 1 0 0 4.53K 4.99K
A A
2GBytes 1GBytes
ZZZ9 ZZZ10 ZZZ11 ZZZ12 ZZZ13 ZZZ14 ZZZ16
Samsung_2G Micron_2G Hynix_2G Samsung_1G Micron_1G Hynix_1G Hynix_1G

SS2G@ SM2G@ SH2G@ SS1G@ SM1G@ SH1G@ SH1GN@ Issued Date 2011/06/15 2012/07/11 Title
X7646738L05 X7646738L06 X7646738L11 X7646738L07 X7646738L08 X7647538L01 X7646738L13 Deciphered Date
VGA Notes List
Rev
Custom 0.3
LA-9641P
5 4 3 2 1
5 4 3 2 1
ZZZ1 14@ ZZZ2 15@
14" PCB LA9641 15" PCB LA9641

+VCOMP_OUT
DA6000WQ000 DA6000WQ100
PEG_RCOMP 2 1
24.9_0402_1% R1
D D
Note:
Trace width=12 mils ,Spacing=15mils
Max length= 400 mils.
Haswell rPGA EDS

JCPU1A
E23 PEG_RCOMP
PEG_RCOMP M29
DMI_CRX_PTX_N0 D21 PEG_RXN_0 K28
<15> DMI_CRX_PTX_N0 DMI_RXN_0 PEG_RXN_1
<15> DMI_CRX_PTX_N1 DMI_CRX_PTX_N1 C21 M31
DMI_CRX_PTX_N2 B21 DMI_RXN_1 PEG_RXN_2 L30
<15> DMI_CRX_PTX_N2 DMI_RXN_2 PEG_RXN_3
<15> DMI_CRX_PTX_N3 DMI_CRX_PTX_N3 A21 M33 PCIE_CRX_GTX_N[0..7] <23>
DMI_RXN_3 PEG_RXN_4 L32
DMI_CRX_PTX_P0 D20 PEG_RXN_5 M35
<15> DMI_CRX_PTX_P0
PEG
DMI_CRX_PTX_P1 C20 DMI_RXP_0 PEG_RXN_6 L34
<15> DMI_CRX_PTX_P1 DMI_RXP_1 PEG_RXN_7
<15> DMI_CRX_PTX_P2 DMI_CRX_PTX_P2 B20 E29 PCIE_CRX_GTX_N7
DMI_CRX_PTX_P3 A20 DMI_RXP_2 PEG_RXN_8 D28 PCIE_CRX_GTX_N6
<15> DMI_CRX_PTX_P3
DMI
DMI_RXP_3 PEG_RXN_9 E31 PCIE_CRX_GTX_N5
DMI_CTX_PRX_N0 D18 PEG_RXN_10 D30 PCIE_CRX_GTX_N4
<15> DMI_CTX_PRX_N0 DMI_TXN_0 PEG_RXN_11
DMI_CTX_PRX_N1 C17 E35 PCIE_CRX_GTX_N3
DMI_CTX_PRX_N2 B17 D34 PCIE_CRX_GTX_N2
DMI_CTX_PRX_N3 A17 E33 PCIE_CRX_GTX_N1
<15> DMI_CTX_PRX_N3 DMI_TXN_3 PEG_RXN_14 E32 PCIE_CRX_GTX_N0
DMI_CTX_PRX_P0 D17 PEG_RXN_15 L29
<15> DMI_CTX_PRX_P0 DMI_TXP_0 PEG_RXP_0
C DMI_CTX_PRX_P1 C18 L28 C
DMI_CTX_PRX_P2 B18 L31
DMI_CTX_PRX_P3 A18 K30
<15> DMI_CTX_PRX_P3 DMI_TXP_3 PEG_RXP_3 L33
PEG_RXP_4 K32
PEG_RXP_5 PCIE_CRX_GTX_P[0..7] <23>
L35
PEG_RXP_6 K34
PEG_RXP_7 F29 PCIE_CRX_GTX_P7
H29 PEG_RXP_8 E28 PCIE_CRX_GTX_P6
<15> FDI_CSYNC
FDI
J29 FDI_CSYNC PEG_RXP_9 F31 PCIE_CRX_GTX_P5
<15> FDI_INT DISP_INT PEG_RXP_10 E30 PCIE_CRX_GTX_P4
PEG_RXP_11 F35 PCIE_CRX_GTX_P3
PEG_RXP_12 E34 PCIE_CRX_GTX_P2
Note: PEG_RXP_13 F33 PCIE_CRX_GTX_P1
Trace width=4 mils ,Spacing=5mil PEG_RXP_14 D32 PCIE_CRX_GTX_P0
PEG_RXP_15 H35
Max length= 10000 mils. PEG_TXN_0 H34
PEG_TXN_1 J33
PEG_TXN_2 H32
PEG_TXN_3 J31
PEG_TXN_4 G30
PEG_TXN_5 PCIE_CTX_GRX_N[0..7] <23>
C33
PEG_TXN_6 B32
PEG_TXN_7 B31PCIE_CTX_GRX_C_N7 C9 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N7
PEG_TXN_8 A30PCIE_CTX_GRX_C_N6 C10 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N6
B PEG_TXN_14 A24PCIE_CTX_GRX_C_N0 C16 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N0 B
PEG_TXN_15 J35
PEG_TXP_0 G34
PEG_TXP_1 H33
PEG_TXP_2 G32
PEG_TXP_3 H31
PEG_TXP_4 PCIE_CTX_GRX_P[0..7] <23>
H30
PEG_TXP_5 B33
PEG_TXP_6 A32
PEG_TXP_7 C31PCIE_CTX_GRX_C_P7 C25 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P7
PEG_TXP_8 B30PCIE_CTX_GRX_C_P6 C26 PX@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P6
PEG_TXP_15
INTEL_HASWELL_HASWELL 1 OF 9
ME@
A A
Security Classification Compal Secret Data

PROCESSOR(1/7) DMI,FDI,PEG
Custom 0.3
LA-9641P
5 4 3 2 1
5 4 3 2 1
D D
R46
1K_0402_5%
H_DRAMRST# 1 2
DDR3_DRAMRST# <12,13>
DDR3 COMPENSATION SIGNALS

+VCCIO_OUT SM_RCOMP0 R5 1 2 100_0402_1%
SM_RCOMP1 R6 1 2 75_0402_1%
SM_RCOMP2 R7 1 2 100_0402_1%
Note: Haswell rPGA EDS
1
JCPU1B Note:
R8 PECI/THERMTRIP:
62_0402_5% Trace width=4 mils ,Spacing=18mil
AP32
SKTOCC
MISC
SM_RCOMP_0
AP3 SM_RCOMP0 Trace width=12~15 mil, Spcing=20 mils
AR3 SM_RCOMP1
SM_RCOMP_1 Max trace length= 500 mils
DDR3
Zo=50 ohm AN32 AP2
THERMAL
T31 H_CATERR# SM_RCOMP2
2
AR27 CATERR SM_RCOMP_2 AN3 H_DRAMRST#

<19,43> H_PECI +VCCST AK31 PECI SM_DRAMRST
<43,48,49,56> H_PROCHOT#
H_PROCHOT# R9 1 2 H_PROCHOT#_R AM30 FC_AK31
PROCHOT PRDY
AR29 XDP_PRDY# PU/PD for JTAG signals
56_0402_5% AM35 AT29 XDP_PREQ#
<19> H_THRMTRIP# THERMTRIP PREQ AM34 XDP_TCLK
C TCK AN33 XDP_TMS +3VS C
TMS AM33 XDP_TRST#
JTAG
R10 1 2 0_0402_5% H_PM_SYNC_R AT28 TRST AM31 XDP_TDI XDP_DBRESET# R11 2 1 1K_0402_5%
<15> H_PM_SYNC
PWR
AL34 PM_SYNC TDI AL33 XDP_TDO
<19> H_CPUPWRGD PWRGOOD TDO
PM_SYS_PWRGD_BUF AC10 AP33 XDP_DBRESET#
R37 1 2 0_0402_5% BUF_CPU_RST# AT26 SM_DRAMPWROK DBR
<19> CPU_PLTRST# PLTRSTIN
2
1 AR30 XDP_BPM#0 1
C536 BPM_N_0 AN31 XDP_BPM#1 C186 +1.05VS
R15 G28 BPM_N_1 AN29 XDP_BPM#2 47P_0402_50V8J
<16> CLK_CPU_DPLL# DPLL_REF_CLKN BPM_N_2
CLOCK
22P_0402_50V8J 10K_0402_5% <16> H28 AP31 XDP_BPM#3
2 CLK_CPU_DPLL DPLL_REF_CLKP BPM_N_3 2 51_0804_8P4R_5%
F27 AP30 XDP_BPM#4
<16> CLK_CPU_SSC_DPLL#
1
E27 SSC_DPLL_REF_CLKN BPM_N_4 AN28 XDP_BPM#5 For EMI XDP_TDO 5 4

C536 ESD reserve <16>
<16>
CLK_CPU_SSC_DPLL
CLK_CPU_DMI#
D26 SSC_DPLL_REF_CLKP
BCLKN
BPM_N_5
BPM_N_6
AP29 XDP_BPM#6 Near Chip XDP_TRST# 6 3
E26 AP28 XDP_BPM#7 XDP_TCLK 7 2
<16> CLK_CPU_DMI BCLKP BPM_N_7 8 1
INTEL_HASWELL_HASWELL 2 OF 9 RP19
+VCCIO_OUT ME@
CLK_CPU_SSC_DPLL 2 @ R26 1 10K_0402_5%
CLK_CPU_SSC_DPLL# 2 @ R27 1 10K_0402_5%
SSC CLOCK TERMINATION, IF NOT USED, stuff R26,R27
B B
SM_DRAMPWROK with DDR Power Gating Topology
+3V_PCH +3V_PCH
@ +1.35V_CPU_VDDQ
1
C35
1
0.1U_0402_16V7K
1
@ @
R28 R29 2 R30
100K_0402_5% 200_0402_1% 1.8K_0402_1%
U1
2
@
2
@ 1 R32 2 1
P
<15,43> SYS_PWROK B
0_0402_5% 4 PM_SYS_PWRGD_BUF
2 O
<15> PM_DRAM_PWRGD A
G
74AHC1G09GW_TSSOP5
3
@ R36
R35 3.3K_0402_1%
39_0402_5%
2
1 2
R133 @ 0_0402_5%
1
D
A 2 Q1 @ A
<47> SUSP
G 2N7002H_SOT23-3
S
3

PROCESSOR(2/7) PM,XDP,CLK
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9641P 0.3
5 4 3 2 1
5 4 3 2 1
Haswell rPGA EDS

JCPU1C
Haswell rPGA EDS
<12> DDR_A_D[0..63] AR15 AC7
DDR_A_D0 T12 JCPU1D
AT14 SA_DQ_0 RSVD U4 <13> DDR_B_D[0..63]
DDR_A_D1 M_CLK_DDR#0
AM14 SA_DQ_1 SA_CK_N_0 V4 M_CLK_DDR#0 <12> AR18 AG8
DDR_A_D2 M_CLK_DDR0 DDR_B_D0 T13
AN14 SA_DQ_2 SA_CK_P_0 AD9 M_CLK_DDR0 <12> AT18 SB_DQ_0 RSVD Y4
DDR_A_D3 DDR_CKE0_DIMMA DDR_B_D1 M_CLK_DDR#2
AT15 SA_DQ_3 SA_CKE_0 U3 DDR_CKE0_DIMMA <12> AM17 SB_DQ_1 SB_CKN0 AA4 M_CLK_DDR2 M_CLK_DDR#2 <13>
DDR_A_D4 M_CLK_DDR#1 DDR_B_D2
AR14 SA_DQ_4 SA_CK_N_1 V3 M_CLK_DDR#1 <12> AM18 SB_DQ_2 SB_CK0 AF10 DDR_CKE2_DIMMB M_CLK_DDR2 <13>
DDR_A_D5 M_CLK_DDR1 DDR_B_D3
AN15 SA_DQ_5 SA_CK_P_1 AC9 M_CLK_DDR1 <12> AR17 SB_DQ_3 SB_CKE_0 Y3 DDR_CKE2_DIMMB <13>
DDR_A_D6 DDR_CKE1_DIMMA DDR_B_D4 M_CLK_DDR#3
AM15 SA_DQ_6 SA_CKE_1 U2 DDR_CKE1_DIMMA <12> AT17 SB_DQ_4 SB_CKN1 AA3 M_CLK_DDR3 M_CLK_DDR#3 <13>
DDR_A_D7 DDR_B_D5
AM9 SA_DQ_7 SA_CK_N_2 V2 AN17 SB_DQ_5 SB_CK1 AG10 DDR_CKE3_DIMMB M_CLK_DDR3 <13>
DDR_A_D8 DDR_B_D6
AN9 SA_DQ_8 SA_CK_P_2 AD8 AN18 SB_DQ_6 SB_CKE_1 Y2 DDR_CKE3_DIMMB <13>
DDR_A_D9 DDR_B_D7
DDR_A_D10 AM8 SA_DQ_9 SA_CKE_2 U1 DDR_B_D8 AT12 SB_DQ_7 SB_CKN2 AA2
DDR_A_D11 AN8 SA_DQ_10 SA_CK_N_3 V1 DDR_B_D9 AR12 SB_DQ_8 SB_CK2 AG9
DDR_A_D12 AR9 SA_DQ_11 SA_CK_P_3 AC8 DDR_B_D10 AN12 SB_DQ_9 SB_CKE_2 Y1
DDR_A_D13 AT9 SA_DQ_12 SA_CKE_3 DDR_B_D11 AM11 SB_DQ_10 SB_CKN3 AA1
DDR_A_D14 AR8 SA_DQ_13 M7 DDR_CS0_DIMMA# DDR_B_D12 AT11 SB_DQ_11 SB_CK3 AF9
D SA_DQ_14 SA_CS_N_0 DDR_CS0_DIMMA# <12> SB_DQ_12 SB_CKE_3 D
DDR_A_D15 AT8 L9 DDR_CS1_DIMMA# DDR_B_D13 AR11
AJ9 SA_DQ_15 SA_CS_N_1 M9 DDR_CS1_DIMMA# <12> AM12 SB_DQ_13 P4
DDR_A_D16 DDR_B_D14 DDR_CS2_DIMMB#
AK9 SA_DQ_16 SA_CS_N_2 M10 AN11 SB_DQ_14 SB_CS_N_0 R2 DDR_CS2_DIMMB# <13>
DDR_A_D17 DDR_B_D15 DDR_CS3_DIMMB#
AJ6 SA_DQ_17 SA_CS_N_3 M8 AR5 SB_DQ_15 SB_CS_N_1 P3 DDR_CS3_DIMMB# <13>
DDR_A_D18 M_ODT0 DDR_B_D16
AK6 SA_DQ_18 SA_ODT_0 L7 M_ODT0 <12> AR6 SB_DQ_16 SB_CS_N_2 P1
DDR_A_D19 M_ODT1 DDR_B_D17
AJ10 SA_DQ_19 SA_ODT_1 L8 M_ODT1 <12> AM5 SB_DQ_17 SB_CS_N_3
DDR_A_D20 DDR_B_D18
DDR_A_D21 AK10 SA_DQ_20 SA_ODT_2 L10 DDR_B_D19 AM6 SB_DQ_18 R4 M_ODT2
AJ7 SA_DQ_21 SA_ODT_3 V5 AT5 SB_DQ_19 SB_ODT_0 R3 M_ODT3 M_ODT2 <13>
DDR_A_D22 DDR_A_BS0 DDR_B_D20
AK7 SA_DQ_22 SA_BS_0 U5 DDR_A_BS0 <12> AT6 SB_DQ_20 SB_ODT_1 R1 M_ODT3 <13>
AF4 SA_DQ_23 SA_BS_1 AD1 DDR_A_BS1 <12> AN5 SB_DQ_21 SB_ODT_2 P2
AF5 SA_DQ_24 SA_BS_2 DDR_A_BS2 <12> AN6 SB_DQ_22 SB_ODT_3 R7
DDR_A_D25 DDR_B_D23 DDR_B_BS0
AF1 SA_DQ_25 V10 AJ4 SB_DQ_23 SB_BS_0 P8 DDR_B_BS0 <13>
DDR_A_D26 DDR_B_D24 DDR_B_BS1
AF2 SA_DQ_26 VSS U6 AK4 SB_DQ_24 SB_BS_1 AA9 DDR_B_BS2 DDR_B_BS1 <13>
DDR_A_D27 DDR_A_RAS# DDR_B_D25
AG4 SA_DQ_27 SA_RAS U7 DDR_A_RAS# <12> AJ1 SB_DQ_25 SB_BS_2 DDR_B_BS2 <13>
DDR_A_D28 DDR_A_WE# DDR_B_D26
AG5 SA_DQ_28 SA_WE U8 DDR_A_WE# <12> AJ2 SB_DQ_26 R10
DDR_A_D29 DDR_A_CAS# DDR_B_D27
AG1 SA_DQ_29 SA_CAS DDR_A_CAS# <12> AM1 SB_DQ_27 VSS R6 DDR_B_RAS#
DDR_A_D30 DDR_B_D28
AG2 SA_DQ_30 V8 DDR_A_MA[0..15] <12> AN1 SB_DQ_28 SB_RAS P6 DDR_B_RAS# <13>
DDR_A_D31 DDR_A_MA0 DDR_B_D29 DDR_B_WE#
J1 SA_DQ_31 SA_MA_0 AC6 AK2 SB_DQ_29 SB_WE P7 DDR_B_WE# <13>
DDR_A_D32 DDR_A_MA1 DDR_B_D30 DDR_B_CAS#
J2 SA_DQ_32 SA_MA_1 V9 AK1 SB_DQ_30 SB_CAS DDR_B_CAS# <13>
DDR_A_D33 DDR_A_MA2 DDR_B_D31
J5 SA_DQ_33 SA_MA_2 U9 L2 SB_DQ_31 R8 DDR_B_MA[0..15] <13>
DDR_A_D34 DDR_A_MA3 DDR_B_D32 DDR_B_MA0
DDR_A_D35 H5 SA_DQ_34 SA_MA_3 AC5 DDR_A_MA4 DDR_B_D33 M2 SB_DQ_32 SB_MA_0 Y5 DDR_B_MA1
DDR_A_D36 H2 SA_DQ_35 SA_MA_4 AC4 DDR_A_MA5 DDR_B_D34 L4 SB_DQ_33 SB_MA_1 Y10 DDR_B_MA2
DDR_A_D37 H1 SA_DQ_36 SA_MA_5 AD6 DDR_A_MA6 DDR_B_D35 M4 SB_DQ_34 SB_MA_2 AA5 DDR_B_MA3
DDR_A_D38 J4 SA_DQ_37 SA_MA_6 AC3 DDR_A_MA7 DDR_B_D36 L1 SB_DQ_35 SB_MA_3 Y7 DDR_B_MA4
DDR_A_D39 H4 SA_DQ_38 SA_MA_7 AD5 DDR_A_MA8 DDR_B_D37 M1 SB_DQ_36 SB_MA_4 AA6 DDR_B_MA5
DDR_A_D40 F2 SA_DQ_39 SA_MA_8 AC2 DDR_A_MA9 DDR_B_D38 L5 SB_DQ_37 SB_MA_5 Y6 DDR_B_MA6
DDR_A_D41 F1 SA_DQ_40 SA_MA_9 V6 DDR_A_MA10 DDR_B_D39 M5 SB_DQ_38 SB_MA_6 AA7 DDR_B_MA7
DDR_A_D42 D2 SA_DQ_41 SA_MA_10 AC1 DDR_A_MA11 DDR_B_D40 G7 SB_DQ_39 SB_MA_7 Y8 DDR_B_MA8
DDR_A_D43 D3 SA_DQ_42 SA_MA_11 AD4 DDR_A_MA12 DDR_B_D41 J8 SB_DQ_40 SB_MA_8 AA10 DDR_B_MA9
DDR_A_D44 D1 SA_DQ_43 SA_MA_12 V7 DDR_A_MA13 DDR_B_D42 G8 SB_DQ_41 SB_MA_9 R9 DDR_B_MA10
DDR_A_D45 F3 SA_DQ_44 SA_MA_13 AD3 DDR_A_MA14 DDR_B_D43 G9 SB_DQ_42 SB_MA_10 Y9 DDR_B_MA11
DDR_A_D46 C3 SA_DQ_45 SA_MA_14 AD2 DDR_A_MA15 DDR_B_D44 J7 SB_DQ_43 SB_MA_11 AF7 DDR_B_MA12
DDR_A_D47 B3 SA_DQ_46 SA_MA_15 DDR_B_D45 J9 SB_DQ_44 SB_MA_12 P9 DDR_B_MA13
DDR_A_D48 B5 SA_DQ_47 DDR_B_D46 G10 SB_DQ_45 SB_MA_13 AA8 DDR_B_MA14
E6 SA_DQ_48 AP15 DDR_A_DQS#[0..7] <12> J10 SB_DQ_46 SB_MA_14 AG7
DDR_A_D49 DDR_A_DQS#0 DDR_B_D47 DDR_B_MA15
DDR_A_D50 A5 SA_DQ_49 SA_DQS_N_0 AP8 DDR_A_DQS#1 DDR_B_D48 A8 SB_DQ_47 SB_MA_15
DDR_A_D51 D6 SA_DQ_50 SA_DQS_N_1 AJ8 DDR_A_DQS#2 DDR_B_D49 B8 SB_DQ_48
C SA_DQ_51 SA_DQS_N_2 SB_DQ_49 DDR_B_DQS#[0..7] <13> C
DDR_A_D52 D5 AF3 DDR_A_DQS#3 DDR_B_D50 A9 AP18 DDR_B_DQS#0
DDR_A_D53 E5 SA_DQ_52 SA_DQS_N_3 J3 DDR_A_DQS#4 DDR_B_D51 B9 SB_DQ_50 SB_DQS_N_0 AP11 DDR_B_DQS#1
DDR_A_D54 B6 SA_DQ_53 SA_DQS_N_4 E2 DDR_A_DQS#5 DDR_B_D52 D8 SB_DQ_51 SB_DQS_N_1 AP5 DDR_B_DQS#2
DDR_A_D55 A6 SA_DQ_54 SA_DQS_N_5 C5 DDR_A_DQS#6 DDR_B_D53 E8 SB_DQ_52 SB_DQS_N_2 AJ3 DDR_B_DQS#3
DDR_A_D56 E12 SA_DQ_55 SA_DQS_N_6 C11 DDR_A_DQS#7 DDR_B_D54 D9 SB_DQ_53 SB_DQS_N_3 L3 DDR_B_DQS#4
D12 SA_DQ_56 SA_DQS_N_7 AP14 DDR_A_DQS[0..7] <12> E9 SB_DQ_54 SB_DQS_N_4 H9
DDR_A_D57 DDR_A_DQS0 DDR_B_D55 DDR_B_DQS#5
DDR_A_D58 B11 SA_DQ_57 SA_DQS_P_0 AP9 DDR_A_DQS1 DDR_B_D56 E15 SB_DQ_55 SB_DQS_N_5 C8 DDR_B_DQS#6
DDR_A_D59 A11 SA_DQ_58 SA_DQS_P_1 AK8 DDR_A_DQS2 DDR_B_D57 D15 SB_DQ_56 SB_DQS_N_6 C14 DDR_B_DQS#7
E11 SA_DQ_59 SA_DQS_P_2 AG3 A15 SB_DQ_57 SB_DQS_N_7 AP17 DDR_B_DQS[0..7] <13>
DDR_A_D60 DDR_A_DQS3 DDR_B_D58 DDR_B_DQS0
DDR_A_D61 D11 SA_DQ_60 SA_DQS_P_3 H3 DDR_A_DQS4 DDR_B_D59 B15 SB_DQ_58 SB_DQS_P_0 AP12 DDR_B_DQS1
DDR_A_D62 B12 SA_DQ_61 SA_DQS_P_4 E3 DDR_A_DQS5 DDR_B_D60 E14 SB_DQ_59 SB_DQS_P_1 AP6 DDR_B_DQS2
DDR_A_D63 A12 SA_DQ_62 SA_DQS_P_5 C6 DDR_A_DQS6 DDR_B_D61 D14 SB_DQ_60 SB_DQS_P_2 AK3 DDR_B_DQS3
+VREF_CA_R AM3 SA_DQ_63 SA_DQS_P_6 C12 DDR_A_DQS7 DDR_B_D62 A14 SB_DQ_61 SB_DQS_P_3 M3 DDR_B_DQS4
+VREF_CA_R SM_VREF SA_DQS_P_7 SB_DQ_62 SB_DQS_P_4
+VREF_DQ_DIMMA_R +VREF_DQ_DIMMA_R F16 DDR_B_D63 B14 H8 DDR_B_DQS5
+VREF_DQ_DIMMB_R F13 SA_DIMM_VREFDQ SB_DQ_63 SB_DQS_P_5 C9 DDR_B_DQS6
+VREF_DQ_DIMMB_R SB_DIMM_VREFDQ SB_DQS_P_6 C15 DDR_B_DQS7
SB_DQS_P_7
INTEL_HASWELL_HASWELL 3 OF 9 INTEL_HASWELL_HASWELL 4 OF 9
ME@ ME@
CPI DRIVER VREF PATH IS DEFAULT
B B
A A

PROCESSOR(3/7) DDRIII
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9641P
5 4 3 2 1
5 4 3 2 1
D D
COMPENSATION PU FOR eDP

+VCOMP_OUT
EDP_COMP 2 1
24.9_0402_1% R60
Note:
Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
Haswell rPGA EDS
JCPU1H
HDMI@ C48 1 2 0.1U_0402_16V7K TMDS_B_DATA2#_PCH T28 M27 EDP_CPU_AUX#

<36> HDMI_TX2-_CK 1 2 U28 DDIB_TXBN_0 EDP_AUXN N27 EDP_CPU_AUX# <33>
HDMI D2 HDMI@ C41 0.1U_0402_16V7K TMDS_B_DATA2_PCH EDP_CPU_AUX
<36> HDMI_TX2+_CK 1 2 TMDS_B_DATA1#_PCH T30 DDIB_TXBP_0 EDP_AUXP P27 EDP_HPD# EDP_CPU_AUX <33>
HDMI@ C42 0.1U_0402_16V7K
<36> HDMI_TX1-_CK 1 2 TMDS_B_DATA1_PCH U30 DDIB_TXBN_1 EDP_HPD E24 EDP_COMP
HDMI D1 HDMI@ C43 0.1U_0402_16V7K eDP
<36> HDMI_TX1+_CK 1 2 TMDS_B_DATA0#_PCH U29 DDIB_TXBP_1 EDP_RCOMP R27
HDMI <36> HDMI_TX0-_CK
HDMI@ C44 0.1U_0402_16V7K
DDIB_TXBN_2 EDP_DISP_UT IL
T14
HDMI D0 HDMI@ C45 1 2 0.1U_0402_16V7K TMDS_B_DATA0_PCH V29
<36> HDMI_TX0+_CK 1 2 U31 DDIB_TXBP_2
HDMI@ C46 0.1U_0402_16V7K TMDS_B_CLK#_PCH
<36> HDMI_CLK-_CK 1 2 TMDS_B_CLK_PCH V31 DDIB_TXBN_3
HDMI CLK HDMI@ C47 0.1U_0402_16V7K
C <36> HDMI_CLK+_CK DDIB_TXBP_3 P35 EDP_CPU_LANE_N0 C
T34 EDP_TXN_0 R35 EDP_CPU_LANE_P0 EDP_CPU_LANE_N0 <33>
U34 DDIC_TXCN_0 EDP_TXP_0 N34 EDP_CPU_LANE_P0 <33>
EDP_CPU_LANE_N1
U35 DDIC_TXCP_0 EDP_TXN_1 P34 EDP_CPU_LANE_P1
V35 DDIC_TXCN_1 EDP_TXP_1 P33 FDI_CTX_PRX_N0
U32 DDIC_TXCP_1 FDI_TXN_0 R33 FDI_CTX_PRX_P0 FDI_CTX_PRX_N0 <15>
T32 DDIC_TXCN_2 FDI_TXP_0 N32 FDI_CTX_PRX_N1 FDI_CTX_PRX_P0 <15>
U33 DDIC_TXCP_2 FDI_TXN_1 P32 FDI_CTX_PRX_N1 <15>
FDI_CTX_PRX_P1
Place on connector side V33 DDIC_TXCN_3 FDI_TXP_1 FDI_CTX_PRX_P1 <15>
DDIC_TXCP_3
P29
R29 DDID_TXDN_0
N28 DDID_TXDP_0
P28 DDID_TXDN_1 DDI
P31 DDID_TXDP_1
R31 DDID_TXDN_2
N30 DDID_TXDP_2
P30 DDID_TXDN_3
DDID_TXDP_3
+VCCIO_OUT
ME@
HPD INVERSION FOR EDP
10K_0402_5%
2
RC1
1
B EDP_HPD# B
1
R458
1 2 1K_0402_5%
OUT
<33> TL_HPD
2
IN
GND
Q6
DTC124EKAT146_SC59-3
3
HPD is a active high signal from device. The HPD processor input is a low voltage
active signal.
A A

PROCESSOR(2/7) PM,XDP,CLK
5 4 3 2 1
5 4 3 2 1
CFG Straps for Processor
CFG2
1
R62
1K_0402_1%
PX@
2
D D
PEG Static Lane Reversal - CFG2 is for the 16x
1: Normal Operation; Lane # definition matches

CFG2 socket pin map definition
0:Lane Reversed
Haswell rPGA EDS *
JCPU1I CFG4
1
AT1
AT2 RSVD_TP C23 R63
AD10 RSVD_TP RSVD_TP B23 1K_0402_1%
RSVD RSVD_TP D24
2
A34 RSVD_TP D23
A35 RSVD_TP RSVD_TP
RSVD_TP
W29
W28 RSVD_TP AT31 CFG_RCOMP
H_CPU_RSVD G26 RSVD_TP CFG_RCOMP AR21 CFG16 T19
W33 TESTLO_G26 CFG_16 AR23
RSVD CFG_18 Embedded Display Port Presence Strap
AL30 AP21
AL29 RSVD CFG_17 AP23
C F25 RSVD CFG_19 C
+CPU_CORE VCC 1 : Disabled; No Physical Display Port
1 2 H_CPU_TESTLO CFG4
R64 49.9_0402_1% C35 AR33 attached to Embedded Display Port
1 2 CFG_RCOMP B35 RSVD_TP RSVD G6
RSVD_TP FC_G6 AM27
R309 49.9_0402_1% 0 : Enabled; An external Display Port device is
R66
1 2 H_CPU_RSVD
49.9_0402_1%
AL25
W30
RSVD_TP
RSVD
RSVD
RSVD
AM26
F5
AM2
* connected to the Embedded Display Port
W31 RSVD_TP RSVD K6
H_CPU_TESTLO W34 RSVD_TP RSVD
TESTLO E18 CFG6
T16 CFG0 AT20 RSVD
T17 CFG1 AR20 CFG_0 U10 CFG5
CFG2 AP20 CFG_1 RSVD P10
CFG_2 RSVD
1
T18 CFG3 AP22
CFG4 AT22 CFG_3 B1 @ R67 @ R68
CFG5 AN22 CFG_4 NC A2 1K_0402_1% 1K_0402_1%
CFG6 AT25 CFG_5 RSVD AR1
CFG7 AN23 CFG_6 RSVD_TP
2
AR24 CFG_7 E21
AT23 CFG_8 RSVD_TP E20
AN20 CFG_9 RSVD_TP
AP24 CFG_10 AP27
AP26 CFG_11 RSVD AR26
AN25 CFG_12 RSVD
AN26 CFG_13 AL31
AP25 CFG_14 VSS AL32
CFG_15 VSS
PCIE Port Bifurcation Straps
INTEL_HASWELL_HASWELL 9 OF 9 11: (Default) x16 - Device 1 functions 1 and 2 disabled

B
ME@ CFG[6:5] *10: x8, x8 - Device 1 function 1 enabled ; function 2 B
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB

CFG7 * de assertion
A
0: PEG Wait for BIOS for training A

PROCESSOR(4/7) RSVD,CFG
5 4 3 2 1
5 4 3 2 1
Haswell rPGA EDS +CPU_CORE

JCPU1E
AA26
VCC AA28
+1.35V_CPU_VDDQ Source K27
RSVD
VCC
VCC
AA34
L27 AA30
T27 RSVD VCC AA32
V27 RSVD VCC AB26
+1.35V_CPU_VDDQ RSVD VCC AB29
D
VCC AB25 D
VCC AB27
+1.35V +1.35V_CPU_VDDQ VCC AB28
@J1
@ J1 AB11 VCC AB30
1 2 AB2 VDDQ VCC AB31
AB5 VDDQ VCC AB33
PAD-OPEN 43x118m AB8 VDDQ VCC AB34
AE11 VDDQ VCC AB32
AE2 VDDQ VCC AC26
AE5 VDDQ VCC AB35
AE8 VDDQ VCC AC28
AH11 VDDQ VCC AD25
K11 VDDQ VCC AC30
N11 VDDQ VCC AD28
N8 VDDQ VCC AC32
T11 VDDQ VCC AD31
T2 VDDQ VCC AC34
T5 VDDQ VCC AD34
T8 VDDQ VCC AD26
W11 VDDQ VCC AD27
W2 VDDQ VCC AD29
W5 VDDQ VCC AD30
W8 VDDQ VCC AD32
VDDQ VCC AD33
N26 VCC AD35
K26 RSVD VCC AE26
+CPU_CORE VCC VCC
AL27 AE32
VCC_SENSE +CPU_CORE
+1.05VS +VCCIO_OUT
AK27 RSVD
RSVD
VCC
VCC
AE28
AE30
VCC AG28
VCC
100_0402_1%
AG34
Note: VCC
1
R78 2 @ 1 0_0603_5% AE34

0 ohm Resistor should be placed VCC
4.7U_0402_6.3V6M
R79
AF25
VCC AF26
cloose to CPU VCCSENSE AL35 VCC AF27
C 1 VCC_SENSE VCC C
C53
RESISTOR STUFFING OPTIONS ARE @ E17 AF28
2
+VCCIO_OUT AN35 RSVD VCC AF29

PROVIDED FOR TESTING PURPOSES +VCCIO_OUT VCCIO_OUT VCC
A23 AF30
VCCSENSE 2 Note: F22 RSVD VCC AF31
<56> VCCSENSE +VCOMP_OUT VCOMP_OUT VCC
Place the UP resistor close to CPU W32
RSVD VCC
AF32
1
AL16 AF33
R81 J27 RSVD VCC AF34
VSSSENSE 75_0402_1% AL13 RSVD VCC AF35
<11,56> VSSSENSE RSVD VCC AG26
VCC AH26
2
VCC
1
100_0402_1%
R83 1 2 43_0402_5% H_CPU_SVIDALRT# AM28 AH29

<56> VR_SVID_ALRT# VIDALERT VCC
AM29 AG30
<56> VR_SVID_CLK VIDSCLK VCC
R84
AL28 AG32
<56> VR_SVID_DAT VIDSOUT VCC AH32
AP35 VCC AH35
2
VSS VCC
1
2 R88 1 H27 AH25
Note: R87
+1.05VS
150_0402_1% AP34 PWR_DEBUG VCC AH27
VSS VCC
2
Place the UP resistor close to CPU 130_0402_1% AT35
RSVD_TP VCC
AH28
AR35 AH30
R89 T23 AR32 RSVD_TP VCC AH31
2
10K_0402_5% AL26 RSVD_TP VCC AH33
@ AT34 RSVD_TP VCC AH34
1
+VCCIO_OUT AL22 VSS VCC AJ25
AT33 VSS VCC AJ26
VDDQ DECOUPLING AM21 VSS
VSS
VCC
VCC
AJ27
AM25 AJ28
+1.35V_CPU_VDDQ AM22 VSS VCC AJ29
AM20 VSS VCC AJ30
AM24 VSS VCC AJ31
AL19 VSS VCC AJ32
AM23 VSS VCC AJ33
VSS VCC
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
AT32 AJ34
VSS VCC AJ35
1 1 1 1 1 1 VCC
C54
C55
C56
C57
C58
G25
+ C59 VCC H25
B B
220U_2.5V_M VCC J25
2 2 2 2 2 VCC K25
2 +CPU_CORE VCC L25
VCC M25
Y25 VCC N25
Y26 VCC VCC P25
Y27 VCC VCC R25
Y28 VCC VCC T25
Y29 VCC VCC
Y30 VCC U25
Y31 VCC VCC U26
VCC VCC
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
Y32 V25
Y33 VCC VCC V26
1 1 1 1 1 VCC VCC
C60
C61
C62
C63
C64
Y34
Y35 VCC W26
VCC VCC W27
2 2 2 2 2 VCC
ME@
A A
Security Classification Compal Secret Data

PROCESSOR(6/7) PWR
Custom 0.3
LA-9641P
5 4 3 2 1
5 4 3 2 1
Haswell rPGA EDS Haswell rPGA EDS

JCPU1F JCPU1G
D A10 AK34 B34 K10 D
A13 VSS VSS AK5 B4 VSS VSS K2
A16 VSS VSS AL1 B7 VSS VSS K29
A19 VSS VSS AL10 C1 VSS VSS K3
A7 VSS VSS AL21 C28 VSS VSS L11
AA11 VSS VSS AL23 C30 VSS VSS L26
AA25 VSS VSS E22 C32 VSS VSS L6
AA27 VSS VSS AL3 C34 VSS VSS M11
AB1 VSS VSS AL6 D10 VSS VSS M30
AB10 VSS VSS AL7 D13 VSS VSS M32
AA33 VSS VSS AL8 D16 VSS VSS M34
AA35 VSS VSS AL9 D19 VSS VSS M6
AB3 VSS VSS AM10 D22 VSS VSS N1
AC25 VSS VSS AM13 D25 VSS VSS N10
AB6 VSS VSS E25 D31 VSS VSS N3
AD11 VSS VSS AN10 D7 VSS VSS N4
AC29 VSS VSS AN13 E1 VSS VSS N5
C AC31 VSS VSS AN16 E10 VSS VSS N6 C
AD7 VSS VSS AN21 E4 VSS VSS P11
AE1 VSS VSS AN24 E7 VSS VSS P26
AE10 VSS VSS AN27 F10 VSS VSS P5
AE25 VSS VSS AN30 F11 VSS VSS R11
AE35 VSS VSS AP1 F17 VSS VSS R32
AE7 VSS VSS AP16 F21 VSS VSS T1
AE9 VSS VSS AP19 F23 VSS VSS T10
AF11 VSS VSS AP4 F24 VSS VSS T29
AF6 VSS VSS AP7 F26 VSS VSS T3
AF8 VSS VSS W25 F28 VSS VSS T31
AG11 VSS VSS AR10 F30 VSS VSS T33
AE31 VSS VSS AR16 F34 VSS VSS T4
AE33 VSS VSS AR2 F6 VSS VSS T7
AH1 VSS VSS AR25 F8 VSS VSS U11
AH10 VSS VSS AR28 F9 VSS VSS U27
AH2 VSS VSS AR31 G1 VSS VSS V11
AG27 VSS VSS AR34 G11 VSS VSS V28
AG29 VSS VSS AR4 G2 VSS VSS V30
AH3 VSS VSS AR7 G27 VSS VSS V32
AG33 VSS VSS AT10 G29 VSS VSS V34
AG35 VSS VSS AT13 G3 VSS VSS W1
B AH4 VSS VSS AT16 G31 VSS VSS W10 B
AH5 VSS VSS AT19 G33 VSS VSS W3
AH9 VSS VSS AT3 H10 VSS VSS W7
AJ11 VSS VSS AT30 H26 VSS VSS W9
AJ5 VSS VSS AT4 H6 VSS VSS Y11
AK11 VSS VSS AT7 H7 VSS VSS H11
AK25 VSS VSS B10 J11 VSS VSS AL24
AK26 VSS VSS B13 J26 VSS VSS F19
AK28 VSS VSS B16 J28 VSS VSS T26
AK29 VSS VSS B19 J30 VSS VSS AK35
AK30 VSS VSS B2 J32 VSS VSS_SENSE AK33 VSSSENSE <10,56>
AK32 VSS VSS B22 J34 VSS RSVD T15
E19 VSS VSS J6 VSS
VSS K1 VSS
VSS
INTEL_HASWELL_HASWELL 6 OF 9 INTEL_HASWELL_HASWELL 7 OF 9
ME@ ME@
A A

PROCESSOR(7/7) VSS
5 4 3 2 1
5 4 3 2 1
+1.35V +1.35V
3A@1.5V
<7> DDR_A_D[0..63] +VREF_DQ_DIMMA_R
DDR3 SO-DIMM A <7> DDR_A_DQS[0..7]
JDIMM1 +VREF_DQ_DIMMA
<7> DDR_A_DQS#[0..7]
+VREF_DQ_DIMMA 1 2
3 VREF_DQ VSS1 4 DDR_A_D4
VSS2 DQ4 <7> DDR_A_MA[0..15]
2.2U_0603_6.3V4Z
0.1U_0402_16V7K
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5
C65
C66
1 1 DDR_A_D1 7 8
9 DQ1 VSS3 10 DDR_A_DQS#0
@ DDR_A_DM0 11 VSS4 DQS#0 12 DDR_A_DQS0 R48 1 2 2_0402_5% +VREF_DQ_DIMMA
13 DM0 DQS0 14
D 2 2 DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6 D
DQ2 DQ6 1
DDR_A_D3 17 18 DDR_A_D7 C39
19 DQ3 DQ7 20 @
DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12 0.022U_0402_16V7K
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13 2
DQ9 DQ13
1
25 26
DDR_A_DQS#1 27 VSS9 VSS10 28 DDR_A_DM1 R54
Note:
DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST# @ VREF trace width:20 mils at least
DQS1 RESET# DDR3_DRAMRST# <13,6> 24.9_0402_1%
31 32
DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14 Spacing:20mils to other signal/planes
2
DQ10 DQ14
DDR_A_D11 35
DQ11 DQ15
36 DDR_A_D15 Place near DIMM scoket
37 38
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21
43 DQ17 DQ21 44
DDR_A_DQS#2 45 VSS15 VSS16 46 DDR_A_DM2
DDR_A_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_A_D22 +1.35V +VREF_CA_R
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
DDR_A_D19 53 DQ18 DQ23 54
DQ19 VSS19
1
55 56 DDR_A_D28
Note:
DDR_A_D25 59 DQ24 DQ29 60 R40 VREF trace width:20 mils at least
61 DQ25 VSS21 62 DDR_A_DQS#3 1K_0402_1%
DDR_A_DM3 63 VSS22 DQS#3 64 DDR_A_DQS3 Spacing:20mils to other signal/planes
2
DM3 DQS3 +1.35V
65
VSS23 VSS24
66 Place near DIMM scoket
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31 +VREF_CA 2_0402_5% 2 1 R47 RP18
71 DQ27 DQ31 72 8 1
VSS25 VSS26 1 +VREF_DQ_DIMMA
C37 7 2
@ +VREF_DQ_DIMMB 6 3
1
0.022U_0402_16V7K 5 4
C DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA 2 C
<7> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <7>
1
75 76 R44 1K_0804_8P4R_1%
77 VDD1 VDD2 78 DDR_A_MA15 1K_0402_1% R45
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14 @
<7> DDR_A_BS2 24.9_0402_1%
2
81 BA2 A14 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
2
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
Layout Note:
99 A1 A0 100 Place near DIMM
M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1
<7> M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 <7>
<7> M_CLK_DDR#0 M_CLK_DDR#0 103 104 M_CLK_DDR#1
CK0# CK1# M_CLK_DDR#1 <7>
105 106
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <7>
<7> DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS#
BA0 RAS# DDR_A_RAS# <7>
111 112
DDR_A_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMA# +1.35V
<7> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>
<7> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 <7>
117 118
DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1
DDR_CS1_DIMMA# 121 A13 ODT1 122
M_ODT1 <7> EVT Check
<7> DDR_CS1_DIMMA# S1# NC2 1
10U_0603_6.3V6M
C69
10U_0603_6.3V6M
C70
10U_0603_6.3V6M
C71
10U_0603_6.3V6M
C72
10U_0603_6.3V6M
C73
10U_0603_6.3V6M
C74
10U_0603_6.3V6M
C75
10U_0603_6.3V6M
C76
0.1U_0402_16V7K
C77
0.1U_0402_16V7K
C78
0.1U_0402_16V7K
C79
0.1U_0402_16V7K
C80
123 124 1 1 1 1 1 1 1 1 1 1 1 1
125 VDD17 VDD18 126 +VREF_CA + C81 @
NCTEST VREF_CA +VREF_CA <13> 220U_6.3V_M
127 128
VSS27 VSS28
0.1U_0402_16V7K
2.2U_0603_6.3V4Z
DDR_A_D32 129 130 DDR_A_D36 @ @
DQ32 DQ36 2 2 2 2 2 2 2 2 2 2 2 2 2
C67
C68
DDR_A_D33 131 132 DDR_A_D37 1 1
133 DQ33 DQ37 134
DDR_A_DQS#4 135 VSS29 VSS30 136 DDR_A_DM4 @
B DDR_A_DQS4 137 DQS#4 DM4 138 B
139 DQS4 VSS31 140 DDR_A_D38 2 2
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#5
DDR_A_DM5 153 VSS36 DQS#5 154 DDR_A_DQS5
155 DM5 DQS5 156
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
161 DQ43 DQ47 162
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
Layout Note:
167 DQ49 DQ53 168 Place near DIMM
DDR_A_DQS#6 169 VSS41 VSS42 170 DDR_A_DM6
DDR_A_DQS6 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDR_A_D54
DDR_A_D51 177 DQ50 DQ55 178 +0.675VS
179 DQ51 VSS45 180 DDR_A_D60 DDR_A_DM0
DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61 DDR_A_DM1
DDR_A_D57 183 DQ56 DQ61 184 DDR_A_DM2
185 DQ57 VSS47 186 DDR_A_DQS#7 @ @ DDR_A_DM3
VSS48 DQS#7
1U_0402_6.3V6K
C82
1U_0402_6.3V6K
C83
1U_0402_6.3V6K
C84
1U_0402_6.3V6K
C85
DDR_A_DM7 187 188 DDR_A_DQS7 DDR_A_DM4
189 DM7 DQS7 190 DDR_A_DM5
VSS49 VSS50 1 1 1 1
DDR_A_D58 191 192 DDR_A_D62 DDR_A_DM6
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63 DDR_A_DM7
195 DQ59 DQ63 196
197 VSS51 VSS52 198 2 2 2 2
199 SA0 EVENT# 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 <13,17,37> Layout Note:
2.2U_0603_6.3V4Z
0.1U_0402_16V7K
A 201 202 SMB_CLK_S3 A

SA1 SCL SMB_CLK_S3 <13,17,37>
Place near DIMM
C86
C87
1 1 203 204 +0.675VS

VTT1 VTT2
205 206 0.65A@0.75V
@ G1 G2
2 2 FOX_AS0A626-U8SN-7F
ME@
DDRIII-SODIMM SLOT1
Custom 0.3
LA-7981P
5 4 3 2 1
5 4 3 2 1
3A@1.35V
<7> DDR_B_D[0..63]
+1.35V +1.35V
<7> DDR_B_DQS[0..7]
JDIMM2
<7> DDR_B_DQS#[0..7]
+VREF_DQ_DIMMB 1 2
3 VREF_DQ VSS1 4 DDR_B_D4
VSS2 DQ4 <7> DDR_B_MA[0..15]
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 7 DQ0 DQ5 8
DQ1 VSS3
2.2U_0603_6.3V4Z
0.1U_0402_16V7K
@ 9 10 DDR_B_DQS#0
DDR_B_DM0 11 VSS4 DQS#0 12 DDR_B_DQS0
1 1 DM0 DQS0
13 14
VSS5 VSS6
C88
C89
DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
D 2 2 19 DQ3 DQ7 20 D
DDR_B_D8 21 VSS7 VSS8 22 DDR_B_D12
25 DQ9 DQ13 26
DDR_B_DQS#1 27 VSS9 VSS10 28 DDR_B_DM1
DDR_B_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <12,6>
31 32
37 DQ11 DQ15 38 +VREF_DQ_DIMMB_R
Note: +VREF_DQ_DIMMB
43 DQ17 DQ21 44 VREF trace width:20 mils at least
DDR_B_DQS#2 45 VSS15 VSS16 46 DDR_B_DM2
DDR_B_DQS2 47 DQS#2 DM2 48 Spacing:20mils to other signal/planes
49 DQS2 VSS17 50 DDR_B_D22
DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23 R49 1 2 2_0402_5% +VREF_DQ_DIMMB
DDR_B_D19 53 DQ18 DQ23 54
DQ19 VSS19 1
55 56 DDR_B_D28 C40
DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D29 @
DDR_B_D25 59 DQ24 DQ29 60 0.022U_0402_16V7K
61 DQ25 VSS21 62 DDR_B_DQS#3 2
VSS22 DQS#3
1
DDR_B_DM3 63 64 DDR_B_DQS3
65 DM3 DQS3 66 R59
DDR_B_D26 67 VSS23 VSS24 68 DDR_B_D30 @
DQ26 DQ30 24.9_0402_1%
71 DQ27 DQ31 72
2
VSS25 VSS26
<7> DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB

CKE0 CKE1 DDR_CKE3_DIMMB <7>
75 76
C 77 VDD1 VDD2 78 DDR_B_MA15 C
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
<7> DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
<7> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <7>
<7> M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3
CK0# CK1# M_CLK_DDR#3 <7>
105 106
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <7>
<7> DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS# Layout Note:
BA0 RAS# DDR_B_RAS# <7>
111 112
DDR_B_WE# 113 VDD13 VDD14 114 DDR_CS2_DIMMB# Place near DIMM
<7> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <7>
DDR_B_CAS# 115 116 M_ODT2
<7> DDR_B_CAS# CAS# ODT0 M_ODT2 <7>
117 118
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3
A13 ODT1 M_ODT3 <7>
<7> DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122
123 S1# NC2 124
125 VDD17 VDD18 126
NCTEST VREF_CA +VREF_CA <12> +1.35V
0.1U_0402_16V7K
2.2U_0603_6.3V4Z
127 128
DQ32 DQ36
C90
C91
DDR_B_D33 131 132 DDR_B_D37 1 1
133 DQ33 DQ37 134
VSS29 VSS30
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
DDR_B_DQS#4 135 136 DDR_B_DM4 @
DQS#4 DM4
C92
C185
C94
C95
C96
C97
C98
C99
C100
C101
C102
C103
DDR_B_DQS4 137 138 1 1 1 1 1 1 1 1 1 1 1 1
139 DQS4 VSS31 140 DDR_B_D38 2 2
B DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39 B
DDR_B_D35 143 DQ34 DQ39 144 @ @
145 DQ35 VSS33 146 DDR_B_D44 2 2 2 2 2 2 2 2 2 2 2 2
DDR_B_D40 147 VSS34 DQ44 148 DDR_B_D45
DDR_B_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
DDR_B_DM5 153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
161 DQ43 DQ47 162
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
167 DQ49 DQ53 168
Layout Note:
DDR_B_DQS#6 169 VSS41 VSS42 170 DDR_B_DM6 Place near DIMM
DDR_B_DQS6 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDR_B_D54
DDR_B_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_B_D60 +0.675VS
DDR_B_D57 183 DQ56 DQ61 184 DDR_B_DM0
185 DQ57 VSS47 186 DDR_B_DQS#7 DDR_B_DM1
DDR_B_DM7 187 VSS48 DQS#7 188 DDR_B_DQS7 @ @ DDR_B_DM2
DM7 DQS7
1U_0402_6.3V6K
C104
1U_0402_6.3V6K
C105
1U_0402_6.3V6K
C106
1U_0402_6.3V6K
C107
189 190 DDR_B_DM3
DDR_B_D58 191 VSS49 VSS50 192 DDR_B_D62 DDR_B_DM4
DQ58 DQ62 1 1 1 1
DDR_B_D59 193 194 DDR_B_D63 DDR_B_DM5
195 DQ59 DQ63 196 DDR_B_DM6
197 VSS51 VSS52 198 DDR_B_DM7
199 SA0 EVENT# 200 SMB_DATA_S3 2 2 2 2
+3VS VDDSPD SDA SMB_DATA_S3 <12,17,37>
1 2 201 202 SMB_CLK_S3
+3VS SA1 SCL SMB_CLK_S3 <12,17,37>
2.2U_0603_6.3V4Z
0.1U_0402_16V7K
C109
1 R93 10K_0402_5% 203 204 +0.675VS

VTT1 VTT2 0.65A@0.675V
C108
A A
@
1
205 206
Layout Note:
G1 G2 Place near DIMM
2 FOX_AS0A626-U4SN-7F
2
ME@

DDRIII-SODIMM SLOT2
0.3
LA-7981P
5 4 3 2 1
5 4 3 2 1
PCH_RTCX1
W=20mils W=20mils 1 2 PCH_RTCX2

R95 10M_0402_5%
+RTCVCC +RTCBATT
1
R94
1K_0402_5% 0_0402_5%
1 2 R689
Note: @
1 PCH_RTCX1/PCHRTCX2
2
C110 Y1
1U_0603_10V6K Trace length <1000 mils 1 2
32.768KHZ_12.5PF_CM31532768DZFT
D 2 D
1 1
C111 C112
15P_0402_50V8J 15P_0402_50V8J
2 2
+RTCVCC
R96 1 2 1M_0402_5% SM_INTRUDER#
R97 1 2 330K_0402_5% PCH_INTVRMEN U4A LPT_PCH_M_EDS

+RTCVCC CLRP2
SHORT PADS
CLRP2
OPEN SAVE ME RTC REGISTER BC8
INTVRMEN C113 1 PCH_RTCX1 B5 SATA_RXN_0 BE8
RTCX1 SATA_RXP_0
1
：：
(INTEGRATED SUS 1.05V VR) 1U_0603_10V6K SHORT CLEAR ME RTC REGISTER
* H Integrated VRM enable PCH_RTCX2 B4 AW8
RTCX2 SATA_TXN_0 AY8
L Integrated VRM disable
RTC
2
1 2 2 PCH_SRTCRST# B9 SATA_TXP_0
(INTVRMEN should always be pull high.) SRTCRST#
R98 20K_0402_5% BC10
1 2 PCH_RTCRST# SM_INTRUDER# A8 SATA_RXN_1 BE10
R99 20K_0402_5% INTRUDER# SATA_RXP_1
1
1
+3V_PCH
SHORT PADS
CLRP3
CLRP3 PCH_INTVRMEN G10 AV10
C115 INTVRMEN SATA_TXN_1 AW10
OPEN SAVE CMOS SATA_TXP_1
R100 2 @ 1 1K_0402_5% HDA_SYNC 1U_0603_10V6K D9
2
2 RTCRST# BB9
SHORT CLEAR CMOS SATA_RXN_2
+3VS BD9
HDA_BIT_CLK B25 SATA_RXP_2
R101 1 @ 2 1K_0402_5% PCH_GPIO33 HDA_BCLK AY13
HDA_SYNC A22 SATA_TXN_2 AW13
HDA_SYNC SATA_TXP_2
C HDA_SPKR AL10 BC12 C
<42> HDA_SPKR SPKR SATA_RXN_3 BE12
+3VS HDA_RST# C24 SATA_RXP_3
HDA_RST# AR13
1 2 1K_0402_5% L22 SATA_TXN_3
AZALIA
R102 @ HDA_SPKR HDA_SDIN0 AT13
SATA
<42> HDA_SDIN0 HDA_SDI0 SATA_TXP_3
K22
HIGH= Enable ( No Reboot )
* LOW= Disable (Default) / weak internal pull low
ME FALSH HDA_SDI1 BD13 SATA_DTX_C_PRX_N4
SATA_RXN4/PERN1 SATA_DTX_C_PRX_N4 <41>
G22 BB13 SATA_DTX_C_PRX_P4
HDA_SDI2 SATA_RXP4/PERP1 SATA_DTX_C_PRX_P4 <41>
HDD
F22 AV15 SATA_PTX_C_DRX_N4 SATA_PTX_C_DRX_N4 <41>
HDA_SDI3 SATA_TXN4/PETN1 AW15 SATA_PTX_C_DRX_P4
SATA_TXP4/PETP1 SATA_PTX_C_DRX_P4 <41>
ME_FLASH A24 SATA 6G
+3V_PCH <43> ME_FLASH HDA_SDO BC14 SATA_DTX_C_PRX_N5
SATA_RXN5/PERN2 SATA_DTX_C_PRX_N5 <41>
R104 1 @ 2 1K_0402_5% PCH_GPIO33 B17 BE14 SATA_DTX_C_PRX_P5 SATA_DTX_C_PRX_P5 <41> ODD
R105 2 @ 1 1K_0402_5% ME_FLASH DOCKEN#/GPIO33 SATA_RXP5/PERP2
+3V_PCH R106 1 @ 2 10K_0402_5% PCH_GPIO13 C22 AP15 SATA_PTX_C_DRX_N5

HDA_DOCK_RST#/GPIO13 SATA_TXN5/PETN2 SATA_PTX_C_DRX_N5 <41>
* Low = Disabled (Default) AR15 SATA_PTX_C_DRX_P5 SATA_PTX_C_DRX_P5 <41>
SATA_TXP5/PETP2
High = Enabled [Flash Descriptor Security Override]
AY5 SATA_COMP +3VS
SATA_RCOMP
AP3 SATA_ACT# 2 R108 1 10K_0402_5%
SATALED#
2 R110 1 PCH_JTAG_TCK AB3 AT1 HDD_DET#
JTAG_TCK SATA0GP/GPIO21 HDD_DET# <19>
RP12 51_0402_5% PCH_JTAG_TMS AD1 AU2 BBS_BIT0_R HDD_DET# and BBS_BIT0_R pull high by 10P8R
JTAG_TMS SATA1GP/GPIO19 BBS_BIT0_R <19>
<42> HDA_BITCLK_AUDIO 8 1 HDA_BIT_CLK
7 2 HDA_SYNC PCH_JTAG_TDI AE2 BD4
JTAG
<42> HDA_SYNC_AUDIO JTAG_TDI SATA_IREF +1.5VS
6 3 HDA_RST#
B <42> HDA_RST_AUDIO# B
<42> HDA_SDOUT_AUDIO 5 4 ME_FLASH PCH_JTAG_TDO AD3 BA2
JTAG_TDO TP9
33_0804_8P4R_5% F8 BB2
TP25 TP8
C26
TP22 SATA Impedance Compensation
AB6
TP20 +1.5VS
+3V_PCH +3V_PCH +3V_PCH
1 OF 11 SATA_COMP 1 2
DH82LPMS-QC4C-A1_FCBGA695~D 7.5K_0402_1% R107
1
Note:
R119 R311 R121
@ @ @
Trace width:4mils
200_0402_1% 200_0402_1% 200_0402_1%
Place the resistor to PCH <500 mils, to 1.5V <100 mils.Avoid
routing next to clock pins.
2
PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI

1
R122 R123 R124

100_0402_1% 100_0402_1% 100_0402_1%
@ @ @
2
A A

PCH (1/9) SATA,HDA,SPI, LPC, XDP
Custom 0.3
LA-9641P
5 4 3 2 1
5 4 3 2 1
+3VS
RP23
4 5 DAC_BLU
3 6 DAC_GRN
1
2 7 DAC_RED
R125 R126 1 8
2.2K_0402_5% 2.2K_0402_5%
150_0804_8P4R_5%
2
CRT_DDC_CLK
CRT_DDC_DATA
LPT_PCH_M_EDS LPT_PCH_M_EDS
U4B U4E
D D
<5> DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 AW22 DAC_BLU T45 R40 HDMICLK_NB HDMICLK_NB <36>
DMI_RXN_0 <35> DAC_BLU VGA_BLUE DDPB_CTRLCLK
<5> DMI_CTX_PRX_N1 DMI_CTX_PRX_N1 AR20
DMI_RXN_1 AJ35 FDI_CTX_PRX_N0 DAC_GRN U44 R39 HDMIDAT_NB
FDI_RXN_0 FDI_CTX_PRX_N0 <8> <35> DAC_GRN VGA_GREEN DDPB_CTRLDATA HDMIDAT_NB <36>
<5> DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 AP17
DMI_CTX_PRX_N3 AV20 DMI_RXN_2 AL35 FDI_CTX_PRX_N1 DAC_RED V45 R35
<5> DMI_CTX_PRX_N3 DMI_RXN_3 FDI_RXN_1 FDI_CTX_PRX_N1 <8> <35> DAC_RED VGA_RED DDPC_CTRLCLK
<5> DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 AY22 AJ36 FDI_CTX_PRX_P0 FDI_CTX_PRX_P0 <8> CRT_DDC_CLK M43 R36
DMI_RXP_0 FDI_RXP_0 <35> CRT_DDC_CLK VGA_DDC_CLK DDPC_CTRLDATA
<5> DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 AP20
DMI_RXP_1 AL36 FDI_CTX_PRX_P1 CRT_DDC_DATA M45 N40
CRT
FDI_RXP_1 FDI_CTX_PRX_P1 <8> <35> CRT_DDC_DATA VGA_DDC_DATA DDPD_CTRLCLK
<5> DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 AR17
DMI_CTX_PRX_P3 AW20 DMI_RXP_2 AV43 N42 N38
<5> DMI_CTX_PRX_P3 DMI_RXP_3 TP16 <35> CRT_HSYNC VGA_HSYNC DDPD_CTRLDATA
DMI_CRX_PTX_N0 BD21 AY45 N44
<5> DMI_CRX_PTX_N0 BE20 DMI_TXN_0 TP5 <35> CRT_VSYNC VGA_VSYNC H45
DMI_CRX_PTX_N1
<5> DMI_CRX_PTX_N1 DMI_TXN_1 DMI FDI AV45 1 2 U40 DDPB_AUXN
CRT_IREF
DISPLAY
DMI_CRX_PTX_N2 BD17 TP15 R132 649_0402_1% DAC_IREF K43
<5> DMI_CRX_PTX_N2 DMI_TXN_2 DDPC_AUXN
DMI_CRX_PTX_N3 BE18 AW44 U39
<5> DMI_CRX_PTX_N3 DMI_TXN_3 TP10 VGA_IRTN J42
DMI_CRX_PTX_P0 BB21 AL39 FDI_CSYNC DDPD_AUXN
<5> DMI_CRX_PTX_P0 DMI_TXP_0 FDI_CSYNC FDI_CSYNC <5>
DMI_CRX_PTX_P1 BC20 PCH_PWM N36 H43
<5> DMI_CRX_PTX_P1 DMI_TXP_1 <33> PCH_PWM EDP_BKLTCTL DDPB_AUXP
AL40 FDI_INT
LVDS
FDI_INT FDI_INT <5>
DMI_CRX_PTX_P2 BB17 PCH_ENBKL K36 K45
<5> DMI_CRX_PTX_P2 DMI_TXP_2 EDP_BKLTEN DDPC_AUXP
DMI_CRX_PTX_P3 BC18 AT45 +1.5VS
<5> DMI_CRX_PTX_P3 DMI_TXP_3 FDI_IREF G36 J44
PCH_ENVDD
BE16 AU42 EDP_VDDEN DDPD_AUXP
+1.5VS DMI_IREF TP17 K40
DDPB_HPD TMDS_B_HPD <36>
AW17 AU44 PCI_PIRQA# H20
SUSACK# is only used on platform TP12 TP13 PIRQA# K38
AV17 AR44 FDI_RCOMP 1 2 PCI_PIRQB# L20 DDPC_HPD
that support the Deep Sx state. TP7 FDI_RCOMP +1.5VS PIRQB#
R145 7.5K_0402_1% H39
1 2 DMI_RCOMP AY17 PCI_PIRQC# K17 DDPD_HPD
+1.5VS DMI_RCOMP PIRQC#
R135 7.5K_0402_1%
PCI_PIRQD# M20
PIRQD# G17 PCH_GPIO2
R136 1 @ 2 0_0402_5% SUSACK#_R R6 C8 DSWODVREN A12 PIRQE#/GPIO2
<43> SUSACK# SUSACK# DSWVRMEN <23> DGPU_HOLD_RST# GPIO50 F17 PCH_GPIO3
10K_0402_5%2 R138 1 SYS_RST# AM1 L13 PCH_DPWROK 1 R139 2 EC_RSMRST# PCH_GPIO52 B13 PCI PIRQF#/GPIO3
C +3VS SYS_RESET# DPWROK @ 0_0402_5% GPIO52 C
L15 PCH_GPIO4
SYS_PWROK AD7 K3 DGPU_PWR_EN C12 PIRQG#/GPIO4
SYS_PWROK WAKE# PCIE_WAKE# <37,38> <25,43,53,55> DGPU_PWR_EN GPIO54 M15 PCH_GPIO5
PCH_PWROK F10 AN7 PM_CLKRUN# BBS_BIT1 C10 PIRQH#/GPIO5
<43> PCH_PWROK PWROK System Power CLKRUN# GPIO51 AD10 PCI_PME#
AB7 Management U7 SUS_STAT# T20 T21 PCH_GPIO53 A10 PME#
APWROK SUS_STAT#/GPIO61 GPIO53 Y11 PLT_RST#
PLTRST# PLT_RST# <23,37,38,43>
PM_DRAM_PWRGD H3 Y6 PCH_WL_OFF# AL6
<6> PM_DRAM_PWRGD DRAMPWROK SUSCLK/GPIO62 SUSCLK <43> <37> PCH_WL_OFF# GPIO55
1
J2 Y7
<43> EC_RSMRST# RSMRST# SLP_S5#/GPIO63 PM_SLP_S5# <43>
1
DH82LPMS-QC4C-A1_FCBGA695~D 5 OF 11 C494 R156
R148 1 @ 2 0_0402_5% SUSWARN#_R J4 C6 PCH_DPWROK R149 1 @ 2 0_0402_5% DPWROK_EC <43> 100K_0402_5%
<43> SUSWARN# SUSWARN#/SUSPWRNACK/GPIO30 SLP_S4# PM_SLP_S4# <43>
22P_0402_50V8J
2
K1 H1 +3VS
<43> PBTN_OUT# PM_SLP_S3# <43>
2
PWRBTN# SLP_S3#
1 2 AC_PRESENT_R E6 F3 SLP_A# T22 SLP_A# can be left NC when IAMT is
<24,43,48,50> ACIN ACPRESENT/GPIO31 SLP_A#
D1 CH751H-40PT_SOD323-2 not support on the platfrom BBS_BIT1 1 R182 2 10K_0402_5%
PCH_GPIO72 K7 F1 SLP_SUS#
BATLOW#/GPIO72 SLP_SUS# SLP_SUS# <43,47>
RI# N4 AY3 H_PM_SYNC
RI# PMSYNCH H_PM_SYNC <6>
AEPWROK can be connect to DVT ESD request
PWROK if iAMT disable AB10 G5
TP21 SLP_LAN#
D2
SLP_WLAN#/GPIO29
SLP_LAN# can be left NC if no use Boot BIOS Strap (GPIO51)
integrated LAN.
DH82LPMS-QC4C-A1_FCBGA695~D 4 OF 11
SATA_SLPD
BBS_BIT1 (BBS_BIT0) Boot BIOS Location
0 0 LPC
0 1 Reserved (NAND)
1 0 PCI +3VS
B B
RP1
PCI_PIRQA# 8 1
1 1 * SPI PCI_PIRQB# 7 2
GPIO51 has internal pull up. PCI_PIRQC# 6 3
U6 PCI_PIRQD# 5 4
@ MC74VHC1G08DFT2G SC70 5P
3
GPIO55 8.2K_0804_8P4R_5%
1
G
<43,56> VGATE A 4SYS_PWROK PCH_WL_OFF# R158 1 @ 2 1K_0402_5% DGPU_HOLD_RST# 2 R167 1 10K_0402_5%

Y SYS_PWROK <43,6>
PCH_PWROK 2
B
P
DGPU_HOLD_RST# 2 R168 1 10K_0402_5%

5
A16 swap overide Strap/Top-Block @

R157 @ Swap Override jumper
100K_0402_5% +3V_PCH
+3VS Low=A16 swap
+RTCVCC override/Top-Block
2
+3VALW PCI_GNT3# Swap Override enabled

4 5 SUSWARN#_R High=Default *
1
3 6 PCIE_WAKE#
2 7 PCH_GPIO72 R134
1 8 RI# 330K_0402_5%
SUSACK# and SUSWARN# can be tied together if +3VS
EC does not want to involve in the handshake RP10
2
mechanism for the Deep Sleep state entry and exit. 10K_0804_8P4R_5%
DSWODVREN PCH_WL_OFF# 1 R176 2 10K_0402_5%
1
SUSWARN#_R 1 2 SUSACK#_R
R169 @ 0_0402_5% R143
330K_0402_5%
CLKRUN#: @
External pull up to core well is required.
2
+3V_PCH RP13
6 5 +3VS
+3VS PCH_GPIO2 7 4 PCH_GPIO4
A A
DGPU_PWR_EN 8 3 PCH_GPIO5
：
DSWODVREN - On Die DSW VR Enable PCH_GPIO3 9 2 PCH_GPIO52
：
1 R172 2 8.2K_0402_5% PM_CLKRUN# 10 1
* H Enable (DEFAULT)
L Disable
+3VS
1 R173 2 200K_0402_5% AC_PRESENT_R
10K_1206_10P8R_5%
2 R312 1 10K_0402_5% EC_RSMRST#

PCH (2/9) PCIE, SMBUS, CLK
Custom 0.3
LA-9641P
5 4 3 2 1
5 4 3 2 1
D D
+3V_PCH
R177 2 1 10K_0402_5%
R178 1 @ 2 0_0402_5%
CLK_REQ_VGA# <24>
PEG_CLKREQ#_R
LPT_PCH_M_EDS
U4C
Y43 AB35 CLK_PCIE_VGA#_R R186 1 2 0_0402_5% CLK_PCIE_VGA#

CLKOUT_PCIE_N_0 CLKOUT_PEG_A CLK_PCIE_VGA# <23>
SW set GPO Y45 AB36 CLK_PCIE_VGA_R R188 1 2 0_0402_5% CLK_PCIE_VGA
CLKOUT_PCIE_P_0 CLKOUT_PEG_A_P CLK_PCIE_VGA <23>
R181 2 @ 1 10K_0402_5% PCH_GPIO73 AB1 AF6 PEG_CLKREQ#_R
+3V_PCH PCIECLKRQ0#/GPIO73 PEGA_CLKRQ#/GPIO47
AA44 Y39
AA42 CLKOUT_PCIE_N_1 CLKOUT_PEG_B SW set GPO
CLKOUT_PCIE_P_1 Y38
R184 2 @ 1 10K_0402_5% PCH_GPIO18 AF1 CLKOUT_PEG_B_P CLK_BUF_DMI# R183 2 1 10K_0402_5%
+3VS PCIECLKRQ1#/GPIO18 U4 PCH_GPIO56 R191 2 @ 1 10K_0402_5% CLK_BUF_DMI R192 2 1 10K_0402_5%
PEGB_CLKRQ#/GPIO56 +3V_PCH
R313 1 2 0_0402_5% CLK_PCIE_WLAN#_R AB43
<37> CLK_PCIE_WLAN# CLKOUT_PCIE_N_2 AF39 CLK_CPU_DMI#
CLKOUT_DMI CLK_CPU_DMI# <6>
WLAN R189 1 2 0_0402_5% CLK_PCIE_WLAN_R AB45 CLK_BUF_BCLK# R193 2 1 10K_0402_5%
<37> CLK_PCIE_WLAN CLKOUT_PCIE_P_2 AF40 CLK_CPU_DMI CLK_BUF_BCLK R194 2 1 10K_0402_5%
2 1 10K_0402_5% AF3 CLKOUT_DMI_P CLK_CPU_DMI <6>
+3VS R195
PCIECLKRQ2#/GPIO20/SMI# AJ40 CLK_CPU_SSC_DPLL#
C <37> CLKREQ_WLAN# CLKOUT_DP CLK_CPU_SSC_DPLL# <6> C
R185 1 2 0_0402_5% CLK_PCIE_LAN#_R AD43 AJ39 CLK_CPU_SSC_DPLL CLK_BUF_DOT96# R197 2 1 10K_0402_5%
<38> CLK_PCIE_LAN# CLKOUT_PCIE_N_3 CLKOUT_DP_P CLK_CPU_SSC_DPLL <6>
R187 1 2 0_0402_5% CLK_PCIE_LAN_R AD45 CLK_BUF_DOT96 R199 2 1 10K_0402_5%
<38> CLK_PCIE_LAN 2 1 10K_0402_5% T3 CLKOUT_PCIE_P_3 AF35
LAN +3V_PCH R201 CLK_CPU_DPLL#
PCIECLKRQ3#/GPIO25 CLKOUT_DPNS AF36 CLK_CPU_DPLL CLK_CPU_DPLL# <6>
<38> CLKREQ_LAN# AF43 CLKOUT_DPNS_P CLK_CPU_DPLL <6> CLK_BUF_CKSSCD# R202 2 1 10K_0402_5%
AF45 CLKOUT_PCIE_N_4 AY24 CLK_BUF_DMI# CLK_BUF_CKSSCD R203 2 1 10K_0402_5%
PCH_GPIO26 V3 CLKOUT_PCIE_P_4 CLKIN_DMI AW24 CLK_BUF_DMI
PCIECLKRQ4#/GPIO26 CLOCK SIGNAL CLKIN_DMI_P
AE44 AR24 CLK_BUF_BCLK# CLK_PCH_14M R205 2 1 10K_0402_5%
AE42 CLKOUT_PCIE_N5 CLKIN_GND AT24 CLK_BUF_BCLK
PCH_GPIO44 AA2 CLKOUT_PCIE_P_5 CLKIN_GND_P
PCIECLKRQ5#/GPIO44 H33 CLK_BUF_DOT96#
AB40 CLKIN_DOT96N G33 CLK_BUF_DOT96
AB39 CLKOUT_PCIE_N_6 CLKIN_DOT96P
PCH_GPIO45 AE4 CLKOUT_PCIE_P_6 BE6 CLK_BUF_CKSSCD#
PCIECLKRQ6#/GPIO45 CLKIN_SATA BC6 CLK_BUF_CKSSCD
AJ44 CLKIN_SATA_P CLOCK TERMINATION for FCIM and need close to PCH
CLKOUT_PCIE_N_7 F45 CLK_PCH_14M
AJ42 REFCLK14IN D17 CLK_PCI_LPBACK
CLKOUT_PCIE_P_7 CLKIN_33MHZLOOPBACK
PCH_GPIO46 Y3 AM43 XTAL25_IN
PCIECLKRQ7#/GPIO46 XTAL25_IN AL44 XTAL25_OUT
AH43 XTAL25_OUT
CLKOUT_ITPXDP C40
AH45 CLKOUTFLEX0/GPIO64
CLKOUT_ITPXDP_P F38
CLK_PCI_LPBACK 22_0402_5% 1 2 R209 CLK_PCI_LPBACK_R D44 CLKOUTFLEX1/GPIO65
CLKOUT_33MHZ0 F36
22_0402_5% 1 2 R211 CLK_PCI_EC_R E44 CLKOUTFLEX2/GPIO66
<43> CLK_PCI_EC CLKOUT_33MHZ1 F39 PCH_GPIO67
CLK_PCI_DB_R B42 CLKOUTFLEX3/GPIO67 PCH_GPIO67 <19>
CLKOUT_33MHZ2 AM45
B ICLK_IREF +1.5VS B
F41
SW set GPO CLKOUT_33MHZ3 AD39
A40 TP19 AD38
+3V_PCH CLKOUT_33MHZ4 TP18
AN44 PCH_CLK_BIASREF 1 R214 2
DIFFCLK_BIASREF +1.05V_+1.5V_RUN
7.5K_0402_1%
4 5 PCH_GPIO26
3 6 PCH_GPIO44
2 7 PCH_GPIO45 DH82LPMS-QC4C-A1_FCBGA695~D 2 OF 11
1 8 PCH_GPIO46
@ XTAL25_IN
RP9
10K_0804_8P4R_5% XTAL25_OUT 1 2
R215 1M_0402_5%
3 4
OSC NC
2 1
NC OSC
Y2
1 25MHZ_10PF_7V25000014 1
C118 C119
12P_0402_50V8J R02 12P_0402_50V8J
2 2
A A

PCH (3/9) DMI,FDI,PM,
5 4 3 2 1
5 4 3 2 1
LPT_PCH_M_EDS
U4D
D Q11A D
2N7002DW-T/R7_SOT363-6 6 1 SMB_CLK_S3
N7 PCH_GPI011 2 R216 1 SMB_CLK_S3 <12,13,37>
SMBALERT#/GPIO11 +3V_PCH
LPC_AD0 A20 10K_0402_5%
<43> LPC_AD0 LAD_0
SMBus R10 PCH_SMBCLK DIMM1
2
LPC_AD1 C20 SMBCLK
<43> LPC_AD1 LAD_1
SMBDATA
U11 PCH_SMBDATA
+3VS DIMM2
5
LPC_AD2 A18
<43> LPC_AD2
MINI CARD
LPC
LAD_2 N8 PCH_GPIO60 @2 R221 1
SML0ALERT#/GPIO60 +3V_PCH
<43> LPC_AD3 LPC_AD3 C18 1K_0402_5% 3 4 SMB_DATA_S3
LAD_3 U8 PCH_SML0CLK SMB_DATA_S3 <12,13,37>
2N7002DW-T/R7_SOT363-6
LPC_FRAME# B21 SML0CLK Q11B
<43> LPC_FRAME# LFRAME# R7 PCH_SML0DATA Q130A
+3VS D21 SML0DATA SW set GPO 2N7002DW-T/R7_SOT363-6 6 1 EC_SMB_CK2
LDRQ0# H6 PCH_HOT# 2 R222 1 10K_0402_5% EC_SMB_CK2 <24,33,40,43>
SML1ALERT#/PCHHOT#/GPIO74 +3V_PCH
R223 2 1 10K_0402_5% G20
LDRQ1#/GPIO23 K6 SML1CLK VGA
Translator
2
SERIRQ AL11 SML1CLK/GPIO58
<43> SERIRQ SERIRQ
SML1DATA/GPIO75
N11 SML1DATA
+3VS EC
5
thermal sensor
AF11 3 4 EC_SMB_DA2
SPI_CLK_PCH R240 1 2 CL_CLK EC_SMB_DA2 <24,33,40,43>
33_0402_5% SPI_CLK_PCH_R AJ11 2N7002DW-T/R7_SOT363-6
SPI_CLK AF10 Q130B
SPI_CS# AJ7 C-Link CL_DATA
SPI_CS0# AF7 +3V_PCH
SPI_SB_CS1# AL7 CL_RST#
SPI_CS1#
AJ10
SPI_CS2#
2
SPI
BA45
SPI_SI AH1 TP1 R226 R227
SPI_MOSI BC45 2.2K_0402_5%
Thermal TP2 2.2K_0402_5%
C SPI_SO AH3 C
SPI_MISO BE43
1
SPI_WP# R246 1 2 0_0402_5% SPI_IO2 AJ4 TP4 PCH_SML0CLK
SPI_IO2 BE44
SPI_HOLD# R245 1 2 0_0402_5% SPI_IO3 AJ2 TP3 PCH_SML0DATA
SPI_IO3 AY43 PCH_TD_IREF 1 2
TD_IREF R228 8.2K_0402_1% +3VS
+3V_ROM
DH82LPMS-QC4C-A1_FCBGA695~D 3 OF 11 RP16
R229 1 2 1K_0402_5% SPI_IO2 PCH_SMBDATA 8 1
SMB_CLK_S3 7 2
+3V_PCH
SMB_DATA_S3 6 3
R230 1 2 1K_0402_5% SPI_IO3 PCH_SMBCLK 5 4
8MB SPI ROM FOR ME

2.2K_0804_8P4R_5%
& Non-share ROM.

+3V_ROM
+3VS
+3VS RP17
@ EC_SMB_CK2 8 1
SPI_CLK_PCH_R PJ2 1 2 JUMP_43X39 EC_SMB_DA2 7 2
1 2 SML1DATA 6 3
+3V_PCH
+3VALW SML1CLK 5 4
1
U8 @
R237 SPI_CS# 1 8 PJ3 1 2 JUMP_43X39 2.2K_0804_8P4R_5%
33_0402_5% SPI_SO 2 CS# VCC 7 SPI_HOLD# 1 2
@ SPI_WP# 3 SO HOLD# 6 SPI_CLK_PCH
4 WP# SCLK 5 SPI_SI
2
GND SI
B 16M W25Q64DVSSIQ SOIC 8P B
C120
22P_0402_50V8J
@
R124;c190 close
to U4.T3 pin RP2
Share ROM
SROM@
SPI_SO 1 8 EC_SPI_SO
2 7 EC_SPI_SO <43>
SPI_SI EC_SPI_SI
SPI_CLK_PCH 3 6 EC_SPI_CLK EC_SPI_SI <43>
SPI_CS# 4 5 EC_SPI_CS# EC_SPI_CLK <43>
EC_SPI_CS# <43>
0_0804_8P4R_5%
A A

PCH (4/9) LVDS,CRT,DP,HDMI
5 4 3 2 1
5 4 3 2 1
D D
U4I LPT_PCH_M_EDS
USB DEBUG=PORT1 AND PORT9
AW31 B37 USB20_N0
AY31 PERN1/USB3RN3 USB2N0 D37 USB20_P0 USB20_N0 <46>
PERP1/USB3RP3 USB2P0 A38 USB20_N1 USB20_P0 <46> LEFT USB
BE32 USB2N1 C38 USB20_P1 USB20_N1 <46> (USB 3.0)
BC32 PETN1/USB3TN3 USB2P1 A36 USB20_N2 USB20_P1 <46> LEFT USB
PETP1/USB3TP3 USB2N2 C36 USB20_P2 USB20_N2 <46>
PCIE_PRX_DTX_N2 AT31 USB2P2 A34 USB20_N3 USB20_P2 <46> Touch panel
<37> PCIE_PRX_DTX_N2 PERN2/USB3RN4 USB2N3 USB20_N3 <34>
PCIE_PRX_DTX_P2 AR31 C34 USB20_P3 USB Camera
<37> PCIE_PRX_DTX_P2 PERP2/USB3RP4 USB2P3 USB20_P3 <34>
WLAN B33
<37> PCIE_PTX_C_DRX_N2
C125 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_N2 BD33
PETN2/USB3TN4
USB2N4
USB2P4
D33 EHCI1
C123 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_P2 BB33 F31
<37> PCIE_PTX_C_DRX_P2 PETP2/USB3TP4 USB2N5 G31
USB2P5 K31
PCIE_PRX_DTX_N3 AW33 USB2N6 L31
<38> PCIE_PRX_DTX_N3 PERN_3 USB2P6
<38> PCIE_PRX_DTX_P3 PCIE_PRX_DTX_P3 AY33 G29
PERP_3 USB2N7 H29
LAN USB2P7
C122 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_N3 BE34 A32
<38> PCIE_PTX_C_DRX_N3 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_P3 BC34 PETN_3 USB2N8 C32
C124
<38> PCIE_PTX_C_DRX_P3 PETP_3 USB2P8 A30 USB20_N9
AT33 USB2N9 C30 USB20_P9 USB20_N9 <46>
AR33 PERN_4 USB2P9 B29 USB20_N10 USB20_P9 <46> RIGHT USB
PERP_4 USB2N10 D29 USB20_N10 <37>
USB20_P10 WLAN
BE36 USB2P10 A28 USB20_N11 USB20_P10 <37>
C BC36 PETN_4 USB2N11 C28 USB20_P11 USB20_N11 <44> C
PETP_4 USB2P11 G26 USB20_P11 <44> CARD READER EHCI2
USB2N12
PCIe
AW36 F26
USB
AV36 PERN_5 USB2P12 F24
PERP_5 USB2N13 G24
BD37 USB2P13
BB37 PETN_5
PETP_5 AR26 USB3_RX1_N
AY38 USB3RN1 AP26 USB3_RX1_P USB3_RX1_N <46>
AW38 PERN_6 USB3RP1 BE24 USB3_TX1_N USB3_RX1_P <46>
PERP_6 USB3TN1 BD23 USB3_TX1_P USB3_TX1_N <46>
BC38 USB3TP1 AW26 USB3_TX1_P <46>
USB3_RX2_N
BE38 PETN_6 USB3RN2 AV26 USB3_RX2_N <46>
USB3_RX2_P
PETP_6 USB3RP2 BD25 USB3_RX2_P <46>
USB3_TX2_N
AT40 USB3TN2 BC24 USB3_TX2_P USB3_TX2_N <46>
AT39 PERN_7 USB3TP2 AW29 USB3_TX2_P <46>
PERP_7 USB3RN5 AV29
BE40 USB3RP5 BE26
BC40 PETN_7 USB3TN5 BC26
PETP_7 USB3TP5 AR29
AN38 USB3RN6 AP29
AN39 PERN_8 USB3RP6 BD27
PERP_8 USB3TN6 BE28
BD42 USB3TP6
PETN_8 CAD NOTE:
BD41 K24 USBRBIAS 1 R242 2
PETP_8 USBRBIAS# K26 22.6_0402_1%
Route single-end 50-ohms and max 500-mils length.
USBRBIAS Avoid routing next to clock pins or under stitching capacitors.
BE30 M33 Recommended minimum spacing to other signal traces is 15 mils.
+1.5VS PCIE_IREF TP24 L33
TP23
BC30 P3 USB_OC0#
TP11 OC0#/GPIO59 V1 USB_OC1# USB_OC0# <46>
B OC1#/GPIO40 U2 USB_OC2# B
BB29 OC2#/GPIO41 P1 USB_OC3#
TP6 OC3#/GPIO42 M3 USB_OC4#
OC4#/GPIO43 T1 USB_OC5# USB_OC4# <46>
1 2 PCH_PCIE_RCOMP BD29 OC5#/GPIO9 N2 USB_OC6#
+1.5VS PCIE_RCOMP OC6#/GPIO10
R244 7.5K_0402_1% M1 USB_OC7#
OC7#/GPIO14
+3V_PCH
RP14
USB_OC1# 6 5
USB_OC2# 7 4 USB_OC4#
10 1 USB_OC0#
+3V_PCH
10K_1206_10P8R_5%
A A

PCH (5/9) PCI, USB
5 4 3 2 1
5 4 3 2 1
+3V_PCH
SW set GPO
@ 1 R273 2 10K_0402_5% PCH_GPIO24
@ 1 R261 2 10K_0402_5% EC_SCI#
GPIO8 Weak internal pull-high but requires an

external pull down.
@ 1 R247 2 10K_0402_5% EC_SMI#
SW set GPO U4F LPT_PCH_M_EDS
D PCH_GPIO0 AT8 D
BMBUSY#/GPIO0
@ 1 R248 2 10K_0402_5% PCH_GPIO1 F13
TACH1/GPIO1
+3VS @ 1 R249 2 10K_0402_5% PCH_GPIO6 A14
TACH2/GPIO6
G15 CPU/Misc
EC_SCI#
Remove strap description <43> EC_SCI# TACH3/GPIO7
inform SW set GPO <43> EC_SMI# EC_SMI# Y1
GPIO8 +1.05VS
+3V_PCH 1 R252@ 2 10K_0402_5% PCH_GPIO12 K13
+3V_PCH LAN_PHY_PWR_CTRL/GPIO12 AN10 GATEA20
TP14 GATEA20 <43>
1 R253 2 1K_0402_5% AB11
GPIO15
2
R256 1 @ 2 10K_0402_5% AY1 PCH_PECI_R 1 @ 2
<43> EC_LID_OUT# PECI H_PECI <43,6>
PCH_GPIO16 AN2 0_0402_5% R255 R258
R260 1 @ 2 1K_0402_5% PCH_GPIO28 SATA4GP/GPIO16 AT6 KBRST#
<55> DGPU_PWROK RCIN# KBRST# <43> 1K_0402_5%
GPIO
+3VS 1 R259@ 2 10K_0402_5% C14
TACH0/GPIO17
@
PU on power side AV3
H_CPUPWRGD <6>
1
PCH_BT_ON# BB4 PROCPWRGD
<37> PCH_BT_ON# SCLOCK/GPIO22 AV1 PCH_THRMTRIP#_R 1 2 H_THRMTRIP# <6>
PCH_GPIO24 Y10 THRMTRIP# R262 390_0402_5%
GPIO24 AU4 CPU_PLTRST#
PLTRST_PROC# CPU_PLTRST# <6>
PCH_GPIO27 R11
GPIO27 N10
+3VALW PCH_GPIO28 AD11 VSS
GPIO28
INTEL_BT_OFF# AN6
<37> INTEL_BT_OFF# GPIO34
R266 1 2 10K_0402_5%
1 R265 2 10K_0402_5% PCH_GPIO35 AP1
R267 1 @ 2 10K_0402_5% PCH_GPIO27 @ GPIO35/NMI#
PCH_GPIO36 AT3
SATA2GP/GPIO36
PCH_GPIO37 AK1
SATA3GP/GPIO37
SW set GPO PCH_GPIO38 AT7
C SLOAD/GPIO38 C
+3VS R268 1 @ 2 10K_0402_5% PCH_GPIO39 AM3 A2

SDATAOUT0/GPIO39 VSS A41
+3VS +3VS PCH_GPIO48 AN4 VSS A43
SDATAOUT1/GPIO48 VSS A44
PCH_GPIO49 AK3 VSS B1
SATA5GP/GPIO49 VSS
1
R270 R271 B2
R272 1 @ 2 10K_0402_5% PCH_GPIO57 U12 VSS B44
200K_0402_5% 200K_0402_5% +3V_PCH GPIO57 VSS B45
Need Update
@ @ ODD_EN C16 VSS BA1
<41> ODD_EN TACH4/GPIO68 VSS BC1
2
PCH_GPIO37 PCH_GPIO36 PCH_GPIO69 D13 VSS BD1

TACH5/GPIO69 VSS BD2
VSS
1
PCH_GPIO70 G13 BD44

TACH6/GPIO70 VSS BD45
R274 R275 PCH_GPIO71 H15 VSS BE2
10K_0402_5% TACH7/GPIO71 VSS BE3
10K_0402_5%
VSS D1
2
BE41 VSS E1
BE5 VSS NCTF VSS E45
C45 VSS VSS A4
A5 VSS VSS
VSS
BIOS Request SKU ID
+3VS +3VS
10K_0402_5%
PCH_GPIO69 Function
@ R276
0
2
1
10K_0402_5%
10K_0402_5%
1
PCH_GPIO69
B R277 R278 B
10K_0402_5%
@ @ +3VS
1
@ R279
PCH_GPIO38 2 1 PCH_GPIO16
R280 10K_0402_5%
PCH_GPIO67 PCH_GPIO67 <16> 2 1 PCH_GPIO49
1
R281 10K_0402_5%
2
1
10K_0402_5%
10K_0402_5%
R282 R283
+3VS +3VS
1
PCH_GPIO38 PCH_GPIO67 Function
2
10K_0402_5%
10K_0402_5%
PCH_GPIO70 Function
MARS@
* 0 0 MUXLESS 0 R286 @ R287
1
PCH_GPIO71 PCH_GPIO70
0 1 Reserved PCH_GPIO71
2
R288 R289
1 0 DIS 0 SUN PRO 200K_0402_5% 200K_0402_5%
1 Mars XT SUN@ @
1 1 UMA
1
RP15
A A
PCH_GPIO48 6 5 +3VS
INTEL_BT_OFF# 7 4 HDD_DET# HDD_DET# <14>
GATEA20 8 3 BBS_BIT0_R BBS_BIT0_R <14>
KBRST# 9 2 PCH_GPIO0
+3VS 10 1 PCH_BT_ON#
10K_1206_10P8R_5%
2011/06/15
Compal Secret Data
2012/07/11 Title
Issued Date Deciphered Date
PCH (6/9) GPIO, CPU, MISC
Custom 0.3
LA-9641P
5 4 3 2 1
5 4 3 2 1
LH1
1_0603_1%
LH1
D +VCCADAC 2 1 D
+1.5VS
BLM18PG181SN1_0603
~@
0.01U_0402_16V7K
0.1U_0402_16V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
1 1 1 1
C128
C133
C126
C127
@
2 2 2 2
PCH Power Rail Table

U4G LPT_PCH_M_EDS
+1.05VS P45 Voltage Rail Voltage S0 Iccmax Current (A)

VCCADAC1_5 +1.05V_+1.5V_RUN
AA24 P43
AA26 VCC CRT DAC VSS
VCC VCC 1.05V 1.29 A
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 AD20 M31
VCC VCCADACBG3_3 +3VS +1.05VS
C129
C130
C131
C132
AD22
AD24 VCC
VCC VCCIO 1.05V 3.629 A
AD26 BB44
2 2 2 2 VCC VCCVRM
1U_0402_6.3V6K
AD28 1
VCC FDI
C134
AE18 AN34 VCCADAC1_5 1.5V 0.070 A
AE20 VCC VCCIO +3VS
AE22 VCC AN35
AE24 VCC VCCIO 2
VCC VCCADAC3_3 3.3V 0.0133 A
AE26 R30
AG18 VCC HVCMOS VCC3_3_R30 R32
VCC VCC3_3_R32
0.1U_0402_16V7K
AG20 1 VCCCLK 1.05V 0.306 A
AG22 VCC Y12 +PCH_USB_DCPSUS1 +3V_PCH
VCC DCPSUS1
0.1U_0402_16V7K
C135
AG24
Y26 VCC AJ30
VCC VCCSUS3_3 2
VCCCLK3_3 3.3V 0.055 A
Core
C136
C AJ32 C
VCCSUS3_3 1
+1.05VS AJ26 +PCH_USB_DCPSUS3 +1.05V_+1.5V_RUN VCCVRM 1.5V 0.179 A
+PCH_VCCDSW U14 USB3 DCPSUS3 AJ28
AA18 DCPSUSBYP DCPSUS3 AK20 2
VCCASW VCCIO +1.05VS
U18 AK26 VCC3_3 3.3V 0.133 A
U20 VCCASW VCCVRM AK28 +1.05V_+1.5V_RUN
VCCASW VCCVRM
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 U22
VCCASW
C137
C138
C139
U24 BE22 VCCASW 1.05V 0.67 A

V18 VCCASW VCCVRM
PCIe/DMI
V20 VCCASW AK18 +1.05V_+1.5V_RUN
2 2 2 VCCASW VCCIO +1.05VS
V22 VCCSUSHDA 3.3V 0.01 A
V24 VCCASW AN11
Y18 VCCASW VCCVRM
Y20 VCCASW SATA AK22
VCCASW VCCIO VCCSPI 3.3V 0.022 A
Y22 +1.05VS
VCCASW AM18
VCCIO AM20
VCCIO VCCSUS3_3 3.3V 0.261 A
AM22
VCCMPHY VCCIO AP22
VCCIO
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
AR22 1 1 1 1 1 VCCDSW3_3 3.3V 0.015 A
VCCIO
C143
C144
C145
C146
C147
AT22
VCCIO
2 2 2 2 2
V_PROC_IO 1.05V 0.004 A
1 2 +PCH_VCCDSW +1.5VS +1.05V_+1.5V_RUN

R290 5.1_0402_1%
+PCH_VCCDSW_R
B B
R291 2 1 0_0603_5%
1U_0402_6.3V6K
1
C149
A A

PCH (7/9) PWR
5 4 3 2 1
5 4 3 2 1
+3V_PCH
+PCH_VCCDSW3_3
R307
1 2 +3VALW
LPT_PCH_M_EDS
U4H
0.1U_0402_16V7K
1 0_0402_5%
D +3V_PCH D
C154
0.1U_0402_16V7K
1
R24 R20
VCCSUS3_3 VCCSUS3_3 2
C155
R26 R22
R28 VCCSUS3_3 VCCSUS3_3
+1.05VS VCCSUS3_3 GPIO/LPC 2
0.1U_0402_16V7K
1 U26
VCCSUS3_3 A16 +PCH_VCCDSW3_3
VCCDSW3_3 +3VS PCH Power Rail Table
C152
M24
VSS AA14 +PCH_VCCSST 1 2
2 +3VS U35 DCPSST C156 0.1U_0402_16V7K
VCCUSBPLL
0.1U_0402_16V7K
1 AE14 Voltage Rail Voltage S0 Iccmax Current (A)
USB
L24 VCC3_3 AF12
VCC3_3 VCC3_3
C153
AG14
VCC3_3 +3V_PCH
0.1U_0402_16V7K
U30 1 VCC 1.05V 1.29 A
2 0.1U_0402_16V7K +1.05VS V28 VCCIO
1 VCCIO
C158
V30 U36
VCCIO VCCIO +1.05VS
C157
Y30 VCCIO 1.05V 3.629 A
VCCIO +3V_PCH 2
2 +1.05V_+1.5V_RUN +PCH_USB_DCPSUS2 Y35 Azalia
DCPSUS2
1U_0402_6.3V6K
0.1U_0402_16V7K
1 A26 1 VCCADAC1_5 1.5V 0.070 A
VCCSUSHDA
C159
AF34
VCCVRM
C160
+RTCVCC
10U_0603_6.3V6M
1U_0402_6.3V6K
1 +PCH_VCC AP45 K8 1 VCCADAC3_3 3.3V 0.0133 A
2 VCC VCCSUS3_3 2
C140
C162
+PCH_VCCCLK Y32 A6
VCCCLK VCCRTC C163
2 RTC 2
VCCCLK 1.05V 0.306 A
+PCH_VCCCLK3_3 M29 P14 +PCH_DCPRTC 0.1U_0402_16V7K
VCCCLK3_3 DCPRTC
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V6K
P16 1 2 1 1 1
DCPRTC
C166
L29 VCCCLK3_3 3.3V 0.055 A
VCCCLK3_3
C164
C165
L26 AJ12 +PCH_VPROC
M26 VCCCLK3_3 V_PROC_IO AJ14 +3V_ROM 2 2 2
VCCCLK3_3
CPU
V_PROC_IO VCCVRM 1.5V 0.179 A
U32 Share ROM
VCCCLK3_3
ICC
V32 AD12 VCC3_3 3.3V 0.133 A
C VCCCLK3_3 SPI VCCSPI C
1U_0402_6.3V6K
+PCH_VCCCLK AD34 1
VCCCLK
C167
P18 +PCH_VCCCFUSE VCCASW 1.05V 0.67 A
AA30 VCC P20
AA32 VCCCLK VCC
VCCCLK L17 2
VCCASW +1.05VS VCCSUSHDA 3.3V 0.01 A
AD35
VCCCLK R18
AG30 VCCASW +1.05VS
VCCCLK VCCSPI 3.3V 0.022 A
AG32
VCCCLK AW40 +PCH_VPROC R297 1 2
VCCVRM +1.05V_+1.5V_RUN
AD36 0_0805_5% VCCSUS3_3 3.3V 0.261 A
+1.05VS VCCCLK AK30 +3VS
VCC3_3
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V6K
AE30 Thermal 1 1 1
VCCCLK
C171
LH2 AE32 AK32 VCCDSW3_3 3.3V 0.015 A
VCCCLK VCC3_3
C169
C170
1 2 +PCH_VCC
0.1U_0402_16V7K
4.7UH_LQM18FN4R7M00D_20% 1 2 2 2
V_PROC_IO 1.05V 0.004 A
10U_0603_6.3V6M
1U_0402_6.3V6K
C173
1 1 DH82LPMS-QC4C-A1_FCBGA695~D 8 OF 11
C172
C174
2 2
Place near pin AP45
+PCH_VCCCFUSE R299 1 2 +1.05VS

+1.05VS +PCH_VCCCLK 0_0805_5%
1U_0402_6.3V6K
R300 1 2 1
C175
0_0805_5%
B B
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1
C176
C177
C178
C179
C180
@
2 2 2 2 2
Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36
Place near pin AG30,AG32,AE30,AE32
+3VS +PCH_VCCCLK3_3
R302 1 2
0_0805_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1
C181
C182
C183
C184
2 2 2 2
Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32
A A

2011/06/15 2012/07/11 Title
Issued Date Deciphered Date PCH (8/9) PWR
Custom 0.3
LA-9641P
5 4 3 2 1
5 4 3 2 1
D D
U4J LPT_PCH_M_EDS
AL34 K39 U4K LPT_PCH_M_EDS

AL38 VSS VSS L2
AL8 VSS VSS L44 AA16 B19
AM14 VSS VSS M17 AA20 VSS VSS B23
AM24 VSS VSS M22 AA22 VSS VSS B27
AM26 VSS VSS N12 AA28 VSS VSS B31
AM28 VSS VSS N35 AA4 VSS VSS B35
AM30 VSS VSS N39 AB12 VSS VSS B39
AM32 VSS VSS N6 AB34 VSS VSS B7
AM16 VSS VSS P22 AB38 VSS VSS BA40
AN36 VSS VSS P24 AB8 VSS VSS BD11
AN40 VSS VSS P26 AC2 VSS VSS BD15
AN42 VSS VSS P28 AC44 VSS VSS BD19
C AN8 VSS VSS P30 AD14 VSS VSS AY36 C
AP13 VSS VSS P32 AD16 VSS VSS AT43
AP24 VSS VSS R12 AD18 VSS VSS BD31
AR2 VSS VSS R2 AD40 VSS VSS BD7
AK16 VSS VSS R34 AD6 VSS VSS D25
AT10 VSS VSS R38 AD8 VSS VSS AV7
AT15 VSS VSS R44 AE16 VSS VSS F15
AT17 VSS VSS R8 AE28 VSS VSS F20
AT20 VSS VSS T43 AF38 VSS VSS F29
AT26 VSS VSS U10 AF8 VSS VSS F33
AT29 VSS VSS U16 AG16 VSS VSS BC16
AT36 VSS VSS U28 AG2 VSS VSS D4
AT38 VSS VSS U34 AG26 VSS VSS G2
D42 VSS VSS U38 AG28 VSS VSS G38
AV13 VSS VSS U42 AG44 VSS VSS G44
AV22 VSS VSS U6 AJ16 VSS VSS G8
AV24 VSS VSS V14 AJ18 VSS VSS H10
BB25 VSS VSS V43 AJ24 VSS VSS H22
AV40 VSS VSS W2 AJ34 VSS VSS H24
AV6 VSS VSS W44 AJ38 VSS VSS H26
AW2 VSS VSS Y14 AJ6 VSS VSS H31
F43 VSS VSS Y16 AJ8 VSS VSS H36
AY10 VSS VSS Y24 AK14 VSS VSS H40
AY15 VSS VSS Y28 AK24 VSS VSS H7
AY20 VSS VSS Y34 AK43 VSS VSS K10
AY26 VSS VSS Y36 AK45 VSS VSS K15
AY29 VSS VSS Y40 AL12 VSS VSS K20
AY7 VSS VSS Y8 AL2 VSS VSS K29
B B11 VSS VSS BC22 VSS VSS K33 B
B15 VSS BB42 VSS VSS BC28
VSS VSS VSS
DH82LPMS-QC4C-A1_FCBGA695~D DH82LPMS-QC4C-A1_FCBGA695~D
10 OF 11 11 OF 11
A A

PCH (9/9) VSS
5 4 3 2 1
A B C D E
PCIE_CTX_GRX_P[7..0] UV1A PCIE_CRX_GTX_P[7..0]

<5> PCIE_CTX_GRX_P[7..0] PCIE_CRX_GTX_P[7..0] <5>
<5> PCIE_CTX_GRX_N[7..0]
PCIE_CTX_GRX_N[7..0] PART 1 0F 9 PCIE_CRX_GTX_N[7..0]
PCIE_CRX_GTX_N[7..0] <5> LVDS Interface
UV1D
1 1
PCIE_CTX_GRX_P0 AA38 Y33 PCIE_CRX_C_GTX_P0 0.22U_0402_10V6K 1 2 CV1 PX@ PCIE_CRX_GTX_P0 PART 7 0F 9
Y37 PCIE_RX0P PCIE_TX0P Y32
PCIE_CTX_GRX_N0 PCIE_CRX_C_GTX_N0 0.22U_0402_10V6K 1 2 CV2 PX@ PCIE_CRX_GTX_N0
PCIE_RX0N PCIE_TX0N
AK27
RSVD/VARY_BL AJ27
PCIE_CTX_GRX_P1 Y35 W33 PCIE_CRX_C_GTX_P1 0.22U_0402_10V6K 1 2 CV3 PX@ PCIE_CRX_GTX_P1 RSVD/DIGON
W36 PCIE_RX1P PCIE_TX1P W32 PCIE_CRX_C_GTX_N1 LVDS CONTROL
PCIE_CTX_GRX_N1 0.22U_0402_10V6K 1 2 CV4 PX@ PCIE_CRX_GTX_N1
PCIE_RX1N PCIE_TX1N
PCIE_CTX_GRX_P2 W38 U33 PCIE_CRX_C_GTX_P2 0.22U_0402_10V6K 1 2 CV5 PX@ PCIE_CRX_GTX_P2 AK35

V37 PCIE_RX2P PCIE_TX2P U32 PCIE_CRX_C_GTX_N2 TXCBP_DPB3P
PCIE_CTX_GRX_N2 0.22U_0402_10V6K 1 2 CV6 PX@ PCIE_CRX_GTX_N2 AL36
PCIE_RX2N PCIE_TX2N TXCBM_DPB3N
AJ38
PCIE_CTX_GRX_P3 V35 U30 PCIE_CRX_C_GTX_P3 0.22U_0402_10V6K 1 2 CV7 PX@ PCIE_CRX_GTX_P3 TX3P_DPB2P AK37
U36 PCIE_RX3P PCIE_TX3P U29 PCIE_CRX_C_GTX_N3 TX3M_DPB2N
PCIE_CTX_GRX_N3 0.22U_0402_10V6K 1 2 CV8 PX@ PCIE_CRX_GTX_N3
PCIE_RX3N PCIE_TX3N
AH35
TX4P_DPB1P AJ36
PCIE_CTX_GRX_P4 U38 T33 PCIE_CRX_C_GTX_P4 0.22U_0402_10V6K 1 2 CV9 PX@ PCIE_CRX_GTX_P4 TX4M_DPB1N
T37 PCIE_RX4P PCIE_TX4P T32
PCIE_CTX_GRX_N4 PCIE_CRX_C_GTX_N4 0.22U_0402_10V6K 1 2 CV10 PX@ PCIE_CRX_GTX_N4 AG38
PCIE_RX4N PCIE_TX4N TX5P_DPB0P AH37
TX5M_DPB0N
PCIE_CTX_GRX_P5 T35 T30 PCIE_CRX_C_GTX_P5 0.22U_0402_10V6K 1 2 CV11 PX@ PCIE_CRX_GTX_P5 AF35
R36 PCIE_RX5P PCIE_TX5P T29 NC#AF35
PCIE_CTX_GRX_N5 PCIE_CRX_C_GTX_N5 0.22U_0402_10V6K 1 2 CV12 PX@ PCIE_CRX_GTX_N5 AG36
PCIE_RX5N PCIE_TX5N NC#AG36
LVTMDP
PCIE_CTX_GRX_P6 R38 P33 PCIE_CRX_C_GTX_P6 0.22U_0402_10V6K 1 2 CV13 PX@ PCIE_CRX_GTX_P6
P37 PCIE_RX6P PCIE_TX6P P32
PCIE_CTX_GRX_N6 PCIE_CRX_C_GTX_N6 0.22U_0402_10V6K 1 2 CV14 PX@ PCIE_CRX_GTX_N6
PCIE_RX6N PCIE_TX6N
AP34
TXCAP_DPA3P AR34
PCIE_CTX_GRX_P7 P35 P30 PCIE_CRX_C_GTX_P7 0.22U_0402_10V6K 1 2 CV15 PX@ PCIE_CRX_GTX_P7 TXCAM_DPA3N
N36 PCIE_RX7P PCIE_TX7P P29
PCIE_CTX_GRX_N7 PCIE_CRX_C_GTX_N7 0.22U_0402_10V6K 1 2 CV16 PX@ PCIE_CRX_GTX_N7 AW37
PCIE_RX7N PCIE_TX7N TX0P_DPA2P AU35
2 TX0M_DPA2N 2
N38 N33 AR37
M37 NC NC N32 TX1P_DPA1P AU39
NC NC TX1M_DPA1N
PCI EXPRESS INTERFACE AP35
M35 N30 TX2P_DPA0P AR35
L36 NC NC N29 TX2M_DPA0N
NC NC
AN36
NC AP37
L38 L33 NC
K37 NC NC L32
NC NC
K35 L30 MARS@ MARS-XT M2_FCBGA962

J36 NC NC L29
NC NC
J38 K33
H37 NC NC K32
NC NC
H35 J33 UV1 SUN@

G36 NC NC J32
NC NC
G38 K30
F37 NC NC K29
NC NC
S IC 216-0841000-00 A0 SUN PRO M2 FCBGA 962P C38
F35 H33
E37 NC NC H32 SA00006BA10
NC NC
3 3
CLOCK +3VGS
CLK_PCIE_VGA AB35
<16> CLK_PCIE_VGA AA36 PCIE_REFCLKP
CLK_PCIE_VGA#
<16> CLK_PCIE_VGA# PCIE_REFCLKN
5
2
P
CALIBRATION <15> DGPU_HOLD_RST# B 4 GPU_RST#
Y30 RV1 1 PX@ 2 1.69K_0402_1% 1 Y
PCIE_CALR_TX +0.95VGS <15,37,38,43> PLT_RST# A
G
PX@
2 PX@ 1 AH16 Y29 RV3 1 PX@ 2 1K_0402_1% UV2
TEST_PG PCIE_CALR_RX +0.95VGS
3
RV2 1K_0402_5% MC74VHC1G08DFT2G SC70 5P
GPU_RST# AA30
PERSTB
1
PX@ MARS@ MARS-XT M2_FCBGA962

RV4
100K_0402_5%
2
4 4

ATI_MarsXTX_M2_PCIE/LVDS
Custom 0.3
LA8642P M/B
A B C D E
A B C D E
UV1B CONFIGURATION STRAPS RECOMMENDED SETTINGS

PART 2 0F 9 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE 0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
MUTI GFX GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET X = DESIGN DEPENDANT
T1 GENLK_CLK AD29 GENLK_CLK AU24 NA = NOT APPLICABLE
AC29 NC AV23
T2 GENLK_VSYNC GENLK_VSYNC NC
AT25 STRAPS STRAPS MLPS DESCRIPTION OF DEFAULT SETTINGS Default Setting
AJ21 NC AR24
SWAPLOCKA DPA NC
AK21 SWAPLOCKB Transmitter Power Savings Enable
AU26 TX_PWRS_ENB PS_1[4] 0:50% Tx output swing 1
NC
AV25 1:Full Tx output swing
NC
+3VGS
AR8 AT27 PCIE Transmitter De-emphasis Enable
NC NC
AU8 NC AR26 TX_DEEMPH_EN PS_1[5] 0:Tx de-emphasis disabled 0
AP8 NC 2 1 100K_0402_5%
DBG_CNTL0 GPU_GPIO5 RV5 @ 1:Tx de-emphasis enabled
AW8 NC AR30
1 NC 1
AR3 AT29 PCIE Gen3 Enable
NC NC
AR1 THM_ALERT# RV6 2 @ 1 2.2K_0402_5% BIF_GEN3_EN_A PS_1[1] (NOTE:RESERVED for Thames/Seymour and should 1
NC
AU1 DBG_DATA0 AV31 be strapped to 0)
AU3 NC AU30
DBG_DATA1 DPB NC
AW3 DBG_DATA2 0:GEN3 not support at power-on
AP6 AR32 1:GEN3 supported at power-on
DBG_DATA3 NC
AW5 AT31
DBG_DATA4 NC
AU5 DBG_DATA5 VGA control
AR6 AT33 BIF_VGA DIS PS_2[4] 0:VGA controller capacity enabled 0
DBG_DATA6 NC
AW6 DBG_DATA7 AU32 1:VGA controller capacity disabled (for multi-GPU)
NC
AU6
DBG_DATA8
AT7 AU14 Serial ROM type or Memory Aperture Size Select
DBG_DATA9 NC
AV7 DBG_DATA10 AV13 ROMIDCFG[2:0] PS_0[3..1] If PS_2[3]=0, defines memory aperture size 000
AN7 NC
DBG_DATA11 If PS_2[3]=1, defines ROM type
AV9 DBG_DATA12 AT15 100 - 512Kbit M25P05A (ST)
NC
AT9 AR14 101 - 1Mbit M25P10A (ST)
DBG_DATA13 NC
AR10 101 - 2Mbit M25P20 (ST)
DBG_DATA14 DPC
AW10 DBG_DATA15 AU16 101 - 4Mbit M25P40 (ST)
AU10 NC AV15
DBG_DATA16 NC 101 - 8Mbit M25P80 (ST)
AP10 DBG_DATA17 100 - 512Kbit Pm25LV010 (Chingis)
AV11 AT17 101 - 1Mbit Pm25LV010 (Chingis)
DBG_DATA18 NC
AT11 AR16
DBG_DATA19 NC
AR12 DBG_DATA20
AW12 AU20 Enable external BIOS ROM device
DBG_DATA21 NC
AU12 DBG_DATA22 AT19 BIOS_ROM_EN PS_2[3] 0:Disabled 0
NC
AP12 1:Enabled
DBG_DATA23
AT21
NC
AR20 00 - No audio function
NC
AUD[1] NA 01 - Audio for DP only XX
VGA_SMB_CK2 AJ23 DPD AU22 10 - Audio for DP and HDMI if dongle is detected
SMBCLK SMBus NC
VGA_SMB_DA2 AH23 AV21 AUD[0] NA 11 - Audio for both DP and HDMI
SMBDATA NC
AT23 HDMI must only be enabled on systems that are
NC AR22 legally entitled. It isthe responsibility of the system
NC
AK26 SCL designer to ensure that the system is entitled to
AJ26 I2C support this feature.
SDA
2 AD39 VGA_R 2
R AD37
GENERAL PURPOSE I/O T24 CEC_DIS PS_0[4] Reserved for future ASIC 1
GPU_GPIO0 AH20 AVSSN
<55> GPU_GPIO0
AH18
GPIO_0
AE36 VGA_G
AVDD MarsCRB Design NOTE:ALLOW FOR PULLUP PADS FOR THE
GPIO_1 G
AN16
GPIO_2 AVSSN
AD35 T25 120ohm 1 1 RESERVED STRAPS BUT DO NOT INSTALL
DV1 RESISTOR
RB751V_SOD323 @
B
AF37 VGA_B 0.1u 1 1 IF THESE GPIOS ARE USEED, THEY MUST KEEP
1 2 GPU_GPIO5 AH17 AE38 T26 LOW AND NOT CONFLICT DURING RESET
<15,43,48,50> ACIN
GPU_VID5 AJ17
GPIO_5_AC_BATT
GPIO_6_TACH
AVSSN 1u 1 1
<55> GPU_VID5 AK17 DAC1
AC36
GPIO_7_BLON HSYNC 10u 1 1 RESERVED PS_1[3] Reserved 0
AJ13 HSYNC AC38 VSYNC T4
GPIO_8_ROMSO VSYNC
AH15 T6 RESERVED PS_1[2] Reserved 0
GPIO_9_ROMSI
AJ16 GPIO_10_ROMSCK
AK16 AB34 RV11 1 PX@ 2 499_0402_1% +AVDD +1.8VGS RESERVED NA Reserved 0
GPIO_11 RSET
AL16 LV1
GPIO_12
AM16 GPIO_13 AD34 +AVDD (1.8V@70mA AVDD) 1 2 RESERVED NA Reserved (for Thames/Whistler/Seymour only) 0
AM14 AVDD AE34
GPIO_14_HPD2 AVSSQ
GPU_VID1 AM13 0_0402_5%
CV17
CV18
CV19
GPIO_15_PWRCNTL_0
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_16V7K
<55> GPU_VID1 (1.8V@117mA VDD1DI)
AK14 AC33 +VDD1DI 1 1 1 STRAPS TO INDICATE THE NUMBER OF AUDIO
GPIO_16 VDD1DI
THM_ALERT# AG30 AC34 AUD_PORT_CONN_PINSTRAP[2] PS_3[5] CAPABLE DISPLAY OUTPUTS XXX
GPIO_17_THERMAL_INT VSS1DI
AN14 GPIO_18_HPD3 111 = 0 usable endpoints
@ RV12 1 2 10K_0402_5% AM17
GPIO_19_CTF AUD_PORT_CONN_PINSTRAP[1] PS_3[4] 110 = 1 usable endpoints
2 2 2
@
GPU_VID2 AL13 GPIO_20_PWRCNTL_1 V13 101 = 2 usable endpoints
<55> GPU_VID2 NC
AJ14 U13 AUD_PORT_CONN_PINSTRAP[0] PS_0[5] 100 = 3 usable endpoints
GPIO_21 NC
AK13 AF33 011 = 4 usable endpoints
GPIO_22_ROMCSB NC
CLK_REQ_VGA# AN13 CLKREQB AF32 010 = 5 usable endpoints
<16> CLK_REQ_VGA# NC AA29
NC 001 = 6 usable endpoints
AG21 +VDD1DI +1.8VGS 000 = all endpoints are usable
NC
GPU_VID3 AG32 AC32 LV2
<55> GPU_VID3 GPIO_29 NC
GPU_VID4 AG33 1 2
<55> GPU_VID4 GPIO_30
AC31
AJ19 NC_SVI2 AD30 0_0402_5%
CV20
CV21
CV22
GENERICA
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_16V7K
NC_SVI2
AK19 GENERICB AD32 1 1 1
NC_SVI2
AJ20
GENERICC
AK20
AJ24
GENERICD VDD1DI MarsCRB Design
GENERICE_HPD4 2 2 2
120ohm 1 1
@
@
AH26
GENERICF_HPD5
AH24 GENERICG_HPD6
3
0.1u 1 1 3
PS_0
AM34 PS_0
1u 1 1 MLPS Strap
AC30 10u 1 1
CEC_1
0.60 V level, Please Bits[5:4] Bits[3:1] Capacitor R_pu R_pd
AK24 AD31 PS_1
VREFG Divider ans HPD1 MLPS PS_1
+1.8VGS +VREFG_GPU cap close to ASIC PS_0[5:1] 11 000 NC NC 4.75K
PX@
2 RV13 1 499_0402_1% +VREFG_GPU AH13 DBG_VREFG PS_2 AG31 PS_2
PX@ PS_1[5:1] 01 001 82 nF 8.45K 2K
2 RV14 1 249_0402_1%
BACO
2 1 0.1U_0402_16V7K PX_EN AL21 AD33 PS_3 PS_2[5:1] 10 000 NC NC 4.75K
PX_EN PS_3
CV23
PX@ Mapping to VRAM type please refer to page 4
PS_3[5:1] 11 XXX NC X X
DEBUG DDC/AUX +1.8VGS
1 @ 2 TESTEN AM26 VGA_CLK
+3VGS DDC1CLK
RV18 5.11K_0402_5% AN26 VGA_DAT T27
DDC1DATA
1 PX@ 2 AD28 T28
TESTEN
RV19 1K_0402_5% AM27
AUX1P
1
AL27
AUX1N
GPIO_28_FDO MLPS
JTAG_TRSTB AM23 JTAG_TRSTB AM19 X76@ RV20 @ RV21 PX@RV22
PX@ RV22 @ RV23
DDC2CLK
H Disable JTAG_TDI AN23 AL19 8.45K_0402_1% 8.45K_0402_1% 8.45K_0402_1% 8.45K_0402_1%
JTAG_TDI DDC2DATA +3VGS
JTAG_TCK AK23
JTAG_TCK
2
L Enable JTAG_TMS AL24 JTAG_TMS AN20 PS_0
AM24 AUX2P AM20
JTAG_TDO JTAG_TDO PS_1
AUX2N
PS_2
AL30 +3VGS PS_3
NC
1
AM30 @ @
NC
1
RV24 RV25 @ 1@ 1 1 @ 1
THERMAL AL29 10K_0402_5% 10K_0402_5% CV26 CV27 PX@ CV28
NC
RV16 1 @ 2 0_0402_5% THERM_D+ AF29 DPLUS AM29 CV29 X76@ RV27 PX@RV28
PX@ RV28 PX@ RV29
PX@RV29 PX@ RV30
<40> REMOTE1+ NC
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
2
RV17 1 @ 2 0_0402_5% THERM_D- AG29

DMINUS 4.75K_0402_1% 4.75K_0402_1% 2K_0402_1% 4.75K_0402_1%
<40> REMOTE1-
2
1 @ 2 GPIO_28_FDO AN21 2 2 2 2
+3VGS NC
2
0.082U_0402_16V7K
4 RV26 10K_0402_5% AM21 VGA_SMB_CK2 1 6 4
1 PX@ 2 AK32 NC EC_SMB_CK2 <17,33,40,43>
GPIO_28_FDO
5
RV31 10K_0402_5% AK30 QV3A @

NC
AL31 AK29 2N7002DW-T/R7_SOT363-6
+1.8VGS +TSVDD TS_A NC
(1.8V@13mA TSVDD) VGA_SMB_DA2 4 3
LV3
DDCVGACLK
AJ30
EC_SMB_DA2 <17,33,40,43> Place CLOSE VGA CHIP
1 2 +TSVDD AJ32 AJ31 QV3B @
TSVDD DDCVGADATA
AJ33 TSVSS 2N7002DW-T/R7_SOT363-6
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_16V7K
0_0402_5%
CV30
CV31
CV32
1 1 1
MARS@ MARS-XT M2_FCBGA962
TSVDD MarsCRB Design Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 2
120ohm 1 1 Issued Date 2012/07/03 Deciphered Date 2013/07/03 Title
PX@
PX@
PX@
0.1u 1 1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_MarsXTX_M2_Main_MSIC
1u 1 1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 0.3
10u 1 1
LA8642P M/B
Date: Monday, April 22, 2013 Sheet 24 of 61
A B C D E
A B C D E
UV1C
PART 9 0F 9
+1.8VGS +MPV18
LV4 (MPLL_PVDD:1.8V@130mA )
MPLL_PVDD MarsCRB Design 1 2 AV33 XTALIN PX@ RV32 1 2 1M_0402_5%
XTALIN
220ohm 1 1
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
CV33
CV34
CV35
1 0_0603_5% 1
0.1u 1 1 1 1 1 YV1
4 3 XTALOUT
1u 1 1 NC OSC
10u 1 1 XTALIN 1 2
2 2 2 OSC NC
PX@
PX@
PX@
AU34 XTALOUT 2 2
XTALOUT
PX@ 27MHZ 10PF +-20PPM X3G027000DA1H PX@
CV36 PX@ CV37
8.2P_0402_50V8D 8.2P_0402_50V8D
+MPV18 H7 1 1
MPLL_PVDD
H8
MPLL_PVDD
+SPV18 (SPLL_PVDD:1.8V@75mA ) AW34
SPLL_PVDD MarsCRB Design +1.8VGS
LV5
XO_IN
120ohm 1 1 1 2 +SPV18 AM10
SPLL_PVDD
PLLS/XTAL
0.1u 1 1
10U_0603_6.3V6M
CV38
CV39
CV40
1U_0402_6.3V6K
0.1U_0402_16V7K
0_0402_5%
1u 1 1 1 1 1
+SPLL_VDDC AN9 SPLL_VDDC
AW35
XO_IN2
10u 1 1
PX@
PX@
PX@
2 2 2
AN10
SPLL_PVSS
+0.95VGS AK10
SPLL_VDDC MarsCRB Design LV6
+SPLL_VDDC
(SPLL_VDDC:0.95V@100mA ) AF30 CLKTESTA AL10
NC_XTAL_PVDD CLKTESTB
120ohm 1 1 1 2 AF31
NC_XTAL_PVSS
1
@ @
0.1u 1 1
10U_0603_6.3V6M
CV43
CV44
CV45
1U_0402_6.3V6K
0.1U_0402_16V7K
0_0402_5% CV41 CV42
1 1 1 0.1U_0402_16V7K 0.1U_0402_16V7K
1u 1 1
2
2 2
10u 1 1
2 2 2
PX@
PX@
PX@
1
@ @
RV33 RV34
51.1_0402_1% 51.1_0402_1%
2
+3VALW
1
+1.5VS to +1.5VGS Transfer PX@
<+3VS TO +3VGS>
RV35
100K_0402_5%
+1.5VS +1.5VGS +3VS +3VGS
2
DGPU_PWR_EN#
3 3 1 3
1
PX@
QV8 @
LP2301ALT1G_SOT23-3 RV36
2
1
D PX@ 470_0603_5%
AO4430: Rdson: 5.5mohm @ VGS=10V DGPU_PWR_EN 2 QV9
<15,43,53,55> DGPU_PWR_EN
2
G 2N7002K_SOT23-3 +5VALW
UV4
S 1 PX@
1
AO4304L_SO8 CV46 D
300mil(7.2A) 8 1
300mil(7.2A) 2
4.7U_0603_6.3V6K
1 7 2 G
CV48 PX@ 6 3 RV37 PX@ RV38 PX@ 2 S @
3
2
4.7U_0603_6.3V6K 5 1 PX@ QV7

CV49 RV39 @ 20K_0402_5% 20K_0402_5% 2N7002K_SOT23-3
2 PX@ 4.7U_0603_6.3V6K 470_0603_5%
4
1 PX@
1
2 D PX@ DGPU_PWR_EN#
1
DGPU_PWR_EN 2 QV6 CV52

G 2N7002K_SOT23-3 0.1U_0402_16V7K
+VSB 2
S
3
RV41 240K_0402_5%
2 1
1
PX@ D
1 @ QV1 2 DGPU_PWR_EN#
2
R02 PX@ 2N7002_SOT23 G

QV2 RV42 @ CV53 S
3
2N7002_SOT23 0_0402_5% 0.1U_0402_25V6

1
D 2
DGPU_PWR_EN# 2
1
G
4 4
S
3
PX@

ATI_MarsXTX_M2_BACO POWER
Rev
Custom 0.3
LA8642P M/B
A B C D E
A B C D E
UV1G
PART 6 0F 9 UV1F
AB39 A3 PART 8 0F 9
E39 GND GND A37 +0.95VGS
GND GND DP_VDDR DP_VDDC
(DP_VDDC:0.95V@280mA/link )
F34 AA16
F39 GND GND AA18 AP31
G33 GND GND AA2 DP_VDDC AP32
GND GND DP_VDDC
0.1U_0402_16V7K
10U_0603_6.3V6M
1U_0402_6.3V6K
G34 AA21 AN33
CV54
GND GND DP_VDDC
CV55
CV56
H31 AA23 AP33
H34 GND GND AA26 AN24 DP_VDDC AL33
GND GND NC DP_VDDC 1 1 1
H39 AA28 AP24 AM33
J31 GND GND AA6 AP25 NC DP_VDDC AK33
PX@
PX@
PX@
1 J34 GND GND AB12 AP26 NC DP_VDDC AK34 1
K31 GND GND AB15 AU28 NC DP_VDDC AN31 2 2 2
K34 GND GND AB17 DP_VDDR MarsCRB Design AV29 NC DP_VDDC
GND GND NC
K39
L31 GND GND
AB20
AB22
0.1u 1 1
L34 GND GND AB24 1u 1 1 AP20 AP13
M34 GND GND AB27 AP21
NC NC AT13
DP_VDDC MarsCRB Design
M39 GND GND AC11 10u 1 1 AP22 NC NC AP14 0.1u 1 1
N31 GND GND AC13 AP23 NC NC AP15
N34 GND GND AC16 AU18 NC NC 1u 1 1
P31 GND GND AC18 AV19 NC
P34 GND GND AC2 +1.8VGS +DP_VDDR (DP_VDDR:1.8V@237mA/link )
NC DP GND 10u 1 1
P39 GND GND AC21 AN27
RV43
R34 GND GND AC23 1 2 +DP_VDDR AH34 DP_VSSR AP27
T31 GND GND AC26 AJ34 DP_VDDR DP_VSSR AP28
GND GND DP_VDDR DP_VSSR
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
T34 AC28 0_0402_5% AF34 AW24
CV57
CV58
CV59
T39 AC6 AG34 AW26
U31 GND GND AD15 AM37 DP_VDDR DP_VSSR AN29
GND GND 1 1 1 DP_VDDR DP_VSSR
U34 AD17 AL38 AP29
V34 GND GND AD20 AM32 DP_VDDR DP_VSSR AP30
PX@
PX@
PX@
V39 AD22 AW30
W31 GND GND AD24 2 2 2 DP_VSSR AW32
W34 GND GND AD27 DP_VSSR AN17
Y34 GND GND AD9 DP_VSSR AP16
Y39 GND GND AE2 DP_VSSR AP17
GND GND AE6 DP_VSSR AW14
GND AF10 DP_VSSR AW16
GND AF16 DP_VSSR AN19
GND AF18 DP_VSSR AP18
GND AF21 DP_VSSR AP19
GND GND DP_VSSR
AG17 AW20
F15 GND AG2 CALIBRATION DP_VSSR AW22
2 F17 GND GND AG20 DP_VSSR AN34 2
F19 GND GND DP_VSSR AP39
F21 GND AG6 AW28 DP_VSSR AR39
F23 GND GND AG9 NC DP_VSSR AU37
F25 GND GND AH21 DP_VSSR AF39
F27 GND GND AJ10 DP_VSSR AH39
F29 GND GND AJ11 AW18 DP_VSSR AK39
F31 GND GND AJ2 NC DP_VSSR AL34
F33 GND GND AJ28 DP_VSSR AV27
F7 GND GND AJ6 DP_VSSR AR28
F9 GND GND AK11 DP_VSSR
RV44 2 PX@ 1 150_0402_1% AM39 AV17
G2 GND GND AK31 DP_CALR DP_VSSR AR18
G6 GND GND AK7 DP_VSSR AN38
H9 GND GND AL11 DP_VSSR AM35
J2 GND GND AL14 DP_VSSR AN32
J27 GND GND AL17 DP_VSSR
J6 GND GND AL2
J8 GND GND AL20
K14 GND GND
K7 GND AL23
L11 GND AL26
L17 GND GND AL32 MARS@ MARS-XT M2_FCBGA962
L2 GND GND AL6
L22 GND GND AL8
L24 GND GND AM11
L6 GND GND AM31
M17 GND GND AM9
M22 GND GND AN11
M24 GND GND AN2
N16 GND GND AN30
N18 GND GND AN6
N2 GND GND AN8
3 N21 GND GND AP11 3
N23 GND GND AP7
N26 GND GND AP9
N6 GND GND AR5
R15 GND GND B11
R17 GND GND B13
R2 GND GND B15
R20 GND GND B17
R22 GND GND B19
R24 GND GND B21
R27 GND GND B23
R6 GND GND B25
T11 GND GND B27
T13 GND GND B29
T16 GND GND B31
T18 GND GND B33
T21 GND GND B7
T23 GND GND B9
T26 GND GND C1
U15 GND GND C39
U17 GND GND E35
U2 GND GND E5
U20 GND GND F11
U22 GND GND F13
U24 GND GND
U27 GND GND
U6 GND
V11 GND AG22
V16 GND NC
V18 GND
V21 GND
V23 GND
4 V26 GND 4
W2 GND
W6 GND
Y15 GND
Y17 GND
Y20 GND
Y22 GND A39 MECH#1 TV12 PAD
Y24 GND VSS_MECH AW1 MECH#2 TV13 PAD
Y27 GND
GND
VSS_MECH
VSS_MECH
AW39 MECH#3 TV14 PAD Security Classification Compal Secret Data Compal Electronics, Inc.
ATI_MarsXTX_M2_PWR_GND
MARS@ MARS-XT M2_FCBGA962 Size Document Number
Rev
Custom 0.3
LA8642P M/B
A B C D E
A B C D E
(PCIE_VDDR:1.8V@100mA ) +PCIE_VDDR +1.8VGS

+1.5VGS UV1E LV7
PART 5 0F 9 +PCIE_VDDR 2 1
PCIE_VDDR MarsCRB Design
0.1u 0 2
0.1U_0402_16V7K
0.01U_0402_16V7K
0_0603_5%
CV62
CV63
CV64
CV65
MEM I/O
10U_0603_6.3V6M
1U_0402_6.3V6K
+1.5VGS AC7
VDDR1 NC
AA31 1 1 1 1u 2 3
1
AD11 AA32
AF7
VDDR1 NC AA33 10u 1 1
CV66
CV60
CV67
CV68
CV69
CV70
CV71
CV72
CV73
CV74
CV75
CV76
CV61
CV77
CV78
CV79
1 VDDR1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
NC
220U_B2_2.5VM_R35
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AG10 VDDR1 AA34
NC
2
2 2 2
PX@
PX@
PX@
PX@
+ AJ7 W30
VDDR1 NC
@ AK8 Y31
VDDR1 NC
AL9 VDDR1 V28
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 NC_BIF_VDDC
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
G11 W29
VDDR1 NC_BIF_VDDC +0.95VGS
G14 AB37
1 VDDR1 PCIE_PVDD PCIE_VDDC MarsCRB Design 1
PCIE
G17 (PCIE_VDDC:0.95V@2.5A_GEN3.0 )
VDDR1
G20
G23
VDDR1 PCIE_VDDC
G30
G31
+0.95VGS 1u 7 5
VDDR1 PCIE_VDDC
G26 H29 10u 2 1
CV80
CV81
CV82
CV83
CV84
CV85
VDDR1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
PCIE_VDDC
G29 VDDR1 H30 1 1 1 1 1 1
PCIE_VDDC
H10 J29
VDDR1 MarsCRB Design J7
VDDR1 PCIE_VDDC J30
VDDR1 PCIE_VDDC
0.01u 5 0 J9 VDDR1 PCIE_VDDC
L28
2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
K11 M28
VDDR1 PCIE_VDDC
0.1u 5 5 K13 VDDR1 PCIE_VDDC
N28
K8 R28
1u 0 5 L12
VDDR1
VDDR1
PCIE_VDDC T28
PCIE_VDDC
2.2u 5 0 L16 VDDR1 U28
L21 PCIE_VDDC +0.95VGS
VDDR1
10u 3 5 L23 VDDR1 (BIF_VDDC:0.95V@1.4A)
L26 N27 +0.95VGS
220u 0 1 VDDR1 BACO BIF_VDDC
L7 T27
VDDR1 BIF_VDDC
10U_0603_6.3V6M
M11
CV86
CV87
CV88
VDDR1
1U_0402_6.3V6K
1U_0402_6.3V6K
N11 1 1 1
VDDR1
P7 VDDR1 AA15
CORE VDDC
R11 AA17
+1.8VGS +VDDC_CT VDDR1 VDDC
PX@
U11 AA20
VDDR1 VDDC 2 2 2
PX@
PX@
LV8 (VDD_CT:1.8V@13mA ) U7 AA22
VDD_CT MarsCRB Design 1 2 Y11
VDDR1 VDDC AA24
VDDR1 VDDC
120ohm 1 1 Y7 VDDR1 VDDC
AA27
AB16
0_0402_5%
CV89
CV90
CV91
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1u 1 1 VDDC AB18
1 1 1 VDDC
AB21
1u 1 3 VDDC AB23 +VGA_CORE
VDDC
10u 1 1 LEVEL AB26
2 2 2 VDDC
PX@
PX@
@
TRANSLATION AB28
AF26 VDDC AC17
+VDDC_CT VDD_CT VDDC
AF27 VDD_CT AC20
AG26 VDDC AC22
VDD_CT VDDC
AG27 AC24
VDDR3 MarsCRB Design VDD_CT VDDC
AC27
VDDC
120ohm 1 0 +3VGS +VDDR3
VDDC
AD18
AD21
2 LV9 (VDDR3:3.3V@25mA) I/O 2
0.1u 1 0 1 2 AF23 VDDC AD23
+VDDR3 VDDR3 VDDC
AF24 VDDR3 AD26
1u 2 3 0_0402_5% AG23
VDDC
AF17
CV92
CV94
CV95
10U_0603_6.3V6M
VDDR3
1U_0402_6.3V6K
1U_0402_6.3V6K
AG24 VDDC AF20
10u 0 1 1 1 1 VDDR3 VDDC
AF22
VDDC AG16
DVP VDDC
AD12 VDDR4 AG18
2 2 2 VDDC
PX@
PX@
PX@
AF11
AF12
VDDR4
VDDR4 VDDC
AH22 VGA_CORE Cap in power side sheet
AF13 VDDR4 AH27
VDDC AH28
VDDC
M26
VDDC
AF15 N24
+1.8VGS +VDDR4 VDDR4 VDDC
AG11 R18
VDDR4 VDDC
LV10 ( VDDR4:1.8V@300mA) AG13 VDDR4 R21
VDDR4 MarsCRB Design 1 2 +VDDR4 AG15 VDDC R23
VDDR4 VDDC
220ohm 1 1 VDDC
R26
T17
0_0603_5%
CV96
CV97
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1u 1 1 VDDC T20

1 1 VDDC
T22
1u 1 1 VDDC T24
VDDC
10u 1 0 U16
2 2 VDDC
PX@
PX@
U18
VDDC U21
VDDC
U23
VDDC U26
VDDC
V17
VDDC
V20
VDDC V22
VDDC
V24
VDDC V27
VDDC
Y16
VDDC
Y18
VDDC Y21
VDDC
Y23
VDDC Y26
VDDC +VGA_CORE
Y28
3 VDDC 3
(VDDCI:0.9~1.15V@8.8A)
AA13
VDDCI
AB13
VDDCI AC12
VDDCI
AC15
VDDCI
AD13
VDDCI AD16
VDDCI
M15
VDDCI M16
VDDCI
M18
Route as differential pair VOLTAGE VDDCI
M23
CORE I/O
SENESE VDDCI
ISOLATED
N13
VDDCI
AF28 FB_VDDC N15
<55> VCCSENSE_VGA VDDCI N17
VDDCI
N20
VDDCI
AG28 N22
FB_VDDCI VDDCI
TV15 R12
VDDCI
R13
AH29 VDDCI R16
<55> VSSSENSE_VGA FB_GND VDDCI
T12
VDDCI
T15
VDDCI V15
VDDCI
Y13
VDDCI
4 4

ATI_MarsXTX_M2_Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
LA8642P M/B
A B C D E
A B C D E
UV1H
UV1I
PART 3 0F 9
MDB[0..63] PART 4 0F 9
GDDR5/DDR3 <31,32> MDB[0..63]
MDA0 C37 G24 MAA0 MDA[0..63]
DQA0_0 MAA0_0/MAA_0 <29,30> MDA[0..63] GDDR5/DDR3
MDA1 C35 DQA0_1 MAA0_1/MAA_1 J23 MAA1 MDB0 C5 MAB0_0/MAB_0 P8 MAB0
A35 H24 MAB[15..0] C3 DQB0_0 T9
MDA2 DQA0_2 MAA0_2/MAA_2 MAA2 MDB1 MAB0_1/MAB_1 MAB1
MAA[15..0] MAB[15..0] <31,32> DQB0_1
MDA3 E34 DQA0_3 MAA0_3/MAA_3 J24 MAA3 MDB2 E3 MAB0_2/MAB_2 P9 MAB2
MAA[15..0] <29,30> B_BA[2..0] DQB0_2
MDA4 G32 H26 MAA4 MDB3 E1 N7 MAB3
DQA0_4 MAA0_4/MAA_4 A_BA[2..0] B_BA[2..0] <31,32> DQB0_3 MAB0_3/MAB_3
MDA5 D33 J26 MAA5 MDB4 F1 N8 MAB4
DQA0_5 MAA0_5/MAA_5 A_BA[2..0] <29,30> DQB0_4 MAB0_4/MAB_4
MDA6 F32 DQA0_6 MAA0_6/MAA_6 H21 MAA6 MDB5 F3 MAB0_5/MAB_5 N9 MAB5
E32 G21 F5 DQB0_5 U9
MDA7 MAA7 MDB6 MAB6
MEMORY INTERFACE A
DQA0_7 MAA0_7/MAA_7 DQB0_6 MAB0_6/MAB_6
MDA8 D31 DQA0_8 MAA1_0/MAA_8 H19 MAA8 MDB7 G4 MAB0_7/MAB_7 U8 MAB7
DQB0_7
MDA9 F30 H20 MAA9 MDB8 H5 Y9 MAB8
MDA10 C30 L13 MAA10 MDB9 H6 W9 MAB9
MDA11 A30 DQA0_11 MAA1_3/MAA_11 G16 MAA11 MDB10 J4 MAB1_2/MAB_10 AC8 MAB10
F28 J16 K6 DQB0_10 AC9
MDA12 DQA0_12 MAA1_4/MAA_12 MAA12 MDB11 MAB1_3/MAB_11 MAB11
DQB0_11
MDA13 C28 DQA0_13 MAA1_5/MAA_BA2 H16 A_BA2 MDB12 K5 MAB1_4/MAB_12 AA7 MAB12
1 DQB0_12 1
MDA14 A28 J17 A_BA0 MDB13 L4 AA8 B_BA2
DQA0_14 MAA1_6/MAA_BA0 DQB0_13 MAB1_5/BA2
MDA15 E28 H17 A_BA1 MDB14 M6 Y8 B_BA0
DQA0_15 MAA1_7/MAA_BA1 DQB0_14 MAB1_6/BA0
MDA16 D27 DQA0_16 MDB15 M1 MAB1_7/BA1 AA9 B_BA1
DQB0_15
MEMORY INTERFACE B
MDA17 F26 A32 DQMA0 MDB16 M3
DQA0_17 WCKA0_0/DQMA_0 DQMA0 <29> DQB0_16
MDA18 C26 DQA0_18 WCKA0B_0/DQMA_1 C32 DQMA1 MDB17 M5 H3 DQMB0
DQMA1 <29> DQB0_17 WCKB0_0/DQMB_0 DQMB0 <31>
MDA19 A26 D23 DQMA2 MDB18 N4 H1 DQMB1
DQA0_19 WCKA0_1/DQMA_2 DQMA2 <29> DQB0_18 WCKB0B_0/DQMB_1 DQMB1 <31>
MDA20 F24 E22 DQMA3 MDB19 P6 T3 DQMB2
DQA0_20 WCKA0B_1/DQMA_3 DQMA3 <29> DQB0_19 WCKB0_1/DQMB_2 DQMB2 <31>
MDA21 C24 DQA0_21 WCKA1_0/DQMA_4 C14 DQMA4 MDB20 P5 T5 DQMB3
A24 A14 DQMA4 <30> R4 DQB0_20 WCKB0B_1/DQMB_3 AE4 DQMB3 <31>
MDA22 DQA0_22 WCKA1B_0/DQMA_5 DQMA5 MDB21 DQMB4
DQMA5 <30> DQB0_21 WCKB1_0/DQMB_4 DQMB4 <32>
MDA23 E24 DQA0_23 WCKA1_1/DQMA_6 E10 DQMA6 MDB22 T6 AF5 DQMB5
DQMA6 <30> DQB0_22 WCKB1B_0/DQMB_5 DQMB5 <32>
MDA24 C22 D9 DQMA7 MDB23 T1 AK6 DQMB6
DQA0_24 WCKA1B_1/DQMA_7 DQMA7 <30> DQB0_23 WCKB1_1/DQMB_6 DQMB6 <32>
MDA25 A22 MDB24 U4 AK5 DQMB7
DQA0_25 DQB0_24 WCKB1B_1/DQMB_7 DQMB7 <32>
MDA26 F22 DQA0_26 C34 QSA0 MDB25 V6
D21 EDCA0_0/QSA_0 D29 QSA0 <29> V1 DQB0_25 F6
MDA27 DQA0_27 QSA1 MDB26 QSB0
EDCA0_1/QSA_1 QSA1 <29> DQB0_26 EDCB0_0/QSB_0 QSB0 <31>
MDA28 A20 DQA0_28 D25 QSA2 MDB27 V3 K3 QSB1
MDA29 F20 E20 QSA3 MDB28 Y6 P3 QSB2
DQA0_29 EDCA0_3/QSA_3 QSA3 <29> DQB0_28 EDCB0_2/QSB_2 QSB2 <31>
MDA30 D19 E16 QSA4 MDB29 Y1 V5 QSB3
DQA0_30 EDCA1_0/QSA_4 QSA4 <30> DQB0_29 EDCB0_3/QSB_3 QSB3 <31>
MDA31 E18 DQA0_31 E12 QSA5 MDB30 Y3 AB5 QSB4
C18 EDCA1_1/QSA_5 J10 QSA5 <30> Y5 DQB0_30 EDCB1_0/QSB_4 AH1 QSB4 <32>
MDA32 DQA1_0 QSA6 MDB31 QSB5
MDA33 A18 DQA1_1 D7 QSA7 MDB32 AA4 AJ9 QSB6
MDA34 F18 MDB33 AB6 AM5 QSB7
DQA1_2 DQB1_1 EDCB1_3/QSB_7 QSB7 <32>
MDA35 D17 A34 QSA#0 MDB34 AB1
DQA1_3 DDBIA0_0/QSA_0B QSA#0 <29> DQB1_2
MDA36 A16 DQA1_4 E30 QSA#1 MDB35 AB3 G7 QSB#0
F16 DDBIA0_1/QSA_1B E26 QSA#1 <29> AD6 DQB1_3 DDBIB0_0/QSB_0B K1 QSB#0 <31>
MDA37 DQA1_5 QSA#2 MDB36 QSB#1
DDBIA0_2/QSA_2B QSA#2 <29> DQB1_4 DDBIB0_1/QSB_1B QSB#1 <31>
MDA38 D15 DQA1_6 C20 QSA#3 MDB37 AD1 P1 QSB#2
MDA39 E14 C16 QSA#4 MDB38 AD3 W4 QSB#3
DQA1_7 DDBIA1_0/QSA_4B QSA#4 <30> DQB1_6 DDBIB0_3/QSB_3B QSB#3 <31>
MDA40 F14 C12 QSA#5 MDB39 AD5 AC4 QSB#4
DQA1_8 DDBIA1_1/QSA_5B QSA#5 <30> DQB1_7 DDBIB1_0/QSB_4B QSB#4 <32>
MDA41 D13 DQA1_9 J11 QSA#6 MDB40 AF1 AH3 QSB#5
F12 DDBIA1_2/QSA_6B F8 QSA#6 <30> AF3 DQB1_8 DDBIB1_1/QSB_5B AJ8 QSB#5 <32>
MDA42 DQA1_10 QSA#7 MDB41 QSB#6
MDA43 A12 DQA1_11 MDB42 AF6 AM3 QSB#7
DQB1_10 DDBIB1_3/QSB_7B QSB#7 <32>
MDA44 D11 J21 ODTA0 MDB43 AG4
DQA1_12 ADBIA0/ODTA0 ODTA0 <29> DQB1_11
MDA45 F10 G19 ODTA1 MDB44 AH5 T7 ODTB0
DQA1_13 ADBIA1/ODTA1 ODTA1 <30> DQB1_12 ADBIB0/ODTB0 ODTB0 <31>
MDA46 A10 DQA1_14 MDB45 AH6 W7 ODTB1
C10 H27 CLKA0 AJ4 DQB1_13 ADBIB1/ODTB1 ODTB1 <32>
MDA47 DQA1_15 CLKA0 MDB46
CLKA0 <29> DQB1_14
MDA48 G13 DQA1_16 CLKA0B G27 CLKA0# MDB47 AK3 L9 CLKB0
CLKA0# <29> DQB1_15 CLKB0 CLKB0 <31>
MDA49 H13 MDB48 AF8 L8 CLKB0#
DQA1_17 DQB1_16 CLKB0B CLKB0# <31>
MDA50 J13 J14 CLKA1 MDB49 AF9
DQA1_18 CLKA1 CLKA1 <30> DQB1_17
2 MDA51 H11 DQA1_19 CLKA1B H14 CLKA1# MDB50 AG8 AD8 CLKB1 2
G10 CLKA1# <30> AG7 DQB1_18 CLKB1 AD7 CLKB1# CLKB1 <32>
MDA52 DQA1_20 MDB51
DQB1_19 CLKB1B CLKB1# <32>
MDA53 G8 DQA1_21 K23 RASA0# MDB52 AK9
RASA0B RASA0# <29> DQB1_20
MDA54 K9 K19 RASA1# MDB53 AL7 T10 RASB0#
DQA1_22 RASA1B RASA1# <30> DQB1_21 RASB0B RASB0# <31>
MDA55 K10 MDB54 AM8 Y10 RASB1#
DQA1_23 DQB1_22 RASB1B RASB1# <32>
MDA56 G9 DQA1_24 K20 CASA0# MDB55 AM7
A8 CASA0B K17 CASA1# CASA0# <29> AK1 DQB1_23 W10 CASB0#
MDA57 DQA1_25 MDB56
CASA1B CASA1# <30> DQB1_24 CASB0B CASB0# <31>
MDA58 C8 DQA1_26 MDB57 AL4 AA10 CASB1#
DQB1_25 CASB1B CASB1# <32>
MDA59 E8 CSA0B_0 K24 CSA0#_0 MDB58 AM6
DQA1_27 CSA0#_0 <29> DQB1_26
MDA60 A6 CSA0B_1 K27 MDB59 AM1 P10 CSB0#_0
DQA1_28 DQB1_27 CSB0B_0 CSB0#_0 <31>
MDA61 C6 DQA1_29 MDB60 AN4 L10
E6 M13 CSA1#_0 AP3 DQB1_28 CSB0B_1
MDA62 DQA1_30 CSA1B_0 MDB61
CSA1#_0 <30> DQB1_29
MDA63 A5 DQA1_31 CSA1B_1 K16 MDB62 AP1 AD10 CSB1#_0
DQB1_30 CSB1B_0 CSB1#_0 <32>
MDB63 AP5 AC10
L18 K21 CKEA0 DQB1_31 CSB1B_1
+VDD_MEM15_REFDA MVREFDA CKEA0 CKEA0 <29>
+VDD_MEM15_REFSA L20 MVREFSA CKEA1 J20 CKEA1 U10 CKEB0
CKEA1 <30> CKEB0 CKEB0 <31>
+VDD_MEM15_REFDB Y12 AA11 CKEB1
MVREFDB CKEB1 CKEB1 <32>
L27 NC WEA0B K26 WEA0# +VDD_MEM15_REFSB AA12
WEA0# <29> MVREFSB
N12 WEA1B L15 WEA1# N10 WEB0#
NC WEA1# <30> WEB0B WEB0# <31>
AG12 AB11 WEB1#
NC WEB1B WEB1# <32>
H23 MAA13
MAA0_8/MAA_13
1 PX@ 2 M27 MEM_CALRP0 MAA1_8/MAA_14 J19 MAA14 MAB0_8/MAB_13 T8 MAB13
RV47 120_0402_1% M21 MAA15 W8 MAB14
MAA0_9/MAA_15 MAB1_8/MAB_14
M12 M20 U12 MAB15
NC MAA1_9/RSVD MAB0_9/MAB_15
AH12 NC MAB1_9/RSVD V12
DRAM_RST AH11 DRAM_RST#_R
MARS@ MARS-XT M2_FCBGA962 MARS@ MARS-XT M2_FCBGA962
3 3
Ball to RV57 < 1"

CV100 to RV57 < 200 mil +1.5VGS
+1.5VGS +1.5VGS CV100 to RV53 < 1" +1.5VGS +1.5VGS
1
RV48
1
1
4.7K_0402_5%
RV49 RV50 @
40.2_0402_1% 40.2_0402_1% RV51 RV52
2
MARS@ MARS@ 40.2_0402_1% 40.2_0402_1%

PX@ PX@
2
2
+VDD_MEM15_REFDA +VDD_MEM15_REFSA 1 PX@ 2 1 PX@ 2 DRAM_RST#_R +VDD_MEM15_REFDB +VDD_MEM15_REFSB
<29,30,31,32> DRAM_RST# RV53 51.1_0402_1% RV54 10_0402_5%
1
1
1 1 1 1
1
2
RV56
RV55 CV98 100_0402_1% CV99 CV100 RV58 CV101 RV59 CV102
100_0402_1% 1U_0402_6.3V6K MARS@ 1U_0402_6.3V6K 120P_0402_50V9 RV57 100_0402_1% 1U_0402_6.3V6K 100_0402_1% 1U_0402_6.3V6K
2
MARS@ 2 MARS@ 2 MARS@ PX@ 4.99K_0402_1% PX@ 2 PX@ PX@ 2 PX@

2
2
PX@
1
DRAM_RST# is a daisy-chain net that connects to all VRAM

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These
Capacitors and Resistor values are an example only. The Series R and
|| Cap values will depend on the DRAM load and will have to be
4 4
calculated for different Memory ,DRAM Load and board to pass Reset
Signal Spec.
Place all these components very close to GPU (Within
25mm) and keep all component close to each Other (within
5mm) except Rser2

ATI_MarsXTX_M2_MEM IF
C 0.3
LA8642P M/B
A B C D E
5 4 3 2 1
UV6
UV5 +VREFC_A1 M8 E3 MDA24

H1 VREFCA DQL0 F7 MDA30
+VREFC_A0 M8 E3 MDA23 VREFDQ DQL1 F2 MDA27
H1 VREFCA DQL0 F7 MDA19 MAA0 N3 DQL2 F8 MDA29
VREFDQ DQL1 F2 MDA22 MAA1 P7 A0 DQL3 H3 MDA25
MAA0 N3 DQL2 F8 MDA18 MAA2 P3 A1 DQL4 H8 MDA28
MAA1 P7 A0 DQL3 H3 MDA21 MAA3 N2 A2 DQL5 G2 MDA26
MAA2 P3 A1 DQL4 H8 MDA17 MAA4 P8 A3 DQL6 H7 MDA31
MAA3 N2 A2 DQL5 G2 MDA20 MAA5 P2 A4 DQL7
MAA4 P8 A3 DQL6 H7 MDA16 MAA6 R8 A5
MAA5 P2 A4 DQL7 MAA7 R2 A6 D7 MDA12
D
MAA6 R8 A5 MAA8 T8 A7 DQU0 C3 MDA10 D
MDA[0..31] MAA7 R2 A6 D7 MDA0 MAA9 R3 A8 DQU1 C8 MDA14
<28> MDA[0..31] MAA8 T8 A7 DQU0 C3 MDA5 MAA10 L7 A9 DQU2 C2 MDA11
MAA9 R3 A8 DQU1 C8 MDA1 MAA11 R7 A10/AP DQU3 A7 MDA13
MAA10 L7 A9 DQU2 C2 MDA6 MAA12 N7 A11 DQU4 A2 MDA9
MAA11 R7 A10/AP DQU3 A7 MDA3 MAA13 T3 A12 DQU5 B8 MDA15
MAA12 N7 A11 DQU4 A2 MDA4 MAA14 T7 A13 DQU6 A3 MDA8
MAA[15..0] MAA13 T3 A12 DQU5 B8 MDA2 MAA15 M7 A14 DQU7
<28,30> MAA[15..0] T7 A13 DQU6 A3 A15/BA3 +1.5VGS
MAA14 MDA7
MAA15 M7 A14 DQU7
A15/BA3 +1.5VGS A_BA0 M2 B2
A_BA1 N8 BA0 VDD D9
M2 B2 A_BA2 M3 BA1 VDD G7
<28,30> A_BA0 N8 BA0 VDD D9 BA2 VDD K2
<28,30> A_BA1 BA1 VDD VDD
M3 G7 K8
<28,30> A_BA2 BA2 VDD VDD
K2 N1
VDD K8 CLKA0 J7 VDD N9
VDD N1 CLKA0# K7 CK VDD R1
J7 VDD N9 CKEA0 K9 CK VDD R9
<28> CLKA0 CK VDD CKE/CKE0 VDD +1.5VGS
K7 R1
<28> CLKA0# CK VDD
K9 R9
<28> CKEA0 CKE/CKE0 VDD +1.5VGS K1 A1
ODTA0
CSA0#_0 L2 ODT/ODT0 VDDQ A8
K1 A1 RASA0# J3 CS/CS0 VDDQ C1
<28> ODTA0 ODT/ODT0 VDDQ RAS VDDQ
L2 A8 CASA0# K3 C9
<28> CSA0#_0 CS/CS0 VDDQ CAS VDDQ
J3 C1 WEA0# L3 D2
<28> RASA0# K3 RAS VDDQ C9 WE VDDQ E9
<28> CASA0# CAS VDDQ VDDQ
L3 D2 F1
<28> WEA0# WE VDDQ E9 F3 VDDQ H2
QSA3
VDDQ <28> QSA3 DQSL VDDQ
F1 QSA1 C7 H9
VDDQ <28> QSA1 DQSU VDDQ
QSA2 F3 H2
<28> QSA2 C7 DQSL VDDQ H9
QSA0
<28> QSA0 DQSU VDDQ DQMA3 E7 A9
<28> DQMA3 D3 DML VSS B3
DQMA1
<28> DQMA1 DMU VSS
DQMA2 E7 A9 E1
<28> DQMA2 DML VSS VSS
DQMA0 D3 B3 G8
<28> DQMA0 DMU VSS E1 G3 VSS J2
QSA#3
VSS <28> QSA#3 DQSL VSS
C G8 QSA#1 B7 J8 C
G3 VSS J2 <28> QSA#1 DQSU VSS M1
QSA#2
<28> QSA#2 DQSL VSS VSS
QSA#0 B7 J8 M9
<28> QSA#0 DQSU VSS VSS
M1 P1
VSS M9 DRAM_RST# T2 VSS P9
VSS P1 RESET VSS T1
T2 VSS P9 L8 VSS T9
<28,30,31,32> DRAM_RST# RESET VSS ZQ/ZQ0 VSS
T1
L8 VSS T9
ZQ/ZQ0 VSS
1
J1 B1
RV85 L1 NC/ODT1 VSSQ B9
NC/CS1 VSSQ
1
J1 B1 240_0402_1% J9 D1
RV84 L1 NC/ODT1 VSSQ B9 MARS@ L9 NC/CE1 VSSQ D8
J9 NC/CS1 VSSQ D1 NCZQ1 VSSQ E2
240_0402_1%
2
L9 NC/CE1 VSSQ D8 VSSQ E8
MARS@ NCZQ1 VSSQ E2 VSSQ F9
2
VSSQ E8 VSSQ G1
VSSQ F9 VSSQ G9
VSSQ G1 VSSQ
VSSQ G9 96-BALL
VSSQ SDRAM DDR3
96-BALL K4W1G1646E-HC12_FBGA96
SDRAM DDR3 X76@
K4W1G1646E-HC12_FBGA96
CLKA0 1 2
MARS@ X76@
RV60 40.2_0402_1%
CLKA0# 1 2
MARS@
RV61 40.2_0402_1%
1
CV195 +1.5VGS
0.01U_0402_16V7K +1.5VGS
MARS@
2
1
MARS@
1
MARS@ RV63
RV62 4.99K_0402_1%
4.99K_0402_1%
B B
15mil
2
15mil
2
+VREFC_A1
+VREFC_A0
0.1U_0402_16V7K
CV104
MARS@
1
1
0.1U_0402_16V7K
CV103
MARS@ RV65
1
RV64 4.99K_0402_1%
4.99K_0402_1% MARS@
2
MARS@
2
2
2
+1.5VGS
+1.5VGS +1.5VGS
10U_0603_6.3V6M
CV105
1U_0402_6.3V6K
CV106
1U_0402_6.3V6K
CV107
1U_0402_6.3V6K
CV108
1U_0402_6.3V6K
CV109
1U_0402_6.3V6K
CV112
1U_0402_6.3V6K
CV113
10U_0603_6.3V6M
CV115
10U_0603_6.3V6M
CV116
1U_0402_6.3V6K
CV117
1U_0402_6.3V6K
CV118
1U_0402_6.3V6K
CV119
1U_0402_6.3V6K
CV120
1U_0402_6.3V6K
CV121
1U_0402_6.3V6K
CV122
0.1U_0402_16V7K
CV124
0.1U_0402_16V7K
CV125
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
@
A A

ATI_Whistler_M2_VRAM_A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C QIQY2 LA6884P 0.3
5 4 3 2 1
5 4 3 2 1
UV7
UV8
+VREFC_A2 M8 E3 MDA38
H1 VREFCA DQL0 F7 MDA36 +VREFC_A3 M8 E3 MDA49
VREFDQ DQL1 F2 MDA39 H1 VREFCA DQL0 F7 MDA51
MAA0 N3 DQL2 F8 MDA34 VREFDQ DQL1 F2 MDA48
MAA1 P7 A0 DQL3 H3 MDA35 MAA0 N3 DQL2 F8 MDA52
D
MAA2 P3 A1 DQL4 H8 MDA33 MAA1 P7 A0 DQL3 H3 MDA50 D
MAA3 N2 A2 DQL5 G2 MDA37 MAA2 P3 A1 DQL4 H8 MDA53
MAA4 P8 A3 DQL6 H7 MDA32 MAA3 N2 A2 DQL5 G2 MDA55
MAA5 P2 A4 DQL7 MAA4 P8 A3 DQL6 H7 MDA54
MAA6 R8 A5 MAA5 P2 A4 DQL7
MAA7 R2 A6 D7 MDA42 MAA6 R8 A5
MAA8 T8 A7 DQU0 C3 MDA44 MAA7 R2 A6 D7 MDA60
MAA9 R3 A8 DQU1 C8 MDA40 MAA8 T8 A7 DQU0 C3 MDA57
MDA[32..63] MAA10 L7 A9 DQU2 C2 MDA46 MAA9 R3 A8 DQU1 C8 MDA63
<28> MDA[32..63] MAA11 R7 A10/AP DQU3 A7 MDA43 MAA10 L7 A9 DQU2 C2 MDA56
MAA12 N7 A11 DQU4 A2 MDA45 MAA11 R7 A10/AP DQU3 A7 MDA61
MAA13 T3 A12 DQU5 B8 MDA41 MAA12 N7 A11 DQU4 A2 MDA59
MAA14 T7 A13 DQU6 A3 MDA47 MAA13 T3 A12 DQU5 B8 MDA62
MAA15 M7 A14 DQU7 MAA14 T7 A13 DQU6 A3 MDA58
MAA[15..0] A15/BA3 +1.5VGS MAA15 M7 A14 DQU7
<28,29> MAA[15..0] A15/BA3 +1.5VGS
A_BA0 M2 B2
<28,29> A_BA0 BA0 VDD
A_BA1 N8 D9 A_BA0 M2 B2
<28,29> A_BA1 M3 BA1 VDD G7 N8 BA0 VDD D9
A_BA2 A_BA1
<28,29> A_BA2 BA2 VDD BA1 VDD
K2 A_BA2 M3 G7
VDD K8 BA2 VDD K2
VDD N1 VDD K8
J7 VDD N9 VDD N1
<28> CLKA1 K7 CK VDD R1 J7 VDD N9
CLKA1
<28> CLKA1# CK VDD CK VDD
K9 R9 CLKA1# K7 R1
<28> CKEA1 CKE/CKE0 VDD +1.5VGS CK VDD
CKEA1 K9 R9
CKE/CKE0 VDD +1.5VGS
K1 A1
<28> ODTA1 L2 ODT/ODT0 VDDQ A8 K1 A1
ODTA1
<28> CSA1#_0 CS/CS0 VDDQ ODT/ODT0 VDDQ
J3 C1 CSA1#_0 L2 A8
<28> RASA1# RAS VDDQ CS/CS0 VDDQ
K3 C9 RASA1# J3 C1
<28> CASA1# L3 CAS VDDQ D2 K3 RAS VDDQ C9
CASA1#
<28> WEA1# WE VDDQ CAS VDDQ
E9 WEA1# L3 D2
VDDQ F1 WE VDDQ E9
QSA4 F3 VDDQ H2 VDDQ F1
<28> QSA4 DQSL VDDQ VDDQ
QSA5 C7 H9 QSA6 F3 H2
<28> QSA5 DQSU VDDQ <28> QSA6 C7 DQSL VDDQ H9
QSA7
<28> QSA7 DQSU VDDQ
C C
DQMA4 E7 A9
<28> DQMA4 DML VSS
DQMA5 D3 B3 DQMA6 E7 A9
<28> DQMA5 DMU VSS <28> DQMA6 DML VSS
E1 DQMA7 D3 B3
VSS G8 <28> DQMA7 DMU VSS E1
QSA#4 G3 VSS J2 VSS G8
<28> QSA#4 B7 DQSL VSS J8 G3 VSS J2
QSA#5 QSA#6
<28> QSA#5 DQSU VSS <28> QSA#6 DQSL VSS
M1 QSA#7 B7 J8
VSS <28> QSA#7 DQSU VSS
M9 M1
VSS P1 VSS M9
DRAM_RST# T2 VSS P9 VSS P1
<28,29,31,32> DRAM_RST# RESET VSS T1 VSS
DRAM_RST# T2 P9
L8 VSS T9 RESET VSS T1
ZQ/ZQ0 VSS L8 VSS T9
ZQ/ZQ0 VSS
1
J1 B1
NC/ODT1 VSSQ
1
RV86 L1 B9 J1 B1
J9 NC/CS1 VSSQ D1 RV87 L1 NC/ODT1 VSSQ B9
240_0402_1% NC/CE1 VSSQ NC/CS1 VSSQ
L9 D8 240_0402_1% J9 D1
MARS@ NCZQ1 VSSQ E2 MARS@ L9 NC/CE1 VSSQ D8
2
VSSQ E8 NCZQ1 VSSQ E2
2
VSSQ F9 VSSQ E8
VSSQ G1 VSSQ F9
VSSQ G9 VSSQ G1
VSSQ VSSQ G9
96-BALL VSSQ
SDRAM DDR3 96-BALL
K4W1G1646E-HC12_FBGA96 SDRAM DDR3
X76@ K4W1G1646E-HC12_FBGA96
X76@
+1.5VGS
B B
+1.5VGS
1
MARS@
CLKA1 1 2
MARS@ RV67
1
RV66 40.2_0402_1% MARS@ 4.99K_0402_1%

RV68
4.99K_0402_1%
15mil
2
CLKA1# 1 2
MARS@
RV69 40.2_0402_1% +VREFC_A3
15mil
2
1
CV196
0.1U_0402_16V7K
CV126
0.01U_0402_16V7K +VREFC_A2 MARS@
1
MARS@ RV70
2
0.1U_0402_16V7K
CV127
MARS@ 4.99K_0402_1%
1
RV71 MARS@
2
4.99K_0402_1%
2
MARS@
2
2
+1.5VGS
+1.5VGS +1.5VGS
10U_0603_6.3V6M
CV128
1U_0402_6.3V6K
CV129
0.1U_0402_16V7K
CV130
1U_0402_6.3V6K
CV132
0.1U_0402_16V7K
CV134
1U_0402_6.3V6K
CV135
1U_0402_6.3V6K
CV136
10U_0603_6.3V6M
CV138
10U_0603_6.3V6M
CV139
1U_0402_6.3V6K
CV141
1U_0402_6.3V6K
CV144
1U_0402_6.3V6K
CV145
1U_0402_6.3V6K
CV146
0.1U_0402_16V7K
CV147
1U_0402_6.3V6K
CV148
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
A A

5 4 3 2 1
5 4 3 2 1
UV9 UV10
+VREFC_B0 M8 E3 MDB19 +VREFC_B1 M8 E3 MDB26

H1 VREFCA DQL0 F7 MDB20 H1 VREFCA DQL0 F7 MDB30
VREFDQ DQL1 F2 MDB22 VREFDQ DQL1 F2 MDB24
MAB0 N3 DQL2 F8 MDB16 MAB0 N3 DQL2 F8 MDB29
MAB1 P7 A0 DQL3 H3 MDB23 MAB1 P7 A0 DQL3 H3 MDB27
MAB3 N2 A2 DQL5 G2 MDB21 MAB3 N2 A2 DQL5 G2 MDB25
MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7
D
MAB6 R8 A5 MAB6 R8 A5 D
MAB7 R2 A6 D7 MDB0 MAB7 R2 A6 D7 MDB15
MDB[0..31] MAB8 T8 A7 DQU0 C3 MDB4 MAB8 T8 A7 DQU0 C3 MDB10
<28> MDB[0..31] MAB9 R3 A8 DQU1 C8 MDB1 MAB9 R3 A8 DQU1 C8 MDB14
MAB10 L7 A9 DQU2 C2 MDB6 MAB10 L7 A9 DQU2 C2 MDB11
MAB11 R7 A10/AP DQU3 A7 MDB3 MAB11 R7 A10/AP DQU3 A7 MDB12
MAB12 N7 A11 DQU4 A2 MDB7 MAB12 N7 A11 DQU4 A2 MDB9
MAB13 T3 A12 DQU5 B8 MDB2 MAB13 T3 A12 DQU5 B8 MDB13
MAB[15..0] MAB14 T7 A13 DQU6 A3 MDB5 MAB14 T7 A13 DQU6 A3 MDB8
<28,32> MAB[15..0] A14 DQU7 A14 DQU7
MAB15 M7 MAB15 M7
A15/BA3 +1.5VGS A15/BA3 +1.5VGS
M2 B2 B_BA0 M2 B2
<28,32> B_BA0 N8 BA0 VDD D9 N8 BA0 VDD D9
B_BA1
<28,32> B_BA1 BA1 VDD BA1 VDD
M3 G7 B_BA2 M3 G7
K2 K2
VDD K8 VDD K8
VDD N1 VDD N1
J7 VDD N9 CLKB0 J7 VDD N9
<28> CLKB0 CK VDD CK VDD
K7 R1 CLKB0# K7 R1
<28> CLKB0# CK VDD CK VDD
K9 R9 CKEB0 K9 R9
<28> CKEB0 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS
K1 A1 ODTB0 K1 A1
<28> ODTB0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSB0#_0 L2 A8
<28> CSB0#_0 CS/CS0 VDDQ CS/CS0 VDDQ
J3 C1 RASB0# J3 C1
<28> RASB0# K3 RAS VDDQ C9 K3 RAS VDDQ C9
CASB0#
<28> CASB0# CAS VDDQ CAS VDDQ
L3 D2 WEB0# L3 D2
<28> WEB0# WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1
QSB2 F3 VDDQ H2 QSB3 F3 VDDQ H2
<28> QSB2 C7 DQSL VDDQ H9 <28> QSB3 C7 DQSL VDDQ H9
QSB0 QSB1
<28> QSB0 DQSU VDDQ <28> QSB1 DQSU VDDQ
DQMB2 E7 A9 DQMB3 E7 A9
<28> DQMB2 DML VSS <28> DQMB3 DML VSS
DQMB0 D3 B3 DQMB1 D3 B3
<28> DQMB0 DMU VSS E1 <28> DQMB1 DMU VSS E1
VSS G8 VSS G8
C C
QSB#2 G3 VSS J2 QSB#3 G3 VSS J2
<28> QSB#2 DQSL VSS <28> QSB#3 DQSL VSS
QSB#0 B7 J8 QSB#1 B7 J8
<28> QSB#0 DQSU VSS <28> QSB#1 DQSU VSS
CLKB0 1 PX@ 2 M1 M1
RV72 40.2_0402_1% VSS M9 VSS M9
VSS P1 VSS P1
T2 VSS P9 DRAM_RST# T2 VSS P9
<28,29,30,32> DRAM_RST# RESET VSS RESET VSS
CLKB0# 1 PX@ 2 T1 T1
RV73 40.2_0402_1% L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
CV197
1
0.01U_0402_16V7K J1 B1 J1 B1
PX@ RV88 L1 NC/ODT1 VSSQ B9 RV89 L1 NC/ODT1 VSSQ B9
2
J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1

240_0402_1% NC/CE1 VSSQ 240_0402_1% NC/CE1 VSSQ
L9 D8 L9 D8
PX@ NCZQ1 VSSQ E2 PX@ NCZQ1 VSSQ E2
2
2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
X76@ X76@
+1.5VGS
+1.5VGS
1
PX@
1
PX@ RV75
RV74 4.99K_0402_1%
4.99K_0402_1%
15mil
2
B B
15mil
2
+VREFC_B1
+VREFC_B0
0.1U_0402_16V7K
CV150
PX@
1
1
0.1U_0402_16V7K
CV149
PX@ RV77
1
RV76 4.99K_0402_1%
4.99K_0402_1% PX@
2
PX@
2
2
2
+1.5VGS
+1.5VGS +1.5VGS
1U_0402_6.3V6K
CV152
1U_0402_6.3V6K
CV154
1U_0402_6.3V6K
CV155
1U_0402_6.3V6K
CV156
0.1U_0402_16V7K
CV158
0.1U_0402_16V7K
CV159
0.1U_0402_16V7K
CV160
10U_0603_6.3V6M
CV161
10U_0603_6.3V6M
CV162
1U_0402_6.3V6K
CV164
1U_0402_6.3V6K
CV165
1U_0402_6.3V6K
CV166
1U_0402_6.3V6K
CV167
0.1U_0402_16V7K
CV168
0.1U_0402_16V7K
CV169
0.1U_0402_16V7K
CV170
0.1U_0402_16V7K
CV171
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
A A

ATI_Whistler_M2_VRAM_B
5 4 3 2 1
5 4 3 2 1
UV11 UV12
+VREFC_B2 M8 E3 MDB33 +VREFC_B3 M8 E3 MDB55

H1 VREFCA DQL0 F7 MDB37 H1 VREFCA DQL0 F7 MDB50
VREFDQ DQL1 F2 MDB35 VREFDQ DQL1 F2 MDB54
MAB0 N3 DQL2 F8 MDB39 MAB0 N3 DQL2 F8 MDB51
MAB3 N2 A2 DQL5 G2 MDB34 MAB3 N2 A2 DQL5 G2 MDB52
MDB[32..63] MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7
<28> MDB[32..63] MAB6 R8 A5 MAB6 R8 A5
MAB7 R2 A6 D7 MDB44 MAB7 R2 A6 D7 MDB56
D
MAB8 T8 A7 DQU0 C3 MDB41 MAB8 T8 A7 DQU0 C3 MDB59 D
MAB9 R3 A8 DQU1 C8 MDB47 MAB9 R3 A8 DQU1 C8 MDB63
MAB10 L7 A9 DQU2 C2 MDB43 MAB10 L7 A9 DQU2 C2 MDB62
MAB[15..0] MAB11 R7 A10/AP DQU3 A7 MDB45 MAB11 R7 A10/AP DQU3 A7 MDB57
<28,31> MAB[15..0] A11 DQU4 A11 DQU4
MAB12 N7 A2 MDB40 MAB12 N7 A2 MDB61
MAB13 T3 A12 DQU5 B8 MDB46 MAB13 T3 A12 DQU5 B8 MDB58
MAB14 T7 A13 DQU6 A3 MDB42 MAB14 T7 A13 DQU6 A3 MDB60
MAB15 M7 A14 DQU7 MAB15 M7 A14 DQU7
A15/BA3 +1.5VGS A15/BA3 +1.5VGS
B_BA0 M2 B2 B_BA0 M2 B2
<28,31> B_BA0 N8 BA0 VDD D9 N8 BA0 VDD D9
B_BA1 B_BA1
B_BA2 M3 G7 B_BA2 M3 G7
<28,31> B_BA2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8
VDD N1 VDD N1
J7 VDD N9 CLKB1 J7 VDD N9
<28> CLKB1 CK VDD CK VDD
K7 R1 CLKB1# K7 R1
<28> CLKB1# K9 CK VDD R9 K9 CK VDD R9
CKEB1
<28> CKEB1 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS
K1 A1 ODTB1 K1 A1
<28> ODTB1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSB1#_0 L2 A8
<28> CSB1#_0 J3 CS/CS0 VDDQ C1 J3 CS/CS0 VDDQ C1
RASB1#
<28> RASB1# RAS VDDQ RAS VDDQ
K3 C9 CASB1# K3 C9
<28> CASB1# CAS VDDQ CAS VDDQ
L3 D2 WEB1# L3 D2
<28> WEB1# WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1
QSB4 F3 VDDQ H2 QSB6 F3 VDDQ H2
<28> QSB4 DQSL VDDQ <28> QSB6 DQSL VDDQ
QSB5 C7 H9 QSB7 C7 H9
<28> QSB5 DQSU VDDQ <28> QSB7 DQSU VDDQ
DQMB4 E7 A9 DQMB6 E7 A9
<28> DQMB4 D3 DML VSS B3 <28> DQMB6 D3 DML VSS B3
DQMB5 DQMB7
<28> DQMB5 DMU VSS <28> DQMB7 DMU VSS
E1 E1
VSS G8 VSS G8
QSB#4 G3 VSS J2 QSB#6 G3 VSS J2
<28> QSB#4 DQSL VSS <28> QSB#6 DQSL VSS
C QSB#5 B7 J8 QSB#7 B7 J8 C
<28> QSB#5 DQSU VSS M1 <28> QSB#7 DQSU VSS M1
VSS M9 VSS M9
VSS P1 VSS P1
DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9
<28,29,30,31> DRAM_RST# RESET VSS RESET VSS
T1 T1
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
1
J1 B1 J1 B1
RV90 L1 NC/ODT1 VSSQ B9 RV91 L1 NC/ODT1 VSSQ B9
J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1
240_0402_1% NC/CE1 VSSQ 240_0402_1% NC/CE1 VSSQ
L9 D8 L9 D8
PX@ NCZQ1 VSSQ E2 PX@ NCZQ1 VSSQ E2
2
2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
X76@ X76@
+1.5VGS
+1.5VGS
1
PX@
RV78
1
CLKB1 1 PX@ 2 PX@ 4.99K_0402_1%

RV79 40.2_0402_1% RV80
4.99K_0402_1%
15mil
2
CLKB1# 1 PX@ 2
RV81 40.2_0402_1% +VREFC_B3
15mil
2
1
1
B B
0.1U_0402_16V7K
CV172
CV198 +VREFC_B2 PX@
1
0.01U_0402_16V7K RV82
1
0.1U_0402_16V7K
CV173
PX@ PX@ 4.99K_0402_1%

2
RV83 PX@
2
4.99K_0402_1%
2
PX@
2
2
+1.5VGS
+1.5VGS +1.5VGS
10U_0603_6.3V6M
CV174
1U_0402_6.3V6K
CV175
1U_0402_6.3V6K
CV176
1U_0402_6.3V6K
CV177
1U_0402_6.3V6K
CV178
1U_0402_6.3V6K
CV179
0.1U_0402_16V7K
CV181
1U_0402_6.3V6K
CV183
10U_0603_6.3V6M
CV184
10U_0603_6.3V6M
CV185
1U_0402_6.3V6K
CV186
1U_0402_6.3V6K
CV187
1U_0402_6.3V6K
CV188
1U_0402_6.3V6K
CV189
1U_0402_6.3V6K
CV190
0.1U_0402_16V7K
CV191
0.1U_0402_16V7K
CV192
0.1U_0402_16V7K
CV193
0.1U_0402_16V7K
CV194
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
@
A A

5 4 3 2 1
5 4 3 2 1
+3VS +3VS_PS
RTD2132R LDO MODE
80mil 1 2
80mil +SWR_V12 1 2 +SWR_LX
@
RT1 0_0805_5% R551 0_0805_5%
+3VS_PS
Close to Pin3 UT2
19
TXEC+ LVDS_ACLK <34>
+DP_V33 LT1 2 1 +DP_V33 40mil 3 20
LVDS_ACLK# <34>
FBMA-L11-201209-221LMA30T_0805 DP_V33 TXEC-
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K 60mil 13 21
SWR_VDD TXE2+ LVDS_A2 <34>
Power
D LT2 2 1 +SWR_VDD 18 22 D
1 1 1
LVDS
PVCC TXE2- LVDS_A2# <34>
FBMA-L11-201209-221LMA30T_0805
CT1
CT2
CT3
+SWR_V12 ~@ LT3 1 2 +SWR_LX 20mil 12 23
LVDS_A1 <34>
SWR_LX TXE1+
2 2 2
4.7UH_PG031B-4R7MS_1.1A_20% 60mil 11 SWR_VCCK TXE1-
24
LVDS_A1# <34>
27
7 VCCK 25
DP_V12 TXE0+ LVDS_A0 <34>
26
TXE0- LVDS_A0# <34>
RTD2132S TL_ENVDD need 60 mil if use for LVDS power on R version

C190 1 2 0.1U_0402_16V7K EDP_CPU_AUX_R 2
<8> EDP_CPU_AUX AUX_P
DP-IN
C191 1 2 0.1U_0402_16V7K EDP_CPU_AUX#_R 1 14
GPIO
<8> EDP_CPU_AUX# AUX_N GPIO(PWM OUT) TL_INVT_PWM <34>
Close to pin11 Close to Pin18 15
GPIO(Panel_VCC) TL_ENVDD <34>
C192 1 2 0.1U_0402_16V7K EDP_CPU_LANE_P0_R 5 16
<8> EDP_CPU_LANE_P0 LANE0P GPIO(PWM IN) PCH_PWM <15>
+SWR_VDD C193 1 2 0.1U_0402_16V7K EDP_CPU_LANE_N0_R 6 17 ENBKL <43>
<8> EDP_CPU_LANE_N0 LANE0N GPIO(BL_EN)
10U_0603_6.3V6M
0.1U_0402_16V7K
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1 1 1 1 9 LVDS 29
<17,24,40,43> EC_SMB_CK2 CIICSCL1 MIICSCL1 EDID_CLK <34>
10 28
<17,24,40,43> EC_SMB_DA2 CIICSDA1 EDID MIICDA1 EDID_DATA <34>
CT4
CT5
CT6
CT7
CT8
Other
2 2 2 2 2 32 ROM 31 MIIC_SCL
<8> TL_HPD HPD MIICSCL0 30 MIIC_SDA
8 MIICSDA0 ADD TP on trace or via
4 DP_REXT 33
DP_GND GND
2
Close to Pin13
RT8 RTD2132R-VE-CG_QFN32_5X5
12K_0402_1%
1
Close to LT3 +3VS_PS
C C
+SWR_V12 EDID_DATA RT9 1 2 4.7K_0402_5%
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
EDID_CLK RT10 1 2 4.7K_0402_5%

1 1 1 1
CT9
CT10
CT11
CT12
2 2 2 2
Close to
Pin27
Close to Pin7
+3VS_PS
ENBKL
2
RT4
4.7K_0402_5%
2
R438
1
100K_0402_5% MIIC_SCL MIIC_SDA
2
RT12
4.7K_0402_5%
B B
1
MIIC_SDA
MIIC_SCL
0 1
0 X EC CODE
1 Internal ROM EEPROM
A A

LVDS Translator - RTD2132S
5 4 3 2 1
5 4 3 2 1
LCD POWER CIRCUIT CMOS Camera

+3VS W=60mils W=60mils +LCDVDD_CONN +3VS
U72 @
1 +LCDVDD_CONN (20 MIL)
5 VOUT +3VS_CMOS
4.7U_0603_6.3V6K
VIN Q83
LP2301ALT1G_SOT23-3
C516
D 2 1 D
4 GND
SS (20 MIL)
D
3 1 10U
1 3 1
EN 2 CMOS@
@ C4 APL3512ABI-TRG_SOT23-5 C519 @
G
2
1500P_0402_50V7K R02 10U_0603_6.3V6M
2 CMOS@ 2
<33> TL_ENVDD 150K_0402_5%
<43> CMOS_ON#
R435
1
R296 for CMOS shake issue reserve
C520 CMOS@
+LCDVDD_CONN 0.1U_0402_16V7K
1
2
W=60mils
R408
100K_0402_5%
TL_ENVDD 1 @ 2
2
R553 0_0805_5%
VGA LCD/PANEL BD. Conn.

C C
RTD2132R Internal load switch for +LCD_VCC +LEDVDD B+
R813 1 2
1 0_0805_5%
@
C541
4.7U_0805_25V6-K
BKOFF# 2
1
JLVDS1
R716 1
2 1 31
10K_0402_5% 2 G1
3 32
4 3 G2 33
2
5 4 G3 34
<43> BKOFF# 5 G4
R39 1 @ 2 0_0402_5% 6
BKOFF# 7 6
R441 1 2 0_0402_5% INVT_PWM 8 7
<33> TL_INVT_PWM 8
9
10 9
<33> LVDS_ACLK 10
11
<33> LVDS_ACLK# 11
12
13 12
B B
<33> LVDS_A2 13
14
<33> LVDS_A2# 14
15
<33> LVDS_A1 15
16
<33> LVDS_A1# 16
17
<33> LVDS_A0 18 17
<33> LVDS_A0# 18
<33> EDID_DATA 19
20 19
<33> EDID_CLK 20
+3VS 21
22 21
+LCDVDD_CONN 22
(60 MIL) 23
24 23
+3VS 24
25
26 25
+3VS_CMOS 26
USB20_P3 0_0402_5% 2 1 R688 USB20_P3_R 27
USB20_N3 0_0402_5% 2 1 R684 USB20_N3_R 28 27
29 28
30 29
30
CMOS 4 3 USB20_P3_R
4 3 ACES_88341-3001 ME@
<18> USB20_P3
<18> USB20_N3
1 2 USB20_N3_R
1 2
L58 WCM-2012-900T_4P
A A
~@

LVDS/CAMERA
Custom 0.3
LA-9641P
5 4 3 2 1
A B C D E
CRT Connector
1 1
FCM1608CF-121T03 0603
1 2 RED
<15> DAC_RED
L30
FCM1608CF-121T03 0603 +5V_Display
1 2 GREEN
<15> DAC_GRN
L31
FCM1608CF-121T03 0603 CONTE_80431-5K1-152
1 2 BLUE
<15> DAC_BLU
C522
C523
C524
C525
C526
C527
L32 JCRT1 ME@
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
1 1 1 1 1 1 6
RP22 PAD T66 NC11 11
4 5 DAC_BLU RED 1
3 6 DAC_GRN 7
2 7 DAC_RED 2 2 2 2 2 2 CRT_DDC_DAT_CONN 12
1 8 GREEN 2
8 G 16
150_0804_8P4R_5% JVGA_HS_R 13 17
BLUE 3 G
9
JVGA_VS_R 14
4
2 10 2
CRT_DDC_CLK_CONN 15
5
+5VS
1 1
C529 C531 @
U10
0.1U_0402_16V7K 0.1U_0402_16V7K
2 2 1 8 1 2
VCC_SYNC BYP C6 0.22U_0402_10V6K +5V_Display
2 3 RED
+3VS VCC_VIDEO VIDEO1
1
7 4 GREEN
VCC_DDC VIDEO2 R31 R33
1 4.7K_0402_5% 4.7K_0402_5%
<15> CRT_DDC_DATA 10 5 BLUE
C537 DDC_IN1 VIDEO3
2
3 3
0.1U_0402_16V7K
2 11 9 CRT_DDC_DAT_CONN
<15> CRT_DDC_CLK DDC_IN2 DDC_OUT1
13 12 CRT_DDC_CLK_CONN
<15> CRT_VSYNC SYNC_IN1 DDC_OUT2
15 14 JVGA_VS 1 R411 2 JVGA_VS_R

<15> CRT_HSYNC SYNC_IN2 SYNC_OUT1 22_0402_5%
6 16 JVGA_HS 1 R412 2 JVGA_HS_R

GND SYNC_OUT2 22_0402_5%
TPD7S019-15DBQR_SSOP16
10P_0402_50V8J
10P_0402_50V8J
1 1
C411
C412
2 2
@ @
4 4

CRT Connector
Custom 0.3
LA-9641P
A B C D E
5 4 3 2 1
+5V_Display
U73
+5VS 3
W=40mils
OUT
1
L35 HDMI@ 1
HDMI_CLK+_CK 1 2 HDMI_CLK+_CONN IN C543
<8> HDMI_CLK+_CK 1 2 1
2
C544 GND 0.1U_0402_16V7K 2
D HDMI_CLK-_CK 4 3 HDMI_CLK-_CONN D
<8> HDMI_CLK-_CK 4 3 +3VS 0.1U_0402_16V7K 2 AP2330W-7_SC59-3
WCM-2012HS-900T
L36 HDMI@
2
<8> HDMI_TX0+_CK HDMI_TX0+_CK 1 2 HDMI_TX0+_CONN
1 2 R485
1M_0402_5% Q93
<8> HDMI_TX0-_CK HDMI_TX0-_CK 4 3 HDMI_TX0-_CONN HDMI@ HDMI@
4 3
2
G
2N7002H_SOT23-3
1
WCM-2012HS-900T
TMDS_B_HPD 3 1 HDMI_DET
<15> TMDS_B_HPD
L37 HDMI@
D
<8> HDMI_TX1+_CK HDMI_TX1+_CK 1 2 HDMI_TX1+_CONN
1 2
2
HDMI_TX1-_CK 4 3 HDMI_TX1-_CONN R488
<8> HDMI_TX1-_CK 4 3
20K_0402_5%
WCM-2012HS-900T HDMI@
1
L38 HDMI@ JHDMI1 ME@
HDMI_TX2+_CK 1 2 HDMI_TX2+_CONN 19
<8> HDMI_TX2+_CK 1 2 HP_DET
18
+5V_Display +5V
17
C DDC/CEC_GND C
HDMI_TX2-_CK 4 3 HDMI_TX2-_CONN HDMIDAT_R 16
<8> HDMI_TX2-_CK 4 3 SDA
HDMICLK_R 15
WCM-2012HS-900T 14 SCL
13 Reserved
HDMI_CLK-_CONN 12 CEC 20
11 CK- G1 21
+3VS HDMI_CLK+_CONN 10 CK_shield G2 22
HDMI_TX0-_CONN 9 CK+ G3 23
8 D0- G4
HDMI_TX0+_CONN 7 D0_shield
HDMI_TX1-_CONN 6 D0+
Q63A 5 D1-
HDMI@ HDMI_TX1+_CONN 4 D1_shield
D1+
2
2N7002DW-T/R7_SOT363-6 HDMI_TX2-_CONN 3
2 D2-
1 6 HDMICLK_R HDMI_TX2+_CONN 1 D2_shield
<15> HDMICLK_NB D2+
5
SUYIN_100042GR019M23DZL
<15> HDMIDAT_NB 4 3 HDMIDAT_R

+5V_Display
Q63B 680 +-5% 8P4R
HDMI@ +3VS RP21 HDMI_TX1+_CONN 5 4
B 2N7002DW-T/R7_SOT363-6 8 1 HDMIDAT_R HDMI_TX1-_CONN 6 3 B
7 2 HDMICLK_R HDMI_CLK+_CONN 7 2
6 3 HDMIDAT_NB HDMI_CLK-_CONN 8 1
5 4 HDMICLK_NB
RP5 HDMI@
2.2K_0804_8P4R_5%
HDMI@ 680 +-5% 8P4R
HDMI_TX0+_CONN 5 4
HDMI_TX0-_CONN 6 3
@ D32 @ D28 @ D29 HDMI_TX2+_CONN 7 2
HDMICLK_R 9 10 1 1 HDMICLK_R HDMI_TX1+_CONN 9 10 1 1 HDMI_TX1+_CONN HDMI_TX0+_CONN 9 10 1 1 HDMI_TX0+_CONN HDMI_TX2-_CONN 8 1
HDMIDAT_R 8 9 2 2 HDMIDAT_R HDMI_TX1-_CONN 8 9 2 2 HDMI_TX1-_CONN HDMI_TX0-_CONN 8 9 2 2 HDMI_TX0-_CONN RP6 HDMI@

+3VS
HDMI_DET 7 7 4 4 HDMI_DET HDMI_CLK+_CONN 7 7 4 4 HDMI_CLK+_CONN HDMI_TX2+_CONN 7 7 4 4 HDMI_TX2+_CONN
1
D
6 6 5 5 HDMI_CLK-_CONN 6 6 5 5 HDMI_CLK-_CONN HDMI_TX2-_CONN 6 6 5 5 HDMI_TX2-_CONN 2
G
3 3 3 3 3 3 S Q95
3
HDMI@
8 8 8 2N7002H_SOT23-3
YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9

A A
Security Classification Compal Secret Data Compal Electronics,Ltd.

HDMI CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 0.3
LA-9641P
5 4 3 2 1
A B C D E
Mini-Express Card for WLAN/WiMAX(Half)
1 1
+3VS_WLAN
+3VS 80mil +3VS_WLAN

J6 1 1
@
C548@ C547@
Mini-Express Card(WLAN/WiMAX) 1
1 2
2
+1.5VS
4.7U_0603_6.3V6K 0.1U_0402_16V7K
2 2
JUMP_43X79
EMI reserve
@ JWLN1
PCIE_WAKE# 1 2 1 2
<15,38> PCIE_WAKE# 1 2
R41 0_0402_5% 3 4
5 3 4 6
<19> PCH_BT_ON# 5 6
<16> CLKREQ_WLAN# 7 8
9 7 8 10
11 9 10 12
<16> CLK_PCIE_WLAN# 11 12
13 14
<16> CLK_PCIE_WLAN 15 13 14 16
17 15 16 18
19 17 18 20
21 19 20 22 PCH_WL_OFF# <15>
21 22 PLT_RST# <15,23,38,43>
23 24 +3VS_WLAN
2 <18> PCIE_PRX_DTX_N2 25 23 24 26
2
<18> PCIE_PRX_DTX_P2 25 26
27 28 R02
29 27 28 30 1 R501 2 @ 0_0402_5%
29 30 SMB_CLK_S3 <12,13,17>
31 32 1 R502 2 @ 0_0402_5%
<18> PCIE_PTX_C_DRX_N2 31 32 SMB_DATA_S3 <12,13,17>
33 34
<18> PCIE_PTX_C_DRX_P2 35 33 34 36
+3VS_WLAN 35 36 USB20_N10 <18>
37 38
39 37 38 40 USB20_P10 <18>
41 39 40 42
43 41 42 44
100_0402_1% 45 43 44 46
R505 47 45 46 48
1 2 49 47 48 50
<43,44> EC_TX 1 2 51 49 50 52
<43,44> EC_RX 51 52
R506
100_0402_1% 53 54
GND1 GND2
DVT
1 R405 2
<19> INTEL_BT_OFF#
1K_0402_5% BELLW_80003-8041
2
ME@
R507
100K_0402_5%
3 For EC to detect 3
1 debug card insert.
4 4

Mini-Card/NEW Card/SIM
Document Number Rev
0.3
LA-9641P
A B C D E
5 4 3 2 1
+3VALW +3V_LAN
+LX
Layout Notice : Place as close Close together
chip as possible. J10
@
LL2 LL3 SWR@
1 2 LL1 SWR@
1 2 +1.1_DVDDL 1 2 +LX FBMA-L11160808601LMA10T_2P FBMA-L11160808601LMA10T_2P
1000P_0402_50V7K
1 2 1 2
10U_0603_6.3V6M
4.7UH_SIA4012-4R7M_20% +1.1_AVDDL_L +1.1_AVDDL +1.1_DVDDL
0.1U_0402_16V7K
JUMP_43X79
CL1
CL2
0.1U_0402_16V7K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
D 1 1 D
CL4
CL5
CL6
Note: Place Close to LAN chip 1 1 1
3 1
D
2 2 LL1 DCR< 0.15 ohm
CL3
Rate current > 1A
RL3 2 2 2
QL1
G
2
LAN_PWR_ON# 2 1 LP2301ALT1G_SOT23-3
<43> LAN_PWR_ON# 10U
2 @
10K_0402_5% CL7 SWR@SWR@SWR@
1
0.1U_0402_16V7K Place close to Pin34
@ Close to
@
Pin40
Vendor recommand reseve the UL1 8162@

PU resistor close LAN chip
RL4 1 2 4.7K_0402_5%
+3V_LAN
AR8162-AL3A-R
@
PLT_RST#
<15,23,37,43> PLT_RST#
SA000065410 S IC QCA8172-BL3A-R QFN 40P E-LAN CTRL
SA000052J20 S IC AR8162-AL3A-R QFN 40P E-LAN CTRL
C C
UL1
Place Close to Chip
CL9 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_N3 29 38 RL12 10K_0402_5%
<18> PCIE_PRX_DTX_N3 TX_N LED_0 39 2 LDO@ 1 mount RL12 if use LDO modue
CL11 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P3 30
Atheros LED_1 23
<18> PCIE_PRX_DTX_P3 TX_P LED_2
AR8151/AR8161
36
<18> PCIE_PTX_C_DRX_N3 RX_N 12 MDI0-
35 TRXN0 11 MDI0- <39>
MDI0+
<18> PCIE_PTX_C_DRX_P3 RX_P TRXP0 15 MDI1- MDI0+ <39>
TRXN1 MDI1- <39>
32 14 MDI1+
<16> CLK_PCIE_LAN# 33 REFCLK_N TRXP1 18 MDI1+ <39>
<16> CLK_PCIE_LAN REFCLK_P TRXN2 17
RL6 1 @ 2 0_0402_5% PLT_RST# 2 TRXP2 21
<15,37> PCIE_WAKE# PERST# TRXN3 20
RL7 1 @ 2 0_0402_5% 3 TRXP3 Place Close to PIN1
<43> LAN_WAKE# W AKE#
25 10 LAN_RBIAS 1 2 +3V_LAN
RL9 1 2 4.7K_0402_5% 26 SMCLK RBIAS RL8 2.37K_0402_1%
+3V_LAN SMDATA
@ Place Close to PIN1
28 1 +3V_LAN
NC VDD33
CL12
CL13
CL14
CL15
CL16
27
1000P_0402_50V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
Vendor recommand reseve the
0.1U_0402_16V7K
1U_0402_6.3V6K
TESTMODE 1 1 1 1
2
PU resistor close LAN chip 40 +LX
LX +LX
LAN_XTALO 7
1
LAN_XTALI 8 XTLO RL10 30K_0402_5% 2 2 2 2
RL11 1 @ 2 4.7K_0402_5% XTLI 5 +1.7_VDDCT 1 2
+3V_LAN VDDCT/ISOLAN +3V_LAN
@
B B
4
<16> CLKREQ_LAN# CLKREQ# 24 @ @
DVDDL/PPS 37 +1.1_DVDDL 10U +3V_LAN
+1.1_AVDDL 13 DVDDL_REG/DVDDL
+1.1_AVDDL 19 AVDDL +2.7_AVDDH
+1.1_AVDDL 31 AVDDL 16
AVDDL AVDDH/AVDD33 +3V_LAN
+1.1_AVDDL_L 34 22 +2.7_AVDDH EMI reserve
+1.1_AVDDL 6 AVDDL AVDDH 9 +2.7_AVDDH
AVDDL_REG/AVDDL AVDDH_REG
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V6K
0.1U_0402_16V7K
1U_0402_6.3V6K
CL17
CL18
CL19
CL20
CL21
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1 1 1 1 CL22
CL23
CL24
CL25
CL26
CL10
CL8
@ 41 1 1 1 1 1 1 1
GND
QCA8172-BL3A-R_QFN40_5X5 @ @
2 2 2 2 2
Near 2 2 2 2 2
@
2 2
Pin6 8172@
Place close to Pin16

Near
Near Near Near Pin9 Near Near
Pin13 Pin19 Pin31 Pin22 Pin37
LAN_XTALI
A YL1 LAN_XTALO A
4 3
NC OSC
1 2
OSC NC
1 1
CL28 25MHZ_10PF_7V25000014CL29
15P_0402_50V8J 15P_0402_50V8J Security Classification Compal Secret Data Compal Electronics, Inc.
2 2
LAN-AR8162/8172
Custom 0.3
LA-7982P
5 4 3 2 1
5 4 3 2 1
@
DL1
Place Close to TL1 AZC099-04S.R7G_SOT23-6 Reserve gas tube for EMI go rural solution
MDI1+ 1 4 MDI0+
I/O1 I/O3
DL1 2
GND VDD
5
1'S PN:SC300001G00
D D
2'S PN:SC300002E00 MDI0- 3
I/O2 I/O4
6 MDI1-
RL14 CL30
1 2 1 2
CHASSIS1_GND
75_0805_5% 10P_0603_50V
2 1
TL1
DLL1
MDI0+ 1 16 MDO0+ BS4200N-C-LV_SMB-F2
<38> MDI0+ TD+ TX+
MDI0- 2 15 MDO0- GAS@
<38> MDI0- 3 TD- TX- 14 MCT
4 CT CT 13
5 NC NC 12
NC NC Place Close to TL1
1 6 11 MCT
MDI1+ 7 CT CT 10 MDO1+
<38> MDI1+ 8 RD+ RX+ 9
@ CL31 MDI1- MDO1-
<38> MDI1- RD- RX-
0.01U_0402_16V7K
2
MHPC_NS681612A
C C
CL63 1 2 0.1U_0603_50V7K
CL61 1 2 0.1U_0603_50V7K
CL62 1 2 0.1U_0603_50V7K
Need check Symbol
CL64 1 2 0.1U_0603_50V7K
JLAN1
MDO0+ 1
PR1+
MDO0- 2 CHASSIS1_GND
PR1-
MDO1+ 3
PR2+
MCT 4
PR3+
5
PR3-
B B
MDO1- 6
PR2-
MCT 7 9
PR4+ GND 10
8 GND
PR4-
SANTA_130456-121
ME@
CHASSIS1_GND
A A

LAN_Transformer
Document Number Rev
B 0.3
LA-7982P
5 4 3 2 1
5 4 3 2 1
D +3VGS D
U9
1 8 EC_SMB_CK2
<24> REMOTE1+ VDD SCLK EC_SMB_CK2 <17,24,33,43>
1
REMOTE1+ 2 7 EC_SMB_DA2
D+ SDATA EC_SMB_DA2 <17,24,33,43>
C587
2200P_0402_50V7K REMOTE1- 3 6
2 D- ALERT#
<24> REMOTE1-
+3VS 1 R335 2 4 5
THERM# GND
4.7K_0402_5%
@ EMC1402-2-ACZL-TR MSOP 8P
EMC1412-A (SA00003YA00)
Address 1111_100xb
S IC EMC1412-A-ACZL-TR MSOP 8P SENSOR
REMOTE1,2+/-:
C C
Trace width/space:10/10 mil
Trace length:<8"
CPU VGA_L VGA_R

H1 H2 H3
HOLEA HOLEA HOLEA H4 H5
HOLEA HOLEA
B FD1 FD2 FD3 FD4 B
1
H_3P8 H_3P8 H_3P8
H_3P3 H_3P3
A
B M/B 橢橢橢 M/B 橢橢
FAN1 Conn H7
HOLEA
H8
HOLEA
H10
HOLEA
H11
HOLEA
H12
HOLEA
H18
HOLEA H16
H17
HOLEA
HOLEA
+5VS
1
1
JFAN1
R581 2 1 0_0603_5% 1
2 1 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P5X3P5N H_3P0N
<43> EC_TACH 3 2
<43> EC_FAN_PWM 3
4
A 2 5 4
G5 2P8 * 7 pcd D A
6
C591 G6 E
10U_0603_6.3V6M ACES_85205-04001
1 ME@ Security Classification Compal Secret Data Compal Electronics,Ltd.
10U Fintek-Thermal IC/FAN/screw
Document Number Rev
B 0.3
LA-9641P
5 4 3 2 1
A B C D E F G H
SATA HDD Conn.

JHDD1
1
0.01U_0402_16V7K 2 1 C116 SATA_PTX_DRX_P4 2 GND
<14> SATA_PTX_C_DRX_P4 RX+
<14> SATA_PTX_C_DRX_N4 0.01U_0402_16V7K 2 1 C114 SATA_PTX_DRX_N4 3
4 RX-
SATA_DTX_C_IRX_N4 C596 1 2 0.01U_0402_16V7K SATA_DTX_PRX_N4 5 GND
<14> SATA_DTX_C_PRX_N4 SATA_DTX_C_IRX_P4 C597 1 2 0.01U_0402_16V7K SATA_DTX_PRX_P4 6 TX-
<14> SATA_DTX_C_PRX_P4 7 TX+
GND
1 1
@ 8
R552 1 2 +3V_HDD 9 3.3V
+3VS 3.3V
0_0805_5% 10
11 3.3V
12 GND
13 GND
@ 14 GND
R550 1 2 +5V_HDD 15 5V
+5VS 5V
0_0805_5% 16
17 5V
18 GND
19 Reserved
+5V_HDD 10U 20 GND 23
R02 21 12V GND 24
22 12V GND
12V
1 1 1
SUYIN_127043FB022G278ZR
C598 @ C599 C602
1000P_0402_50V7K 0.1U_0402_16V7K 10U_0603_6.3V6M
2 2 2
2
ODD Power Control 2
@ J9
1 2
1 2 +5V_ODD FOR 15"
EMI reserve
+5VALW +5VS JUMP_43X79
SATA ODD FFC Conn.
S
3 1 ZODD@ JODD2
1 1
1
1
Q99 <14> SATA_PTX_C_DRX_P5 SATA_PTX_C_DRX_P5 R401 1 15@ 2 0_0402_5% SATA_PTX_DRX_P5_15 2

ZODD@ LP2301ALT1G_SOT23-3 C604 SATA_PTX_C_DRX_N5 R402 1 15@ 2 0_0402_5% SATA_PTX_DRX_N5_15 3 2
G
<14> SATA_PTX_C_DRX_N5
2
R568 @ 0.1U_0402_16V7K 4 3
10K_0402_5% R675 2 SATA_DTX_C_PRX_N5 R403 1 15@ 2 0_0402_5% SATA_DTX_PRX_N5_15 5 4
100K_0402_5% <14> SATA_DTX_C_PRX_N5 SATA_DTX_C_PRX_P5 R404 1 15@ 2 0_0402_5% SATA_DTX_PRX_P5_15 6 5
1
2
1 2 <14> SATA_DTX_C_PRX_P5 1 2 ODD_DETECT# 7 6

ZODD@ C608 R710 ZODD@ 0_0402_5% +5V_ODD 8 7
8
1
1 10U_0603_6.3V6M 9
ZODD@ 2 ODD_DA# 10 9
OUT
C607 <43> ODD_DA# R02 10 11

GND 12
0.01U_0402_16V7K GND
2 2 1 R555 2
<19> ODD_EN IN +3VS
ZODD@ 10K_0402_5%
GND
Q100 HB_A051020-SAHR21
3
ME@
3 Co-lay 3
FOR 14"
SATA ODD Conn.
JODD1
1
SATA_PTX_C_DRX_P5 14@ C616 1 2 0.01U_0402_16V7K SATA_PTX_DRX_P5_14 2 GND
SATA_PTX_C_DRX_N5 14@ C615 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N5_14 3 A+
4 A-
SATA_DTX_C_PRX_N5 14@ C614 1 2 0.01U_0402_16V7K SATA_DTX_PRX_N5_14 5 GND
SATA_DTX_C_PRX_P5 14@ C613 1 2 0.01U_0402_16V7K SATA_DTX_PRX_P5_14 6 B-
7 B+
GND
ODD_DETECT# 8
+5V_ODD 9 DP
10 +5V
ODD_DA# 11 +5V
12 MD 15
13 GND GND 14
GND GND
4 ALLTO_C18518-11305-L 4
ME@

HDD/ODD/BT Connector
Custom 0.3
LA-9641P
A B C D E F G H
5 4 3 2 1
CX20751 Sense resistors must be

connected same power
High Definition Audio Codec SoC that is used for VAUX_3.3
With Integrated Class-D Stereo
RA5 1 2 5.11K_0402_1%
Amplifier. +3VS
An integrated 5 V to 3.3 V Low-dropout RA6 10K_0402_1%

mount RA6 on the Jack Sense circuit
voltage regulator (LDO). 1 2 to configure Port-C for mono MIC.
An integrated 3.3 V to 1.8V Low-dropout JSENSE RA7 1 2 20K_0402_1% Don't support LINE_IN function
voltage regulator (LDO). RA8 1 2 39.2K_0402_1% PLUG_IN
RA7 could be @
+VREF_1V65 CA3 vendor suggest
D D
RA1 1 2 0_0402_5% change to 2.2U
+3VLP
+LDO_OUT_3.3V
RA2 1 @ 2 0_0402_5%
1U_0603_10V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
2.2U_0603_6.3V4Z
+3V_PCH AVDD_3.3 pinis output of
1 1 2 1
CA1
CA2
CA4
internal LDO. NOT connect
0.1U_0402_16V7K
4.7U_0603_6.3V6K
CA3
1 1 to external supply.
CA5
CA6
2 2 1 2
2 @ 2
+3VS
+3VS
1U_0603_10V6K
1U_0603_10V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1
CA8
CA9
1 1
Should be same supply rail as used for
CA15
CA10
PCH HDA bus controller section @
For EMI @ 2 2
Layout Note:Path from +5VS to LPWR_5.0
Near Audio Chip 2 2
RPWR_5.0 must be very low
+3VS resistance (<0.01 ohms)
1
0.1U_0402_16V7K
4.7U_0603_6.3V6K
+5VS
RA15 +3V_PCH RA4 1 2 0_0402_5% 1 1
4.7K_0402_5% +LDO_1.8V
CA16
CA17
0.1U_0402_16V7K
4.7U_0603_6.3V6K
+5VS
1 1
CA18
CA19
10 mils
0.1U_0402_16V7K
0.1U_0402_16V7K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2
@ 2 2
1 1 1 1
HDA_RST_AUDIO#
CA20
CA21
CA22
CA23
@
0.1U_0402_16V7K
4.7U_0603_6.3V6K
2 2
1 1 1
CA24
CA25
@ @
CA11 2 2 2 2 Check footprint
C 0.1U_0402_16V7K C
0.1U_0402_16V7K
2 2 2
18
29
27
28
24
1
3
7
2
UA1
CA26
FILT_1.8
VDDO_3.3
DVDD_3.3
AVDD_3.3
VDD_IO
VREF_1.65V
AVDD_5V
AVDD_HP
2
Please bypass caps very close to device. HGNDA, HGNDB 80mils
13
LPWR_5.0 16
HDA_RST_AUDIO# 9 RPWR_5.0 11
<14> HDA_RST_AUDIO# RESET# CLASS-D_REF
HDA_BITCLK_AUDIO 5
<14> HDA_BITCLK_AUDIO BIT_CLK
HDA_SYNC_AUDIO 8 38 JSENSE
<14> HDA_SYNC_AUDIO 1 2 33_0402_5% SYNC JSENSE
RA9 6
<14> HDA_SDIN0 SDATA_IN
HDA_SDOUT_AUDIO 4 34 +MICBIASB
<14> HDA_SDOUT_AUDIO SDATA_OUT MICBIASB 35 +MICBIASC JHP1
MICBIASC APPLE_MIC RA16 1 2 100_0402_1% CA28 1 2 2.2U_0402_6.3V6M HGNDB 4
PC_BEEP 10 32 MICB_L NOKIA_MIC RA12 1 2 100_0402_1% CA27 1 2 2.2U_0402_6.3V6M HGNDA 3
39 PC_BEEP PORTB_L_LINE 33 MICB_R HP_L RA13 1 2 15_0402_5% HPOUT_L 1
<43> EC_MUTE# SPKR_MUTE# PORTB_R_LINE Universal Jack 1 2 2
using wide copper bridge HP_R RA14 15_0402_5% HPOUT_R
under codec (100 mils or more) 30 APPLE_MIC External MIC
PORTD_A_MIC 31 NOKIA_MIC PLUG_IN 5
T3 1 PORTD_B_MIC 25 HGNDA
40 DMIC_DAT/GPIO1 HGNDA 26 HGNDB 6
DMIC_CLK / MUSIC_REQ/GPIO0 HGNDB CA36
MICB_L RA17 1 2 100_0402_1% 1 2 HP_L SINGA_2SJ2352-000131F
Internal analog MIC MIC_IN 36 22 HP_L 2.2U_0402_6.3V6M
37 MUSIC_REQ/GPIO0/PORTC_L_MIC PORTA_L 23 HP_R CA46
GPIO1/PORTC_R_MIC PORTA_R Headphone MICB_R RA18 1 2 100_0402_1% 1 2 HP_R
ME@
CA64 1 2 @ 0.1U_0402_16V7K 2.2U_0402_6.3V6M
RA20 1 2 3K_0402_5%
SPK_L2+ 12
CA65 1 2 @ 0.1U_0402_16V7K SPK_L1- 14 LEFT+ RA19 1 2 3K_0402_5% Pin Ref
LEFT- +MICBIASB
Internal SPEAKER 21 1:L

CA66 1 2 @ 0.1U_0402_16V7K SPK_R2+ 17 AVEE 19 2:R
SPK_R1- 15 RIGHT+ FLY_P 20 1 2 3:GND/MIC
0.1U_0402_16V7K
2.2U_0603_6.3V4Z
RIGHT- FLY_N CA29 1U_0603_10V6K 4:MIC/GND
1 2 for Universal jack
CA35
CA30
5:normal open
GND
CA7
B
6:GND B
1 2 HDA_BITCLK_AUDIO
2 1
41
@ RA21 CX20757-11Z_QFN40
22P_0402_50V8J 33_0402_5% HPOUT_L
@
EMI request reserve RA21 & CA7 HPOUT_L
HPOUT_R
HPOUT_R
CA30 vendor suggest HGNDB
follow vendor suggest change to 2.2U HGNDB
& reserver default design HGNDA
Place colose to Codec chip HGNDA
220P_0402_50V8K
220P_0402_50V8K
220P_0402_50V8K
220P_0402_50V8K
2
AZ5125-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3
+MICBIASC
1 1 1 1
CA31
CA32
CA33
CA34
1
DA1 DA2
PC Beep RA23
2.2K_0402_5%
2 2 2 2 @ @
EC Beep 1 2 RA492 ~@ ~@
<43> BEEP#
2
1
CA37 0.1U_0402_16V7K 1 2 PC_BEEP MIC1 CA41 1U_0603_10V6K LA1 LA2
<14> HDA_SPKR
1 2 33_0402_5% 1 EXT_MIC 1 2 MIC_IN 0_0603_5% 0_0603_5%
CA45 0.1U_0402_16V7K 2 GNDA ~@ ~@
ICH Beep LA3 LA4 LA1~LA4 vendor suggest mount 0 ohm first~
1 1
WM-64PCY_2P 0_0603_5% 0_0603_5% Bead reserve for EMI if needed
0.1U_0402_16V7K
0.1U_0402_16V7K
JSPK1
1
MIC@ CA41 vendor suggest

change to 1U SPK_R1- LA1 1 2
FBMA-L11-160808-121LMT_0603 SPK_R1-_CONN 1
RA22 2 2 SPK_R2+ LA2 1 2
FBMA-L11-160808-121LMT_0603 SPK_R2+_CONN 2 1
1 2 3 2
CA42
CA44
@ 10K_0402_5% SPK_L1- LA3 FBMA-L11-160808-121LMT_0603 SPK_L1-_CONN

SPK_L2+ LA4 1 2
FBMA-L11-160808-121LMT_0603 SPK_L2+_CONN 4 3
2
5 4
@ @ 6 G5
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
G6
wide 20MIL vendor suggest
1 1 1 1
CA38
CA39
CA40
CA43
+5VS ME@
A change to 1000p A
DA3 2 2 2 2 ACES_85205-04001
SPK_R1-_CONN 6 3 SPK_L1-_CONN
I/O4 I/O2
5 2
VDD GND
SPK_R2+_CONN 4
I/O3 I/O1
1 SPK_L2+_CONN Security Classification Compal Secret Data Compal Electronics, Inc.
AZC099-04S.R7G_SOT23-6
CX20751 Codec
@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
LA-7982P
5 4 3 2 1
+3VLP Vcc 3.3V +/- 5%
R301 2 @ 1 0_0603_5% 100K +/- 5%
+3VLP R694
1
C535 Board ID
R304 2 @ 1 0_0603_5% +3VALW_EC @ 100P_0402_50V8J
R695 VAD_BID min V AD_BID typ VAD_BID max
+3VALW
2 0 0 0 V 0 V 0 V MP
L44 12K +/- 5%
FBM-11-160808-601-T_0603
1 0.347V 0.354 V 0.360 V PVT
1 1 1 1 1 1
+EC_VCCA
0.1U_0402_16V7K
C653
0.1U_0402_16V7K
C654
1000P_0402_50V7K
C662
0.1U_0402_16V7K
C655
0.1U_0402_16V7K
C657
1000P_0402_50V7K
C658
1 2 15K +/- 5%
+3VALW_EC
1 1
+EC_VCCA 2 0.423 V 0.430 V 0.438 V DVT
C659 @ @ 33K +/- 5%
C656 @ 2 2 2 2 2 2 3 0.712 V 0.819 V 0.875 V EVT
111
125
0.1U_0402_16V7K 1000P_0402_50V7K U31
22
33
96
67
9
1 2 2 ECAGND 2
L45
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
FBM-11-160808-601-T_0603
1 21 ADP_65
<19> GATEA20 GATEA20/GPIO00 GPIO0F ADP_65 <49>
2 23 BEEP#
<19> KBRST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# <42>
3 26 EC_FAN_PWM
<17> SERIRQ SERIRQ GPIO12 EC_FAN_PWM <40>
4 27 ACOFF
<17> LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 ACOFF <50>
LPC_AD3 5
<17> LPC_AD3 LPC_AD3
LPC_AD2 7 PWM Output
<17> LPC_AD2 LPC_AD2
LPC_AD1 8 63 BATT_TEMP +3VALW
<17> LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMP <48,49>
LPC_AD0 10 LPC & MISC 64
<17> LPC_AD0 LPC_AD0 GPIO39 GPU_IMON <55>
2
2 1 2 1 65
ADP_I/GPIO3A ADP_I <49,50>
@ C660 22P_0402_50V8J @ R589 10_0402_5% 12 AD Input 66 ADP_ID
<16> CLK_PCI_EC CLK_PCI_EC GPIO3B ADP_ID <48>
13 75 BRDID R694
<15,23,37,38> PLT_RST# PCIRST#/GPIO05 GPIO42
1 2 EC_RST# 37 76 100K_0402_1%
EC_RST# IMON/GPIO43 ENBKL <33>
R590 47K_0402_5% EC_SCI# 20
+3VALW_EC <19> EC_SCI#
1
BATT_LEN# 38 EC_SCII#/GPIO0E BRDID
2 <49> BATT_LEN# GPIO1D 68 ADP_90
ADP_90 <49>
2
C661 DAC_BRIG/GPIO3C 70 R04 +5VALW
EN_DFAN1/GPIO3D SUSACK# <15>
0.1U_0402_16V7K DA Output 71 R695
1 IREF/GPIO3E DPWROK_EC <15>
KSI0 55 72 +3VALW 0_0402_5%
KSI0/GPIO30 CHGVADJ/GPIO3F SUSWARN# <15>
KSI1 56 @
KSI2 57 KSI1/GPIO31 EC_MUTE# 1 R593 2 10K_0402_5%
1
KSO[0..15] KSI3 58 KSI2/GPIO32 83 R594
<44> KSO[0..15] KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# <42>
KSI4 59 84 USB_ON# USB_ON# 1 2
KSI[0..7] KSI4/GPIO34 USB_EN#/GPIO4B USB_ON# <46>
KSI5 60 85 ADP_135
<44> KSI[0..7] KSI5/GPIO35 CAP_INT#/GPIO4C ADP_135 <49>
KSI6 61 PS2 Interface 86 10K_0402_5%
KSI6/GPIO36 EAPD/GPIO4D SYS_PWROK <15,6>
KSI7 62 87 TP_CLK
+3VALW_EC KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <44>
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <44>
R600 KSO1 40
1 2 EC_SMB_CK1 KSO2 41 KSO1/GPIO21
2.2K_0402_5% KSO3 42 KSO2/GPIO22 97 EC_TS_ON#
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 EC_TS_ON# <46>
R604 KSO4 43 98 R406 1 @ 2 0_0402_5%
KSO4/GPIO24 WOL_EN/GPXIOA01 +1.5VS_PWRGD <53>
1 2 EC_SMB_DA1 KSO5 44 99
2.2K_0402_5% KSO6 45 KSO5/GPIO25 Int. K/B HDA_SDO/GPXIOA02 109
ME_FLASH <14>
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 NTC_V <49>
KSO7/GPIO27 SPI Device Interface
KSO8 47
KSO9 48 KSO8/GPIO28 119 EC_SPI_SO
KSO9/GPIO29 SPIDI/GPIO5B EC_SPI_SO <17>
KSO10 49 120 EC_SPI_SI
KSO10/GPIO2A SPIDO/GPIO5C EC_SPI_SI <17>
KSO11 50 SPI Flash ROM 126 EC_SPI_CLK
KSO11/GPIO2B SPICLK/GPIO58 EC_SPI_CLK <17>
KSO12 51 128 EC_SPI_CS#
KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS# <17>
KSO13 52
KSO14 53 KSO13/GPIO2D +5VS
KSO15 54 KSO14/GPIO2E 73
KSO15/GPIO2F ENBKL/GPIO40 IMVP_IMON <56>
KSO16 81 74
<44> KSO16 KSO16/GPIO48 PECI_KB930/GPIO41 VGATE <15,56>
KSO17 82 89
<44> KSO17 KSO17/GPIO49 FSTCHG/GPIO50 LAN_PWR_ON# <38>
90 BATT_CHG_LED#
BATT_CHG_LED#/GPIO52 BATT_CHG_LED# <44>
91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# <44>
EC_SMB_CK1 77 GPIO 92 TP_CLK R603 1 2 4.7K_0402_5%
<49,50> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PWR_LED# <44>
EC_SMB_DA1 78 93 BATT_LOW_LED#
<49,50> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# <44>
EC_SMB_CK2 79 SM Bus 95 SYSON
<17,24,33,40> EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON <52>
EC_SMB_DA2 80 121 TP_DATA R598 1 2 4.7K_0402_5%
<17,24,33,40> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON <56>
127 PM_SLP_S4# <15>
PM_SLP_S4#/GPIO59
+3VS
6 100
<15> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# <15>
14 101 EC_LID_OUT# BATT_TEMP 1 2
<15> PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# <19>
EC_SMI# 15 102 Turbo_V C663 100P_0402_50V8J
<19> EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 Turbo_V <49>
1 2 EC_TACH 16 103 PROCHOT ACIN 1 2
<34> CMOS_ON# GPIO0A H_PROCHOT#_EC/GPXIOA06 PROCHOT <49>
R605 10K_0402_5% 17 104 C664 100P_0402_50V8J
<15,47> SLP_SUS# GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON <51>
18 GPO 105 BKOFF# 1 2
<55> EC_VGA_EN GPIO0C BKOFF#/GPXIOA08 BKOFF# <34>
ODD_DA# 19 GPIO 106 PBTN_OUT# R522 @ 4.7K_0402_5%
<41> ODD_DA# GPIO0D PBTN_OUT#/GPXIOA09 PBTN_OUT# <15>
25 107 PCH_PWR_EN
<48> ADP_ID_CLOSE EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 PCH_PWR_EN <47>
EC_TACH 28 108 1.05VS_EN
<40> EC_TACH FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 1.05VS_EN <54>
29
<38> LAN_WAKE# EC_TX 30 EC_PME#/GPIO15 +3VALW
<37,44> EC_TX EC_TX/GPIO16
EC_RX 31 110 ACIN
<37,44> EC_RX EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN <15,24,48,50>
PCH_PWROK 32 112 EC_ON
<15> PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <51>
NOVO# 34 114 ON/OFF <44>
<44> NOVO# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03
36 GPI 115 LID_SW#
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# <44>
2 1 NUM_LED#: NC 116 SUSP#
SUSP#/GPXIOD05 SUSP# <47,52,53,54>
@ R608 117 NUVOTON_VTT R595 1 @ 2 10K_0402_5% +1.05VS
10K_0402_5% GPXIOD06 118
PECI_KB9012/GPXIOD07
AGND/AGND
122 PECI_KB9012 1 2
<15> SUSCLK XCLKI/GPIO5D H_PECI <19,6>
GND/GND
GND/GND
GND/GND
GND/GND
DGPU_PWR_EN 123 124 +V18R R669 43_0402_1% LID_SW# 2 R601 1 100K_0402_5%

<15,25,53,55> DGPU_PWR_EN XCLKO/GPIO5E V18R
1
GND0
C667
1
4.7U_0603_6.3V6K
1
R740 C93 2
11
24
35
94
113
69
100K_0402_5% 20P_0402_50V8
2
2
KB9012QF A3 LQFP 128P_14X14

ECAGND
@ @
PN : SA00004OB20 S IC KB9012QF A3 LQFP 128P KB CONTROLLER

+3VALW
H_PROCHOT# <48,49,56,6>
ECAGND
2
1
D
R606 PROCHOT 2 1
10K_0402_5% EMC Request G
Q37 S C493
1
3
SYSON 2N7002H_SOT23-3 47P_0402_50V8J
2
C492
0.1U_0402_16V7K
1
@
LAN_WAKE#
2 Security Classification Compal Secret Data Compal Electronics, Inc.
BIOS & EC I/O Port
Custom 0.3
LA-9641P
KSI[0..7]
KSI[0..7] <43>
JKB1 ME@
KSO[0..17] KSI1 1 JKB2 ME@
KSO[0..17] <43> 2 1 26
KSI7
KSI6 3 2 25 GND2
KSO9 4 3 GND1
KSI4 5 4 KSI1 24
KSI5 6 5 KSI7 23 24
KSO0 7 6 KSI6 22 23
KSI2 8 7 KSO9 21 22
KSI3 9 8 KSI4 20 21
KSO5 10 9 KSI5 19 20
KSO1 11 10 KSO0 18 19
KSI0 12 11 KSI2 17 18
KSO2 13 12 KSI3 16 17
KSO4 14 13 KSO5 15 16
KSO7 15 14 KSO1 14 15
KSO8 16 15 KSI0 13 14
KSO6 17 16 KSO2 12 13
KSO3 18 17 KSO4 11 12
KSO12 19 18 KSO7 10 11
+3VLP KSO13 20 19 KSO8 9 10
KSO14 21 20 KSO6 8 9
KSO11 22 21 KSO3 7 8
KSO10 23 22 KSO12 6 7
KSO15 24 23 KSO13 5 6
24 5
2
KSO16 25 KSO14 4
R643 KSO17 26 25 KSO11 3 4
100K_0402_5% 27 26 KSO10 2 3
28 27 KSO15 1 2
29 28 31 1
1
30 29 GND 32 ACES_88514-2401
JP3 30 GND
1 ACES_88514-3001
+3VALW 1
2 2 1
<37,43> EC_TX 2 @
3 R628 0_0402_5%
<37,43> EC_RX 4 3
4
ACES_85205-0400
ME@
+3VALW
2
R642 @
100K_0402_5%
1
D26 @ L67 WCM-2012-900T_4P
NOVO# 2 USB20_N11 1 2 USB20_N11_R
<43> NOVO# 1 2
1 NOVO_BTN#
ON/OFF 3
USB20_P11 4 3 USB20_P11_R
4 ~@ 3 +3VS
DAN202UT106_SC70-3
ME@
CVILU_CF06041H0RB-NH
1
+3VLP USB20_N11 0_0402_5% 2 1 R687 USB20_N11_R 2 1
<18> USB20_N11 2
USB20_P11 0_0402_5% 2 1 R683 USB20_P11_R 3
<18> USB20_P11 4 3
4
2
J11: TOP 5
GND
J12: BOT J12
R701
GND
6
100K_0402_5%
1 2
1
JCR1
SHORT PADS
J11
1 2 ON/OFF
ON/OFF <43>
SHORT PADS LED1
PWR_LED# 1 2 R623 2 1 649_0402_1%

<43> PWR_LED# +5VALW
14@
19-213A-T1D-CP2Q2HY-3T_WHITE +3VALW
14@
C605 ESD reserve
+5VS
EMI reserve JPWRB1 1

1 C605
JTP1 ME@ 2 1 0.1U_0402_16V7K
<43> LID_SW# 2 2
@ C696 LED2 NOVO_BTN# 3
8 ON/OFF 4 3
0.1U_0402_16V7K 7 GND BATT_LOW_LED# 1 2 R764 2 1 470_0402_5% 5 4
GND <43> BATT_LOW_LED# +3VALW 5
6
6
2
6 14@
TP_CLK 5 6 HT-191UD5_AMBER @ 7
<43> TP_CLK 4 5 8 GND
TP_DATA
<43> TP_DATA 4 GND
TP_3 3 14@ D24
TP_2 2 3 ACES_88058-060N
TP_1 1 2 PJSOT24C 3P C/A SOT-23
1
1
ACES_88058-060N ME@
3
15@
@ D15 2 R627 1 TP_3 LED5
PSOT24C_SOT23-3 0_0402_5%
<43> BATT_CHG_LED# BATT_CHG_LED# 1 2 R765 2 1 649_0402_1% +5VALW
1
2 R619 1 14@ TP_1

0_0402_5% 14@
19-213A-T1D-CP2Q2HY-3T_WHITE
14@
15" 14"
L R +5VALW 1
JLED1
1
2
SW4 14@ SW5 14@
1 VCC 1 VCC +3VALW
3 2
+5VS 3
TJG-533-V-T/R_6P TJG-533-V-T/R_6P LID_SW# 4
4
5
6
5
6
5
4 2 4 2
2 CLK 2 CLK LED6 PWR_LED# 6 5
TP_3 TP_2 BATT_LOW_LED# 7 6
3 1 3 1 CAPS_LED# 1 2 R303 2 1 649_0402_1% BATT_CHG_LED# 8 7
3 DAT 3 DAT <43> CAPS_LED# +5VS
CAPS_LED# 9 8
14@ 10 9
19-213A-T1D-CP2Q2HY-3T_WHITE 10
4 GND 4 L 11
12 GND
14@ GND
5 L 5 R HB_A091020-SAHR21
SW6 15@ SW7 15@ ME@
TJG-533-V-T/R_6P TJG-533-V-T/R_6P
GND
5
6
5
6
4 2 4 2
6 R 6
TP_2 TP_1
3 1 3 1

2011/06/15 2012/07/11 Title
Issued Date Deciphered Date ROM/KBD/PWR/CR/LED/TP Conn.
C 0.3
LA-9641P
A B C D E
1 1
2 2
3 3
4 4

USB ext. ports
Document Number Rev
B 0.3
LA-9641P
A B C D E
5 4 3 2 1
+3VS +3VS_TS
ME@
1 TS@ 2
R5583 0_0402_5% 8
Right Ext.USB Conn. 7
6
GND
GND
+3VS_TS 6
D
3 1 R20 5
D +5VALW 4 5 D
+USB_VCCB <18> USB20_N2 3 4
<18> USB20_P2 3
R5581 @ Q156 2
G
2
100K_0402_5% LP2301ALT1G_SOT23-3 EC_TS_ON# R722 1 @ 2 0_0402_5% TS_RST# 1 2
R02 1 2 @ 1
0.1U_0402_16V7K
<43> EC_TS_ON#
U36 RUSB@ RIGHT USB PORT X1
C1322
1 2 JTS1
1 8
2 GND VOUT 7 C1331
3 VIN VOUT 6 0.1U_0402_16V7K TS@
4 VIN VOUT 5 2 1
<43> USB_ON# EN FLG USB_OC4# <18> @
G547I2P81U_MSOP8
Touch Screen
JUSB3 ME@
8
+USB_VCCB 7 GND
W=80mils GND
6
RUSB@ +USB_VCCB 5 6
4 5
1 4
C714 USB20_N9 R868 2 ~@ 1 0_0402_5% USB20_N9_C 3
+ <18> USB20_N9 3
USB20_P9 R869 2 ~@ 1 0_0402_5% USB20_P9_C 2
<18> USB20_P9 2
220U_6.3V_M 1
1
2
6.3Φ * 5.9 2 ACES_88058-060N
SF000001500
L66 RUSB@
USB20_N9 4 3 USB20_N9_C
4 3
USB20_P9 1 2 USB20_P9_C
C 1 2 D25 @ C
1
WCM-2012HS-900T PJDLC05_SOT23-3
@ D27
U3RXDN1 9 10 1 1 U3RXDN1 Intel_PCH_USB2.0
U3RXDP1 8 9 2 2 U3RXDP1 WCM-2012-900T_4P
1 2 U2DN2
B <18> USB20_N1 1 2 WCM-2012-900T_4P B
U3TXDN1 7 7 4 4 U3TXDN1
1 2 U2DN1
<18> USB20_N0 1 2
U3TXDP1 6 6 5 5 U3TXDP1 4 3 U2DP2
<18> USB20_P1 4 3
2A/Active Low L55
3 3 4 3 U2DP1
+5VALW +USB3_VCCA <18> USB20_P0 4 3
8 L51
U35 R02 W=80mils
1 8
2 GND VOUT 7 YSCLAMP0524P_SLP2510P8-10-9
3 VIN VOUT 6
USB_ON# 4 VIN VOUT 5 @ D30
EN FLG USB_OC0# <18> WCM-2012HS-900T +USB3_VCCA
Intel_PCH_USB3.0
U3RXDN2 9 10 1 1 U3RXDN2
G547I2P81U_MSOP8 1 2 U3RXDN2 WCM-2012HS-900T +USB3_VCCA
<18> USB3_RX2_N 1 2
U3RXDP2 8 9 2 2 U3RXDP2 W=80mils 1 2 U3RXDN1
U3TXDN2 7 4 U3TXDN2 4 3 U3RXDP2 JUSB1

LP2 <18> USB3_RX1_N 1 2
W=80mils
LP1
7 4 <18> USB3_RX2_P 4 USB30@ 3 U3TXDP2 9 4 3 U3RXDP1 JUSB2
L54 SSTX+ <18> USB3_RX1_P 4 3
U3TXDP2 6 6 5 5 U3TXDP2 1 USB30@ U3TXDP1 9
U3TXDN2 8 VBUS L50 SSTX+
1
3 U2DP2 3 SSTX- U3TXDN1 VBUS
8
3
7 D+ U2DP1 SSTX-
3
+USB3_VCCA 8 U2DN2 2 GND 10 D+
7
U3RXDP2 6 D- GND 11 U2DN1 GND
2 10
C850 USB30@ 4 SSRX+ GND 12 U3RXDP1 D-
6 GND 11
YSCLAMP0524P_SLP2510P8-10-9 0.1U_0402_16V7K WCM-2012HS-900T U3RXDN2 5 GND GND 13 C849 USB30@ SSRX+
4 GND 12
1 2 U3TXDN2_L 1 2 U3TXDN2 SSRX- GND 0.1U_0402_16V7K WCM-2012HS-900T U3RXDN1 GND
5 GND 13
<18> USB3_TX2_N 1 2 SSRX- GND
TAITW_PUBAU1-09FNLSCNN4H0 1 2 U3TXDN1_L 1 2 U3TXDN1
<18> USB3_TX1_N 1 2
ME@ TAITW_PUBAU1-09FNLSCNN4H0
1 2 U3TXDP2_L 4 3 U3TXDP2 ME@
D22 D31 <18> USB3_TX2_P 4
1 @ @ USB30@ 3 1 2 U3TXDP1_L 4 3 U3TXDP1
L53 <18> USB3_TX1_P 4 3
C736 U2DN1 3 6 U2DP2 3 6 C848 USB30@ USB30@
A + I/O2 I/O4 I/O2 I/O4 0.1U_0402_16V7K C847 USB30@ L49 A
220U_6.3V_M 0.1U_0402_16V7K
SF000001500 2 2 5 2 5
GND VDD +5VALW GND VDD +5VALW
1 4 U2DP1 1 4 U2DN2
I/O1 I/O3 I/O1 I/O3 Security Classification Compal Secret Data Compal Electronics, Inc.
AZC099-04S.R7G_SOT23-6 AZC099-04S.R7G_SOT23-6 Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
USB3.0/Left USB Ports
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
5 4 3 2 1
A B C D E
+5VALW TO +5VS +3VALW TO +3VS

+3VALW +3VS
+5VALW +5VS
U38 U39
AP4800BGM_SOP8L-8 +3VALW TO +3VALW(PCH AUX Power)
AP4800BGM_SOP8L-8 8 1
8 1 1 7 2 1 1
1
1 7 2 1 1 C723 6 3 C724 +3VALW +3V_PCH
1
C720 6 3 C721 4.7U_0603_6.3V6K @ 5 @ 4.7U_0603_6.3V6K C725
4.7U_0603_6.3V6K @ 5 @ 4.7U_0603_6.3V6K C722 @ 1U_0603_10V6K R645
R644 2 2 2 PJ1
@
1 @ 1U_0603_10V6K 470_0603_5% 1
4
2 2 2 470_0603_5% 2 1
1 2
@ 2 1
1 2
+VSB +VSB D
D 2 SUSP JUMP_43X79
1
2 SUSP G 3 1 4.7U_0603_6.3V6K 1U_0603_10V6K
1
G S Q108 1 1
1
R646 S Q107 R647 2N7002_SOT23 C782 @ @ @ 1
3
150K_0402_5% 2N7002_SOT23 470K_0402_1% 4.7U_0603_6.3V6K Q121 C780 @
@ LP2301ALT1G_SOT23-3 R777
2
2 2 C783 @ 470_0603_5%
2
2
5VS_GATE 2 R649 15VS_GATE_R 2
1
2
1
D R650 +5VALW
1
1
D SUSP 2 Q111 C727

82K_0402_5% 0_0402_5%
1
SUSP 2 Q110 C726 G 2N7002_SOT23 0.01U_0402_25V6 D
G 2N7002_SOT23 0.01U_0402_25V6 S @ 2 2
R778
1
S 2 G
3
1 2 S @
3
Q118
2N7002K_SOT23-3
47K_0402_5%
@ 1 @
1
D @ SLP_SUS
DS3_EN 2 Q120 C781
2N7002K_SOT23-3 0.1U_0402_16V7K
G
2
S
3
+RTCVCC
+3VLP
1
+5VALW
@ R652
2 R653 2
220K_0402_5%
1
220K_0402_5%
2
R780 @ SUSP
<6> SUSP
100K_0402_5%
Q117
2
1
SLP_SUS
OUT
Q124
1
2
<43,52,53,54> SUSP# IN
GND
OUT
@ 1 2 DS3_EN 2
<15,43> SLP_SUS#
3
R34 0_0402_5% IN @
GND
1
<43> PCH_PWR_EN @ 1 2 DTC124EKAT146_SC59-3

3
R38 0_0402_5% R781 @

100K_0402_5%
先先先,C phase再再再
2
+1.5VS +1.05VS
1
3 3
R655 R659
470_0603_5% 470_0603_5%
@ @
1 2
1 2
D D
2 SUSP 2 SUSP
G G
S Q113 S Q116
3
2N7002_SOT23 2N7002_SOT23
@ @
4 4

DC Interface
Custom 0.3
LA-9641P
A B C D E
5 4 3 2 1
PL101
FBMA-L11-453215800LMA90T_2P
VIN
1 2
PF101 PL102 135W@

12A_65V_451012MRL FBMA-L11-453215800LMA90T_2P
1 2 APDIN1 1 2
D JDCIN1 D
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
1 APDIN
1 2
2 3
3
1
PC101
PC102
PC103
PC104
4
4 5 ADP_ID
5
2
ACES_50312-00541-001
@
PQ102A
PR103
2N7002KDW-2N_SOT363-6
1 2 6 1
+3VALW ADP_ID
680P_0402_50V7K
0.1U_0402_16V7K
750_0402_1%
PR110
2
1
PC108
PC109
1 2
VIN
2
2
C 100K_0402_1% C
100K_0402_1%
2N7002KDW-2N_SOT363-6
1
3
PR111
PQ102B
5
2
ADP_ID_CLOSE
4
+5VS
+3VALW
47K_0402_1%
H_PROCHOT#
PR106
10K_0402_1%
2N7002KDW-2N_SOT363-6
PU101A
PR108
AS393MTR-E1 SO 8P OP
8
PC105 3 BATT_TEMP
P
+
PQ101A
2 2 1 1
1N4148WS-7-F_SOD323-2
1
O 2
-
G
1.5M_0402_5%
0.022U_0402_16V7K
100K_0402_1%
100P_0402_50V8J
+CHGRTC
1
PR104
PD105
PR109
B B
PC107
PR101
2
1K_0603_1%
1
1 2
PD101 +3VLP +5VS
S SCH DIO BAS40CW SOT-323
2 +CHGRTC_R
+RTCBATT 1
3 PR102
1K_0603_1% JRTC1 @ H_PROCHOT#
47K_0402_1%
1 2 1
2 1
3 2
PR107
4 GND 2N7002KDW-2N_SOT363-6
GND 3
8
ACES_50271-0020N-001 PC106 5
P
+
PQ101B
5 2 1 7
O 6 ACIN
1N4148WS-7-F_SOD323-2
-
G
0.022U_0402_16V7K
4
1.5M_0402_5%
PU101B
RTC Battery
4
PD104
PR105
2
A A

PWR DCIN / RTC Battery
5 4 3 2 1
5 4 3 2 1
PH201 under CPU botten side :

JBATT1 -15" JBATT2 -14"
CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C +3VS
@ VMB2 VMB
+EC_VCCA
JBATT1 PF201 PL201
SUYIN_200082GR007M229ZR
1 12A_65V_451012MRL SUPPRE_ KC FBCA-K5B-302540-L1-T 1812

1
2
<43,50> ADP_I
100K_0402_1%
12.7K_0402_1%
2 1 2 1 2
2 BATT+
1
PR215 @
3 EC_SMCA
3
PR226
8.45K_0402_1%
0.01U_0402_25V7K
4 EC_SMDA
4 5 <43,48,56,6> H_PROCHOT#
5
PR227
6
1
6
PC203
D 7 D
2
7
1
D <43> NTC_V
PQ201 @
8 PC201
1
GND
100K_0402_1%_TSM0B104F4251RZ
100_0402_1%
100_0402_1%
9 1000P_0402_50V7K 2 ADP_OCP_1
2
GND <43> Turbo_V G
S 2N7002KW_SOT323-3
3
PR201
PR204
@
2
1
JBATT2 PR216 @
2
@
1 0_0402_5%
SUYIN_200082GR007M229ZR
1 2 PR233 <43,49> PROCHOT 1 2

2
2
25.5K_0402_1%
9.31K_0402_1%
5.9K_0402_1%
PH201
3 100K_0402_1%
3
2
4
2
4
PR230
2N7002KW_SOT323-3
PR229
PR232
5
1
5 6 PR225
6 7 100K_0402_1%
1
7 8
EC_SMB_CK1 <43,50> <43,49> PROCHOT
1
GND 9
GND
1
D
PQ206
2N7002KW_SOT323-3
2 PR228
EC_SMB_DA1 <43,50> <43> ADP_65 G PJ202 0_0402_5%
PR206 @ S @ JUMP_43X39
2N7002KW_SOT323-3
1 2 1 2
+3VALW B+ +VSB
2
1 2
1
D
PQ208
6.49K_0402_1% 2
<43> ADP_90 G
PQ207
S
3
1 2 ECAGND
BATT_TEMP <43,48,49> A/D
1
PR207 D
10K_0402_5% 2
<43> ADP_135 G
S
3
PR209
1 2
C +3VLP C
6.49K_0402_1%
+3VALW +3VALW ECAGND
100K_0402_1%
2
PR214
100K_0402_1%
2
1
VL
PR211
BATT_OUT <50>
1
VL
0.01U_0402_25V7K
6
1
47K_0402_1%
PC202
PQ202A
PR210
2 2N7002KDW-2N_SOT363-6
PR202
2
2
75K_0402_1%
1
1
3
8
PC208
1
3 0.068U_0402_16V7K PQ202B
P
<43,48,49> BATT_TEMP + 1 2 1 5 2N7002KDW-2N_SOT363-6

2 O
-
G
PU201A
1N4148WS-7-F_SOD323-2
4
100P_0402_25V8K
1
100K_0402_1%
+3VLP
1.5M_0402_5%
B AS393MTR-E1 SO 8P OP B
2
2
PD201
1
PR213
PC207
PR205
+5VALWP
100K_0402_1%
2
D 2 @
1
PU202
PR220
2 PQ209 @
G 2N7002KW_SOT323-3 1 5
IN OUT +3V_LDO
S
3
1
22U_0603_6.3V6M
2
1
GND PC213 @
1 D
PC211 @
3 4 4.7U_0402_4V6M
2
SHDN# BYP
1
2 PQ205
<43> BATT_LEN#
G 2N7002KW_SOT323-3 G9191-330T1U_SOT23-5
S
+5VALWP
3
2
VMB VL
1
PC212 @
1U_0402_6.3V6K
2
2
75K_0402_1%
47K_0402_1%
PR212 @
2
PR203 @
PC210 @
1
5 0.068U_0402_16V7K
P
+3V_LDO
1
+ 7 2 1
6 O
-
G
100P_0402_25V8K
PU201B
1N4148WS-7-F_SOD323-2
100K_0402_1%
1.5M_0402_5%
4
2
2
PR217 @
PC209 @
PD203 @
PR208 @
1
A A
2
1

PWR-BATTERY CONN/OTP
5 4 3 2 1
5 4 3 2 1
P3
B+
P2
PQ301 PQ302 65W @
AO4407AL_SO8 AO4407AL_SO8
8 1 1 8 PR301
VIN 7 2 2 7 0.01_1206_1% CHG_B+
6 3 3 6
5 5 1 4 1 2 PQ312
PL301 AO4407AL_SO8
2 3 1UH_PCMB061H-1R0MS_7A_20% 1 8
10U_0805_25V6K
4
4
2 7
3 6
10U_0805_25V6K
@ 10U_0805_25V6K
10U_0805_25V6K
2
PQ304 1 2 5
10U_0805_25V6K
10U_0805_25V6K
D D
PC318
47K_0402_5%
1
2
PC301
200K_0402_1%
0.1U_0603_25V7K
4
1
PR302
PC310
PC313
PC315
PC316
PC319
DTA144EUA_SC70-3 5600P_0402_25V7K DISCHG_G
PC302
PR304
1
PQ302 PQ302 PR322
200K_0402_1%
2
2
2 1 2
2
90W @ 135W @ ACN VIN
2ACOFF-1
1SS355_SOD323-2
2
1
AO4407AL_SO8 AO4423L_SO8 ACP PR321
1DISCHG_G-1
47K_0402_1%
1
2
PD302
P2-1 PR325
1
2 200K_0402_1%
PQ303 PQ311
1
PC307 PC311 DTC115EUA_SC70-3
1
DTC115EUA_SC70-3
PR306 1 2 2 1
3
20K_0402_1%
1 2 0.1U_0402_25V6 0.1U_0402_25V6 2 1 2
6
PQ306
1
D 2N7002KW _SOT323-3 PC308 PD303 PQ313

150K_0402_1%
PR305
PQ307A 2 1SS355_SOD323-2
2 2N7002KDW -2N_SOT363-6 G BATT_OUT <49,50> 0.1U_0402_25V6 P2 2N7002KW _SOT323-3
0.1U_0402_25V6
3
1
D
S
3
1
2 1
PC324
2 PACIN
1
VIN G
S
3
ACPRN
392K_0402_1%
1
P2-2
10_1206_5%
MDS1525URH 1N SO8
2
5
6
7
8
C C
PR309
2N7002KDW-2N_SOT363-6
PQ309
PR319
3
PQ307B
ACOK
CMPIN
CMPOUT
ACP
ACN
PR303 <43,49> ADP_I
2
47K_0402_1% PR308 21
1
PACIN 1 2 5 1 2 6 TP DH_CHG 4
ACDET PC314
64.9K_0402_1% PC304 20 BQ24737VCC 1 2
4
PC303 1 2 7 VCC
1 2 IOUT PL302 PR324
3
2
1
1U_0603_25V6K
1
PQ305 100P_0402_50V8J 19 10UH_PCMB104T-100MS_6A_20% 0.01_1206_1%

PHASE
DTC115EUA_SC70-3 0.1U_0402_25V6
<43,49> EC_SMB_DA1
8
SDA
PU301
1 2
BATT+
PR311 BQ24737RGRR_VQFN20_3P5X3P5 PR326 LX_CHG CHG1 4
10K_0402_1% 18 DH_CHG-1 1 2
HIDRV
5
6
7
8
1 2 ACOFF-12 9 2 3
<43> ACOFF SCL
1
<43,49> EC_SMB_CK1
PQ310
PR315 0_0603_5% PR320 PC317
4.7_1206_5%
MDS1521URH 1N SO8
PR323
200K_0402_1% 2.2_0603_5% 0.047U_0603_16V7K
PQ314 1 2 10 17 BST_CHG 1 2 2 1 SRP SRN
10U_0805_25V6K
10U_0805_25V6K
2N7002KW_SOT323-3
124737_SN
ILIM BTST
1
+3VALW PD301
3
1
D PR316 4
LODRV
1
<49,50> BATT_OUT 2 16 2 1
PC322
PC323
100K_0402_1%
GND
SRN
SRP
REGN
BM
G
S
3
2
RB751V-40_SOD323-2
680P_0603_50V7K
11
12
13
14
15
3
2
1
1
BQ24737VDD
PC320
2
PC312
6.8_0402_5%
1
10_0402_5%
1U_0603_25V6K
2
PR317
PR318
PC306 DL_CHG
2
2
B 0.1U_0402_25V6 B
2 1
1
PC305 1 PC309
0.1U_0402_25V6 0.1U_0402_25V6
2
BQ24737VDD
PR314
10K_0402_1%
1
1 2
47K_0402_1%
ACIN <15,24,43,48>
PR307
PR310
10K_0402_1%
PACIN
2
PQ308
2N7002KW_SOT323-3
1
D PR312
ACPRN 2
G 12K_0402_1%
2
S
3
A A

CHARGER-BQ24737
0.2
LA-9641P
5 4 3 2 1
A B C D E
PR410
3VALW_EN 2 1 3V5V_EN
4.7U_0402_6.3V6M
PC432 @
0_0402_5%
1
PR415
2
2 1 ENLDO_3V5V
1 0_0402_5% 1
PR402
499K_0402_1%
PR411 @ ENLDO_3V5V 2 1
2 1 ENLDO_3V5V B+
1
150K_0402_1%
1U_0603_25V6K
1
PR403
0_0402_5%
PC407
2
B+
2
PL401 PC435 PR414
HCB2012KF-121T50_0805 PU401 1 2 1 2
1 2 3V_VIN 7 1 3VALW_EN
IN EN1 0.01U_0402_50V7K1K_0402_1%
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
0.1U_0402_25V6
8 3
IN EN2
PC433 @
PC403 @
PR421 PC402
6 1
BST_3V 2 BST_3V_1 1 2
BS
1
1
PC404
PC405
PC406
0_0603_5% 0.1U_0603_25V7K
PL402
2
10 LX_3V 1 2
LX +3VALWP
9 4 1.5UH_PCMC063T-1R5MN_9A_20%
GND OUT
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
PC410 @
4.7_1206_5%
2 5
PG LDO +3VLP
PC408
PC409
PC411
PC412
PC413
1
PR404
SY8208BQNC_QFN10_3X3
2
PC414
13V_SN
4.7U_0603_6.3V6M
680P_0603_50V7K
PC415
2 2
2
PR412 @
ENLDO_3V5V_1 1 2 ENLDO_3V5V
0_0402_5%
B+ PL403
HCB2012KF-121T50_0805
1 2 5V_VIN
PC419 PR413
ENLDO_3V5V_1 1 2 1 2
1K_0402_1%
6800P_0402_25V7K
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
0.1U_0402_25V6
PU402
8 1 3V5V_EN
IN EN1
PC434 @
PC418 @
1
1
PC420
PC416
PC417
3 ENLDO_3V5V_1 PC421
EN2 PR422 0.1U_0603_25V7K
6 BST_5V 1 2 BST_5V_1 1 2
2
BS
0_0603_5%
PL404 @PJ401
@ PJ401
9 10 LX_5V 1 2 +5VALWP +3VALWP 1 2 +3VALW
GND LX 1 2
5V_VCC 5 4 1.5UH_PCMB063T-1R5MS_9A_20% JUMP_43X118
VCC OUT
1
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
680P_0603_50V7K 4.7_1206_5%
PC428 @
2 7
PG LDO VL
1
PC422
PR406
PC423
PC424
PC425
PC426
PC427
4.7U_0603_6.3V6M
SY8208CQNC_QFN10_3X3
2
1 5V_SN
@PJ402
@ PJ402
2
2
1
PC430
4.7U_0603_6.3V6M
+5VALWP 1 2 +5VALW
3 1 2 3
JUMP_43X118
2
PC429
2
PR407
2.2K_0402_5%
2 1
<43> EC_ON
2 PR408 1
<43> MAINPWON
0_0402_5%
3V5V_EN
1M_0402_1%
4.7U_0402_6.3V6M
1
1
PR409
PC431
2
2
4 4

PWR- 3VALWP/5VALWP
A B C D E
A B C D
PL502
1.35V_B+ 1 2 B+
HCB2012KF-121T50_0805
STATE S3 S5 1.5VP VTT_REFP 0.75VSP
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
4.7U_0805_25V6-K
PC520 @
PC509 @
1
1
PC501
PC513
S0 Hi Hi On On On
5
Off
2
S3 Lo Hi On On (Hi-Z) PQ501
MDU1516URH_POW ERDFN56-8-5
+1.35VP UG_1.35V 4
S4/S5 Lo Lo Off Off Off
2
1 1
JUMP_43X39
LX_1.35V
3
2
1
PJ503 @
Note: S3 - sleep ; S5 - power off
2
1
PR501 PC512 PL501
2.2_0603_5% 0.1U_0603_25V7K 1UH_PCMB104T-1R0MH_18A_20%
1
BST_1.35V 1 2 BST_1.35V-1 1 2 2 1
+0.675VSP +1.35VP
10U_0805_25V6K
10U_0805_25V6K
4.7_1206_5%
MDU1511RH_POWERDFN56-8-5
1
PR515 @
PC504
20
19
18
17
16
1
PC505
PU501
VTT
VLDOIN
BOOT
UGATE
PHASE
2
11.35V_SN
21 1
2
PAD
330U_2.5V_M
+
PQ502
1 15 4
PC522
LG_1.35V
VTTGND LGATE
PC517 @
680P_0603_50V7K
2 14 2
VTTSNS PGND PR511
3
2
1
2
6.65K_0402_1%
3 13 2 1
GND RT8207MZQW _W QFN20_3X3 CS
4 12
+1.35VP
+VTT_REFP VTTREF VDDP
OCP min 20A
5 11 2 1 OVP min 1.485V
+1.35VP VDDQ VDD
+5VALW
PGOOD
PR514
1
5.1_0603_5%
1U_0603_10V6K
TON
PC506
1U_0603_10V6K
FB
S3
S5
2 0.033U_0402_16V7K 2
2
1
PC510
PC511
6
S3_1.35V 7
10
2
S5_1.35V
PR502
49.9K_0402_5%
<43,47,53,54> SUSP# 1 2
PR505 PR509
0_0402_5% 887K_0402_1%
<43> SYSON 1 2 2 1 1.35V_B+
PR507 PJ505
1
PC503 PC508 @ 8.2K_0402_1% 2 1

0.1U_0402_16V6K 0.1U_0402_16V7K 2 1 2 1
@ JUMP_43X118
2
PJ504
+1.35VP 2 1 +1.35V
PR506 2 1
10K_0402_1% @ JUMP_43X118
2
PJ506
2 1
+0.675VSP 2 1 +0.675VS
JUMP_43X79
@
3 3
4 4

+1.35V_DDR
Custom 0.2
LA-9641P
A B C D
5 4 3 2 1
PR601
40.2K_0402_1%
2 1
SUSP# <43,47,52,54>
1
1M_0402_1%
PC637
PR613
.1U_0402_16V7K
2
1
@ PR603 @ PC601
4.7_1206_5% 680P_0603_50V7K
PL603 1 2SNB_1.5V 1 2
D D
HCB2012KF-121T50_0805 PU601
B+ 1 2 B+_1.5V 8
IN EN
1 PC602
0.1U_0603_25V7K
10U_0805_25V6K
6 1
BST_1.5V 2 PL601
0.1U_0402_25V6
2200P_0402_50V7K
BS
1
1.5UH_PCMB063T-1R5MS_9A_20%
PC604
+3VS
+1.5VSP
PC603 @
9 10 LX_1.5V 1 2
PC617
GND LX
30.1K_0402_1%
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1
1
PR604 @
0_0402_5%
330P_0402_50V7K
1
PC612 @
4
PR607
FB
PC607
PC608
PC609
PC610
PC611
ILMT_1.5V 3 7
+3VALW
2
ILMT BYP
2
2
4.7U_0603_6.3V6K
ILMT_1.5V 2 5
4.7U_0603_6.3V6K
PG LDO
PC606
1
1
SY8208DQNC_QFN10_3X3 +1.5VSP PJ602
PC605
<43> +1.5VS_PWRGD
PR605 @
2 1
0_0402_5%
+1.5VS
2
2 1
1
2
PR608 @ JUMP_43X118
10K_0402_1%
1
2
20K_0402_1%
PR602
2
+1.8VGSP PJ603
2
2 1 +1.8VGS
2 1
@ JUMP_43X118
+3VALW
+0.95VGSP PJ606
2 1 +0.95VGS
2 1
@ JUMP_43X118
C C
@ PU603 PL604
PJ605 1UH_PHT32251B-1R0MS_2.34A_20%
+3VALW 1 2 +1.8V_VIN 4
IN LX
3 +1.8V_LX 1 2 +1.8VGSP
5 2
PAD-OPEN 3x3m PG GND
4.7_1206_5%
22U_0805_6.3V6M
22U_0805_6.3V6M
1
PR614 @
6 1
FB EN
1
PC626
PC618
PC620
22U_0805_6.3V6M
SY8032ABC_SOT23-6
2
2
+1.8V_FB
+1.8V_SNUB
+1.8V_EN
PC625
22P_0402_50V8J PR626
2 1 60.4K_0402_1%
1 2
1000P_0603_50V7K
PC613 @
<15,25,43,53,55> DGPU_PWR_EN
1
0.1U_0402_25V6
2
PR625
47K_0402_1%
1
20K_0402_1%
PR623
PC619
2
1 2 PD601 @
RB751V-40_SOD323-2
2
2 1
1
2
PR624
10K_0402_1%
1
B B
PR612
0.95V_EN 2 1
DGPU_PWR_EN <15,25,43,53,55>
82.5K_0402_1%
2
1M_0402_1%
2
PR616
PC638
.1U_0402_16V7K
1
1
@ PR610 @ PC634
4.7_1206_5% 680P_0603_50V7K
PL606 1 2SNB_0.95V 1 2
HCB2012KF-121T50_0805 PU604
B+ 1 2 B+_0.95V 8
IN EN
1 PC632
0.1U_0603_25V7K
10U_0805_25V6K
6BST_0.95V
1 2 PL605
0.1U_0402_25V6
2200P_0402_50V7K
BS
1
1.5UH_PCMB063T-1R5MS_9A_20%
PC627
+3VS
+0.95VGSP
PC636 @
9 10 LX_0.95V 1 2
PC621
GND LX
2
2
0_0402_5% @
59K_0402_1%
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1
220P_0402_50V7K
1
1
4
PR618
PR611
FB
PC635
PC629
PC633
PC631
PC622
ILMT_0.95V3 7
+3VALW
2
2
ILMT BYP
2
2
4.7U_0603_6.3V6K
ILMT_0.95V 2 5
4.7U_0603_6.3V6K
PG LDO
1
PC628
1
1
0_0402_5% @
SY8208DQNC_QFN10_3X3
PC630
PR609
1
2
PR615
2
100K_0402_1%
2
A A

1.5V_VRAM/1.8V/0.95V
C 0.2
LA-9641P
5 4 3 2 1
5 4 3 2 1
D D
PR702
0_0402_5%
1 2
<43> 1.05VS_EN
PR701 @
20K_0402_1%
1 2 1.05V_EN
<43,47,52,53> SUSP# +1.05VSP PJ701 +1.05VS
2
PR706 @
2 1
1M_0402_1%
.1U_0402_16V7K
2 1
PC701 @
@ JUMP_43X118
2
1 PL702
C HCB2012KF-121T50_0805 C
100K_0402_1%
1.05VSP_B+ 1 2
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
4.7U_0805_25V6-K
B+
PC713 @
PC715 @
PR712
1
PC712
MDS1525URH 1N SO8
5
6
7
8
PR713 PC707
PC711
PQ701
2.2_0603_5% 0.1U_0603_25V7K
2
BST_1.05VSP1 2 BST_1.05VSP_1
1 2
1
17
16
15
14
13
10.7K_0402_1%
2
PU701 4
PR704
PAD
PGOOD
EN
MODE
BST
1 12 LX_1.05VSP
0.1U_0402_25V6
3
2
1
VREF SW PL701
+1.05VSP
1
1 2
PC702
2 11 DH_1.05VSP 3.3UH_PCMB063T-3R3MS_6.5A_20%
12K_0402_1%
2
REFIN DH
2
1000P_0603_50V7K 4.7_1206_5%
MDS1521URH 1N SO8
5
6
7
8
PC703
PR705
PQ702
0.01UF_0402_25V7K TPS51219RTER_QFN16_3X3
PR714
1
3 10 DL_1.05VSP 1
GSNS DL
220U_6.3V_M
1
2
@ +
PC714
4
4 9
VSNS V5 +5VALW 2
+1.05VP
COMP
1
PGND
TRIP
GND
B B
OCP min 8A
3
2
1
1
PC709
2
PC706 PC708 OVP min 1.24V
5
8
2
1U_0603_10V6K
1000P_0402_50V7K
2
2
PR707 1 2 @
PC704
45.3K_0402_1%
1
10_0402_5%
0.01UF_0402_25V7K
1
PR711
PR709
1 2
10_0402_1%
2
PC705
1000P_0402_50V7K
1
A A

+1.05VS
Custom 0.2
LA-9641P
5 4 3 2 1
A B C D
+3VGS
0_0402_5%
10K_0402_1%
10K_0402_1%
PR803 @ 10K_0402_1%
10K_0402_1%
PR805 @ 10K_0402_1%
PR806 @ 10K_0402_1%
PR807 @ 10K_0402_1%
PR808 @ 10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
2
2
+VGA_B+ PL801
VGA Boot Up Voltage Setting
HCB4532KF-800T90_1812
Sun Pro:0.9V(0110000) 1 2
PR801
PR802
Mars@ PR804
PR809
Sun@ PR810
PR811
PR812
B+
1
Mars XT:0.85V(0110100)
PC803 Mars@
PC804 Mars@
PR813 @
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
147K_0402_1%
PC801 @
1 2VRON_VGA
1
<15,25,43,53> DGPU_PWR_EN
PC802 @
1 1
2
PR820
1 2
2
<43> EC_VGA_EN
0_0402_5%
0_0402_5%
PR814
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
<24>
<24>
<24>
<24>
<24>
1
PR816 @
2.2K_0402_1% PC805 @ PR817 Mars@ PC806 Mars@ PQ801 Mars@
1
1 2 1 2 2.2_0603_5% 0.22U_0603_10V7K CSD87351Q5D_SON8-7
+3VGS
BOOT2_VGA 2 1 BOOT2_2_VGA 1 2 2 PL802 Mars@
PR818 @ .1U_0402_16V7K
<24,55> GPU_GPIO0 1 2 UGATE2_VGA 0.22UH_PCME064T-R22MS_28A_20% +VGA_CORE
7
0_0402_5% PHASE2_VGA 3 6 SW2_VGA 1 4
PR819 5
GPU_VID0
1 2 DPRSLPVR_VGA-1 4 LF2_VGA 2 3 V2N_VGA
PC810 Mars@
1 1 1 1
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
1
1
PR827 Mars@
PR829 Mars@
2.2K_0402_1%
1_0402_1%
4.7_1206_5%
3.65K_0402_1%
+ + + +
PR828 Mars@
+3VGS PR830 @
PC807
PC808
PC809
10K_0402_1%
GPU_VID6
1.91K_0402_1%
PR826
8
1 2 CLK_ENABLE#_VGA
LGATE2_VGA 2 2 2 2
1.91K_0402_1%
2
1
SNUB2_VGA
PR831
VSUM-_VGA
PR832
0_0402_5%
2
1 2
VSUM+_VGA
PR833
ISEN2_VGA
2.2K_0402_1%
+3VGS 1 2
680P_0402_50V7K
> DGPU_PWROK
1
1 PR834 @2
PC811
<24,55> GPU_GPIO0 0_0402_5%
PR835 @
2
1 2
PSI#_VGA
2 2
2.2K_0402_1%
2 PR836 1
RBIAS_VGA
147K_0402_1% PC812
1U_0603_10V6K +VGA_CORE
40
39
38
37
36
35
34
33
32
31
PU801 1 2
PR843
CLK_EN#
VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON
30
Sun@ BOOT2 29
1 UGATE2 28
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2 PGOOD PHASE2 27
PSI# VSSP2
1
1K_0402_1% 3 26
PC824
PC825
PC826
PC827
PC828
PC829
PC830
PC831
PC832
PC833
PC834
PC835
PC836
PC837
PC838
PC839
4 RBIAS LGATE2 25
5 VR_TT# VCCP 24 +5VS
2
VW_VGA 6 NTC PWM3 23
COMP_VGA 7 VW LGATE1 22
FB_VGA 8 COMP VSSP1 21
1 2ISEN3_VGA 9 FB PHASE1
ISEN3
1
UGATE1
10 PC872
BOOT1
ISUM+
ISEN2
ISEN1
ISUM-
VSEN
IMON
PC871 1U_0603_10V6K
5.9K_0402_1%
VDD
1000P_0402_50V7K
RTN
VIN
22P_0402_50V8J 41
249K_0402_1%
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
2
AGND
2
1
PR840 @
PC873
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
ISL62883CHRTZ-T_TQFN40_5X5
PR841
11
12
13
14
15
16
17
18
19
20
1
PR842 PR864 Sun@
PC840
PC841
PC842
PC843
PC844
PC845
PC846
PC851
PC852
PC853
PC854
PC855
PC856
PC857
2
499_0402_1% PC874 0_0402_5%

1 2FB1_VGA1 2 1 2
ISUM-_VGA
1
2
VDD_VGA
RTN_VGA
390P_0402_50V7K
PC847 PR843 Mars@ PR844 @ 0_0402_5%
33P_0402_50V8J 1.4K_0402_1% 1 2
+5VS
1 2 1 2 VSEN_VGA PR847
PR863 Sun@ PR845 0_0402_5%
0.047U_0402_16V7-K
2
VIN_VGA 1 2 GPU_IMON <43>

PR847 Mars@
0_0402_5%
11K_0402_1%
1
PR846 Mars@ 1 2 Sun@

PC849
+5VS +VGA_B+
1 2FB2_VGA1 2 PR848
ISEN2_VGA 1_0402_5%
2
3
PC848 221K_0402_1% 1 2 7.5K_0402_1% +VGA_B+ 3
1
1
150P_0402_50V8J ISEN1_VGA +5VS

1
1
PC876
PC877
1U_0603_10V6K
0.22U_0603_25V7K
VSSSENSE_VGA <27,55>
PC850 Mars@
PC875 Mars@
PR846 PR849 Sun@

0.22U_0402_10V6K
0.22U_0402_10V6K
30K_0402_1%
2200P_0402_50V7K
2
2
1
BOOT1_VGA
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2
Sun@
PC878 @
2
1
158K_0402_1%
PC879
PC880
PC881
2
2
PR849 VSUM+_VGA UGATE1_VGA
VSUM-_VGA
1 2 PQ802
82.5_0402_5%
+VGA_CORE
PR851 @
Mars@ PR852 PC858 CSD87351Q5D_SON8-7

1
1
PR850 2.2_0603_5% 0.22U_0603_10V7K
1
10_0402_1% 2 1 BOOT1_1_VGA 1 2 2 PL803

2.61K_0402_1%
40.2K_0402_1%
PR853
PR854 0.22UH_PCME064T-R22MS_28A_20%
1 2 7
<27> VCCSENSE_VGA
2
PHASE1_VGA 3 6 SW1_VGA 1 4
+VGA_CORE
2
5
PC860 Sun@
PC861 Sun@
0_0402_5%
.1U_0603_25V7K
VSUM_VGA_N001
0.047U_0603_25V7K
1
4 2 3 V1N_VGA
NTC_VGA
PC859 LF1_VGA
1
1
PR855 Mars@
330P_0402_50V7K
3.65K_0402_1%
2
1
PR857 Mars@
PR856
1_0402_1%
4.7_1206_5%
10K_0402_1%
PR858
2
8
0.01U_0402_25V7K
PC864 @
LGATE1_VGA
330P_0402_50V7K
2
1
1
PC863 @
11K_0402_1%
2
1
PC862 PH802
PR859
1000P_0402_50V7K 10K_0402_1%_TSM0A103F34D1RZ
1 SNUB1_VGA
PR860
2
1 2
VSUM-_VGA
<27,55> VSSSENSE_VGA
2
Layout Note:
0_0402_5%
Place near Phase1 Choke
VSUM+_VGA
PC865 Mars@
PR862 Mars@
ISEN1_VGA
680P_0402_50V7K
PR861 1.1K_0402_1%
4
1 2 1 2 4
VSUM-_VGA
10_0402_1%
2
1
PC860 PR862 PC866

0.1U_0402_16V7K
2
Mars@ Sun@
0.22U_0603_10V7K 845_0402_1%
VGA_COREP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9641P 0.2
A B C D
5 4 3 2 1
D D
PR918
121K +-1% 0603
1 2 SWN3
PR911 PR919 47W@ 37W: @
220K_0402_5%_ERTJ0EV224J
165K_0402_1% 121K +-1% 0603
1 2 1 2 SWN2 47W: INSTALL
1000P_0402_50V7K
0.047U_0402_16V7K
CSREF
820P_0402_50V7K
75K_0402_1%
20K_0402_1%
PR920
PR926 @
121K +-1% 0603
1
PH901
PR901
PC901
PC910
PC916
1 2 SWN1
PR929
2
5.76K_0402_1%
1
CSP3 2 1
SWN3 <57>
Place close to
1000P_0402_50V7K
0.047U_0402_16V7K
CSREF
phase 1 inductir
20K_0402_1%
PC917 47W@
37W: @
PR927 @
PC911
47W: INSTALL
1
1
PR930 47W@
2
5.76K_0402_1%
CSREF <57>
1
CSP2 2 1
SWN2 <57>
PR922
CSP3
0.047U_0402_16V7K
CSREF
20K_0402_1%
CSP2 37W@
PR928 @
PR913
PC918
CSP1
CSSUM
C CPU_B+ 43K_0402_1% C
PR904 37W@ PR931
DRON <57>
2
5.76K_0402_1%
1
PR922 47W@ CSP1 2 1
SWN1 <57>
37W@ 10K_0402_1% 66.5K_0402_1%
2 CSCOMP 1 2 37W=43K
PR907
10K_0402_1% 1K_0402_1% 37W=10K 47W=66.5K
+5VS
<43> IMVP_IMON 47W=15.4K 81103_PWM <57>
1
2
0.01U_0402_25V7K
PR932 37W@
PC902 PC904 BST_CPU_Phase3
2K_0402_1%
330P_0402_50V7K 10P_0402_25V8K PR913 47W@
1 2 1 2 1 2 PR912 15.4K_0402_1%
1
PC905
PR902 37W=10K 24.3K_0402_1% PU901 PR924 PC913
27
26
25
24
23
22
21
20
19
49.9_0402_1% 1 2 NCP81103MNTWG_QFN36_5X5 2.2_0603_5% 0.22U_0402_10V6K
47W=7.5K
1
1 2BST_CPU_Phase3-2
1 2
CSSUM
CSREF
CSCOMP
PWM2/IMAX
DRON
CSP3
CSP2
CSP1
BST3
2
2
PC908
PR904 47W@ 470P_0402_50V7K CSP2 37W: INSTALL
1 2 1 2 2 1 28 18
ILIM HG3 HG3 <57> 47W: @
PR903 29 17
IOUT SW3 SW3 <57>
1K_0402_1% 7.5K_0402_1% 30 16 PC914
VRMP LG3 LG3 <57>
31 15 1 2
32 COMP PVCC 14
33 FB PGND 13 2.2U_0603_10V7K
1 2 34 DIFFOUT LG1 12
LG1 <57> +5VS
VSN SW1 SW1 <57>
PR909 35 11
VSP HG1 HG1 <57>
1K_0402_5% 36 10
<10,11> VSSSENSE VCC BST1
1
VR_RDY
VRHOT#
INT_SEL
TSENSE
1 2
ALERT#
PC903 PR925 PC915
ROSC
1000P_0402_50V7K 37 2.2_0603_5% 0.22U_0402_10V6K
SCLK
SDIO
PC906 GND 1
BST_CPU_Phase1 2BST_CPU_Phase1-1
1 2
EN
<10> VCCSENSE
2
2200P_0402_50V7K
1
2
3
4
5
6
7
8
9
PR921
B 1 2 45.3K_0402_1% B
+5VS 1 2
TSENSE
2.2U_0603_10V7K
PR908 PR914 @
2_0603_5% 0_0402_5%
ALERT#
2
PC907
1 2
VR_RDY
SCLK
SDIO
PR945 <43> VR_ON
2
1 2 PR915 @
1
0_0402_5% PC912
0.1U_0402_10V7K 1 2 .1U_0402_16V7K
<43,48,49,6> H_PROCHOT#
1
0.1U_0402_25V6K
TSENSE
PR946
2
PC987 @
1
1 2 PR917
1
34.8K_0402_1%
0.1U_0402_10V7K PR942 @
2
0_0402_5%
1
+VCCIO_OUT
PR947
100K_0402_1%_TSM0B104F4251RZ
1 2
1.91K +-1% 0402
0.1U_0402_10V7K
1
130_0402_1%
54.9_0402_1%
VRHOT Assert Threshold : 472 mV

2
61.9K_0402_1%
PR916
PR948 TSENSE Bias Current : 120 uA
2
PR923 @
PH902 @
PR906
PR910
@ ALER# pull high at HW side

1 2 PRZ146=61.9K, 110C active
need to confirm HW circuit
2
0_0402_5% PC909
1
.1U_0402_16V7K
1
1
PC989 @ 1 2 SDIO
<10> VR_SVID_DAT
+3VS
560P_0402_50V7K PR905
1 2 0_0402_5% Close VR side
VGATE
<15,43>
ALERT#
<10> VR_SVID_ALRT#
A Place close to A
SCLK
<10> VR_SVID_CLK phase 1 MOSFET
2011/12/14
Compal Secret Data
2012/12/31 Title
Issued Date Deciphered Date
CPU_CORE1
Custom 0.2
LA-9641P
5 4 3 2 1
5 4 3 2 1
B+
PL901
D D
FBMA-L11-453215800LMA90T_2P
1 2
CPU_B+
560P_0402_50V7K
470P_0402_50V7K
560P_0402_50V7K
470P_0402_50V7K
560P_0402_50V7K
1 1
220U_25V_M
100U_25V_M
1
+ +
PC985
PC986
PC942
PC943
PC944
PC945
PC988
CPU_B+
2
2 2
10U_0805_25V6K
10U_0805_25V6K
5
PQ901
1
PC920
PC925
2
2
4
<56> HG1
MDU1516URH_POWERDFN56-8-5
3
2
1
PL902
0.22UH +-20% PCMB104T-R22MS 35A +CPU_CORE
1 4
<56> SW1
2 3
5
<56> LG1
1
PQ902
R22
4.7_1206_5%
V1N_CPU
CPU_B+
PR937
0.82mohm
10U_0805_25V6K
10U_0805_25V6K
5
4 2 1
CSREF <56>
2
1SNUB_CPU1
PQ905
1
PR939
PC938
PC939
10_0402_1%
680P_0603_50V7K
MDU1511RH_POWERDFN56-8-5 SWN1 <56>
3
2
1
2
4
<56> HG3
PC922
C C
2
MDU1516URH_POWERDFN56-8-5
+CPU_CORE
3
2
1
PL904
0.22UH +-20% PCMB104T-R22MS 35A
1 4
<56> SW3
1
2 3
4.7_1206_5%
5
<56> LG3
PQ906
PR943
2
PR944
4 V3N_CPU 2 1 CSREF
SNUB_CPU3
10_0402_1%
MDU1511RH_POWERDFN56-8-5 SWN3 <56>
3
2
1
680P_0603_50V7K
1
PC940
2
CPU_B+
10U_0805_25V6K
10U_0805_25V6K
PC932 47W@
PC933 47W@
PR936 47W@
1
2.2_0603_5%
B B
BSTA2 1 2 BSTA2_1
47W@
0.22U_0402_10V6K
2
5
PQ903
PC923 47W@
1
2
4
PU902 47W@
NCP81151MNTBG_DFN8_2X2
1 9
BST FLAG
MDU1516URH_POWERDFN56-8-5 PL903 47W@ +CPU_CORE
3
2
1
2 8 HG2 0.22UH +-20% PCMB104T-R22MS 35A

<56> 81103_PWM PWM DRVH
PR935 47W@
2 1EN_VCORE2 3 7 SW2 1 4
<56> DRON EN SW
2K_0402_1%
+5VS 2 1 VCC_VCORE2 4 6 2 3
VCC GND
5
PR940 47W@
1
PR933 47W@ 5 LG2 PQ904

4.7_1206_5%
2.2U_0603_10V7K
0_0402_5% DRVL 47W@

PC919 47W@
1
4
2
SNUB_CPU2 2
PR941 47W@
10_0402_1%
MDU1511RH_POWERDFN56-8-5 V2N_CPU 2 1 CSREF
3
2
1
PC930 47W@
680P_0603_50V7K
1
SWN2 <56>
2
A A

CPU_CORE2
C 0.2
LA-9641P
5 4 3 2 1
A
B
C
D
+CPU_CORE
2 1 2 1
PC947 PC946
5
5
22U_0805_6.3V6M 22U_0805_6.3V6M
2
1
2
1
PC950 PC949
+CPU_CORE
22U_0805_6.3V6M 22U_0805_6.3V6M
+
2
1
2
1
2
1
PC953 PC952 @ PC951 @

22U_0805_6.3V6M 22U_0805_6.3V6M 330U_D2_2.5V_Y
+
2
1
2
1
2
1
PC956 PC955 PC954

22U_0805_6.3V6M 22U_0805_6.3V6M 330U_D2_2.5V_Y
34 X 22u/0805
2
1
2
1
2
1
3 X 330u/9m(47W)
PC959 PC958 PC957

22U_0805_6.3V6M 22U_0805_6.3V6M 330U_D2_2.5V_Y
+
2 1 2 1
2
1
PC962 PC961 @ PC960

22U_0805_6.3V6M 22U_0805_6.3V6M 330U_D2_2.5V_Y
2 1 2 1 2 1
PC965 PC964 @ PC963 @

22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
4
4
34 X 22u/0805
2 1 2 1
2X330u/9m(37W)
2
1
PC968 PC967 PC966 @

22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1
2
1
PC971 PC970 PC969

22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1
2
1
PC974 PC973 PC972

22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1
2
1
PC977 PC976 PC975 @

22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1
PC979 PC978
22U_0805_6.3V6M 22U_0805_6.3V6M
Issued Date
2 1 2 1
PC981 PC980 @
22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1
3
3
PC983 @ PC982
22U_0805_6.3V6M 22U_0805_6.3V6M
2 1
PC984
22U_0805_6.3V6M
2012/04/03
Compal Secret Data
Deciphered Date
2
2
2014/12/31
Size
Title
Date:
LA-9641P
Document Number
Friday, April 19, 2013

1
1
PROCESSOR DECOUPLING
Sheet
of58
59
0.2
Rev
A
B
C
D
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase
1 48 Add PR103,PR110,PR111,PQ102,PC108,PC109
Adapter ID selection circuit 2012.11.28
49 DVT
D
Add PR227,PR230,PR229,PR232,PR225,PQ206,PQ208,PQ207 D
2 Delete reserve circuit B+ to VSB 49 Delete PR217,PR218,PR219,PC204,PQ203,PR223,PR224,PC205,PQ204,PC206 2012.11.28 DVT
3 Pop Snubber by EMI request 50 PR323,PC320 2012.11.28 DVT
4
To reduce Ripple 51 PC411,PC426 and change PL404 to 3.3uH 2012.11.28 DVT
5 Reserve enable signal by HW request 51 Add PR410,PC432 2012.11.28 DVT
6 Add boost resistor by EMI request 51 Add PR421,PR422 2012.11.28 DVT
7 Reserve feedback signal for IC application 51 Add PR413,PC419 2012.11.28 DVT
C C
8 To reduce Ripple 53 Change PL601and PL605 to 1.5uH 2012.11.28 DVT
Delete PC623,PU602,PC624,PR619,PR620,PR622,PC614,PR627,PL602,PR613,
9 Delete reserve circuit 53 2012.11.28 DVT
PC612,PC615,PC616
10 To reduce Ripple 54 Change PL601and PL701 to 3.3uH 2012.11.28 DVT
11 Reserve enable signal by HW request 54 Add PR702 2012.11.28 DVT
12 Pop Snubber by EMI request 55 PR826,PC811,PR855,PC865 2012.11.28 DVT
13 Add input MLCC by EMI request 57 Add PC943,PC944,PC945,PC988 2012.11.28 DVT
B 49 Add PR2003,PR217,PC209,PR212,PC210,PD203,PR208,PQ209,PC211,PU202,PC212,PC213 B
14 Reserve battery detective circuit 2013.03.03 PVT
50 Add PQ314,PR311(Pop)
15 Reserve capacitor by EMI request 50 Add PC318,PC319 2013.03.03 PVT
16 Reduce Component 51 Delete PD401 2013.03.03 PVT
17 Reserve 1.5VSP Power Good by HW request 53 Add PR602 2013.03.03 PVT
18 Reserve bridge resistor by EMI request 55 Add PR948,PC989
A A

PIR (PWR)
Custom 0.2
LA-9641P
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 2 for HW

Change U8 to SA000039A30 8MB ROM 12/25
1 USE singal 8M ROM for BIOS DVT
Del U7,R239,R234,R235,R233,R236
POWER NEW AC Connector U31.21--> ADP_65 U31.68 change from EC_WL_OFF# to ADP_90 12/25
D
2 U31.85 change from EC_TS_ON#to ADP_135 U31.66 change from BRDID_1 to ADP_ID DVT
D
Change XDP pull down Resistor to R pack Del R18,R21,R23 / Add RP19 12/25
3 DVT
Update Lenovo BGA footprint UV1,U4,UV5,UV6,UV7,UV8,UV9,UV10,UV11,UV12 12/25

4 DVT
Move 15" ODD CAP to Small Board ChangeC605 to R401/ChangeC606 to R402/ 12/25
5 ChangeC618 to R403/ChangeC617 to R404 DVT
WLAN Control change to PCH PCH_GPIO55--> PCH_WL_OFF#

12/25
6 PCH_GPIO22-->PCH_BT_ON# DVT
PCH_GPIO34-->INTEL_BT_OFF#
7 POP TL_ENVDD PULL DOWN POP R408 12/25

DVT
8 Del RP19 12/25 DVT

Change HDMI LV from 10P8R to 8R4R X2 ADD RP5, RP6
C C
NOVO# change form pin 26 to 34

9 Update EC GPIO EC_FAN_PWM change form pin 34 to 26
12/25 DVT
ENBKL change form pin 73 to 76
IMVP_IMON change form pin 76 to 73
DGPU_PWR_EN change form pin 107 to 123
10 VGA sequence +1.5VGS : RV41 --> 240K / CV53 --> 0.1U 12/25 DVT
EC Board ID Change R695 to 15K 12/25 DVT

11
JODD1->ALLTO_C18518-11305-L_13P-T 12/25 DVT

12 Change ODD connector symbol
13 C111/ C112 --> 15p 12/25 DVT

Update Crystal cap Value by vendor suggestion CV36/CV37-->8.2p
B B
14 Reserve for EMI ADD R411,R412,C411,C412 12/25 DVT
15 Change PCIE port and clock connection by SW request

LAN-->Port 3 / WLAN--> Port2 12/25 DVT
Reserve R301 Reserve +3VLP power rail to EC 12/25 DVT

16
Change EC_RST# power rail to +3V_EC Using power rail which the same with EC. 12/25 DVT
17
Change EC_SMB_CK1 & EC_SMB_DA1 power rail to +3V_EC Using power rail which the same with EC. 12/25 DVT
18
19
20
A 21 A
22

PIR (HW)
Custom 0.3
VIWGQ/GS
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List) Page 2 of 2 for HW
1 Add resistor to switch audio power from +3VS Add RA1,RA2 02/18 PVT
to +3VLP and +3VALW.
D D
Reconnect HDD +3VS power rail. Add R-short R552. 02/18 PVT
2
Modify LED current limiting resistor value. Modify : R623,R765,R303 02/18 PVT
3
Add parallel resistor to separate BIOS and EC. Add RP2 02/18 PVT
4
Add a Capacitor to connect CHASSIS_GND and GND by EMI request. Add CL64 02/18 PVT
5
8
C C
10
11
12
13
B B
14
15
16
17
18
19
20
A 21 A
22

PIR (HW)
Custom 0.3
VIWGQ/GS
5 4 3 2 1

Lenovo G410 G510 (Compal LA-9641P)

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A B C D E

DIS M/B Schematics Document

Security Classification Compal Secret Data Compal Electronics, Inc.

1 AMD MARS XT M2 128 bits

/ SUN PRO M2 64 bits

LVDS Conn. LVDS Translator rPGA946

Left USB3.0 x2 Right USB2.0 Int. Camera

USB20 x6 Touch Screen Card Reader

Board ID PCB Revision Full ON HIGH HIGH HIGH HIGH ON ON ON ON

+5VALW +1.35V +VCC_CORE

USB Port Table

S5 S4/AC BTO Item BOM Structure

Mars XT VRAM STRAP Power-Up/Down Sequence

2GBytes 1GBytes VDDR1(1.5VGS)

Samsung_2G Micron_2G Hynix_2G Samsung_1G Micron_1G Hynix_1G Hynix_1G

ZZZ1 14@ ZZZ2 15@

14" PCB LA9641 15" PCB LA9641

Haswell rPGA EDS

Security Classification Compal Secret Data

DDR3 COMPENSATION SIGNALS

AR27 CATERR SM_RCOMP_2 AN3 H_DRAMRST#

E27 SSC_DPLL_REF_CLKN BPM_N_4 AN28 XDP_BPM#5 For EMI XDP_TDO 5 4

CLK_CPU_SSC_DPLL# 2 @ R27 1 10K_0402_5%

SSC CLOCK TERMINATION, IF NOT USED, stuff R26,R27

SM_DRAMPWROK with DDR Power Gating Topology

Security Classification Compal Secret Data Compal Electronics, Inc.

Haswell rPGA EDS

CPI DRIVER VREF PATH IS DEFAULT

Security Classification Compal Secret Data Compal Electronics, Inc.

COMPENSATION PU FOR eDP

HDMI@ C48 1 2 0.1U_0402_16V7K TMDS_B_DATA2#_PCH T28 M27 EDP_CPU_AUX#

Security Classification Compal Secret Data Compal Electronics, Inc.

CFG Straps for Processor

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition matches

INTEL_HASWELL_HASWELL 9 OF 9 11: (Default) x16 - Device 1 functions 1 and 2 disabled

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

Security Classification Compal Secret Data Compal Electronics, Inc.

Haswell rPGA EDS +CPU_CORE

R78 2 @ 1 0_0603_5% AE34

+VCCIO_OUT AN35 RSVD VCC AF29

R83 1 2 43_0402_5% H_CPU_SVIDALRT# AM28 AH29

Security Classification Compal Secret Data

Haswell rPGA EDS Haswell rPGA EDS

Security Classification Compal Secret Data Compal Electronics, Inc.

A 201 202 SMB_CLK_S3 A

1 1 203 204 +0.675VS

<7> DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB

1 R93 10K_0402_5% 203 204 +0.675VS

Security Classification Compal Secret Data Compal Electronics, Inc.

W=20mils W=20mils 1 2 PCH_RTCX2

R96 1 2 1M_0402_5% SM_INTRUDER#

R97 1 2 330K_0402_5% PCH_INTVRMEN U4A LPT_PCH_M_EDS

+3V_PCH R106 1 @ 2 10K_0402_5% PCH_GPIO13 C22 AP15 SATA_PTX_C_DRX_N5

PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI

R122 R123 R124

Security Classification Compal Secret Data Compal Electronics, Inc.

<43,56> VGATE A 4SYS_PWROK PCH_WL_OFF# R158 1 @ 2 1K_0402_5% DGPU_HOLD_RST# 2 R167 1 10K_0402_5%

DGPU_HOLD_RST# 2 R168 1 10K_0402_5%

A16 swap overide Strap/Top-Block @

+3VALW PCI_GNT3# Swap Override enabled

2 R312 1 10K_0402_5% EC_RSMRST#

Y43 AB35 CLK_PCIE_VGA#_R R186 1 2 0_0402_5% CLK_PCIE_VGA#