Presentación Eamta

2016
4 y 5 de AGOSTO
A ñ o s
DDepartamepartamenento de Elto de Electrectrootecnia -

Ftecnia - Faculacultad de Ingtad de Ingenieríaeniería
UnivUniversidad Nacional del Cersidad Nacional del Comahue
- NeuquénActas de la Conferencia
- Argomahue Argentina de
- Neuquén - Argenentinatina
Micro-Nanoelectrónica, Tecnología y Aplicaciones
Proceedings of the Argentine Conference
of Micro-Nanoelectronics Technology and Applications
www.eamta.com.ar
IEEE Part Number: CFP16H30-CDR - ISBN: 978-1-5090-3776-6 Universidad
Nacional del Comahue
Buenos Aires 1400, Neuquén, Argentina. | Tel. Fax: +54(299)4488305 E-
mail: departamento.electrotecnia@fain.uncoma.edu.ar
2016 Argentine Conference of Micro-
Nanoelectronics, Technology and
Applications
Conferencia Argentina de
Microelectrónica, Tecnología y
Aplicaciones 2016
ii
2016 Argentine Conference of Micro-
Nanoelectronics, Technology and
Applications
Conferencia Argentina de
Microelectrónica, Tecnología y
Aplicaciones 2016
Coordinated by:
Pedro Julián – Universidad Nacional del Sur
Andreas G. Andreou – The Johns Hopkins University
Universidad Nacional del Sur

Av. Alem 1253, Bahía Blanca, 8000
Argentina
July, 2016
iii
Proceedings of the 2016 Argentine Conference of Micro-
Nanoelectronics, Technology and Applications (CAMTA)
Pedro Julián, Andreas G. Andreou, Editors

CD-ROM: ISBN 978-1-5090-3777-3
71 pages
Copyright and Reprint Permission: Abstracting is permitted with credit to the

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through Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA
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For reprint or republication permission, email to IEEE Copyrights Manager at
pubs-permissions@ieee.org.
All rights reserved. Copyright ©2016 by IEEE.
iv
Message from the Technical Program Chairs
The tenth edition of the “Conferencia Argentina de Microelectrónica, Tecnología y
Aplicaciones” CAMTA, is taking place in Neuquén, hosted by Facultad de Ingeniería,
Universidad Nacional del Comahue, co-located with the eleventh edition of its associated
school (EAMTA).
Eleven regular papers, out of twenty initial submissions were accepted to be presented at the
conference and afterwards be published in IEEE Xplore. The revision process was rigorous and
achieved a 55% acceptance rate. Paper topics include simulation, process design kits, CCD,
wireless power transfer systems, on-chip dosimeters, APS, radiation effects, power converters,
solar cells, filtering, regulators and Hall plates. Three student posters were accepted to be
presented during the conference, encouraging young researchers to present their work. We want
to specially thank all reviewers for their hard work in providing useful feedback to improve the
papers, as they are the key to maintain the technical quality of the proceedings.
The Technical Program is also very diverse and rich. During the event, several lectures will be
delivered by experts from Argentina, Brazil, Uruguay, Chile and Belgium. Industry day will
count with known Semiconductor, Design and EDA companies from around the world, plus
representatives of investment funds and important national electronic companies. This year, a
work session with EDA and local companies will be held with the objective of setting up new
initiatives to leverage local industry using new technologies.
One of the targets of the event is to help establish a technological platform in the country, and in
doing this, we continue emphasizing the central role of students. Therefore, continuing with the
tradition started in the first EAMTA, sixty four (64) full lodging grants, nine (9) full travel grants
and thirty eight (38) partial travel grants were provided to students from different provinces of
Argentina, Chile and Uruguay. We want to thank all sponsors for making this possible. One
hundred and twelve participants have registered for the event so far.
This year, six course tracks will be offered during EAMTA. The basic track (38 attendees) will
cover basic topics on analog circuits, digital circuits, tools, device physics and design
laboratories with EDA tools. An additional analog basic course will provide hands-on design of
CMOS amplifiers. Synopsys will deliver a track covering advanced digital techniques (14
attendees) and entry-level knowledge of digital design flow and advanced industrial tools &
techniques for digital synthesis. An advanced analog design track will cover design techniques
using unified models. In addition, there will be two specialized tracks in radiation effects and
fault tolerant design, and solar cells (81 attendees).
We hope you enjoy the event and the city, and wish you an enriching experience.
Marcelo Moreyra Pedro Julián – Andreas G. Andreou

General Chairs Technical Program Chairs
v
Conference Organization
General Chair
Dr. Marcelo Moreyra
Financial Chairs
Ing. Nicolás Calarco
Dr. José Lipovetzky
Publicity Chair
Dr. Benjamín Reyes
Organizing Committee
Srta. Virginia Aleandri
Ing. Nicolás Calarco
Ing. Facundo Quiñones
Ing. Gustavo San Martín
Ing. Robinson Zapata
Dr. Fernando Perez Quintián
Dr. Marcos Soldera
Dr. Marcelo Moreyra
Sr. Ricardo Fonseca (student)
Sr. Francisco Maldonado (student)
Support Team
Ing. Darío Mendieta
Ing. Daniel Simone
Lic. Rafael Zurita
Sr. Luis Corrale
Sr. Bruno de León (student)
Sr. Bruno D’Angelo (student)
Sr. Fernando Ilafaya (student)
Sr. Mauro Seguel (student)
Sr. Martin Rubin (student)
Sr. Laureano Morcillo (student)
vii
Technical Program
Program Chairs
Pedro Julián
Andreas G. Andreou
Reviewers
Aboushady University of Pierre and Marie Curie

Jaber Abu Qahouq The University of Alabama
Angel Abusleme Pontificia Universidad Catolica de Chile
Laurentiu Acasandrei Instituto de Microelectronica de Sevilla
Antonio Acosta IMSE-CNM/University of Seville, Spain
Osvaldo Agamennoni Universidad Nacional del Sur
Oscar Agazzi ClariPhy Communications, Inc
Luciano Agostini Universidade Federal de Pelotas
Eduard Alarcon UPC BarcelonaTech
Heiner Alarcon Cubas LSITEC
Massimo Alioto University of Siena
Miguel A. Allende Universidad de Cantabria
Jose Aller Universidad Simon Bolivar
Federicoa Agustin Altolaguirre NCTU
Martı́n Alurralde CNEA
Luis Nero Alves Universidade de Aveiro
Vinı́cius Alves UFSC
José Amaya University of Sao Paulo
Santiago José Amodeo Universidad Nacional del Sur
Paul Ampadu University of Rochester
Andreas Andreou Johns Hopkins University
George Antoniou Montclair State University
Jose A. Apolinario Jr. IME - SE/3
Pablo Aqueveque University of Concepcion
Javier Aracil Universidad Autonoma de Madrid
Jorge Ardenghi Universidad Nacional del Sur
Hugo Arelovich Universidad Nacional del Sur
Alfredo Arnaud Universidad Católica del Uruguay
Babak Ayazifar UC Berkeley
Andres Aymonino Universidad Nacional del Sur
Rodolfo Azevedo University of Campinas
Juan Balda University of Arkansas
Sergio Bampi Federal University of Rio Grande do Sul
Franck Banag Dialog Semiconductors
Leonardo Barboni UDELAR
viii
Fernando Baruqui UFRJ
Philippe Benabes Supelec
Mario Benedetti Universidad Nacional de Mar del Plata
Fabio Luiz Bertotti Universidade Tecnológica Federal do Paraná
Eduardo Bezerra UFSC
Ignatius Bezzam Santa Clara University
Marco Binello Alenia Aermacchi
Gery Bioul UNCPBA
Jennifer Blain Christen Arizona State University
Elena Blokhina University College Dublin
Ivan Bobrinetskiy National Research University of Electronic Technology
Guillermo Bomchil GB NANOCONSULTING
Juan Jose Bonaparte CNEA - UTN-FRH
Mounir Boukadoum Université du Québec à Montréal
Guilherme Brasil Pintarelli IEB-UFSC
Julian Fernando Bravo-Parra Universidad del Valle
Robison Brito Universidade Tecnológica Federal do Paraná
Marcelo Bruno Universidad Nacional del Sur
Marcelo Javier Bruno Universidad Nacional del Sur
Fabián Buffa Universidad Nacional de Mar del Plata
Claudio Busada Universidad Nacional del Sur
Sergio Callegari University of Bologna
Belen Calvo University of Zaragoza
Pablo Cancela UDELAR
Adilson Jair Cardoso Federal University of Santa Catarina
Ricardo Carmona-Galán Instituto de Microelectronica de Sevilla
Walter Carpes Jr Universidade Federal de Santa Catarina
Hugo Carrer Clariphy Argentina S.A.
Daniel Carrica Universidad Nacional de Mar del Plata - CONICET
Luigi Carro UFRGS
Andrew Cassidy IBM
Juan Castagnola Universidad Catolica de Córdoba
Carlos Castro-Pareja Harmonic Inc
Gert Cauwenberghs UCSD
Ricardo Cayssials Universidad Nacional del Sur
Ariel Cedola GEMYDE
Santiago Celma Universidad de Zaragoza
Roberto Cerdas-Robles ITCR
Alfonso Chacon-Rodriguez Instituto Tecnológico de Costa Rica
Victor Champac INAOE
Edgar Charry Rodrı́guez Universidade de São Paulo
Wang Chau University of Sao Paulo
Fernando Chavez Ceitec-SA
Liang-Gee Chen National Taiwan University
Shuai Chen University of Toronto
Hector Chiacchiarini Universidad Nacional del Sur
Jun Rim Choi Kyungpook National University
Malgorzata Chrzanowska-Jeske Portland State University
ix
Pau-Choo Chung National Cheng Kung University
Dalton Colombo CEITEC
Lucas Compassi Severo Federal University of Pampa - UNIPAMPA
David Javier Cordova Vivas NSCAD
Maria Luisa Corona CUJAE
Nelson Correa Andinum, Inc.
Pascal Cotret Supélec
Juan Cousseau Universidad Nacional del Sur
Eugenio Culurciello Yale University
Rene Cumplido INAOE
Ana Isabela Cunha Universidade Federal da Bahia
Maria Belen D’Amico UNS-CONICET
Eduardo Da Costa Catholic University of Pelotas - UCPel
Diogenes Da Silva UFMG - Federal U. of Minas Gerais
Paulo Augusto Dal Fabbro Chipus Microelectronics
Robeto Damore Technological Institute of Aeronautics
Ali Davoudi University of Texas at Arlington
Francisco-J De La Hidalga-W INAOE
Alejandro De La Plaza UBA
Jose M. De La Rosa Universidad de Sevilla
Alexandre S. de La Vega Universidade Federal Fluminense
Jader De Lima Freescale Semiconductor Brazil
Roberto de Matos Instituto Federal de Santa Catarina
Luciana De Micco FIUNMDP CONICET
Jocemar Francisco de Souza Technological Institute of Aeronautics
Tobi Delbruck UNI-ETH Zurich
Simon Deleonibus CEA-LETI
Gustavo Denardin UTFPR
Martin Di Federico INTI-CMNB, Universidad Nacional del Sur
Alejandro Diaz-Sanchez INAOE
Jean-Philippe Diguet Lab-STICC
Steve Dilbeck Skyera Inc
Patricio G. Donato CONICET - Universidad Nacional de Mar del Plata
Carlos Dualibe Fresscale Semiconductors Brasil LTDA
Carlos Dualibe Université de Mons
Francisco Duque-Carrillo University of Extremadura
Hebe Duran CNEA
Abdelali El Aroudi Universitat Rovira i Virgili
Paulo Engel Universidade Federal do Rio Grande do Sul
Burcu Erkmen Yildiz Technical University
Gustavo Escudero Instituto Nacional de Tecnologı́a Industrial
Parastoo Eshraghi Islamic Azad University, West Tehran Branch, Tehran, Iran
Guillermo Espinosa INAOE
Horacio Estrada Centro Nacional de Metrologia
Ralph Etienne-Cummingss JHU
Eric Fabris UFRGS
Adrian Faigon Universidad de Buenos Aires, Facultad de Ingenierı́a
Adrian Faigon Facultad Ingenieria - UBA
x
Arturo Fajardo Pontificia Universidad Javeriana
Fahti Farag Electronics and Communication Dept., Faculty of Eng.
Zagazig University
Luis Ernesto Farah Fernández Instituto Superior Politécnico ”José Antonio Echeverrı́a”
Lester De Abreu Faria Technological Institute of Aeronautics
Gregorio Fernando Universidad Nacional del sur
Enrique Ferreira UCU
Sandro Ferreira NSCAD
Romualdo Alejandro Ferreyra VCU
Tomas Figliola
Igor Filanovsky U. of Alberta
Pablo Fillottrani Universidad Nacional del Sur
Erlon Finardi UFSC
Carlo Fiocchi AMS Italy s.r.l.
Rafaella Fiorelli Instituto de Microelectrónica de Sevilla
Maximiliano Fischer CNEA
Liliana Fraigi PhD
Marcos Funes Universidad Nacional de Mar del Plata - CONICET
Joel Gak Universidad Católica del Uruguay
Antonio Garcia Professor
Guillermo Garcia GEA-UNRC
Lorena Garcia IEEE Colombia Section
Miguel Ángel Garcı́a Andrade
José Gerardo Garcı́a Sánchez Cinvestav
Carlos Arturo Gayoso UNMdP
Alessandro Girardi Universidade Federal do Pampa
Gregorio Oscar Glas FIUBA
José Gabriel Gomes Universidade Federal do Rio de Janeiro
Hector Gomez Universidad Industrial de Santander
Walter Gontijo LINSE/EEL/UFSC
Agustı́n González Universidad Técnica Federico Santa Marı́a
Oscar C. Gouveia-Filho UFPR
Michael Green Univ. of California, Irvine
Fernando Gregorio Universidad Nacional del sur
Victor Grimblatt Synopsys
Marcelo Guarini Pontificia Universidad Catolica de Chile
Guillermo Guichal Emtech
Shalabh Gupta IIT Bombay
Sergio N. Gwirc Instituto Nacional de Tecnologı́a Industrial
Juan Carlos Gómez UTN-FRBA-GIAR
Jose Luis Güntzel Universidade Federal de Santa Catarina
Matias Hadad Universidad Nacional de Mar del Plata
Reiner Hartenstein TU Kaiserslautern
Luis Hernandez-Martinez INAOE
Arturo Hernández González Instituto Superior Politécnico ”J. A. Echeverrı́a”
Fabiano Hessel PUCRS
João Ari Hill IAPAR
xi
Nuno Horta Instituto Superior Técnico
Yalin Hu Sandia National Laboratories
Mario Hueda LCD-UNC
Anh Huynh university of melbourne
Tingting Hwang National Tsing Hua University
Ricardo Jacobi UnB
Julian Jenkins Perceptia Ltd
Manuel Jimenez University of Puerto Rico, Mayagüez Campus
Victor Jimenez-Fernandez Universidad Veracruzana
Marcelo Johann UFRGS
Gordana Jovanovic Dolecek INAOE
Alfredo Juan UNS
Rodriguez Juan Agustin UNS
Pedro Julian Universidad Nacional del Sur - CONICET
Fernanda Kastensmidt Universidade Federal do Rio Grande do Sul - UFRGS
Eric Kerherve IMS
Hamilton Klimach Federal University of Rio Grande do Sul
Marcio Kreutz UFRN
Cristiano Krug CEITEC S.A.
Ney L. V. Calazans FACIN-PUCRS
Walter Lancioni Univ Catolica de Cordoba
Vianney Lapotre Université de Bretagne-Sud - Lab-STICC
Hilda Angela Larrondo UNMDP, CONICET
Ching-Ting Lee National Cheng Kung University
Bernardo Leite UFPR
Diego Lemos UdeA
Betiana Lerner CONICET
Djones Lettnin UFSC
Djones Lettnin
Julio Leão Da Silva Jr.
Omar Lifschitz INTI-CMNBB
Chin-Teng Lin National Chiao-Tung University
Gustavo Linan IMSE-CNM
Mónico Linares-Aranda INAOE
Jose Lipovetzky Low Temperature Lab, CAB, CNEA
Bin-Da Liu National Cheng Kung University
Carlos Humberto Llanos Universidade de Brasilia
Antonio Lopez-Martin Public University of Navarra
Mónica Lovay UTN Fac. Reg. Villa Marı́a
Alex Lozano INTI
Fernando Lozano Universidad de los Andes
Marcelo Lubaszewski CEITEC SA
Marcelo Lubaszewski UFRGS Federal University
Daniel Lupi INTI
Ariel Lutenberg FI-UBA
Laura Malatto INTI - Electronica e Informatica
Pablo Mandolesi Universidad Nacional del Sur
Andre Mariano DELT - GICS - UFPR
xii
Carlos Marques FAMAF (UNC)
Jefferson Luiz Brum Marques IEB-EEL-CTC-UFSC
Franco Martin Pirchio Graduate Student
Jaime Martinez Universidad Veracruzana
Mar Martinez University of Cantanbria
Herminio Martinez-Garcia Technical University of Catalonia
Favio Masson Universidad Nacional del Sur
Fabricio Mattos CEITEC
Miguel Mayosky UNLP
Nicolas Medrano University of Zaragoza
Venkata Rakesh Mekala JNTU
Matias Miguez Universidad Catolica del Uruguay
Shahriar Mirabbasi University of British Columbia
Jose Mireles Jr Universidad Autónoma de Ciudad Juarez
Gerardo Monreal Allegro Microsystem
Jose Monteiro INESC-ID, IST ULisboa
Juan A. Montiel-Nelson Univ. de Las Palmas de Gran Canaria
Carlos Montoro UFSC
Fernando Moraes PUCRS
Robson Luiz Moreno UNIFEI
Miguel Moreto Federal University of Santa Catarina
P.R. Mukund Rochester Institute of Technology
Carlos Muravchik Universidad Nacional de La Plata
Roberto Murphy INAOE
Keivan Navi Shahid Beheshti University
Jean-Francois Naviner TELECOM Paristech
Lirida Naviner Telecom ParisTech
Gabriel Nazar Universidade Federal do Rio Grande do Sul
Roberto Ribeiro Neli Universidade Tecnologica Federal do Paraná
Sergio Netto Federal University of Rio de Janeiro
Robson Nunes De Lima Universidade Federal da Bahia
Maciej Ogorzalek Jagiellonian University
Vojin G. Oklobdzija University of California
Alejandro Oliva Universidad Nacional del Sur
Juan Oliver Universidad de la Republica
Alberto Oliveri University of Genoa
Beatriz Olleta Austria Microsystems
Carlos Martin Orallo UNMdP
Ariel Oroz De Gaetano Universidad Nacional del Sur
Williams Ortiz Martı́nez Universidad Nacional del Sur
Adelmo Ortiz-Conde Universidad Simon Bolivar
Rogelio Palomera University of Puerto Rico at Mayaguez
Felix Palumbo CONICET
Maneesh Pandey Freescale Semiconductor Inc
Eduardo Paolini Universidad Nacional del Sur
Alvaro Pardo Universidad Católica del Uruguay
Flavio Pardo Bell Labs, Alcatel-Lucent
Pablo Daniel Pareja Obregón CNEA
xiii
Mauro Parodi DIBE-University of Genova
Alejandro Pasciaroni Universidad Nacional del Sur
Hernan Pastoriza Centro Atómico Bariloche; CONICET
Marcelo Antonio Pavanello Centro Universitário da FEI
Aristides Pavani Filho CTI
Volnei Pedroni UTFPR
Aldo Pena Perez Stanford University
Roberto Pereira-Arroyo ITCR
Maximiliano S. Perez UNSAM
Sofia Perez UdelaR
Marcelo Peruzzi UNS
Antonio Petraglia Federal University of Rio de Janeiro
Pablo Antonio Petrashin Universidad Catòlica de Còrdoba
Stanislaw Piestrak IJL/Universite de Lorraine
Tales Pimenta Universidade Federal de Itajuba
Pedro Pinto UFMG
Vanja Plicanic Samuelsson Sony mobile
Ariel Luis Pola Fundación Fulgor
Marcelo Porto UFPel
Cesar Augusto Prior Federal University of Santa Maria
Pablo Pérez-Nicoli IIE-FING-UDELAR
Syed Manzoor Qasim King Abdulaziz City for Science and Technology
Max Hering De Queiroz Universidade Federal de Santa Catarina
Flavio Quizhpi Universidad Politécnica Salesiana
Jorge Ramirez LASCAS
Jaime Ramirez-Angulo New Mexico State University
Jorge Ramı́rez Instituto Superior Politecnico J. A. Echeverrı́a
Juan M. Ramı́rez-Cortés INAOE
Fernando Rangel de Sousa Universidade Federal de Santa Catarina
Jose Ernesto Rayas-Sanchez ITESO
Andre Reis UFRGS
Ricardo Reis UFRGS
Leonardo Resende Federal University of Santa Catarina
Benjamin T. Reyes FCEFyN - Universidad Nacional de Cordoba
Linder Alejandro Reyes Martinez Universidad de la República de Uruguay
Claudia Reyes-Betanzo INAOE
Renato Ribas UFRGS
Carlos Rocha Federal University of Santa Catarina
Paloma Maria Silva Rocha Rizol UNESP
Paula Roldán Universidad de Sevilla
Leonardo Romano Centro Universitário da FEI
Hernan Romero Allegro Microsystems Argentina
Murilo Romero University of Sao Paulo
Pedro Agustı́n Roncagliolo UNLP
Conrado Rossi Universidad de la Republica
Adoracion Rueda IMSE-CNM
Alireza Saberkari University of Guilan
Julio Saldaña-Pumarica Universidade de São Paulo
xiv
Gustavo San Martin UNComahue
Juan Sanchez-Garcia IPN ESIME CULHUACAN
Federico Sandoval Cinvestav-Guadalajara
Edson Santana UFBA
Gerard Santillan Federal University of Santa Catarina
Ivan Saraiva Silva Universidade Federal do Piauı́
Arturo Sarmiento INAOE
Mohamad Sawan École Polytechnique de Montréal
Vishal Saxena Boise State University
Silvana Sañudo Universidad Nacional del Sur
Jürgen Scheible Reutlingen University
Marcio Schneider UFSC
Antonio Carlos Schneider Universidade Federal do Rio Grande do Sul
Hiroo Sekiya Chiba Univ.
Nataliya Semyonova North-Caucasus Federal University
Bruno Serra Fing - UdelaR
Francisco Serra-Graells IMB-CNM(CSIC)
Shihab Shamma University of Maryland
Mrigank Sharad IIT Kharagpur
Danilo Silva Federal University of Santa Catarina
Carlos Silva Cardenas UC Peru
Fernando Silveira Universidad de la Repblica
L. Miguel Silveira Universidade de Lisboa
Galo J. A. A. Soler-Illia CNEA
Jorge Solsona UNS
Worawit Somha Fukuoka Institute of Technology
Santiago Sondon INTI
Celso Luis De Souza Alstom Grid
Anderson Spengler UFSC
Milutin Stanacevic Stony Brook University
Leonardo Steinfeld Universidad de la República del Uruguay
Marco Storace University of Genoa
Antonio Strollo University of Napoli
Marius Strum Genia Strum
Guillermo Stuarts Allegro
Altamiro Susin Federal University of Rio Grande do Sul
Gustavo Sutter Universidad Autonoma de Madrid
Daniela Suzuki IEB - UFSC
Santiago Sánchez Solano IMSE-CNM
Carlos Sánchez-López Autonomous University of Tlaxcala
Francisco Tejada Sensing Machines
Esteban Tlelo-Cuautle INAOE
Elı́as Todorovich UNCPBA
Luis Toledo Universidad Católica de Crdoba
Pedro Toledo NSCAD Microeletronics
Diego Tondo Cintelec Electronic Engineering
Guido Torelli University of Pavia
xv
Lionel Torres LIRMM
Reydezel Torres INAOE
Alfonso Torres Jacome INAOE
Massimo Traversone Selex zES
Vladimir Trujillo-Olaya Universidad del Valle
Bartolomeu Uchôa-Filho Federal University of Santa Catarina
J. Alejandro Urrego University of San Buenaventura Bogotá
Carlos Valderrama University of Mons
Manuel Valencia Universidad de Sevilla
Ronald Valenzuela Synopsys
Maria Ines Valla Universidad Nacional de La Plata
Wilhelmus Van Noije University of São Paulo
Cristian Rolando Vargas Santo Tomás University
Gustavo Vazquez Universidad Católica del Uruguay
Cristian Vega Universidad De Antioquia
Alejandro Veiga Universidad Nacional de La Plata
Jaime Velasco-Medina Univ. del Valle Colombia
Raoul Velazco Laboratoire TIMA
Alonzo Vera The University of New Mexico
Omar P. Vilela Neto UFMG
Héctor Vázquez-Leal Universidad Veracruzana
Kyle Web University of Colorado Colorado Springs
Jonathan Wu Canada Research Chair
Vivek Yadav IIT Bombay
Akira Yasuda Hosei Univ.
Bruno Zatt Federal University of Pelotas - UFPel
Cesar Zeferino University of Vale do Itajaı́
Pablo Zegers Universidad de los Andes
Zhaonian Zhang Johns Hopkins University
Hongwei Zhu ARM, Inc.
Julio Zola FIUBA
Marcela Álvarez Universidad Nacional del Sur
xvi
Table of Contents
High-Level Simulation of an FSK Modulator Based on Memconductor . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Carlos Sánchez-López, Luis Enrique Aguila-Cuapio, Iliani Carro-Pérez and Hugo Gustavo
González-Hernández
Development of a sCMOS Interoperable Process Design Kit and an open set of standard digital
cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Gabriel Andrés Sanca, Octavio Alpago and Mariano Garcia-Inza
Measurement of the Read-Out Noise of Fully Depleted Thick CCDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Miguel Sofo Haro, Gustavo Cancelo, Guillermo Fernandez Moroni, Xavier Bertou, Eduardo
Paolini, Javier Tiffenberg and Juan Estrada
Modelling Approach for Low-Frequency Strongly Coupled Magnetic Resonance Wireless Power
Transfer System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Agustı́n Rodrı́guez-Esteva, Pablo Pérez-Nicoli, Fernando Silveira, Bruno Serra and Sofia Perez
COTS CMOS Active Pixel Sensors Damage After Alpha, Thermal Neutron, and Gamma
Irradiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Fabricio Alcalde Bessia, Jose Lipovetzky, Martı́n Perez, Ivan Sidelnik, Miguel Sofo Haro,
Jerónimo Blostein, Mariano Gómez Berisso and Julio Marı́n
Simplified model for radiation effects in MOS devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Lucas Sambuco Salomone and Adrian Faigon
Steady state characterization of current ripple in DCM interleaved power converters . . . . . . . . . . . . . . 33
Maria Paula Cervellini, Pablo Daniel Antoszczuk, Rogelio Garcia Retegui, Marcos Funes and
Daniel Carrica
Study of Excitonic Carrier Dynamics in Quantum Dot Solar Cells by Numerical Simulations . . . . . . 39
Ariel Cedola, Marcelo Cappelletti and Eitel Peltzer Y Blancá
An Statistical Filtering Models Comparison for GNSS LEO Satellite Navigation . . . . . . . . . . . . . . . . . 44
Jorge Cogo, Javier Garcia, Pedro Agustı́n Roncagliolo and Carlos Muravchik
A Floating Voltage Regulator with Output Level Sensor for Applications with Variable High
Voltage Supply in the Range of 8.5V to 35V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Javier Osinaga, Julio Saldaña and Wilhelmus Van Noije
Design and Characterization of Hall Plates in a 0.5 µm CMOS Process . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Nicolás Ronis and Mariano Garcia-Inza
xvii
Author Index
Aguila-Cuapio, Luis Enrique 1

Alcalde Bessia, Fabricio 22
Alpago, Octavio 6
Antoszczuk, Pablo Daniel 33
Bertou, Xavier 11
Blostein, Jerónimo 22
Cancelo, Gustavo 11
Cappelletti, Marcelo 39
Carrica, Daniel 33
Carro-Pérez, Iliani 1
Cedola, Ariel 39
Cervellini, Maria Paula 33
Cogo, Jorge 40
Estrada, Juan 11
Faigón, Adrian 27
Fernandez Moroni, Guillermo 11
Funes, Marcos 33
Garcia Retegui, Rogelio 33

Garcia, Javier 40
Garcia-Inza, Mariano 6, 52
González-Hernández, Hugo Gustavo 1
Gómez Berisso, Mariano 22
Lipovetzky, Jose 22
Marı́n, Julio 22
Muravchik, Carlos 40
Osinaga, Javier 46
Paolini, Eduardo 11
Peltzer Y Blancá, Eitel 39
Perez, Martı́n 22
Perez, Sofia 17
Pérez-Nicoli, Pablo 17
Rodrı́guez-Esteva, Agustı́n 17
Roncagliolo, Pedro Agustı́n 40
xviii
Ronis, Nicolás 52
Saldaña, Julio 46
Sambuco Salomone, Lucas 27
Sanca, Gabriel Andrés 6
Serra, Bruno 17
Sidelnik, Ivan 22
Silveira, Fernando 17
Sofo Haro, Miguel 11, 22
Sánchez-López, Carlos 1
Tiffenberg, Javier 11
Van Noije, Wilhelmus 46
xix
2016 Argentine Conference of Micro-Nanoelectronics, Technology and Applications
High-Level Simulation of an FSK Modulator Based

on Memconductor
C. Sánchez-López, L.E. Aguila-Cuapio, I. Carro-Pérez, H.G. González-Hernández
Abstract—This paper deals with the high-level simulation of emulator circuit can be used for researching real applications,
a frequency-shift-keying (FSK) modulator based on charge- as those mentioned above, a computer model of the memristor
controlled memconductor. The behavioral model of the mem- is of great help for forecasting the behavior of systems to high-
conductor is built on SIMULINK under MATLAB environment. level.
It is demonstrated that the incremental memconductance in- Into the applications described above, modulator circuits are
creases and decreases according the width and amplitude of
important blocks in digital communications since they are used
a positive and negative pulse signal, respectively; whereas the
decremental memconductance increases and decreases according to convert a unipolar bit sequence in an appropriate form for
the width and amplitude of a negative and positive pulse signal. modulation and transmission [24]. Among the modulator cir-
Both incremental and decremental memconductances are used cuits, frequency-shift keying (FSK) modulation is a frequency
to on-line reconfigure the frequency of oscillation of a single- modulation scheme in which digital information is transmitted
memconductor controlled oscillator configured as FSK modulator. through discrete frequency changes of a carrier wave. FSK is
The obtained results not only allows an easy reconfigurability of widely used in modems, radio-teletype, fax modems and can
the FSK modulator, but also demonstrate the viability of the also be used to send Morse code [24]. The main advantage
memconductor to be used in other applications such as cellular of FSK modulation with respect to other modulation schemes
neural networks, controllers, sensors, chaotic systems, relaxation is its low immunity to noise. Since FSK modulation uses,
oscillators, nonvolatile memory devices and programmable analog
basically, two operating frequencies as carriers, a voltage-
circuits.
controlled oscillator (VCO) is commonly used to get these
two frequencies. Because a digital signal has two states, the
I. I NTRODUCTION high-frequency of the VCO is assigned to signal 1 and the low-
frequency is assigned to signal 0, with respect to the center
With the solid-state fabrication of the memristor [1]-[3], a frequency of the VCO. However, a robust synchronization
lot of real applications not only in the analog domain, such scheme between the VCO and the modulating signal level
as cellular neural networks [4], modulators [5]-[7], chaotic is necessary in order to avoid spurious emission, since the
systems [8], relaxation oscillators and programmable analog continuity between bits could not be holded, resulting at
circuits [9], but also in the digital domain, such as nonvolatile unnecessary spectrum regrowth. Furthermore, the use of an
random access memory [10], logic gates and reconfigurable single oscillator not only reduces the discontinuities in the
logic circuits [11], [12], are current research topics. A charge- phase and has as consequence the elimination of sudden
or flux-controlled memristor is a two-terminal element whose changes in amplitude, but also reduces the sideband power
memristance changes with the current flow through it and at a and the interference with neighbor channels [5]. In this sense,
particular direction. This memristance is freezed whether the a lot of programmable VCOs designed with different active
current flow is stopped and hence, at this state, the memristance devices have been proposed in the literature. However, despite
becomes a linear resistor until that the current flow begins of that these oscillators can be used as FSK modulators,
again. This feature makes that the memorize memristor the several passive components and a large number of switches
passed amount of electric charge. Despite that some solid-state are necessary to control the frequency of oscillation (FO)
memristors have been fabricated by different companies and in a wide range, and hence not only lead to relatively high
research labs, they are not still availables on the market and power consumption and complex designs, but also limiting
hence, not only a lot of computer models have been proposed their functionality [24].
in the literature to be used in numerical simulations [13]-[15], All in all, the purpose of this paper is demonstrate, by
but memristor emulator circuits have also been designed using means of high-level simulations, that the behavior of an
different active devices [16]-[23]. In this point, although an FSK modulator based on memconductors can be achieved
[5], [6]. Unlike of VCOs used as main core into an FSK
Manuscript received July 17, 2016. This work was supported in part by the modulator, a single-resistance-controlled sinusoidal oscillator
National Council for Science and Technology (CONACyT), Mexico, under
Grant 222843; in part by the Universidad Autónoma de Tlaxcala (UATx), (SRCO) is herein used, where the SRCO becomes a single-
Tlaxcala de Xicohtencatl, TL, Mexico, under Grant CACyPI-UATx-2015; and memconductor sinusoidal oscillator (SMCO). The charge-
in part by the Program to Strengthen Quality in Educational Institutions, under controlled incremental or decremental memconductor, whose
Grant P/PROFOCIE-2015-29MSU0013Y-02. behavioral model has been experimentally validated in [22], is
C. Sánchez-López and L. E. Aguila-Cuapio are with UATx-Mexico. (e-mail:
carlsanmx@yahoo.com.mx, luis aguila10@outlook.es) here used. The rest of the paper is organized as follows: Section
I. Carro-Pérez and H. G. González-Hernández are with Tecnológico de II introduces the behavioral model of the memconductor built
Monterrey, Puebla-Mexico. (e-mail: icarrop@itesm.mx, hgonz@itesm.mx) on SIMULINK under MATLAB environment. We will show
ISBN 978-1-5090-3777-3/16/$31.00 ©2016 IEEE 1 IEEE Catalog Number CFP16H30-ART

2.5
I Y3 W X1
2
S (3) (7) (1)
Y Z 1.5
(3) (5) Y4 JN
33
N D6 1
84
4A D (4) A
Rm Rx AD (6) (2)
X W Cm Z X2 0.5
VR1(t)(V)
(2) (6) Ca
im 0
+v ï0.5
m
ï1
ï1.5
ï2
Fig. 1. Charge-controlled grounded memconductor emulator circuit taken ï2.5
ï2 ï1.5 ï1 ï0.5 0 0.5 1 1.5 2
from [22]. Vm(t)(V)
Fig. 3. Frequency-dependent pinched hysteresis loop of Fig. 2.
2.5
1.5
Amplitude (V)
0.5
!
0
Fig. 2. SIMULINK model of (1). −0.5
−1
−1.5
how the memconductance can be varied according the width
−2
and amplitude of a negative and positive pulse signal, respec-
tively. The SMCO design is presented in Section III, whereas −2.5
0 1 2 3 4 5 6 7 8
Time (sec)
numerical simulations of the FSK modulator are presented x 10
−6
in Section IV. Finally, some conclusions are summarized in (a)

Section V. 7
x 10
−4
II. M EMCONDUCTOR M ODEL 6
Among all the memristor emulator circuits reported in the 5

Memconductance (S)
literature, the simpler emulators and with better performance

4
are those designed with second generation current conveyors
(CCIIs). In this sense, floating and grounded memristor emula- 3
tor circuits in their versions incremental and decremental were
proposed in [19], [22], [23], showing a good performance at 2
high-frequency. Herein, the charge-controlled grounded mem-

1
conductancia emulator circuit described in [22] and shown in
Fig. 1 is used. Its behavioral model is given by 0
0 1 2 3 4 5 6 7 8
Time (sec)
± Av Ai −6
1 x 10
W2 (qm (t)) = Rm +Rx 10(Rm +Rx )(Cm +Ca ) qm (t) (1)
(b)
where Av ≈0.98 and Ai ≈0.98 are the voltage and current
gains between the Fig. 4. (a) Pulse train to control the memconductances, (b) Variation of
∫ t y- and x-terminal and x- and z-terminal of the incremental (blue line) and decremental (red line) memconductance in
CCII+; qm (t)= 0 im (τ )dτ ; Rx ≈75Ω and Ca ≈8.5pF are the function of the pulse train.
parasitic resistance and capacitance connected in the x- and
z-terminal, respectively [25]. The positive sign in (1) denotes
an incremental memconductor and the negative sign denotes [23], the memconductor was configured to operate to 577 kHz
the decremental memconductor. According to [23] the average with Am =2 V and therefore Rm =2.9 kΩ and Cm =27 pF so that
current will occur when the linear time-varying part of (1) is k=0.5. It is worth to stress that Am can lightly be increased but
zero and hence one should have care that k<1 to avoid distorting the hysteresis
vm (t)
im (t) = (2) loop [19], [23]. Figure 3 shows the pinched hysteresis loop
Rm + Rx of Fig. 2. As evident in figure, the memconductance varies
By merging (1) and (2), a SIMULINK model can be built, according the amplitude and period of a sinusoidal input
as depicted in Fig. 2. In this figure the input-terminal second signal. In practice, however, the memconductance value must
of the adder block must be negative to obtain a decremental be increased or decreased to a specific value and should be hold
behavior. According the design guide described in [19], [22], up during a time interval. This behavior achieves through a

R3 V0
Y W Y W
(3) (6) (3) (6)
AN1 AN2
844 8 44
AD AD
X Z X Z
(2) (5) (2) (5)
R1 W2
C1 C2
(Inc or Dec)
Fig. 5. SMCO based on SRCO taken from [26].
positive or negative pulse signal applied to the memconductor,

as depicted in Fig. 4 (a). Note that for incremental topology, the
memconductance increases according the amplitude and width
of the positive pulse signal, as shown in Fig.4(b) (blue line).
Once that the pulse is zero, the value of the memconductance
is frozen until the following pulse. In order to decrease the
memconductance, a negative pulse signal is applied. A similar !
behavior obtains for the decremental topology, only that here,

the memconductive behavior is inverted, as illustrated in Fig. Fig. 6. FSK modulator based on memconductors.
4(b) (red line).
where Rxj and Czj =Ca are the parasitic resistances and
III.
S INGLE -M EMCONDUCTOR C ONTROLLED capacitances in each x- and z-terminal associated to j-th CFOA;
S INUSOIDAL O SCILLATOR Ayx,zw is the voltage gain between the y- and x-terminal and
vj
In the literature there are a great amount of sinusoidal z- and w-terminal of each CFOA, respectively; and Aij is the
oscillators by using different topologies and active devices. j-th current gain between the x- and z-terminal of each CFOA
Among all they, second-order sinusoidal oscillators employing [25]. It is seen that CO and FO can be independently controlled
a minimal active devices and passive elements and providing through R3 and W2 , respectively. In this paper, the SMCO was
a control of FO independently of the condition of oscillation designed with an oscillation center frequency of fo =577 kHz
(CO) are desirables [26]. Furthermore, second-order oscillators and hence, R1 =1 kΩ, R3 =942 Ω, C1 =C2 =140 pF and W2 =0.33
by using grounded discrete capacitors are preferable since the mS which correspond to a memristance M2 = W12 =2.9 kΩ. It is
parasitic capacitances associated to the terminals of the active worth noting that the numeric value of M2 correspond to the
devices are absorbed by these discrete capacitors. On the other numeric value of Rm obtained in Section II and when (1) is
hand, since the memconductor depicted in Fig. 1 is a grounded operating as linear time-invariant resistor.
topology, the control of FO of the SMCO selected must also
satisfy this condition. In this way, Fig. 5 shows the SMCO IV. N UMERICAL RESULTS
to be used as FSK modulator, which is based on a SRCO
topology designed with current-feedback operational amplifier Once obtained the behavioral models of the grounded mem-
(CFOA) [26]. Routine analysis of Fig. 5 we get conductor emulator circuit and SMCO given by (1) and (3),
these can be merged in order to built an FSK modulator at
s2 + a1 s + a0 = 0 (3) SIMULINK under MATLAB environment. It is worth noting
that the design of FSK modulators based on memristors
where have been addresed in [5], [6]. However, [5] presents several
( yx ) drawbacks. Firstly, two memristors are required to design the
Azw
v1 Ai1 Av1
a1 = (C1 +Cz1 ) Azw
1
− FSK modulator. Secondly, a preprocessor scheme is needed to
v1 Ai1 R1 (R3 +Rx1 )
Azw zw yx
v1 Av2 Av2 Ai1 Ai2 W2
convert the binary-message signal to a special form to control
a0 = (R3 +Rx1 )(C1 +Cz1 )(C2 +Cz2 )(1+W2 Rx2 ) each memristor. Thirdly, a synchronization scheme between
the signal binary and the switching between the incremental
From (3), the CO becomes and decremental memristors is required. Regarding [6], the
R3 = Ayx major drawback found was that FO and CO of the oscillator
v1 Av1 Ai1 R1 − Rx1
zw
(4)
circuit used cannot independently be controlled and hence,
and the FO is the time-response of FSK modulator cannot be hold in a
√ long time. On the other hand, the full FSK modulator using
1 Azw zw yx
v1 Av2 Av2 Ai1 Ai2 W2 the SMCO described in the previous section along with an
fo =
2π (R3 + Rx1 )(C1 + Cz1 )(C2 + Cz2 )(1 + W2 Rx2 ) incremental memconductor is depicted in the upper part of Fig.
(5) 6, whereas the FSK modulator based on the SMCO and using a

0.18
16000
0.14
14000
0.1
12000
0.06
Memristance (Ω)
10000
Amplitude (V)
0.02
8000
−0.02
6000
−0.06
4000
−0.1
2000
−0.14
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (sec) −4
x 10
−0.18
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (sec) −4
(a) x 10
2.5 (a)
0.18
2
0.14
1.5
1 0.1
0.5 0.06
Amplitude (V)
Amplitude (V)
0
0.02
−0.5
−0.02
−1
−0.06
−1.5
−0.1
−2
−0.14
−2.5
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (sec) −4
x 10 −0.18
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
(b) Time (sec) −4
x 10
(b)
Fig. 7. (a) Variation of the incremental (red line) and decremental (blue line)
memristance in function of a pulse signal with amplitude diferents, (b) Pulse
Fig. 8. Time response of the FSK modulator using: (a) an incremental
train to vary incrementally (blue line) and decrementally (red line) M2
memconductor, (b) a decremental memcondcutor.
signal, as shown in Fig. 8. From Fig. 8(a) and Fig. 8(b) and
decremental memconductor is depicted in the bottom. For each
into the interval [0, 2ms], the operating frequency of the FSK
case, a pulse train with amplitude different is used to vary the
modulator is the same of the SMCO. Next, when a positive
memconductance as shown in Fig. 7. According to Fig. 7(b)
digital signal is applied to the incremental and decremental
(blue line) a pulse with 2 V of amplitude and width of 3µs is
memconductor, as depicted in Fig. 7(b), the memconductance
used to decrement M2 (or increase W2 ), as depicted in Fig.
(or memristance) increases or decreases, respectively. As a
7(a) (blue line), whereas a pulse with 0.3 V of amplitude and
consequence, the FO of the SMCO also increases or decreases,
with the same width mentioned before is used to increase M2
as shown in Fig. 8(a) and Fig. 8(b) into the interval [2ms, 4ms],
(or decrease W2 ), as illustrated in Fig. 7(a) (red line). To both
approximately. Afterwards, by applying a negative digital
cases, the memristances (or meconductances) are frozen until
signal to the meconductors, the FSK modulator returns to its
the next pulse. Therefore, when negative pulses with the same
original FO. Therefore, we can observe that a memconductor
amplitudes mentioned before are applied, both memristances
(or memristor) device is useful for controlling the FO of a
(or memconductances) return to their original state, as one
SMCO and they can be used to design an FSK modulator.
can observe in Fig. 7(a). According the previous analysis, a
preprocessor scheme is needed to convert a digital signal (5
V and 0 V) to the levels required (i.e. ±2 V and ±0.3 V) V. C ONCLUSION
to control the meconductance level. Nevertheless, by applying In this paper, the design of an FSK modulator based
the control signals of Fig. 7(b) in Fig. 6, one obtain an FSK on incremental and decremental memconductors has been

presented. Basically, the memconductors are replacing to a [18] C. Sánchez-López, A. Ruiz-Pastor, R. Ochoa-Montiel and M.A.
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Development of a sCMOS Interoperable Process

Design Kit and an open set of standard digital cells
G. A. Sanca, O. Alpago, M. Garcia-Inza
Abstract—An Interoperable Process Design Kit (iPDK) was Interoperable PDK’s structure was defined by the IPL Al-
developed for the scalable CMOS process SCN3ME provided by liance, an industry standard organization established to develop
ON Semiconductors, reachable across MOSIS. It includes DRC interoperable eco-systems for custom design [1], and following
and LVS rules, SPICE models, technology files, verification and
extraction files, execution scripts, symbol library and parametric OpenAccess guidelines, which must be respected to maintain
cells (PCells). Then, using the iPDK, a set of standard digital interoperability. Two different groups of components can be
cells were developed. A test chip was designed and fabricated. distinguished: those which are supplied by the foundry (maybe
Measurements results are presented. not in OpenAccess format) and those which should be part of
Index Terms—CMOS, iPDK, IC Design, PCells, Standard iPDK by definition.
Cells. In the first group, the information related to verification
is placed, such as design rules (DRC) and layout versus
schematic rules (LVS); SPICE model of the transistors and
I. I NTRODUCTION
files related to parasitic extraction.
I N this paper, the development of an Interoperable Process

Design Kit is introduced. Even though this kit is extendible
to others scalable processes, in this particular case it was
In the second group, there are five major sub-groups: the
PDK library itself (with layouts and schematics of different
devices); clear and reliable process and PDK documentation;
designed for the open process SCN3ME. Also, using our own technology files and display files; scripts to run different tools
PDK, a standard cell library was designed and tested. and ‘lib.defs’ files (which define how to load and open the
A PDK is a set of files, usually developed by the foundry, library).
which describes and provides specific information to be used
by EDA tools for IC design. Each PDK contains all the
III. S CALABLE P ROCESS
information required by the EDA tools to assist in the in-
tegrated circuits design flow. Simultaneously, a PDK includes The metric unit in the definition of a set of design rules is
schematic symbols, SPICE models, design rules (which allow the minimum width, minWidth, and is equal to the minimum
to validate designs before manufacturing), parametric cells size of the mask that can be safely transferred to the wafer.
(PCells), CDF (Component Description Format) files, and In general, minimum width is set by the resolution of the
callbacks or evaluator code to be executed when one or more lithography.
of these parameters change. Scalable design rules concept, popularized by Mead and
Standard cells are a collection of digital gates with specific Conway, defines all their rules in terms of a single parameter,
functions, which are used in digital design flow to design VLSI called lambda (λ) [3]. The rules are chosen in order to enable
(very large scale of integration) chips. a design to be directly portable to any other industrial process
or feature size. The minimum size scaling is accomplished by
changing the value of λ, resulting in a linear scale of all sizes.
II. I NTEROPERABLE PDK
For a specific process, λ is set to a specific value, and all
The need for developing an Interoperable Process Design the design dimensions are accordingly translated into absolute
Kit was due to the fact that the PDKs were pre-qualified only numbers. Typically, the length of a minimum channel MOS
against specific EDA tools and not against a set of common transistor of a process is set to 2λ [4].
EDA tools available in the industry. MOSIS offers several sCMOS processes: TSMC 0.35, 0.25
iPDK concept addresses this need, and has been the result and 0.18µm, and ON Semiconductors 0.5µm. This last one is
of joint work between EDA tools developers. A iPDK offers included in its MEP program.
the following advantages [2]: Generally, native or vendor rules may be more appropriate
1) A single PDK for all design tools, thus reducing PDK when the design must be improved for using the optimum
development and maintenance time, generating a feed- silicon area (when directly control over the parameters of
back and strong cooperative relationship between the analog design is required), or for large series of production
different entities that use the same processes. (where the loss of design portability is clearly justified) [5].
2) Free choice of analog design flow EDA tools. The iPDK presented in this paper was developed for scalable
3) OpenAccess database for the development of PDK. process SCN3ME SUBM ON Semiconductors. It has two
4) Eliminates the need to translate data. layers of polysilicon, 3 metals and the minimum size λ is
5) Enables the use of parametric cells portable process. equal to 0.3µm. It is important to mention that the iPDK can be
simply modified for working accross different MOSIS sCMOS corresponding EDA tool runs, a copy of it called “super-
available process. master” is generated in memory. This element contains a list
This technology can work with two different power volt- of parameter names, and for each parameter a default value
ages: 5 and 3.3 volts. Minimum transistors have a channel and the acceptable range. In turn, it provides access to the
lenght equal to 2λ (0.6µm) and channel width of 10λ (3µm). script that can be executed by the EDA tool.
However, lithography allows to manufacture channel widths When a user wishes to instantiate a PyCell, a super master
equal to 0.9µm, making dog bone transistors type. view thereof is generated and stored in memory according to
the script. The user will then specify values for the parameters
IV. K IT C OMPONENTS of the cell. When this entry is complete, the system design
will execute the script PCell with the values of the input
The PDK was designed to use OpenAccess libraries and to
parameters. The result will be the creation of a cell, called
be compatible with IPL Alliance standard. For this reason, the
”sub-master”. Each instance of a sub-master has properties
parametric cells were written in pyhton. The DRC and LVS
that contain the set of parameters used for creating instances,
rules are presented primarily for Calibre. The kit comprises:
and the name of the original PCell.
• PCells: OpenAccess library with parametric cells, written
PyCells’ paradigm faces the closed paradigm of EDA ven-
in python (PyCells).
dor tools, where PCells are written in proprietary language,
• Technology files.
such as SKILL or Ample. In this way, the PyCells have
• Layer Maps: for exporting and importing GDSII and for
the property of being portable PCells, which can be used in
running verification tools.
different work environments.
• Design rules: DRC and LVS written for Calibre.
• Standard cells
• SPICE models (given by MOSIS).
D. Verification Files
A. Technology Files DRC and LVS files were generated based on the distributed
Calibre version of MOSIS, and being re-adapted and written
Technology files are used to add process information to
for the iPDK designed. For this, different supports layers were
a library. Generally it contains information on the different
created to run verification routines.
manufacturing layers, design rule definitions and display pack-
ages defined in the display resource file.
Technology files for both PyCell Studio environment (San-
V. S TANDARD D IGITAL C ELLS
tana.tech) and for Synopsys Custom Designer environment
was written, generated from a compilation in OpenAccess Using the iPDK, 28 standard digital cells were designed,
format of the technology file distributed by North Carolina including basic logic functions, such as NOT, AND, NAND,
State University [6], adapted and re-generated to work in a NOR, OR with two and four inputs; multiplexers; AOI and
purely OpenAccess environment. OAI basic functions; and sequential circuits as flip-flops were
designed.
B. Front-End Components The layout was designed considering the concept of Man-
A library called “onc5 pycells”, which contains the PyCells hattan routing, using only polysilicon and METAL1 inside the
designed for the process, was created. Besides the scripts in cells, providing more degrees of freedom to the place and
phyton, the iCDF files (Interoperable Component Description) route tool. METAL2 can be used within standard cells, but it
which define the values of the cells by dafault, were written. should be used always vertically and on a grid. Even with
The SDL, auLVS and SPICE CellViews were also gen- these considerations, it was decided not to use METAL2 in
erated for each PCell, defined in the iCDF file. Symbols cells.
were copied from the fictional PDK SAED28/32, designed
by Synopsys. The ivpcell CellView was copied from the
standard library analogLib. A. Routing Grid
A grid for routing purposes was established according to
C. Parametrics Cells the rules of the scalable process and with reference to the λ
Parametric cells (PCells) are structures which, besides hav- parameter. All cells are single height type.
ing a fixed geometry, also contain an executable program According to Figure 1, measures W2 and W3 are 9λ defined,
just as geometry that can vary according to a number of i.e. 2.7µm. W4 , NWELL extension, was defined as 54λ, i.e.
parameters, such as the width of a channel in a MOS transistor 16.2µm. V1 is defined as 5λ, 1.5µm. Finally, the pitch, defined
or the value of the resistance of a resistor. The importance of as H, is 27µm, that is, 90λ.
these cells lies in the remarkable simplification provided to In addition, the routing grid was defined with an 4.5λ offset,
the kit, while providing flexibility and reducing design time. in order to avoid DRC rules violations. Thus, when cells are
Each PyCell exists within the PDK in two ways: as a layout abutted, the spacing within the nearest structures inside is
in OpenAccess format and as a python script. Whenever the always equal or higher than the grid spacing.
(a) Standard cells. (b) Oscillators.

Fig. 2. Testing structures.
Fig. 1. Pitch and grid [8]. B. Results

1) Static Analysis: A PCB was built with LEDs to verify
that the truth table of the different gates is correct, while
B. Transistor’s sizing entries also have a LED to indicates their output status.
To size the transistors of digital cells the minimum inverter Static operation of all cells was tested changing the input
was taken as reference. The sizing criteria was WP = 2WN as combinations of standard cells. The board is shown in Figure
general rule. 3a.
Then, this criterion was extended to size all pull-up and
pull-down networks. For example, for a 2-input NAND cell,
the model considers the pull-down network as two nMOS
transistors in series and the pull-up network as two pMOS
transistors in parallel. Thus, WN = 2Wmin and WP = 2Wmin .
For a two-input NOR gate, the model is constituted with
two nMOS transistors in parallel in the pull-down network,
and two pMOS transistors in series in the pull-up network. In
this case, WN = Wmin ; and WP = 4Wmin . (a) DIP40 in PCB.
VI. T EST C HIP

In order to test the accurate functionality of the entire PDK
a chip was manufactured across MOSIS Academic Account.
A. Floorplanning
Figure 2a shows the block diagram of the chip. Inputs
A, B, C and D are shared by all cells, divided into three (b) Oscillators measurement.
different groups of gates: four inputs cells, two inputs cells Fig. 3. Measurements bench.
and inverters. In the first group there are eight cells, and in
second and third there are six. The outputs of each group are 2) Dynamic Analysis: In Figure 3b there is a picture of the
multiplexed, using nine control inputs. Then, there are three measurement bench used to estimate the propagation delay by
different outputs. measuring the frequency of the RO. The values shown in Table
In order to estimate the minimum inverter propagation time I are averages obtained from different measurements for each
and having an empirical value to compare with characteriza- oscillator.
tion, four ring oscillators (RO) were designed with different Knowing that the measurement in each case is 256 times
lengths (m-stages), as detailed in the block diagram of Figure lower than the frequency of each oscillator, before calculating
2b, considering that the oscillating frequency would be the propagation time we had to calculate de real frequency:
1
fOR = (1) freal = fmeasured × 256 (2)
2 × td × m
With the signals s0 and s1 each of the oscillators can be Then,
chosen, through a multiplexer. Then, an eight flip-flop chain

 65 , s = 00
is placed in series with the multiplexer, in order to divide the

1 
129, s = 01
output frequency to simplify the output buffer and facilitate td = ,m = (3)
2 × freal × m  193, s = 10
measurements, detailed in Table I.

257, s = 11


Using this iPDK a set of standard cells were designed to be

used in digital designs. To characterize an verify this circuits
a chip was fabricated and tested. The results of measurements
showed the correct operation of the cells.
It is planned to advance in parasitic extraction, and to add
more PCells in order to increase the functionality of the PDK,
especially to extend it for analog design.
VIII. C ONCLUSION
(a) Layout. (b) Photomicrograph. This work is intended as a contribution to the academic
Fig. 4. Top level of the tiny chip manufactured by MOSIS. community; the kit is already shared with some universities
for testing purposes and is actually being used in EAMTA. In
TABLE I the near future it will be shared more extensively. The scalable
P IN CONFIGURATIONS S 1 AND S 0 TO SELECT DIFFERENT RING
OSCILLATORS . M EASURED FREQUENCIES SHOWN HERE ARE ARITHMETIC
0.5µm MOSIS’ process is widely used in various universities
MEAN . to teach courses on VLSI design, analog and mixed-signal
design. At the same time, although it is an old process, it is
s1 s0 Z Stages Ref. Measured Freq. Estimated td very used by the scientific community to validate large number
0 0 A0 65 osc1 252.08 kHz 119.15ps
0 1 A1 129 osc2 125.96 kHz 120.19ps
of prototypes. The development of an Interoperable PDK for
1 0 A2 193 osc3 84.00 kHz 120.47ps this process provides a great help to various research groups.
1 1 A3 257 osc4 63.02 kHz 120.58ps
A PPENDIX A
BASICS PC ELLS
A total of 38 measurements values were used to calculate In this Appendix the layouts of basics PCells are presented.
the propagation delay average. Five of them was from the In Figure 6 the layout of the nMOS PyCell is presented. This
largest RO, fifteen from the 193-stages RO, twelve from the is a basic instance with w = 3µm and l = 0.6µm. In Figure
129-stages RO and six from 65-stages RO. In Figure 5 the 7 the layout of the pMOS PyCells is presented with the same
results are showed. configuration parameters that the nMOS cell. In Figure 8 the
layout of the elec (poly2) resistor, with high resistence layer,
VII. S UMMARY set with W and H equal to 1.5µm and one finguer, is presented.
In this paper we presented the development of an iPDK in- In Figure 9 the poly and elec capacitor is presented. W and
cluding a set of parametric cells (PCells). The interoperability H are set equal to 2.1µm.
of the kit was considered by following the recommendations of
the consortium IPL Alliance and the OpenAccess community.
Files that describe the process technology, verification files,
such as DRC and LVS rules and component description files
were also developed.
The kit can be configured with a menu written in tcl.
Minumun CMOS inverter propagation delay

121 Fig. 6. Layout of the nmos PyCell.
120.5
t_d [ps]
120
119.5
119
0 10 20 30 40
Fig. 7. Layout of the pmos PyCell.

Fig. 5. propagation delay calculated from measured frequencies of RO.

Fig. 8. Layout of the HR_res PyCell.
Fig. 9. Layout of the capacitor PyCell.
ACKNOWLEDGMENT
The authors would like to thank Ronald Valenzuela and
Victor Grimblatt for their contributions and their continued
support. We also thank the MOSIS, Synopsys and Mentor
Graphics academic programs.
This work was supported by Universidad de Buenos Aires,
Facultad de Ingenierı́a, Departamento de Electrónica. The
integrated circuit was designed using Synopsys tools under the
Synopsys University Program. Chips were fabricated through
the MOSIS foundry service supported by the MOSIS Educa-
tional Program (MEP).
R EFERENCES
[1] IPL Alliance [Online]. Available: https://www.iplnow.com.
[2] R. Goldman, K. Bartleson, T. Wood, V. Melikyan, “Synopsys Intero-
perable Process Design Kit”, European Workshop on Microelectronics
Education, Darmstadt, Germany, 10-12 May, 2010, pp. 119-121.
[3] C. Mead and L. Conway, Introduction to VLSI Systems, United States:
Addison-Wesley, Reading, MA, 1980.
[4] J.M Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits,
United States: Prentice Hall, 2003.
[5] MOSIS, “Design Rules: MOSIS Scalable CMOS (SC-
MOS)”, Revision 8.00, May 2009 [Online]. Available:
https://www.mosis.com/files/scmos/scmos.pdf
[6] NCSU Electronic Design Automation (EDA) Wiki [Online]. Available:
http://www.eda.ncsu.edu/wiki/NCSU EDA Wiki
[7] N. H.E. West, D. Harris, CMOS VLSI Design, United States: Addison-
Wesley, 2011.
[8] Goldman R., Bartleson K., Wood T., Kranen K., Cao C., Melikyan V.,
“Synopsys Open Educational Design Kit: Capabilities, Deployment and
Future”, Proceedings of the International Conference on Microelectronic
Systems Education, San Francisco, USA, 25-27 July, 2009, pp. 45-48.

Measurement of the Read-Out Noise of Fully

Depleted Thick CCDs
Miguel Sofo Haro, Gustavo Cancelo, Guillermo Fernandez Moroni, Xavier Bertou, Javier Tiffenberg, Eduardo
Paolini, Juan Estrada
Abstract—Fully depleted thick CCDs have been designed

for infrared astronomy, but their low read-out noise of the
order of ≈2 e− and their considerable mass of ≈5.2 gr, allows
novel uses for them in low energy threshold particle detection
applications, such as the CONNIE and DAMIC experiments. For
both experiments, a reduction of the CCD read-out noise is vital.
In this work we present a method to measure the read-out noise
coming from electronic and non-electronic sources. The impact
of the external electronics on the noise is discussed and its full
characterization is presented.
Index Terms—CCD, Read-Out Noise, Spurious Charge.
Fig. 1. Pixel cross section of a 250 µm thick CCD developed by Lawrence
I. I NTRODUCTION Berkeley Laboratory. The electrostatic potential generated by the three phases
under the gates is also shown as a function of depth (Y axis) and one of the
Although invented as memory devices [1], [2], Charge lateral directions (X axis).
Coupled Devices (CCDs) have found a niche as imaging
detectors due to their ability to obtain high resolution digital
images of objects placed in its line of sight. In particular,
scientific CCDs have been extensively used in ground and
space-based astronomy and X-ray imaging [3]. CCDs have
high detection efficiency, low noise, good spatial resolution,
and low dark current. Furthermore CCDs can be made thick
to increase their detector mass, enabling their use as particle
detectors [4]. In particular, their extremely low read-out noise
around 2 e− makes observations with a low energy threshold
of 50 eVee possible [5].
Two novel experiments take advantage of this technology
to detect the interactions between incoming particles and a
nucleus of the silicon atoms of the CCD. One is the direct
dark matter detector called DAMIC (Dark matter in CCDs) [6];
the other one is the CONNIE experiment (Coherent Neutrino-
Nucleus Interaction Experiment) [7] which aims at the de-
Fig. 2. Compendium of particle events at sea level using a 250 µm CCD.
tection of the neutrino-nucleus coherent scattering interaction,
which is predicted but has yet to be observed.
The read-out noise is the current limitation defining the
energy threshold and limiting the study of low energy particle for the DECam project [4], [8] is shown in Fig. 1. Several
interactions [5]. In this work a detailed study and measurement million pixel CCD are fabricated on high resistivity silicon to
of the readout noise of a CCD is presented. The output CCD maximize the depleted silicon volume and therefore increase
circuit is explained with special focus on the design aspects the near-IR photon response. The thickness of these detectors
that degrades the SNR. An estimation of the noise of the is 250 µm, with a mass of approximately 1 gram. The CCDs
output transistor is given. The impact of the external electronic are fully depleted using a substrate voltage. The CCDs are
needed to read the CCD on the final read out noise is also three-phase, p-channel, back illuminated with a special coating
analyzed. in the backside to increase photon absorption and to reduce
backside dark current generation. However, for neutrino detec-
II. F ULLY D EPLETED T HICK CCD S tion the optical features are not relevant. Pixel size is 15 µm×
15 µm. This size gives very good spatial resolution that can
The structure of a scientific CCD developed by Lawrence
be efficiently used in these rare events experiments to reject
Berkeley Laboratory, and extensively characterized at Fermilab
some of the background interactions.
A compendium of backgrounds events from blind mea-
V4 V1 V2 V3
PULSE() 40 -12.5 -22

VREF CGS,MSF
VOUT
VDD
input
MRST CT RL CL
VSUB 20K
PMOS MSF Q 15pF
RG VSUB gm*VGS,MSF
PMOS
CSN VOUT
0.046pF Fig. 5. Small signal model of the output circuit of the CCD of Fig. 3. The
RL CL
input is modeled with a current source i(t) = Qδ(t), Q is the pixel charge.
20K
15pF The parasitic capacitances are included in the model.
used to sense the voltage of the SN. The load resistor RL is not
Fig. 3. CCD output circuit. CSN models the capacitance of the SN. The SN integrated in the CCD chip. CL is the parasitic capacitance of
is reset to VREF through MRST. MSF is in a source follower configuration.
VDD = −22V , VREF = −12.5V . RL is external to de CCD. CL is the the flex cable that connects the CCD with the read-out system,
parasitic capacitance of the flex cable connected to the CCD. and, as we will see, it limits the maximum read-out speed.
Fig. 5 shows the small signal model of the circuit of Fig.
3. The input has been modeled as a current source i(t) =
Qδ(t), representing a packet of charge Q from a pixel that is
CSN transferred to the SN in t = 0. The model includes the parasitic
MRST capacitance of the circuit. CT is given by equation 1. CW is the
capacitance of the connection between the SN and the gate of
MSF. CGD,M SF and CGD,M RST are the gate to drain parasitic
capacitance of the M SF and M RST transistors respectively.
MSF CT = CSN + CW + CGD,M SF + CGD,M RST (1)

Equations 2, 3 and 4 are the calculated transfer function
of the circuit. The gain is inversely proportional to Ceq
capacitance, and must be as low as possible to achieve a
Fig. 4. Output stage of the CCD used in this work. The MSF, MRST transistor
and the sense node are labeled. The metal connection between the SN and high SNR. In this sense, the CCD used in this work has
the MSF has a capacitance of CW and reduce the signal level at the output. been designed with special attention to keep the parasitic
capacitances CW and CGS,M SF in the order of ≈ 10 fF [10].
surements at sea level is shown in Fig. 2: muon tracks

Vout (s) (gmRL ) (sCGS gm−1 + 1)
appear as a straight line crossing the entire silicon volume; = (2)
energetic electrons from electromagnetic radiation produce Q (1 + gmRL )Ceq s (sRL Cp + 1)
wiggling tracks called worms; bright large dots are produced CGS,M SF
by alpha particles as a consequence of the plasma effect that Ceq = CT + (3)
(1 + gmRL )
they generate in the silicon [9]. Point like events, expected
from the coherent neutrino-nucleus scattering and dark matter CGS,M SF CT + CL CGS,M SF + CT CL
Cp = (4)
interaction, appear as energy deposition within a single pixel CGS,M SF + CT (1 + gmRL )
volume where some of the ionized charge flows to neighbor CL does not affect the gain of the circuit but it dominates
pixels by diffusion. the upper frequency cut because CL >> CGD,M SF , CT .
The bandwidth is given by equation 5. For this work CL ≈
III. T HE OUTPUT STAGE OF THE CCD 15 pF and gm ≈ 150 µA/V, resulting in a frequency cut of
Fig. 3 and 4 show the output circuit of the CCD. The ≈ 2.5 MHz. CL limits the maximum read-out speed of the
capacitor CSN models the capacitance of the sense node (SN). CCD, but this is not a limitation for the CONNIE and DAMIC
The charge of a pixel is placed into this capacitance for its experiment, as they only read an image every 1 and 14 hours
measurement using the clock signals. A key aspect to achieve respectively. As will be shown later, this capacitance does not
low read-out noise is to make CSN as low as possible, produc- affect the noise in the bandwith of interest.
ing a higher voltage per electron and therefore improving SNR.
For the CCD used in this work CSN ≈ 0.046 pF, producing a 1 gm
fc = (5)
gain of ≈ 3.5 µV/e− [4]. 2π CL
Before adding the charge of the pixel to the sense node, Fig. 6 shows the output signal that corresponds to the read-
it is charged to a VREF value through a P-MOS transistor, out of one pixel of the CCD. The signal has been digitized
called reset transistor (MRST). Then the charge of the pixel with 24 bits at 2 Msps and downsampled by 8. After applying
is added using the SW phase. MSF is a floating gate P-MOS the reset pulse, the signal is kept at the reset level for a time
transistor working in a source follower configuration, and is T . Then the SW phase is clocked and the charge of the pixel is
58
UPS
57
CRYO
Signal Value [mV]
56 Power
Supply
CTRL
55 SEQUENCER
CCD
RESET SIGNAL DAQ
54
LEVEL LEVEL DEWAR
Electrical isolators
53
PUMP Ground connections
0 200 400 600 800 Cable shielding
Time [µs]
Signals
Cold head
Fig. 6. Signal at the output of the CCD when a pixel is read out. The reset
Heater
level is the level after the reset of the SN, while the signal level is obtained
after adding the pixel charge to the SN. The peaks are due to the clock feed-
trough of the RG and SW pulses. Fig. 7. The CCD is in vacuum inside a metallic vessel. The cryocooler cools
down the CCD to 130 K. The read-out system used is a Monsoon, composed
of a sequencer and a DAQ. The whole system is connected to ground in one
point.
transferred to the sense node. The signal level is also kept for
a time T before the sense node is reset to read the next pixel.
T is called integration time. The peaks in Fig. 6 correspond MONSOON
to the clock feed-through of the RG and SW pulses.
The technique used for processing and measuring the charge SEQUENCER
of the pixel v̂p is the correlated double sampling (CDS) [11]. SMPS
As indicated in equation 6, the CDS consists of taking an CCD x1 x2 DAQ
average of the signal level s(t) and subtract to it an average
of the reset level r(t). CDS removes all the correlated noise
between the reset level and the signal level.
Fig. 8. Simplified diagram of the read-out electronics used in the DAMIC and
Z Z CONNIE experiments. The DAQ and the sequencer are the Monsoon system.
v̂p = s(t)dt − r(t)dt (6) The buffer load the CCD with a low capacitance. The amplifier matches the
<T > <T > output impedance to 50Ω of the connection cable.
IV. E XPERIMENTAL S ET-U P

Fig. 7 shows the experimental set-up used in this work. the two stages are not integrated in the same board and are
To reduce the dark current, the CCD is cooled to 130 K connected by a flex cable of 30 cm long. The connection
with a cryocooler. The CCD is inside a metallic vessel, in between the amplifier and the Monsoon system is a 50 Ω
which a vacuum of 2 × 10−4 mbar is made to avoid humidity coaxial cable with a length of over 1 m.
condensation over the CCD. A temperature controller keeps The CCD is bound to a 35 cm long flex cable connected
the temperature stable and adjusts the velocity of the cooling to the buffer. The parasitic capacitance of the flex cable is
and heating cycles to avoid possible damages to the CCD due ≈ 15 pf, and as was formally mentioned it limits the maximum
to mechanical stress. read-out speed. The buffer is kept far from the CCD to avoid
The read-out system used in this work is the Monsoon the radioactive contamination from the PCB and the circuit
system [12]. It consists of the sequencer, which generates the components [13].
clock signals that shift the charge packets collected in the With the purpose of shielding the CCD and the read-out
pixels to the output circuit, and the DAQ which applies the electronics from EMI, the metallic vessel and the crate of the
CDS to the output video signal of the CCD. The Monsoon Monsoon system are connected to ground in only one point.
is supplied with external switching power supplies, which, as In addition, the metallic vessel is electrically isolated from the
will be shown later in this work, impact the CCD read-out cryocooler and the vacuum pump.
noise. The CCD used in this work is a 250 µm thick with
The CCD is connected to the DAQ through two stages [12]. 4096×2048 pixels. With 40 V of substrate voltage the CCD is
The first stage is a buffer made with a JFET in a source fully depleted. VREF is -12.5 V and VDD -22 V. The horizontal
follower configuration. It provides a low load capacitance to clock swings between 8.5 V and -3.5 V.
the MSF transistor of the CCD output circuit, and has a low
output impedance that makes possible to drive a long cable V. M EASUREMENT OF THE E LECTRONIC R EAD -O UT
without reducing the read-out speed. The second stage is an N OISE
operational amplifier in a non inverting configuration of gain In particle detection applications, there are three sources of
×2 with an output impedance of 50 Ω. For space reasons noise. One of them is the noise added to the signal during
7
L U σR U−side
σ L−side
SIDE SIDE 6 R
NOISE [electrons]
5
V1L,V2L,V3L V1U,V2U,V3U
4
2
H1L,H2L,H3L H1U,H2U,H3U
1
5 10 15 20 25 30 35 40
Integration Time [µs]
Fig. 9. The CCD is split in two half. Depending on the sequence of the Fig. 10. Electronic read out noise of both CCD output stages for different
horizontal clock signals (H1U/L, H2U/L and H3U/L) the charge of the pixels integration time of the CDS. A minimun noise of (1.33 e− ) is achieved with
can be read in three ways: one CCD half through each output stage (green an integration time of 20 µ. The bump between 20 µs and 35 µs, and the high
arrows), the whole CCD through the U-side output stage (red arrow) or the noise below 20 µs, are due to the switching frequencies of the power supplies.
whole CCD through the L-side output stage (blue arrow).
4
10
2
exposure of the CCD, σD , such as dark current and visible 2
light. A second source of noise, σS2 , is the spurious charge 10
that is generated during the shifting of the charge packets [3],

2 0
[14], [15]. The last source, σR , is the noise added by the read- 10
# Pixel
out electronics, and is the subject of study in this work. These

three sources are uncorrelated between them, and as is shown 10
−2
in equation 7 they are added in quadrature. Data U−side

Fit, σT= 1.96 e−
−4
10
Data U−side
−
σT2 = σD
2
+ σS2 + σR
2
(7) Fit, σR= 1.33 e
−6
10
−150 −100 −50 0 50 100 150
In equation 7, σT2 is the variance of the total read-out noise. Pixel value [ADU]
2
For this work σD ≈ 0, due to that at 130 K the dark current is
− Fig. 11. Histogram of the pixels from the overscan section of the U amplifier,
less than 1e /pixel/day, and the CCD is properly shielded for two cases: when the whole CCD is read through the U-side (red curve)
against light [5]. and when only electronic noise is read (gray curve).
The CCD has two output stages, U and L. The serial register
is split in half, allowing each half of a row to be read-out from
one output. Another interesting possibility is to manipulate the VI. N OISE ADDED INSIDE THE CCD
horizontal clock signals to read the whole CCD using only one Each block of Fig. 9 adds noise to the signal. The first
output stage. For example, if the horizontal signals are clocked source of noise is inside the CCD: it is the noise σM SF
to read the CCD through the L-side, the reset and summing from the MSF transistor of the CCD output stage. The MSF
well gates of the U-side can be clocked and the obtained output introduces thermal noise and flicker noise. It can be proved
signal will be only affected by the electronic read-out noise that for a long channel device working in saturation, like MSF,
2
σR . the thermal noise can be modeled as a current source between
Fig. 10 shows the result of measuring σR 2
for both sides with the drain and source terminal with spectral density given by
different integration time of the CDS. The gain of the system equation 8 [16]. The MSF also introduces flicker noise due
was calibrated with a x-ray source [3]. As will be shown in to fluctuations of the carrier mobility and of a traping and
the next section, the bump between 20 µs and 35 µs, and the detraping mechanism of carriers near the oxide interface [16].
high noise below 20 µs, are due to the switching frequencies Like the thermal noise, this last noise can be modeled as a
of the power supplies. current source between drain and source with spectral density
Fig. 11 shows the histogram of the pixels in the overscan given by equation 9. The flicker noise decreases with the area
section at an integration time of 20 µs, for two cases: when of the transistor W L and with the oxide capacitance Cox .
the whole CCD is read through the U-side and when only
2 = 4k T 2 gm
Ith (8)
electronic noise is read from that side. The noise goes up from B
3
1.33 e− to 1.96 e− , meaning the spurious charge generated
when the horizontal phases are clocked is of about 1.46 e− . gm2 K 1
2
I1/f = (9)
There are methods to reduce the spurious charge [3]. Cox W L f
CGS,MSF
VOUT 5
input Ith I1/f IRL SC CDS input
CT RL CL
SC AMP input
20K
Q 15pF 4 SC BUFFER input
gm*VGS,MSF
CCD
NOISE [electrons]
3
Fig. 12. Small signal model of the CCD output circuit that includes the noise
sources of MSF. The are two current sources, one to model the thermal noise
2
(Ith), the other the flicker noise (I1/f)
TABLE I 1
M EASURED NOISE AT DIFFERENT POINTS OF THE READOUT CHAIN . T HE
NOISE INTRODUCED
√ BY MSF CAN BE CALCULATED BY
1.332 e− − 0.872 e− = 1.00e− 0
10 15 20 25 30 35 40
Integration Time [µs]
Noise (T=20µs)
SC@ DAQ input 0.28e− Fig. 13. CDS output at different integration times for: a short circuit (SC)
SC@ Amp input 0.84e− at the input of the CDS of the Monsoon sytem, a SC at the input of the
SC@ Buffer input 0.87e− amplifier, a SC at the input of the buffer and for the full chain.
CCD 1.33e−
−5
10
Fig. 12 shows the small signal model of the output stage in SMPS
which the MSF noise current sources have been included with LMPS
also the thermal noise due to the resistor RL . The frequencies

of interest are below 1 MHz [17], hence the CGS,M SF can be 10
−6
2
[V/Hz0.5]
considered an open circuit. The total noise voltage Vnout can
be calculated and is given in equation 10.
gm2 K 1 2

2 2 1 RL 10
−7
Vnout = 4kB T gm + +
3 RL Cox W L f ω 2 CL2 RL 2 +1
(10)
The second noise source σJF ET is added by the JFET 0 20 40 60 80 100 120
Frecuency [KHz]
buffer. The next one σA is added by the amplifier, and the
last source σDAQ added by the DAQ in the analog circuit that Fig. 14. Power spectrum of the amplifier output signal at two situations: with
performs the CDS and the ADC of the Monsoon system. Other the Monsoon supplied with LMPS and with SMPS.
source of noise σCLK is introduced to the CCD through the
capacitive coupling between the clock phases and the SN. To
determine the amount of noise that is added by MSF, a short the most powerful peak at 50 kHz is totally removed. The
circuit (SC) was made at the input of each stage, and the noise effect on the output of the CDS at different integration time
after the CDS was measured at different integration times. Fig. can be seen in Fig. 10. For an integration time of 20 µs, the
13 shows the result and table I gives the noise values obtained frecuency response of the CDS is zero at 50 kHz [17] and
for an integration time of 20 µs. the SMPS frecuency peak is totally removed. For this reason,
To estimate the noise introduced by the MSF, the 0.87 e− at 20 µs the output noise when the system is supplied with
noise obtained with the input of the buffer in short circuit must LMPS or SMPS is the same as can be seen in Fig. 15. The
be subtracted in quadrature to the noise of 1.33 e− obtained noise of the SMPS is introduced in the system by the supplies
with the full chain. This results in 1.00 e− of noise introduced of the operational amplifier that perform the CDS and drives
by the MSF. This value is the result of filtering the spectrum the clock signals for the CCD.
of equation 10 by the CDS [17].
The actual configuration of the system has a noise floor VII. C ONCLUSION
of 0.87 e− . To get a read-out noise below 1.00 e− with this In this work the factor that governs the signal gain in
CCD technology, it is necesary to improve the external read- a CCD was shown. The CCD internal parasitic capacitance
out electronics. must be reduced in order to increase the signal, and this
The switching mode power supplies (SMPS) of the Mon- constitutes an open issue in the design of new CCDs. The
soon generates undesirable frequencies that affect the read- CCD output signal is degraded by noise introduced inside the
out noise. Fig. 14 shows the power spectrum of the output CCD and by the external read-out electronics. In this work
amplifier signal when the CCD is exposed in two different a method to measure only the electronic read-out noise and
situations, when the Monsoon system is supplied by SMPS and spurious charge noise has been introduced. With this method
linear mode power supplies (LMPS). With LMPS frecuency is was possible to estimate the noise introduced by the output
peaks between 40 kHz and 60 kHz are removed. In particular MOSFET transistor of the CCD. It was found to be 1.00 e− .
[10] Haque, S., et al. “Design of low-noise output amplifiers for p-channel
7 charge-coupled devices fabricated on high-resistivity silicon,” IS&T/SPIE
SMPS
Electronic Imaging, International Society for Optics and Photonics, 2012.
LMPS
6 [11] White, Marvin H., et al. “Characterization of surface channel CCD
image arrays at low light levels,” IEEE Journal of Solid-State Circuits,
NOISE [electrons]
vol. 9, no. 1, pp. 1-12, 1974.

5 [12] Shaw, Theresa, et al. “System architecture of the Dark Energy Survey
Camera readout electronics.” SPIE Astronomical Telescopes+ Instrumen-
4 tation, International Society for Optics and Photonics, 2010.
[13] Aguilar-Arevalo, A., et al. “Measurement of radioactive contamination
in the high-resistivity silicon CCDs of the DAMIC experiment,” Journal
3
of Instrumentation, vol. 10 no. 08, 2015.
[14] Zhang, Wen W., and Qian Chen. “Optimum signal-to-noise ratio perfor-
2 mance of electron multiplying charge coupled devices.” World Academy
of Science, Engineering and Technology, vol. 54, pp. 264-268, 2009.
[15] Wei, Mingzhi, and Richard J. Stover. “Characterization and optimization
1
5 10 15 20 25 30 35 40 of MIT Lincoln Laboratories CCID20 CCDs,” Astronomical Telescopes
Integration Time [µs] & Instrumentation, International Society for Optics and Photonics, 1998.
[16] B. Razavi, “Design of Analog CMOS Integrated Circuits”, McGraw-
Fig. 15. Electronic read-out noise for different integration times. The Hill, 2001.
Monsoon was supplied with LMPS, with less than 300 µVrms of ripple. [17] Cancelo, Gustavo Indalecio, et al. “Achieving sub electron noise in
The bump between 20 µs and 35 µs, and the noise below 20 µs, due to the CCD systems by means of digital filtering techniques that lower 1/f pixel
SMPS, was removed. The minimum noise is 1.29 e− at an integration time correlated noise,” Experimental Astronomy, vol 34, no. 1, pp. 12-29, 2012.
of 20 µs.
The external electronics adds a noise floor of 0.87 e− , and

must be improved if a lower read-out noise needs to be
achieved.
As was shown the CCD output signal is not only affected by
electronic readout noise. When packets of charge are shifted
pixel to pixel during the CCD read-out process, a spurious
charge is added as another source of noise. The spurious
charge contributes 1.43 e− to the noise level and must be
reduced if a noise level lower than 1.00 e− needs to be
achieved.
ACKNOWLEDGMENT
This work was done under grant PICT 2013-2128, PICT-
2014-1225 and with the BECAR-Fullbright program. Miguel
Sofo Haro, Guillermo Fernandez Moroni are supported by
CONICET, Juan Estrada, Gustavo Cancelo and Javier Tiff-
enberg by Fermilab, and Xavier Bertou by CNEA and CON-
ICET.
R EFERENCES
[1] Boyle, Willard S. “Nobel lecture: CCD an extension of mans view,”
Reviews of Modern Physics, vol 82, no. 3:2305, 2010.
[2] Smith, George E. “Nobel Lecture: The invention and early history of the
CCD,” Reviews of Modern Physics, vol 82, no. 3:2307 , 2010.
[3] Janesick, James R. “Scientific charge-coupled devices,” SPIE press, Vol.
117, 2001.
[4] Holland, Stephen E., et al. “Fully depleted, back-illuminated charge
coupled devices fabricated on high-resistivity silicon,” IEEE Transactions
on Electron Devices, vol. 50, no. 1, pp. 225-238, 2003.
[5] Chavarria, Alvaro E., et al. “Damic at Snolab,” Physics Procedia, vol.
61, pp. 21-33, 2015.
[6] Barreto, J., et al. “Direct search for low mass dark matter particles with
CCDs,” Physics Letters B, vol. 711, no. 3, pp. 264-269, 2012.
[7] Moroni, Guillermo Fernandez, et al. “Charge coupled devices for detec-
tion of coherent neutrino-nucleus scattering,” Physical Review D, vol. 91,
no. 7, 2015.
[8] Estrada, J., et al. “CCD testing and characterization for dark energy
survey,” SPIE Astronomical Telescopes+ Instrumentation, International
Society for Optics and Photonics, 2006.
[9] Estrada, Juan, et al. “Plasma effect in silicon charge coupled devices
(CCDs),” Nuclear Instruments and Methods in Physics Research Section
A: Accelerators, Spectrometers, Detectors and Associated Equipment, vol.
665, pp. 90-93, 2011.

Modelling Approach for Low-Frequency Strongly

Coupled Magnetic Resonance Wireless Power
Transfer System
Agustı́n Rodrı́guez-Esteva, Ma. Sofı́a Perez Casulo, Bruno Serra Laborde, Pablo Pérez-Nicoli, and Fernando Silveira
{arodriguez, maria.sofia.perez, bruno.eduardo.serra, pablop, silveira}@fing.edu.uy
Abstract—This work describes the characterization of a three

coil system presenting strongly coupled magnetic resonance
(SCMR) at low frequency. A theoretical model for the power
transmission efficiency between coils is studied, in order to
predict the system behaviour, for different positions of the
auxiliary coil placed in the middle of the transmission. The
best approach for determining each parameter that impacts
the performance (inductance, coupling coefficients and quality
factor) is found for this low-frequency system. The power transfer
efficiency of a typical two coil system is increased 270 times by
adding an optimized auxiliary coil in the middle. Theoretical Figure 1: Two and three coil SCMR system magnetic field
models and experimental measures are in good agreement.
Index Terms—SCMR, strongly coupled magnetic resonance,
three-coil-system, wireless power transfer, modeling the literature and numerical simulation are considered. The
results are applied for optimizing a 3 coil system, where the
I. I NTRODUCTION
optimal auxiliary coil was found for a given transmitter and
The applications of wireless power transfer (WPT) are receiver. Experimental results on this system are presented and
increasingly diverse such as electric vehicle battery charger, compared with the model predictions.
implantable medical devices, and RFID communications. This paper is organized as follows, Section II introduces the
Strongly Coupled Magnetic Resonance (SCMR) was pro- SCMR effect and its theoretical model. Section III describes
posed by a group of researchers from the MIT in 2007 [1]. the models that will be used to characterize the coils. These
This effect achieves a higher efficiency in a wireless power models are then used to find the optimal auxiliary coil in
transmission between coils without making major changes to section IV. Section V-B presents the efficiency experimental
the original circuits, just introducing passive resonant auxiliary results and section VI summarizes the main conclusions.
coils between the ends of the transmission.
Based on this principle, many papers have been published, II. SCMR
modelling and designing WPT systems. However, most of The SCMR effect was simulated (using CST Studio Suite
these papers are focused on high-frequency [2] (in the M Hz R [5]) in order to illustrate the principle proposed by [1].
range) or high-power [3] (in the hundreds of Watt range) Figure 1 shows the simulated magnetic field of two coils,
applications. The case of study in this paper will be a low both resonating at 134.2 kHz, where the left one is being
power system oriented to a low frequency RFID tag detection excited at this frequency. A current is induced in the right
application (134, 2 kHz). These kind of tags are used in cattle coil due to magnetic coupling. If a passive auxiliary coil
identification via radiofrequency and they can be characterized with the same resonant frequency is placed in the middle,
by their range of distance and power consumption. The SCMR it works as a relay increasing the magnetic field through
is proposed as an alternative to improve the efficiency of the the receiver, Fig. 1. An optimal auxiliary coil radius a2 and
transmission in order to enhance the reading distance of the an optimal intermediate position (D12 , D23 ) that maximize
RFID detectors. the transmission efficiency exist for a given transmitter and
A thorough analysis using actual tags and reader is done in receiver [6].
[4] showing how an auxiliary coil can be used to increase In the remaining of this section an analytic expression for
read distance. The values of coils quality factors and self the efficiency ηSystem of the system is obtained as a function
inductance were measured in [4]. This paper however, con- of coil parameters (intrinsic resistances R, self L and mutual
tributes by analysing the best approach for determining each M inductances). Then, in section III analytic expressions to
parameter that impacts the performance (inductance, coupling predict these coil parameters are found. These expressions are
coefficients and quality factor). Analytic models available in used in the parametric sweep done in section IV to find the

2 L2
k23 Q23 R3 RL
optimal auxiliary coil and in section V-B to validate the model Where RV 3 = L3
can be found using the
RL +Q23 R3
against measurements. transformer equations.
Figure 2 shows the equivalent circuit model of the three coil
link. The system is divided in three stages and the impedance Analogously the efficiency η1 can be calculated as the power
seen and efficiency between stages are studied in order to transfer to L2 (which is equal to the power dissipated in RV 2 )
obtain the overall efficiency. divided the total power dissipated in L1:
RV 2
η1 = (3)
RV 2 + R1
ω 2 k2 L L
1 2
Where RV 2 = R212 +RV 3 can be calculated in the same
manner that RV 3 was found, using the transformer equations.
Finally the efficiency of the complete system is:

Figure 2: Equivalent circuit
ηSystem = η1 .η2 .η3 (4)
The capacitor added in each subcircuit is for tuning the
resonance frequency of each stage to the desired frequency f . L
2 2 2
Each coil resonant frequency is set at f = 134.2kHz. The k23 L Q3 R3 RL
ω 2 k12
2
L1 L2 3
R2 +RV 3 RL +Q23 R3 Q23 R3
parasitic capacitances were neglected since they are orders of ηSystem =
magnitude lower than the discrete capacitors added.
ω 2 k 2 L1 L2
R1 + R212
2 L2
k23 L3 Q23 R3 RL RL + Q23 R3
+RV 3 R2 + RL +Q23 R3
The subcircuit containing L3 can be modeled as: (5)
M12 M23
Where k12 = √ and k23 = √ are both less than
L1 L2 L2 L3
1 because only part of the magnetic flux of the transmitting
coil goes through the receiving coil.
This equation is the same as the expression obtained using
reflected load theory (RLT) on [6].
Figure 3: Receiver equivalent subcircuit III. C OIL CHARACTERIZATION
In this section theoretical models for calculating the induc-
Where the quality factor, Q3 = ωL R3 , of the coil L3 was
3
tance and resistance of the coils are presented. The mutual
assumed to be Q3 >> 1. The L3 efficiency η3 , can be inductance was calculated using different models which are
calculated as the power dissipated in RL divided into the total going to be compared in order to select the one that provides
power dissipated in the subcircuit Q23 R3 and RL . the best fitting with the experimental values.
The coils L1 and L3 have the characteristics of an example
Q23 R3 RFID system. The load resistance on the L3 coil’s circuit is
η3 = (1)
Q23 R3 + RL RL = 10kΩ. Additionally, the distance between reader and tag
The equivalent circuit for the second stage is presented in is considered fixed at 15 cm to simulate a standard reading
Fig. 4, where Vs2 is the induced voltage on L2 and RV 3 the distance. The design of the auxiliary coil radius and distance
impedance seen in L2 from the subcircuit containing L3. to L3 are presented in section IV.
radius a (cm) wire d (mm) N (turns) m (layers)
Coil L1 6 0.2 45 1
Coil L2 Sec. (IV) 0.9 25 1
Coil L3 1.05 * 405 27
Table I: Coil characteristics (radius, wire diameter, number of

turns and layers) - * 4 twisted wires of 0,09mm
Figure 4: Subcircuits for L2 and L3 A. Mutual inductances

To characterize the three coil system, different approaches
Finally, the efficiency η2 can be calculated as the power were considered to calculate the mutual inductance between
transfer to L3 (which is equal to the power dissipated in RV 3 ) transmitter and auxiliary coils M12 and the mutual inductance
divided the total power dissipated in L2: between auxiliary and receiver coils M23 .
RV 3 • Weinstein approach [7]
η2 = (2) • Nagaoka first and second approach [8], [9]
R2 + RV 3

• Approximation given by Microchip AN710 [10]

• Software simulations using CST Studio Suite
R [5]. √ 1 1
The results of the different models for M12 and M23 are M = 4π rR [(1+8q1 −8q12 +1 )log −4] (6)
2(1 − 2q1 )2 q1
presented in Fig. 5 and 6 respectively.
l1
q1 = 2 + 2( l21 )5 + 15( l21 )9 + ...
1 = 32q13 − 40q14 + 48q15 − ...
√
1−√k
l1 = 1+ k
√
Rr
k =2∗ p 2
(R+r)2 +Dij
Where R and r are the radii of the coils and Dij the distance
between coils.
B. AC resistance and self-inductance

For theoretical modeling of the AC resistance the approach
of Ferreira [11] will be used:
γ ber(γ)bei0 (γ) − bei(γ)ber0 (γ)

Figure 5: Proposed theoretical models, CST simulation and RAC = RDC [ +
2 ber02 (γ) + bei02 (γ)
experimental results for M12 (Nagaoka 1st and 2nd approach
and Weinstein approach show approximately the same curve). ber2 (γ)ber0 (γ) + bei2 (γ)bei0 (γ)
−2π(2m − 1)2 ] (7)
ber2 (γ) + bei2 (γ)
Where m is the number of layers of the coil, ber, bei, ber0 ,
bei0 , ber2 and bei2 are the Kelvin functions and gamma is
equal to:
d
γ= √
δ 2
Where δ is the Skin Depth:
r
2
δ=
ωµσ
The self-inductance L for a single layer coil will be calcu-
lated using the following expression [12]:
(aN )2
L= µH (8)
Figure 6: Proposed theoretical models, CST simulation and 22.9a + 25.4l
experimental results for M23 . where a and l are the width and length of the coil in cm
and N the number of turns as shown in Fig. 7. This expression
In the case of the mutual inductance M12 between coils L1 will be used for the transmitter (L1) and auxiliary (L2) coils.
and L2 presented at Fig. 5, a good correspondence between the
experimental values and approaches of Nagaoka and Weinstein
is observed. In the case of M12 it is noted that the coils are not
within the hypothesis of one being much larger than the other
coil used in the expression given by Microchip’s AN710.
Nagaoka’s 1st expression is a good approximation for M23
while Weinstein’s approach underestimates the value of M23
at greater distances than 4 cm while Nagaoka’s 2nd expression
overestimates it.
First approach of Nagaoka [9] (6), will be used for coils
because it presents the best fitting with the CST simulations
and with the experimental values for all the distances D23
considered. Figure 7: Coil dimensions

In the case of L3 which in the example system will

be a multiturn coil with rectangular section, the following
expression [13] will be used:
0, 31(aN )2
L= µH (9)
6a + 9h + 10b
With a, b and h in cm and N total number of turns as
shown in Fig. 8.
Figure 9: Auxiliary coil design chart with D13 = 15 cm
Figure 8: Multilayer coil dimensions
The experimental results, the CST simulations and the the-

oretical model values for AC resistances and self-inductances
for each coil are compared in Table II.
L (mH) RAC (Ω) Figure 10: Experimental set-up
Coil L1 theoretical 0.455 19.84
Coil L1 simulated 0.495 -
Coil L1 measured 0.499 17.90
Coil L2 theoretical 0.148 2.812 The main criterion for this design was that the centers of
Coil L2 simulated 0.133 -
the three coils should be on the same axis. The auxiliary coil
Coil L2 measured 0.130 2.766
Coil L3 theoretical 2.68 172.68 fixture was designed to be moved between the transmitter
Coil L3 simulated 2.72 - and receiver. The capacitors were manually tuned to fix the
Coil L3 measured 2.56 100.1 resonant frequency of each coil at 134.2 kHz and a class E
Table II: Comparison of the parameters for the system coils amplifier was implemented to drive L1.
B. Experimental measurements
IV. AUXILIARY C OIL D ESIGN
The efficiency of the two coil system L1-L3 (without L2
The transmission efficiency of the system presenting SCMR and with d13 = 15 cm) obtained experimentally was 0.037%.
was studied as a function of the dimensions and characteristics Regarding the efficiency of the three coil system (L1 −
of the auxiliary coil. To design the auxiliary coil, Fig. 9 plots L2 − L3), it was calculated in two ways. The first one,
the constant efficiency contours as a function of the auxiliary exclusively using the theoretical models Eqs. (5, 6, 7, 8, 9) for
coil position D23 and radius a2 . The efficiency is calculated the characterization of the coils. The second one, using only
using the expression (5) and the theoretical models (6, 7, 8, the theoretical model for the efficiency (5) with resistances,
9). self and mutual inductances experimentally measured. Figure
The radius a2 = 6.5 cm shows the maximum efficiency of 11 shows also the experimental values for the efficiency of the
the system and was used to build the auxiliary coil. Addition- whole system with D13 = 15 cm.
ally, the optimal auxiliary coil position for D13 = 15 cm is The maximum deviation between experimental and theoret-
D23 = 2 cm. ically calculated values was observed for D23 = 2 cm. It was
V. E FFICIENCY MEASUREMENTS proposed that for this distance the hypothesis of independence
for values of L and RAC in terms of the proximity of the
A. Experimental set-up other windings is not valid. This was studied using an Agilent
It was necessary to build an experimental set-up in order 4395 network analyzer with the auxiliary coil near the receiver.
to evaluate the proposed model and study the experimental For D23 = 2 cm it was obtained that the resonant frequency
efficiency of the system. The set-up was made of acrylic and varies approximately 600Hz. The efficiency for a system with
wood in order to affect as little as possible the magnetic field this frequency shift in the resonance frequency (600Hz) was
of the coils. simulated in Spice (using the model presented in Fig. 2)

[6] M. Kiani and M. Ghovanloo, “The Circuit Theory Behind Coupled-

Mode Magnetic Resonance-Based Wireless Power Transmission,” Cir-
cuits and Systems I: Regular Papers, IEEE Transactions, vol. 59, no. 9,
pp. 2065–2074, 2012.
[7] E. B. Rosa, Revision of the formulae of Weinstein and Stefan for the
mutual inductance of coaxial coils. U.S. Dept. of Commerce and Labor,
Bureau of Standards, 1906.
[8] J. Agbinya, Ed., Wireless Power Transfer. River Publishers, 2012.
[9] H. Nagaoka, “Note on the Mutual Inductance of Two Coaxial Circular
Currents,” Proceedings of the Physical Society of London, vol. 25, no. 1,
pp. 31–34, 1912.
[10] Y. Lee and M. T. Inc, “Antenna Circuit Design for RFID Applications,”
Application Note 710, 2003.
[11] J. A. Ferreira, “Improved Analytical Modeling of Conductive Losses
in Magnetic Components,” IEEE Transactions on Power Electronics,
vol. 9, no. 1, 1 1994.
[12] E. B. Rosa and L. Cohen, Formulae and tables for the calculation of
mutual and self-inductance, Bureau of Standards, 1907.
[13] I. A. Johnson, Principles of Inductive Near Field Communications for
the Internet of Things. River Publishers, 2011.
Figure 11: Three coils system’s efficiency
obtaining 11%. This presents a better fit with the experimental

value of 10%.
Finally, the results of system efficiency for two and three
coils were compared, showing a significant improvement of the
three coils with an efficiency 270 times higher at D23 = 2 cm
and D13 = 15 cm.
VI. C ONCLUSIONS
A system presenting SCMR was fully modeled, optimized,
fabricated and measured. In particular the case of a low
frequency RFID system with a distance from transmitter to
receiver D13 = 15 cm was studied. For the typical two-coil
system, an efficiency of 0.037% was obtained. The optimal
intermediate coil was then placed at a distance D23 = 2 cm
(D13 = 15 cm) increasing the efficiency to 10%. Therefore,
the efficiency for this system increased 270 times by placing
a passive intermediate winding 2 cm away from the receiver.
Additionally, experimental results are presented and com-
pared with the model predictions showing good agreement.
Therefore, the mathematical models used to describe the char-
acteristics of the coils and the system were adequate, allowing
the proper selection of the dimensions for the auxiliary coil.
R EFERENCES
[1] A. Kurs, A. Karalis, R. Moffatt, J. D. Joannopoulos, P. Fisher, and
M. Soljacic, “Wireless Power Transfer via Strongly Coupled Magnetic
Resonances,” Science, pp. 83–86, 2007.
[2] C. Chih-Jung, C. Tah-Hsiung, L. Chih-Lung, and J. Zeui-Chown, “A
Study of Loosely Coupled Coils for Wireless Power Transfer,” IEEE
Transactions on circuits and systems, vol. 57, no. 7, 2010.
[3] L. Seung-Hwan and R. D. Lorenz, “Development and Validation of
Model for 95%-Efficiency 220-W Wireless Power Transfer Over a 30-
cm Air Gap,” IEEE Transactions on industry applications, vol. 47, no. 6,
2011.
[4] P. Perez-Nicoli, A. Rodriguez-Esteva, and F. Silveira, “Bidirectional
Analysis and Design of RFID Using an Additional Resonant Coil to
Enhance Read Range,” 2016.
[5] Computer Simulation Technology. [Online]. Available:
https://www.cst.com

COTS CMOS Active Pixel Sensors Damage After

Alpha, Thermal Neutron, and Gamma Irradiation
Fabricio Alcalde Bessia, Martin Perez, Iván Sidelnik, Miguel Sofo Haro, J. Jerónimo Blostein,
Mariano Gómez Berisso, Julio Marin, and José Lipovetzky, Member, IEEE
Abstract—This work compares the damage produced by alpha several defective pixels have values higher than the average,
particles, thermal neutrons and gamma photons to Commercial- even higher than this threshold. This response of a sensor
Off-The-Shelf CMOS image sensors. Image sensors were exposed not being exposed to radiation is called Fixed Pattern Noise
to alpha particles from the decay of Uranium and Americium
sources which caused permanent damage to pixels immediately (FPN). Pixels with high values due to FPN might be mistaken
after a particle hit. Similar failure mode was seen when sensors as events produced by particles interaction, leading to false
were exposed to thermal neutrons in the Neutron Imaging Facility positive counts. To mitigate this problem our group proposed
of the RA-6 Nuclear research reactor, whereas no damage was a method to use these image sensors with a negligible false
seen after exposure to 137 Cs gamma rays. Due to the similarity count rate, using an auto-regressive filter to remove FPN [7].
between alpha and thermal neutron effects, and since silicon
transmutation by neutron capture is very unlikely, we conclude Using this FPN cancellation technique the sensors showed
that the Boron-Phosphorous Silicate Glass (BPSG) on top of the dose resolutions of tens to hundreds of nanoSieverts [6], [7].
silicon acts as a conversion layer producing charged particles Finally, the use of MAPS or CCD sensors for the detection
which in turn cause damage to the sensor. of thermal neutrons is possible by placing a conversion layer
Index Terms—Active pixel sensors, Alpha particles, CMOS on top of the sensor. Neutron capture in this layer produces
image sensors, CMOS technology, Ionizing radiation, Gamma- secondary particles which are detected by the sensor and are
rays, Neutron radiation effects directly correlated to the arrival of thermal neutrons. This is
also of interest in applications such as Boron Neutron Capture
I. I NTRODUCTION Therapy (BNCT) for cancer or neutron imaging [8], [9].
C MOS image sensors are used in a wide range of appli-

cations in consumer electronics as cell phones, portable
or security cameras, medical applications, among others [1].
B. Ionizing radiation effects on MAPS
However, the effects on the sensor of the ionizing radiation
Performance improvement in power consumption, miniaturiza- that one wants to detect should be taken in account. Two main
tion, cost, and speed thanks to scaling; and the possibility of effects were reported, Total Ionizing Dose (TID) effects and
integrating in the same silicon chip the pixels array, analog Displacement Damage Effects (DDE) [10]. Total ionizing dose
processing stages, ADCs and control electronics; allowed the responses cause an almost uniform increase in dark current in
realization of camera-on-chip systems [1] which can even the sensors [10]. This increase in dark current is caused by the
include on-chip image processing [2]. generation of interface traps in the Si-SiO2 interface and the
Recently, several works have dealt with the detection of creation of leakage paths between diffusions. It was reported
ionizing particles showing that Commercial-Off-The-Shelf that COTS sensors can survive gamma doses higher than 1 kGy
(COTS) CMOS image sensors have a good performance in [10].
interventional radiology dosimetry [3], [4], low dose dosimetry On the other hand, irradiation with heavy ions or high
[5], [6], and particle identification [7]. energy neutrons generates the displacement of Si atoms from
their position in the lattice, which behave as Shockley Reed
Hall (SHR) generation centers in the bulk of the sensor [10].
A. Monolithic Active Pixel Sensors These centers provide charge which can be collected in the
CMOS image sensors used for ionizing radiation detection reversed-biased junctions of the pixels, leading to an increase
are called Monolithic Active Pixel Sensors (MAPS). When in the dark current which has a high non-uniformity. Many
a particle hits the sensor, charge is generated in a cluster works [11], [12] have dealt with this effect important in space
of pixels of the image sensor. The image is acquired, and applications—see [10] for a review. On the other hand irradia-
if a cluster of pixels has values greater than a threshold, a tion with 1 MeV equivalent high energy neutrons with fluences
system based on these sensors determines that a particle was of 1011 n/cm2 shows an increase in dark current attributed
detected. Usually, in a sensor not exposed to light or particles, to displacement damage caused by the direct interaction of
neutrons with silicon [13].
Fabricio Alcalde Bessia <falcalde@ib.edu.ar>, José Lipovetzky <jose.
lipovetzky@ieee.org>, Iván Sidelnik, Miguel Sofo Haro, J. Jerónimo The effects of thermal neutrons on a CMOS image sensor
Blostein, Mariano Gómez Berisso and Martin Perez <mperez@ib.edu.ar> were—to our knowledge—never systematically investigated.
are with Balseiro Institute, Bariloche Atomic Center and CONICET. Also Since these sensors can be used with conversion layers for
Jose Lipovetzky and Julio Marı́n are with CNEA.
This work was supported with grant PICT 2011-0534, PICT 2012-0770, thermal neutron detection [8], [9], [14], [15], these effects are
PICT 2014-1969 and PIP CONICET 112201100552. of importance.
B) C)
A)
Fig. 1. Experimental setup with alpha sources. The CMOS sensor is behind
the Uranium alpha source.
This work studies the effects of thermal neutron irradiation

on a COTS CMOS sensor, comparing the damage with gamma
and alpha particle irradiation. Fig. 2. Typical damage produced by alpha particles of 235 U source. 16 pixel
values of a 4 by 4 matrix are shown as a function of observed frame number.
Inset A shows the image before particle hit, B shows the frame in which
II. E VALUATION OF DAMAGE CAUSED BY DIFFERENT interaction took place and C shows the resulting image after damage.
PARTICLES
COTS CMOS sensors were irradiated with alpha particles, event took place, and finally one after the event showing the
gamma rays and a mixed field of thermal neutrons and gamma damaged pixels. The plot is shown for the Uranium source, but
rays in order to compare the damage caused by each particle. the same happens with Americium. This kind of damage was
The image sensor used was the APTINA CMOS color image typical of alpha particles released by the radioactive sources
sensor model MT9V011, with a size of 0.25 inches, 640 x in these experiments.
480 pixels with pixel pitch of 5.6 µm x 5.6 µm. The color
sensor has a color Bayer filter covering the sensitive area.
More information about this sensor can be found in [6] and B. Neutron irradiation
[7]. For each of the experiments, only one sensor was exposed Two CMOS cameras were irradiated in the Neutron Imaging
to the ionizing radiation at a time. Facility of the RA-6 nuclear research reactor1 . The facility
beam is composed by a neutron flux and gamma rays generated
in the reactor core and passing through a Sapphire filter. There
A. Alpha particle irradiation
is a thermal neutron flux of 107 n(cm2 s)−1 and a gamma
One CMOS sensor was exposed to alpha particles from the dose rate of 800 mGy.h−1 . The experiment consisted in the
decay of 235 U and another to alpha particles coming from an exposure of one CMOS sensor covered with a Gadolinium
241
Am source. The experimental arrangement can be seen in layer of 150µm of thickness and another sensor without this
figure 1, where, in that case, a small Uranium source lays on layer. Gadolinium has a very high absorption cross-section in
top of the sensor. The whole set, the camera and the source, the thermal neutron energy range, and acts as a blocking layer,
was placed in a sealed box in order to isolate the sensor from not allowing thermal neutrons to reach the device [16]. In this
ambient light. Alpha particles from 235 U and 241 Am sources way, the sensor without Gadolinium was exposed to gamma
have energies of 4.7 MeV and 5.5 MeV, respectively, but the and thermal neutrons directly from the beam, and the other
energy of the particles arriving to the sensor is spread to lower sensor was exposed only to gamma rays, since the thickness
energies due to attenuation in the source and in air. of the Gadolinium layer is enough to stop thermal neutrons
The cameras were exposed to the sources while recording but is almost transparent to gamma rays.
at the same time their video outputs. The analysis of the A mixture of SU-8 photo-lithography resin and Gadolinium
video shows the interaction of the alpha particles with the Oxide in a powder form was prepared and applied to the sensor
silicon as bright spots in the image and those interactions over the whole die as shown in figure 3.
are called events. Each event is the consequence of energy Both cameras were placed inside an aluminum box, in order
deposited by an alpha particle and may produce damage to the to avoid any light coming from outside, the box was placed
sensor by atom displacement or by leaving charges trapped in in the neutron radiography facility and both cameras were
SiO2 . In any case, damage can be seen in the output image irradiated at the same time while recording two video files
as bright pixels—with values higher than the average—that from their outputs.
remain illuminated in every frame after the event. Figure
2 shows a typical damage produced by an Uranium alpha 1 RA-6 research reactor is placed in San Carlos de Bariloche city and is
particle. Pixel values were plotted as a function of frame operated by the Argentine Atomic Energy Commission (CNEA). The purpose
of this reactor is to carry out teaching, training, research and development
number and also three images of the event are displayed, one tasks in the field of nuclear engineering. It is an extremely versatile reactor,
before the interaction, one of the exact frame in which the useful for a wide range of experiments.

B) C)
A)
Fig. 4. The values of a 4 by 4 pixel matrix, i.e. 16 adjacent pixels, are shown
versus time and also three samples of how those pixels look like in the video.
Image A shows the pixels before particle hit, B shows the frame in which
interaction takes place, and C shows the resulting damage.
Fig. 3. Top: Neutron Imaging Facility at RA-6 Nuclear Research reactor.

Bottom left: CMOS sensors prepared without (left) and with Gadolinium
(right). Bottom right: Aluminum box with cameras inside placed in the neutron
imaging facility and ready for irradiation.
After 10 minutes of irradiation, the video recorded with

the Gadolinium covered sensor showed that this device was
clearly less damaged than the other. Moreover, after 2 hours
and a half, the sensor not covered began to malfunction and
stopped working a few minutes later, whereas the Gd covered
sensor continued working for five hours, the duration of the
experiment.
As was done in the alpha irradiation section, in figure 4 a
typical behavior of a group of pixels after damage is shown by Fig. 5. Experimental setup with the 137 Cs source. The sensor was inside the
plotting the values of the pixels in a 4 by 4 cluster as a function gray aluminum box at 29 cm of the source.
of frame number. Before the particle interaction, pixels have
low values with relatively low noise. The interaction of the
particle with the semiconductor produces free carriers that layer is called Boron-Phosphorous Silicate Glass (BPSG), and
discharge the pixels in the neighboring area. During the frame due to the Boron doping it is highly likely the interaction with
in which the interaction takes place, those pixels are shown thermal neutrons and the release of alpha and 7 Li particles as
as a very bright spot in the image because of their very reaction products. Those particles could damage the sensor in
high values. If any damage is produced by the particle to the same way as the Uranium and Americium sources of the
those pixels, by atom displacement or by charges trapped previous section.
in oxide layers, then a leakage current appears and after the
reset cycle that leakage current discharges the photodiodes and C. Gamma irradiation
those pixels stay illuminated in the image. The leakage current In another experiment one sensor was exposed to gamma
continue affecting those pixels for the next frames and this is radiation from a 137 Cs calibration source as shown in figure
seen as a sudden change in the pixels mean values after the 5. 137 Cs decay by beta emission to 137 Bam which remains in
particle hit, as shown in the figure. Also an increase in pixel a excited state and emits a gamma photon of 662 keV in the
noise is typically seen. transition to its ground state.
Comparing figures 2 and 4 it is easy to see that they are very The distance from the sensor to the source was 29 cm and,
similar. Since thermal neutron interaction with silicon has low at that distance, a gamma dose rate of 20 mGy/h (air) was
probability, due to its low absorption cross-section, it is not measured using a calibrated proportional counter. The CMOS
possible that the damage had been caused by thermal neutrons. camera was irradiated continuously for a period of 113hs,
On the other hand, there is a SiO2 layer on top of the active while recording two videos from its output. One video was
region of the imager doped with Boron and Phosphorous. That recorded in real time grabbing all the frames produced by the
sensor but only of a 64 by 64 matrix in the center of the

image. That was done in order to reduce the amount of data
recorded. The second video was taken at full resolution, 640 Pixel value
Short Filt er
by 480 pixels, but recording one frame every 60 seconds, again Long Filt er
in order to reduce the file size. 150
The experiment resulted in a total dose of 2.2 Gy (air)

received by the sensor. The analysis of the recorded videos
Pixel Value
showed an event rate of 49 events every 1000 frames while 100
no damage was observed to the sensor. Also the average dark
signal, i.e. the mean value of all pixels in the image throughout
the video, maintained its value and no raise of the background 50
noise was observed.
Threshold Damage
Detected
III. D ETECTION OF DAMAGED PIXELS 0
2400 2500 2600 2700 2800 2900 3000 3100
Fram e #
In order to detect the kind of damage showed in figures 2
and 4 an algorithm was written using Python and OpenCV. The
idea was to analyze the videos taken in the Neutron Imaging Fig. 6. Pixel damage is detected by looking at the difference of two filters,
with short and long time constants. When damage is detected, a reset of the
Facility and with Americium and Uranium sources, and look long filter is performed in order to avoid counting again the same pixel.
for sudden changes in the mean value of each pixel. Two
temporal running average filters are applied to the video for
each pixel, one with a long time constant and the other with by thermal neutrons, or by their interaction with the BPSG
a short time constant. The objective of these filters is first to layer.
remove noise and events produced by particle hits, and second The algorithm counted zero damaged pixels for the gamma
to track the mean value of each pixel. In the case that an event irradiation of section II-C. It is worth noticing that the gamma
produces any damage to one or more pixels, like in figure 4, dose received by the sensor in this case was the same as in
the short filter changes more rapidly than the other as shown the Neutron Imaging Facility, approximately 2 Gy, although
in figure 6 for one pixel. So by comparing the results of the the gamma ray energies involved were different.
two running average filters and looking for a difference of
more than a certain threshold, it is possible to detect damaged IV. D ISCUSSION AND C ONCLUSIONS
pixels. Commercial CMOS image sensors were exposed to three
When damage is detected on a pixel, the long time constant kinds of ionizing radiation: alpha particles, thermal neutrons
filter is updated to the pixel current value in order to avoid and gamma photons. The failure mode caused by thermal
counting the same pixel more than once. neutrons seems to be very similar to the damage caused by
As already said, one of the objective of the filter is to alpha particles. Also, it was totally different to total ionizing
eliminate pixel noise and also high peaks due to particle dose damage caused by gamma photons, as was reported
events, which always have a duration of one frame, so the in previous works [10]. Moreover, the damage was reduced
time constant of the short filter has to be chosen to comply considerably by adding the Gadolinium layer on top of the
with those objectives only. On the other hand, the long time sensor, as was seen in the experiment with a mixed beam
constant filter should be long enough to retain the mean value of thermal neutrons and gamma rays of section II-B. Also,
of one pixel after a sudden change when damage occurs. This since Gd have a very high thermal neutron absorption cross-
is done by using a time constant ten times greater for the long section, the reduction of damage can be attributed to less
filter than for the short filter. neutrons interacting with the sensor. The Gd layer attenuation
Using this algorithm an analysis of the damage produced of gamma rays in this experiment was negligible due to its
to the CMOS sensors exposed to alpha, neutrons and gamma small thickness and thus the damage reduction because of a
radiation was carried out by counting the number of damaged lower gamma ray intensity is not possible.
pixels per frame. In the case of the irradiation with alpha On the other hand, thermal neutron absorption cross-section
particles of section II-A a damage rate of 25 damaged pixels of silicon is very low, which makes very unlikely the damage
per 1000 frames—that is, at 25 frames per second, in 40 by silicon transmutation. Moreover, the failure modes caused
seconds—with the 235 U source and 34 damaged pixels/1000 by alpha particles and neutrons were very similar. That leads
frames with the 241 Am source. to think if there is another reaction, not directly neutrons
Applying the algorithm to the irradiation in the Neutron with silicon, but neutrons with something else. This reaction
Imaging Facility of section II-B resulted in a damage rate of produces charged particles similar to alphas and these particles
338 damaged pixels per thousand frames for the uncovered in turn produce the damage to the sensor. It is widely known
sensor and only 14 damaged pixels/1000 frames for the Gd [17] that the isolation layers in a chip are made of a Boron-
covered one. Thus the reduction in thermal neutron flux due Phosphorous Silicate Glass (BPSG). This layer could be
to absorption in the Gadolinium layer lead to a reduction of responsible of the damage to the pixels because the neutron-
the damage to the sensor, indicating that damage is produced Boron reaction products are alphas and 7 Li particles.
ACKNOWLEDGMENT
The authors would like to thank to the staff of the RA-6
Nuclear Research Reactor for their assistance during the
experiments.
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Simplified Model for Radiation Effects in

MOS Devices
L. Sambuco Salomone, and A. Faigón
Abstract—The spatial distribution of trapped holes in the gate Vt value.

oxide of MOS exposed to ionizing radiation plays a significant Different models have been proposed to reproduce the total
role in the dynamics of the threshold voltage shift with dose, ionizing dose (TID) effects in MOS devices, specially the Vt
specially when switched bias measurements are considered. In
this work, we analyze currently available simplified models shift with dose, with different levels of complexity. Several
stressing out their limitations when dealing with complex models that try to include the main physical processes from
measurements. Therefore, we present a simplified model based the electron-hole pair generation to hole trapping and
on the fitting of the evolution with dose of the spatial distribution neutralization are based in a set of equations which are solved
of trapped holes obtained from a physics-based numerical model. self-consistently by numerical methods [1]-[3]. The main
For that, a two-exponential expression was considered, with four problem with this kind of models is the computational cost,
fitting parameters. Then, the change with dose of these
parameters is considered. The effect the variation of the capture i.e. the time a computer is dedicated to solve the problem,
and neutralization rates has on the spatial distribution of trapped without considering the time dedicated by the researcher to
holes is analyzed to better understanding radiation effects in programming the model. To alleviate this, some
MOS devices and also to contribute to the development of simplifications are usually assumed reducing the complexity
simplified numerical models capable of reproducing complex level, such as a steady state condition for the electron and hole
dynamics. fluxes [4]-[9], or a simplified hole trap distribution [4], [7]-[9].
Index Terms— MOSFETs, radiation effects, dosimeters. Finally, there are also simple analytical equations that capture
the essential characteristics of ΔVt vs. dose curves [10]-[11].
I. INTRODUCTION Recently, we developed a physics-based numerical model
When a metal-oxide-semiconductor (MOS) device is and we applied it to fit the real-time radiation response of
subjected to ionizing radiation, as 60Co γ-rays, X-rays, protons, MOS dosimeters, showing that the spatial redistribution of
or any other source, electron-hole pairs are generated within trapped holes within the oxide plays a key role during
the gate oxide. After an initial recombination, which is switched bias irradiations [12]-[13]. As noticed in those
strongly electric field dependent, the remanent charge is works, to reproduce this effect, it is mandatory (i) to consider
drifted by electric fields. For a positive voltage applied to the the hole traps as actually they are spatially distributed, and (ii)
gate electrode, holes moves towards the substrate, while to solve the transient problem without steady-state
electrons move in the opposite direction. For usual oxide assumptions for electron and hole fluxes. Thus, the usual
thicknesses and applied electric fields, electrons leave the assumptions found in many TID models are not valid for this
oxide in a time not higher than some dozens of ps. However, kind of measurements.
holes in SiO2 have a much lower mobility than electrons In this work, we tried to contribute to the understanding of
(10-5 cm2V-1s-1 and 20 cm2V-1s-1, respectively), so that once all radiation effects on MOS devices and to the task of obtaining
the electrons are swept out the oxide, a moderate density of a simplified model, by fitting the evolution of the spatial
mobile holes remains there. Then, holes moving towards distribution of trapped holes during irradiation through a
substrate can be captured in structural defects before leaving simple two-exponential expression. This leads to four fitting
the oxide. This positive charge screens the external electric parameters which evolve with dose. The fitting procedure is
field, modifying the voltage at which the substrate channel is applied to the above mentioned experimental results on 70 nm
formed, known as threshold voltage (Vt). Additionally, if a MOS dosimeters, and both the exact and simplified models are
free electron is close enough to a filled hole trap there is a compared.
probability of neutralization, which can partially restores the
II. LIMITATIONS OF CURRENT SIMPLIFIED TID MODELS
This work has been supported in part by the Universidad de Buenos Aires Two main assumptions are usually found in the literature
with grant UBACYT Y064, by the Consejo Nacional de Investigaciones regarding TID models:
Científicas y Técnicas (CONICET), by the Agencia Nacional de Promoción
Científica y Tecnológica (ANPCyT) with grant PICT 2007-01907, by the o Free electrons and holes reach a steady state in a time
Instituto de Tecnologías y Ciencias de la Ingeniería (INTECIN).
Lucas Sambuco Salomone (lsambuco@fi.uba.ar), and Adrián Faigón
much lower than the duration of the irradiation.
(afaigon@fi.uba.ar) are with the Device Physics - Microelectronics o Hole traps can be considered to be located in a narrow
Laboratory, INTECIN, Facultad de Ingeniería, Universidad de Buenos Aires, region close to the Si/SiO2 interface.
Av. Paseo Colón 850, C1063ACV, Ciudad Autónoma de Buenos Aires,
Argentina. Adrián Faigón is also with the CONICET.

switch to a lower value VG = 2.3 V after approximately 500 s

(370 krad). During the inital stage, positive charge buildup
occurs, leading to a Vt shift towards more negative values.
After bias switches, a non-monotonic response is observed. As
explained in [12], the bias switch generates a potential well
which attracts electrons generated all over the oxide enhancing
the trapped holes neutralization far from the Si/SiO2 interface
for short times after switching. At the same time, holes
generated at the substrate side of the potential well moves
towards the substrate increasing the trapped holes density
close to the Si/SiO2 interface. Both processes compete each
other, and eventually, positive charge buildup dominates the
dynamics giving place to the turn-around observed
experimentally.
Taking into consideration the two assumptions mentioned
above, the first issue comes from the fact that the presence of
the potential well after switching causes the assumption of a
steady state for electron flux to be invalid, because the
Fig. 1. ΔVt vs. dose curves for an irradiation with VG = 5.5 V → 2.3 V in
70 nm MOS dosimeters. Symbols correspond to the experimental data, potential well leads to an accumulation of free electrons at the
whereas solid line is from the numerical model and dashed line is the best fit middle of the well, and those electrons that not recombine
when a simplified trapped holes distribution is assumed inmediately before with a trapped hole could not escape from the potential well.
switching. The inset shows the spatial distribution of trapped holes at the
switching time for the numerical (solid line) and simplified (dashed line) Now, we can also test the validity of a simplified trapped
models. holes distribution during the first stage at VG = 5.5 V. As
supposed in different works, we considered that trapped holes
Steady state condition for electron and hole fluxes are uniformly distributed from the Si/SiO2 interface up to a
implicitly considered that electric field is the main force distance xf, which is known as the “trapping region”. A simple
responsible for the carriers motion within the oxide. This is calculation shows that for the potential well to be present after
true if local electric field (modified by trapped holes) is high switching xf should be higher than 17 nm. Figure 1 shows
enough to neglect diffusion, which tries to move carriers in the experimental (symbols) and simulated (lines) ΔVt vs. dose
opposite direction. curves for this experiment. Solid line corresponds to our
On the other hand, the assumption that hole traps are numerical model [12], whereas dashed one is the best fit
located very close to the Si/SiO2 interface is based on several obtained after switching if a uniform distribution of trapped
studies that shown that after irradiation, holes are trapped holes is considered with xf slightly higher than 17 nm, to
close to this interface [14]-[16]. However, inferring that hole secure the presence of the potential well (the inset shows the
traps are located close to the interface based on the acquired distribution of trapped holes for each model). As shown, the
spatial distribution of trapped holes is not entirely reliable as sole presence of the potential well is not sufficient to fit the
shown in [12], where a uniform distribution of hole traps in a experimental result. Moreover, it is needed that both the
70 nm oxide leads to a trapped holes centroid around 6.5 nm magnitude of the trapped charge to be neutralized far from the
for high enough dose levels. Si/SiO2 interface and that of the charge to be trapped close to
Additionally, the Vt shift and the density of trapped holes the interface are high enough, which both are related with the
are related through the expression [17], potential well height. Thus, xf should be much higher than 17
tox nm to reproduce the response after switching, i.e., trapped
q
ΔVt = −
ε ox  p ( x ) (t
t ox − x ) dx (1) holes distribution should to get closer to that obtained from
0 our numerical model. Such a thick trapping region invalidates
where q is the elementary charge, εox is the SiO2 permitivity the uniform trapped holes distribution hypothesis.
(3.9ε0), pt is the density of trapped holes, x is the distance As a conclusion, the two main assumptions on which
referred to the Si/SiO2 interface and tox is the oxide thickness. simplified TID models are built are not valid for
Thus, it is clear that any spatial distribution which keeps measurements not so complex such as this considered.
constant the product pt(x)(tox-x) leads to the same ΔVt, so that III. EVOLUTION WITH DOSE OF THE SPATIAL DISTRIBUTION
it is not surprising that different models that assume simplified OF TRAPPED HOLES
trapped holes distributions are good enough to fit simple
Considering the problems described in section II, we think
measurements, like positive charge buildup under a constant
that to reach a simplified TID model capable to reproduce
positive bias.
complex experiments involving bias switching, it is mandatory
Let us now to consider a particular case (middle curve in
to study the spatial distribution of trapped holes during
Fig. 6 in [12]). It consists of an irradiation at a dose rate
irradiation.
Dr = 740 rad/s, with a positive bias VG = 5.5 V followed by a

Fig. 3. Experimental (symbols) and simulated (lines) ΔVt vs. dose curves
for positive charge buildup under different positive applied voltages.
Fig. 2. Spatial distribution of trapped holes for an irradiation at VG = 2.3 V

and tsim = 500 s (370 krad). Symbols corresponds to the exact model, whereas
solid lines are best fitting results with both two-exponential and single
  D 
pt 0 ( D ) = K pt 0 1 − exp  −   cm
−3
(3.1)
exponential models.
  D 
 pt 0  
Our approach consists in fitting the spatial distribution of   D 

xc ( D ) = K xc 1 + f xc exp  −  nm
 Dx  
trapped holes for different accumulated doses for positive bias (3.2)
irradiations using an expression as simple as possible. To do   c 
this, we propose the following trial expression   D 

α1 ( D ) = Kα1 1 − fα1 exp  −   nm
−1
(3.3)
 D
 pt 0 e −α1 x , x ≤ xc   α1   
pt ( x ) =  −α x −α ( x − x )
(2)
 pt 0 e 1 c e 2 c , x ≥ xc   D 
α 2 ( D ) = Kα2 1 − fα2 exp  −   nm
−1
(3.4)
 D
where it is clear that two regions are considered. From the   α2   
Si/SiO2 interface up to a critical distance (xc), pt(x) decreases
exponentially with a decay constant α1. Then, between xc and Figure 3 shows the simulated response of the same
the metal/SiO2 interface, pt(x) is given by another exponential dosimeters irradiated with a 60Co γ-ray source with a dose rate
with a different decay constant α2. As natural, the set of four of 740 rad/s at room temperature and different applied
parameters (pt0, xc, α1, α2) evolves with dose. For comparison, voltages. Further details about experimental conditions are in
Fig. 2 shows the spatial distribution of trapped holes for a [18]. A fair agreement between the exact (symbols) and two-
typical irradiation (it corresponds to a simulation time exponential (lines) models is achieved with a mean relative
tsim = 500 s for the applied bias VG = 2.3 V curve in Fig. 3) error around 5% for the three cases.
from the exact model (symbols), the two-exponential model fit Figure 4 shows the spatial distribution of trapped holes for
and a single exponential fit. As shown, a single decay constant the VG = 1.8 V case of Fig. 3 for different simulation times,
for all the oxide does not results in a good representation of i.e., accumulated doses. Symbols correspond to the spatial
the physical situation, so that a more complex expression like distribution obtained from the exact model, whereas lines are
our two-exponential one is required. the result of our two-exponential fitting model. As dose
The fitting procedure is as follows: From the simulations increases, the peak trapped holes density at Si/SiO2 interface
with the exact model, the spatial distributions of trapped holes increases and also the distribution becomes narrower, i.e., the
for different accumulated doses are acquired. Then, they are charge centroid moves towards substrate. As shown, the two-
fitted using our two-exponential model through the adjustment exponential model is able to well reproduce the spatial
of the four fitting parameters (pt0, xc, α1, α2) for each dose distribution of trapped holes for each dose level. For a high
level. Finally, the evolution with dose of each parameter is enough dose level, as for tsim = 5000 s in Fig. 3, trapped holes
fitted through the following simple analytical functions. distribution can be fitted using a single-exponential model.

Fig. 5. Evolution with dose of the model parameters for an applied bias
Fig. 4. Spatial distribution of trapped holes for an applied bias VG = 1.8 V VG = 1.8 V. Symbols are taken from the fitting of the spatial distribution of
from the exact (symbols) and simplified (lines) models, and different trapped holes for different dose levels, whereas lines are the best fit to these
simulations times (tsim). values.
Figure 5 shows the evolution with dose of the four fitting

parameters of the two-exponential model for the case
VG = 1.8 V. Symbols correspond to the values obtained by
fitting the spatial distribution of trapped holes at different dose
levels, whereas lines correspond to the fit of these values using
expressions (3.1)-(3.4). As shown, the density of trapped holes
at the Si/SiO2 interface monotonically increases with dose and
does not completely saturate for the time involved in the
experiment. The critical distance xc is slightly reduced with
dose from 20 nm to 10 nm. Both decay constant α1 and α2
increases with dose. This produces a displacement of the
charge centroid towards the Si/SiO2 interface, which is
observed in Fig. 4. For low and moderate dose levels, α2 > α1.
However, as dose increases, α1 approaches α2, which indicates
that the spatial distribution of trapped holes can be reproduced
with a single decay constant, as shown in Fig. 4 for
tsim = 5000 s. In this case, either xc or α2 is not properly
determined: if one take α1 = α2 then xc can take any value, or
alternatively, if xc = 70 nm then α2 does not play any role. Fig. 6. Spatial distribution of trapped holes from the exact (symbols) and
Finally, Fig. 6 shows that our two-exponential model is able simplified (lines) models for the experiment of Fig. 1.
to reproduce the spatial distribution of trapped holes even after
the bias switch of the experiment of Fig. 1. As shown, the
two-exponential model fits quite well the actual trapped holes
distribution. It is worthy to note that as a consequence of the
potential well presence, an increase in the trapped holes
density near the metal/SiO2 interface is also observed, because
holes generated at the metal side of the potential well are
drifted towards this contact. The simple expression we are
using to fit the trapped holes distribution does not reproduce
this phenomenon. However, the weight this charge has on ΔVt
is very lower than that of the charge close to the Si/SiO2
interface, as long as both are of the same magnitude, as in this
case.

neutralization (RN) rates, for the VG = 2.3 V curve in Fig. 3

when ΔVt = -10 V. The results are shown in Fig. 7, where the
trapped holes distribution from the numerical (symbols) and
simplified (lines) models are shown. Circles are from the best
fit to the experiment. The increase of the capture rate by an
order of magnitude (upwards triangles) results in lower values
for the peak density (pt0) and the first decay constant (α1),
shifting the charge centroid away from the interface. This
result has a clear physical origin: as capture rate increases,
more holes are captured on their travelling, impeding they
reach traps closer to the interface. The decrement of the
neutralization rate by an order of magnitude (downwards
triangles) and by three orders of magnitude (diamonds)
strongly affects the trapped holes distribution. As RN is
reduced both pt0 and α1 are reduced, shifting the charge
centroid away from the interface, as occurs when RC increases.
From a physical point of view, the neutralization of trapped
Fig. 7. Spatial distribution of trapped holes with capture (RC) and holes, which increases away from the interface due to the
neutralization (RN) rates as parameters for the experiment with VG = 2.3 V in density of free electrons, contributed to accelerates the process
Fig. 3 when ΔVt = -10 V. Symbols are from the numerical model, whereas
lines are the fit with the two-exponential model. Circles correspond to the best for which the trapped holes distribution becomes narrower as
fit of the experiment. dose increases. Thus, a decrement of the neutralization rate
implies a “slower” response. The same analysis was made for
ΔVt values of -15 V and -20 V showing the same pattern (not
IV. DISCUSSION
shown here for brevity).
From the results shown in the previous section we can Future work will be oriented to perform detailed
conclude that a two-exponential expression, based in four simulations varying all involved physical parameters, trying to
fitting parameters, is able to reproduce the spatial distribution correlate these ones with the obtained distribution of trapped
of trapped holes at a given dose during an irradiation holes, and hence the Vt value.
experiment. Even more, the fitting parameters evolution with
dose seems to be quite smooth and can be represented by V. SUMMARY AND CONCLUSIONS
single exponential expressions. However, two main issues are The limitations of simplified models for radiation effects in
worthy to be discussed. The first one is about the physical MOS devices were analyzed and the steady state assumption
origin of this particular shape when a positive bias is for carriers fluxes together with very simple trapped holes
considered. We can mention the following three physical distributions were identified as the main defects when these
processes that could lead to the two-exponential pattern: models are applied to switched bias irradiation experiments.
o Electric field increases the density of holes available Therefore, a new kind of simplified model was presented. The
for trapping towards the Si/SiO2 interface. main idea of the model consists in fitting the spatial
o Electric field increases the density of free electrons distribution of trapped holes, which was acquired from
available for neutralize a trapped hole towards the simulations with a physics-based numerical model, using a
metal/SiO2 interface. simple two exponential expression, based on four parameters,
o Trapped holes distorts the local electric field which evolve with the accumulated dose. A comparison with
enhancing the effective electron-hole pair generation experimental results on 70 nm MOS dosimeters showed that
towards the Si/SiO2 interface due to the fractional this simple expression fit quite well the trapped holes
yield dependence on electric field. distribution and also the threshold voltage shift with dose.
To better understand the physical origin of this particular
The second issue is about our goal to obtain a simplified trapped holes distribution and to finally develop a simplified
TID model without the problems current simplified models model capable to deal with complex measurements, some
have, as mentioned in section II. As previously shown, simulations were performed varying physical parameters like
equations (3.1) to (3.4) well approximate the evolution with capture and neutralization rates. The results showed each
dose of the four parameters of the two-exponential model. To parameter plays a specific role determining the spatial
obtain a predictive model it is neccesary to known how the distribution of trapped holes. Future work will be oriented to
parameters involved in these equations varied with physical perform many more simulations, trying to numerically
parameters like the applied bias and capture and neutralization correlate the variations of physical parameters with the
rates. Doing this, also the physical origin of the spatial trapped holes distribution.
distribution could be clarified. To make a first step in this
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Steady state characterization of current ripple in

DCM interleaved power converters
Paula Cervellini, Pablo Antoszczuk, Rogelio García Retegui, Marcos Funes and Daniel Carrica
ICYTE, UNMDP, CONICET, Juan B. Justo 4302, 7600 Mar del Plata, Argentina.
e-mail: {paulacervellini, pablo_ant, rgarcia, mfunes, carrica}@fi.mdp.edu.ar
Abstract—Power converters that operate in Discontinuous and estimating power losses in input and output DM filters,
Conduction Mode (DCM) are able to reduce switching losses, as well as a key performance indicator [7].
when compared to Continuous Conduction Mode (CCM) opera- Total ripple in CCM has been characterized in [8], for the
tion. This reduction is mainly due to zero current commutation
and the reduction of the reverse recovery losses. However, DCM case where the inductance value is the same in each phase,
operation in high power converters is limited due to the increment and generalized on [9] for any inductance ratio. These char-
in current ripple, which increases losses and volume in the acterizations have allowed to predict total ripple for the entire
differential mode (DM) filter. Multiphase DCM power converters duty cycle range, as a function of the system parameters. As
can reduce total ripple by dividing total current among N a consequence, amplitude, RMS value and harmonic content
phases and interleaving its ripples. Nevertheless, magnitude of
ripple reduction as a function of the system parameters has of total current ripple have been found.
not yet been completely determined. This information would On the other hand, DCM total current ripple has not been
be an important performance indicator and a useful tool for fully characterized. Available methodologies are not able to
aiding in the design of key converter features, such as the compute total ripple for the entire duty cycle range [6], or
number of phases and DM filter design, in order to meet total focus on a particular topology or number of phases [10],
ripple, losses or electromagnetic interference specifications. In
this sense, this paper proposes a methodology for the steady [11]. Therefore, said methods cannot be used to predict the
state characterization of input and output ripple in both buck current ripple characteristics for any N or input and output
and boost converters operating in DCM. Experimental tests on voltages. This lack of information makes difficult to select
a 4-phase buck converter validate the proposal. the optimal number of phases, and to design the DM filter
Index Terms—Multiphase power converters, discontinuous to meet total ripple, losses or electromagnetic interference
conduction mode (DCM), ripple, photovoltaic systems (PV).
(EMI) specifications, which has to be performed by evaluating
I. I NTRODUCTION particular cases [12], [13].
In this paper a methodology for the characterization of input
WITCHING power converters are extensively used in a
S wide range of applications, including photovoltaic (PV)
energy systems, Power Factor Correction (PFC) and Electrical
and output total ripple, in both buck and boost topologies,
for DCM operation, is presented. This methodology analyses
total ripple in the time domain for any number of phases and
Vehicles (EV) [1]–[3]. The efficiency achieved in these appli- the entire range of duty cycle. It also allows to obtain total
cations can be improved by operating in Discontinuous Con- ripple reduction pattern and location of cancellation points, as
duction Mode (DCM), which reduces the reverse recovery and a function of input voltage Vin , output voltage Vout and switch
hard switching losses found in Continuous Conduction Mode on time Ton . Experimental tests on a 4-phase buck converter
(CCM) [4]. However, DCM current ripple is as large as twice validate the proposal.
the mean inductor current, which increases losses and volume
of the differential mode (DM) filter in high power converters, II. P ROPOSED M ETHOD
and could therefore limit maximum converter power [5]. The proposed method characterizes the total input and
Multiphase DCM power converters allow to reduce the DM output current ripple either in boost (Fig. 1a) or buck (Fig. 1b)
noise, and therefore the requirements on the DM filters, by DCM interleaved power converters, based on the analysis of
interleaving 2π/N each phase current ripple [2], [6]. In this each phase ripple in the time domain.
condition, total ripple frequency is increased to N times the The analysis takes into consideration the following:
switching frequency fsw and its amplitude is decreased. • the power converter is operating in steady-state;
Knowledge of total ripple characteristic, as a function of the • the current is approximated by linear segments, as the
system parameters, could prove an important tool for designing time constant associated with the inductors and their
This work was supported in part by the Universidad Nacional de Mar resistive component is much higher than the switching
del Plata (UNMDP), Argentina, the Consejo Nacional de Investigaciones period [14];
Científicas y Tecnológicas (CONICET) project PIP 0210, Argentina, by • the phase errors among phases, with respect to the ideal
the Ministerio de Ciencia, Tecnología e Innovación Productiva (MINCYT),
Argentina, by the Agencia Nacional de Promoción Científica y Tecnológica phase shift ( 2π
N ), are small compared to the switching
(ANPCYT), Argentina. period [15], therefore they are neglected;

(a) Boost interleaved converter. (b) Buck interleaved converter.

Fig. 1: Interleaved power converters topology.
• all N phases have the same period T and the same turn
on time (Ton ).
Under these considerations, total current ripple is a wave- (a) Phase (rLk ) and total (IL ) inductor current ripples.
form composed by linear segments with different slope and
duration, which depend on N , Ton and phase current slopes.
Therefore, said ripple can be fully determined by locating the
instants in which the slope changes, defined as inflexion points,
and the total current value in these points. As an example,
Fig. 2a shows the phase inductor current ripple (rLk ) and total
inductor current ripple (IL ) for an N -phase interleaved power
converter operating in DCM. In this figure, three intervals
can be identified in each phase ripple, Tz (in which inductor
current is zero), Ton (where the switch is on) and finally Tf
(interval in which the switch is off and the current is still not
zero). Additionally and without prejudice to the generality,
Fig. 2b shows the output switch phase current ripple (rSk )
and total output switch current ripple for an N -phase boost
interleaved converter, defined as ISbs . In this case, current is
zero also for Ton interval. Switch current ripple in buck (ISbk )
converters is similar to boost one, but the zero current interval
(b) Phase (rSk ) and total (ISbs ) switching boost current ripple.
is during Tf instead of Ton .
Fig. 2: Phase and total current ripples
Initially, IL is characterized and then the same analysis
is performed for ISbs and ISbk . As it can be observed on
Fig. 2a, the inflexion points of IL (pLx ) agree with certain
instants of each phase current ripple. These instants in the be determined.
phase ripple are: tz (instant where current becomes zero),
ton (instant where current starts incrementing) and tf (instant tz (k + 1) = tz (k) + Tn
where current starts decrementing). The same occurs when tf (k + 1) = tf (k) + Tn
analyzing ISbs and ISbk , with the special consideration that ton (k + 1) = ton (k) + Tn (1)
its inflexion points agree only with tz and tf for boost and
with ton and tf for buck converters. This is due to the fact
In order to calculate said inflexion points, one phase has
that, for boost converters current is zero for Ton and for buck
to be assumed as a reference. If phase one is used for this
ones, current is zero for Tf .
purpose, the first three inflexion points are tz1 , tonN and tfk−2 ,
Since the time when all these particular points occur in each as shown in Fig. 2a. So as to compute the instants of interest,
phase can be analytically calculated, the inflexion points in IL this method has to contemplate the time intervals Tz , Ton and
can be precisely defined. As previously stated, there are three Tf included in a switching period as:
inflexion points in each phase so total current may have up
to 3N different inflexion points. Additionally, every point in tz1 = t1 = 0
each phase current is delayed Tn=T /N from the same point
tonN = t2 = t1 + y1 Tn − Tf
in the previous phase, as shown in (1). Therefore, using the
location of the first three inflexion points, the remaining can tfk−2 = t3 = t1 + y2 Tn − Tf − Ton (2)

where y1 is the top integer that results from Tf /Tn and y2 is Once fx is defined, (4) can be rewritten as:
the top integer that results from (Tf + Ton )/Tn , as:
pLx =A1 .fx + A2 .fx−3 + · · · + Ak .fx−3k+3
y1 = {y1 : y1 ∈ Z ∧ (Tf /Tn ) ∈ R ∧ + · · · + AN .fx−3N +3 , (7)
(y1 − 1) < (Tf /Tn ) < y1 } Generalizing the expression, the inflexion point for tx
y2 = {y2 : y2 ∈ Z ∧ [(Tf + Ton )/Tn ] ∈ R ∧ instant in IL is described as:
N
(y2 − 1) < [(Tf + Ton )/Tn ] < y2 } X
pLx = Ak .fz (8)
The resulting 3N−3 points are calculated as follows: k=1
where subindex z is calculated as:
tx = tx−3 + Tn x = 4, . . . , 3N. (3) (
x − 3k + 3 if x > 3k − 3
z= (9)
Once all 3N points are located, total inductor ripple for tx x − 3k + 3(N + 1) if x ≤ 3k − 3
instant (pLx ) can be computed as the sum of phase ripples
In (8), fz and Ak values must be determined. In order to
(rk ) in that instant.
calculate fz , intervals Tf and Tz are required. These values
pLx = rL1 (tx ) + · · · + rLk (tx ) + · · · + rLN (tx ) are calculated as a function of Ton and current ripple positive
N
and negative slopes (spk and snk , respectively) as:
=
X
rLk (tx ) (4) sp
Tf = Ton k
k=1 snk

spk
In order to obtain the values of rLk (tx ), a generic rep- Tz = T − Ton − Tf = T − Ton 1 +
snk
resentation of phase current ripples is proposed, based on
the periodicity of the system, as shown in Fig. 3. In this Ak = Ton spk (10)
representation, current ripple of a given phase is defined as Current ripple slopes as a function of phase inductance Lk ,
a normalized triangular piecewise function f (t), with period Vin and Vout are summarized on Table I.
T . Therefore it can be represented as a three section function:
one with zero current (Tz ), another with a positive slope (Ton ) TABLE I: S LOPE VALUES FOR T HE C ONVERTERS
and the last one with negative slope (Tf ). The minimum value
Boost Buck
it can reach is 0 and its maximum value is 1. In this sense, Vin Vin −Vout
spk
phase ripple is represented by weighting f (t) by its amplitude, Lk Lk
Vout −Vin Vin
as depicted on (5). The remaining phases are generated using snk Lk Lk
a Tn delayed version of f (t).
The presented method can be easily particularized to com-
rLk (t) = Ak f (t) (5) pute total switch current for boost (ISbs ) and buck (ISbk )
converters. As previously stated, phase switch current is zero
Since f (t) value is required only in the points of interest
during Ton interval for boost converters, and during Tf interval
(tx ), fx is defined by sampling f (t) in the instants calculated
for buck ones. Therefore, in order to use the presented method,
in (2) and (3), as shown in Fig. 3. Then, fx is computed as:
Ton in boost and Tf in buck are redefined as small arbitrary
time values that represent the rise and fall times (Toni and Tfi ,

0
 0 ≤ tx < Tz
respectively) associated with the switches and drivers delays.
fx = (tx − Tz ).Ton −1 Tz ≤ tx < Tz + Ton (6)
It is important to point out that, in order to avoid affecting the
(T − tx ).Tf −1 Tz + Ton ≤ tx < T


switching period, it is necessary to recalculate Tz using (10)
as follows:
Tzbs = T − Toni − Tf
Tzbk = T − Ton − Tfi (11)
where Tzbs and Tzbk are the boost and buck redefined Tz ,
respectively. Hence, fx (6) is modified accordingly to obtain
the piecewise functions gx (12) and hx (13) for boost and buck
converters, respectively, as shown in Fig. 4.

0
 0 ≤ tx < Tzbs
gx = (tx − Tzbs ).Toni −1 Tzbs ≤ tx < Tzbs + Toni
(T − tx ).Tf −1

Tzbs + Toni ≤ tx < T

Fig. 3: Function Ak f (t) and sampled version Ak fx . (12)

information could be used as a first approach for determining

the number of phases and the converter operating point.
∆ILn = max(pLx ) − min(pLx ) An −1

(16)
−1
∆ISn = max(pSx ) − min(pSx ) An (17)
where An is the nominal phase ripple amplitude. This ampli-

tude can be calculated as a function of the nominal inductance
value and the control parameter Ton , using (10) and the slopes
definition listed on Table I. Furthermore, as the maximum Ton
that prevents the converter from operating in CCM depends on
the operating point, a normalized Ton is defined as:

Ton Ton sp
Tonn = = 1+ (18)
Tmax T sn
Likewise, taking into consideration that the maximum turn
on time (Tmax ) also depends on the operating point and the
maximum value it could reach is the switching period, it is
normalized with regard to T as follows:
−1
Tmax sp
Tmaxn = = 1+ (19)
Fig. 4: g(t), phase shifted g(t) and sampled version gx . h(t), T sn
phase shifted h(t) and sampled version hx
Once normalization is made it is possible to compare ripple
attenuation for different operating points and topologies.
 For the case of IL , total ripple attenuation is illustrated
0
 0 ≤ tx < Tzbk
−1 on Fig. 6, which shows the resulting ∆ILn as a function
hx = (tx − Tzbk ).Ton Tzbk ≤ tx < Tzbk + Ton of Tonn and Tmaxn for a five-phase converter. From this
(T − tx ).Tfi −1

Tzbk + Ton ≤ tx < T

figure, it can be seen that ∆ILn is always smaller than
(13) the ripple of a single phase. Furthermore, there are certain
As an example, Fig. 5 shows each phase contribution to values of Tonn and Tmaxn that yield total ripple cancellation.
total input and output current in time instant t3 for a five- Additionally, it can be observed that these cancellation points
phase boost converter. In this case, the value of total current delimit the zone with larger attenuation. Therefore, knowledge
for instant t3 is computed as:
pL3 = A1 f3 + A2 f15 + A3 f12 + A4 f9 + A5 f6 (14)

pS3 = A1 g3 + A2 g15 + A3 g12 + A4 g9 + A5 g6 (15)
Total current is then obtained by similarly calculating the

remaining inflexion points in each tx . Once these points are
determined, they can be used to obtain useful information of
the DCM interleaved current ripple. This analysis is performed
on the following section.
III. R IPPLE ATTENUATION ANALYSIS
The proposed method can be used to compute any of

total ripple characteristics. Among them it can be included
the RMS value, harmonic content and total current ripple
attenuation. Ripple attenuation is defined as the ratio among
total current ripple amplitude and the current ripple amplitude
corresponding to a single phase, as shown in (16) and (17).
Total ripple attenuation is a useful performance indicator, as it
can be used to determine whether cancellation points exist
and the zones with larger ripple reduction. Therefore, this Fig. 5: Total inductor and switch current in t3 .

Fig. 8: Slope superposition examples for an N = 5 converter.
to determine Tonn and Tmaxn through (18) and (19). This

Fig. 6: ∆ILn as a function of Tonn and Tmaxn for N = 5. analysis is summarized in Table II, where the combinations
of Tonn and Tmaxn that yield total ripple cancellation for the
described superposition cases are shown.
of these points location provides important information on
ripple characteristics. TABLE II: S LOPE S UPERPOSITION E XAMPLES IN C ANCEL -
Cancellation points are better illustrated on Fig. 7, which LATION P OINTS F OR N=5
shows ripple attenuation as a function of Tmaxn , for several sp
Ton Tf Tonmax Tonn Tmaxn
Tonn . Selected Tonn are such values in which zeros on sn
1 T 2
∆ILn exist. For the particular case of Tonn = 1 the CCM 1sp 1sn Tn Tn 1 2
T N T
= 25 1
2
1 2 2T 3
case is obtained, identifying the known case of N −1 ripple 2sp 1sn 2Tn Tn 2 3
T N 2T
= 53 1
3
nulls. Conversely, when Tonn < 1, which correspond to DCM 1sp 2sn Tn 2Tn 2 1
3
T T
N
3
T
= 35 2
3
operation, there are additional ripple nulls.
In order to determine the location of these ∆ILn nulls,
From the aforementioned analysis it can be observed that
the previously mentioned five-phase converter is analyzed.
for three slopes superposition, two cancellation points with the
Through this analysis, a general expression for the location
same Tonn are possible. This is due to the fact that, although
of nulls is found as a function of N .
there are two different values for Ton , Ton and Tonmax change
For the nulls to exist it is essential to have negative and in the same proportion. Consequently, the Tonn values that
positive slopes superposition, with coincident inflexion points. bring out total ripple cancellation are obtained using:
Additionally, through (1), it can be determined that the inflex-
ion points coincidence implies that Ton and Tf intervals must i
be multiple of Tn . As an example, some of the superposition Tonc = i=2:N (20)
N
cases for the N = 5 converter are shown in Fig. 8.
Considering the case of two slopes superposition, in order where i represents the amount of overlapped slopes. Similarly,
to produce a cancellation point, Ton =Tf =Tn . Analogously, for the Tmaxn values that lead to ripple cancellation for the
the case of three slopes superposition there are two possible obtained Tonc points are computed as:
situations: Ton =Tf /2=Tn and Ton /2=Tf =Tn , as seen in Fig. 8. j
Knowing the relation between Ton and Tf (10), it is possible Tmaxc = j =1:i−1 (21)
i
with j representing all the possible combinations for a given
superposition case. For example, for the case of two slopes
superposition i = 2 and j = 1. For three slopes superposition
i = 3, which implies that j can take the values 1 or 2. Hence,
analyzing (20) and (21), it can be determined that there is a
total of N (N − 1)/2 cancellation points.
Related to ∆ISn , it should be pointed out that, as no super-
position of different sign slopes is possible, no nulls can exist.
Additionally, considering that each rSk has a discontinuity
from 0 to Ak , for the boost case, or from Ak to 0 in the buck
case, ∆ISn is always equal to 1. Therefore, no attenuation of
ripple is possible in ISbs and ISbk when working in DCM.
However, interleaving technique makes it possible to increase
total ripple frequency, which improves filtering requirements
Fig. 7: ∆ILn as a function of Tmaxn , for N = 5 case. even though no amplitude attenuation exists.

IV. E XPERIMENTAL TEST

In order to validate the calculations of the proposed method,
computed inflexion points are contrasted with the results
obtained from measurements on an N = 4 buck converter.
The converter parameters are summarized on Table III. Phase
current control is implemented in an FPGA with a clock period
Tclock = 20 ns. Switch on time Ton is set to 13.5 µs.
TABLE III: Experimental Setup Parameters
Description Value
Switching period, T 40.96 µs
Input voltage, Vin 100 V
Output voltage, Vout 48 V
Nominal phase inductance, Ln 200 µH
Inductor equivalent series resistance, ESRL 10 mΩ
Phase inductance tolerance ±1 %
Fig. 9: Experimental (continuous line) and calculated (dots)

Fig. 9 exhibits the phases ripple rLk , output current IL and
currents.
input current ISbk obtained by measurements on the above
described buck converter. In order to compare the calculated
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1151, March 2012.

Study of Excitonic Carrier Dynamics in

Quantum Dot Solar Cells by Numerical
Simulations
Ariel Cedola, Marcelo Cappelletti, and Eitel L. Peltzer y Blancá
 GaAs cells with layers of InAs QDs, are the most studied QD-
Abstract— This paper presents a theoretical study about the based photovoltaic devices [7]-[12]. Typically, in comparison
influence of fully correlated electron and holes on the to a similar device with no QD layers, a QDSC shows a higher
performance of quantum dot solar cells. A device-level model short-circuit current but a reduced open-circuit voltage, being
combining drift-diffusion equations for bulk carriers and rate
this last a result of the capture of carriers from the bulk into
equations for carrier dynamics in the quantum dot states,
developed ad hoc by some of the authors, was applied to the QD states and subsequent recombination within the
investigate the internal processes involved in the operation of nanostructures. This finally leads to solar cells with
InAs/GaAs quantum dot solar cells, considering excitonic capture efficiencies comparable or even below those of conventional
and escape dynamics. It is demonstrated, in line with previous devices [7]-[12]. Several design strategies have been
theoretical and experimental works, that the excitonic behavior implemented in order to improve the QDSC efficiency, with
of carriers in the nanostructures could be the responsible of the
laboratory prototypes reaching values in the order of 20% [9],
non-additive characteristic of the quantum dot contribution to
the total solar cell photocurrent. Separate carrier capture and [13]-[19]. The performance of the QDSCs may become further
escape are also investigated and compared to the excitonic worsen due to the character of the carrier escape. The non-
dynamics. additive effect of the QD photocurrent occurs when the total
photocurrent of the cell is lower than the sum of the
Index Terms—Quantum dot solar cells, carrier dynamics, photocurrents contributed by the bulk and the QDs separately,
device modeling, numerical simulation, excitonic escape. as reported in [9] for undoped InAs/GaAs solar cells. It has
been shown in [20], [21] that a possible explanation of the
non-additive effect in QDSCs is the excitonic dynamics of
C
I. INTRODUCTION
carriers in the nanostructures.
ARRIER dynamics in quantum dots (QDs) involve In this paper, the influence of the excitonic carrier escape on
capture, relaxation, escape and recombination processes the operation of QDSCs is investigated in-depth by numerical
[1]. As can be inferred from photoluminescence simulations. A physics-based model previously developed for
measurements, the electron and hole escape mechanism may QDSCs, coupling drift-diffusion transport equations for bulk
have excitonic, independent or correlated characteristics, and carriers and rate equations for electrons and holes in the QD
the nature of the carrier escape in the QDs strongly affects the states, is exploited [22]. QDs introducing different energy
behavior of the whole semiconductor structure [2]-[5]. In the states configurations are analyzed, all of them associated with
case of quantum dot solar cells (QDSCs), the type of carrier excitonic dynamics of carriers, as evidenced by photolumi-
escape has a strong impact on the current-voltage (J-V) nescence measurements in [23]. The theory of the exciton-
response of the devices. QDSCs are one of the most feasible induced non-additive effect of the QD photocurrent is
implementations of the intermediate band solar cell (IBSC) reinforced by the new results presented in this work. The main
concept [6], whose theoretical efficiency exceeds 63% under differences between the non-excitonic (separate) and excitonic
maximum sunlight concentration. QDSCs consist on p-i-n carrier behavior are also demonstrated from a physical point of
semiconductor structures with several layers of QDs view, taking advantage of the advanced features of the model.
embedded within the intrinsic region, which allow the
harvesting of low energy photons. InAs/GaAs QDSCs, i.e. II. MODEL DESCRIPTION
The devices to be studied in this paper are GaAs p+-i-n+
A. Cedola is with the Group of Study of Materials and Electronic Devices,
GEMyDE, Facultad de Ingeniería, Universidad Nacional de La Plata (UNLP), structures with a stack of InAs self-assembled QDs layers
1900, Buenos Aires, Argentina (e-mail: ariel.cedola@ing.unlp.edu.ar). embedded within the intrinsic region. Subband energy levels
M. Cappelletti and E. Peltzer y Blancá are with the Group of Study of introduced by the QD layers consist of one strongly confined
Materials and Electronic Devices, GEMyDE, Facultad de Ingeniería,
Universidad Nacional de La Plata (UNLP) and also with CONICET (e-mail: level, the ground state (GS), one or more excited states (ES),
marcelo.cappelletti@ing.unlp.edu.ar; eitelpyb@ing.unlp.edu.ar). both of them zero-dimensional, and a two-dimensional state
This work has been supported by UNLP grant I205 and by CONICET with associated with the wetting layer [1]. The relative energy
grant PIP 0292.
separations between these levels depend on the QD size, shape

experimental measurements published in the literature [9].
III. RESULTS AND DISCUSSION

The simulated GaAs cell structure consists basically in a
wide 1050 nm intrinsic region sandwiched between a 150 nm
p+ emitter region, from where light enters the device, and a
300 nm n+ back contact region. The p+ emitter is formed by a
50 nm p+ contact layer and a 100 nm p layer. A stack of 20
InAs QD layers uniformly spaced is embedded within the
intrinsic region. The density of QDs at each layer is assumed
to be 6x1010 cm-2. The GS absorption distribution of the QDs
under study is initially centered around 1130 meV (∆ =
1130 meV), in agreement with experimental observations [9],
[28]. Intersubband energy separations ∆ and most
significant simulation parameters are summarized in Table I.
Full details about the QDs and physical constants related to
Fig. 1. Band structure of the InAs/GaAs QDSC simulated in this work
the materials are reported in [22].
including the considered carrier processes: capture/relaxation (red), escape The excitonic nature of the carrier dynamics in the QDs is
(blue), photogeneration (yellow) and recombination (black arrows). modeled by forcing the relaxation and escape times of holes
(less confined carriers) to be equal to those of electrons (more
and on the lattice strain introduced during the fabrication confined ones) [29]. More precisely, the thermal activation
process [24]. Figure 1 shows the energy band diagram of the energy of the excitonic escape process is given by the sum of
InAs QD layers as will be considered in this work. The WL is the conduction and valence band discontinuities between the
treated as a discrete level with a much higher degeneracy than initial and the final states, in such a way that
GS and ES [25]. The arrows in the picture indicate the
intersubband and band-to-band charge transfer processes taken → →
∝
∆ ∆
, (2)
into account: capture from barrier to WL and cascaded
relaxation towards the lower levels, escape from a confined ∆ ∆
level to the upper one and from WL to the barrier, net
→ →
∝ . (3)
recombination and photogeneration. No connection between
adjacent layers is assumed, and the coupling between the QDs The summed energies in (2) and (3) correspond to the optical
and the barrier is established through the WL. The balance energy gaps between the QD bound state and the level
between all the processes is modeled by a set of rate equations immediately above, given by ∆ −∆ and ∆ −
describing the population of electrons and holes at each energy ∆ , respectively, as seen in Fig. 1 [2], [4].
level [22]. Transport of carriers in the barrier is modeled by a In previous works [20], [21], the excitonic dynamics model
drift-diffusion approach. Electron and hole dynamics in the was successfully applied to explain the non-additive effect of
QDs are characterized by capture, relaxation, recombination the photocurrent contributed by the QDs, an anomalous
and escape time constants. Capture and relaxation times are behavior of the J-V characteristic of QDSCs, depicted in
determined from experimental data [22], whereas the thermal Section 1. Excitonic escape of carriers was also
escape times are calculated from the rate equations by experimentally observed for shallow level QDs in [3], [23]
imposing the thermal equilibrium condition [26], [27], as and [30]. In Ref. 23, strong evidence of excitonic escape was
follows found in particular from small sized QDs with transition
energies ∆ −∆ between 40 meV and 70 meV.
→ →
∆
, (1) Assuming excitonic escape, the dependence of the non-
additive characteristic of the QD photocurrent on the zero-
TABLE I. SIMULATION PARAMETERS
where  and  refer to the states GS, ES, WL and ES, WL,
GaAs, respectively, and are the effective Parameter Value
densities of states at each state, →
is the capture time of p , p, i, n GaAs region thicknesses [nm]
+ +
50, 100, 1050, 300
p+, p, i, n+ GaAs doping densities [cm-3] 5x1018, 1018, 1013 (n-type),
electrons (holes) from  down to , ∆ is the energy 5x1018
separation between levels, as sketched in Fig. 1, is the ∆ ,∆ ,∆ [meV] 140, 62, 70
∆ ,∆ ,∆ [meV] 28, 16, 16
Boltzmann constant and is the lattice temperature. Solar QD capture range [nm] 4
photon flux density is assumed to decay exponentially into the QD density [cm ]
-2
6x10 10
material following the Beer-Lambert’s law. The absorption Solar spectrum AM1.5G
coefficient spectra of WL, ES and GS were extracted from

Fig. 3. Degree of non-additive effect of the QD photocurrent calculated as

the normalized difference between the QD current under filtered and full
illumination, for both carrier dynamics models.
additive characteristic. This is shown in Fig. 2(b). Even

though the QD contribution is still important, 3.31 mA/cm2
and 2.83 mA/cm2 for transition energies of 40 meV and 70
meV, respectively, the enhancement in the short-circuit
current of the QDSCs under full illumination, with respect to
the reference cell, is only 1.71 mA/cm2 for 40 meV and 0.26
mA/cm2 for 70 meV, values far below the QD photocurrents
calculated without the presence of photogenerated carriers in
the barrier.
Fig. 2. Simulated J-V characteristic of the QDSCs considering (a) separate
The difference between the QD contribution to the
carrier dynamics and (b) excitonic carrier dynamics. Legend in (a) applies to photocurrent under filtered and full solar spectrum
both figures. illumination, i.e. the measure of the current non-linearity
induced by the excitonic dynamics, gives an idea of the degree
dimensional energy states configuration is analyzed below by
of non-additivity for each considered scenario. This difference
numerical simulations. The optical gap between the WL and
(normalized) is shown in Fig. 3 as a function of the transition
the QD states is adjusted in the range 40-70 meV by changing
energy, at short-circuit condition. Non-excitonic results are
the peak energy of the GS spectral distribution (∆ ), while
also included for comparison. As can be seen, the non-additive
keeping constant the gap between QD states (∆ −∆ ).
characteristic increases with the energy confinement of the
The nearly unvarying energy separation between bound states
QDs, being very pronounced for the excitonic dynamics and
with the QD size, to which the energy fluctuations could be
almost negligible for the separate model. For the maximum
associated, was theoretically demonstrated in [31]. Figure 2
confinement (70 meV), indeed, the usable contribution of the
shows the calculated J-V curves of QDSCs with these
QDs to the solar cell photocurrent under normal operation is
transition energies, considering both, separate and excitonic
practically zero. The power conversion efficiency of this cell
carrier dynamics, along with the J-V curve of a reference cell
falls to 8.7%, more than 30% (relative) below the efficiency of
(identical structure but without QDs). The increment in the
the GaAs reference cell. Under the hypothesis of non-
short-circuit current and the reduction in the open-circuit
excitonic dynamics, on the other hand, it is concluded that
voltage of the QDSCs with respect to the reference cell are, as
slight variations in the peak position of GS and ES spectra do
explained in Section 1, typical in these devices. Each cell was
not lead to significant changes in the collection of carriers
simulated under illumination with full and filtered solar
photogenerated in the QDs.
spectrum. In the last case, the wavelengths absorbed by the
Taking advantage of the physics-based developed model,
GaAs ( < 880 nm) were filtered out in order to determine
the internal processes leading to this difference in the behavior
only the contribution of the QDs to the cell photocurrent. As
of the cell, dependent on the illumination spectrum, can be
can be seen in Fig. 2(a), there is no evidence of a significant
visualized. As demonstrated earlier [21], recombination rates
non-additive effect of the QD photocurrent in the separate
in all QD layers become larger under the excitonic dynamics,
dynamics case. For each transition energy, the addition of the
mainly due to the increment of the hole densities in the QD
short-circuit current calculated under filtered illumination plus
states. The enhanced recombination limits the carrier escape
that of the reference cell leads practically to the value of the
from WL to barrier, in other words, lessens the ability of the
current obtained under full illumination. However, as
QDs to provide the barrier with the extra charges
anticipated, the excitonic model reproduces well the non-

Fig. 5. Equivalent current densities obtained after integrating the rates of the
involved processes (photogeneration, recombination and escape from WL-to-
barrier), for both separate and excitonic dynamics, simulated at V = 0 under
full illumination.
calculated by integrating the sum of all the photogeneration

rates in the QD layers, leading to extraction efficiencies in the
range 73% - 83%.
It is interesting to visualize the variation in the strength of
the photogeneration, recombination and WL-to-barrier net
Fig. 4. Comparison between the net escape rate from WL to barrier for full escape processes with the energy confinement, under full
(a) and filtered (b) solar spectrum illumination, considering excitonic
dynamics and short-circuit condition. spectrum illumination, which is opposite depending on the
nature of the carrier dynamics. Figure 5 shows the balance
photogenerated in WL, ES and GS by the long-wavelength between these three mechanisms, that define the QDSC
portion of the solar spectrum. As the population of electrons performance, as a function of ∆ −∆ , at short-circuit
and holes in the barrier increases due to the photogeneration, condition and under full spectrum illumination. Both non-
both the occupation of the QD states and as a consequence the excitonic and excitonic transitions are evaluated. As can be
recombination rates are further increased. This occurs under verified, the sum of net escape and recombination currents is
full illumination. By filtering out the shorter wavelengths of perfectly balanced with the photogeneration current in all
the solar spectrum, the carrier populations in the barrier keep cases. For excitonic dynamics, the portion of recombining
relatively low, preventing the raise of the recombination rates carriers is higher than that of escaping carriers, and it increases
and allowing a more efficient extraction of carriers from WL. with the energy confinement to such an extent that for
This situation can be observed in Fig. 4(a) and 4(b), which ∆ −∆ = 70 meV almost all the photogenerated
show the net escape rates of carriers from WL to barrier at the electrons and holes in the QDs are lost by recombination. This
whole QD region, simulated under full and filtered is aligned with the results shown in Fig. 3. The opposite
illumination, respectively, for energy confinement in the range scenario is achieved for the non-excitonic carrier model. The
40-70 meV, considering excitonic dynamics. The main net escape current approaches the total photogeneration
difference between the two addressed situations lies in the QD current and, for shallower confinements, recombination is
layers near the contact areas of the solar cell, where the negligible and practically all the photogenerated electrons and
electron and hole occupations are high due to their diffusion holes are able to reach the barrier, enhancing the device
from the contacts [21]. For full solar spectrum, capture from response.
barrier to WL rather than escape towards the GaAs prevails in
layers 1, 2, 3 and 4, see the inset in Fig. 4(a). The worst case is IV. CONCLUSIONS
found for the QDs with deeper confinement. This behavior is We have investigated the non-additive effect of the
reversed for the filtered solar spectrum operation, for which, in photocurrent contributed by the QDs in InAs/GaAs QDSCs,
addition, the escape rates in layers 18, 19 and 20 are by modeling and numerical simulations. Both separate and
incremented. As a result the contribution of the QDs to the excitonic carrier dynamics in the confined energy levels have
total current gets closer to the total photogeneration current

been considered. From the obtained simulation results, we can [12] K. Tanabe, D. Guimard, D. Bordel and Y. Arakawa, High-efficiency
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[14] Y. Okada, T. Morioka, K. Yoshida, R. Oshima, Y. Shoji, T. Inoue, T.
two sets of experimental works. On the one hand, Kita, “Increase in photocurrent by optical transitions via intermediate
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An Statistical Filtering Models Comparison for

GNSS LEO Satellite Navigation
Jorge Cogo∗, Javier G. Garcı́a∗ , Pedro A. Roncagliolo∗ and Carlos H. Muravchik∗†‡
∗ Departamento de Electrotecnia, Facultad de Ingenierı́a, Universidad Nacional de La Plata (UNLP).
Calle 48 y 116, La Plata, Bs. As., Argentina.
† Instituto LEICI, UNLP. Calle 48 y 116, La Plata, Bs. As., Argentina.
‡ CIC-PBA. Calle 526 entre 10 y 11, La Plata, Bs. As., Argentina.
{jorge.cogo, jgarcia, agustinr, carlosm}@ing.unlp.edu.ar
Abstract—In this work the performance of different statistical models obtained based on this approach are described in
filtering models used for estimating states of aerospace vehicles, section III.
particularly LEO satellites, based on measurements of GNSS On the other hand, dynamics studies the laws of motion
systems are compared. This problem is non-linear in nature,
since both the state variables model and the output function are of bodies in relation to the causes that originated them,
non-linear. Thus we resort to the use of the extension of the the intervening forces. The formulation known as Newtonian
Kalman filter called EKF. mechanics enables the description of the motion based on
Different models based on several kinematic and dynamic ordinary differential equations in cartesian coordinates; this
approaches are considered. For the performance assessment will be sufficient for the vehicles we want to model. This
we use representative simulation scenarios. Finally, as a real
application example, the case of GPS measurements taken on approach is described in section IV.
board the Argentine SAC-D satellite is analyzed. Since these models are of a non-linear nature, and that
measurements obtained with GNSS are also related non-
I. I NTRODUCTION linearly with the states, the problem of state estimation is also
The Global Navigation Satellite Systems (GNSS) provide nonlinear. In numerous papers such as [3] and [4] filtering
an alternative for the accurate determination (estimation) of schemes based on the Extended Kalman Filter (EKF) for
position and velocity of Low Earth Orbit (LEO) satellites. precise orbit determination based on GPS signals are used,
Currently there are several fully operational GNSS systems and in [5] and [6] the case of orbit determination using other
as GPS (USA) and GLONASS (Russia), or in stage of filtering schemes such as the Unscented Kalman Filter (UKF)
development, as Galileo (European Union) and Beidou (China) or Sigma-Point Kalman Filter are presented.
[1], [2]. In a previous work [7] the performance of two different
The measurements obtained with GNSS are related to the filtering schemes (EKF and Positioning Kalman Filter (PKF))
satellite-receiver range (pseudorange) and their rate of change is compared for the case of using the same vehicle model.
(deltarange). The former is based on the signal time-of-arrival, In this paper we will focus on analyzing the behavior of the
while the latter is based on the carrier doppler frequency same filtering scheme, the EKF, with different versions of the
shift. Since it requires synchronism of time references of both vehicle model. A brief summary of the EKF formulation is
the GNSS system and the user (receiver), which can’t be described in section V, while section VI describes how the
ensured a-priori, two additional unknowns are incorporated to formulation for each one of these analyzed models results.
the problem: bias and drift of the user’s clock. A mathematical In section VII, the performance of EKF with the different
model of the measurements is presented in section II. proposed models is compared by simulation, while in section
These measurements are affected by various factors that VIII an application example with actual GPS data from
induce both systematic and random errors. For the first type of onboard argentine SAC-D satellite is presented. Finally, in
errors one generally resorts to the use of models to discount or section IX the conclusions are set.
at least reduce them, while to mitigate the effect of the latter,
II. M EASUREMENTS M ODEL
statistical filtering methods are often used. These filtering
methods usually take advantage of a model that describes The pseudorange measurement at time k obtained by a user
vehicle behavior in terms of a state variable system. at position rk based upon the signal of the j-th satellite at
To obtain state variable models for LEO satellite vehicles position skj is given by
we use two approaches of classical physics: the kinematic
ρkj = kskj − rk k + bk + εkj + νkj (1)
approach and the dynamic approach. Kinematics studies the
laws of motion of bodies without considering the causes that where bk is the receiver’s clock bias multiplied by the speed
originate them. Such description generally begins with the of light to be interpreted as range, and εkj and νjk group the
knowledge of some of the involved variables, and the rest sistematic and stochastic errors, respectively. We model the
are obtained based on derivation/integration as required. The latter as an i.i.d. gaussian process, with zero mean and variance

σρ2 . We denote with ρk the column vector that groups all the attraction, if it is modeled as a point mass, and ap corresponds
pseudorange measurements available at time k. to the acceleration due to other factors. In the case of LEO
We also denote satellites, the four effects that contribute the most to ap are:
skj − rk non-uniform distribution of Earth’s mass, ane ; gravitational
ekj , (2) attraction of other celestial bodies, a3b ; atmospheric drag, ad
kskj − rk k
and thrust of the engines used for orbital maneuvers, at [8]
the line-of-sight vector that points from the user’s position to
the j-th GNSS satellite. If the user and satellite velocity vec- ap = ane + a3b + ad + at . (7)
tors are ṙk and ṡkj , respectively, the deltarange measurement
of that satellite results To formulate Eq. 6 in an ECEF frame we need to add the
terms due to the rotation between the ECEF and ECI frames
ρ̇kj = ekj · (ṡkj − ṙk ) + ḃk + ξkj + υkj (3) [9]
µ
where ḃk is the user’s clock drift converted to velocity, and ξkj r̈ = − 3 r + aep + 2S(ωeei ) ṙ + S(ω eei )2 r (8)
and υjk group the sistematic and stochastic errors, respectively. r
We model the latter as an i.i.d. gaussian process, with zero where aep denotes the acceleration due to disturbances ex-
mean and variance σρ̇2 . We denote with ρ̇k the column vector pressed in the ECEF frame, S(·) denotes the cross product
that groups all the deltarange measurements available at time matrix, S(x)y = x × y, and ω eei denotes the angular velocity
k. vector of the ECI frame relative to the ECEF frame, measured
in ECEF. In Eq. 8 the three vectors r̈, ṙ and r are expressed
III. K INEMATIC A PPROACH in ECEF coordinates.
If we consider as state variables the three position states and
the three velocity states (contained in xk ), and as a disturbance V. K ALMAN F ILTER (KF)
input the three acceleration states (contained in ak ); and The KF is an estimator for what is known as linear
neglect higher order terms, a kinematic model discretized in quadratic problem of estimating the state of a linear dynamic
time every T seconds is system disturbed by white noise, using measurements linearly
2
T
related to the state and affected linearly by white noise. The
I3×3 T I3×3 2 I3×3 resulting estimator is statistically optimal with respect to any
xk = xk−1 + ak−1 . (4)
03×3 I3×3 T I3×3 quadratic function of the estimation error [10].
If we also consider that the state vector includes the three We will focus on analyzing the variant of the KF used for
acceleration states, and considering as a disturbance input the discrete systems, whose mathematical description is
three jerk states (contained in jk ); neglecting the higher order
xk = Fk−1 xk−1 + Gk−1 wk−1 (9)
terms, the model is
 2  yk = Hk xk + vk (10)
I3×3 T I3×3 T2 I3×3
xk =  03×3 I3×3 T I3×3  xk−1 + where xk denotes the system’s state, and yk denotes the
03×3 03×3 I3×3 measurements vector, both at time k. Matrices Fk−1 , Gk−1
 T3  and Hk are commonly referred to as System Matrix, Input
62 I3×3 Matrix and Output Matrix, respectively. The vectors wk and
+  T I3×3  jk−1 . (5) vk are modeled as uncorrelated white stochastic processes
2
T I3×3 with zero mean and covariance matrices denoted Qk and Rk ,
Equations 4 and 5 represent linear time-invariant discrete respectively.
systems, in whose formulation no assumption was made about In the formulation of the KF, two estimates of the state
+
the causes of the acceleration (or higher order terms), in line vector are defined: x̂−
k , or a-priori estimate, and x̂k , or a-
with a kinematic approach. Therefore, these models can be posteriori estimate, with covariance matrix of the estimation
+
used in a wide variety of vehicles when no other, more accurate error P−k and Pk , respectively. The relationships between
model is available. Moreover, being very simple and time- them and the measurements are given by [10], [11]
invariant models, they often result in a low computational load +
x̂−
k = Fk−1 x̂k−1 (11)
implementation.
P−
k = Fk−1 P+ ′
k−1 Fk−1 + Gk−1 Qk−1 Gk−1
′
(12)
IV. DYNAMIC A PPROACH
x̂+ − −
k = x̂k + Kk (yk − Hk x̂k ) (13)
To describe the orbital motion from a dynamic approach,
P+ −
k = (I − Kk Hk )Pk (14)
we start from the equation describing the acceleration of a
satellite in the ECI frame (Earth-Centered Inertial) [8] Kk = P− ′ − ′
k Hk (Hk Pk Hk + Rk )
−1
(15)
µ where Eqs. (11) and (12) are called temporal updates of
r̈ = − 3 r + ap (6)
r the estimate and the covariance matrix of the estimation
where µ is the Earth’s gravitational constant and r = |r|. error, respectively; Eqs. (13) and (14) are called observational
The first term corresponds to the effect of Earth’s gravitational updates of the estimate and the covariance matrix of the

estimation error, respectively; and Eq. (15) is called Kalman Thus, in all cases the linearization of the system function
gain matrix [11]. A′ denotes the transpose of A. is given by
At every moment in which the state must be estimated, 
1T

the steps of temporary update (Eqs. (11) and (12)) and 0 2×M
Fk =  0 1  (19)
observational update (Ecs. (13) and (14)) have to be carried 0M×2 F⋆k
out. The latter also requires the computation of the Kalman
gain matrix (Eq. (15)). where F⋆k denotes the system matrix state without expanding,
and M depends on the dimensions of F⋆k . E.g., for Kinematic
A. Extended Kalman Filter (EKF) models I and II this matrix is obtained by inspection of Eqs.
(4) and (5) (i.e. the leftmost matrix of the right-hand side of
The EKF is an extension of the KF for the case where
each equation); and for the Dynamic I model it’s
the state model and/or the relationship between the state and "
T2 µ
#
the measurements is non-linear [11]. Eqs. (11) and (13) are 1 − 3 I3×3 T I 3×3
reformulated as F⋆k = 2 rk
+
−T rµ3 I3×3 I3×3
k
+
x̂−
k = fk−1 (x̂k−1 ) (16) T2 2
S(ω eei )2 T2 2S(ωeei )

+ 2 . (20)
x̂+
k = x̂−
k + Kk (yk − hk (x̂−
k )). (17) T S(ωeei )2 T 2S(ωeei )
All other equations remain the same, but replacing the The input matrix is given by
matrices Fk−1 and Hk by a linearization of the equations
 T2 
around the latest estimate of the state.
2 02×1 
Gk =  T (21)
0M×1 G⋆k
VI. M ODELS TO BE C OMPARED
where G⋆k denotes the input array for the state without
For the formulation of the EKF we consider the following expanding, and M depends on the dimensions of G⋆k . For
models Kinematic I and II G⋆k is obtained by inspection from Eqs.
• Kinematic I: We consider as states the three position (4) and (5) (i.e. the rightmost matrix of the right-hand side of
states and the three velocity states; the perturbation is each equation); for Dynamic I and II, it is equal to those of
given by the acceleration. It corresponds to the model Kinematic I, while for Dynamic III and IV is equal to those
described in Eq. (4). of Kinematic II.
• Kinematic II: We consider as states the three position Meanwhile, assembling the vector of measurements as the
states, the three velocity states and the three acceleration concatenation of measurements of pseudorange and deltarange
states; the perturbation is given by the jerk. It corresponds ′
yk = ρ′k ρ̇′k

to the model described in Eq. (5). (22)
• Dynamic I: We consider as states the three position states the matrix Hk results
and the three velocity states related as in Eq. (8). The
∂h(xk )
perturbation is given by the acceleration ap . Hk , = (23)
• Dynamic II: Similar to Dynamic I, but incorporating the
∂xk x̂−
k
effect of the J2 coefficient (Jeffery’s second constant in 1Nk ×1 0Nk ×1 H⋆k 0Nk ×3 0Nk ×L

= (24)
the description of the Earth’s gravitational potential [9]) 0Nk ×1 1Nk ×1 0Nk ×3 H⋆k 0Nk ×L
in ap . The perturbation is given by the remaining terms
where H⋆k is a matrix containing in its rows the line-of-
in ap .
sight vectors, Eq. (2), corresponding to the satellites whose
• Dynamic III: Similar to Dynamic I, but adding three
measurements were grouped into yk , Nk is the number of
aditional states to estimate the non-modeled acceleration.
measurements available at time k, and L is equal to 3 if the
The perturbation is given by the jerk.
state includes acceleration and zero otherwise.
• Dynamic IV: Similar to Dynamic II, but adding three
aditional states to estimate the non-modeled acceleration. VII. S IMULATION R ESULTS
The perturbation is given by the jerk. To define a significant simulation scenario, we generate
In all cases we extend the model by incorporating two the true states of position and velocity that would have our
additional states to contemplate bias, bk , and drift, ḃk , accord- vehicle in a given time interval (actually we are interested
ing to the measurements model as described in II. We also in a sampled interval, tk = kT , k ∈ K ⊂ Z). Based on
incorporate an element to the disturbances to model the clock these states and a description of the GNSS constellation we
“acceleration”, b̈k . We assume that the relation between these synthesize the measurements that the vehicle would have at
states corresponds to a linear system each time k. By entering these synthesized measurements to
T2 the filtering algorithm (in each of its variants) the estimation
bk 1 T bk−1 of the corresponding states is obtained. In this way, it is
= + 2 b̈k−1 . (18)
ḃk 0 1 ḃk−1 T possible to compare the solutions obtained in each case with

the true solution and analyze the performance attained using

the different proposed models. 106
We consider a LEO satellite with orbital parameters i = 98, Kin. I
Kin. II
e = 0, a = 7.028 × 103 m, similar to the nominal orbital Dyn. I
105
parameters of the argentine SAC-D satellite, a simulation Dyn. II
interval equal to the orbital period and a sampling step of Dyn. III
Dyn. IV
1 second. To generate the states of position and velocity we 104
use the model with disturbances described in section IV in
which all disturbances are modeled in detail accordingly to
e.g. [8], without considering trust forces. 103
ǫ2p
We also obtain the status of GNSS satellites in the simula-
q
tion interval as described e.g. in [1], using a set of arbitrarily 102
chosen broadcast ephemeris, and determine which of them are
visible by the vehicle at each point of its trajectory.
We next synthesize the pseudorange and deltarange mea- 101
surements for each one of the satellites in view at every
moment. For that, we include a model of the user’s clock 100
bias and drift (Eqs. 1 and 3), and the noise affecting each
measurement.
We adjust the covariance matrix Rk (used in Eq. (15)) with 10−1
10−6 10−4 10−2 100
the same value used to generate the measurements’ noise, σẍ , σj
and compare the performance of each filtering scheme (with
the diverse proposed models) for different values of the noise
Fig. 1. Mean square error in bias-position solutions as a function of σẍ (or
model covariance matrix Qk (used in Eq. (12)), given by σj ) for the six models considered using GPS system. In all cases σb̈ = 0.01
is taken.
σb̈2

01×3
Qk = (25)
01×3 σα2 I3×3
TABLE I
where σα = σẍ for those models in which it is considered R ESULTS OF COMPARISON OF DIFFERENT MODELS .
that the disturbance is given by the acceleration, and σα = σj Mod. pt. σẍ ( σj )
q
E{ǫ2p }
p
E{ǫ2v }
for those models where it is considered that the perturbation
Pos 5.75 7.71 × 10−1 1.56 × 10−1
is given by the jerk. To analyze the performance of each of Kin. I
Vel 6.00 7.71 × 10−1 1.56 × 10−1
the models we used as a metric the mean square error in bias- Kin. II
Pos 2.00 × 10−2 7.68 × 10−1 9.69 × 10−2
position and drift-velocity solutions Vel 2.00 × 10−2 7.68 × 10−1 9.69 × 10−2
Pos 1.00 × 10−1 7.65 × 10−1 8.64 × 10−2
Dyn. I
4.00 × 10−2 7.98 × 10−1 6.85 × 10−2
v
u K−1 Vel
q u 1 X kx̂p,k − xp,k k2 Pos 7.50 × 10−4 3.87 × 10−1 1.69 × 10−2
ǫ2p = t (26) Dyn. II
Vel 7.50 × 10−4 3.87 × 10−1 1.69 × 10−2
K 4
k=0 Pos 2.50 × 10−4 7.12 × 10−1 3.20 × 10−2
Dyn. III
Vel 2.50 × 10−4 7.12 × 10−1 3.20 × 10−2
v
u K−1
q u 1 X kx̂v,k − xv,k k2 Pos 2.50 × 10−6 4.06 × 10−1 1.57 × 10−2
2
ǫv = t (27) Dyn. IV
Vel 2.50 × 10−6 4.06 × 10−1 1.57 × 10−2
K 4
k=0
where xp,k and x̂p,k respectively denote the sub-vectors of xk

and x̂k , that contain the three position coordinates and bias errors. In other words, the estimator cannot follow the user’s
(in meters) elements; and xv,k and x̂v,k respectively denote variations, resulting in estimation errors.
the sub-vectors of xk and x̂k that contain the three velocity On the other hand, tuning the filter to large values of
coordinates and drift (in m/s) elements. “sigmas” also leads to large estimation errors. This tuning can
In Figs. 1 and 2 the results of evaluation of these metrics as be interpreted as relying more in the measurements than in
a function of the parameter σẍ (or σj ), for the different models the model; however, since the measurements are contaminated
proposed, are presented. The optimal values are summarized in with noise, too much reliance on them leads to the noise not
Table I. In this case GPS measurements are used. The results being filtered. In other words, the estimator follows the noise-
obtained with the GLONASS system are similar. produced variations of the measurements, resulting again in
It can be seen that, when tuning the filter with small values estimation errors.
of “sigmas”, the estimation error is large. This tuning can be It can be seen that the Kinematic I model is the one with the
interpreted as putting more confidence in the model than in worst performance, which is expected based on its simplicity:
the measurements; however, if the model is not quite accurate, it does not attempt to model or estimate the acceleration. It
putting too much confidence in it leads to bigger estimation may also be seen that Kinematic II and Dynamic I models

VIII. A PPLICATION E XAMPLE

4
10
Kin. I As a real-data application example, we analyzed GPS mea-
Kin. II
Dyn. I surements taken on board the argentine SAC-D satellite. In
103 Dyn. II this case we applied corrections to systematic errors in the
Dyn. III
Dyn. IV
pseudorange and deltarange measurements, and we model the
standard deviation for each measurement according to the
102 C/N0 estimated by the receiver itself. Since there are not real
positions and velocities of reference, we chose to compare the
results obtained with different models among themselves.
ǫ2v
101 In Figs. 3 and 4 errors observed in the three coordinates

q
of position and velocity using the Dynamic II model, with

reference to the solution of the Dynamic IV model are pre-
100 sented. In order to make a comparison, the errors against the
same reference obtained in the punctual solution (an algebraic
solution based on the measurements sampled simultaneusly
10−1 on a single time instant) are also presented. To this end, we
consider the same noise covariance matrix of measurements
used in the filtering process. The ±3σ error intervals, based
10−2
10−6 10−4 10−2 100 on the corresponding element on P+ k , are also plotted in each
σẍ , σj coordinate. It can be seen that virtually at all times the error
is kept within these limits.
Fig. 2. Mean square error in drift-velocity solutions as a function of σẍ (or When comparing the results obtained with other models, a
σj ) for the six models considered using GPS system. In all cases σb̈ = 0.01 good correspondence with simulation results was observed.
is taken. This allows a real data validation of the operation of the
proposed filtering schemes.
have a similar performance, i.e. using a simple acceleration

model achieves a similar performance to trying to estimate it
on the filter.
It may also be noted that the Dynamic III model has a
better performance, since that, besides using a simple model
of acceleration, it estimates the non-modeled acceleration.
Finally, Dynamic II and IV models are the ones that get the
best performance, which is expected because they use a more
accurate model of acceleration including the effect of J2 . The
fact that both obtain a similar performance is because the effect
of non-modeled acceleration is small in this case and therefore,
estimating it doesn’t produce any advantage over leaving it as
part of the unmodelled perturbations.
Figures 1 and 2 are also useful for analyzing how the
performance of each model gets worse in case of choosing
another tuning value, e.g. when trying to obtain a better
performance against non-ideal effects, which have not been
taken into account.
In comparing the Kinematic II and Dynamic III and IV
models with others it should be noted that the horizontal
axis corresponds to jerk, while in the others it corresponds
to acceleration.
Searching the optimal considering the σb̈ dimension as well
(not presented due to space limitations), shows that the optimal
value is obtained for σb̈ = 0.01 or very close values. In the Fig. 3. Error in solving point position (blue) and by EKF (red) using the
latter case, the optimum value doesn’t differ significantly from Dynamic II model, with respect to the solution taken as a reference. The
that obtained taking σb̈ = 0.01. For this reason this value was interval ±3σ of error estimated by the same filter (black) is also displayed.
used in the comparison of all models.

in which the algorithms will be implemented and it’s beyond

the scope of this work.
As future work, an analysis of the performance against
unmodeled disturbances, such as the effect of thrust, will
be addressed. Also, some modifications needed in order to
use measurements from more than one GNSS system, i.e.
GLONASS or Galileo, will also be considered.
ACKNOWLEDGMENT
This work was funded by the Argentine ANPCyT grant
PICT2014-1232, Universidad Nacional de La Plata grant 11-
I-166, and CIC Pcia de Buenos Aires.
Real data used in this work were provided by the CONAE
(Comisión Nacional de Actividades Espaciales) within the
framework of the Satellite SAC-D/Aquarius mission.
R EFERENCES
[1] E. Kaplan and C. Hegarty, Understanding GPS: Principles and Appli-
cations. Artech House, 2005.
[2] B. Hofmann-Wellenhof, H. Lichtenegger, and E. Wasle, GNSS – Global
Navigation Satellite Systems: GPS, GLONASS, Galileo, and more.
Springer, 2007.
[3] O. Montenbruck, T. van Helleputte, R. Kroes, and E. Gill, “Reduced
dynamic orbit determination using GPS code and carrier measurements,”
Aerospace Science and Technology, vol. 9, no. 3, pp. 261 – 271, 2005.
[4] H. Bock, A. Jäggi, D. Švehla, G. Beutler, U. Hugentobler, and P. Visser,
“Precise orbit determination for the GOCE satellite using GPS,” Ad-
vances in Space Research, vol. 39, no. 10, pp. 1638 – 1647, 2007.
[5] E.-J. Choi, J.-C. Yoon, B.-S. Lee, S.-Y. Park, and K.-H. Choi, “Onboard
Fig. 4. Error in solving point velocity (blue) and by EKF (red) using the orbit determination using GPS observations based on the unscented
Dynamic II model, with respect to the solution taken as a reference. The kalman filter,” Advances in Space Research, vol. 46, no. 11, pp. 1440 –
interval ±3σ of error estimated by the same filter (black) is also displayed. 1450, 2010.
[6] P. C. Pinto, M. Pardal, H. K. Kuga, and R. V. de Moraes, “A discussion
related to orbit determination using nonlinear sigma point kalman filter,”
Mathematical Problems in Engineering, 2009.
IX. C ONCLUSIONS [7] J. Cogo, J. G. Garcı́a, R. P.A., and C. H. Muravchik, “Comparación de
Métodos de Filtrado Estadı́stico para Navegación de Satélites LEO con
In this work we proposed different statistical filtering mo- Señales GNSS,” in Argencon 2014, 2014.
[8] O. Montenbruck and E. Gill, Satellite Orbits: Models, Methods and
dels that can be employed in the formulation of an EKF Applications. Springer Berlin Heidelberg, 2012.
filtering scheme for LEO satellite navigation based on GNSS [9] A. Tewari, Atmospheric and Space Flight Dynamics: Modeling and
measurements. The simplest ones are based on a kinematic Simulation with MATLAB R and Simulink .R Birkhäuser Boston, 2007.
[10] M. Grewal and A. Andrews, Kalman filtering: theory and practice using
approach and could be extended to a variety of vehicles. The MATLAB, 2nd ed. Wiley, 2001.
other ones are based on a dynamic approach that takes into [11] D. Simon, Optimal State Estimation: Kalman, H Infinity, and Nonlinear
account the most significant forces acting in the motion of Approaches. Wiley, 2006.
this kind of vehicle. It should be noted that in all cases we
prioritize obtaining simple models, feasible for implementing
real-time algorithms, i.e. without a high computational burden
associated.
Based on a representative simulation scenario, we compared
the performance of these different models obtaining in each
case the optimum tuning value of the filter and analyzing the
relative improvements of each one. Based on actual measure-
ments took by the argentine satellite SAC-D, the applicability
of filtering schemes proposed for this kind of vehicle was also
verified.
From a purely qualitative analysis, we can conclude that,
in general the better performance is attained with the most
complex implementation in terms on computational burden.
However, the additional complexity seems not to be prohibitive
for a real-time implementation. A quantitative analysis of the
computational burden depends on the particular architecture

A Floating Voltage Regulator with Output Level

Sensor for Applications with Variable High Voltage
Supply in the Range of 8.5V to 35V
Javier Osinaga, Julio Saldaña and Wilhelmus Van Noije
LSITec – Laboratório de Sistemas Integráveis Tecnológico
Polytechnic School of Engineering – University of São Paulo, Sp, Brazil.
Abstract-- In this paper we present the design and

implementation of a linear voltage regulator using a 0.6µm
CMOS high voltage process. The circuit provides a “floating
ground” of 5V below a supply voltage that can vary between 8.5V
and 35V. An additional feature of a voltage level sensor,
generating a low voltage signal that advise the state of the
regulator is provided by the circuit. The proposed topology,
calculations, simulations and measurements of the implemented
circuit are exposed in this work. The area of the floating
regulator circuit is 599µm x 329µm, the measured output voltage
presents a 2.5% standard deviation from the designed voltage.
Index Terms -- floating ground, floating regulator, high voltage

regulator high side, power-on reset.
I. INTRODUCTION
In many applications, like industrial or automotive, the

supply voltage of the electronic circuits may have larges
variations that can reach tens of volts. In this kind of system it
is common to found current sensors or gate drivers intended to Fig. 1. Basic Low DropOut voltage regulator basic topology.
detect over current and activate high voltage protection
switches, preventing damages on the circuits. Those no floating reference voltage exist, so there is no reference to
protections and drivers may be connected between the compare. To add to the system the level sensing feature for the
protected circuit and ground, called low side, or between the output of the floating regulator, a comparator without high
supply and the circuit, called high side. side reference must be designed.
For high side and low side protection circuits it is very In this work we have designed, implemented and measured a
useful to have separated voltage domains that avoid exposing floating linear voltage regulator with an output level sensor. In
the components through wide voltage differences. This allow section II we introduce some fundamental concepts about
to use transistors of a standards CMOS process instead of high linear voltage regulators, in section III we present the
voltage transistor. The possibility to use standard process proposed topology and the equations that describe the
transistors allow to improve the matching of the components behavior of the floating voltage regulator, in section IV we
and reach a higher accuracy on designed circuit. present the proposed topology and the equations that describe
A solution to obtain a separated voltage domain for high the behavior of the voltage level sensor, in section V and
side is implement a floating voltage regulator that provide a section VI we expose the post-layout simulations of the circuit
“floating ground”, maintaining a constant voltage difference and the measurements done on the fabricated chip, finally in
against the variable supply. section VII we present the conclusions of this work.
As voltage regulators referenced to ground, floating voltage
regulators must be sensed by a Power-On Reset (POR) circuit
[1] or similar to determine if the system is in proper operating II. LINEAR VOLTAGE REGULATOR
conditions. In many cases for better accuracy the voltage level
is determined comparing the output voltage against a voltage The linear voltage regulators are widely used on electronics
reference of the system [2]. Sense the output voltage level of a to provide a constant low noise supply. The basic idea is that
floating regulator is a more challenging task because generally the regulator acts like a variable resistor adjusting the current

III. FLOATING VOLTAGE REGULATOR
To implement a high voltage domain that allow to supply

loads composed by standard 5V PMOS transistors and bulk
isolated 5V NMOS transistors, a linear voltage regulator that
generate a floating ground was designed. The regulator
provide a node, able to drain the variable current consumed by
the load, that remains constantly 5V below a supply voltage
variable in the range between 8.5V to 35V. The topology
presentation was divided in three sub-circuits, first the floating
voltage reference circuit, second the linear regulator loop and
third the pre-regulator circuit.
A. Floating voltage reference

The reference voltage is critical for the accuracy of the
regulator, the error in the reference is propagated directly to
the output. On Fig (2) inside the red dashed trace is shown the
implemented reference composed by the transistors N 1, N2,
NHV1, NHV2 and the resistor Rext, the supply voltage is named
BPOS. The reference current Iref is copied by the cascode
current mirror and generate a constant 5V voltage drop on the
external resistor Rext for the all supply range as it is described
on equation (2). The mirror is designed in cascode
configuration increasing the output resistance and so reducing
the channel length modulation [5], which in this application is
crucial because of the wide voltage range that the reference
assume. The NHV1 and NHV2 are NMOS high voltage transistors
Fig. 2. Proposed floating regulator; inside the red trace is the voltage reference that, besides increasing the mirror output resistance, protect
circuit; inside the blue trace is the linear regulator loop; inside the green trace
is the pre-regulator. the N1 and N2 transistors against breakdown voltages. N 1 and
N2, are designed in the standard 5V NMOS process to reach a
drained from the supply in accordance to the load better matching and improve the copy accuracy. The
consumption and thus maintain constant the output voltage. A utilization of an external resistor allow to tune the voltage
very common topology of linear regulator is the Low-DropOut reference increasing the robustness of the circuit providing
(LDO) illustrated on Fig (1). The supply voltage is considered immunity against process variations. Another motivation for
the input of the circuit and the negative feedback circuit, this choice is that this chip count with an output voltage level
through the PMOS transistor M1, regulates the amount of sensor, so the variable reference is necessary to test this part of
current I1 that is delivered to the output node Vout. This circuit the circuit. Nevertheless R ext was designed with a commercial
need a voltage reference Vref that is commonly generated by a value so a potenciometer is not strictly necessary.
Bandgap circuit [3]. The reference is compared against the
feedback signal Vfb resulting an error signal that drives the M 1 V ref =BPOS−( I ref ×R ext ) (2)
channel opening in function of the load current Iload and thus
maintain Vout in the designed level as expressed in equation Another topology for this circuit is adopted on the floating
(1). The negative feedback makes I 1 variate in the same ground circuit of [6]. The floating reference is generated using
amount that Iload to maintain Ibias constant. This topology is a buffered low voltage reference, protection high voltage
named LDO because the circuit can deliver an output that transistors and two integrated resistors. With this topology a
present only a low voltage drop in relation to the input, good resistors matching is critical to reduce the dependence on
corresponding to the saturation voltage VSD of the transistor the resistors absolute values variations. This solution present
M1. the advantage that the circuit is fully integrated, but in this
application the tuning feature was considered very important,
R1× R2 so the presented topology was adopted providing a small area
V out =V ref ×( ) (1)
R2 solution.
The capacitor Cstb is not strictly necessary in all projects, it is B. Linear regulator loop
designed to ensure the loop stability imposing a dominant pole The negative feedback loop of the regulator is implemented
in the negative feedback. For a further information about by the high voltage operational amplifier AO1 and the high
theory and design of linear voltage regulators we recommend voltage NMOS transistor NHV3 presented inside the blue
to consult [4]. dashed trace on Fig (2). Notice that the feedback signal is

connected to the positive input of the amplifier AO1, this is

due to the common source configuration of the transistor N HV3
that include a negative gain into the loop, so multiplying the
positive gain of AO1 and the negative gain of N HV3 results the
total negative gain of the feedback loop. It can be observed too
that there are no feedback resistors as in the linear regulator
exposed in Fig (1), this is because this regulator was designed
to copy the reference voltage Vref to the output Vout, so the
voltage gain is unitary as it is established in equation (3).
There is no need place resistors to obtain the output voltage
value. An external capacitor Cext is connected at the regulator
output to impose a dominant low frequency pole and ensure
the loop stability.
A high side load, for example a gate driver or an isolated
comparator, can be supplied between BPOS and the output of
the regulator. The current across the load is drained by N HV3
that, through the feedback loop, regulates the channel opening
in function of the load consumption. In this work the current
range was specified to feed a load that consume between 20uA
to 80uA. The source node of the N HV3 transistor is connected to
the pre-regulator output that provide a floating voltage VPR,
few volts under the regulator output, working like a
pseudo-ground. It was necessary to provide this pre-regulator
voltage to keep the regulator loop in linear region.
Fig. 3. Voltage level sensor implemented through a current comparator.
V out =V ref (3)
I bias =I load +I PR (4)
C. Pre-regulator
A floating voltage named VPR is generated by the V PR= BPOS−(V sg2 +V sg3+V sg4+V sg5 ) (5)
pre-regulator circuit composed by the PMOS high voltage
transistors PHV1, PHV2, PHV3, PHV4 and PHV5 illustrated inside the IV. VOLTAGE LEVEL SENSOR
green dashed trace in Fig (2). This voltage was not considered
as a possible solution to implement the floating ground Facing the need to sense the regulator output we designed a
because its variation on worst cases can reach almost 2V. This novel floating voltages comparator that generate a low voltage
variation is acceptable for the floating regulator logical signal advising the state of the regulator. This signal is
pseudo-ground application but would be excessive for the intended to systems that require determine if the regulator is in
regulator output. proper operating conditions. For the all range of supply, when
A bias current source provide the Ibias current that is the the floating ground reach the designed threshold voltage
addition of the regulator current I load and pre-regulator current difference against BPOS, the logical output of the sensor is
IPR as is expressed in equation (4). Those currents can vary in turned on. Otherwise the logical signal is 0V avoiding
function of the load current consumption but the addition malfunctions or damages.
remains approximately constant. The transistors PHV2, PHV3, In absence of floating voltage references, besides the one
PHV4 and PHV5 are connected as four cascade diodes, shorting generated by the regulator that can not be used with this end,
each gate with drain nodes, resulting in a total voltage drop the level of the regulator output can not be determined directly
through them expressed in the equation (5). The gates of P HV1 by a voltage comparator. The purpose of this circuit is
and PHV2 are connected resulting a current mirror. The area of generate a low voltage signal proportional to the voltage
PHV1 is 8 times bigger than PHV2 so the current across them difference between BPOS and Vout so this can be compared
have this ratio too, draining the most part of the current I PR with a low voltage reference. The proposed solution for this
through PHV1. Those current ratios imply that against variations task is the circuit illustrated in Fig (3). The regulator output
of the current Iload, that will make IPR variate too, the current Vout is replicated by a high voltage buffer so no current is
through PHV2, PHV3, PHV4 and PHV5 will variate in a much smaller drained from the regulator. The supply voltage BPOS and V out
proportion, so their source-gate voltage drops V sg2, Vsg3, Vsg4 generates proportional currents, I1 and I2 respectively, as is
and Vsg5 maintains almost the same values. Thus this calculated in equations (6) and (7). Those currents are copied
pre-regulator circuit provide a floating output voltage VPR that through current mirrors composed by the transistors N HVa1,
present small variations amount against supply voltage or NHVa2, Na1, Na2 and Pa1, Pa2 for I1, and NHVb1, NHVb2, Nb1, Nb2 for
current variations. I2. The I1 current copy is provided by the PMOS transistor P a2
and the I2 copy is received by the NMOS transistors N HVb2 and

Nb2, so the current Idif that flows across the Rsensor is the
difference between I1 and I2. The transistors NHVa1, NHVb1, Na1,
Nb1, NHVa2, NHVb2, Na2, Nb2 were sized with a wide area, thus the
variations on the currents I 1 and I2 modify the voltages Von1 and
Von2 only some tens of millivolts. The resistors R were sized
with very high values, 2MΩ each one, thus the maximum
current across them is less than 17uA. A high current value
through those resistors, besides increase the chip power
consumption, would implied a high dissipated power through
the resistor and heat dissipation, risking to damage the circuit.
Furthermore, the high value of those resistors that implies a
low Von1 and Von2 allow to assume the approximation done on
equation (8).
( BPOS−V on 1)
I 1= (6)
R
(V out −V on2 )
I 2= (7)
R
(BPOS−V out )
I dif =( I 1− I 2 )≈ (8)
R
R sensor
V sensor = I dif × R sensor≈( BPOS −V out )×( ) (9) Fig. 5. Transient simulation of the floating regulator with a variable load
R
connected switching between BPOS and Vout. The red trace is BPOS; the
green trace is Vout; the blue trace is VPR.
if (V sensor > V BG )V POR =5 V ; else V POR= 0 V (10)
V. SIMULATIONS
The current difference Idif across the resistor Rsensor cause a
voltage drop Vsensor expressed on equation (9). The voltage After implement the layout of the designed circuits
Vsensor is compared against a voltage reference V BG generated post-layout simulations were done to consider parasites
by a Bandgap circuit. The resistors R and Rsensor ratio is components, due to the routing and block interconnections,
designed to generate a V sensor voltage equal to VBG when the checking the behavior of the circuit with a more realistic
difference between BPOS and Vout is 4.3V. The threshold value model. The layout of the all circuit is illustrated on Fig (4),
can be changed just adjusting this resistors ratio. The resulting including the floating regulator and the level sensor. The total
function for the output signal VPOR is expressed on (10). area of the circuit is 599µm x 909µm divided in 599µm x
329µm for the floating voltage regulator and 599µm x 580µm
for the level sensor. All corners were considered on
simulations checking the behavior of the regulator and the
sensor against process variations, operating condition
variations and missmatch. Also were considered the Operating
Condition Check (OCC) [7] simulations to ensure that the
components are not over stresses on normal operating
conditions. This is a very important simulation on high voltage
applications because of the risk to expose components against
breakdown voltages.
On Fig (5) are illustrated the pre-regulator output V PR and
the regulator output Vout on a transient simulation. The supply
voltage BPOS is varied from 8.5V to 35V causing that V PR and
Vout variate too, a load is connected between BPOS and Vout
switching its current consumption between 20uA and 80uA
periodically. It is visible that both outputs keep approximately
the same voltage difference against the supply in the all range.
The pre-regulator output VPR present a small variations due to
Fig. 4. Layout of the complete circuit; inside the yellow shape are the the current switching that is considered normal for this
reference circuit and the linear loop regulator; inside the pink shape is the topology, this variation is not propagated to the regulator
pre-regulator; inside the green shape is the level sensor; inside the white output. The circuit pass the OCC simulations confirming that
shape are current mirrors to copy the bias currents of the all circuit. The total all components stay in the safe operating conditions.
area is 599µm x 909µm.

connected in parallel to Rext, so varying the voltage reference

the output of the regulator vary too and thus can be
determined the threshold value sensing the VPOR signal.
The measured values of the floating regulated voltage and
the voltage level sensor are exposed on table (1) and the
statistical density functions of both signals are illustrated on
Fig (8). In table (1) are exposed the mean, the standard
deviation and the worst case considering all measurements
taken for the all supply voltage range on the six samples. For
the voltage regulator output the mean value measured was
5.009V, with a standard variation of 2.5% and the measured
worst case present less than 5% variation under the designed
value. The transistors of this technology are characterized to
work under a voltage difference of 10% so this results reach
the specification and are considered good for this application.
Name Mean Standard Worst case

deviation
Vout BPOS – 5.009V 125mV BPOS – 5.21V
VPOR threshold BPOS – 4.226V 86mV BPOS – 4.1V
Table 1: Measures for the regulator output Vout; and the level sensor
threshold VPOR_TH.
Fig. 6. Transient simulation of the voltage level sensor. The red trace is The measurements of the threshold voltage of the level
BPOS; the green trace is Vout; the blue trace is VPOR. sensor have a mean value of 4.226V under the supply voltage,
with a standard variation of 86mV and the worst case present
A transient simulation of the sensor circuit for the same range a variation 200mV under the designed value. In all the chip
of supply considered on the simulation exposed before is samples the VPOR signal, that advice the state of the regulator,
shown on Fig (6). The input signal of the sensor is the output was turned on correctly when the regulator reach the operating
of the voltage regulator named Vout, this signal was varied level.
crossing the threshold of the sensor many times. It can be
observed how the sensor output VPOR turn on and turn off when
Vout cross the threshold value for the all supply range.
VI. MEASUREMENTS
The regulator and sensor circuits were fabricated, as part of a

bigger project, to supply high side drivers and over current
sensors whose switching behavior impose a variable current
consumption. The current that the connected circuits consume
vary between 20uA and 80uA. The measurements were done
on six different samples of the chip. On Fig (7) is shown a gate
driver output signal on the oscilloscope, the gate driver circuit
is supplied within BPOS and the floating regulator output. In
this test the supply voltage was set at 20V, the measured wave
switch correctly between 20V and 15V. The supply voltage
was varied in the range of 8.5V to 35V verifying the correct
output voltage levels of the driver, proving the correct
behavior of the designed circuit.
Fig. 7. Test measurement on oscilloscope of a driver output connected within
The measurements of the regulator and the level sensor were the supply of 20V and the regulator output of 15V.
done for low, medium and high voltage on the six chip
samples, generating a measures data matrix. The output of the
floating regulator was measured without tune, with a VII. CONCLUSIONS
commercial resistor to fix the voltage reference, so all the
samples were measured with the same resistor. This resistor is In this work was presented the design, implementation and
named Rext and is illustrated on Fig (2). To measure the the measurements of a floating voltage regulator, able to
threshold voltage of the level sensor a potenciometer was provide a high side floating ground 5V below a supply voltage

that can vary in the range of 8.5V to 35V. In addition, the [3] Banba, H.; Shiga, H.; Umezawa, A.; Miyaba, T.; Tanzawa, T.; Atsumi,
S.; Sakui, K., "A CMOS bandgap reference circuit with sub-1-V
regulator output is sensed by a monolithic circuit that provides
operation", IEEE J. Solid-State Circuits vol. 34, no. 5, pp. 670–674.
a low voltage logical signal controlling the state of the
regulator. The test results demonstrate the correct behavior of [4] G. Rincon-Mora. Analog IC Design with Low-Dropout Regulators. New
the designed circuits, thus, verifying that the proposed York, NY: McGraw-Hill Inc., 2009, pp. 1-43.
topology is a valid choice for this application. This project was
customized to a load that presents a current consumption [5] A. S. Sedra and K. C. Smith. Microelectronic Circuits. New York, NY:
varying between 20uA and 80uA, the chosen topology can by Oxford University Press, 2004, pp. 253-255.
easily scaled to design a regulator that supply a different load
current range. The circuit occupies a total area of 599µm x [6] Biziitu, F., “On-chip 500uA at 5V above battery Dual-Chain Dickson
909µm, among them 599µm x 329µm is occupied by the Charge Pump with Regulated Clock Supply”, International
Semiconductor Conference (CAS), vol. 2, pp. 203–206.
voltage regulator and 599µm x 580µm by the level sensor. The
floating regulated voltage reach an accuracy of 2.5% standard
[7] X-FAB Semiconductor Foundries, “Application Note SPICE Models &
deviation from the designed value. Simulations”, Release 1.3, March 2014.
Fig. 8. Distribution functions of a) the floating regulator output voltage and

b) the level sensor threshold.
ACKNOWLEDGMENT
The authors wish to thank the grant provided by CNPq

Brazilian Research Agency for partial support of this work.
REFERENCES
[1] Kuo-Hsing Cheng, Yu-Lung Lo, Wei-Bin Yang “A Novel Power-On
Reset Circuit Without Capacitor”, in 6th WSEAS Int. Multi-Conf. on
Circuits, Systems, Communications and Computers, Crete, Gr., 2002,
pp. 102-104.
[2] K. Yasunaka, “Power-On Reset Circuit and High-Frequency

Communication Device”, Japan Patent WO2016063597, Apr, 28, 2016.

Design and Characterization of Hall Plates in a

0.5µm CMOS Process
Nicolás Ronis and Mariano Garcia-Inza
Abstract—Four different N-well Hall Plate geometries were Section IV shows the Hall Plates designed, its parameters, as
designed and fabricated in a 0.5µm CMOS process provided by well as the current spinning technique used in the
MOSIS. Different shapes, sizes, contact distribution and measurements. In Section V, the Hall voltage, sensitivity and
dimensions were used in order to characterize Hall Plate resistance measurement results over temperature are shown.
sensitivity and resistance in a range of temperatures from -40°C Section VI introduces the model used for the Finite Element
up to 165°C. To remove the offset a four-phase current spinning
Method (FEM) simulation, the results obtained and a
method was used. The results show a better sensitivity
performance in the cross-shaped whereas the small square shape comparison with the measurements is shown. Finally in
has a slight improvement in the SNR behavior. The sensitivity of Section VII the conclusions of this work are shown.
the different Hall Plate geometries was simulated using a model
based on finite-element showing good agreement with the II. HALL EFFECT
measurements.
A. Equations
Index Terms—Hall Plate, CMOS design, Solid state magnetic The Hall voltage ( ) in an ideal Hall Plate (i.e. infinitely
field sensor long with punctual contacts) can be expressed as follows[2]
I. INTRODUCTION
= (1)
A magnetic transducer has as purpose to turn the sensed
magnetic field into voltage. They can be found in many
applications such as printers, TV, scanners, automotive where is the Hall Plate thickness, is the Hall Plate bias
industry, etc. current, is the external perpendicular magnetic field and
The Hall effect was first discovered in 1879 by Edwin Hall is called Hall coefficient given, for an n-type semiconductor,
[1]. This effect is the manifestation of the Lorentz Force, by
which will appear over mobile charges exposed to an external
magnetic field. This force will push positive and negative
charges in opposite directions causing the appearance of a Hall =− (2)
electric field and hence a measurable Hall voltage.
A Hall Plate consists in a doped semiconductor section, where is the electron concentration, is the electron charge,
defined by a width, a length and a thickness where the Hall is the anisotropy factor and is the Hall scattering factor
effect takes place. It has two pairs of contacts, one for sensing
which is dependent both on temperature and scattering
and one for biasing. It can be made by different materials, but
mechanism.
as it will be seen later, low doped n-type materials are
In a Hall Plate we can find two different electric fields. In
normally used.
This paper begins with an introduction to the equations of the absence of external magnetic field, only an external
the Hall effect and the influences of the geometry in the Hall electric field, , exists, responsible of the current flowing
Plate behavior. In Section III, important aspects of the Hall and collinear with the current density lines, . When a
Plate treated as a sensor (sensitivity, temperature behavior) are magnetic field is applied, the Lorentz Force will cause the
shown. appearance of a new electric field, called Hall electric field
, perpendicular to the first one. Therefore, the total electric
Manuscript received June 10, 2016. This work was supported by field, , in the Hall Plate has two components
Universidad de Buenos Aires, grant UBACyT Q025 and by Facultad de
Ingeniería, Departamento de Electrónica. The integrated circuit was designed
using Mentor Graphics tools under the Higher Education Program (HEP). The = + =( , , 0) (3)
chip was fabricated through the MOSIS foundry service supported by the
MOSIS Educational Program (MEP).
Nicolás Ronis is with the Microelectronics Laboratory, Universidad de resulting that the current density lines and the total electric
Buenos Aires, Argentina. field are tilted by a an angle called Hall Angle, " .
Mariano Garcia-Inza is with the Device Physics - Microelectronics
Laboratory - INTECIN, Universidad de Buenos Aires - CONICET, Argentina.

electric field is
01 3, 0 3, 0 (8)
replacing (8) in (6) we obtain
'0 3 (* (9)
This result shows that only the component of the current

density lines parallel to the contact boundary contributes to the
Hall voltage. This "loss" of current density lines due a real
Fig. 1. Boundary conditions in a Hall Plate [2] geometry can be expressed as
B. Geometry influence 4 5 (10)

In an ideal Hall Plate, the current density lines are parallel
to the boundary in all its path and the equipotential lines are where 4 is known as the geometrical correction factor of the
tilted by a Hall angle with respect to its position without Hall voltage and 5 is the Hall voltage seen in the case of an
external magnetic field. When dealing with real geometries, ideal Hall Plate (1). For an infinitely long Hall Plate,
the boundary conditions that the geometry imposes (Fig. 1) 4 ~1whereas for a extremely short 4 ~0, therefore 0 7
have to be taken into account. 4 7 1.
In an isolated boundary, the current density lines have only
a tangential component, which means III. HALL PLATE AS SENSOR
∙ $% = 0 (4) A. Sensitivity
The sensitivity of a Hall Plate is given by the variations of
where $% is a unit vector normal to the boundary. When an the Hall voltage due the variations of the magnetic field in a
external magnetic field is applied, the electric field will be set of operating conditions Q
:
tilted by a Hall angle.
In the vicinity of a contact, since no tangential component 8 9 9 4
: ;
(11)
of the electric field can exist, only a normal component for the
electric field appears
A Hall Plate can be biased by either a constant voltage over
∙ $& 0 (5) temperature (voltage driven) or a constant current over
temperature (current driven). In this work we will focus on the
where $& is a unit vector tangential to a contact. In this case,
first case.
For a voltage driven, the sensitivity can be expressed as
when a magnetic field is applied, the current density lines will
be tilted by a Hall angle.
Analyzing a real geometry of a Hall Plate, the Hall voltage 8 4 (12)
can be obtained solving (6) where A and B are two opposite
contacts (in the y direction) lying in the same equipotential where is the bias voltage and is the Hall Plate
plane in absence of magnetic field. resistance, which in the case of a square geometry can be
expressed as
' ∙ () = 1 =
<
(6)
(13)
> ?@ >
where () 0, (*, 0 and is the total electric field present where > and = are the width and the length of the Hall Plate
in the Hall Plate given by (3) where respectively, < its resistivity and ?@ the electron mobility.
Combining (12) and (13) and dividing by the sensitivity
+ , - ./ (7) in , ⁄4 ∙ / can be expressed as
>
As it can be seen in Fig. 1, in a real geometry, the current 8B 4 ?
density lines have two components 0 , 01 , 0 . Applying a = @ (14)
perpendicular magnetic field in the 2 direction the total

B. Temperature variation
When analyzing the temperature variation of the sensitivity
in a voltage driven Hall Plate is easy to see that the only
parameters in (14) that vary with temperature are the
scattering factor and the mobility. However, the variation of
the first one is negligible compared with the mobility,
therefore the sensitivity variation with temperature will follow
the mobility variation, which can be expressed as [3, 4]
7.4 - 10K D EL.MM

?@ 88D@E .GH
15
OP
(a) (b)
1 N [ 0.88D@E .R\S
QR.LS-R TU VWX.Y Z
where ^_ is the doping level, D is the temperature and D@

300⁄D .
IV. DESIGN AND IMPLEMENTATION

A. Hall Plates
Four different Hall Plate geometries were designed in a
0.5?a CMOS ONC5N/F process provided by MOSIS. As it is (c) (d)
shown in (14) the mobility plays an important role in the Hall
Fig. 2. Designed Hall Plates in a CMOS process. (a) Big square shape. (b)
Plate sensitivity. For this reason, an n-type material, N-well Cross-shaped. (c) Orthogonal square shape. (d) Small square shape.
for this particular process, was selected for the design.
Some important points had to be considered previous to the
design. First, in order to be able to apply the current spinning where
technique [5], the Hall Plates must be symmetrical, which
means that their sensing and bias contacts must be 1
eff |c ° g i (17)
interchangeable. Second, the contacts should be placed such 2 2 ∆
that they lie in the same equipotential plane in the absence of
external magnetic field. If now the current is rotated 90° as in Fig. 3(b) the bridge
The Hall Plates designed can be seen in Fig. 2 and their voltage is
geometric parameters in TABLE I.
L R | ° eff | ° (18)
TABLE I
Geometric dimensions of the Hall Plates designed. where
PARAMETER HP1 HP2 HP3 HP4
1
eff | ° g i
W [µm] 80 40 80 40 (19)
L [µm] 80 40 80 40 2 2 ∆
W contact [µm] 5.1 39.1 39.1 3.1
L contact [µm] 5.1 3.1 3.1 3.1 Since |c ° | ° and eff |c ° eff | ° , averaging
Arm [µm] - 40 - - (16) and (18) will remove the offset.
In this work a four-phase current spinning was used, having
a better offset removal. In order to be able to apply this
B. Current Spinning method, a 2-bit decoder and MOS switches for bias rotation
An ideal Hall Plate can be modeled as a balanced were designed and implemented in the same chip. Since these
Wheatstone bridge. But from many different causes [6] a Hall
Plate suffers from offset, which can be seen as a variation in
one of the resistors in the bridge. Taking this into account, the
voltage across the bridge can be expressed as the Hall voltage
in addition to an offset voltage. In order to remove the latter,
the current spinning technique was used in this work. It
consists in making the current flow in two opposite directions,
called phases and then averaging the result.
The Fig. 3 shows an unbalanced Wheatstone bridge with the
current flowing in the two phases. In the case of Fig. 3(a) the
voltage across the bridge can be expressed as
(a) (b)
L R |c ° eff |c ° (16) Fig. 3. Current spinning technique (a) Phase 90° (b) Phase 0°

6
5
1 2
3 4
100µm
Fig. 4. Microphotograph of the fabricated integrated circuit. 1)HP1, 2)HP2,

3)HP3, 4)HP4, 5)Bias switches, 6)Phase and Hall Plate selectors
switches are in series with the Hall Plates, special care has to
be taken regarding their dimensions. However, for this work, Fig. 5. Hall voltage vs. Magnetic Field for the Hall Plates biased with 4V.
the voltage across the Hall Plates was measured directly from
their contacts, accessible through the package pins, so no error With this result we can say that the Hall Plates designed
was introduced due switches resistance. Also accessible from showed a linear behavior in the range of the magnetic field
outside are the inputs of the 2-bit decoder which is used to tested and up to 4V bias.
select the desired phase intended to be measured. In addition,
another 2-bit decoder was used to select the desired Hall Plate. B. Temperature
Fig. 4 shows a microscope capture of the fabricated chip.
Sensitivity and resistance measurements were done in a
temperature range from -40°C up to 165°C. To do so, the chip
V. MEASUREMENTS
was placed in a thermal chuck. Special care was taken at low
The measurements made in this paper aim to characterize temperature, applying the baking technique in order to ensure
the sensitivity, resistance and the variation of these parameters that all the surrounding humidity was removed.
with temperature. The Fig. 6 shows the normalized temperature sensitivity
calculated using (20) as well as the normalized mobility using
A. Sensitivity (15). It can be seen that at -40°C the sensitivity increases 40%
whereas at 165°C it decreases up to 50% of its value at room
During the sensitivity measurements, external and temperature. Fig. 6 confirms what is was stated in Section III,
perpendicular magnetic fields were applied with bias voltages that in a voltage driven Hall Plate, the sensitivity variation
of 2V, 3V and 4V. The results are summarized in the TABLE over temperature follows (15).
II. Through the sense of the current in the bias contacts the
Hall Plate resistance was measured for the different
TABLE II temperatures. Results are shown in the Fig.7.
Sensitivity measured for each Hall Plate
HALL PLATE SENSITIVITY [µV/G·VBIAS]
HP1 3.00
HP2 4.08
HP3 3.09
HP4 3.64
From the results obtained, it is clear that the HP2 has a

better performance regarding sensitivity. This confirms our
assumptions, since the geometry this Hall Plate has benefits
the confinement of the current density lines parallel to the
sense contacts having, as a result, a better geometrical factor.
The Fig. 5 shows the results obtained from the sensitivity
measurements at room temperature for a 4V bias. The dots
represent the measured values while the curve was constructed
using least squares by a second order polynomial. It can be
seen that the quadratic term is negligible whereas the linear
term fits the sensitivity value, in [V/G] given in TABLE II. Fig. 6. Normalized sensitivity and mobility over temperature

8m n maom p m D
^j a kl2m( 8m n (20)
8m n 25°q
It can be seen that the resistance increases with temperature.

This is expected since when the temperature increases, the
thermal energy of the electrons increase and so it does the
collisions, causing a decrease in the conductivity.
In Fig.8 the variation of the resistance with respect to its
nominal value at 25°C, calculated using (21) is shown
D 25°q
∆ % - 100 (21)
25°q
As it is shown, the four Hall Plates have the same variations

which is, actually, the N-Well resistance variation for the
ONC5N/F process. The result shows that it doubles its value at Fig. 8. Resistance variations over temperature with respect its nominal value
165°C and is reduced to 35% at -40°C. at room temperature.
Treating the Hall Plate as an N-well resistor, it will
present thermal noise given by
with
O √4tD (22) v
v v11
1 xy z L (24)
where t is the Boltzmann constant, D the temperature, the
resistance value and the bandwidth.
vxz
v 1 v1
1 xy z L (25)
VI. FINITE ELEMENT METHOD SIMULATION
In order to have a model that can predict the Hall Plate where the conductivity v is
behavior in this process, a computational model based on
finite elements was done. To do so, first we had to use a L
z
v (26)
physic model in which we can express the conductivity as a a∗
tensor [7], such that
being z the time between collisions and a ∗ the electron
effective mass. The parameter xy is the cyclotron frequency
0 v v1
N0 [ uv v11 w ∙ N [ (23) given by
1 1 1
3
xy (27)
a∗
The Fig. 9 allows to compare the results obtained by the

measurements (M) with the results obtained by FEM
simulations (S), made using Elmer software, for a 4V bias. It
can be seen that the extrapolation curves obtained from the
FEM simulations are almost coincident with the
measurements. The TABLE IV summarizes the values of the
sensitivity obtained with both methods. In the worst case, the
simulations shown a discrepancy of 7.1% with respect to the
measurements, allowing us to conclude that the FEM
simulation, and in particular the model used, is a precise tool
to predict a Hall Plate sensitivity behavior.
Fig. 7. Hall Plate resistance vs. temperature

REFERENCES
[1] E. H. Hall, “On a new action of the magnet on electric
currents”, American Journal of Mathematics, vol. 2, np. 3,
1879, pp. 287-292.
[2] R. S. Popovic, Hall effect devices. Philadelphia, PA: CRC
Press, 2003.
[3] N. D. Arora, J. R. Hauser, D. J. Roulston, “Electron and
hole mobilities in silicon as a function of concentration and
temperature”, IEEE Transactions on Electron Devices,
vol. 29, np. 2, 1982, pp. 292-295.
[4] E. Ohta, M. Sakata, “Temperature dependence of Hall
factor in low-compensated n-type silicon”, Japanese Journal
of Applied Physics, vol. 17, np. 10, 1978, p. 1795.
[5] A. Bilotti, G. Monreal, R. Vig, “Monolithic magnetic Hall
sensor using dynamic quadrature offset cancellation”, IEEE
journal of solid-state circuits, vol. 32, np. 6, 1997, pp. 829-
836.
[6] A. A. Bellekom, “Origins of offset in conventional and
spinning-current Hall plates”, Ph.D. dissertation, Dept. Elect.
Eng., Delft Univ. of Technology, Delft, Netherlands, 1998.
Fig. 9. Hall voltage obtained from the measurements (M) and FEM [7] J. R. Brauer, J. J. Ruehl, B. E. MacNeal, F. Hirtenfelder,
simulations for a 4V bias.
“Finite element analysis of Hall effect and
magnetoresistance”, IEEE transactions on electron
TABLE IV devices, vol. 42, np.2, 1995, pp. 328-333.
Sensitivity comparison between measurements and FEM
simulations
Sensitivity [µV/G·VBIAS]
HP Measurements FEM Error [%]
HP1 3.00 2.94 2.0
HP2 4.08 3.9 4.4
HP3 3.09 3.31 7.1
HP4 3.64 3.38 7.1
VII. CONCLUSIONS
In the present work four different Hall Plate topologies were
designed, characterized and fabricated in a 0.5µm CMOS
ONC5N/F process provided by MOSIS. The Hall Plates
implemented had differences both in the geometries and in the
contacts size and position.
Results showed that the HP2 has a better sensitivity
performance due the high geometric factor this geometry can
achieve. The HP4, although it has a lower sensitivity, showed
the best behavior regarding SNR at the expense of an increase
in the current consumption. The results of the measurements
confirmed that the fabrication process used in this paper
allows the development of Hall Plates with good
performances, since the results obtained are comparable with
existing data.
A Hall Plate model based on FEM was developed. Results
showed a worst case error of 7.1% in comparison with the
measurements, which allows us to say that the model
developed and the FEM simulations are a precise tool in order
to predict the behavior of the Hall Plate sensitivity.

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2016

DDepartamepartamenento de Elto de Electrectrootecnia -

Universidad Nacional del Sur

Pedro Julián, Andreas G. Andreou, Editors

Copyright and Reprint Permission: Abstracting is permitted with credit to the

Marcelo Moreyra Pedro Julián – Andreas G. Andreou

Aboushady University of Pierre and Marie Curie

High-Level Simulation of an FSK Modulator Based on Memconductor . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Aguila-Cuapio, Luis Enrique 1

Garcia Retegui, Rogelio 33

Van Noije, Wilhelmus 46

High-Level Simulation of an FSK Modulator Based

ISBN 978-1-5090-3777-3/16/$31.00 ©2016 IEEE 1 IEEE Catalog Number CFP16H30-ART

Fig. 3. Frequency-dependent pinched hysteresis loop of Fig. 2.

Fig. 2. SIMULINK model of (1). −0.5

in Section IV. Finally, some conclusions are summarized in (a)

II. M EMCONDUCTOR M ODEL 6

Among all the memristor emulator circuits reported in the 5

literature, the simpler emulators and with better performance

high-frequency. Herein, the charge-controlled grounded mem-

ISBN 978-1-5090-3777-3/16/$31.00 ©2016 IEEE 2 IEEE Catalog Number CFP16H30-ART

Fig. 5. SMCO based on SRCO taken from [26].

positive or negative pulse signal applied to the memconductor,

behavior obtains for the decremental topology, only that here,

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ISBN 978-1-5090-3777-3/16/$31.00 ©2016 IEEE 5 IEEE Catalog Number CFP16H30-ART

Development of a sCMOS Interoperable Process

I N this paper, the development of an Interoperable Process

(a) Standard cells. (b) Oscillators.

Fig. 1. Pitch and grid [8]. B. Results

VI. T EST C HIP

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Using this iPDK a set of standard cells were designed to be

Minumun CMOS inverter propagation delay

Fig. 7. Layout of the pmos PyCell.

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Fig. 8. Layout of the HR_res PyCell.

Fig. 9. Layout of the capacitor PyCell.

ISBN 978-1-5090-3777-3/16/$31.00 ©2016 IEEE 10 IEEE Catalog Number CFP16H30-ART

Measurement of the Read-Out Noise of Fully

Abstract—Fully depleted thick CCDs have been designed

PULSE() 40 -12.5 -22

MSF CT = CSN + CW + CGD,M SF + CGD,M RST (1)

surements at sea level is shown in Fig. 2: muon tracks

IV. E XPERIMENTAL S ET-U P

that is generated during the shifting of the charge packets [3],

out electronics, and is the subject of study in this work. These

in equation 7 they are added in quadrature. Data U−side

also the thermal noise due to the resistor RL . The frequencies

vol. 9, no. 1, pp. 1-12, 1974.

The external electronics adds a noise floor of 0.87 e− , and

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Modelling Approach for Low-Frequency Strongly

Abstract—This work describes the characterization of a three

ISBN 978-1-5090-3777-3/16/$31.00 ©2016 IEEE 17 IEEE Catalog Number CFP16H30-ART

Finally the efficiency of the complete system is:

Table I: Coil characteristics (radius, wire diameter, number of

Figure 4: Subcircuits for L2 and L3 A. Mutual inductances

ISBN 978-1-5090-3777-3/16/$31.00 ©2016 IEEE 18 IEEE Catalog Number CFP16H30-ART

• Approximation given by Microchip AN710 [10]

B. AC resistance and self-inductance

γ ber(γ)bei0 (γ) − bei(γ)ber0 (γ)

ISBN 978-1-5090-3777-3/16/$31.00 ©2016 IEEE 19 IEEE Catalog Number CFP16H30-ART