Evolution of CMOS Ring Oscillator

NOR SAMIDA YAACOB

p91116@siswa.ukm.edu.my
Department of Electric, Electronic & System
Faculty of Engineering & Built Environment
National University of Malaysia

ABSTRACT

Over the past few decades, CMOS technologies continue to be scaled down in order to lower costs,
increase speeds, and achieve a higher level of integration. As a result, CMOS has flourished in
wireless communication applications. This review will serve as a comparative study and reference
for researches working on voltage-controlled Ring Osscilator(VCO), ring oscillator-based True
randon Number generator (TRNG) and ring oscillator-based time-to-digital converters (TCDs )
in noise performance and low power consumption..

INTRODUCTION

A voltage controlled oscillator (VCO) is one of the most important basic building blocks
in analog and digital circuits. There are many different implementations of VCOs. The two main
topologies of CMOS VCOs are ring VCO and inductance (L)capacitance (C) VCO. Ring oscillator
based VCO is commonly used in the clock generation Subsystem. The main reason of ring
oscillator popularity is a direct consequence of its easy integration. LC VCO designs have a large
quality factors (Q), the reason for their superior noise and frequency performance. Ring VCO
structures consume less area and power. They also are less complex in design compared to their
LC counterparts. Ring oscillators can be built in standard CMOS process. They can provide a
superior tuning range as well as multiple output phases. Ring VCOs can further be classified as
differential and single ended oscillators. The former gives better noise performance while the latter
is easy to design [25].
With the extremely rapid development of integrated circuits, smart cards have been widely
used in electronic financial transactions, identification and wireless communication systems.
Power and area are limited resources in most smart cards. However, most TRNGs mentioned
above have either high power consumption or low statistical property. A low-cost low-power ring
oscillator-based TRNG with high randomicity for encryption. Fig. 1 illustrates the principle of a
ring oscillator-based TRNG. The ring oscillator-based TRNG is more robust to deterministic noise
and 1/f noise [13]. In addition, ring oscillator-based TRNGs are easy to be implemented and
occupy small area, suitable to be integrated in low-cost low-power systems such as smart cards
and RFID tags.

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 Fig. 1. Diagram of ring oscillator-based TRNG

Time-to-digital converters have been a hot researchtopic over a few years. However, the
time resolution provided by self-loaded inverters does not always satisfy all TDC requirements,
and thus different kinds of solution based on Vernier algorithm and noise-shaping were
investigated. TDCs can be divided into two categories according to their operating principles. The
analog-type TDCs use timeto- amplitude conversion, followed by an ADC. These TDCs achieve
good resolution and linearity at the expense of high power dissipation, large size, low scalability
with CMOS technology nodes, and high noise susceptibility. TDCs based on digital techniques
can be classified into delay-line-based TDCs and RO-based TDCs. RO-based TDCs can
simultaneously achieve high resolution and wide dynamic range, with small area and low power
dissipation. Fig. 2 shows the concept of basic RO-based TDC.

Fig. 2. Diagram of basic RO-based TDC

The aim of this article is to study several aspects of the voltage controlled oscillator (VCO), ring
oscillator-based TRNG and RO-based TDCs in tem of power consumption, noise performance and
comparison of RO-based TDCs.

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 RESEARCHES

Table 1: Performance comparison of phase noise and power consumption for voltage-controlled ring oscillator

Technology Frequency Phase Noise Power FoM

(nm) (dBc/Hz) (dBc/Hz)

[1] 65 645 MHz -110.8 10mW -157

(at 1 MHz)

[2] 180 1.1-2.3 -108.15 65mW -155.2

GHz (at 1 MHz)

[3] 180 0.479GHz - -93.3 13mW -154.4

4.09GHz (at 1 MHz)

[4] 180 1861 MHz -108 22mW -150.6

(at 1 MHz)

[5] 180 630 MHz -102 13mW -156.3

(at 1 MHz)

[6] 180 1.1GHz - -105.5 - -

1.86GHz (at 1 MHz)

[7] 500 900 MHz -105.5 15.4mW -157.1

(at 600 KHz)

[8] 600 900 MHz -117 30mW -165.7

(at 600 KHz)

[9] 180 0.075GHZ -101.1 9.3mW -153.7

to 6.9GHz (at 1 MHz)

DISCUSSION

As shown in Table I, [1], [4], [5], [6], [7] and [8] were implemented in 65nm, 180nm, 180nm,
180nm, 500nm, and 600nm CMOS technologies, respectively. The delay cells of [8] was used in
[4] and [6] which [6] report a high oscillation frequency of 5.9 GHz with good phase noise
performance. However, the FoM cannot be estimated to compare with other ring VCOs in Table I
because the power dissipation was not reported. In Table I, it can be seen that the FoMs of [7] and
[8] are better than those of [4] and [5]. Although the channel lengths of [5] and [4] are the same,
the FoM of [5] is better than that of [4]. However, the delay cell of [8] suffers from a narrow tuning
range at a low supply voltage. In the case of [4], the frequency tuning range is only 8.13% under
a tuning voltage of 1.6 V. If the supply voltage continues to be reduced with the development of
CMOS technology, the frequency tuning range would be narrower, and the delay cell of [8] will
be difficult to be used in wideband applications.

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Thus, new low-noise delay cells are required for an acceptable frequency tuning range at a low
supply voltage [1]. In spite of the low supply voltage and the short-channel technology whose
phase noise performance is inferior, [1] shows a frequency 645 and a FoM of −157 dBc/Hz, which
is similar to FoM of [7] and is 6.4 and 0.7 dB better than those of [5] and [4], respectively. which
can be used as a low-noise ring VCO for low supply voltage and scaled-down technology.

RESEARCHES

Table 2: Performance comparison of low power consumption for ring oscillator-based truly random number generator (TRNG)

Technology Chip area Power Bit rate Randomness Advantages

(μm²) (Mb/s)
TRNGs passed all NIST tests
[10] 65nm 920 0.289mW 8.2 High without pre-tuning to mitigate
process variation effects.
A low-cost low-power ring
[11] 130nm 5000 0.04mW 0.1 High oscillator-based TRNG

Constructed entirely using a

[12] 28nm 375 0.54mW 23.16 High standard cell library and
conventional place and route
tools, this design presents a
‘soft IP’ TRNG that passes all
NIST
randomness tests without post
processing.
Overcomes the
[13] 45nm 93.1 1.1mW 127 High need to use ring oscillators
with large number of stages to
amplify jitter
Enabling low-reported
[14] 45nm 4004 7mW 2400 High energy-consumption
use only a simple Von
[15] 250nm 104000 190mW 125 High Neumann
corrector, thus 4 times faster
throughput can be obtained
compare to previous design

[16] 180nm 50000 1.04mW 0.04 Medium

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 DISCUSSION

As shown in Table 2, [11] is fabricated in 130nm standard CMOS process, the proposed TRNG
has an area as low as 0.005 mm2. Powered by a single 1.8V supply voltage, the power consumption
is 0.04mW. The bit rate of the proposed TRNG after post processing in the SD card is 100 kb/s.
[12] which is using CMOS 28nm technology, TRNG generates random bits at 23.16Mb/s, while
consuming 0.54mW and 375μm2 area.
The demonstration circuit [13] was designed in a 45nm process. It occupies an area of 93.1μm²
and provides a throughput of 127 Mbps at a power of 1.1 mW. Simplicity of design, ease of
integration in CMOS, lower area, higher throughput and proven randomness makes this an
attractive alternative to traditional TRNG designs.
The power consumption of 7mw for [14] is higher than power consumption for [11].
[15] have been designed and fabricated by using HHNEC’s 0.25μm eFlash process with a supply
voltage of 2.5V. The chip area is 104000 μm² and high power consumption.
Power consumption of the TRNG for [16] with medium randomness is only 1.04 mW with a
minimum supply voltage of 0.8V, and its total chip area is 0.05 mm² but higher compare to
consumption in [11].

RESEARCHES

Table 3 : Performance comparison of RO-based Digital TDCs

Architecture Technology LSB CR Precision DR DNL INL Power Area Advantages

(nm) (ps) (Hz) (ps) (ns) (LSB) (LSB) (mW) (mm²)

improving
[17] 2-D Vernier 65 4.8 50M - 0.6 1 3.3 1.65 0.02 the
GRO resolution to
picoseconds
level

[18] Multi-Path 65 4.22 200M - 1 - - 2.2 0.02

GRO

[19] Basic RO 90 13.6 3.9M - 111. - - 18 0.02

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With two
[20] Vernier RO 90 5.8 25M - 40 - - 3.6 0.03 ROs
operating in
the Vernier
manner can
obtain
arbitrarily
fine
resolution
An
[21] 2-D Vernier 90 15 100M - 40 - - 2.16 0.04 improved 2-
RO D Vernier
RO TDC.

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 Yielded a
six time
reduction
of the
latency time
with no
compromise
on the
dynamic
range

[22] Free-running 130 50- 51M 1 - 0.5 0.5 - -

RO 300

[23] Vernier GRO 130 8 15M 3.35 32 - - 7.5 0.26

[24] Gateable 130 7.3 2.4M 11 9 3.2 1.2 1.2 0.03

Vernier RO

DISCUSSION

TDCs using Basic RO topology usually have a time resolution limited by the propagation delay of
the inverter. For example, the TDC in [19] implemented in the 90-nm CMOS technology had a
resolution of 13.6 ps. Basic RO-based TDC is its high power consumption because the RO is
working in free-running mode, e.g., 18 mW in [19].

TDCs using Multipath RO can improve the limited resolution achieved with the RO-based TDC.
The multipath RO-based TDC has been proposed and demonstrated in [18]. With this topology, a
fine resolution that is several times higher than the minimum propagation delay of an inverter can
be achieved. Using multiple-input inverters, the multipath technique is used to reduce the delay
per stage. Using this leverage multipath technique, the transition time of each delay unit can be
greatly speeded up.

TDCs using Vernier RO is an alternative technique to obtain high resolution is to adopt the Vernier
scheme.The propagation delays of elements in the slow RO and the fast RO are τ1 and τ2,
respectively. With two ROs operating in the Vernier manner, the resolution is determined by the
delay differences (τ1−τ2). Setting τ1 close to τ2, we can obtain arbitrarily fine resolution. A
resolution of 3.2 ps was reported in [20].

TDCs Gated RO was proposed [24] in order to reduce the power consumption of an RO-based
TDC. Several methods can be used to introduce the gating feature into the delay units. In one
method, gating transistors are inserted at both the top and bottom of a conventional inverter to
build the gated-inverter delay cell, such as in [18], [20], and [21]. When the gating transistors are
closed, the current path in the cell is cut off. Thus, the gated-inverter is off and its output will be
maintained by the capacitor at the output node. In another type, some specific logic circuits are
added into the RO. For example, in [23], the NAND gate, which had the exactly the same

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implementation as the inverter gate at transistor level, was used to add the gating feature and match
the propagation delay as other delay unit’s. In another example [24], a pair of multiplexers was
inserted between the delay units. Fig. 6 shows the principle of the GRO TDC with its timing
waveform.

TDCs 2-D Vernier RO: The techniques we have discussed so far mainly focus on improving the
resolution to picoseconds level. Nevertheless, in those solutions, the tradeoff between resolution
and latency time exists, which greatly limits the dynamic range at a given sampling frequency [17]
and [21]. A 2-D Vernier RO TDC was proposed and demonstrated as an effective solution for high
resolution and greatly reduced latency time.

An improved 2-D Vernier RO TDC prototype was reported in [21]. Through a specially designed
phase sequence in the delay line and a specific allocation, the whole Vernier plane was used. This
yielded a six time reduction of the latency time with no compromise on the dynamic range [21].

In Table II, a comparison of RO-based TDCs and variants reported in the past five years is
provided. The TDC based on the basic RO implemented in the 90-nm CMOS [19] achieved a 111-
ns dynamic range and moderate resolution (13.6 ps). However, due to its architecture, the power
dissipation was high, 18 mW. The multipath GRO TDC in the 65-nm CMOS [18] had a state-of-
the-art resolution of 4.22 ps, with small power consumption (2.2 mW) and compact size (0.02
mm2). With the help of 2-D Vernier GRO, the TDC reported in [21] achieved 15 ps resolution, 40
ns dynamic range, and 2.1 mW power consumption.

CONCLUSION

The phase noise is improved by eliminating the noise currents that are added for frequency tuning
during the output high–low transition. The VCO is implemented in a 65-nm CMOS technology.
At 645 MHz, the measured phase noise is −110.8 dBc/Hz at a 1-MHz offset frequency while
dissipating 10 mA at a 1-V supply. The FoM of the proposed VCO is −157 dBc/Hz. The proposed
VCO can be used as a low-noise ring VCO for low supply voltage and scaled-down technology.
The most low-cost low-power ring oscillator-based TRNG is designed and implemented in [11].
A tetrahedral oscillator with large jitter is employed to realize the TRNG.Measures to enhance the
randomness of ring oscillator-based TRNG is analyzed based on phase noise models and verified
by simulation.

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