180 IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO.

3, MARCH 2003

Fluorine-Assisted Super-Halo for

Sub-50-nm Transistors
Kaiping Liu, Jeff Wu, Jihong Chen, and Amitabh Jain

Abstract—The potential of using a fluorine-assisted super-halo

for sub-50-nm transistors is analyzed for the first time. The ca-
pability of producing a super-sharp halo using fluorine is demon-
strated by one-dimensional (1-D) SIMS profiles. The added ability
to tailor the halo profile using fluorine for different transistor cri-
teria on junction capacitance, tunneling current, roll-off, and
mobility is demonstrated. The impact of the resulting fluorine-as-
sisted halo dopant profile on the transistor characteristics is eval-
uated using TCAD simulations. Experimental data show that the
fluorine-assisted halo process results in lowered junction capaci-
tance and improved on – o characteristics for both nMOS and
pMOS.
Index Terms—Fluorine, halo, junction capacitance, MOSFET.

I. INTRODUCTION Fig. 1. Fluorine energy impacts on the nMOS halo profile sharpness and
the amount of halo dopant segregation into the heavily doped drain extension
Hdd
W HEN transistor gate length is scaled down, the impact
of the halo profile on device performance becomes
more important [1]-[2]. The halo profile not only determines
( ).

the magnitude of the transistor short-channel effect, but also II. SIMULATIONS AND EXPERIMENTS
impacts the transistor channel mobility, junction capacitance
A set of SIMS wafers consists of: 1) implants; 2)
( ), band-to-band tunneling current, and source–drain resis-
pre-halo fluorine implants with different energies at 1e15
tance. Since the profile of the halo is mainly determined by its
cm ; and 3) halo implants are generated. The dopant profiles
diffusivity, many super-halo processes proposed earlier [3]–[6]
are measured using CAMECA IMS-4f/6f Secondary Mass
were centered on the use of disposable spacer, reduced thermal
Spectrometers (SIMS) with an O primary beam. TCAD
budget, or heavy ion species with low diffusivity. These ap-
simulations, using a TSUPREM4 process simulator tuned
proaches have various shortcomings, such as increased process
to the SIMS profile and silicon data, are used to predict and
complexity and reduced dopant activation level in silicon or
normalize transistor electrical characteristics. A set of full
poly gate. Fluorine implants at different steps of the process
flow experiments based on simulation results is designed.
have been studied for many years. These include the use of
Bulk CMOS transistors with gate lengths down to 45 nm were
fluorine to improve pMOS NBTI, reduce hot-carrier damage,
fabricated using a 130-nm CMOS process. After poly-silicon
and produce shallow boron drain extension [7]–[9]. In this
gate etch, some wafers received the fluorine halo process.
letter, we report for the first time the potential use of fluorine
Fluorine energies are chosen to produce implant peaks between
to produce a super-halo for both nMOS and pMOS transistors.
25 and 85 nm deep. A high-angle boron or phosphorus halo is
Our SIMS profiles indicate that the fluorine-assisted halo
either implanted before or after the fluorine implant. All wafers
process is able to produce a super-sharp halo profile and reduce
subsequently received a 1050 C rapid thermal anneal (RTA)
halo dopant segregation into heavily doped drain extension
spike anneal. Cross-sectional transmission electron microscope
( ) by reducing halo dopant diffusivity. Furthermore, the
(XTEM) images are obtained to measure the defect distribution
SIMS profiles also indicate that the degree of halo profile
in the silicon at the end of the process.
sharpness and the amount of dopant segregation can be tailored
by varying the fluorine implant conditions. This added flexi-
bility in halo profile and dopant segregation control enables III. RESULTS AND DISCUSSIONS
one to meet different transistor parametric requirements on ,
Comparisons between the nonfluorine and the fluorine halo
diode leakage, drive current, and roll-off more easily.
processes are made in terms of the halo diffusion profile and
transistor dc electrical characteristics. The ability to use fluo-
Manuscript received October 18, 2002; revised December 16, 2002. The re- rine implant to tailor a halo profile is illustrated in Figs. 1 and 2.
view of this letter was arranged by Editor B. Yu. From the SIMS profiles, it can be seen that the halo profile
The authors are with Silicon Technology Development, Texas Instruments,
Inc., Dallas, TX 75243 USA (e-mail: K-liu2@ti.com). sharpness and the amount of dopant segregated into can be
Digital Object Identifier 10.1109/LED.2003.809532 tailored independently by using different fluorine implant order
0741-3106/03$17.00 © 2003 IEEE
LIU et al.: FLUORINE-ASSISTED SUPER-HALO FOR SUB-50-nm TRANSISTORS 181

Fig. 2. Fluorine energy impacts on the pMOS halo profile sharpness, the Fig. 4. NMOS I –I comparison between the fluorine halo process and
amount of halo dopant segregation into the H dd, and the H dd profile nonfluorine process. Current gain of 3.9% at I = 3 nA is observed on nMOS
sharpness. with T = 1:6 nm and V dd = 1:2 V.

Fig. 5. PMOS I –I comparison between the fluorine halo process and

nonfluorine process. A current gain of 6% at I = 10 nA can be achieved
Fig. 3. nMOS I –I simulation results between the fluorine halo process for pMOS with T = 1:6 nm and V = 1:2 V.
and nonfluorine process. The simulation result shows that a 5.5% improvement
in drive current can be achieved on nMOS with a 1.6-nm gate oxide and an
operating voltage of 1.2 V. and a smaller depletion width due to reduced halo dopant seg-
regation into the region.
The experimental data show that different aspects of transis-
and conditions. Aside from the impact on as-implant profile, a
tors improve when the fluorine halo implant process is used.
fluorine implant affects the halo profile by creating two regions
When comparing under approximately the same , ,
in silicon with different dopant diffusion mechanisms—within
and halo implant conditions, the ’s show an improvement of
the amorphous layer and beyond the amorphous layer. Within
3.9% at nA for nMOS and 6% at nA for
the amorphous layer, fluorine passivates the silicon dangling
pMOS, as shown in Figs. 4 and 5. In addition, the pMOS and
bond and reduces the solid phase regrowth rate [10]. As a re-
nMOS ’s are reduced by 11% and 5.8%, respectively. Part
sult, the boron TED is reduced and boron diffusivity is increased
of the drive current improvement observed for pMOS could be
[11]. These effects allow a better profile to be achieved,
due to boron drain extension ( ) having 35% higher acti-
as observed in Fig. 2. Upon regrowth, fluorine within the re-
vation level at the knee of the profile and 27% sharper gradient,
grown layer continues to bond with the silicon interstitial and
as shown in Fig. 2. Although the nMOS drive current did not im-
the dopant. Therefore, dopant diffusivity continues to be slow.
prove at nA, the fluorine halo process transistor has
Beyond the amorphous region, it has been reported that flu-
a smaller and 17% smaller than the nonfluorine
orine pre-amorphization implant (PAI) produces smaller EOR
process, even with the same halo implant energy and dose. The
dislocation loop and allows faster loop dissolution upon anneal
smaller improvement observed in our experiment, especially for
[12]. These results increase dopant diffusivity and TED beyond
the nMOS transistor, compared to simulation data, could be due
the amorphous layer.
to higher leakage current caused by silicon end-of-range defects.
Simulations performed using a tuned TCAD process simula-
tion deck show that the device performance can be significantly
IV. CONCLUSION
enhanced. The increase in drive current, as shown in Fig. 3,
is attributed to higher channel mobility, which is the result of We have shown for the first time that fluorine could be an
reduced halo dopant diffusion and halo dopant pileup at the effective means to produce a super-halo for sub-50-nm tran-
gate oxide–silicon interface. The improvement in roll-off, not sistors. A SIMS profile shows that fluorine is capable of tai-
shown, is credited to having a sharper halo profile in the channel loring halo profiles for different transistor requirements. Based
182
on TCAD simulations, a 5.5% drive current improvement is pos-
sible, while our preliminary silicon data showed a smaller im-
provement. This discrepancy is believed to be caused by silicon
defects indicating that the fluorine implant condition needs to be
further optimized or a defects reduction scheme has to be used.
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