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Design and Implementation of a 5-Bit Flash ADC for

Education
Alaa A. Abualsaud, Saeed Mian Qaisar, Sara H. Ba-Abdullah, Zainab M. Al-Sheikh, Mohammad Akbar
Electrical and Computer Engineering Department, Effat University, Jeddah, KSA
sqaisar@effatuniversity.edu.sa

Abstract – The DSP (Digital Signal Processing) has many engineering students. To keep the system interactive each
advantages over the analog processing. Therefore, with the recent module is kept accessible via separate input and output test
advent of technology most of the signal processing tasks have been points.
transferred from the analog to the digital domain. The ADCs (Analog
to Digital Converter) provide a liaison between the real world
analog signals and the digital processors. Therefore, ADCs become
an elementary part of almost all modern electronic systems. This
work focuses on the development of a simple Flash ADC for students
demonstration purpose. In this context, a 5-Bit Flash ADC is
implemented. Being designed for illustration purpose, the ADC has
easily accessible inputs and outputs to each module. In order to keep
the system cost effective with an ease of reimplementation. The low
cost and easily market available discrete analog components are
employed. The digital part is kept configurable with the help of a
FPGA (Field Programmable Gate Array) based implementation. The
digital circuit implementation is done via Verilog, a HDL (Hardware
Description Language). The system implementation is described.
Testing results are also presented. These results assure a proper
functionality of the designed ADC.
Figure 1: ADC Architectures Cover Different Ranges of Sample Rate
Index Terms – Verilog, FPGA, A/D Conversion, Computer Aided and Resolution [12]
Design.
The Section 2 of this article briefly describes the A/D
conversion principle. The proposed ADC block diagram is
I. INTRODUCTION described in Section 3. Section 3 also illustrates the
implementation, integration and testing steps of the devised
Because of ever wanted features, the DSP (Digital Signal solution along with system functionality verification. Section
Processing) has replaced the analog processing in most of the 4 finally concludes the article.
modern systems [1-3]. The ADC is a critical component of a
DSP system and it imposes a major impact on the performance II. THE A/D CONVERSION PRINCIPLE
of whole system [4-6]. A smart ADC can lead towards an
efficient solution and vice versa [4, 7-8, 17]. Figure 2 illustrates the basic concept of an Analog to Digital
converter. It accepts a continuous analog signal at input and
The increasing sophistications in the recent applications delivers a digital signal at the output (cf. Figure 2).
like software radio, sensors networks, autonomous control,
bioinformatics, etc. require out of the shelf solutions. In this
context several advances have been made in the domain of
A/D conversion. A rich literature is available in this
framework; a few examples are [9-12, 18]. The ADCs have
different possible architectures [5-6, 9-12, 18] and they cover Figure 2: A/D Conversion Principle.
different ranges of sample rates and resolutions (cf. Figure 1).
Classically the A/D conversion is performed by
The focus of this work is to design and develop a employing the combination of a uniform sampling, (cf.
simplified ADC model for teaching purpose. The idea is to Equation 1), and a uniform deterministic quantization process
demonstrate the A/D conversion concept to undergraduate (cf. Figure 2). There also exist novel and original event driven

978-1-5090-5306-3/16/$31.00 ©2016 IEEE


signal digitization and processing solutions [4, 7-8, 17]. hand, they typically consume more power than other ADC
However, the focus of this work is on the classical A/D architectures and are generally limited to around 12-bits
conversion process. In this context, the term uniform resolution [5-6].
quantization states that the reference thresholds are uniformly
distributed, which means that the consecutive amplitude Digital
Output
difference between all thresholds is unique. If q is the uniform X[n]

quantization step, then the quantization process in this case is D4


Analog Input 31 31
clear from Figure 3. x(t) Comparators/Discriminators
Interface between 32 to 5
D3

Comparators and the Priority Encoder D2


Network
Amplitude Axis

Priority Decoder
1 1 D1
Analog Signal Quantized Signal 0 0
D0

xn-1 Resistors Network


Provides Reference Voltage
Cyclone-II FPGA
xn Qe Levels

q Figure 4: Block Diagram of 5-Bit Flash ADC.

tn-1 tn a. SYSTEM IMPLEMENTATION


Time Axis
TS Figure 4 shows that the proposed solution is composed of four
Figure 3: Uniform deterministic quantization: original and quantized main modules the resistors network, comparators bank, clock
signals. and encoder. In terms of implementation the project is divided
into two main parts (cf. Figure 5). The First part deals with the
∞ ∞ analog modules, composed of resistors network and
xs (t ) =  x(t ).δ (t − nTs ) =  x(nT ) …(1)s comparators bank. The second part deals with the digital
n =−∞ n =−∞ modules, composed of a 32-to-5 priority encoder and the
In Equation 1, Ts is the sampling period and δ is the Dirac interface between analog front end to digital encoder. The
function. clock is generated with the help of an external function
generator [16].
Theoretically speaking during the classical A/D
conversion process, the only imprecision caused by an ideal System Implementation Description
ADC is the quantization error (Qe). This error arises because
the analog input signal may take any value within the ADC Analog Module Digital Module
amplitude dynamics while the output is a sequence of finite
precision samples [4-11]. The samples precision is defined by
the ADC effective resolution in terms of bits [5-6]. An interface between comparators
Comparator Bank output and the priority encoder
If the ADC voltage ranges between [0; Vmax], then in the (LM393)
case of uniform deterministic quantization the quantum of an
M-bit resolution converter can be defined by Equation 2. In The Priority Encoder
Resistor Network
this case, the upper bound on Qe is posed by Equation 3 (1k Ohm and 500 Ohm)
(Designed in Verilog
[5-6]. Implemented on Cyclone-II FPGA
Mounted on the Terasic DE2 board)
Vmax LSB
q= …(2) Qe ≤ ± …(3) (3.1)
Figure 4: The system Implementation description.
2M 2
i. Analog Modules Implementation

III. THE PROPOSED SOLUTION The first analog module is the comparators bank. It requires
(3.2)
32 comparators, each one comparing the input signal to a
The block diagram of proposed 5-Bits Flash ADC is shown on unique reference voltage. The LM393, vide supply range and
Figure 4. Flash ADC is a parallel A/D conversion architecture. low offset voltage, dual Comparator chips are employed for
It is one of the fastest architectures to convert an analog signal this purpose [13].
to a digital one [5-6]. Flash ADCs are extremely applicable for
the applications which required large bandwidth like radar, Each comparator produces a logic '1' when its analog
digital oscilloscopes, satellite transceivers, etc. On the other input voltage is higher than the reference voltage applied to it.
Otherwise, the comparator output remains at logic '0'. It shows
the requirement of 32 equi-spaced reference voltages
generation. It is done with the help of a resistors network,
comprises of a 0.1% precision resistances [14]. The principle
of generating the equi-spaced reference voltages, within the
given voltage range [0; Vmax] is shown on Figure 6.

Figure 7: The system testing setup

Figure 8, shows that the Quantum, q= 0.09375V, in this case.


At first time the digital outputs are observed with the help of 5
LEDs, available on the DE2 board [15]. In order to keep a
track between analog input and digital output combinations,
the input is kept constant for a certain period of time, DC
level, and the corresponding digital output is verified with the
help of employed LEDs. Once verified another input DC
Figure 6: The principle of generating the reference voltages value is applied and the corresponding digital output is
verified. The process is repeated, in an iterative fashion, to
ii. Digital Modules Implementation verify all possible input and output system combinations.
Moreover, the system functionality is also studied for
analytical input signals like sinusoid, square, etc. It is done
The first digital module is an interface between comparators
with the help of a function generator [16] and digital
output and the priority encoder. This interface is designed in
oscilloscope. The analog signals are generated with the
Verilog and the implementation is done on Cyclone-II FPGA,
function generator and the corresponding digital outputs are
mounted on the Terasic DE2 board [15].
observed on the digital oscilloscope.
The second digital module is the priority encoder. It is a
circuit that converts 2K digital inputs into a K binary
representation. Each of input has assigned priority where the
least significant bit has the highest priority and the most
significant bit the lowest. If more than one input is active at
the same time the input having highest priority will take
precedence. Additional output signal indicates that output
grant is valid. The priority Encoder is designed in Verilog and
is implemented on Cyclone-II FPGA, mounted on the Terasic
DE2 board.

b. SYSTEM TEST AND VERIFICATION


In order to verify the proposed A/D convertor functionality, a
testing setup is devised. The implemented A/D converter
along with the simplified employed testing setup is shown on
Figure 7.

As a case study the Vmax equal to 3v is chosen. The value


of R=1kΩ is chosen [14]. It leads to the following reference
system voltages (cf. Figure 8).

Figure 8: The system reference voltages values


[6] Marcel J.M. Pelgrom, “Analog-to-Digital Conversion”,
ASIN: B00BWZ1U4M, Springer Netherlands, 1st edition,
IV.CONCLUSION 2010.
In this paper a 5-Bit Flash ADC design and [7] S. M. Qaisar et al., "Computationally efficient adaptive
implementation has been presented. During this project, resolution short-time Fourier transform." EURASIP,
we have gone through a complete electronic system RLSP (2008).
design, implementation and verification cycle. This [8] S. M. Qaisar et al., “Computationally efficient adaptive
exercise has clarified our A/D conversion concepts. It has rate sampling and filtering for low power embedded
also enriched our Verilog, Altera-Quartus, Multisim, systems,” in Proceedings of the International Conference
interfacing and prototyping with discrete electronics on Sampling Theory and Applications (SampTA ’07),
skills. Thessaloniki, Greece, June 2007.
The project goal has been achieved, which is to design a [9] Pieter Harpe, Eugenio Cantatore and Arthur van
cost effective and interactive ADC demonstration kit for Roermund, "A 2.2/2.7 fJ/conversion-step 10/12b 40kS/s
the undergraduate engineering students. Students can SAR ADC with data-driven noise reduction", IEEE
easily access and analyze the different ADC modules International Solid-State Circuits Conference, IEEE,
inputs and output. At first time a 5-Bits resolution ADC is 2013.
implemented and tested. However, because of the system [10] Takumi Danjo et al., "A 6-bit, 1-GS/s, 9.9-mW,
configurability, the idea can be extended to implement a Interpolated Subranging ADC in 65-nm CMOS", IEEE
higher resolution and cost effective ADCs demonstration Journal of Solid-State Circuits 49.3 (2014): 673-682.
kits. The current implementation is based on a Flash [11] Monk, Timothy A., Paul J. Hurst, and Stephen H. Lewis.
architecture. The implementation of other ADC "Iterative Gain Enhancement in an Algorithmic ADC."
architectures like SAR (Successive Approximation IEEE Transactions on Circuits and Systems I: Regular
Conversion) [9], Subranging [10], Algorithmic [11], Papers 63.4 (2016): 459-469.
delta-sigma [12] and time interleaved ADCs [18] is a [12] Gerry Taylor and Ian Galton, "A reconfigurable mostly-
future work. Moreover, the implementation of a real time digital delta-sigma ADC with a worst-case FOM of 160
interface between the front end electronics and the PC dB", IEEE Journal of Solid-State Circuits 48.4 (2013):
(Personal Computer) is a prospect. It will facilitate the 983-995.
A/D converted data visualization and the ADC kit [13] “LM393 Low-Power, Low-Offset Voltage, Dual
evaluation, calibration and analysis. Comparator”, data sheet, Texas Instruments, 2014.
[14] “Wirewound Resistors, Non Magnetic, Non-Inductive,
Axial Lead” data sheet, Vishay Mills, 2012.
V.ACKNOWLEDGEMENT [15] “Altera DE2 Board” Reference Manuel, Altera, 2005.
[16] “Function Generator- SFG-2000” Reference Manuel,
Authors are thankful to anonymous reviewers for their 2001.
valuable feedback. They are also thankful to the Effat [17] S. M. Qaisar et al., "Adaptive rate filtering a
university DGSR and ECE department respectively for computationally efficient signal processing approach",
providing the financial support and the system Signal Processing 94 (2014): 620-630.
implementation and testing resources. [18] Manar El-Chammas and Boris Murmann, "Time-
Interleaved ADCs", Background calibration of time-
interleaved data converters, Springer New York, 2012.
REFERENCES
[1] E.C. Ifeachor and B.W. Jervis, “Digital Signal Processing:
A Practical Approach”, Printice-Hall, 2001.
[2] A.V. Oppenheim and R.W. Schafer, “Digital Signal
Processing”, Printice-Hall, 1997.
[3] S.W. Smith, “Scientists and Engineers Guide to Digital
Signal Processing”, 2nd Edition, California Technical
Publishing, 1999.
[4] S. M. Qaisar et al., “An Efficient Signal Acquisition with
an Adaptive Rate A/D Conversion”, IEEE, ICCAS’13,
Kuala Lumpur, Malysia, 2013.
[5] Analog Devices Inc. “Data Conversion Handbook”, 1st
edition, ISBN-13: 978-0750678414, Newnes, 1st edition,
2004.

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