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Alaa A. Abualsaud, Saeed Mian Qaisar, Sara H. Ba-Abdullah, Zainab M. Al-Sheikh, Mohammad Akbar
Electrical and Computer Engineering Department, Effat University, Jeddah, KSA
sqaisar@effatuniversity.edu.sa
Abstract – The DSP (Digital Signal Processing) has many engineering students. To keep the system interactive each
advantages over the analog processing. Therefore, with the recent module is kept accessible via separate input and output test
advent of technology most of the signal processing tasks have been points.
transferred from the analog to the digital domain. The ADCs (Analog
to Digital Converter) provide a liaison between the real world
analog signals and the digital processors. Therefore, ADCs become
an elementary part of almost all modern electronic systems. This
work focuses on the development of a simple Flash ADC for students
demonstration purpose. In this context, a 5-Bit Flash ADC is
implemented. Being designed for illustration purpose, the ADC has
easily accessible inputs and outputs to each module. In order to keep
the system cost effective with an ease of reimplementation. The low
cost and easily market available discrete analog components are
employed. The digital part is kept configurable with the help of a
FPGA (Field Programmable Gate Array) based implementation. The
digital circuit implementation is done via Verilog, a HDL (Hardware
Description Language). The system implementation is described.
Testing results are also presented. These results assure a proper
functionality of the designed ADC.
Figure 1: ADC Architectures Cover Different Ranges of Sample Rate
Index Terms – Verilog, FPGA, A/D Conversion, Computer Aided and Resolution [12]
Design.
The Section 2 of this article briefly describes the A/D
conversion principle. The proposed ADC block diagram is
I. INTRODUCTION described in Section 3. Section 3 also illustrates the
implementation, integration and testing steps of the devised
Because of ever wanted features, the DSP (Digital Signal solution along with system functionality verification. Section
Processing) has replaced the analog processing in most of the 4 finally concludes the article.
modern systems [1-3]. The ADC is a critical component of a
DSP system and it imposes a major impact on the performance II. THE A/D CONVERSION PRINCIPLE
of whole system [4-6]. A smart ADC can lead towards an
efficient solution and vice versa [4, 7-8, 17]. Figure 2 illustrates the basic concept of an Analog to Digital
converter. It accepts a continuous analog signal at input and
The increasing sophistications in the recent applications delivers a digital signal at the output (cf. Figure 2).
like software radio, sensors networks, autonomous control,
bioinformatics, etc. require out of the shelf solutions. In this
context several advances have been made in the domain of
A/D conversion. A rich literature is available in this
framework; a few examples are [9-12, 18]. The ADCs have
different possible architectures [5-6, 9-12, 18] and they cover Figure 2: A/D Conversion Principle.
different ranges of sample rates and resolutions (cf. Figure 1).
Classically the A/D conversion is performed by
The focus of this work is to design and develop a employing the combination of a uniform sampling, (cf.
simplified ADC model for teaching purpose. The idea is to Equation 1), and a uniform deterministic quantization process
demonstrate the A/D conversion concept to undergraduate (cf. Figure 2). There also exist novel and original event driven
Priority Decoder
1 1 D1
Analog Signal Quantized Signal 0 0
D0
III. THE PROPOSED SOLUTION The first analog module is the comparators bank. It requires
(3.2)
32 comparators, each one comparing the input signal to a
The block diagram of proposed 5-Bits Flash ADC is shown on unique reference voltage. The LM393, vide supply range and
Figure 4. Flash ADC is a parallel A/D conversion architecture. low offset voltage, dual Comparator chips are employed for
It is one of the fastest architectures to convert an analog signal this purpose [13].
to a digital one [5-6]. Flash ADCs are extremely applicable for
the applications which required large bandwidth like radar, Each comparator produces a logic '1' when its analog
digital oscilloscopes, satellite transceivers, etc. On the other input voltage is higher than the reference voltage applied to it.
Otherwise, the comparator output remains at logic '0'. It shows
the requirement of 32 equi-spaced reference voltages
generation. It is done with the help of a resistors network,
comprises of a 0.1% precision resistances [14]. The principle
of generating the equi-spaced reference voltages, within the
given voltage range [0; Vmax] is shown on Figure 6.