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I/O Interfacing
Embedded Systems
I/O Interfacing
Switch, LED Devices
ADC / DAC
LCD
Opto Isolator
High Power Devices Relays
OP Amps :
Adder, Subtracter, Gain , Low Pass filter,
High Pass filter, Integrator,
Differentiator, Current to Voltage Converter
R = V / I
VD 1) R1 = 3.5 V / 15 mA
2) R2 = 3.5 V / 20 mA
R1 < R <R2
10/7/2013 I/O Interfacing 4
Embedded Systems
I/O Interfacing
Switch
1 0
Digital signals only have two states. For digital computer, we refer to binary
states, 0 and 1.
ADC Provides a link between the analog world of transducers and the digital
world of signal processing and data handling.
0
1
ADC 1
2.5 Volts 1
1 128
1
1
1
0 Volts 00000000
5 Volts 11111111
2 steps
Sampling Pulse
Sampled Signal
Resolution:
The smallest change in analog signal that will result in a change in the
digital output.
Vr
∆V = n
2 −1
V = Reference voltage range
N = Number of bits in digital output.
2N = Number of states.
ΔV = Resolution
Encoding:
Assigning a unique digital code
to each quantum, then allocating
the digital code to theinput signal.
2n states
• Linear Error
• Offset Error
• Gain Error
Process
1. MSB initialized as 1
2. Convert digital value to analog using DAC
3. Compares guess to analog input
4., Is Vin>VDAC
• Set bit 1
• If no, bit is 0 and test next bit
Fundamental components
Integrator
Electronically Controlled Switches
Counter
Clock
Control Logic
Comparator
Hitachi HD47780
1 Line * 8 Char
.
.
4 Line * 40 Char
Simplest Form
Transmitter Receiver
LED , IRED , Laser Photo Sensor
converts electrical signal into Converts the modulated light
a beam of modulated visible or IR back into an electrical
light or infrared (IR). signal
MCT 2 E
4 pin DIP
Viso ` 5000V
Mechanical
Vcc = 5 V
LED Current = 18 mA
R = 100 Ω
Device can C
Source / Sink 2 mA
B
E
R=?
I/O Interfacing
10/7/2013 43
Embedded Systems
I/O Interfacing Relay
Easy to configure
Possibility of central diagnosis
• Make Ready
• Send Message
• Receive Message
• Select
• Accept
• Frame Check
• Format Errors
• ACK Errors
• transmission Error Detected by receipents
• Ack Field Corrupted
• No Receivers
• Monitoring
• Node Transmits and Observes Bus Signal
• Detect Global and Tx errors
• Bit Stuffing
• After 5 Similar Bits + 1 Complimentary Bit Txed
• Rx removes the Bit
• Rx sends Error Flag
The efficiency of the bus arbitration procedure is increased by the fact that the
bus is utilized only by those stations with pending transmission requests.
These requests are handled in the order of the importance of the messages for
the system as a whole.
Describes the physical interface and protocol for relatively low-speed serial data
communication between computers and related devices.
Named by Motorola
Multiple slave devices are allowed with individual slave select (chip select) lines.
• speeds:
– 100 kbps (standard mode)
– 400 kbps (fast mode)
– 3.4 Mbps (high-speed mode)
Frames
• bus state
– busy … after S and before next P
– free … after P and before next S
• Master sets SCL = 0 and generates pulse for each data bit
• 8 pulses for data bits are followed by one pulse for ack. bit
• after ack.
– master tries to generate next byte’s first pulse
– slave can hold SCL low master switches to wait state
– address matches its own device switches state according to R/W bit
Master-transmitter
Acknowledge
• Acknowledge Done on the 9th clock pulse and is mandatory
• Transmitter releases the SDA line
• Receiver pulls down the SDA line (SCL must be HIGH)
• Transfer is aborted if no acknowledge
Clock Stretching
• Clock Stretching-Slave device can hold the CLOCK line LOW when
performing other functions
• Master can slow down the clock to accommodate slow slaves
Ideal OpAmp
• The current flow into the input leads of the op amp is zero.
• The op amp gain is assumed to be infinite.
• The voltage between the input leads is zero
• The input impedance of the op amp is infinite.
• The output impedance of the ideal op amp is zero
• The frequency response of the ideal op amp is flat
Inverting Amplifier
VIN- = VIN+
Rg is very Large
Freq = f
Time = t = 1/f
T OFF = t / 2 T ON = t / 2