-- Company: UNAD

-- Engineer:

-- ESTUDIANTE ING DE TELECOMUNICACIONES

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity simu1 is

-- Port ( );

end simu1;

architecture Behavioral of simu1 is

component MULTIPLXOR_6A1

port(

E0 : in std_logic_vector(3 downto 0);

E1 : in std_logic_vector(3 downto 0);

E2 : in std_logic_vector(3 downto 0);

E3 : in std_logic_vector(3 downto 0);

E4 : in std_logic_vector(3 downto 0);

E5 : in std_logic_vector(3 downto 0);

SELECTOR : in std_logic_vector(2 downto 0);

SALIDA : out std_logic_vector(3 downto 0)

);

end component;
-- Señales de las entradas

signal E0 : std_logic_vector(3 downto 0) := (others => '0');

signal E1 : std_logic_vector(3 downto 0) := (others => '0');

signal E2 : std_logic_vector(3 downto 0) := (others => '0');

signal E3 : std_logic_vector(3 downto 0) := (others => '0');

signal E4 : std_logic_vector(3 downto 0) := (others => '0');

signal E5 : std_logic_vector(3 downto 0) := (others => '0');

signal SELECTOR : std_logic_vector(2 downto 0) := (others => '0');

-- Señales de salidas

signal SALIDA : std_logic_vector(3 downto 0);

begin

UO: MULTIPLXOR_6A1 Port map (

E0 => E0,

E1 => E1,

E2 => E2,

E3 => E3,

E4 => E4,

E5 => E5,

SELECTOR => SELECTOR,

SALIDA => SALIDA

);

process begin

--- Estímulos de la simulación wait for 100 ns;

wait for 100 ns;

E0 <= "0001";

E1 <= "0011";

E2 <= "0111";

E3 <= "1111";

E4 <= "0000";

E5 <= "1000";

SELECTOR <= "000";

wait for 100 ns;

SELECTOR <= "010";

wait for 100 ns;

SELECTOR <= "100";

wait for 100 ns;

SELECTOR <= "110";

wait for 100 ns;

SELECTOR <= "001";

wait for 100 ns;

SELECTOR <= "111";

wait for 100 ns;

SELECTOR <= "011";

wait;
end process;

end Behavioral;
-- Company: UNAD

-- Engineer: HUMBERTO ROJAS

-- ESTUDIANTE ING DE TELECOMUNICACIONES

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity simu1 is

-- Port ( );

end simu1;

architecture Behavioral of simu3 is

component MULTIPLXOR_8A1

port(

E0 : in std_logic_vector(7 downto 0);

E1 : in std_logic_vector(7 downto 0);

E2 : in std_logic_vector(7 downto 0);

E3 : in std_logic_vector(7 downto 0);

E4 : in std_logic_vector(7 downto 0);

E5 : in std_logic_vector(7 downto 0);

E6 : in std_logic_vector(7 downto 0);

E7 : in std_logic_vector(7 downto 0);

SELECTOR : in std_logic_vector(3 downto 0);

SALIDA : out std_logic_vector(7 downto 0)

);

end component;

-- Señales de las entradas

signal E0 : std_logic_vector(7 downto 0) := (others => '0');

signal E1 : std_logic_vector(7 downto 0) := (others => '0');

signal E2 : std_logic_vector(7 downto 0) := (others => '0');

signal E3 : std_logic_vector(7 downto 0) := (others => '0');

signal E4 : std_logic_vector(7 downto 0) := (others => '0');

signal E5 : std_logic_vector(7 downto 0) := (others => '0');

signal E6 : std_logic_vector(7 downto 0) := (others => '0');

signal E7 : std_logic_vector(7 downto 0) := (others => '0');

signal SELECTOR : std_logic_vector(3 downto 0) := (others => '0');

-- Señales de salidas

signal SALIDA : std_logic_vector(7 downto 0);

begin

UO: MULTIPLXOR_8A1 Port map (

E0 => E0,
E1 => E1,

E2 => E2,

E3 => E3,

E4 => E4,

E5 => E5,

E6 => E6,

E7 => E7,

SELECTOR => SELECTOR,

SALIDA => SALIDA

);

process begin

--- Estímulos de la simulación wait for 100 ns;

wait for 100 ns;

E0 <= "00000111";

E1 <= "00110000";

E2 <= "01110000";

E3 <= "11110000";

E4 <= "00001111";

E5 <= "10000000";

SELECTOR <= "0000";

wait for 100 ns;

SELECTOR <= "0001";

wait for 100 ns;

SELECTOR <= "1000";

wait for 100 ns;

SELECTOR <= "1100";

wait for 100 ns;

SELECTOR <= "0011";

wait for 100 ns;

SELECTOR <= "1110";

wait for 100 ns;

SELECTOR <= "0110";

wait;

end process;

end Behavioral;