M icrOPl'ocessors are power-

ful devices and it is,

therefore, not to be wondered
PSD3XX CHIPS known as Address Strobe 01'
AS). The polarity ofthe inputs
is deterrnined by the operator
at that their popularity has as required. As lang as the
grown so fast in such a short ALE 01' AS signals is valid, the
time. A disadvantage remain- input stage is transparent.
ing until recently was the
By A. Riet jens When this signal becomes in-
need of several more les to active, the data are stored in
design a complete micro- the latches.
processor system. Since more The Programmable Ad-
cornponents require more dress Decoder (PAD) plays an
space and result in higher CENTRAL PROCESSING UNIT important role. It will be seen
casts, a demand arose for CPU in Fig. 2 that address Iiues
more powerful system compo- ADDRESS DATA I CONTROL An-AI5 and, if desired,
nents to simp1ify the design of A16~A19' are connected di-
a microprocessor circuit. US
PSD3XX I rectly to the PAD. Other input
chip manufacturer Wafer I
PAGING
I signals applied to the decoder
I
Scale has responded to this are RD(E), WR(R!W) and ALE
LOOIC
need with the introduction of CIRCUlTRY
DECODED (AS). Programming of the

.~
OUTPUTS
its PSD3xxx family. PAD gives tbe user the oppor-
The chips in the PSD3xxx tunity of selecting EPROM
family contain flexible 110 banks internalJy via the
ports, a PLD, Page Registers, ESo-ES7 !ines.
~
EPROM (choice of 32 kbyte, Also, there is a selection
64 kbyte, 0]' 128 kbyte), EPROM SRAM INPUT/OUTPUT signal for the static memory,
2 kbyte static RAM and some RSo·
logic circuitry to make connec- Port C is a 3-bit 1/0 port
tion with the microprocessor-
INPUT/OUTPUT
0 PORTS
with two functions: it can take
see Fig. 1. Because of the 940110 -11
internal signal CSs-CSlO out-
power of the new chips, the side, 01' it can receive address
design of a microprocessor lines A16-AIB and pass these
system 1Sbrought down to two Fig. 1. Functions that can be assumed by a PSD3xxx chip. to the PAD. Moreover, address
components (since the latch line A 19 can be passed directly
for demultiplexing of the ad- to the PAD. This shows that
dress and data buses is no the PAD 18 capable of ar-rang-
I PAGE lQGIC
longer needed). A similar "-" Al6--A18 ing an entire address decoding

• Fr
function would until recently - Al1 AlS PROG. up to 1 MHz without any ex-
have required 8 to 12 discrete
les. The chips have been de-
,~
t,

r m
CS~f'{)RT
m d LOGICIN

-
eoer
EXP. temal components.
.=:~" c '0'- Ports A and Bare 8-bit
signed to work with a variety
of microprocessor les, irrelud-
ing, for example, the 68HCll
~
~
~
I
~
I:SET
ÄLElAS
PACA

13 P.T.

I~
~
I
ÄlEIAS

I:
IRESET
PAC B

27P.T. -
,,~
CS10_
soar
c ~ ports that can be used by the
operator as conventional 1/0
pcrts. Figure 3 shows the
as weil as the Z80. The f---- • -- EPROM special mode in which 1/0
, ,,
256 K BIT·' MBIT
PSD3xxx farnily may be split ports A, Band C may be used.
into two branches: the
~AC
'I· r
'"
co,
co, This is especially useful if an

t....
c CO'
PSD31x, intended for 8-bit 8-bit processor system uses a
.-
-"
CO,
processors, and the PSD3x for I-'
CO, PRQG,
multiplexed address and data

-
eonr
16-bit processors. ~ bus (ADo-AD7)' Address lines
..
CSO- EXP.
CS7 I---
A block diagram of one of " Ag-AI5 are then available as

rr
PORT ~
the new chips, the Iß-bi t .Q!;QJ.l .- ~ BLOCK rr ~ normal and may be applied to
PSD30x, is given in Fig. 2. At
~~~
the address inputs. Ports B
the left are all the functions r- .- I ~ 0>0"
and C are then available as
needed to make connection 110 functions or for passing

-~ --- CSI(JPOIU
with a microprocessor; and at oo-os
~-A7 01' ADO-AD7Iines (track
the right, the 1/0 functions. I- -- mode) respectively,
The memory banks are in the 1- ~'- Apart from functioning as
centre.
Inputs ADo-AD7 reach the
'-
~~
--.. SRAM
16KBIT
TRACK MODE
"00
PORT
EXP.
an rio port, port B can also
take the chip-select signals of
SELECTS f--
nucleus of the IC via latches, ,~, "0- the PAD outside. Port C can
which can be arranged to AOO-AD71OO-07
eoat
, ~ then be used to obtain more
store data. This obviates the AlEf"'S
~ inputs, 01' for writing addi-
need of a separate register
such as a 74HCT373 or
'"',
WAIRIW
• I
PROG.CHIP
CONFIGUAATION
SECURrTY
tose tional address lines AlB-AlS,
or for taking chip-select lines
PROG. XB,X16
BHEJP EN
74HCT573. In the transparent , 00'""'"
SIGNALS
MUX '" NON--MUX BUSSES
CSa-CSIO outside.
mode, the latches function as A'91C t 940110--12

buffers. However, the latched

mode is more usual, for exam-
pIe, with the 8031. Data stor-
age in the latches at the input
of the circu it is then accom-
plished by an ALE instruction
(in Motorola processors better
Address lines
The 16 address lines of a mul-
tiplexed bus are stored in one
Fig. 2. Block diagram 01 the 16-bit PSD30x; in the B-btt or two 8-b-it wide latches, de-
PSD31x the 16/B demultiplexer and associated buffer pending on the type of proces-
are not used. SOl'. With non-mul tiplexed

ELEKTOR ELECrRONICS DECEMßER 1994

-- PSO.lXX CHIPS

,~
V
ese
~
A8-AlS [110] er [AC - A7J er [ADO - AD7) ~
'"
"
, ese
~ 8 EPI'ICIM BlOCK
SEI.ECT L1NE5

ess PAD
[1/0] or [eSO - CS7] .lLE ot"'S
ese
A
~O",E
~
~ Sf1AM BtOCI( SB.ECT

~ ro_~

~.~
WlIorllM
A16, An, AlB er CS8, CS9, csro es ••• }

...
TRACKIoIC!DIO
CSAOO\JT'I CONmOl SIGNALS

940110 -13
... cso.'PBO

.., CS11P1I'

Fig. 3. The ports in the PSD3xx may have several lunctions.

... ~~~

buses, the inputs rematn the 16-bit mode, the da ta in

... C5:III'83

transparent. Address Iines the two blocks (Do-D7 and ... ~c~.
PAD
AI-AlO go direct1y to the static DS-D'5) are buffered. If it is ~CSIJl'85 B
."
memory, while address lines set to the byte-wide mode, the
Al-AU are applied to the S-bit wide data stream 18con- .., =L> CMtPIO

EPROM. The EPROM banks trolled with BHE and AO'

are selected via selection lines Which of the two bytes is ad- ." =L> CS1IPB7

ESO-ES7• which originate in

the PAD. The statie memory 1S
dressed depends on the level
of An. -"'--- --J?o csesce

CSg'PC,
AESET • ~
selected by the RSo signal that The EPROM section is di- , , , V
CS'(lIfIC<!

15 also generated by the PAD. vided into eigbt banks., which 940110-14

Address lines An-A 15and op- are selected by ESo-ES7.

tional address lines A16-A19
are used in the PAD array.
In ternallv, the memory
banks are ward wide (16 bits);
provision is made by an isola-
tion buffer for splitting th is
into two bytes. The operation
of the buffer is enabled by the
configuration of the PSD. If
this is eonfigured to work in
These signals originate in the
PAD.
Figure 4 shows a detailed
sketch of the construction of
the PAD. Depending on the
choice of the user, this seetion
of the PSD generates the se-
lection signals from the ad-
dress signals and some control
signals. The PAD is a repro-
Fig. 4. The array with which the PAD is programmed.
grammable fuse array with an and E are used. Inputs es!
EPROM-like structure. Used and Reset are used to deselect
with Intel rnicroprocessors, the PAD, astate that is de-
the PAD employs, apart from sired during power-down and
inputs Au-A19, signals ALE, initializa tion.
RD and WR. With Motorola In the PSD301, signals
processors, signals RfW, AS ESo-ES7 are used 10 address

A1A2 WR RD CSIOPORT
A1 A2 WR AC CSIOPORT

CSO-CS7

REAO'----
PIN

MUX
MUX BPORT Oi
APORT Oi

0
PORT

0
WRITE Ai PIN ~:ft..E RES 01
DATA
aes Aal

CMOS OPEN csr

Ai DRAIN
o 0 CONTROL

G
aes OUTPUT
ENABLE
MULTIPLEX
MULTIPLEX REAO DIRECTION
SELECT REGISTER
I. _J.-----1-:::!-" SELECT
OPTiON
OPTION

CONFIGURATION
CONAGURATION

WAlTE RES
D1RECTION L_~
PORT B STRUCTURE
PORT A STRUCTURE ANYONEOFI",OT07
08- 015
AOO ·A07 ANYONEOFi"OT07

940110-16
940110·15 RESET
ALE RESET

Fig. 5. Structure behind a single 110 line 01 port A. Fig. 6. Structure behind a single 110 line 01 port B.

ELEKTOR ELECTRONlCS DECEMllER 1994

 COMPONENTS

Two new books from Elektor Electronics

Build gOUT own Electronic Test
Instruments
In the testing and inspection of
I Build your own
Short course 8051/8032
Microncontrollers and assem-
bler
electrical and electronic equipment
a vartety of elcctronrc test Instru-
Electronic test This book prescnts a course which
descrtbes the hardware and the
ments is required. Most ofthese in-
struments are, of course, commer-
instruments software (assembler code) to make
a complete rnicrocontroller system.
cially available. However, Ior all The controller used is selected
kinds ofreason [cost, challenge) from the MCS-51 farruly produced
many researchers. enthusiasts and by Intel and others.
experimenters like to build such in- In addition to an extensive descrtp-
struments themselves. tion ofthe eontrollerboard and its
This book may heip them: it con- anctllanes, this book teaches you
tatns destgns for 17 measurtng to program MCS-51 mtcrocon-
instruments. seven generators and trollers in assembly code. ustng a
analysers, ten mtscellaneous large number oftested and exten-
instruments arid a number of an- sively documented examples.
cülanes and auxtlianes. The From the contents:
designs range from a simple multi- • low-cost controller eard
core cable tester to a • hardware extensions
sophtsucated legte analyser. Most • 8051 instruction set
of the destgns contain a spectal • programming
prtnted ctrcutt, full-scale drawings • analogue stgnal processing
[with a Iew exceptions) of wluch are • port programming
given in an appendix to atd the con-
struction. ISBN 0 905705 38 6
Beginncrs in electronics may find Price il9,95
the first chapter, dealing with mea- Published November 1994
surement techniques, a good introduction to the fasctnatrng
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in thts chapter many worthwhile refreshers on measure- bookshops, schools, colleges. ete. should be sent to
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ISBN 0 905705 37 8
Price il 15,95
Published December 1994

Elektor Electronics (Publishing), PO Box 1414, Dorchester, Dorset, England DT2 8YH.

the EPROM banks. There is
always one produet term
available per EPROM bank. A
produet term, RSO, ts also
used for seleeting the statie
memory.
The address and eontrol
lines of the EPROM are split
irrte a block capacity of 4 to
16 kbyte. The exaet locaticn of
the bloek in the address range
of the proeessor can be deeided
freely by the user. The 2 kbyte
available for the static RAM
can be seleeted in a aimilar
manner.
Other produet terms pro-
vided by the PAD are CSIO-
PORT, CSADIN, CSADOUTl
and CSADOUT2. The single
product term CSIOPORT de-
termines the base address of
ports A and B. An offset must
be added to this base address
to reaeh the various registers.
'Table 1 shows the structure of
this division.
Port structure
The eomplete port section of
tbe PSD3xx chips eontains
three registers: A (8 bits), B (8
bits), and C [3 bits). These
registers support various 1/0
fuuctions. For example, ports
A and B may be arranged as
8-bit VO ports tb at send data
to, and reeeive data from, ex-
ternal eomponents. Figure 5
shows the structure of a single
eell in port A, while Figure 6
shows that of a single eell in
port B. Writing data to a port
is the same as writing data to
a RAM location.
Although a port ean not be
addressed at bit level , it is
possible to determine of each
I/O line whether it is arranged
as input or as output. Any
eombination of inputs and out-
puts (for example, PAO-PAS the I/O pins of port A and/or
input and Pi\o and PA7 output) port B.
is thus possible. After a reset, all bits in the
Whether an 1/0 pin is data direetion register are low
arranged as an input or an level, that is, the ports are set
output can be determined as inputs. If in the applieation
with the data direction regis- only inputs are used, nothing
ter. Sinee this register oper- more needs to be done. If out-
ates dynatnically, it is possible puts are wanted, the assoei-
during the exeeution of a pro- ated bits must be made high.
gram to adapt the function of [940110)
Name ofregister Offset w.r.t. base address
Pin register port A +2 (byte)
Pin register port B +3 (byte)
Diraction register port A +4 (byte)
Direction register port B +5 (byte)
Data register port A +6 (byte)
Data register port B +7 (byte)
Pin register ports A and B +2 (word
Directionregister ports Aand B +4 (word)
Data register ports A and B +6 (word)
Table 1, Addressing 01 Ihe ports.

ELEKTOR ELECTRONICS DECEMBER 1994