2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE)
Ultra-Low Power Op-Amp Design with
Memristor-based Compensation
Mohammad Rasekh Jahromi†, Jafar Shamsi*, Amirali Amirsoleimani**,
Karim Mohammadi*, Majid Ahmadi**
mohammad.rjahromi@student.uni-siegen.de { jafarshamsi, mohammadi}@elec.iust.ac.ir
†
Department of Elektrotechnik Informatik, Universität Siegen, Siegen, Germany
*
Department of Electrical and Computer Engineering, Iran University of Science and Technology, Tehran, Iran
**
Department of Electrical and Computer Engineering, University of Windsor, Windsor, Canada
Abstract— In this paper, an ultra-low power single output two
stage CMOS operational amplifier (Op-Amp) is designed based on
using a novel memristor-based compensation technique. Also, a
novel memristor programmer is applied for regulating the
memristance of the compensation block of the proposed Op-Amp.
By applying memristor as a potentiometer, the proposed Op-Amp
can regulate its right half plain zero to improve stability and phase
margin. Simulation results are presented for proposed ultra-low
power single output two-stage CMOS Op-Amp. The two-stage
CMOS Op-Amp is designed in 0.18 μm CMOS technology. The
proposed Op-Amp exhibits 94 dB DC gain. The unity gain
bandwidth (UGB) is 1 MHz and the Op-Amp consumes only 2.7
µW while most transistors are in saturated region. The phase
margin of the proposed Op-Amp is 47 degree.
I. INTRODUCTION
M
emristor as the fourth fundamental element was
discovered in HP laboratory in 2008 [1]. In [2], operation
of an analog circuit based on memristor is divided into
programming phase and main working phase. In programming
phase, the memristance of the memristors in the circuit should
be changed from their initial value to proposed values based on
the design specification of the analog circuit. Subsequently in
main working phase the programmed memristors are
considered as simple resistors in the circuit.
One of the significant challenges in operational amplifiers as
one of the most common analog circuit is the compensation
issue. Accurate adjusting of dominant poles and zeroes is
considered for compensation in analog circuits for improving
bandwidth, gain and frequency response. Several works in the
literature were presented different compensation techniques
based on conventional CMOS technology [3][4][5]. These
compensation techniques require a separate compensation
circuit beside the main circuit which is a major drawback. This
additional block is increased the area and power consumption
of the amplifier dramatically.
In this paper, a novel ultra-low power Op-Amp is presented by
utilizing emerging memristor technology for its compensation.
This compensation is inspired from Miller compensation
technique [5]. For regulating the memristance of the memristor
a programmer is designed. This memristor programmer has
some advantages over its peers [2] [6]. Unlike the previous
works, the proposed programmer can be used in several
integrated circuits. Also using this circuit in the designed Op-
Amp is more efficient in terms of the total area and power
consumption of the circuit in comparison with conventional
978-1-5090-5538-8/17/$31.00 ©2017 IEEE
{amirsol, ahmadi}@uwindsor.ca
CMOS designs that include resistor or current source in their
circuits for compensation.
II. ULTRA-LOW POWER OP-AMP DESIGN
Since multi-stage amplifiers have more poles and zeroes than
single-stage amplifiers their frequency response and time
response are more complicated than the single-stage peers.
Therefore, all multi-stage amplifiers suffer closed-loop stability
problems. One of the common compensation techniques is
using single Miller approach [5] which requires placing a
compensation capacitor between input and output nodes of the
second inverting amplifier in a two stage amplifiers. The
dominant pole is created due to the Miller feedback. For
eliminating the right half plane zero a null resistor is placed in
series with Miller capacitor [7]. In circuit design, fabricating a
resistor in an integrated circuit is not preferred since it requires
a considerable area.
Here, an ultra-low power two stage Op-Amp is designed by
using memristor-based compensation technique. This Op-Amp
is consisted of one NMOS differential pair cascaded with a
PMOS differential pair that is followed by a PMOS common
source amplifier. Also a current mirror is used to create the tail
current of cascaded amplifier stage. For compensation block, a
memristor programmer and a series memristor with one
capacitor are utilized as shown in the Fig. 1. The idea in this
technique is using the non-volatile behaviour of memristor to
eliminate the right half plane zero in Miller technique.
The memristor device can be regulated based on the desired
resistance with the programmer circuit to push the right half
plane zero to infinity. Since a capacitor is in series with the
memristor, DC currents cannot pass through memristor during
Op-Amp operation phase. Also, considered values for the
current passing through first and second stages of the op-amp
are insufficient to make any change in memristor state. This
results the memristance not to change and remain constant for
compensation issue. The small signal model for this Op-Amp is
shown is Fig. 2 and the transfer function can be written as,
  C  
a1  s C   MRC C 
 
  gm II   ,
H ( s)  (1)
1  bs  cs 2  ds 3
where,
a  gm I gm II R I R II , (2)
b  (C II  C C ) R II  (C I  C C ) R I  gm II R I R II C C , (3)
 2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE)

2
VDD Vout1 Cc MR Vout2

Vin
M3 M4 gmIVin RI CI gmIIVout1 RII CII
M6
Vout1
Cc Vout2
Fig. 2. Op-Amp small signal model of two stage Op-Amp with memristor-based
M1 M2 MR compensation.
Vin
M1 A M6

M8 M7
M5

M2 MR M5
Vss
Fig. 1. Proposed two stage Op-Amp design.
B
M3 M4
c  R I R II C I C II  C C C1  C C C II   MRC C R I C I  R II C II  , (4)
Vin
d  R I R II MRC I C II C C , (5)
where gmII, RII and CII are transconductance, resistance and
capacitance of stage II of the Op-Amp. Also gmI, RI and CI are
Fig. 3. The proposed programmer design topology based on three NMOS and
transconductance, resistance and capacitance of stage I of Op- three PMOS transistors with 0.18 µm technology.
Amp circuit. The CC is the capacitance of the compensation
capacitor. Here in this circuit gmI and gmII are equal to the
I5
transconductance of M1 transistor (gm1) and M6 transistor (gm6) SR   I 5  0.2 A . (12)
respectively. Based on Eqn. (1) and with the assumption that CC
CII > CC > CI the first, second and third pole can be determined
Based on Fig. 1, the power consumption of the Op-Amp is,
through,
Ptot  VDD  VSS I tot , (13)
1
P1  , (6) where, I tot  I 5  I 7  I 8 .
gm II R I R II C C
In Eqn. (13) VDD-VSS = 1.8 V and Ptot = 2.5 µW so Itot = 1.4
 gm II µA (I5 = I8 = 0.2 µA, I7 = 1 µA). We also have ±0.75 V output
P2  , (7)
C II swing by giving M6 and M7 aspect ratios is as follow,
1 Swing   VDD  VDC 6(min)  VDC 6(min)  150 mV , (14)
.
P3  (8)
MRC I 
Swing  VDC 7(min)  VSS  VDC 7(min)  150 mV . (15)
The positive zero of the proposed circuit obtained from,
Subsequently, by applying the above equations aspect ratio of
1 , (9)
Z1  transistors can be determined. Then DC gain can be obtained
 1  from Eqn. (2) and it is equal to 81 dB. By using Eqn. (11)-(13)
C C   M MR 
 gm II  P1 = 21 Hz, P2 = 2.23 MHz and P3 = 19 MHz, by considering
where MMR is the memristance of the memristor. The third pole zero of the circuit at infinity, phase margin is,
is a high frequency pole and it doesn’t have a considerable      
impact on transfer function of the circuit. As it can be seen from PM  180  tan -1     tan -1     tan -1    . (16)
P
 1 P
 2  P3 
Eqn. (9) the memristor can regulate the first zero of the circuit.
By programming the memristance of MR to 1/gm2 the first zero The phase margin is about 47 degree. The parameters values
of the circuit goes to infinity. The unity-gain bandwidth of the of this circuit are shown in Table 1. Memristance of the
Op-Amp circuit with memristor-based compensation block is compensation memristor according to Eqn. (9) is 83 kΩ.
determined by,
IV. MEMRISTOR PROGRAMMER DESIGN
gmI . (10)
UGB 
2 CC For adjusting memristor’s memristance for compensation
In this work, we have designed an amplifier with 1 MHz issue, a programmer is designed and applied in the ultra-low
bandwidth, greater than 6 V/µs slew rate, 2.5 µW power power Op-Amp circuit. The proposed programmer is comprised
consumption, zero DC output offset, greater than 80 dB DC of six CMOS transistors based on the topology depicted in Fig.
gain, greater than 45° phase margin and over ±0.7 V output 3. M1, M2 and M3 are NMOS transistors. These transistors are
swing. For having 1 MHz bandwidth with 6 V/µs slew-rate (SR) cascaded. M4, M5 and M6 are PMOS transistor devices that
with capacitor CC is 0.3 pF, gm1 and gm2 can be determined cascaded to each other. All gates of CMOS transistors are
through, connected to the input. The memristor placed from the doped
gm I A region to drains of the second stage of NMOS and PMOS
 z  2UGB   gm I  gm II  2 , (11)
CC V transistors M2 and M5 respectively. Also, the un- doped side of
the memristor is connected to the source of the second stage
CMOS transistors M2 and M5. The drain terminals
 2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE)

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Table 1. Transistor’s properties are shown for proposed Op-Amp.

MOSFETs Operation Region Aspect Ratio(W/L) (µm)

𝑴𝟏 , 𝑴𝟐 Sub-threshold 18.2 / 2
𝑴𝟑 , 𝑴𝟒 Saturation 0.252 / 2
𝑴𝟓 Saturation 0.31 / 2
𝑴𝟔 Saturation 2.79 / 2
𝑴𝟕 Saturation 2.045 / 2
𝑴𝟖 Saturation 0.336 / 2

Table 2. Transistor’s properties are shown for programmer circuit.

Operation Operation
Aspect (a)
MOSFET Region with Region with
Types Ratio(W/L)
Devices Negative Positive
µm
Input Voltage Input Voltage
𝑴𝒙𝟏 NMOS Cut-off Saturation 20 / 2
𝑴𝒙𝟐 NMOS Cut-off Linear 0.75 / 2
𝑴𝒙𝟑 NMOS Cut-off Linear 8.268 / 2
𝑴𝒙𝟒 PMOS linear Cut-off 44.296 / 2
𝑴𝒙𝟓 PMOS linear Cut-off 4.86 / 2
𝑴𝒙𝟔 PMOS Saturation Cut-off 99 / 1

Table 3. Memristor parameters used in simulation for TEAM model [13].

Parameters Numerical value Parameters Numerical value

RON 1 KΩ iOFF 2 µA
ROFF 100 KΩ fON 40 µm/s
αON, αOFF 3 fOFF 3.5 µm/s
kON -8e-13 m/s xON 0 nm
kOFF 8e-13 m/s xOFF 3 nm
iON -1 µA wc 107 pm
of M1 and M6 are connected to input. Also, the source terminals
of M3 and M4 are connected to the ground. The transistor sizing
and properties are shown in Table 2.
For setting MR memristor to the desired memristance for
compensation, the proposed programmer is applied. Proposed
programmer is not turned ON until the input is zero. All CMOS
transistors are OFF in this state. By applying an input voltage
into the gates of the CMOS transistors, the programmer circuit
starts its operation. Applying positive voltage turns ON the
NMOS transistors M1, M2 and M3 While the inverse bias to the
input turns ON the PMOS transistors M4, M5 and M6. By
applying positive voltage NMOS transistors turns ON and
PMOS transistors remain OFF. The M1 transistor goes to
saturation since both voltages of the drain and gate are equal to
Vinput. M2 and M3 are in linear region and ID1 current goes
through memristor MR from the doped side. Therefore, the
doped region length start increasing in MR. This results in
memristance reduction in MR. This procedure is shown in Fig.
4a. Applying negative voltage turns ON PMOS transistors M4,
M5 and M6 while NMOS peers M1, M2 and M3 remain OFF. The
current of M6 goes into MR memristor from the un-doped side
while other two memristors M4 and M5 are in triode region. This
causes dopants return back and the un-doped region extends
over the film. This results in increasing the memristance of the
device from RON to 83 kΩ which is displayed in Fig. 4b.
V. SIMULATION RESULTS
For simulation of the proposed ultra-low power Op-Amp with
memristor based compensation block, a memristor model
presented in [13] with the parameters in Table 3 is utilized in
(b)
Fig. 4. Programming memristor with different inputs. (a) Programming
memristor with +0.9 V pulsed input voltage with 50% duty cycle and 2 Hz
frequency. Current of memristor changes from +3.62 µA to +71 µA while
memristance reaches RON from ROFF. (b) Programming memristor with -0.9 V
pulse input voltage with 50% duty cycle and 500 Hz frequency. The current of
memristor changes from -58 µA to -3.62 µA while memristance reaches 83 kΩ
from RON.
HSPICE®. Also, the CMOS transistors are 180 nm CMOS
technology. This operational amplifier is implemented with and
without programming block. In the implementation without
programming circuit the memristor device for compensation
should be first programmed with programmer. It should be
removed from circuit during the normal working phase of the
Op-Amp. For removing the programmer from the proposed Op-
Amp a CMOS switch can be applied. Although existence of the
programmer does not have a considerable effect on the gain and
phase margin of the amplifier. However, it reduces the output
swing value. For simulating the proposed Op-Amp without
programmer, the memristor should be set to 83 KΩ initially.
In this stage, -0.9 V pulsed voltage with 10 Hz frequency and
50 percent duty cycle is applied to programmer circuit. As it can
be seen in Fig. 4b, designed programmer requires 12
milliseconds to set the memristor’s memristance from RON to 83
KΩ. The proposed Op-Amp circuit with the programmer circuit
is shown in Fig. 5. Also the simulation results and designed Op-
Amp characteristics are compared with previous works in the
literature in Table 4. Simulations shows that, for 1.8 V DC
supply voltage it has 94 dB open loop DC gain and 1 MHz unity
gain bandwidth for both modes (with and without programmer
block). The DC gain for the proposed Op-Amp is displayed in
Fig. 6. The proposed Op-Amp consumes only 2.7 µW power
for its operation in both modes. The power consumption is
lower than previous Op-Amp designs. One of the best power
consumption is for the Op-Amp in [3] about 4.37 µW while the
 2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE)

4
VDD technology. The compensation block is used a bipolar
memristor device in series with a compensation capacitor. This
M3 M4
configuration allows the circuit to eliminate the right half plane
M6 zero of the Op-Amp by adjusting the memristance of the
IDC
Mx1
Cc
Mx6
proposed memristor to 1/gmII. For regulating the memristor
Mx2 Mx5 Vout memristance, a memristor programmer is designed with six
CMOS transistors. Simulation results in HSPICE ® proved that

MR
M1 M2
Vin Mx3 Mx4 Cout
the proposed Op-Amp is compensated with the memristor-
Gate based technique with 83 kΩ memristance of the compensation
M8
M5
M7
memristor. The proposed circuit is required a low power for its
operation.
Vss

Fig. 5. The proposed ultra-low power operational amplifier circuit with the
compensation block and programmer circuit. The CMOS technology for
transistors are 180 nm.
Fig. 6. The proposed operational amplifier DC gain for both Op-Amp
configurations, with programmer and without programmer.
proposed ultra-low power amplifier in this work requires 39%
lower power in each mode. Also the phase margin is 47 degree
and CMRR for the proposed Op- Amp is 100 dB. The proposed
Op-Amp slew-rate is about 5.72 V/µs for the mode that the
programmer is in the circuit and it is 6.3 V/µs for the mode
without programmer. Also the swing is between -0.850 V to
+0.850 V in the mode without programmer. By inserting the
programmer in the circuit, the swing is decreased to -0.3 V to
+0.5 V.
IV. CONCLUSION
In this work an ultra-low power operational amplifier was
introduced based on a novel memristor-based compensation
technique. The Op-Amp block is CMOS two stage amplifier
implemented by eight CMOS transistors with 180 nm CMOS
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Table 4. The proposed ultra-low power amplifier circuit in two configurations (with and without programmer circuit) compared with previous design op-Amps.

This work with This work without

Properties programmer programmer [8] [3] [9] [10] [11] [12]
Dc supply (V) 1.8 1.8 1.8 1.8 1 0.9 2.5 1.9
CMOS Technology (nm) 180 180 130 180 180 350 500 500
Open loop gain (dB) 90 90 49 73 84 62 81 44.7
Phase margin (Degree) 47 47 42 65 81 52 65 52
Unity gain freq. (MHz) 1 1 69.2 1 12.45 0.54 5 1.4
Slew-rate (V/𝝁𝒔) 5.72 6.3 11.96 N/A 9.7 N/A 5.5 1.25
Output swing (V) -0.3~+0.5 ±0.850 -0.4~+0.39 N/A ±(0.07-0.93) N/A 2.3 N/A
CMRR (dB) 100 100 89.62 147 62.5 129 N/A 88
Power consumption (𝛍𝐖) 2.7 2.7 28.6 4.37 85 9.9 378 62