Professional Documents
Culture Documents
VT220
Technical Manual
• Access mux
• Line buffer
• Character (CHAR) output circuit
FROM ,.-----...1'\
9007 SCO H-SC3 H
TO/FROM
~~~M ~
o,l..-
AO H-A3 H
..,/
CHAR
OUTPUT
CIRCUiT
CPU LOGIC
TO
LOGiC lJ CONTROLS
CHRO ,",-CHR7 H ViDEO
CONVERTER
FROM
QUART \ BNKSO H-BNKSl H
I
I .
I
FROM
8051 CPU ' - -_ _---,
FROM
I
SCREEN RAM 1..- -1 TO
ATTRIBUTE
FROM CiRCUITS
ATTRIBUTE
RAM .....-----1
ADO H-AD7 H
FRorv1
TiMiNG TIMING
GEN 1-.----..;;...,--1
ACCESS
MUX
FROM iALT SEL)
ATTRIBUTE --------1
C1RCUITS L..-_ _, j
6-16
6.2.4.1 Access Mux The access mux (Figure 6-13) selects
outputs based on select input (EN CHR GEN RW H) from the CPU
logic. Video logic inputs when select is low and CPU logic inputs
when select is high.
FROM
(Al T SEL A TTRIBU TE)
ATTRIBUTE 4A
AlT SEL TO
CIRCUITS
4Y CHAR
4B
OUTPUT
3A lBA elK l
3B 3Y
FROM
TIMING
T5 L
1 2A
ACCESS
MUX
VIDEO
LATCH H TO
GEN
FROM Vl_T L
..--- 28 2Y LINE
BUFFER
11' }
9007 lBA ClR H
r 1B
1Y
ALTSElH SEl
L8A ClKS H
6-17
6.2.4.2 Line Buffer -- The line buffer circuit is used to store
character address and attribute values during DMA transactions,
and to process those character address and attribute values out to
the character output (character address data) and attribute
(attribute data) circuits.
FROM
TIMING
{:::~~:A H
LBF WR L
CS WE OE
f_B_NK.....S_1- H - - - - - r - t - - - l A10
FROM ~ BNKSO H
FROM
r
QUART l - ' - - - - - - - - + - + - - " " ' ! A 9 LINE DATA
8051 CPU
~~:"
INPUT
OR
BUFFERS
SCREEN RAM
I FROM
ATIRIBUTE
RAM
ruN;BuFm~
TO
ATIRIBUTE
CIRCUITS
I ADDRESSj ,
I COUNTER ~~~~ TO
CHAR
I
GEN
, r LBA CLR H
:~~~ss~
MUX l LBA CLK L
6-18
• Line buffer RAM -- is a 2K X 8-bit wide RAM device that
provides for storage and processing of the following
character address data and attribute values:
• A8 input (ATR/CHR)
(ATR/CHR high)
defines character address data
or attribute value (ATR/CHR low) is
being loaded;
Figure 6-14 also shows the data input buffers which consist of two
latch devices.
Figure 6-15 provides a memory map of the line buffer RAM. Figure
6-16 shows the attribute and character latches. Later in this
chapter, Table 6-2 describes the signals shown in Figure 6-16.
6-19
.....- - - -... 7FFH
BANK 3
CHARACTER
IA8=ll
IA9=1 A10=1j I
- - - 3- -1700
BANK 6FF
H
H
ATTRIBUTE
(A8=Oi
(A9=1, A10=1) ,
I
-----,600H
BANK 2 Ii 5FF H
'I' CHARACTER
(A8=1! "
IA9=0, A10=111
- _ _ - - 500H
BANK 2 4FF H
ATTRIBUTE
(AB=O)
IA9=0,
_ __ A10=111
_ _ 400 H
I BANK 1 , 3FF H
I
CHARACTER
(A8=11
,IA9=l, A10=01
300 H
BANK 1 2FF H
ATTRIBUTE
n (AB=O)
I (A9=], A10=01
- - - - -1200 H
BANK 0 l1FF H
CHARACTER '
(AB=1)
IA9=0 A 10=0)
- - - - - 100 H
BANK 0 OFF H
ATTRiBUTE
t
I (A9=O, A 1O=O) I
(AB=OI '
! 1 000 H
FROM
CHAR
B051 CPU .i.:..~;";";";"';;;'"
LATCH TO
FROM 1 CHAR
SCREE'N RAM4- --J OUTPUT
FROM TO
ATTR IBUTE .L.;.;A..;;,D..;;,0_H;.,-_A;,;;D,;.7,;.H_ _... ATTRIBUTE
RAM CIRCUITS
6-20
6.2.4.3 Character Output Circuit -- The character output circuit
generates the dot matrix character pattern used for the display.
The character output circuit (Figure 6-17) consists of the
following components.
FROM
SCO H-SC3 H TOiFROM
9007
ADDRESS CPU
MUX LOGIC
AO H-A3 H
EN CHRGEN RW H
FROM
CPU WR L
TO
LOGrC EN CHRGEN L
VIDEO
CONVERTER
RDL
CHRG SEL H
ALT SEl H
FROM
ACCESS
MUX
CHAR CHAR
FROM LATCH GEN
IADDRESS DATA!
LINE 2 ROM
BUFFER
OE
FROM T5L
TIMiNG
GEN R73
NOTE
WRITE LINES FROM READ,WRITE BUFFER ARE SAME LINES AS CHROH- CHR7H
THEY ARE illUSTRATED SEPARATELY FOR CLARITY OF BUFFER FUNCTION
6-21
• Alternate character generator RAM contains "soft"
character set (down-line loadable characters), with font
storage of up to 94 characters (each character consisting
of 10 bytes of data, one byte r each scan line).
r ;;1'.1 1FILL
11 EX H/01 FX H
y ~ ~
FilL
CHARACTERS
1AOX H/OAOX H !--_ _
CR_M_I_l2 _7-_1_60_1_---1
lA1X H/OA1X H DEC
SUPPLEMENTAL
- DEC
1 FOX H/DF OX H SUPPLEMENTAL
1 EEX H/OFEX H CRM 12541 CHARACTERS
1FFX HIOFFX H
CRM (255)
6-22
characters (CRM0-CRM3l) packed one character per each 5 data rows
(ROM space not taken up by character font data is filled with FFH
data) .
Figure 6-19 shows that each of the 256 characters packed one
character per data row consist of 10 bytes of data, one byte for
each scan line of the character. When addressing one of these
characters, a single base address is provided to the character ROM
by character latch 2, and each of the 10 scan lines is addressed
by the address mux input.
SCAN LINE
ADDRESS
.
BASE
ADDRESS
II su
X~O
I I I
SL2
X=l
SL3
X=2
SL41 SLS! SL6l SL7
X=3 X=4 X=5 X=5
I
SLsl SL91 SL10
X=7 X=B X=9
100X H/OOOX Hi (CRM 32! f-s PACE
101 X H/OO; x H
; 02X H i 002X H,
f-- (SGC 961 -
~
(SGC 971 - D EC
103X H/003X H
104X Hi004X H f--
(SGC
(SGC
98)
99)
- SP ECIAL
- G RAPHICS
CHARACTERS
-
l;DX H/O;DX HE
11 EX
l1FX
H
H/O; EX
H/01FX
H
F (SGC 124)
(SGC 125)
(SGC 126)
-
-
(96-126)
R EV. QUESTION
120X H/020X
H( (CRM 261 ~(E RROR
121 X H/02; X
H (CRM 331 HARACTERI
122X H/022x H I-- (CRM 34) -
123X H!023X H
I-- (CRM 351 - SCII
f- - };HARACTERS
17DX H/07DX H
I-- -
17EX H/07EX H
I- (CRM 1251
(CRM 1251 -
1 7FX H/07FX H
lS0X H/OBOX H f -
(CRM 127)
(CRM 1281 -
181 X H/081 X H
I--
(CRM 129) -
I-- - CR M
CHARACTERS
19EX H/09EX H
I--
(CRM 1581
- 11 27-160)
19FX H/09FX H
I--
(CRM 1591
-
1AOX H/OAOX H
I--
(CRM 150) -
1A1 X H/OA 1X H (CRM 151)
1A2X H/OA2X H
I--
(CRM 162)
-
1 A3X HiOA3X H
I- - C
I--
(CRM 153)
- SU PPLEMENTAL
F=" -=
J"
1 F8X HiOFBX H (CRM 251) CH ARACTERS
1FCX H/oFCX H
I-
(CRM 252) -
1FOX HiOFDX H
I--
(CRM 253)
-
1 FEX H/OFEX H
1FFX HiOFFX H
6-23
ODD EVEN
SCAN LINE CAM LINE
ADDRESSES 10-311 ADDRESSES
~~~~
100A KIODOA H
lOlA H/OO1A H
102 A H/002A H
103A HI003A H
104A H/004A H 1048 HI0048
105A HI005A H 1----1.-~ 1058 H!0058 H
10M H!OOSA H 1068 H/0068 H
l07AH/007AH Ii} 107BH/007BH
108A HJOOSA H 10SB H
10BA H!ODBA H
10AA HIDOAA H 1 - - - - - 1
193A H!OB3A H
194 A H!094A H
195A HI095A H I-----{
196A HIOBBA H
197A HIOB7A H
198A H
lB9A H:099A
19AA H/09AA 14
198A HIOBBA H ;;.....----1
1geA H/0geA H
190A HIOSOA H
I HIOSEA
ISEA HIOSE,A
6-24
FROM _--:.B_L_iN_'K_H_ _
DUART ~ FROM
NORM FiElD H
CPU
LOGIC
BLINK ATR H BLINK ATR H
~~DEO
BOLD ATR H
FROM
\ BOLD ATR H }
CHAR ATR REV ATR H ATR
GEN LATCH I.ATCH OUTPUT
REV/NORM
u.~__--t~3~~
4
ULATR H TO
~C~I.K~C~L~Rr---- VIDEO
FROM , CONVERTER
I
-+1------+1 J
TIMING i - - - ' I (AL T SELl TO
GEN \ T51. '-t--- .. CHAR
~-!C-l-Ri---<------'---+i
'j 8 r - I -t
FROM
GEN
l
I
JlI
BLANK CBLANK L
CIRCUiTS CLR r-." -.-.JI I
VLT H GATE
c~
FROM
9007 S~~
SC1H
<
H II
_
-<1\-J
~
P - tAiR
> JHU I .
i I
6-25
6.2.6 Video Converter
• Conversion control
• Parallel-to-serial (pIS) converter
6-26
FROM Ul ATR H TO
(SERIAL DATA)
ATIRIBUTE VIDEO
CIRCUITS OUTPUT
...
FROM
CHAR
{
\CHRl H-CHR7 H /
y " p·S
CONVERSION
GEN
I -
CHRO H
CBLANK l -I Sl
CLR CK CillNH
FROM
i Or
BLANK
CIRCUITS
IClR} Y
DOT ClK H
T5l
FROM
TIMING
GEN
{ T3H
T2L
II! I
CONVERSION - - - - '
CONTROL
FROM
9007 { CURS H
CBLANK H
,1
Figure 6-22 Video Converter Block Diagram
INH
LATCH
r~ T3H
HR LD l
FROM
TIMING i' _T_2_L +-_-t_ _-t_-.;
lOAD
GEN L .._ ./
FIF
lOOT ClK H
TO
P-5
C B LHA = D - J N K CONVERTER
FROM [
9007 L
CURS H r-"'--t--.L-+-+-t--l--~
CURSOR
SKEW
FIF
FROM CG BLANK H
BLANK - - - - - L__ ...J
CIRCUiTS
6-27
6.2.6.2 Parallel-to-Serial (PIS) Converter -- The piS converter
performs the actual parallel-to-serial conversion of dot matrix
data, and in the process performs dot stretching. It converts
single "on" dots into two adjacent "on" dots (and, due to
construction of the dot stretching circuit, converts the last "on"
dot of a sequence into two dots as well).
c ••••
• '
.• • ••••
_.c
--
AFTEr, DOT STRETCHING
._
._ ._.. _c . _.
..
- .-_.-._.-
S.c • . • • . c .... _ _ _ _ • _ _ c
6 .•••••••...•• c •••
7 •. c •• c • • • • • •
B.. ••
9 •.
10 • c
..
I~I J..
T BRIGHTNESS LOSS SIMPLE LOGIC ADDS ONE PULSE TO THE
~INPUTL ~
TRAILING EDGE OF ANY INCOMING PULSEc
INPUT OUTPUT
MONITOR
PULSE REsPONSE • JTL
THE MONITOR RESET TiME is TOO SLOW TO REACH MAXIMUM
BRIGHTNESS BEFORE THE SHORT PULSE FALLS.
6-28
The piS converter (Figure 6-26) circuit consists of the following
components.
The outputs from the serial latch are gated with the underline
attribute (UL ATR H) to provide all high output to video output
circuit during processing of the ninth scan line of a data row
when underline attribute is selected.
FROM UL t,TP H
ATTRIBUTE --,
CIRCUJTS
(SERIAL
DATAi
)Q-_ _ TO
ViDEO
FROM
CHAR
GEN
CHRO H
FROM
TIMiNG DOT eLk H !
GEN
FROM {ICLR
BLA~K"
CIRCU" S l
CBLANKe
-C-HR-.-----+-~_L_J
FROM {
CO~VERSION ....J
CONTRO,. ..
6-29
6.2.7 Video Output
The video output circuit converts serial data input from the video
converter into video outputs to the monitor circuits and an
optional monitor device.
fiNPU~~:~'~ 14rlCt5MPOs.TIVI0E0-
STAGE II OUTpuT STAGE +12V
- - .,
I
ro.. TVBH R14
I' 'II I
DUART ""1'" C
'It 55 R
13
(REV/NORM, I ~ II R
6-30
• Input stage gates data gate value with blink, bold,
and blank attribute inputs to provide biasing to
composite video output and video output stages.
NOTE
A complete pin-out for Jl is provided in
the system communication logic
description presented in Chapter 5
(Figure 5-9).
6-31
Table 6-2 Video Logic Signal Descriptions
6-32
Table 6-2 Video Logic Signal Descriptions (Cont)
Mnemonic Signal Description
ATR/CHR Attribute/c~aracter Timing generator output
controlling transfer of
attribute (ATR/CHR low)
and character address
values (ATR/CHR high)
into line buffer RAM
(during DMA
transactions) or out of
line Buffer RAM to
attribute latch 2 and
character latch 2
(during active line
time)
BAD0--BAD7 H Buffered data bits 0-7 Data bus used by CPU
high logic to transfer data
to and from 9007 VPAC,
or to and from the
alternate character
generator RAM, and by
video logic to transfer
character address data
from the CPU logic RAM
to the character
generator circuit
BLINK H Blink high DUART signal which
produces blink rate at
screen; BLINK H is
gated with blink
attribute (BLINK ATR H)
at attribute circuits
with BLINK H high for
blink off at screen and
low for blink on
BLINK ATR H Blink attribute high Enables blinking
display at screen
through biasing of
video output stage
circuit (intensity of
video output increased
for BLINK ATR H high
and decreased for BLINK
ATR H low)
6-33
Table 6-2 Video Logic Signal Descriptions (Cont)
6-34
Table 6-2 Video Logic Signal Descriptions (Cont)
Mnemonic Signal Description
6-35
Table 6-2 Video Logic Signal Descriptions (Cont)
6-36
Table 6-2 Video Logic Signal Descriptions (Cont)
Mnemonic Signal Description
6-37
Table 6-2 Video Logic Signal Descriptions (Cont)
6-38
Table 6-2 Video Logic Signal Descriptions (Cont)
6-39
Table 6-2 Video Logic signal Descriptions (Cont)
Mnemonic Signal Description
6-40
Table 6-2 Video Logic Signal Descriptions (Cont)
NOTE
The reference information provided in
Table 6-3 is based Rev. A of the logic
board schematics (CS 5415653-9-1).
6-41
Table 6-3 Video Logic Schematic References
6-42
CHAPTER 7
KEYBOARD (LK201)
7.1 INTRODUCTION
PS ANO
MONITOR
BOARD
AC MONiTOR
INPlJT '--,....-,.1 Clf<;U ITS
LOGIC
BOARD
7-1
7.2 PHYSICAL DESCRIPTION
The VT240 Series terminal keyboard (Figure 7-2) has 105 keys
arranged in the following four groups.
7-2
You can install the keycaps manually, but you need a special tool
to remove them.
You can lift a plastic window along the top edge above the special
function keys to insert a user function label. The label, a thin
paper' strip, fits into the indented space and varies according to
the application program.
You can place the cable in a channel in the bottom case and the
modular type telephone connector fits into jack J4. You can insert
the cable in the channel on either side of the keyboard. Section
7.6 provides keyboard specifications.
r-
, ,
4 WiRE
KEYBOARD
CABLE MONiTO"
,-,
I!
KEYBOARD
!
I
I
!
!
I
I
I
i
+12V
GND
SYSTEM
BOX
i I I
C! RCU1T I I I I
BOARD I I I I
I I SERIAL OUT i I -------,
I
I
I
ISEPlALiN ,
I I
I
CENTRAL
PROCESSOR
I
I
,
- I
'f
I _ _ _ _ _ --JI
I
PART OF
VIDEO
CABLE
7-3
7.3 FUNCTIONAL DESCRIPTION
r-
-
BCD TO -1 KEYBOARD
+5V LEO
DECIMAL
DECODER 8 0,
P I I P
10 4
LEOs
CONTROL SUPPLY
~ I I R CIRCUIT
18 I I T
1
_J I 2 BEEPER
( ) CONN. I BEEPER ]" JL BEEP=KEYCLICK
I I
3 CONTROL 2 MS
1<8 DRIVE
()'17 CONN
pi
I
~- ON/OFF CIRCUiT Y ~BEEP.BELL
KEYBOARD
,,-., KB
DAiA a'
1 2KHz 125MS
..------.-,.-~=---,J
MATRiX
" I
18 X 8 LINES 8 07 T i TIMER
o I I. TIMING NO 1 -IOV
_J 8051 i NETWORKS ~-T-IM-E-R--" 190 KHz SUPPLY _·10V
• MICRDPROCESSO~ I - NO.2
r -I
I ,
I P I JUMPERS FOR
10 I HARDWARE 10
I R I
i
IT
I3 ....
I
}
I RECEIVE r"'
POWER UP RECEIVER
I
+5V_
RESET
SIGNAL
CIRCUIT
~---.{RfSET I
I TRANSMIT
"""" CO NFORMS
TO RS-423
DRIVER SERIAL OUT
L_ 1
-IOV
t
4KB ROM
+12V
128 BYTES RAM +5V
SUPPLY I-- +5V
GND
'-'
J4
KEYBOARD
CABLE
CONNECTOR
7-4
The firmware in the 8051 8-bit microprocessor controls the
following three major keyboard operations at the same time.
The firmware scans the lS-line axis and detects a pressed or newly
released key by reading the 8-line axis. The firmware then
verifies the detected keystroke and changes this position
information into an a-bit code that is unique to that key.
Power-Up test
Keycodes
Special codes
7-5
Power-up Test
Keycodes
Special Codes
7-6
7.4 Detailed Keyboard Circuit Description
This section describes the keyboard circuit. Figure 7-4 shows the
keyboard block diagram.
2 TYPE
74LS 145
DECODE RS
r---
I PORT 1
i8 BCD
I
1BXBlINE
I SCA',S MATRIX
! MATR:X INPUTS
L... _
8 UNES AND 18
DECIMAL
18 LINES
KB DRIVE 0-17
I
OUTPUTS}
r---
I PORT 0
I READS
I KEY
[,S 8 ur;ES
KB DATA (n
h
I
TYPiCAL. S\\!ITCH
CONNECTION AT
MATRiX
INTERSECTION
7-7
The 8051 scans the 18 drive lines. Key closures are detected by
reading the eight data lines. The complete matrix is scanned every
8.33 ms.
DRiVE
LINES
DATA
LINES
7-8
Table 7-1 Keyboard Matrix
Refer to Figure 7 (A and B). It shows the international matrix for the LK201
keyboard. The legends are from the LK20l keyboard and are provided for convenience
only.
KB KB DATA
Drive 7 6 5 4 3 2 1. o
17 Reserved F19 Reserved F20 PF4 N N, ENTER
(Note 1)
NOTES
1. Note that N0 -- N9, N_, N" refer to the numeric keypad.
2. N0 of the numeric keypad can be divided into two keys. Normally only the N0
keyswitch is implemented as a double-sized key.
3. The RETURN key also can be divided into two keys. The one that is decoded as
return is the RETURN (C13) key.
Table 1-1 Keyboard Matrix (Cont)
KB KB DATA
Drive 1 6 5 4 3 2 1 0
KB KB DATA
Drive 7 6 5 4 3 2 1 0
0 SHIFT
B99,B11
7-12
BBGL::JB BBBBB G[~GG
---
-Gr=:::--] BBBB
GGGGCJc:JGGGc:JGGGc:J G[J[J c:J[JGG
~~oGGGGGoGGG~J[JD [J8B G8GB
~ rGOGGGGBBGGGEJL][J '" [J GGEJEJ
C:=JGGGGGGGGGGGr--::] DGG GGGn
-'[=:=]1 '01t0'~ ~.
C:~GL:J
ftttOTE rHE- GRAPHIC CHAPACTf ns ARE SHOWN rnA It \ tlSTRAT10N PUAPOSfS ONt y
ANO ARE NOT MEANT TO AS~IGN l({ yeAP U~>Af;f ()r! l. f (J[NOS
A low signal from the 8051 drives the inverter output high, which
cuts off the LED. A high signal from the 8051 drives the inverter
output low. This provides a path to ground from the +5 V through
the LED. The LED then turns on.
7-14
,...-----r--+12V
BEEPER
74LS05
INVERTERS
ON/OFF CONTROL
8051
PORT 2
2KHZIU
74LS05
INVERTERS
A--r--+12V
805'
PORT 2
HIGH
r--------
+ HIGH SIGr,AL FROM 8051 PROVIDES
PATH THROUGH LAST STAGE OF
OPEN COLLECTOR INVERTER TO TURN
ON LED
7-15
7.4.4 Keyboard Communication
r CHARACTER °1
I I'" 8 DATA BITS "'I
,-"'-T-
1-_.L.-
MARK (11----, T--r-,. -T--r - , . , .
I
SPACE \01
I I I
J.
I 1 I I I I
_.L _..1. _.I. _.I. _1. _J i
START STOP
BIT BIT
MA,026ti"*2
7-16
7.4.5 Reset Signal for 8051 Microprocessor
There are six jumpers. Each jumper line goes from an input in PORT
3 of the 8051 to ground. All jumpers are installed so the keyboard
hardware 10 is zero.
7-17
Table 7-2 Keyboard Functional Divisions
Division Description Representation
1 48 graphic keys and spacebar 130131
2 Numeric keypad 1313113
3 Delete character (E12) 131311
4 Return (C13) Tab (0130) 0100
5 Lock (C1313) Compose (A99) 0101
6 Shift (B99 and B11) CTRL (C99) 0110
7 Horizontal cursors 0111
(B16 and B18)
7-18
Table 7-3 Keycode Translation Table
Keycode Keycode
Division Position Keycap Decimal Hexadecimal
Function Keys
11 Reserved 099 63
G05 Interrupt 100 64
G06 Resume 101 65
G07 Cancel 102 66
G08 Main screen 103 67
G09 Exit 104 68
Reserved 105--110 69--6E
12 Reserved III 6F
Reserved 112 70
GIl Fll (ESC) 113 71
G12 F12 (BS) 114 72
G13 F13 (LF) 115 73
G14 Additional 116 74
Options
Reserved 117--122 75--7A
13 Reserved 123 7B
G15 Help 124 7C
G16 D0 125 70
7-19
Table 7-3 Keycode Translation Table (Cont)
Keycode Keycode
Division Position Keycap Decimal Hexadecimal
Keypad
2 Reserved 145 91
A20 0 146 92
Reserved 147 93
A22 148 94
A23 Enter 149 95
820 1 150 96
B21 2 151 97
B22 3 152 98
C20 4 153 99
C21 5 154 9A
C22 6 155 98
C23 156 9C
D20 7 157 9D
D21 8 158 9E
D22 9 159 9F
D23 160 A0
E20 PFI 161 Al
E21 PF2 162 A2
E22 PF3 163 A3
E23 PF4 164 A4
Reserved 165 A5
Cutsor Keys
7 Reserved 166 A6
B16 Left 167 A7
B18 Right 168 A8
6 Reserved 173 AD
B99,B11 Sh i ft 174 AE
C99 CTRL 175 AF
7-20
Table 7-3 Keycode Translation Table (Cont)
Keycode Keycode
Division position Keycap Decimal Hexadecimal
Special Codes
Delete
7-21
Table 7-3 Keycode Translation Table (Cont)
Keycode Keycode
Division Position Keycap Decimal Hexadecimal
1 Reserved 223 OF
E0'7 &7 224 E0
D0'7 U 225 El
C07 J 226 E2
B0'7 M 227 E3
Reserved 228 E4
C0'8 *8 229 E5
00'8 I 23@ E6
C0'8 K 231 E7
B0'8 I I
232 E8
Reserved 233 E9
E0'9 (9 234 EA
00'9 0' 235 EB
C0'9 236 EC
B0'9 237 ED
Reserved 238 EE
El0' ) 0' 239 EF
DIe p 240' Fe
Reserved 241 Fl
Cl0' · ,. 242 F2
Bl0' ? / 243 F3
Reserved 244 F4
E12 + = 245 F5
D12 } ) 246 F6
C12 I \ 247 F7
Reserved 248 Fa
Ell 249 F9
011 T[ 250' FA
Cll · ,
Reserved
251
252-255
FB
FC-FF
NOTE
The legends under "keycap" are taken from the keycap legends of
the LK20'l-AA (American).
7-22
7.5.2 Modes
Example 1
a metronome metronome
Example 2
a metronome metronome
7-24
7.5.2.2 Special Considerations Regarding Down/Up Mode -- If two
DOWN/UP keys are released simultaneously (within the same scan),
and there are no other DOWN/UP keys down on the keyboard, only one
ALL UPS code is generated.
If either the BI1 or B99 keys (the left and right SHIFT keys on
the LK20l) or the C99 key (the CTRL key on the LK20l) are pressed,
the keyclick is not generated. However, if a command is sent from
the system module to enable the keyclick on the C99 key, the
keyclick is generated (refer to section 7.5.5.3). Figure 7-7 shows
the positions of these keys.
The keyclick or bell {or both) may be disabled. When the keyclick
or bell is disabled, it does not sound. If the system module
requests sound (refer to section 7.5.5.3) the keyclick or the bell
does not sound.
7-25
Both the keyclick and bell may be independently set to one of the
following eight volume levels.
000 highest
001
010 default
011
100
101
110
I I I -- lowest
Refer to Figure 7-7 and Tables 7-1 and 7-2 for complete keycode
matrix translation table information.
The following nine special codes have values above 6410 (keycode
value range).
7-26
• INPUT ERROR Keycode 182 (decimal)
B6 (hexadecimal)
,
ALL UPS -- indicates to the system module that a DOWN/UP MODE key
was just released and no other DOWN/UP keys are pressed.
7-27
• KEYBOARD 10 (firmware) Keycode 01 (decimal),
01 (hexadecimal)
• KEYBOARD 10 (hardware) Keycode 00 (decimal),
00 (hexadec imal)
• KEY DOWN ON POWER-UP ERROR CODE Keycode 61 (decimal),
3D (hexadecimal)
• POWER-UP SELF-TEST ERROR CODE Keycode 62 (decimal) ,
3E (hexadec ima I)
7-28
If the keyboard finds a key pressed on the first scan, it
continues to look for an ALL UPS condition. The keyboard sends the
corrected four-byte power-up sequence when the pressed key is
released. This avoids a fatal error condition if a key is pressed
by mistake while powering up.
The keyboard LEOs are lit during the power-up self-test. If the
self-test passes, the keyboard turns the LEOs off. If a bell is
selected on powerup, the system module can transmit a sound bell
command to the keyboard. However, this should not be done until
the system module receives the last byte of the four-byte
sequence. The request for self-test tests the serial line and
system module connection. The power-up self-test takes 70 ms or
less.
The system module can request a jump to powerup at any time. This
causes the LEOs on the keyboard to blink on and off (for the
power-up self-test) •
COMMAND
07 06 05 04 03 02 01
o REPRESENTATION
PARAMETERS
~ DATA
~ DATA
..... ·O'1.e~
7-29
7.5.5.1 Commands There are two kinds of commands, commands
that control keyboard transmission characteristics and commands
that control keyboard peripherals. The low bit of the command is
the TYPE flag. The TYPE flag is clear if the command is a
transmission command, and set if the command is a peripheral
command.
The high order bit of every command is the PARAMS flag. If there
are any parameters to follow, the PARAMS flag is clear. If there
are no parameters to follow, the PARAMS flag is set.
7-30
The following eight commands control the keyclick and bell sounds.
• Disable keyclick
• Enable keyclick and set volume
• Disable CTRL keyclick
• Enable CTRL keyclick
• Sound keyclick
• Disable bell
• Enable bell and set volume
• Sound bell
7-31
To send a peripheral command, set the TYPE flag (low order bit).
Bits six -- three contain a command representation from the chart
below. Bits two and one specify on (01), off (00), or sound (11).
Bit seven should be set if there are no parameters to follow.
Flow control
Indicators
Audio
Autor t
Other
7-32
Command Representation
o 0 0 0
LED 4 LED 3 LED 2 LED 1
morn
07 06 05 04 03 02
3-B;T
01 00
VO~UME
7-33
The audio has the following volume levels.
000 -- highest
001
010
011
100
101
110
III -- lowest
Either keyclick or bell (or both) can be disabled. When the
keyclick or bell is disabled, it does not sound, even if the
system module requests it.
7-34
7.5.5.4 Mode Set Commands -- This section describes the mode set
commands. It does not provide information about division mode
settings. Refer to section 7.5.2 for an explanation of
transmission modes and rates.
Modes Representation
Down only 00
Autorepeat down 01
Down/up 11
7-35
Autorepeat Rate Buffer Values -- At keyboard power-up time, the
four autorepeat rate buffers contain default values (refer to
section 7.5.2.3 for autorepeat rates and section 7.5.7 for
defaults). The system module may change these values.
In the command byte, bit seven (PARAMS flag) should be clear, bits
six three are 1111 (to indicate that this is a rate set
command), bits two and one should be the buffer number (0 -- 3),
and bit zero (TYPE flag) is clear.
NOTE
This code (635) is reserved for internal
keyboard use. 00 is an illegal value.
RATE CHANGE
PARAM COMMAND BUFFER NO. TYPE
~,,.... _ _..JA_ _- - . . , ~
07 06 05 04 03 02 01 00
0 1
I I I I I I
1 1 1 1 1 0
0 PARAMETE R 1 (TIMEOUT)
1 PARAMETER 21INTERVAL!
7-36
The lowest rate which can be implemented by the keyboard is 12 Hz.
Values as low as 1 can be transmitted, but are translated to 12
Hz.
NOTE
The system module must not send 125
(11111191) • This code is the power-up
command.
7.5.6.1 Error Handling -- There are four error codes. The first
two are sent at power-up if the self-test fails (refer to section
7.5.4.3). The other two codes are the INPUT ERROR code and the
OUTPUT ERROR code.
The INPUT ERROR (B6 hexidecimal) is sent when the keyboard detects
noise (unidentified command or parameter) on the line. B6 is also
sent if the keyboard detects a delay of more than 199 ms when it
expects a parameter.
The output first in the first out (FIFO) buffer in RAM is four
bytes. When the keyboard is locked it attempts to store characters
received from the keyboard. The keyboard stops scanning its
matrix. When the keyboard is unlocked by the system module, it
transmits all four bytes in the output buffer. If any keystrokes
have been missed due to buffer overflOW, the keyboard transmits an
error code as the fifth byte (OUTPUT ERROR). Any keys that were
not transmitted and are being pressed when the keyboard is
unlocked are processed as new keys. An error code upon unlocking
the keyboard indicates a possible loss of keystrokes to the system
module.
The keyboard stops scanning its matrix when its buffer is full.
However, it processes all incoming commands.
7-37
7.5.6.3 Reserved Code -- The number 7F (hexidecimal) is reserved
for the internal keyboard input and output buffers that handle
routines.
7.5.7.1 Audio Volume Both keyclick and bell volumes are two
decimals (010 binary) by default. The key in position C99 of the
keyboard (the CTRL key in the LK201) does not generate a click
unless enabled by the system module. The keys in po~ition B99 and
Bl1 (SHIFT keys on the LK201) never generate a keyclick.
7-38
Table 7-5 Keyboard Division Default Modes
0 500 30
1 300 30
2 500 40
3 300 40
7.6 SPECIFICATIONS
Functional
7-39
Numeric keypad 18 keys
Special function keypad 20 keys, firmware and software driven
Physical
Height 5 em (2.0 in) at highest point
Le th 53.3 em 21 in
Width 17.1 em (6.75 in)
Weight 2 kg (4.5 Ib
7-40
CHAPTER 8
MONITOR CIRCUITS
8.1 GENERAL
The monitor circuits and CRT (shaded areas of Figure 8-1), along
with the yoke assembly, are responsible for actual display to the
VT220 operator. The monitor circuits, located on the PS and
monitor board, develop the drive potentials for both the CRT and
the yoke assembly. The CRT generates an electron beam to provide
actual visual output; the yoke assembly controls the positioning
of the electron beam generated by the CRT.
COMPOSiTE
ViJ~O
ViDEO
I LOGiC
____ ...1 _
SYSTEM
COMMUNICATION
LOGIC LOGIC
BOARD
MONITOR
EIA PRINTER 20mA ASSEMBl Y
HOST PORT PORT
PORT
8-1
8.2 MAJOR CIRCUITS AND COMPONENTS
• Video amp
• Horizontal deflection circuit
• Flyback transformer
• Vertical deflection circuit
• Dynamic focus
• Brightness control
• CRT
• Yoke assembly
• +12 V filter
The yoke assembly is described in conjunction with the horizontal
and vertical deflection circuit descriptions. No description is
provided concerni +12 V filter.
NOTE
Circuit illustrations provided are based
on REV A of CS 5415651-0-1.
CONTRAST BRIGHTNESS
THUM8\VHE EL THUMBWHEEL
ViDEO
AMP
FROM
VIDEO - -.... OEF FLYBACK
TRANS
LOGiC
T O P S _ -_ _........J
DYNAMIC
FOCUS
8- 2
8.2.1 Video Amplifier (Amp) Circuit
With no signal input, 0101 is off, and 0102 has a bias of 7.2 V on
its base from R106 and R107. When a video signal is applied to the
base of 0101, 0101 is turned on, forward biasing 0102. With 0102
on, the potential developed across R109 is dc coupled to the CRT
emitter through RIG8 (R1G8 protects 0102 from transients that can
occur as a result of high voltage arcing at the CRT anode).
J2
PiN
FR. OM
VIDEO 11
~ ViDEO iN 0101
0102
BF457 Rl0S
2N2369A 2201/2 W
lOGiC R101
250B R109
Rl03
B20
75
R102 0102 2W
;~L
150
Cl--::-=-+--------"---'----'--f-L...:;.::..;-'-----' FROM
FLYBACK
TRANSFORMER
(01001
J2
PINS
8-3
8.2.2 Horizontal Deflection Circuit
• Horizontal processor
• Horizontal driver
• Horizontal output
8-4
FLYBACK
TRANSFORMER
PRIMARY
ITl i
HORIZONTAL
WINDINGS
(YOKE ASSYI
R210
lOC1/2W FROM
r---,-----r--r-----r---r~{Y-. .- - - - +12V
R206 FILTER
R203 C205
1.2K .1
5K
, ZDI
3.6V
C206
470
100V
R209
196 16V 820
R204
16.5K
HOP R200 1% 6 8 TO
FROM lr, 1.8K 3 HORIZ
V IDEO 121---,-"""'....,.---+---1 ..4 - + - - - - - - - - ' - - - - - DRIVER
LOGiC J2 E201
MC1391P R215 IR212
P", 2 18K FROM
HORIZ
C207 OUTPUT
R205
.068 'i' 10202
150K
R202 lOCV I COLLECTORj
C200
3OCP500, 18K C208...L
.027 .........
250V
R211
looB
GND
}-_..L-_-L_ _...L.. ..L-_ _.L- ........ GND 8
OUTPUT TO PUlSEWIDTH MODULATOR FROM
E201, PiN 1, IS NOT SHOWN IN SCHEMATICS.
THIS OUTPUT SYNCHRONIZES PUlSEWIDTH
MODULATOR OPERATION TO HORIZONTAL
RETRACE PERIODS
8-5
8.2.2.2 Horizontal Driver Circuit The horizontal driver
circuit converts the square wave input from the horizontal
processor to a bias potential to the horizontal output circuit.
R213 limits the current through Q201, and R214 and C211 limit
voltage across this transistor.
FROM
+12V
FILTER
~2~
~
I
I 4
T201
3
TO
HORIZ
~11~=:2=======:-_· ~L~b:;~T
I, 0201
I MPS ~-...,
FRO~..1 R2l2
, uos
HORIZ 470 i R214
PROCESSOR -N..--!--H 68
(E201 Ii2W
PIN 1;
C211
.1
100V
)---J.._ _. l . . - _ - - l ._ _- l - _ GND 8
Figure 8-6 Horizontal Driver Circuit Diagram
8-6
8.2.2.3 Horizontal Output Circuit The horizontal output
circuit is turned on and off by the horizontal driver circuit to
generate the potential applied to the horizontal windings of the
yoke assembly. The horizontal output circuit potential is also
used to control flyback transformer activity (refer to description
in section 8.2.4).
• Collector
R218)
voltage network (Tl primary, D201, C214, and
TO PART OF FLYBACK
BRiGHTNESS TRANSFOMER
CONTROL (T 11
iR 1 iO
I TO 5207
PUR
r -
I ~207
~
I
f---DYNAMIC
5
I
FOCUS
(Rn1l 5207
YEL
I P207
6 I
~~' 13006
C106l.
!
T ,f I
I
I
FRO M
HO RIZ
ORI YER
L200 02
500Y
I :---
L201
WIDTH
r----
5207
BRN 7 I
P207
(T20
0101
RG 1J
..-toI-
I
R217
100
1/2W 0200
EkJ
~"IA115~~0
1:5201
' j"" I 22
0102,
RG1J ;;:
C212
.1
" LIN
L202
C213
.022
250V
A115M
,..r:
""C215
1000
16v
CWE l00Y ""I' C214 R218
10 ;;:
-,
470
I I 250V 16V
1
3W
GND
a i
I
I - \ r-
I C2l6
R231 2 I
*
10 270
iI
I
25v
C224
6801'
lKV
I I
I
.~
3
L
1
TO TO
FROM
+12V FILTER TO PART
HORIZ PROC DYNAMIC FOCUS DYNAMIC OF OF
(C2071 102031 FOCUS Jl YOKE
(Cn3, ASSY
8-7
Q202 is turned on and off by current flow through the secondary of
T201 in the horizontal driver circuit. During the second half of
retrace, Q202 is turned on to saturation. At other times, Q202 is
backbiased by T20l, quickly turning Q202 off to minimize
dissipation.
The Q202 collector voltage is sourced at +12 V and boosted through
the collector voltage network to +15.5 V.
The charge pump circuit inverts the large positive voltage swings
at the collector of Q202 into -170 V bias used by brightness
control and dynamic focus circuits.
The output components switch yoke current back and forth between
C213 and C216.
N-~"'"
I THROUGH
YOKE
- 0 AMPS
t~m===~~===-1r!=:l_OIlOLTS
l. L IIOLTAGE
iI II ACROSS
rI I
T,j;3 TO
YOKE
T2
. ..-..
Figure 8-8 Horizontal Deflection Waveform
8-8
YOKE
Q20:
+155
'-- ...JT C216
ACTIVITY DESCRIPTION
INITIAL CONDITION
1 0202 OF F,
2 CURRENT THROUGH YOKE AT ZERO.
3 C216 CHARGED TO +155V
ACTION
ACTIViTY DESCRiPTION
iNITIAL CONDITiON
1 0202 SATURATED;
2 CURRENT THROUGH YOKE AT MAXIMUM,
3. C216 CHARGED TO OV
8-9
yOKE
ACTIVITY DESCRiPTiON
iNiTiAL CONDiTiO',
-----~
ACTJO\:
0200
8-10
8.2.3 Flyback Transformer Circuit
HV
ANODE TO TO
TO POTENTIAL CRT CRT
BRiGHT"-iESS TO {CUTOFF (FOCUS
iR 113. Cl0n CRT GRID! GRIDI
•I Dl0C
TO RG1J L204
I !Ill
l
ViDEO AMP •
IR109\ f---
[--Til
5207 PUR P207 5 ...1 T1I
) R224
R219
5207 YEL ) P207 6 P;~7 41 L203 I 1M lOOK
P207
I 2I 5207 RED 10202 R223
Lo
6.8M
TO/FROM
5207 BRN
)
p207 7 " 5207 BLU I N5623 -
HORIZONTAL P207 d R220
IL: 8 1M
OUTPUT
D201
115M
P207
5201 GRN
I
'-' 5207
BLK
C219
;; ,02 --1'02
lKV
R221 lKV
-t-~ 5M
R222
C218
.02
:;:r: lOOK
lKV
G"'D b
·170V FROM
FROM DYNAMiC
HOR ,ZONT AL OUTPUT FOCUS
(CHARGE PUMP) (C222)
8-11
The anode output is rectified internal to Tl, and filtered by
graphite coatings at the CRT end of the anode wire, which can
connect or disconnect only at the CRT end.
The operational voltage (+60 V) used by the video amp and
brightness control circuits is output from pin 2 of Tl and
regulated and filtered by 0100 and L204.
The cutoff grid potential is taken from pin 4 of Tl and regulated
by L203 and D202. The regulated potential (+750 V) is routed to
the CRT cutoff grid via a voltage divider network (R2l9 and R224,
filtered by C219 and C220), and to R220 in the dynamic focus
circuit.
• Vertical processor
• Vertical output
8-12
TO
DYNAMIC
FOCUS
(C3131
VERTICAL
FROM
VIDEO -----I VERTICAL VERTICAL 1--""'-....,........ WINDINGS
OUTPUT OF
LOGIC PROCESSOR r--........
..J YOKE
' - -_ _.--J ASSY
FROM
-12V +12V
FILTER D301 "
IN4004
C303
;:;::100
R305
221K
196
C305
1 R310
33 1/2'11 ,
1---'-------4'1if---,
25V 5 11
4
JOOPFT
SOOV
C310
10100V
J2 R254
c...2. TO/FROM
10 } VERTICAL
PIN F h - - - - - - - - - - + + _ OUTPUT
15 f-~lwK ......,_ _8, E301
V-LIN
TDA 11705 R3()6
562K R308 nR307
rI ~~'-;""1'-6..,.--....,,7R-3~1~4~2:--+----r,
FROM VER IN
47K lOOK
VIDEO
LOGiC
R30i - - - - l)'!f------l
I
4.7K
~ 390K I I ~3~~v
1 C304
~EIGHTl
R303 C306 R309 C308
"r-
T 1
150V
-- 250K "r'2200P
l00V
820K 1
150V
GND I I i
c l---L.........- - - - I . - - I . - . l . . - - - ' - - - - - ' - - - - - - - . . . L . . -....... GN00
MA<013!>8A
8-13
The vertical sync input initiates retrace each time it goes low
(60 times per second). However, the E301 is capable of
free-running trace and retrace, in the event no retrace sync
signal is sensed from the video logic. R302 and C304 define E30l
internal free-running oscillation at 60 Hz (~l Hz).
4.7K
TO
'910 DYNAMIC
TO/FROM { ..
FOCUS
VERTICAL
lC313)
PROCESSOR ----r--+----,----,
R312~
C311
1000
562K PART
1~"O R313 16V
C312 OF
47.5K
1000 Jl
1% 16V
C309
47 R314 R315
10V 1 1 R317
100
1/1W 4
PART
OF
YOKE
ASSY
8-14
Output from the vertical processor circuit is applied to the
voltage divider network. The resulting voltage drop caused by
current flow through R3l4 and R3l5 is reflected back to the
vertical processor circuit at R3l3.
FROtio~ ----,---- .. TO TO
HOP FLYBACK CRT
TRANSFORMER FOCUS
'Q202i D203 iTl, PiN 6: GRiD\
RG!j
FROM
vERTiCAl-
OUTPUT
C313
47
10V
R316
470
---l1---1-"'-"-;
R225
270K
R227
75K Lii' ---r::
600V FROM
HORiZ
OUTPUT
TO
YOKE
ASSY
(C3L? IC2161 C223 (Jl, PIN 21
.047
R230
lK
8-15
D203 and C22l rectify and filter an operational voltage input of
+160 V supplied to the base and collector of Q203 through the bias
resistors.
R i!1 Ri12
47K
lOOK
....
Ii
",I
... 9
r-- - - - - t - - - - - -
..
TO
CRT
r (INTENSITY
i
GRIDI
I 1
I
'
I 0103 Cl04
i IN4004 "'" 22
1. Cl03 l00V
I 1" 01
I l00V I R1l3
...--
~!
RllO Cl07
lOOK 47K" 47
' 100V
ro
VIDEO
I F~
FL YBACK
AMP _--t---I---....l---I----'----- TRANSFORMER
IR 109! 101001
8-16
The voltage divider network, which includes the brightness
thumbwheel (Rlll), provides for a variable bias (from +9.5 V to
-80 V) to the intensity grid of the CRT. The bias is developed
from -170 V input from the charge pump in the horizontal output
circuit (refer to section 8.2.2.3) and +60 V input to the
reference voltage network from the video amp operational voltage
developed by the flyback transformer.
The CRT device (Figure 8-19) provides for actual output to the
operator. Video input to the monitor circuits is converted to
emitter potential to the CRT emitter. FOcus, intensity, and cutoff
potentials applied to the three grids of the CRT inhibit (cut off
input from flyback transformer circuit), refine (focus i t from
the focus circuit of the flyback transformer coupled to the value
developed by the dynamic focus circuit), and contr 1 the
brightness (intensity input from brightness control) of the
display generated by the CRT beam from the emitter potential
provided by the video amp.
r-----,
CRT
FROM
VIDEO
AMP
R 108
EMiTTER
I
FROM
FLYBACK ANODE
I
TRANSFORMER ---------+--+++---++
I
FOCUS GR '0 I II, , I 7 ALL
i
CUTOFF GRiD cI I! :......= I I I RED
I I . I
INTi;NSITY GRiD GRN ~
I 3 I
BRN I
r~ II
'17V~ I
I II I BLK
II I ~
WHT i
I
L --- _ --J
I
I I
FROM F ROfl~~ FROM GND
DYNAMIC FLYBACK BRIGHTNESS f7'\b
FOCUS TRANSFORMER CONTROL V
IA227' (R224) IR111i
8-17
9.2 MAJOR CIRCUITS AND COMPONENTS
• AC input components
• AC conversion circuits
• Interboard connectors (Jl and J2)
• DC input circuits
• DC power ok
NOTE
Circuit illustrations in this chapter
are based on REV A of CS 5415651-9-1.
AC DC
CONVERSION 1-_ _...,/ INPUT
C1RCU!TS COMPONENTS
fDCl
L:.::J
AC
iNPUT
9-2
9.2.1 AC Input Components
J501
AC
INPUTS
AC EMf
TO
INPUt FILTER
PS
CHASSIS
GROUND
LUG
PS AND MONITOR
BOARD
....·OM1 ....
9-3
9.2.2 AC Conversion Circuits
PART
J501 OF
I J2
~ ...
El
I-- -12V
i230VAC, 21 -12V
FROM{ 115VAC
1
'--
INPUT
OUTPUT
I ~ 7
I--
+SV
S2 2 RECT1FJCATJON
I -
~
TO ~ I- 8 +SV
Fl
RETURN
3 I--
! I-
-
r- -
GND ~ +5\/ 18 +5V
FROM CHASSIS
GND
FROM( I,' 5VAC' ~
4
5
...
TS04
U U I
OUTPUT
fJ-
I - 19 +SV TO
LOGIC
I
~i - 20 +12V
52 \...
(230VACi
I I BOARD
i
I
I
- GND
it~
• 9
I
+12V
OUTPUT
+....
I
•
•
----10
16
GND
GND
I i.:~!_ .J
I •
---17 GND
-'
I I
-
,--
START WIDTH
PROTECT
UP MODULATOR
}r
+SV
-12v
... t +12V
C
K
{SYNCI
+5V
:1 TO /FROM
-12V > MCIONITOR
RCUITS
+12V
9-4
• T50l transforms regulated ac input into secondary
voltages used by the dc output circuits to generate the
required dc potentials.
9-5
Table 9-1 Input Voltage Specifications (Cont)
9-6
RETU RN , T502 4
-----.IIIC---..,
TO/FROM 230VAC 2 : TO
J50' I 'J-r-"'"'1 h--t~t--r--PUlSE WIDTH
{ lN4oo4 MODULATOR
'15VAC 3 I, -.;..51---' C502
10 TO
25V OVERCURRENT
PROTECT
R501
T5D,
I
230VAC
R503
I
PART OF
lOOK
lW
C503
220 T504 5
I
I
~~~~E
250V R5D6
TO/FROM RETURN 2
J50' {"
56
2W
I
4 WIDTH
MODULATOR 6 C507
I
1-2.:'1~5::':VA:'::C'-~---'~-1~----~~::;C;52;:2~==+-.J I~~~P I
I
R502 405J ~~~6 I
, OOK C504 PART OF I
--r~5S
1W
I
T504 \
' 0505
I
I
:~!~~ {1171N~~ 0502
2SC
R500
I
MODULATOR .8
2335 I
I
¢
• Rectifier (E503)
• Filter networks (R503 and C503, R502 and C504, and R506,
C507, and C530)
9-7
Q501 and 0502 are coupled to the pulse width modulator in reverse
polarity via T504. Current is induced in T504 by the pulse width
modulator, with the effect on the switching transistors determined
by the direction of the current flow. When current in T504 is
induced from pin 6 to pin 5 and pin 7 to pin 8, back biasing of
0502 occurs, turning this transistor off, which results in 0501
being turned on (with charge of C505 speeding up the transition).
When current is the reverse, 0501 is back biased and turned off,
with 0502 turned on (with charge of C506 speeding up the
transition). The result is an ac signal to the T50l primary
controlled by the width of pulses output from E505, the pulse
width modulator.
T50, D507
RG1J
I L501
-1;2V
I 3
2
I C508
1. 0509 R525 R526
,II ~ ,
330
D508
RG1J
I T 50V T47
1K 1K
I
14
I. i r-j
I 9
0509
1FE16D
I
I 8
I
I
I L_J 1
+5V
I ,-.., 0523
470
16V
+12V
I 12 R5D8
68
I
11 1/2W 10510 0511 0510
I FE160 1000 1000 0512 0518 0513
C520 I 25V 10V 47 1 47
I
I 10 WOOP I
l00V
I R507
I L_J05
25W
~ TO
OVERCURRENT
PROTECT
... ot.·06'Y,· ...
9-8
• +12 V output circuit containing a rectifier (0510), and
filter networks (R508 and C520, and T503, C511, C512, and
C518).
NOTES:
1. Ripple and noise must be measured with wide band oscilloscope
such as Tektronix P6046 differential probe, with scope set for
>100 MHz bandwidth, and specification applies only to
repetitive voltage variations occuring while operating with
constant input voltage and fixed load.
9-10
9.2.2.4 Overcurrent Protect Circuit The overcurrent protect
circuit monitors the +S V dc output to sense an undervoltage
condition, and the dc output circuits sensing resistor (R507)
potential to sense overcurrent condition resulting from a short in
either the +5 V or +12 V output circuits.
FROM
+12V
START UP
+51 V
FRO~~!\
R524
PULSE WiDTH 16K 1%
MODULATOR - _ _-....,
R523
4871% R5D9 TO
FROM
r-7_3"""3....
0 _ . . PULSE WIDTH
CURRENT
MODULATOR
SENSING R514
RESISTOR 15K
IR507,
1% I
5V
9-11
9.2.2.5 Pulse Width Modulator Circuit The pulse width
modulator monitors the +12 V output potential, along with inputs
from the +5 V output, overcurrent protect, and horizontal
processor in the monitor circuits, to control the width and
frequency of pulses passed through the primary of T501 by biasing
of the switching transistors in the input rectification circuit
(via T504).
• Oscillator
C514-C516 )
frequency control components (RSll, R527,
TO FROM
l OVERCURRENT +SV DC
r FROM +12V PROTECT OUTPUT FROM +12V
OS11 OUTPUT CIRCUIT OUTPUT
1N4004
rfFROM+12V
rI RS17
S 11 I(
R519
6 491(
STARTUP 1% 1%
PART 0 F CS21
TO T50\
.47 9' I 10 1 R518
511 I(
R520
5.11 I( FROM
15 ,.!l! ,,1 %
INPUT r-;- R510
68
I
,
13 ~ 3
1%
HORIZ
RECTIFICATION { II 1
1/2 11
E50S
4
~
054
--PROCESSOR
IN
14 BBOP MONITOR
SG3525A 1- CIRCUITS
DS12 6 L 054
0664 .4~ ~ .0513 R51S R515 .4~ 1N4004
0664 7
~ r- 33K 4701(
r-- R527
~'7 5008
R511
J C517
;;:
lL.
C515*
1000P
~
;F'
C514
:::
C516 -
RS4
22K
4.751< .0047 01
1%
47 ~'7
100V
" FROM
OVERCURRENT
PROTECT
9-12
The pulse width modulator circuit generates two outputs: Biasing
to the switching transistors in the input rectification circuit
(via T504) and +5.1 V reference voltage to the overcurrent protect
circuit.
9.2.3 DC OK Circuit
The dc ok circuit provides visual indication of the presence of dc
in the monitor module. The dc ok circuit (Figure 9-10) consists of
the following components.
+5V +12V
R400
12K
-12V
9-13
+5 V, +12 V, and -12 V potentials are applied as inputs to the dc
ok circuit. When all three inputs are present to turn on 0499,
0400, which is mounted on the front panel of the VT220, and
connected to 0400's collector via J7, it will light.
PART OF
/ " J1
+5V
+5V
+5V
C471 I '"'41
1 C1,C3C4,C11
.+5V
..L ~ Cl4-C39,C48-C54
FROM +5V 2200}J.F "T' ,22}J.F ,01,uF
PS AND
MONITOR
+12V t---,..--f--f---+----- +12V
BOARD GND
GND
GND C45
GND 10/LF
9-14
APPENDIX A
SPECIFICATIONS
GENERAL
This appendix lists the specifications of the VT220 terminal.
VT220 SPECIFICATIONS
Physical
Terminal
Height: 28.3 em (11 1/8 in)
Width: 33.3 em (13 1/8 in)
Depth: 38.7 em (15 1/4 in)
Weight: 11.8 kg (26 1bs)
Adjustable
Tilt: +5 to -15 degrees
Environmental
A-I
Electrical
Display
A-2
Keyboard
Audible signals
Keyclick: Audible feedback for each keystr
Bell: Sounds when BEL character received,
when 8 characters from right margin
and for compose errors
14,-3
APPENDIX B
VT102/220 DIFFERENCES
B-1
Difference Area VT102 VT220
Terminal 10 Responds to Responds to primary
primary device device attribute with:
attributes with:
ESC [ ? 6 c CSI ? 62;1;2;6;7;8;9 c
NOTE
If the terminal is in VT100 mode and an
10 other than VT220 10 is selected, then
the following primary exchanges apply.
B-2
APPENDIX C
REGISTER BIT VALUES
o~ 06 05 04 03 02 01 00
! I
Rx
RTS
I
II RxiDT
SEl
ERROR
MODE
I PAR ITY MODE
PARiTY
TYPE
BiTS PER
CHARACTER
I I
IBAD7 Hi" .. (BADO Hi
BIT VALUES
"'.-06'&-'"
C-l
MR2A ADDRESS B7FOH (RD)/B7FOH (WR)
MR2B ADDRESS B7F8H (RD)/B7F8H (WR)
07 06 05 04 03 02 01 00
I I
CTS
CHANNEL T.
ENABLE STOP BIT LENGTH
MODE RTS
T.
I I I
4_-----------------_
{BADl HI .. .... (BAOO H)
BIT VALUES
C-2
SRA ADDRESS B7F1 H (RD)
SRB ADDRESS B7F9H IRD)
07 06 05 04 03 02 01 00
t--------------------.. . .
IBAD7 HI..... (BADO Hi
BIT VALUES
C-3
DCSRA ADDRESS B7F1 H (WAj
DCSRB ADDRESS B7F9H /WA)
07 06 05 D3 D2 Dl 00
I I I
I I I
BIT C>-3
OR 4-7 BAUD RATE SET 1 BAUD RATE SET 2
0000 50 75
0001 110 110
0010 1345 1345
0011 200 150
0100 300 300
0101 600 600
0110 1200 1200
DIll 1050 2000
1000 2400 2400
1001 4800 4BOO
1010 7200 1800
1011 9600 9600
1101 3841< 192K
1110 IP4-1 6XI R.CAI IP4-16XiA.CAJ
; 110 1PS-16XIR.CB, IP6-16XIAxCBj
1110 IP3-16 XfTxCA) IP3-16X(TxCA)
1110 IP5-l6X(' .CBj IP5-16XiT.CB)
1111 IP4-1 XIRxCAj IP4-1 XIAxCAJ
111 ! IP6-1 XiRxCB) IPS-I XiAxC81
11i1 IP3-1 XITxCAj IP3-1 XITxCAI
1111 IP5-1 X(T.CBj IP5-1 XiT.CBj
NOTES-
1 AxC AND TxC AAE ALWAYS 16X EXCEPT FOA 1111 CONDITION
2 SET SELECTION MADE BY ACA 81T 7
C-4
CRA ADDRESS B7F2H(WR)
CRB ADDRESS B7FAH(WR)
07 06 05 04 03 02 01 00
I I
NOT DISABLE ENABLE DISABLE ENABLE
MISC COMMANDS
USED T. T. R. R.
IJ
I-------------------•• (BADO HI
(BAD7 HI ....
BIT VALUES
BIT 7 ALWAYS 0
BIT 4-6 000 NOT USED
001 RESET MODE REGISTER (MRI POINTER
010 RESET R.
011 RESET Tx
100 RESET ERROR STATUS
101 RESET CHANNEL BREAK CHANGE INTERRUPT
110 START BREAK
111 STOP BREAK
BIT 3 0 NO COMMAND
1 TERMINATE Tx AND RESET TxRDY AND TxEMT
STATUS BITS
BIT 2 0 DISABLE Tx
1 ENABLE Tx
BtT 1 0 NO COMMAND
1 TERMINATE R. IMMEDIATELY
BIT 0 0 DISABLE Rx
1 ENABLE Rx
BIT VALUES
C-5
ICR ADDRESS £l7F4H(RD)
07 06 05 03 02 01 00
...-------------------l~~(BADO
IBAD7 H)" HI
BIT VALUES
I BiT 6
BIT 5
0
1
0
NO CHANGE OF STATE DETECTED AT IP2
CHANGE OF STATE DETECTED AT IP2
NO CHANGE OF STATE DETECTED AT IP1
I BiT 4
1
0
CHANGE OF STATE DETECTED AT IPI
NO CHANGE OF STATE DETECTED AT iPO
I
I BIT 3 Oil
CHANGE OF STATE DETECTED AT IPO
CURRENT STATE OF IP3 ITVS)
BIT 2 011 CURRENT STATE OF IP2 (SPO INDI
BiT i 0/1 CURRENT STATE OF IPI IDSR)
BiT 0 on CURRENT STATE OF IPO leTSi
C-6
ACR ADDRESS B7F4H(WR)
06 05 04 03 02 01 00
BIT VALUES
C-7
ISR ADDRESS B7F5H JRDI
07 06 05 04 03 02 01 00
INPUT DELTA I RxRDYI DELTA II I
II
<
CNTR RxRDYI TxRDYA
PORT BREAK FFULLB TxRDYB BREAK
CHANGE B i
READY
A i FFULLA
..1-------------------~,BADD Hl
IBADl Hl4l ..
BIT VALUES
BIT 1 0 NO INTERRUPT
1 INPUT PORT CHANGE OF STATE DETECTED
BIT 6 0 NO INTERRUPT
1 CHANGE IN BREAK STATE DETECTED ,Cf4 B)
BIT 5 0 NO INTERRUPT
1 R,RDY/HULL CONDITION (CH BI
8fT 4 0 NO INTERRUPT
TxRDY CONDITION ,CH III
BIT 3 0 NO INTERRUPT
COUNTER READY CONDITION
BIT 2 0 NO INTERRUPT
CHANGE IN BREAK STATE DETECTED ,CH A)
I
BIT 1 0 NO INTERRUPT
I BIT 0
1
0
RxRDY/FFULL CONDITION (CH Ai
NO INTERRUPT
II INPUT I DELTA
P~RT I BRC' K
I c~
I I
R,RDY; I CNTR
i
II DELTA
BREAK R,RDYI II ,.RDYB T.RDYA
I v
<
CHANGE
< < <
8 I! HULLS I
READY
A
FFULLA
I BIT VALUES
C-8
CTUR ADDRESS 87F6H (RD)/87F6H (WRI
CTLR ADDRESS 87F7H (RDi/87F7H (WR)
07 06 05 04 03 02 01 00
I
IP6 IPS IP3 IP2 IPl IPC
USED j
I I
IBAD7 HI ..... I-------------------.... IBADO HI
BIT VALUES
C-9
OPCR ADDRESS B7FDH {Wi'll
07 06 05 04 03 02 01 00
OP7
(BAD] HI"
I OPS OP5
~
R
(BADO HI
BIT VALUES
(BAD] HjOl
.. t__------------------4-.. iBADO Hi
BIT VALUES
NOTE
VALUE STORED IN CHARACTERS PER DATA
ROW REGISTER SUBTRACTED FAOM ABOVE
VALUE DEFINES CHARACTER TIMES IN
RETRACE PERiOD
............
Figure C-14 91307 VPAC: Characters Per
Horizontal Per iod Reg i ster
C-10
ADDRESS 17C1 H (WR)
07 06 05 04 03 02 01 00
NOTE
THIS REGISTER VALUE SUBTRACTED FROM
CHARACTERS PER HORIZONTAL RETRACE
REGISTER VALUE DEFINES CHARACTER TIMES
IN HORIZONTAL RETRACE PERIOD
C-ll
ADDRESS 17C3H (WRj
oi 06 05 04 03 02 01 00
,BAD7 HI ..
4 1 - - - - - - - - - - - - - - - - - - -.... IBAOO H)
BIT VALUES
IBAD7 HI..
4 1 - - - - - - - - - - - - - - - - - - -.... (BADO HI
BiT VALUES
41------------------_..... ,BADO HI
IBAD7 HI ..
BiT VALUES
C-12
ADDRESS 17C6H(WRI
07 06 05 04 03 02 01 00
I I I I
PIN
CONFIGURATION CURSOR SKEW BLANK SCEW
I I J I
(BA07 HI .... I-------.. . . .- ------------t.... (BADO HI
BIT VALUES
BIT VALUES
C-13
ADDRESS 17C8H (WRI
07 06 05 04 03 02 01 00
BIT VALUES
NOTE
BITS 5 THROUGH 7 ARE USED AS 3 MSB. OF
SCAN LINES PER VERTICAL PERIOD REGISTER
AND ARE WRITTEN TO AT SAME TIME AND
ADDRESS AS BiTS 0-4 ABOVE.
Mll-OlSll·"
06 05 04 03 02 01 00
:• o"~.",,,, :
:
15 14 13 12 11 10 09 08
IBAD7 Hi"
9 8
':'0,"":' .. IBADO HI
BIT VALUES
NOTES·
1 VERTiCAL BLANKING PERiOD IS DEFINED BY
SUBTRACTING THE TOTAL NUMBER OF SCAN
LINES PER VERTICAL TRACE IVALUE OF DATA
ROWS PER FRAME REGISTER X VALUE OF
SCAN LINES PER DATA ROW) FROM ABOVE
VALUE
C-14
ADDRESS 17CBH (WR)
07 06 05 04 03 02 01 00
I I
SCROLL
NOT INTERLACE OPERATING CURS
OR
USED MODE MODE HEIGHT
BLANK
I
IBAD7 H!...-et--------------------..... IBADO HI
BIT VALUES
15 14 13 12 11 10 09 08
,,,;,,,
M~DE
t----------------------..... IBADD HI
IBAD? Hi .....
BIT VALUES
C-15
ADDRESS 17CFH (WA)
07 06 05 04 03 02 01 00
,,,.:,,"
SI~E
BIT VALUES
l "":,w. : :
'BAD7 Hi'" .. IBADO HI
BIT VALUES
NOTE
TYPE OF OPERATION IS DEFINED BY BIT 6
OF CONTROL REGISTER.
C-16
ADDRESS 17D2H (WRi
07 06 05 04 03 02 01 00
IBAD7 HI4
IDA" :OW' : : .. IBADD HI
BIT VALUES
NOTE
TYPE OF OPERATiON is DEFINED BY BIT 6
OF CONTROL REGISTER
BIT VALUES
C-17
ADDRESS 17D8H (WR. VERTICAL)
ADDRESS 17D9H (WR, HORiZONTAL)
ADDRESS 17F8H (RD, VERTICAL)
ADDRESS 17F9H (RD, HORIZONTAL)
07 06 05 04 03 02 01 00
BIT VALUES
BIT VALUES
C-l8