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Solar Battery Charger Design The switching signal of the DC/DC boost converter
is generated from an inverter-based ring oscillator
DC/DC Boost Converter followed by an inverter-chain buffer. Note that the
DC/DC boost converter is supplied by the solar cell,
Figure 2 shows the schematic of the DC/DC boost providing a voltage as low as 0.65V. The loading of M2
converter in the proposed system. A diode-connected can be too large for the clock generator, thus a buffer is
mosfet M1 is connected to inductor LD , RL, CL and switch needed between the clock generator and the boosting
M2 [4]. Switch M2 is controlled to a clock. When M2 stage.
shorts, the current passes from the solar cell to the
ground through M2. At this time, energy is stored in the Battery Charger
inductor as current. When M2 suddenly opens, the
Li-ion battery offer high electricity capacity but this
conducting current in LD cannot respond in time, so the
advantage is based on the assumption that the charging
current is forced to flow into the diode-connected mosfet
procedure is precisely controlled. An ideal Li-ion battery
M1. As a result, the charge is stored in Cload. In steady
charging procedure is shown in Figure 4. The process
state, the output voltage of this converter is constant as
entails three charging modes: trickle charging mode (TC),
shown in Figure 3. By adjusting the clock frequency and
constant current mode (CC), and constant voltage mode
capacitance value CL , one can control the final voltage of
(CV).
this stage.
(b)
(c) (d)
Figure 6. Circuit blocks schematics in the solar battery charger: (a)
amplifier (b) current driver (c) low voltage detector (d) voltage
Figure 5. Block diagram of battery charger. reference.
In the early charging procedure, when VBAT is low in
the trickle charging mode, the low V BAT detector senses
this low VBAT value and outputs a high ENTC voltage as
shown in Figure 6(c). Receiving the high ENTC signal, the
current driver is switched to the trickle charging mode
(Figure 6(b)). VBAT increases gradually. Once VBAT meets a
specific voltage determined by the transistor size ratio in
the low VBAT detector), ENTC voltage is shifted to a low
voltage, which changes the charging current to a higher
value for CC mode.
Note that this analog circuit makes use of the
saturation and linear regions of an amplifier as shown in
Figure 7. In the beginning of the CC mode, the amplifier
operates in the saturation region, in which the output Figure7. Mapping the modes of the amplifier to charging modes.
current of this amplifier is constant, leading to a constant To maximize power efficiency, it is better to bias
charging current as needed by CC mode. As VBAT the transistors in sub-threshold region. The
approaches Vref , the amplifier enters the linear region transconductance over bias current (gm/ID) versus VGS is
and its gain rises, forming a negative feedback loop that shown in Figure 8. It is obvious that one can have a
locks VBAT with Vref. Through this step the charger moves higher gm in sub-threshold region with power constraints.
from CC mode to CV mode. In the battery charger design, the battery is simply
www.ausmt.org 101 auSMT Vol. 4 No. 2 (2014)
Copyright © 2014 International Journal of Automation and Smart Technology
ORIGINAL ARTICLE Solar Battery Charger in CMOS 0.25 um Technology
modeled by a capacitor. The simulated time response is the output voltage can be easily boosted to a high
shown in Figure 9. Three modes are found to exist in this voltage. However, the charge stored in CB will be
transient response. However, different curves of the CC insufficient to sustain the battery charger, because the
mode between Figures 4 and 9 can be observed because charge stored in CB is quickly drained. As illustrated in
the battery model is simplified by a small capacitor for Figure 11, the battery charger is periodically turned
faster simulation results, whereas an enormous capacitor on/off because of a lack of charge. To solve this problem,
would be needed to accurately model the battery, but we use a super-capacitor to store enough charge before
this would result in unacceptably long simulation times. turning the charger on. Figure 12 shows the time
response when a 40 mF super capacitor is used. With a
large capacitor, the battery charger keeps charging
without interruption. The drawback is that it requires
more time to first charge the super-capacitor.
Figure 11. Time response of solar battery charger with CB of 0.4 pF.
Conclusion
A solar battery charger consisting of a DC/DC boost
converter and an analog battery charger is proposed for
an SOC powered by a rechargeable battery. The
proposed system is able to charge a 1.8V Li-ion battery
from a 0.65V solar cell. This system requires a super
capacitor, and future work will focus on refining the
integration.
Acknowledgment
This work was supported by the National Science
Figure 14. Layout of the DC/DC boost converter and battery charger Council of Taiwan (NSC 102-2221-E-182-025). The
integration. authors are grateful to TSMC and CIC for chip fabrication
and tapeout support, respectively.
References
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Mingoo, C. Mao-Ter, F. ZhiYoong, D. Sylvester, and
Figure 15. DC/DC boost converter test bench.
D. Blaauw, "Millimeter-scale nearly perpetual
sensor system with stacked battery and solar
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Figure 16. Output voltage versus clock frequency of DC/DC converter.
"A DC/DC boosting technique and power
management for ultralow-voltage energy
Measurement results of the DC/DC boost harvesting applications," IEEE Transactions on
converter in 0.25um technology is done by loading the Industrial Electronics, vol. 59, no. 6, pp. 2701-2708,
output with a resistor with 1MΩ as shown in Figure 15 . 2012.
The relationship between the output voltage and clock doi: 10.1109/TIE.2011.2167890
[5] B. Do Valle, C. T. Wentz, and R. Sarpeshkar, "An
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ultra-compact and efficient Li-ion battery charger
the input DC is 0.65V. A clock frequency needed to obtain
circuit for biomedical applications," in IEEE
the maximum output DC voltage can be observed. When International Symposium on Circuits and Systems
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be reduced, leading to a lower averaged dc voltage doi: 10.1109/ISCAS.2010.5537287
output. On the other hand, if the clock frequency is too
high, the MOS switch cannot catch up to the clock speed,
thus reducing dc voltage output.