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1FEATURES DESCRIPTION
• Ultra Low Power: The THS4531 is a low-power, fully-differential op amp
with input common-mode range below the negative
– Voltage: 2.5 V to 5.5 V rail and rail-to-rail output. The device is designed for
– Current: 250 µA low-power data acquisition systems and high density
– Power-Down Mode: 0.5 µA (typ) applications where power consumption and
dissipation is critical.
• Fully-Differential Architecture
• Bandwidth: 36 MHz The device features accurate output common-mode
control that allows for dc coupling when driving
• Slew Rate: 200 V/µs analog-to-digital converters (ADCs). This control,
• THD: –120 dBc at 1 kHz (1 VRMS, RL= 2 kΩ) coupled with the input common-mode range below
• Input Voltage Noise: 10 nV/√Hz (f = 1 kHz) the negative rail and rail-to-rail output, allows for easy
interface from single-ended ground-referenced signal
• High DC Accuracy:
sources to successive-approximation registers
– VOS Drift: ±4 µV/˚C (–40°C to +125°C) (SARs), and delta-sigma (ΔΣ) ADCs using only
– AOL: 114 dB single-supply 2.5-V to 5-V power. The THS4531 is
• Rail-to-Rail Output (RRO) also a valuable tool for general-purpose, low-power
differential signal conditioning applications.
• Negative Rail Input (NRI)
The THS4531 is characterized for operation over the
• Output Common-Mode Control
extended industrial temperature range from –40°C to
+125°C. The following package options are available:
APPLICATIONS • 8-pin SOIC (MSOP) and VSSOP (D and DGK)
• Low-Power SAR, ΔΣ ADC Driver • 10-pin WQFN (RUN)
• Low Power, High Performance: 0
– Differential to Differential Amplifier −10 VS = 5 V
−20 G = 1 V/V
– Single-Ended to Differential Amplifier −30 VOUT = 1 VRMS
−40 RF = 2 kΩ
• Low-Power, Wide-Bandwidth Differential Driver
Magnitude (dBV)
RL = 600 Ω
−50
• Low-Power, Wide-Bandwidth Differential −60
Signal Conditioning −70
−80
• High Channel Count and Power Dense −90
Systems −100
−110
−120
−130
−140
0 5k 10k 15k 20k 24k
Frequency (Hz) G071
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2011–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
THS4531
SLOS358B – SEPTEMBER 2011 – REVISED MARCH 2012 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
THERMAL INFORMATION
THS4531 THS4531 THS4531
VSSOP
SOIC WQFN
THERMAL METRIC (1) (MSOP) UNITS
(P) (RUN)
(DGK)
8 PINS 8 PINS 10 PINS
θJA Junction-to-ambient thermal resistance 133 198 163
θJCtop Junction-to-case (top) thermal resistance 78 84 66
θJB Junction-to-board thermal resistance 73 120 113
°C/W
ψJT Junction-to-top characterization parameter 26 19 17
ψJB Junction-to-board characterization parameter 73 118 113
θJCbot Junction-to-case (bottom) thermal resistance N/A N/A N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at +25°C; over temperature limits by characterization and
simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
(2) Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range.
ELECTRICAL CHARACTERISTICS: VS = 5 V
Test conditions at TA = +25°C, VS+ = 5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP, RF = 2 kΩ, RL = 2 kΩ differential, G = 1 V/V,
single-ended input, differential output, and input and output referenced to mid-supply, unless otherwise noted.
TEST
PARAMETER CONDITIONS MIN TYP MAX UNITS
LEVEL (1)
AC PERFORMANCE
VOUT = 100 mVPP, G = 1 36
VOUT = 100 mVPP, G = 2 17
Small-signal bandwidth MHz
VOUT = 100 mVPP, G = 5 6
VOUT = 100 mVPP, G = 10 2.7
Gain-bandwidth product VOUT = 100 mVPP, G = 10 27 MHz
Large-signal bandwidth VOUT = 2 VPP, G = 1 36 MHz
Bandwidth for 0.1-dB flatness VOUT = 2 VPP, G = 1 15 MHz
Slew rate, rise/fall, 25% to 75% 220/390 V/µs
Rise/fall time, 10% to 90% 4.6/5.6 ns
Settling time to 1%, rise/fall 25/20 ns
VOUT = 2 VStep
Settling time to 0.1%, rise/fall 60/60 ns
Settling time to 0.01%, rise/fall 150/110 ns
Overshoot/undershoot, rise/fall 1/1 %
f = 1 kHz, VOUT = 1 VRMS –122
C
2nd-order harmonic distortion f = 10 kHz –128 dBc
f = 1 MHz –60
f = 1 kHz, VOUT = 1 VRMS –130
3rd-order harmonic distortion f = 10 kHz –137 dBc
f = 1 MHz –71
2nd-order intermodulation distortion f = 1 MHz, 200-kHz tone spacing, –85
dBc
3rd-order intermodulation distortion VOUT envelope = 2 VPP –83
Input voltage noise f = 1 kHz 10 nV/√Hz
Voltage noise 1/f corner frequency 45 Hz
Input current noise f = 100 kHz 0.25 pA/√Hz
Current noise 1/f corner frequency 6.5 kHz
Overdrive recovery time Overdrive = 0.5 V 65 ns
Output balance error VOUT = 100 mV, f = 1 MHz –67 dB
Closed-loop output impedance f = 1 MHz (differential) 2.5 Ω
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at +25°C; over temperature limits by characterization and
simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
(2) Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range.
DEVICE INFORMATION
PIN CONFIGURATIONS
THS4531 THS4531
SOIC-8 (D), VSSOP-8 (DGK) PACKAGE (TOP VIEW) WQFN-10 (RUN) PACKAGE (TOP VIEW)
VS+
VIN- 1 8 VIN+
10
VOCM 2 7 PD VOUT- 1 9 VOUT+
VS+ 3 6 VS- NC 2 8 NC
VS-
PIN FUNCTIONS
NUMBER NAME DESCRIPTION
THS4531 D, DGK PACKAGE
1 VIN– Inverted (negative) output feedback
2 VOCM Common-mode voltage input
3 VS+ Amplifier positive power-supply input
4 VOUT+ Noninverted amplifier output
5 VOUT– Inverted amplifier output
6 VS– Amplifier negative power-supply input. Note VS– tied together on multichannel devices.
7 PD Power-down, PD = logic low = low power mode, PD = logic high = normal operation (PIN MUST BE DRIVEN)
8 VIN+ Noninverted amplifier input
THS4531 RUN PACKAGE
1 VOUT– Inverted amplifier output
2, 8 NC No internal connection
3 PD Power-down, PD = logic low = low power mode, PD = logic high = normal operation (PIN MUST BE DRIVEN)
4 VIN+ Noninverted amplifier input
5 VS– Amplifier negative power-supply input. Note VS– tied together on multichannel devices.
6 VIN– Inverting amplifier input
7 VOCM Common-mode voltage input
9 VOUT+ Noninverted amplifier output
10 VS+ Amplifier positive power-supply input
TABLE OF GRAPHS
Description VS = 2.7 V VS = 5 V
Small-signal frequency response Figure 2 Figure 35
Large-signal frequency response Figure 3 Figure 36
Large- and small- signal pulse response Figure 4 Figure 37
Single-ended slew rate vs VOUT step Figure 5 Figure 38
Differential slew rate vs VOUT step Figure 6 Figure 39
Overdrive recovery Figure 7 Figure 40
10-kHz FFT on audio analyzer Figure 8 Figure 41
Harmonic distortion vs Frequency Figure 9 Figure 42
Harmonic distortion vs Output voltage at 1 MHz Figure 10 Figure 43
Harmonic distortion vs Gain at 1 MHz Figure 11 Figure 44
Harmonic distortion vs Load at 1 MHz Figure 12 Figure 45
Harmonic distortion vs VOCM at 1 MHz Figure 13 Figure 46
Two-tone, 2nd and 3rd order intermodulation distortion vs Frequency Figure 14 Figure 47
Single-ended output voltage swing vs Load resistance Figure 15 Figure 48
Single-ended output saturation voltage vs Load current Figure 16 Figure 49
Main amplifier differential output impedance vs Frequency Figure 17 Figure 50
Frequncy response vs CLOAD Figure 18 Figure 51
RO vs CLOAD Figure 19 Figure 52
Rejection ratio vs Frequency Figure 20 Figure 53
Turn-on time Figure 21 Figure 54
Turn-off time Figure 22 Figure 55
Input-referred voltage noise and current noise spectral density Figure 23 Figure 56
Main amplifier differential open-loop gain and phase vs Frequency Figure 24 Figure 57
Output balance error vs Frequency Figure 25 Figure 58
VOCM small signal frequency response Figure 26 Figure 59
VOCM large and small signal pulse response Figure 27 Figure 60
VOCM input impedance vs frequency Figure 28 Figure 61
Count vs input offset current Figure 29 Figure 62
Count vs input offset current temperature drift Figure 30 Figure 63
Input offset current vs temperature Figure 31 Figure 64
Count vs input offset voltage Figure 32 Figure 65
Count vs input offset voltage temperature drift Figure 33 Figure 66
Input offset voltage vs temperature Figure 34 Figure 67
3 3
0 0
−3 −3
−6 VS = 2.7 V −6 VS = 2.7 V
−9 G = 1 V/V −9 G = 1 V/V
−12 RF = 2 kΩ −12 RF = 2 kΩ
−15 RL = 2 kΩ −15 RL = 2 kΩ
−18 VOUT = 100 mVpp −18 VOUT = 2 Vpp
−21 −21
100k 1M 10M 100M 100k 1M 10M 100M
Frequency (Hz) G001
Frequency (Hz) G002
Figure 2. Figure 3.
1
RF = 2 kΩ RF = 2 kΩ
RL = 2 kΩ 300 RL = 200 Ω
Slew Rate (V/µs)
0.5
250
0 200
150
−0.5
100
−1
50 Rising
Falling
−1.5 0
0 20 40 60 80 100 0 0.5 1 1.5 2 2.5
Time (ns) G003 Differential VOUT (V) G004
Figure 4. Figure 5.
200 RF = 2 kΩ
1 2
RL = 200 Ω
Slew Rate (V/µs)
0.5 1
150
0 0
100 −0.5 −1
−1 VS = 2.7 V −2
G = 2 V/V
50 −1.5 RF = 2 kΩ −3
Rising RL = 2 kΩ
Falling −2 −4
0 0 100 200 300 400 500 600 700 800 900 1000
0 1 2 3 4 5 6 Time (ns) G005
Differential VOUT (V) G053
Figure 6. Figure 7.
Figure 8. Figure 9.
RF = 2 kΩ VOUT MIN
Single-Ended VOUT (V)
−30 RL = 2 kΩ 2
VOUT = 2 Vpp Envelope
−40
1.5
−50 VS = 2.7 V
G = 2 V/V
−60 1 RF = 2 kΩ
−70
0.5
−80 Second Intermodulation
Third Intermodulation
−90 0
1 10 50 100 1k 10k
Frequency (MHz) G012 Load Resistance (Ω) G013
0.8 RF = 2 kΩ
10 VOUT = 100 mVpp
0.6
VS = 2.7 V
1
G = 2 V/V
0.4 RF = 2 kΩ
0.1
0.2
0 0.01
0.1 1 10 30 10k 100k 1M 10M 40M
Differential Load Current (mA) G014
Frequency (Hz) G015
FREQUENCY RESPONSE RO
vs vs
CLOAD CLOAD
3 200
0 100
−3 VS = 2.7 V, G = 1 V/V
RF = 2 kΩ, RL = 2 kΩ
−6 VOUT = 100 mVpp
Gain (dB)
RO (Ω)
−9
10
CL = 0 pF, RO = 0 Ω
−12
CL = 15 pF, RO = 200 Ω
−15 CL = 39 pF, RO = 100 Ω VS = 2.7 V
CL = 120 pF, RO = 50 Ω G = 1 V/V
−18 CL = 470 pF, RO = 20 Ω RF = 2 kΩ
CL = 1200 pF, RO = 12 Ω RL = 2 kΩ
−21 1
100k 1M 10M 100M 1 10 100 1k 2k
Frequency (Hz) G016 CLOAD (pF) G017
−80
Power Down
−90 CMRR VOUT
PSRR 0 0
−100 0 200 400 600 800 1000
100k 1M 10M 30M Time (ns) G019
Frequency (Hz) G018
2 1 10 10
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 200 Ω
1 0.5 1 1
0 0 0.1 0.1
0 10 20 30 40 50 10 100 1k 10k 100k 1M
Time (ns) G020
Frequency (Hz) G021
Phase G = 1 V/V
VOCM SMALL-SIGNAL FREQUENCY RESPONSE VOCM LARGE- and SMALL SIGNAL PULSE RESPONSE
3 2
Output Common-Mode Voltage (V)
0 1.8
−3 1.6
Gain (dB)
−6 1.4
−9 1.2
−12 VS = 2.7 V 1
G = 1 V/V
−15 RF = 2 kΩ 0.8 0.2-V Step
VOUT = 100 mVpp 1-V Step
−18 0.6
100k 1M 10M 50M 0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz) G024
Time (ns) G025
TA = 25°C
400
10k
Count
300
1k 200
100
100 0
100k 1M 10M 50M
−50
−45
−40
−35
−30
−25
−20
−15
−10
−5
0
5
10
15
20
25
30
35
40
45
50
Frequency (Hz) G026
Input Offset Current (nA)
G055
10 20
10
8
Count
0
6 −10
4 −20
−30
2
−40
0 −50
−50 −25 0 25 50 75 100 125
−200
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
20
40
60
80
100
120
140
160
180
200
6
Count
Count
100
4
50
2
0 0
−1000
−900
−800
−700
−600
−500
−400
−300
−200
−100
0
100
200
300
400
500
600
700
800
900
1000
1100
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
1
2
3
4
5
6
7
8
9
10
Input Offset Voltage Temperature Drift (µV/°C)
Input Offset Voltage (µV)
G058 G059
400
200
0
−200
−400
−600
−800
−1000
−50 −25 0 25 50 75 100 125
Temperature (°C) G060
Figure 34.
TYPICAL CHARACTERISTICS: VS = 5V
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0V, VOCM = open, VOUT = 2Vpp, RF = 2kΩ, RL = 2kΩ Differential, G =
1V/V, Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply, TA = 25°Cunless otherwise noted.
Gain (dB)
3 3
0 0
−3 −3
−6 VS = 5 V −6 VS = 5 V
−9 G = 1 V/V −9 G = 1 V/V
−12 RF = 2 kΩ −12 RF = 2 kΩ
−15 RL = 2 kΩ −15 RL = 2 kΩ
−18 VOUT = 100 mVpp −18 VOUT = 2 Vpp
−21 −21
100k 1M 10M 100M 100k 1M 10M 100M
Frequency (Hz) G027
Frequency (Hz) G028
1 500
RF = 2 kΩ RF = 2 kΩ
RL = 2 kΩ RL = 200 Ω
Slew Rate (V/µs)
0.5 400
0 300
−0.5 200
−1 100
Rising
Falling
−1.5 0
0 20 40 60 80 100 0 1 2 3 4 5
Time (ns) G029 Differential VOUT (V) G030
2 4
Differential Input Voltage (V)
200 RF = 2 kΩ
RL = 200 Ω
Slew Rate (V/µs)
1 2
150
0 0
100 −1 −2
VS = 5 V
G = 2 V/V
50 −2 −4
RF = 2 kΩ
Rising RL = 200 Ω
Falling −3 −6
0 0 100 200 300 400 500 600 700 800 900 1000
0 1 2 3 4 5 6 7 8 Time (ns) G031
Differential VOUT (V) G054
−60
−60 −65
−70
−70
−75 Second Harmonic
Third Harmonic
−80 −80
1 2 3 4 5 6 7 8 0 2 4 6 8 10
VOUT (Vpp) G034
Gain (V/V) G035
RF = 2 kΩ 4
Single-Ended VOUT (V)
−60 2
VS = 5 V
1.5
−70 G = 2 V/V
1 RF = 2 kΩ
−80 Second Intermodulation
0.5
Third Intermodulation
−90 0
1 10 50 100 1k 10k
Frequency (MHz) G038 Load Resistance (Ω) G039
1
RF = 2 kΩ
10 VOUT = 100 mVpp
0.8
VS = 5 V
0.6 G = 2 V/V 1
RF = 2 kΩ
0.4
0.1
0.2
0 0.01
0.1 1 10 30 10k 100k 1M 10M 40M
Differential Load Current (mA) G040
Frequency (Hz) G041
FREQUENCY RESPONSE RO
vs vs
CLOAD CLOAD
3 200
0 100
−3 VS = 5 V, G = 1 V/V
RF = 2 kΩ, RL = 2 kΩ
−6 VOUT = 100 mVpp
Gain (dB)
RO (Ω)
−9
10
CL = 0 pF, RO = 0 Ω
−12
CL = 15 pF, RO = 200 Ω
−15 CL = 39 pF, RO = 100 Ω VS = 5 V
CL = 120 pF, RO = 50 Ω G = 1 V/V
−18 CL = 470 pF, RO = 20 Ω RF = 2 kΩ
CL = 1200 pF, RO = 12 Ω RL = 2 kΩ
−21 1
100k 1M 10M 100M 1 10 100 1k 2k
Frequency (Hz) G042 CLOAD (pF) G043
−60
2 1
−70
−80 1 0.5
−90 CMRR
PSRR 0 0
−100 0 200 400 600 800 1000
100k 1M 10M 30M Time (ns) G045
Frequency (Hz) G044
4 2
VS = 5 V
Power Down (V)
10 10
3 G = 1 V/V 1.5
RF = 2 kΩ
RL = 200 Ω
2 1
1 1
1 0.5
0 0 0.1 0.1
0 10 20 30 40 50 10 100 1k 10k 100k 1M
Time (ns) G046
Frequency (Hz) G047
Phase G = 1 V/V
VOCM SMALL-SIGNAL FREQUENCY RESPONSE VOCM LARGE- and SMALL SIGNAL PULSE RESPONSE
3 3.2
Output Common-Mode Voltage (V)
0 3
−3 2.8
Gain (dB)
−6 2.6
−9 2.4
TA = 25°C
10k 400
Count
300
1k 200
100
100 0
100k 1M 10M 50M
−50
−45
−40
−35
−30
−25
−20
−15
−10
−5
0
5
10
15
20
25
30
35
40
45
50
Frequency (Hz) G052
Input Offset Current (nA)
G061
10 20
10
8
Count
0
6 −10
4 −20
−30
2
−40
0 −50
−50 −25 0 25 50 75 100 125
−200
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
20
40
60
80
100
120
140
160
180
200
6
Count
Count
100
4
50
2
0 0
−1000
−900
−800
−700
−600
−500
−400
−300
−200
−100
0
100
200
300
400
500
600
700
800
900
1000
1100
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
1
2
3
4
5
6
7
8
9
10
Input Offset Voltage Temperature Drift (µV/°C)
Input Offset Voltage (µV)
G064 G065
400
200
0
−200
−400
−600
−800
−1000
−50 −25 0 25 50 75 100 125
Temperature (°C) G066
Figure 67.
APPLICATION INFORMATION
VIN+ RG RF RO
Input From 50-Ω
Test Equipment
PD
RIT VS+
VOUT– 1:1 Output to 50-Ω
+ Test Equipment
0.22 μF
VOCM THS4531 ROT
–
0.22 μF VOUT+
VS–
VIN– RG RO
No Connection
RF
0.22 μF RIT
Installed to Balance
Amplifier 49.9 Ω
(1) Note components are chosen to achieve gain and 50Ω input termination. Resistor values shown are closest standard values so gains
are approximate.
Table 3. Load Component Values For 1:1 Differential to Single-Ended Output Transformer (1)
RL RO ROT ATTEN
100Ω 25Ω open 6
200Ω 86.6Ω 69.8Ω 16.8
499Ω 237Ω 56.2Ω 25.5
1kΩ 487Ω 52.3Ω 31.8
2kΩ 976Ω 51.1Ω 37.9
(1) Note the total load includes 50Ω termination by the test equipment. Components are chosen to achieve load and 50Ω line termination
through a 1:1 transformer. Resistor values shown are closest standard values so loads are approximate.
Due to the voltage divider on the output formed by the load component values, the amplifier’s output is
attenuated. The column “Atten” in Table 3 shows the attenuation expected from the resistor divider. When using
a transformer at the output as shown in Figure 68, the signal will see slightly more loss due to transformer and
line loss, and these numbers will be approximate. The standard output load used for most tests is 2kΩ with
associated 37.9dB of loss.
Distortion
At 1MHz and above, the circuit shown in Figure 68 is used to measure harmonic, intermodulation distortion, and
output impedance of the amplifier.
A signal generator is used as the signal source and the output is measured with a spectrum analyzer. The output
impedance of the signal generator is 50Ω and is AC coupled. RIT and RG are chosen to impedance match to 50Ω
and maintain the proper gain. To balance the amplifier, a 0.22µF cap and 49.9Ω resistor to ground is inserted
across RIT on the alternate input. A low-pass filter is inserted in series with the input to reduce harmonics
generated at the signal source. The level of the fundamental is measured and then a high-pass filter is inserted
at the output to reduce the fundamental so it does not generate distortion in the input of the spectrum analyzer.
Distortion in the audio band is measured using an audio analyzer. Refer to audio measurement section for detail.
Slew Rate, Transient Response, Settling Time, Overdrive, Output Voltage, and Turn-On/Off Time
The circuit shown in Figure 69 is used to measure slew rate, transient response, settling time, overdrive
recovery, and output voltage swing. Turn on and turn off times are measured with 50Ω input termination on the
PD input, by replacing the 0.22µF capacitor with 49.9Ω resistor.
VIN+ RG RF RO VOUT–
Input From 50-Ω Output to
Test Equipment Test Equipment
PD
RIT VS+
0.22 μF +
VOCM THS4531
–
0.22 μF VS–
VIN– RG RO VOUT+
Output to
No Connection
Test Equipment
RF
0.22 μF RIT
Installed to Balance
Amplifier 49.9 Ω
Figure 69. Slew Rate, Transient Response, Settling Time, ZO, Overdrive Recovery, VOUT Swing, and Turn-
on/off Test Circuit
VIN+ RG RF RO
Input From 50-Ω
Test Equipment
VS+
VOUT–
+
VOCM THS4531 ROT Measure With
– Diff Probe
0.22 μF
VOUT+
VS–
VIN– RG RO
No Connection
RF
RIT Cal Diff Probe
Figure 71 is used to measure the PSRR of VS+ and VS-. The power supply is applied to the network analyzer’s
DC offset input. For both CMRR and PSRR, the output is probed using a high impedance differential probe
across ROT.
Power
Supply
Network
Analyzer
Cal Diff Probe
VIN+ RG RF RO
No Connection
VS+
RIT
VOUT–
+
VOCM THS4531 ROT Measure With
– Diff Probe
0.22 μF VOUT+
VS–
VIN– RG RO
No Connection
RF
RIT
VOCM Input
The circuit shown in Figure 72 is used to measure the transient response, frequency response and input
impedance of the VOCM input. For these tests, the cal point is across the 49.9Ω VOCM termination resistor.
Transient response and frequency response are measured with RCM = 0Ω and using a high impedance
differential probe at the summing junction of the two RO resistors, with respect to ground. The input impedance is
measured using a high impedance differential probe at the VOCM pin and the drop across RCM is used to calculate
the impedance seen looking into the amplifier’s VOCM input.
VIN+ RG RF RO
No Connection
RIT
VS+ For BW
VOUT± Measure With
VOCM RCM Diff Probe Here
From Network +
VOCM THS4531
Analyzer For ZIN -
Measure With
49.9 VOUT+
Diff Probe Here VS±
Cal Diff Probe VIN± RG RO
No Connection
RF
RIT
NC
Balance Error
The circuit shown in Figure 73 is used to measure the balance error of the main differential amplifier. A network
analyzer is used as the signal source and the measurement device. The output impedance of the network
analyzer is 50Ω and is DC coupled. RIT and RG are chosen to impedance match to 50Ω and maintain the proper
gain. To balance the amplifier, a 49.9Ω resistor to ground is inserted across RIT on the alternate input. The output
is measured using a high impedance differential probe at the summing junction of the two RO resistors, with
respect to ground.
VIN+ RG RF RO
Input From 50-Ω
Test Equipment
RIT VS+
Cal Diff Probe VOUT–
Measure With
+ Diff Probe Here
VOCM THS4531
–
0.22 μF
VOUT+
VS–
VIN- RG RO
No Connection
RF
49.9 Ω RIT
Installed to Balance
Amplifier
APPLICATION CIRCUITS
The following circuits show application information for the THS4531. For simplicity, power supply decoupling
capacitors are not shown in these diagrams – please see the EVM and Layout Recommendations section for
recommendations. For more detail on the use and operation of fully differential op amps refer to application
report “Fully-Differential Amplifiers” SLOA054D.
VS±
RG RF
VIN± VOUT+
Figure 74. Differential Input to Differential Output Amplifier
RG RF
VIN+ VOUT–
VS–
RG RF
VOUT+
VS+
Internal 60 kΩ IEXT
VOCM Circuit
VOCM
60 kΩ
VS–
Single-Supply Operation
To facilitate testing with common lab equipment, the THS4531 EVM is built to allow for split-supply operation and
most of the data presented in this data sheet was taken with split-supply power inputs. But the device is
designed for use with single-supply power operation and can easily be used with single-supply power without
degrading the performance. The only requirement is to bias the device properly and the specifications in this data
sheet are given for single supply operation.
−6
−9
−12
−15 RF = 2 kΩ
RF = 10 kΩ
−18
RF = 100 kΩ
−21
100k 1M 10M 100M
Frequency (Hz) G067
Figure 77. THS4531 Frequency Response with Various Gain Setting Resistor Values
200
100
RO (Ω)
10
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
1
1 10 100 1k 2k
CLOAD (pF) G068
Figure 78. Recommended Series Output Resistor vs Capacitive Load for Flat Frequency Response
0
VS = 2.7 V
−3 G = 1 V/V
RF = 2 kΩ
−6 RL = 2 kΩ
Gain (dB)
Audio Performance
The THS4531 provides excellent audio performance with very low quiescent power. To show performance in the
audio band, the device was tested with an audio analyzer. THD+N and FFT tests were run at 1Vrms output
voltage. Performance is the same on both 2.7V and 5V supply. Figure 80 is the test circuit used, and Figure 81
and Figure 82 show performance of the analyzer. In the FFT plot the harmonic spurs are at the testing limit of the
analyzer, which means the THS4531 is actually much better than can be directly measured. Because the
THS4531 distortion performance cannot be directly measured in the audio band it is estimated from
measurement in high noise gain configuration correlated with simulation.
RG RF 10
VIN– VOUT–
100 pF
VS+
+
From Analyzer VOCM THS4531 To Analyzer
–
0.22 μF
RG 10
VIN+ VOUT+
100 pF RF
−95
No Weighting VS = 5 V
−97
A−Weighting G = 1 V/V
−99 VOUT = 1 VRMS
RF = 2 kΩ
−101
RL = 600 Ω
THD+N (dB)
−103
−105
−107
−109
−111
−113
−115
0 5k 10k 15k 20k 24k
Frequency (Hz) G070
0
−10 VS = 5 V
−20 G = 1 V/V
−30 VOUT = 1 VRMS
−40 RF = 2 kΩ
Magnitude (dBV)
RL = 600 Ω
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
0 5k 10k 15k 20k 24k
Frequency (Hz) G071
4 2
VS = 5 V
3 G = 2 V/V 1.5
RF = 2 kΩ
RL = 200 Ω
2 1
5 2.5
Power Supply
VOUT +
4 VOUT − 2
VS = 5 V
3 G = 2 V/V 1.5
RF = 2 kΩ
RL = 200 Ω
2 1
1 0.5
0 0
0 50m 100m 150m 200m
Time (s) G073
With no input tone, Figure 85 shows the voltage waveforms using the PD pin to enable and disable the
THS4531. The transients during power on and off show no audible pop should be heard.
5 2.5
Power Down
VOUT +
4 VOUT − 2
1 0.5
0 0
0 50m 100m 150m 200m
Time (s) G074
2 kΩ
2 kΩ 1 nF 40.2 Ω
VIN–
100 pF
5V
VOUT–
+ To Analyzer
From Analyzer VOCM THS4531 2.7 nF PCM4204
–
0.22 μF
VOUT+
2 kΩ 1 nF 40.2 Ω
VIN+
2 kΩ 100 pF
An audio analyzer is used to provide an analog audio input to the EVM and the PCM formatted digital output is
read by the digital input on the analyzer. Data was taken at fS = 96kHz, and audio output uses PCM format.
Other data rates and formats are expected to show similar performance in line with that shown in the data sheet.
Figure 87 shows the THD+N vs Frequency with no weighting and Figure 88 shows an FFT with 1kHz input tone.
Input signal to the PCM4204 for these tests is -0.5dBFS. Table 4 summarizes results of testing using the
THS4531 + PCM4204 versus typical Data Sheet performance, and show it make an excellent drive amplifier for
this ADC.
−95
−97
−99
−101
THD+N (dBFS)
−103
−105
−107
−109
−111
−113
−115
20 100 1k 10k 20k
Frequency (Hz) G075
0
−10
−20
−30
−40
Magnitude (dBFS)
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
20 100 1k 10k 24k
Frequency (Hz) G076
Table 4. 1kHz AC Analysis: Test Circuit versus PCM4204 Data Sheet Typical Specifications (fS = 96kSPS)
CONFIGURATION TONE THD + N
THS4531 + PCM4204 1kHz -106 dB
PCM4204 Data Sheet (typ) 1kHz -103 dB
The standard ADS8321 EVM and THS4531 EVM are modified to implement the schematic in Figure 89 and used
to test the performance of the THS4531 as a drive amplifier. With single supply +5V supply the output common-
mode of the THS4531 defaults to +2.5V as required at the input of the ADS8321 so the VOCM input of the
THS4531 simply bypassed to GND with 0.22µF capacitor. The summary of results of the FFT analysis versus
typical data sheet performance shown in Table 5 show the THS4531 will make an excellent drive amplifier for
this ADC.
2 kȍ 2 kȍ 121 ȍ
No Input VIN–
100 pF 220 pF
49.9 ȍ 5V
VOUT– To Data
+ Analysis
VOCM THS4531 2.2 nF ADS8321
–
0.22 ȝF
VOUT+
Single-Ended 2 kȍ 2 kȍ 121 ȍ
Signal from
V
Generator and IN+
10 kHz BPF 100 pF 220 pF
49.9 ȍ
0
−10 VS = 5 V
−20 G = 1 V/V
−30 RF = 2 kΩ
−40 VOUT = −0.5 dBFS
Magnitude (dBFS)
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
0 10k 20k 30k 40k 50k
Frequency (Hz) G078
The standard ADS7945 EVM and THS4531 EVM are modified to implement the schematic in Figure 91 and used
to test the performance of the THS4531 as a drive amplifier. With single supply +5V supply the output common-
mode of the THS4531 defaults to +2.5V as required at the input of the ADS7945 so the VOCM input of the
THS4531 simply bypassed to GND with 0.22µF capacitor. The summary of results of the FFT analysis versus
typical data sheet performance shown in Table 6 show the THS4531 will make an excellent drive amplifier for
this ADC.
2 kȍ 2 kȍ 40.2 ȍ
VIN–
100 pF
5V
VOUT– To Data
Differential
+ Analysis
Signal from
VOCM THS4531 1 nF ADS7945
Generator and –
10 kHz BPF 0.22 ȝF
VOUT+
2 kȍ 2 kȍ 40.2 ȍ
VIN+
100 pF
0
−10 VS = 5 V
−20 G = 1 V/V
−30 RF = 2 kΩ
−40 VOUT = −0.5 dBFS
Magnitude (dBFS)
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
1k 10k 100k 1M
Frequency (Hz) G077
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Deleted DC Performance, Input-referred offset voltage parameter typical specifications for TA = 0°C to +70°C,
–40°C to +85°C, and –40°C to +125°C in 2.7 V Electrical Characteristics table ................................................................. 4
• Changed DC Performance, Input-referred offset voltage parameter maximum specifications for TA = 0°C to +70°C,
–40°C to +85°C, and –40°C to +125°C in 2.7 V Electrical Characteristics table ................................................................. 4
• Changed DC Performance, Input offset voltage drift parameter typical and maximum specifications in 2.7 V
Electrical Characteristics table .............................................................................................................................................. 4
• Deleted DC Performance, Input bias current parameter typical specifications for TA = 0°C to +70°C, –40°C to
+85°C, and –40°C to +125°C in 2.7 V Electrical Characteristics table ................................................................................. 4
• Deleted DC Performance, Input bias current drift parameter typical specifications in 2.7 V Electrical Characteristics
table ...................................................................................................................................................................................... 4
• Deleted DC Performance, Input offset current parameter typical specifications for TA = 0°C to +70°C, –40°C to
+85°C, and –40°C to +125°C in 2.7 V Electrical Characteristics table ................................................................................. 4
• Deleted DC Performance, Input-referred offset voltage parameter typical specifications for TA = 0°C to +70°C,
–40°C to +85°C, and –40°C to +125°C in 5 V Electrical Characteristics table .................................................................... 7
• Changed DC Performance, Input-referred offset voltage parameter maximum specifications for TA = 0°C to +70°C,
–40°C to +85°C, and –40°C to +125°C in 5 V Electrical Characteristics table .................................................................... 7
• Changed DC Performance, Input offset voltage drift parameter typical specifications in 5 V Electrical Characteristics
table ...................................................................................................................................................................................... 7
• Deleted DC Performance, Input bias current parameter typical specifications for TA = 0°C to +70°C,–40°C to +85°C,
and –40°C to +125°C in 5 V Electrical Characteristics table ................................................................................................ 7
• Deleted DC Performance, Input offset current parameter typical specifications for TA = 0°C to +70°C, –40°C to
+85°C, and –40°C to +125°C in 5 V Electrical Characteristics table .................................................................................... 7
www.ti.com 11-Apr-2013
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples
(1) Drawing Qty (2) (3) (4)
THS4531ID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 T4531
& no Sb/Br)
THS4531IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 4531
& no Sb/Br)
THS4531IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 4531
& no Sb/Br)
THS4531IDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 T4531
& no Sb/Br)
THS4531IRUNR ACTIVE QFN RUN 10 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 4531
& no Sb/Br)
THS4531IRUNT ACTIVE QFN RUN 10 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 4531
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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