Code No. B22103083 Date: 25.05.

2015

CVR COLLEGE OF ENGINEERING

UGC Autonomous Institution - Affiliated to JNTUH R12
B. Tech. II year, II sem. Main Examinations, May – 2015
Subject: Structured Digital System Design
Branch: EIE
Time: 3 hours Max. Marks: 75

PART – A 10x2= 20 Marks

(Answer ALL Questions)

1. What is a multiplexer and list some applications of multiplexers?

2. Define figure of merit and clock skew?
3. Draw only circuit diagram which convert J-k flip flop into T flip flop?
4. Write short notes on analysis of synchronous sequential circuits?
5. With necessary diagram explain the operation of modulus 4 (mod-4) counter?
6. Define the basic operational characteristics of systems?
7. Write short notes on wired logic?
8. Compare ROM and PLA?
9. Draw the diagram for binary to gray code conversion?
10. Differentiate between registers and counters?

PART – B 5x11 = 55 Marks

(Answer any FIVE questions)

11. a) Draw the logic diagram using AND, OR and INVERTERS for F = (A 𝐵 + C 𝐷 ) (H); if A and C are
ASSERTED HIGH and B and D are ASSERTED LOW.
b) Draw circuit diagrams for creating AND, OR and NOT gates using 4x1 MUXs. [6+5]

12. a) Define fan-out, fan-in, standard load and propagation delay.

b) Make a comparison between open collector and tri – state bus system by considering loading,
speed etc. [5+6]

13. a) Explain the difference between latch and flip flop.

b) Design D Latch from SR flip-flop. [5+6]

14. a) With an example explain the Analysis of Synchronous Sequential Circuits.

b) Explain in detail, the design steps For Traditional Synchronous sequential circuits. [6+5]

15. a) Design a mod-10 ripple counter using T flip flops and explain the operation?
b) Design a Mod-6 synchronous counter using J-K flip flops. [6+5]

16. a) Explain System Controllers. Discuss the Controller Design Phase and System Documentation.
b) Explain the MDS diagram construction concepts with flow diagram. [5+6]

17. a) Explain about the next state decoder.

b) How is clock Frequency Determined? [5+6]

18. a) Design a PLA circuit to implement the following function

FO=ABC+AD; F1=ABD+BD; F2=ACD+D’.
b) Design full adder using ROM . [6+5]

*****