Allegro PCB SI 230/610/630 Tutorial, Product Version 15.

Contents
Lesson 1
Welcome #32;

Objectives #32;

About Online Documentation #32;

Working with Database Files #32;

Board databases used in this tutorial #32;

Starting the Tutorial #32;

Controlling your View of the design #32;

Save the Design #32;

To Summarize What You Have Learned #32;

Lesson 2
Objectives #32;

Working with a Single Net #32;

Extracting a Net Topology #32;

To Summarize What You Have Learned #32;

Lesson 3
Objectives #32;

Extracting a Net Topology #32;

Exploring the Circuit Topology #32;

 Examine the circuit parameters #32;
Examine the IOCell models #32;

Setting Up for Simulation #32;

Specifying Stimulus #32;

Specifying Reflection Measurements #32;

Simulation and Analysis #32;

Taking a closer look #32;

Finishing Up #32;

To Summarize What You Have Learned #32;

Lesson 4
Revising the Board Layout #32;

Moving the clock driver #32;

Swapping Components #32;

Simulation and Analysis #32;

Making Signal-to-Signal Comparisons #32;

Finishing Up #32;

To Summarize What You Have Learned #32;

Lesson 5
Routing the Clock Driver Net #32;

Exploring the Extracted Circuit Topology #32;

Simulation and Analysis #32;

Finishing Up #32;

To Summarize What You Have Learned #32;

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For support, see http://www.cadence.com/support or try Cadence's SourceLink service.

Copyright © 2004, Cadence Design Systems, Inc.

All rights reserved.
Legal notices and trademark attributions
Allegro PCB SI 230/610/630
Tutorial
Product Version 15.2
June 2004

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Copyright © 2004, Cadence Design Systems, Inc.

All rights reserved.
 Allegro PCB SI 230/610/630 Tutorial, Product Version 15.2

Lesson 1

Welcome
This tutorial is designed to familiarize you with Allegro PCB SI
230/610/630. It assumes that you already know how to use SI 230/610/630
and that you are familiar with Windows®. You begin this tutorial from the
PCB Editor.

Objectives
In this lesson, you learn:

• about what comprises the SI 230/610/630 information set.

• about the board database files that are used in this tutorial.
• how to start the tutorial from the PCB Editor.
• how to change your view of the board in the PCB Editor.

About Online Documentation

The SI 230/610/630 documentation set consists of online help and an
online books. All documentation is accessible from the SI 230/610/630
help menu.

Refer to . . . for this level of information

Getting Started with This book is for users who know how to use the PCB
Allegro PCB SI Editor but are new to the signal integrity field.
230/610/630
A light introduction to the major features of SI
230/610/630 including net extraction, reflection
simulation, and analysis.
Allegro PCB SI This book complements Getting Started by guiding you
230/610/630 Tutorial through a series of exercises that lead to optimized
(this book) placement based on signal exploration and analysis.
Allegro PCB SI Online help provides a more in-depth look at SI
230/610/630 online 230/610/630 and signal integrity concepts.
help

Working with Database Files

The SI 230/610/630 tutorial uses five board database files for use in each
successive lesson. The prerequisite section of each lesson informs you
which board file to use. To start the tutorial, you should first make a
writable folder (a working directory) on your hard drive. You should copy
the board (.brd) files, and the devices.dml file, from the product CD (or
from your network) to this local, working directory on your hard drive.
The board files for the tutorial are on the product CD at the following
location in your installation heirarchy.

<install_dir>\doc\assetut\goldenboards

We suggest that you complete each lesson in sequence. In this way, the
state of the board file at the end of one lesson can be used as the starting
point for the next lesson. You can, though, take a lesson out of sequence
by loading the appropriate board file for that lesson. See Board databases
used in this tutorial.

You can also complete this tutorial by copying and renaming

tutboard1.brd to any file name that you like: perhaps
myboard1.brd. As you progress through each lesson, you
would then save the board in succession (myboard2.brd, . . .)
and use it to start the next lesson. In this way, your results are
based on the placement decisions that you make; therefore,
they may differ slightly with those in the text. This approach
also promotes a feeling of continuity in the tutorial.
Board databases used in this tutorial

Lesson 1 • Board database contains netlist

tutboard1.brd • Board shows full ratsnest display

Lesson 2 • Clock net (cclock) in the PCB Editor is not extractable

tutboard2.brd for topology exploration and analysis in SI 230/610/630.
• Board shows full ratsnest display

Lesson 3 • Board shows full ratsnest display off (blank); cclock

tutboard3.brd visible
• Clock net (cclock) is now extractable for topology
exploration and analysis

Lesson 4 • Critical high-speed components are not optimally placed

tutboard4.brd resulting in excessive length of the clock driver signal
that feed these components
•

Lesson 5 • Clock driver, U9, is relocated to a central location among

tutboard5.brd the components that it drives
• The clock net, cclock, is reduced in length from
swapping component U93 with U70 and U85 with U16

Note: Although the design databases tutboard1.brd and

tutboard2.brd are identical, as are tutboard3.brd and
tutboard4.brd,we've supplied each to maintain continuity between the
board number and the lesson number.

Also, to end this tutorial, you can optionally save the clock net that you
routed in Lesson 5, as myboard6.brd. In this way, you can archive the
entire tutorial for later reference.
Starting the Tutorial
Now that you have set up a working directory as described in Board
databases used in this tutorial, you're ready to start the first lesson.

The first lesson explains how to navigate within the PCB Editor using
zoom and pan commands. These principles hold true for moving around in
SI 230/610/630 and SigWave, which you are asked do in later lessons.

To open the board database file

1. From the PCB Editor, choose File > Open.

If a design is already open, you will be prompted to save it before

continuing.

The Open dialog box appears.

2. Click the change directory check box to ensure that your design is
saved to the working directory that you set up.

3. Double-click tutboard1.brd.
The board database is loaded into the PCB Editor with all ratsnest
displayed.

Controlling your View of the design

This section discusses zoom and pan commands. You use these commands
to refocus your view of the board layout (in the PCB Editor), topology
canvas or spreadsheet (in SI 230/610/630), or waveform display (in
SigWave). These commands can be accessed from the View menu in the
PCB Editor and SI 230/610/630, or from the Zoom menu in SigWave. You
can also access each of these commands from icons in the tool bar

This section is only for reference. You do not perform any exercises.
There are many zoom commands; however, in this tutorial, we'll limit our
discussion In, Out, Points, Fit, and Pan.

This zoom Is used to . . .

command . . .
In Display an enlarged view of the board, topology, or
waveform.
Out Display an reduced view of the board, topology, or waveform.
Points Display an area of the board, topology, or waveform by
selecting a starting and ending point.

Click to anchor the starting point, drag across the area,

and click to define the end point.

The view now focuses around this area.

Fit Display the entire board, topology, or waveform.
Pan Roam the board or topology.

To pan the board or topology, hold down the SHIFT

key, click-right, and drag (Up, Down, Left, Right)

The following depicts zoom commands available from the PCB Editor.
The equivalent menu commands from SI 230/610/630 and SigWave are
also shown.
Save the Design

You have not modified the board in this lesson, but to maintain continuity
between the board number and the lesson number, if you are using your
own board files choose File > Save As and specify myboard2.brd (or
whatever naming convention you chose).

Congratulations! You have completed Lesson 1.

 To Summarize What You Have Learned
In this lesson, you learned:

• what is contained in the information set.

• about the board database files and their design state.
• how to use the zoom and pan commands.

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For support, see http://www.cadence.com/support or try Cadence's SourceLink service.

Copyright © 2004, Cadence Design Systems, Inc.

All rights reserved.
Legal notices and trademark attributions
 Allegro PCB SI 230/610/630 Tutorial, Product Version 15.2

Lesson 2

Objectives
In this lesson, you:

• highlight a net in the PCB Editor for extraction into Allegro PCB
SI 230/610/630.
• become familiar with the Topology Template dialog box.
• attempt to extract a net from the PCB Editor for topology
exploration in Allegro PCB SI 230/610/630.
• prepare a net for extraction by running the Database Setup
Advisor.

Working with a Single Net

High-speed considerations do not necessarily involve the entire design;
rather, they may just involve the placement and routing, one-by-one, of
only a few critical nets. In this tutorial, you will analyze the clock net
cclock for optimum placement and routing.

In this exercise, you will isolate the clock net so that it is easier to work
with. You accomplish this in two steps.

To begin this lesson, you should have tutboard2.brd open in the PCB
Editor.

To hide all ratsnest

From the PCB Editor, choose Display - Blank Rats - All.

The drawing appears to be far less cluttered.

To display a single ratsnest

1. From the PCB Editor, choose Display - Show Rats - Net. (For
Allegro PCB SI 230/610/630, choose Display - Ratsnest...)

2. Click the Find (find filter) tab in the Control Panel.

The Nets checkbox is active.

 3. Enter cclock in the Find By Name field.

4. Press Return

The ratsnest connections for cclock are now highlighted in your

drawing.

Notice the net connects connector J7, the clock driver U9, and the
processor chipset.

Extracting a Net Topology

In this exercise, you attempt to extract cclock for exploration and analysis.
The device definition for connector J7, which is connected to cclock, has
an incorrect CLASS property, rendering cclock unextractable.

You will run the Database Setup Advisor to identify and correct this
problem.

To extract a net topology

1. From the Menu, pick Analyze->SI/EMI Sim->Probe.

The Signal Analysis form appears.

 2. Select the clock driver net, cclock, using one of the following
methods:
o Pick the Net Browser button and filter for net cclock, then
OK the Signal Select Browser form.
o Click on the net in the design.

The selected net (cclock) will seed the Signal Analysis form. Pick
View Topology to extract the net topology.

The net extraction begins.

The following message appears.

3. Click Yes.

The Database Setup Advisor is invoked.

The Database Setup Advisor guides you through the following five steps
that prepare a net for extraction into SI 230/610/630.

• Cross-section
• DC Nets
• Devices
• SI Models
• SI Audit
 Consult Getting Started with Allegro PCB SI 230/610/630 for
information on using the Database Setup Advisor.

The Database Set Up Advisor is invoked automatically when a non-

extractable net is encountered. You can also invoke the advisor with the
Tools - Setup Advisor command from the PCB Editor.

As mentioned earlier, the device definition for connector J7, which is

connected to cclock, has an incorrect CLASS property, rendering cclock
unextractable. Therefore, you need only work in the Devices section of
the Database Setup Advisor.

To correct a device PINUSE with the Database Setup Advisor

From the previous exercise, you should have the advisor displayed.

1. Click Next three times to advance to the Device Setup form in the
advisor.

2. Click Device Setup.

The Device Setup dialog box appears with a brief explanation of

how to set up device parameters.

3. Click the Device Setup button.

The following dialog box appears.

4. Accept J* in the Connectors field (the default).

The device's PINUSE information derives from the device's

CLASS definition.

5. Click OK.

The Device Setup Changes report appears.

 Note that connector J7 was changed from class IC to IO. Because J9
shares the same device definition, it was changed as well. Other
connectors in the design remain unchanged with class IO.

Had you explicitly specified J7 (instead of J*), J7 and J9

would change to class IO because they share the same part
type; however, all other connectors would change to class IC
because it is the default value.

6. Dismiss the report.

7. Click Finish to accept the database modifications and dismiss the

advisor.

With the correct CLASS properties (IO) on Connectors J7 and J9, the clock
net is now prepared for extraction.

You repeat the net extraction process in the next lesson. If you are using
your own board files, in the PCB Editor, choose File - Save As and specify
myboard3.brd (or whatever naming convention you chose).

Congratulations! You have completed Lesson 2.

To Summarize What You Have Learned

In this lesson, you have learned to

• isolate a single net among a sea of nets.

• use the Topology Template dialog box.
• prepare a net for extraction by running the Database Setup
Advisor.

Return to top of page

For support, see http://www.cadence.com/support or try Cadence's SourceLink service.

Copyright © 2004, Cadence Design Systems, Inc.

All rights reserved.
Legal notices and trademark attributions
 Allegro PCB SI 230/610/630 Tutorial, Product Version 15.2

Lesson 3

Objectives
In this lesson, you:

• extract a net from the PCB Editor for topology exploration in Allegro PCB SI
230/610/630.
• explore the extracted circuit topology in SI 230/610/630.
• set up reflection measurements in SI 230/610/630.
• simulate a net topology in SI 230/610/630.
• analyze the resulting spreadsheet- and waveform-data in SI 230/610/630.

Extracting a Net Topology

In this exercise, you will extract a net topology for clock signal -- cclock. You begin with
tutboard3.brd loaded in the PCB Editor.

To extract a net topology

1. From the Menu, pick Analyze->SI/EMI Sim->Probe.

The Signal Analysis form appears.

 2. Using the net selection techniques that you learned in the previous lesson, extract
the clock driver net--cclock.

The net extraction begins.

The following message appears - because no signal models have been assigned to
components on the net:

3. Select 'No' to launch SigXplorer and extract the topology using default Cadence
SI buffer models.

Exploring the Circuit Topology

Upon initial invocation, the editor displays only the canvas. The spreadsheet is 'sized' out
of view. Resize the canvas so that it occupies about three-quarters of the SI 230/610/630
window.

To resize the canvas area and zoom level

1. Click the horizontal border separating the canvas and the spreadsheet, then drag
the border vertically.

2. Click in the canvas and click the zoom fit icon.

The circuit topology expands to accommodate the resized canvas view.

With the topology extracted from your design in the PCB Editor and visible in SI
230/610/630, you should make the following observations. You may have to zoom and
pan as appropriate.

Notice that:

• The off-board connector (J7) along with a single driver (U9, Pin 9) and many
receivers
• Transmission lines with delays based on length (derived from Manhattan distance
estimates)
• The driver and all receivers default to Tristate on initial extraction.
• Default IOCell models were assigned to drivers and receivers based on PINUSE

When you select a circuit component in the spreadsheet at the bottom

of the editor, it will highlight in the topology canvas, at the top of the
editor.

Examine the circuit parameters

Click Parameters and expand all circuit parameters by clicking the + signs until the
spreadsheet shows all - signs, indicating the lowest level.
Note the characteristic impedances for the transmission lines in the circuit. You can click
in the attribute Name field and change any of these values. The topology element in the
canvas will be updated with the new value.

Examine the IOCell models

Examine the attribute and value (IOCell buffer model) field of receiver U69.

You can select a different IOCell buffer model based on your requirements.

Dismiss the Set Buffer Parameter dialog box.

Note: Consult the ` online help for a thorough discussion of signal integrity models.

Setting Up for Simulation

Before you can simulate and analyze this circuit topology, you must set up for simulation.
This involves specifying:

• Stimulus for the driver (U9, Pin 9)

• Reflection measurements

Each is discussed in the sections that follow.

Specifying Stimulus

The receivers are preset to their default tri-state condition. You must set the driver to
either a Pulse, Rise, or Fall state. You can simulate with only one active driver at a time,
which is not an issue with the cclock net as it has only a single driver (U9, Pin 9).

To set the driver stimulus state

1. Zoom in on the driver.

Note the label on the symbol indicating it is 'tri-stated.'

2. Click the TRISTATE label on U9.

The Stimulus Editor appears.

 3. Click Pulse.

4. Click OK.

The stimulate state of the driver changes to Pulse.

Specifying Reflection Measurements

1. Resize the spreadsheet view to occupy about two-thirds of the editor.

2. Click the Measurements tab.

 3. Click the reflection button to expand the measurements view.

4. Click the circle adjacent to the reflection label, and then right-click and choose All
Off from the pop-up window.

5. Click on individual measurements as follows:

You are ready to simulate.

Simulation and Analysis

Now that you have specified a stimulus for the driver, have verified that all receivers are
tri-stated, and have set up measurements to sample, you are now ready to simulate.

To simulate the topology

Choose Analyze - Simulate.

A pop-up window displays as the simulation progresses. The Command window also
becomes active in the spreadsheet so you can monitor the simulation.

Once simulation is complete, the Results View appears showing the spreadsheet data.

You can click on a column header followed by a right-click to invoke

a pop-up menu from which you can specify an ordering scheme for
the spreadsheet data. The figure below shows an ascending ordering
of data.

Notice in the Overshoot Low column, many of the receivers approach negative 900
millivolts.

Next, SigWave appears showing the output waveforms from the simulation.
Observations include: (1) skew at the clock input to the receivers; (2), a fair amount of
ringing; (3), a noticeable negative overshoot of 900 mV below ground; and (4), some
non-monotonic activity.

Taking a closer look

In SigWave, you are going to take a closer look at the problem areas of the waveforms.

To zoom in on the bottom of the waveform

1. Click in the SigWave window.

2. Choose Zoom - In Region.

3. Drag over the bottom of the waveforms.

SigWave focuses on the selected area.

The input protection diodes in the receivers are designed to fire at -700 millivolts. You
are going to measure the duration that the waveforms dip below this threshold.

To mark off time measurements

1. Drag the horizontal marker--vertically--to this point (-700 mV).

 2. Click the differential vertical marker icon in the toolbar and size each marker to
correspond to the beginning and ending points where the waveforms extend
below the -700 mV threshold.

This should measure approximately 3 nanoseconds in duration. This much negative

overshoot lasting for this duration will soon damage the receivers. You will need to take
corrective actions to optimize the placement.

Finishing Up

In SigWave, save the waveform as preplaced.

A .sim file extension is automatically added to the base file name. In the next lesson, you
will use this for making comparisons.

If you are using your own board files, in the PCB Editor, choose File - Save As and
specify myboard4.brd (or whatever naming convention you chose).

Congratulations! You have completed Lesson 3.

To Summarize What You Have Learned

In this lesson, you learned to:

• extract a circuit topology.

• explore the circuit topology.
• set up simulation parameters (stimulus and measurements).
• simulate and analyze a circuit topology.
Return to top of page

For support, see http://www.cadence.com/support or try Cadence's SourceLink service.

Copyright © 2004, Cadence Design Systems, Inc.

All rights reserved.
Legal notices and trademark attributions
 Allegro PCB SI 230/610/630 Tutorial, Product Version 15.2

Lesson 4
Objectives

In this lesson, you:

• move the clock driver chip in the PCB Editor to a location that is
central to other components on the clock circuit.
• swap components in the PCB Editor to reduce the length of the
clock circuit.
• simulate this revised circuit topology in Allegro PCB SI
230/610/630.
• analyze the resulting spreadsheet- and waveform-data in Allegro
PCB SI 230/610/630.

Revising the Board Layout

In Lesson 3, you extracted the clock circuit from the PCB Editor based on
its initial placement. You performed a reflection simulation in SI
230/610/630 and analyzed results that were unacceptable. In this lesson,
you modify the placement of the clock circuit and repeat the analysis
process.

To begin this lesson, you should have tutboard4.brd open in the PCB
Editor.

Moving the clock driver

The clock driver (U9) is located in the lower-left quadrant of the board,
which is some distance from many of the chips (receivers) that it controls.
To minimize delays at the receivers, it is best to centralize the placement
of this driver.
To move the clock chip

1. From the PCB Editor, choose Place - Move.

2. Drag the cursor (crosshair) across U9 and select it to move.

3. Move U9 by dragging to the location shown below.

The ratsnest connections follow the movement of the chip.

4. Click to anchor the placement.

5. Right-click and choose Done from the pop-up menu.

Swapping Components

Although the clock driver is now closer to the receivers, you can shorten
the length of the clock net even more by swapping some of the receivers,
with chips of the same type, that are even closer to the driver.

In this exercise, you will swap U93 with U70, and U85 with U16.
To swap components

1. From the PCB Editor, choose View - Zoom by Points.

2. Drag across the lower-right quadrant of the board.

The view now focuses on the chips that you will swap. Allegro
PCB SI 230/610/630 menus do not have a component swap
sselection, but the command can still be accessed by typing
helpcmd.

3. From the Command Browser, select Swap Components.

o Click U93 (the source component), then click U70 (the
target component)

The components exchange places on the board.

o Click U85 (the source component), then click U16 (the

target component)

The components exchange places on the board.

o Right-click and choose Done from the pop-up menu.

This ends the swap component mode.

Close the Command Browser.

Simulation and Analysis

Now that you modified the placement in your design by moving the clock
chip and some of the receivers, resimulate the clock net to see if you have
reduced the noise margin.

In Lesson 3, you learned how to do the following.

• Extract a Net Topology

• Examine Circuit Parameters
• Specify Stimulus (Pulse)
• Specify Measurements
• Simulate

Put these skills to work and simulate the revised circuit topology. The
measurements that you previously specified are still in effect. You do not
have to reselect them. If SigXplorer is still open, confirm that you want to
overwrite the old topology.

Making Signal-to-Signal Comparisons

To go a step further, you superimpose the pre-placed waveform

(preplace.sim) that you saved in the previous lesson onto the placed
waveform which currently displays in SigWave.

You then examine pre- and post-placement waveforms with all signals
displayed, followed by a signal-to-signal comparison.

To superimpose simulation waveforms

1. From SigWave, choose File - Import - SigWave or Touchstone file.

The File Open dialog box appears.

2. Double click preplaced.sim.

The pre-placed waveform (preplaced.sim) is superimposed over

the placed waveform which remains in memory.
 3. Expand the signals (as shown) in the waveform libraries folder by
clicking the + signs.

4. Size the SigWave window (as shown) so that you can view the
signal names.

You should observe that all signals from both waveforms display with
minimal deviation.

To examine both waveforms (signal-by-signal)

1. Click on each waveform sub-folder in the waveform library folder,

then right-click and choose hide all subitems from the pop-up
menu.

Each signal in SigWave is now identified with a slashed-circle in the left

pane; waveforms are suppressed in the right pane.
 When manipulating a signal in the left pane of SigWave, you
may have to click in the right pane to refresh the waveform
display.

2. One at a time, compare each pin of the pre-placed waveform with

the corresponding pin of the placed waveform by selecting the net,
and then right-click and choose Display from the pop-up menu.

You should observe results similar to the following.

Note: The composite drawing below captures the resulting waveform and
spreadsheet data from pre-placed and placed simulations.

You should observe a marked improvement in the waveforms and in the

numbers. The negative overshoot is approximately -150 mV. Well within
 the -700 mV margin where the input protection diodes turn on. There is
also far less ringing and skew among the receivers.

Finishing Up

From SigWave, choose File - Save and enter placed.

In the next lesson, you compare this pre-route waveform (placed.sim)

against the post-route waveform.

If you are using your own board files, in the PCB Editor, choose File - Save
As and specify myboard5.brd (or whatever naming convention you chose).

Congratulations! You have completed Lesson 4.

To Summarize What You Have Learned

In this lesson, you have learned to:

• modify placement by moving and swapping components.

• compare current simulation waveforms (based on revised
placement) against previously saved waveforms (based on initial
placement).

Return to top of page

For support, see http://www.cadence.com/support or try Cadence's SourceLink service.

Copyright © 2004, Cadence Design Systems, Inc.

All rights reserved.
Legal notices and trademark attributions
 Allegro PCB SI 230/610/630 Tutorial, Product Version 15.2

Lesson 5
Objectives

In this lesson, you:

• route the clock net.

• simulate the clock net using actual trace models instead of
Manhattan distance estimates.
• compare simulation waveforms (routed) against previously saved
waveforms (unrouted).

Routing the Clock Driver Net

In Lesson 4, you extracted the clock circuit from the PCB Editor based on
the revised placement. You performed a reflection simulation in SI
230/610/630 and analyzed the results that are now acceptable. In this
lesson, you route the clock net and repeat the simulation and analysis
process to verify that you still meet the noise budget.

To begin this lesson, you should have tutboard5.brd open in the PCB
Editor.

To route the clock net

1. From the PCB Editor, choose Route - Route Net(s) By Pick.

2. Click on the visible ratsnest -- cclock.

The PCB Router routes your board in the background. RMB and
pick done when the route completes.
Exploring the Extracted Circuit Topology
Using the skills that you learned in previous lessons, extract the topology
of net cclock.

• Resize the SigXplorer canvas and the spreadsheet equally.

• Zoom in on transmission line symbol MS1.
• Click the parameters tab in the spreadsheet and expand the
parameter view to examine the attribute values of MS1.
The extracted interconnect model describes the trace model for the cline
section of routed net.

Simulation and Analysis

Now that you have routed the clock net in your design, you resimulate to
verify that you have maintained the revised placement noise margin.

In previous lessons, you learned how to do the following:

• Specify Stimulus
• Specify Measurements
• Simulate
• Compare resulting simulation waveforms

Put these skills to work and simulate the routed circuit topology.
 The pre-routed topology that you extracted in the previous
lesson was based on a virtual representation. The routed
topology that you are about to extract is based on a physical
layout with layer and via information; therefore, before you
simulate from SI 230/610/630, you must choose Analyze -
Reset Sim Data to reload the interconnect library that
contains the electrical model for the extracted via.

If SigXplorer is still open, confirm that you want to overwrite the old
topology. You should observe results similar to the following.

Note: The composite drawing below captures the resulting waveform and
spreadsheet data from pre-route and post-route simulations.

Notice that the post-route waveforms are even more ideal than the
waveforms from the modified placement. There is less skew among the
receivers, the negative overshoot was reduced from -148.9 mV to -95.5
mV.

Finishing Up

If you are using your own board files, in the PCB Editor, choose File - Save
As and specify myboard6.brd (or whatever naming convention you chose).

Congratulations! You have completed Lesson 5 and the tutorial.

 To Summarize What You Have Learned
In this lesson, you learned to:

• extract a net topology from the PCB Editor into SI 230/610/630.

• compare current simulation waveforms against previously
generated waveforms (based on revised placement).

In this tutorial, you learned to:

• prepare a net for extraction from the PCB Editor into SI

230/610/630.
• Extract a net based on the initial placement in the PCB Editor,
simulate the net in SI 230/610/630 , and examine the resulting data
in the results view of the spreadsheet as well as the resulting
waveforms in SigWave.
• Modify the placement in the PCB Editor, resimulate and analyze
the waveforms, and observe more ideal (less ringing among the
receivers, less skew, and less negative overshoot) waveforms.
• Route the net, resimulate and analyze to verify that the net remains
within the noise budget.

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