Embedded

Systems and Automation Evolution of FPDs

1. Mask-Programmed Gate Arrays
---------------------PPT 1--------------------- (MPGAs)
Embedded System -traditional gate arrays
-control system -pre-fabricated transistors that can be
-specific tasks customized into the user’s logic
-specialized computing machine circuit by connecting the transisors
-NOT FPD
Types of Computing Machines -motivated the design of FPGAs
-General Purpose
-Embedded 2. Field-Programmable Logic Array (FPLA)
-Simple Programmable Logic Devices
General-Purpose Computing Machine (SPLDs)
-has few, standardized I/Os -two levels of logic gates (AND
-end user directly interacts with it followed by OR)
-maintain balance, therefore compromising -suited for sum of products form
other areas -also known as PLA
-expensive and offers poor speed
Embedded Computing Machine
-more specialized peripherals 3. Complex Programmable Logic Devices
-component of some larger product (CPLD)
-no interaction with end user -pioneered by ALTERA
-specific purpose only -equivalent to 50 typical SPLD

Digital Design Platforms 4. Field-Programmable Gate Arrays
Microprocessor (FPGAs)
-central processing of a computer, does not
have RAM and ROM Structure of FPGAs
-unspecific tasks
I/O interfaces
Microcontroller -internal logic to external sources
-has memory, microprocessor, and I/O in a -data are received from external
single chip (computer on a chip) -can either be unidirectional or bidirectional
-specific tasks
Basic Logic Building Blocks (in general)
Field Programmable Devices (FPDs) -Preconfigured logic or resources used to build
-Programmable Logic Devices (PLDs) your design
-any IC used for implementing digital hardware -defined by manufacturer
-uses special programming unit

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Basic Logic Building Blocks (for Altera)
-called ADAPTIVE LOGIC MODULE (ALM) Conventions
-combinational logic of ALM has 8 inputs and a
lookup table (LUT) White Space – for readability
Comments - // (for single line), /* */ for
multiple lines
Basic Logic Building Blocks (for Xilinx) Strings – “Verilog!”
-called CONFIGURABLE LOGIC BLOCKS (CLBs) Identifiers – variables used by coder. Case
sensitive, must begin with a letter. Numbers,
Interconnect underscore, and $ can be used.
-connecting basic building blocks to perform
design-specific functions Verilog Statements
-also connecting the internal logic to I/O
interfaces Concurrent
-Do not follow any order
-Even if statements are rearranged, same
----------------------PPT 2----------------------- result.

Popular HDL Tools Ex:
same as
VHDL (VHSIC HDL) if (z==1) if (z==1)
-Very High-Speed Integrated Circuits Hardware begin begin
Description Language x<=y; y<=z;
-for US Dept of Defense y<=z; x<=y;
end end
Verilog HDL
-most commonly used in the design, (past value of y is transferred to x, value of z is
verification, and implementation of digital logic transferred to y as new value, regardless of
chips at register-level order)

HDL vs C
HDL utilizes: Sequential
Not same as
Concurrency – ability to do several things if (z==1) if (z==1)
simultaneously begin begin
x=y; y=z;

y=z; x=y;
Timing – ability to represent the passing of end end
time and sequence events accordingly
(past value of y to x, (new value of
new value of y is z) y is z, new value
of x is new y.
Therefore, z is
transferred to
both x and y)

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Verilog Model Structure Logic Values
4 main parts: 1 – one, high, true
-Module Header 0 – zero, low, false
-Port Declaration z – high impedance (data cannot pass)
-Variable Declaration x – unknown (or don’t care)
-Main Body
Memories – two-dimensional arrays
Module Header

Parameters – defines a parameter, should be
an integer constant number


Port Declaration
1. input
2. output
3. reg Numbers
syntax: port_direction [port_size] port_name;
example: reg [40:0] counter;

Data Types

1. Nets, Registers, Vectors
2. Logic Values
3. Integer, Real
4. Arrays
5. Memories
6. Parameters
7. Strings Example: 8’hAA ----> stored as 10101010

Nets – connections between elements NOTE: (tinanong ni ma’am nung naglecture)

If bitwidth is smaller than value, leftmost bits
are truncated.
If bitwidth is greater than value, leftmost bits
are filled depending on value of leftmost bit.
Registers – data storage Convention:
If leftmost bit is 0 or 1, fill in with 0s.
If leftmost bit is Z, fill in with Z’s.
If leftmost bit is X, fill in with X’s.

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Examples: Programming Statements
6’b10101111 ----> stored as 101111 (truncated)
6’b001 ----> stored as 000001 (filled in with 0s) Conditional Statements
10’bZ --> stored as ZZZZZZZZZZ (filled in with Zs) - If-else and case statements

Looping Statements
Procedural Blocks - while and for statements

Initial Blocks – executed once only Operators: Bitwise
Always Blocks – loop continuously

Note:
Multiple blocks are CONCURRENT
Statement groups are enclosed with ‘begin’ and
‘end’

Initial blocks:

assign ledred = red;
assign ledgreen = green;
parameter n8 = 7’b0000000;

Always blocks:

always @ (posedge clk)
if (x==0)
begin
. . .
end
Miscellaneous Operators

Concatenation {,}
- joins bits together two or more comma-
Procedural Assignment separated expression

Non-blocking
-value of RHS is transferred to LHS
-LHS must be a register data type only


blocking ---> = (sequential)

non-blocking ---> <= (concurrent)

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-----------------------PPT 3-------------------- --------------SOME POST LAB QUESTIONS-----------

Design Implementation 1. What is a TCL script and why is it important in
1. Design your logic circuit a verilog project?
2. What is the funtion/s of assign statement in
2. Use logic synthesizer program to
verilog?
transform the HDL into a netlist 3. What are the types of conditional statements
3. Use implementation tools to map the in verilog?
logic gates and interconnections 4. What are the different bit-wise logic
4. Program extracts state of switches in operators in verilog?
the routing matrices and generates a 5. What should be modified in the sample code
bitstream if the blinking interval is set to 5 seconds?
6. Referring to the sample code in exercise 3, is
5. Bitstream is downloaded into physical
it possible to combine two “always” block in
FPGA chip one single block? If yes, what are the
necessary changes to be done? If not, what
Equipment: DE1 Starter Kit (D1SK) possible errors will occur?
Chip: EP2C20F484C7 7. What is the difference between the verilog
-Chip has 18,752 logic elements operators ~ (tilde) and !(exclamation point)?
-315 I/O lines 8. When should you use case statements instead
of if-else?
-240K RAM bits
9. Are default statements required in case
-26 embedded multipliers statements?
10. What is a switch bounce?
Hardware Specs: 11. Name at least one way to remedy switch
-3 internal oscillators (used in experiments is bounce.
clock with 50MHz freq) 12. Is the 7-segment display low or high enabled?
-10 toggle switches 13. What should be modified in the code if TCL
assignment of hex is interchanged such that
-4 button switches
MSB is to ‘g’ and LSB is to ‘a’?
-10 red LEDs 14. When do you use parameters in a verilog
-9 green LEDs code?
-4 7-segment hexadecimal displays 15. If the frequency of the oscillator used is
25MHz, how are you going to set the counting
interval to 0.5s?
16. How to set counting interval to 0.1s in D1SK?
17. Does the order of the sensitivity list matter? If

yes, how should they be arranged?
18. Differentiate blocking and non-blocking
statements.
19. Derive a verilog line that concatenates two
BCD inputs into one 8-bit port.

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