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input [7:0] a ;
input [2:0] arg ;
output [15:0] pprod ;
3'b010 :
if ((data < 0))
temp = {1'b1,data};
else
temp = {1'b0,data};
3'b011 :
if ((data < 0))
begin
temp1 = {1'b1,data};
temp = {temp1[7:0],1'b0};
end
else
temp = {{1'b0,data[6:0]},1'b0};
3'b100 :
if ((data < 0))
begin
temp1 = {1'b1,data};
temp2 = (~ (temp1) + 9'b000000001);
temp = {temp2[7:0],1'b0};
end
else
begin
temp1 = {1'b0,data};
temp2 = (~ (temp1) + 9'b000000001);
temp = {temp2[7:0],1'b0};
end
3'b101 :
if ((data < 0))
begin
temp1 = {1'b1,data};
temp = (~ (temp1) + 9'b000000001);
end
else
begin
temp1 = {1'b0,data};
temp = (~ (temp1) + 9'b000000001);
end
3'b110 :
if ((data < 0))
begin
temp1 = {1'b1,data};
temp = (~ (temp1) + 9'b000000001);
end
else
begin
temp1 = {1'b0,data};
temp = (~ (temp1) + 9'b000000001);
end
default :
temp = 9'b000000000;
endcase
begin
encoder__0=temp;
disable Function;
end
end
end // Function
endfunction
end // Function
endfunction
result[i] = tbl_binary[a[i]];
end
end //for
end //end Block
begin
make_binary__3=result;
disable Function;
end
end
end // Function
endfunction
endmodule
VHDL Code for Hybrid Adder:
input [7:0] a ;
input [2:0] arg ;
output [15:0] pprod ;
3'b010 :
if ((data < 0))
temp = {1'b1,data};
else
temp = {1'b0,data};
3'b011 :
if ((data < 0))
begin
temp1 = {1'b1,data};
temp = {temp1[7:0],1'b0};
end
else
temp = {{1'b0,data[6:0]},1'b0};
3'b100 :
if ((data < 0))
begin
temp1 = {1'b1,data};
temp2 = (~ (temp1) + 9'b000000001);
temp = {temp2[7:0],1'b0};
end
else
begin
temp1 = {1'b0,data};
temp2 = (~ (temp1) + 9'b000000001);
temp = {temp2[7:0],1'b0};
end
3'b101 :
if ((data < 0))
begin
temp1 = {1'b1,data};
temp = (~ (temp1) + 9'b000000001);
end
else
begin
temp1 = {1'b0,data};
temp = (~ (temp1) + 9'b000000001);
end
3'b110 :
if ((data < 0))
begin
temp1 = {1'b1,data};
temp = (~ (temp1) + 9'b000000001);
end
else
begin
temp1 = {1'b0,data};
temp = (~ (temp1) + 9'b000000001);
end
default :
temp = 9'b000000000;
endcase
begin
encoder__0=temp;
disable Function;
end
end
end // Function
endfunction
end // Function
endfunction
result[i] = tbl_binary[a[i]];
end
end //for
end //end Block
begin
make_binary__3=result;
disable Function;
end
end
end // Function
endfunction
endmodule
Verilog code for eightbit_fa :
input [7:0] a ;
input [7:0] b ;
input cin;
output [7:0] yout ;
output ovf;
wire [7:0] p;
wire [7:0] g;
wire [8:0] c;
wire [7:0] yout;
wire ovf;
assign {c[0]}=cin;
generate
begin :Block_Name_1
genvar i;
for (i=0;i<=7;i=i+1) begin :Block_Name_2
end//generate for
end//generate Block
endgenerate
assign {ovf}=c[8];
endmodule
Verilog Code for Radix-4 Booth Multiplier:
input [7:0] a ;
input [7:0] b ;
output [15:0] yout ;
assign {st}={b[1:0],1'b0};
assign {s1}={pp2[13:0],2'b00};
assign {s2}={pp3[11:0],4'b0000};
assign {s3}={pp4[9:0],6'b000000};
endmodule
VHDL Code for Radix-2 Booth Multiplier:
input [7:0] a ;
input [7:0] b ;
output [15:0] yout ;
assign {st}={b[0],1'b0};
assign {s1}={pp2[14:0],1'b0};
assign {s2}={pp3[13:0],2'b00};
assign {s3}={pp4[12:0],3'b000};
assign {s4}={pp5[11:0],4'b0000};
assign {s5}={pp6[10:0],5'b00000};
assign {s6}={pp7[9:0],6'b000000};
assign {s7}={pp8[8:0],7'b0000000};
endmodule