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Code for Booth Encoder:

module booth_encoder ( a, arg, pprod );

input [7:0] a ;
input [2:0] arg ;
output [15:0] pprod ;

wire [8:0] s1;


wire [15:0] pprod;

assign {s1}=encoder__0(arg, a);

assign {pprod}=sxt__1(s1, 16);

function [8:0] encoder__0;


input [2:0] arg1 ;
input [7:0] data ;
reg [8:0] temp;
reg [8:0] temp1;
reg [8:0] temp2;
reg sign;
begin : Function
begin
case (arg1)
3'b001 :
if ((data < 0))
temp = {1'b1,data};
else
temp = {1'b0,data};

3'b010 :
if ((data < 0))
temp = {1'b1,data};
else
temp = {1'b0,data};

3'b011 :
if ((data < 0))
begin
temp1 = {1'b1,data};
temp = {temp1[7:0],1'b0};
end
else
temp = {{1'b0,data[6:0]},1'b0};

3'b100 :
if ((data < 0))
begin
temp1 = {1'b1,data};
temp2 = (~ (temp1) + 9'b000000001);
temp = {temp2[7:0],1'b0};
end
else
begin
temp1 = {1'b0,data};
temp2 = (~ (temp1) + 9'b000000001);
temp = {temp2[7:0],1'b0};
end

3'b101 :
if ((data < 0))
begin
temp1 = {1'b1,data};
temp = (~ (temp1) + 9'b000000001);
end
else
begin
temp1 = {1'b0,data};
temp = (~ (temp1) + 9'b000000001);
end

3'b110 :
if ((data < 0))
begin
temp1 = {1'b1,data};
temp = (~ (temp1) + 9'b000000001);
end
else
begin
temp1 = {1'b0,data};
temp = (~ (temp1) + 9'b000000001);
end

default :
temp = 9'b000000000;
endcase
begin
encoder__0=temp;
disable Function;
end
end
end // Function
endfunction

function [(16 - 1):0] sxt__1;


input [8:0] arg;
input [31:0] size ;
parameter msb = (min__2((8-0+1), 16) - 1);//constant
reg [((8-0+1) - 1):0] new_bounds;
reg [(16 - 1):0] result;
begin : Function
begin
new_bounds = make_binary__3(arg);
if ((new_bounds[0] == 1'bx))
begin
result = {((size - 1)-0+1- 0){1'bx}};
begin
sxt__1=result;
disable Function;
end
end

result = {((size - 1)-0+1- 0){new_bounds[((8-0+1) - 1)]}};


result[msb:0] = new_bounds[msb:0];
begin
sxt__1=result;
disable Function;
end
end
end // Function
endfunction

function [31:0] min__2;


input [31:0] l ;
input [31:0] r ;
begin : Function
if ((l < r))
begin
min__2=l;
disable Function;
end
else
begin
min__2=r;
disable Function;
end

end // Function
endfunction

function [8:0] make_binary__3;


input [8:0] a;
reg [3:0] one_bit;
reg [8:0] result;
begin : Function
begin
begin :Block_Name_1
integer i;
for (i=8;i>=0;i=i-1) begin
begin
if (is_x[a[i]])
begin
begin
if (!(1'b0) ) $display(" There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the
result will be 'X'(es). time=%d",$time);
end
result = {(8-0+1- 0){1'bx}};
begin
make_binary__3=result;
disable Function;
end
end

result[i] = tbl_binary[a[i]];
end

end //for
end //end Block
begin
make_binary__3=result;
disable Function;
end
end
end // Function
endfunction

endmodule
VHDL Code for Hybrid Adder:

module booth_encoder ( a, arg, pprod );

input [7:0] a ;
input [2:0] arg ;
output [15:0] pprod ;

wire [8:0] s1;


wire [15:0] pprod;

assign {s1}=encoder__0(arg, a);

assign {pprod}=sxt__1(s1, 16);

function [8:0] encoder__0;


input [2:0] arg1 ;
input [7:0] data ;
reg [8:0] temp;
reg [8:0] temp1;
reg [8:0] temp2;
reg sign;
begin : Function
begin
case (arg1)
3'b001 :
if ((data < 0))
temp = {1'b1,data};
else
temp = {1'b0,data};

3'b010 :
if ((data < 0))
temp = {1'b1,data};
else
temp = {1'b0,data};

3'b011 :
if ((data < 0))
begin
temp1 = {1'b1,data};
temp = {temp1[7:0],1'b0};
end
else
temp = {{1'b0,data[6:0]},1'b0};

3'b100 :
if ((data < 0))
begin
temp1 = {1'b1,data};
temp2 = (~ (temp1) + 9'b000000001);
temp = {temp2[7:0],1'b0};
end
else
begin
temp1 = {1'b0,data};
temp2 = (~ (temp1) + 9'b000000001);
temp = {temp2[7:0],1'b0};
end

3'b101 :
if ((data < 0))
begin
temp1 = {1'b1,data};
temp = (~ (temp1) + 9'b000000001);
end
else
begin
temp1 = {1'b0,data};
temp = (~ (temp1) + 9'b000000001);
end

3'b110 :
if ((data < 0))
begin
temp1 = {1'b1,data};
temp = (~ (temp1) + 9'b000000001);
end
else
begin
temp1 = {1'b0,data};
temp = (~ (temp1) + 9'b000000001);
end

default :
temp = 9'b000000000;
endcase
begin
encoder__0=temp;
disable Function;
end
end
end // Function
endfunction

function [(16 - 1):0] sxt__1;


input [8:0] arg;
input [31:0] size ;
parameter msb = (min__2((8-0+1), 16) - 1);//constant
reg [((8-0+1) - 1):0] new_bounds;
reg [(16 - 1):0] result;
begin : Function
begin
new_bounds = make_binary__3(arg);
if ((new_bounds[0] == 1'bx))
begin
result = {((size - 1)-0+1- 0){1'bx}};
begin
sxt__1=result;
disable Function;
end
end

result = {((size - 1)-0+1- 0){new_bounds[((8-0+1) - 1)]}};


result[msb:0] = new_bounds[msb:0];
begin
sxt__1=result;
disable Function;
end
end
end // Function
endfunction

function [31:0] min__2;


input [31:0] l ;
input [31:0] r ;
begin : Function
if ((l < r))
begin
min__2=l;
disable Function;
end
else
begin
min__2=r;
disable Function;
end

end // Function
endfunction

function [8:0] make_binary__3;


input [8:0] a;
reg [3:0] one_bit;
reg [8:0] result;
begin : Function
begin
begin :Block_Name_1
integer i;
for (i=8;i>=0;i=i-1) begin
begin
if (is_x[a[i]])
begin
begin
if (!(1'b0) ) $display(" There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the
result will be 'X'(es). time=%d",$time);
end
result = {(8-0+1- 0){1'bx}};
begin
make_binary__3=result;
disable Function;
end
end

result[i] = tbl_binary[a[i]];
end

end //for
end //end Block
begin
make_binary__3=result;
disable Function;
end
end
end // Function
endfunction

endmodule
Verilog code for eightbit_fa :

module eightbit_fa ( a, b, cin, yout, ovf );

input [7:0] a ;
input [7:0] b ;
input cin;
output [7:0] yout ;
output ovf;

wire [7:0] p;
wire [7:0] g;
wire [8:0] c;
wire [7:0] yout;
wire ovf;

assign {c[0]}=cin;

generate
begin :Block_Name_1
genvar i;
for (i=0;i<=7;i=i+1) begin :Block_Name_2

assign {p[i]}=(a[i] ^ b[i]);

assign {g[i]}=(a[i] & b[i]);

assign {yout[i]}=(p[i] ^ c[i]);

assign {c[(i + 1)]}=(g[i] | (p[i] & c[i]));

end//generate for
end//generate Block
endgenerate

assign {ovf}=c[8];

endmodule
Verilog Code for Radix-4 Booth Multiplier:

module booth4_hybridadder ( a, b, yout );

input [7:0] a ;
input [7:0] b ;
output [15:0] yout ;

wire [15:0] pp1;


wire [15:0] pp2;
wire [15:0] pp3;
wire [15:0] pp4;
wire [15:0] s1;
wire [15:0] s2;
wire [15:0] s3;
wire [15:0] sum1;
wire [15:0] sum2;
wire [2:0] st;
wire k1;
wire k2;
wire k3;
wire [15:0] yout;

assign {st}={b[1:0],1'b0};

booth_encoder uo(.a(a), .arg(st), .pprod(pp1));

booth_encoder u1(.a(a), .arg(b[3:1]), .pprod(pp2));

booth_encoder u2(.a(a), .arg(b[5:3]), .pprod(pp3));

booth_encoder u3(.a(a), .arg(b[7:5]), .pprod(pp4));

assign {s1}={pp2[13:0],2'b00};

assign {s2}={pp3[11:0],4'b0000};

assign {s3}={pp4[9:0],6'b000000};

hybrid_adder1 u4(.a(pp1), .b(s1), .yout(sum1), .ovf(k1));

hybrid_adder1 u5(.a(s2), .b(s3), .yout(sum2), .ovf(k2));

hybrid_adder1 u6(.a(sum1), .b(sum2), .yout(yout), .ovf(k3));

endmodule
VHDL Code for Radix-2 Booth Multiplier:

module booth2_hybridadder ( a, b, yout );

input [7:0] a ;
input [7:0] b ;
output [15:0] yout ;

wire [15:0] pp1;


wire [15:0] pp2;
wire [15:0] pp3;
wire [15:0] pp4;
wire [15:0] pp5;
wire [15:0] pp6;
wire [15:0] pp7;
wire [15:0] pp8;
wire [15:0] s1;
wire [15:0] s2;
wire [15:0] s3;
wire [15:0] s4;
wire [15:0] s5;
wire [15:0] s6;
wire [15:0] s7;
wire [15:0] sum1;
wire [15:0] sum2;
wire [15:0] sum3;
wire [15:0] sum4;
wire [15:0] sum5;
wire [15:0] sum6;
wire [1:0] st;
wire k1;
wire k2;
wire k3;
wire k4;
wire k5;
wire k6;
wire k7;
wire [15:0] yout;

assign {st}={b[0],1'b0};

booth_encoder uo(.a(a), .arg(st), .pprod(pp1));

booth_encoder u1(.a(a), .arg(b[1:0]), .pprod(pp2));

booth_encoder u2(.a(a), .arg(b[2:1]), .pprod(pp3));


booth_encoder u3(.a(a), .arg(b[3:2]), .pprod(pp4));

booth_encoder u4(.a(a), .arg(b[4:3]), .pprod(pp5));

booth_encoder u5(.a(a), .arg(b[5:4]), .pprod(pp6));

booth_encoder u6(.a(a), .arg(b[6:5]), .pprod(pp7));

booth_encoder u7(.a(a), .arg(b[7:6]), .pprod(pp8));

assign {s1}={pp2[14:0],1'b0};

assign {s2}={pp3[13:0],2'b00};

assign {s3}={pp4[12:0],3'b000};

assign {s4}={pp5[11:0],4'b0000};

assign {s5}={pp6[10:0],5'b00000};

assign {s6}={pp7[9:0],6'b000000};

assign {s7}={pp8[8:0],7'b0000000};

hybrid_adder1 u8(.a(pp1), .b(s1), .yout(sum1), .ovf(k1));

hybrid_adder1 u9(.a(sum1), .b(s2), .yout(sum2), .ovf(k2));

hybrid_adder1 u10(.a(sum2), .b(s3), .yout(sum3), .ovf(k3));

hybrid_adder1 u11(.a(sum3), .b(s4), .yout(sum4), .ovf(k4));

hybrid_adder1 u12(.a(sum4), .b(s5), .yout(sum5), .ovf(k5));

hybrid_adder1 u13(.a(sum5), .b(s6), .yout(sum6), .ovf(k6));

hybrid_adder1 u14(.a(sum6), .b(s7), .yout(yout), .ovf(k7));

endmodule

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