1936
4, APRIL 2012
A Single-Inductor Multiple-Output Switcher With
Simultaneous Buck, Boost, and Inverted Outputs
Pradipta Patra, Amit Patra, Member, IEEE, and Neeraj Misra
Abstract—Portable applications require multiple supplies with
different output levels and some applications also require neg-
ative outputs. Single-inductor multiple-output (SIMO) switchers
are a good for existing parallel output configurations. This study
presents an SIMO dc–dc converter capable of generating buck,
boost, and inverted outputs simultaneously. The operation of this
class of converter being driven by the ripple in the inductor cur-
rent the conventional averaging method does not work well. An
inductor current ripple-based modeling approach has been pro-
posed to accurately model and analyze the converter. The control,
cross-coupling, and cross-regulation transfer functions, generated
through the model, accurately represent the performance of the
converter. The proof of concept has been carried out with discrete
components on an in-house built PCB and the experimental results
validating the steady state and ac responses of the converter are
presented.
Index Terms—Buck–boost-inverted outputs, cross-regulation,
dc–dc converter modeling, single-inductor multiple-output
(SIMO), switching converter.
I. INTRODUCTION
ORTABLE devices commonly composed of a variety of
P submodules can provide several functions, such as LED
backlight, liquid crystal display (LCD) monitor, and several
signal-processing utilities. Applications may require step-down,
step-up, or at times even a bipolar supply (e.g., in flat panel LED
displays) from the same battery supply. Bipolar supplies also
find a wide range of application in organic light emitting diodes
(OLEDs) [1]–[5]. As a result, the design of a power management
IC typically comprises boost to step-up, buck to step-down,
buck-boost to generate negative supply, and linear regulators to
meet different supplies for various circuit applications [6]–[10].
The most popular solution of late, among those proposed
in the literature, addresses SIMO dc–dc converters based on
buck- and boost-derived topologies [11]–[13]. Quite a number
of studies on SIMO switching converters have been reported in
the literature over the last decade which are capable of gener-
Manuscript received April 19, 2011; revised June 24, 2011 and August 17,
2011; accepted August 30, 2011. Date of current version February 20, 2012.
This work was supported by Advanced VLSI Consortium. Recommended for
publication by Associate Editor C. K. Tse.
P. Patra is with Intel Technology India Pvt. Ltd. Bangalore 560 017, India
(e-mail: pradiptapatra@gmail.com).
A. Patra and N. Misra are with the Department of Electrical Engineering,
Indian Institute of Technology, Kharagpur, West Bengal 721302, India (e-mail:
amit.patra@ieee.org; 19neeraj89@gmail.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2011.2169813
0885-8993/$26.00 © 2011 IEEE
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO.
ating buck and/or boost outputs simultaneously [14]–[18] have
been reported in the literature. However, very few works present
an SIMO architecture that is capable of delivering an inverted
output along with positive buck and boost outputs. Some re-
cent reports in the literature show simultaneous buck and boost
output operation. As in the case of generation of inverted out-
put from a dc supply, traditionally, buck–boost topology has
been used. In SIMO configuration, only a couple of works have
been reported in the literature which generate negative outputs
along with a boost output but the negative output is not indepen-
dently controlled and the output level is defined by the positive
boost output [4], [5]. However, no topology generates indepen-
dently controlled negative and positive outputs simultaneously
in multiple-output configurations with a wide range of the out-
put voltages. Thus, a topology capable of delivering multiple
outputs, each with any level of voltage (positive/negative step-
up/step-down), using a single inductor from a single supply is
of interest.
This study proposes an SIMO topology capable of generating
independently controlled buck, boost, and inverted (buck/boost)
outputs simultaneously. Conventional modeling techniques do
not work well for this class of converters as the operation is
defined by the ripple in the inductor current [6], [19]–[31]. Con-
sequently, an inductor current ripple-based modeling technique
has been proposed for this class of converters which can ac-
curately analyze the steady-state and dynamic performance for
these converters. This modeling can accurately predict the pos-
sible operating range for different outputs and also the cross-
coupling and cross-regulation factors (a significant challenge
in the design of SIMO converters) among the different outputs.
With the information made available through this modeling tech-
nique, it would be possible to address and design a controller for
SIMO systems which can make the system stable with subse-
quent reduction and probable elimination of the cross-regulation
factors among the outputs.
Section II presents the topology to generate buck, boost, and
inverted outputs simultaneously and discusses its operation. The
inductor current scheme that drives the generation of different
types of outputs is illustrated. An inductor current ripple-based
modeling technique is used to model this converter and the mod-
eling is presented in Section III. The feasible operating range
and the voltage levels that can be achieved using this topology
for a set of parameters are presented in Section IV. In Section V,
simulation and experimental results that validate the concept of
generating buck, boost, and inverted outputs simultaneously are
put forth. The accuracy of the model is proven by a compara-
tive study of modeling, simulation, and experimental data (see
Section V-C). Section VI concludes this study.
PATRA et al.: SINGLE-INDUCTOR MULTIPLE-OUTPUT SWITCHER WITH SIMULTANEOUS BUCK, BOOST, AND INVERTED OUTPUTS
Fig. 1. Proposed SIBBI converter topology.
II. A SINGLE-INDUCTOR TRIPLE-OUTPUT DC–DC
CONVERTER WITH BUCK, BOOST, AND INVERTED
OUTPUTS—OPERATING PRINCIPLE
The proposed topology discussed here is a single-inductor
buck, boost, and inverted (SIBBI) output dc–dc converter (see
Fig. 1) that can simultaneously generate buck, boost, and in-
verted outputs. To elaborate the proposed scheme, a converter
topology is presented here with a single input (Vin ) and three
outputs of which one is boost (V1 ), one is buck (V3 ), and one
is inverted (V2 ). C1 , C2 , and C3 are the output capacitors to
the outputs V1 , V2 , and V3 , respectively, whereas R1 , R2 , and
R3 define the loads at the corresponding output nodes. Worth
noting, this topology can be extended to generate “n” outputs
and each can be subjected to deliver any output from among
buck, boost, or inverted on the condition that at least one of the
outputs is a boost. In the proposed configuration, the voltage
levels of all three outputs can be adjusted by varying the duty
cycles of switches S0 , S1 , S2 , and S3 . Sf is a freewheel switch
and can be used only for dynamic operation. Its use can give
a degree of freedom but it would restrict the zone of operation
to some extent. So, for the present scope, we will not consider
using it and the remainder of this paper will not accomodate it.
The timing diagram (see Fig. 2) describes the operation of
the converter to generate the desired outputs. The inductor is
charged through switch S0 as in Fig. 1 during d0 Ts . Once S0
is turned OFF, S1 turns ON for the time d1 Ts to supply the
mandatory boost output. S2 turns ON for the next d2 Ts time
to drive the inverted output. Finally, the buck output is driven
in the last part of the switching cycle, d3 Ts through switch S3 .
The inductor current waveform iL and the voltage across the
1937
Fig. 2. Timing diagram and inductor current waveform for a three-output
SIBBI converter.
inductor VL are also plotted. It should be noted that a different
timing sequence or a different switching sequence will result in
a different output configuration. Let us assume V1 to be boost,
V2 to be inverted, and V3 to be buck. The switching action for
all the states in one switching cycle will be referred to as a
“Mode” of operation. To start off, initially the inductor needs
to be charged and so let this condition be termed as Mode 1
where the inductor current rises from “m” to “n.” Boost output,
being greater than the supply voltage, makes the inductor current
fall (“n” to “p”) and if this is allowed for a short duration of
time (D2 Ts ), then, to maintain the output, the current has to
fall sharply by a large value. If the inductor current is forced to
turn negative, it forces generation of an inverted output. Thus,
Mode 2 is dedicated to the boost output V1 . Since the inductor
current turns negative in Mode 2, Mode 3 can be configured
to generate inverted output, V2 . The inductor, having a positive
voltage drop across it, has to rise (from “p” to “q”), but the
negative energy in it drives the output to be inverted. The value
of the output would be decided by the duty cycle in this mode
(D2 Ts ) and the slope at which the inductor current is made to
rise (from “q” to “m”). By the end of Mode 3, the state for
driving the inverted output, the inductor current turns positive,
and the final state can be used to deliver a buck output, V3 the
level again being defined by its corresponding duty cycle, D2 Ts .
Finally, at the end of the switching cycle Ts , the inductor current
reaches the initial value “m.” Driving the buck output makes
the voltage across the inductor positive, and thus, the inductor
current has to rise to reach its initial level, in the process driving
its output node capacitor. It may be noted that the sequence
of operation mentioned here is one specific example in which
all three types of outputs, as discussed, can be generated. The
switching sequence can be easily reordered to generate different
1938 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 4, APRIL 2012

levels of voltages at the outputs but the inductor current has to (vin − v2 )d2 Ts
go below zero (turn negative) to generate the inverted output. q =p+
L
vin d0 Ts (vin − v1 )d1 Ts (vin − v2 )d2 Ts
III. INDUCTOR CURRENT RIPPLE-BASED STATE SPACE =m+ + + . (7)
L L L
AVERAGED SMALL-SIGNAL MODELING OF SIBBI
The inductor current averaged over the entire switching cycle
The conventional state space averaging technique used to can be represented as
model single output buck and boost converter does not work
m+n p+n p+q
well for this class of SIMO converters, as the ripple in the in- īL = d0 + d1 + d2
ductor cannot be ignored. Here, the ripple information is the 2 2 2
driving factor to analyze the operation in SIMO. Consequently, q+m
+ (1 − d0 − d1 − d2 ). (8)
an inductor current ripple-based averaging method for model- 2
ing has been proposed in this section. Unlike conventional state On simplification,
space, the steady-state solutions obtained through this technique
vin Ts v1 T s
bring out the dependences of the output voltages on the vari- m = īL − (d0 + d1 + d2 )(1 − d2 ) + d1 (1 − d0 )
ous system parameters, e.g., the inductor, the output loads, and L L
the switching frequency. For simplicity, we assume that all de- v2 T s
+ (1 − d0 )(1 − d0 − d1 − d2 ). (9)
vices are ideal. The different modes in the steady-state inductor L
current in one switching cycle are illustrated in Fig. 2. Each
such state corresponds to a mode of operation of SIBBI. As dis- A. State Space Equations
cussed, “m” is the initial value of the inductor current; during The average inductor current (iL ) and output capacitor volt-
energizing period, it rises to a peak value “n.” The first slot for ages (v1 , v2 , and v3 ) are considered to be the state variables of
de-energizing is designated for the boost output and the induc- the system. The duty cycles (d0 , d1 , and d2 ) are the indepen-
tor current falls to a low “p” at the end of Mode 2. In Mode dent control variables and disturbances are observed at the input
3, the current is used to drive the inverted output and reaches voltage (vin ) and at the output loads (i1 , i2 , and i3 ). Based on
a peak “q.” In the final mode, the inductor current reaches its the aforementioned nomenclature, the state space equations to
initial value “m.” Conventional state space averaging method the system for all the modes are defined in the following.
averages the inductor current over the entire switching period, Mode 1: In this mode, S0 turns ON and S1 , S2 , and S3 remain
and hence, the ripple information is lost. The proposed approach OFF as illustrated in the timing diagram in Fig. 2. The circuit
averages the inductor current for every mode of a switching cy- is illustrated in Fig. 3. The corresponding differential equations
cle, which can be depicted as (m + n)/2, (n + p)/2, (p + q)/2, for all the state variables (iL , v1 , v2 , v3 ) can be written as
and (q + m)/2, respectively. Thus, the shift in the level of the
diL diL vin
inductor current for each mode can be represented as follows. vin = L → = (10)
dt dt L
Mode 1: 0 < t < d0 Ts
dv1 v1 i1
vin d0 Ts =− − (11)
n−m= . (1) dt R1 C1 C1
L
dv2 v2 i2
Mode 2: d0 T < t < (d0 + d1 )Ts =− − (12)
dt R2 C2 C2
(vin − v1 )d1 Ts dv3 v3 i3
p−n= . (2) =− − . (13)
L dt R3 C3 C3
Mode 3: (d0 + d1 )Ts < t < (d0 + d1 + d2 )Ts Thus, the state space representation becomes
(vin − v2 )d2 Ts ⎡ ⎤
q−p= . (3) 0 0 0 0
L ⎡ ⎤ ⎢ 1 ⎥⎡ ⎤
i̇L ⎢0 − 0 0 ⎥ iL
Mode 4: (d0 + d1 + d2 )Ts < t < (d0 + d1 + d2 + d3 )Ts , ⎢ R1 C1 ⎥
⎢ v̇1 ⎥ ⎢ ⎥ ⎢ v1 ⎥
where d0 + d1 + d2 + d3 = 1 ⎣ ⎦=⎢ 1 ⎥⎣ ⎦
v̇2 ⎢0 0 − 0 ⎥ v2
⎢ R2 C2 ⎥
(vin − v3 )(1 − d0 − d1 − d2 )Ts v̇3 ⎣ 1 ⎦ 3
v
m−q = . (4) 0 0 0 −
L R3 C3
Each of the levels can be simplified to ⎡1 ⎤
0 0 0
⎢L ⎥⎡
vin d0 Ts ⎢ ⎥ vin ⎤
n=m+ (5) ⎢0 − 1 0 0 ⎥
L ⎢ C1 ⎥ ⎢ i1 ⎥
(vin − v1 )d1 Ts +⎢ ⎢ 1
⎥⎣
⎥ ⎦. (14)
p=n+ ⎢0 0 − 0 ⎥ i2
L ⎢ C2 ⎥ i3
⎣ 1 ⎦
vin d0 Ts (vin − v1 )d1 Ts 0 0 0 −
=m+ + (6) C3
L L
PATRA et al.: SINGLE-INDUCTOR MULTIPLE-OUTPUT SWITCHER WITH SIMULTANEOUS BUCK, BOOST, AND INVERTED OUTPUTS 1939

Fig. 3. Mode 1 of operation for SIBBI.

Fig. 4. Mode 2 of operation for SIBBI.

Mode 2: In this mode, the inductor starts its de-energizing

through the boost output (v1 ) through S1 . Consequently, S1
turns ON and S0 , S2 , and S3 remain OFF as explained in the
timing diagram in Fig. 2. The circuit is illustrated in Fig. 4. The
corresponding differential equations for all the state variables
(iL , v1 , v2 , v3 ) can be written as

diL diL vin − v1

vin = L + v1 → = (15)
dt dt L
dv1 n+p v1 i1
=− − − (16)
dt 2C1 R1 C1 C1
dv2 v2 i2
=− − (17)
dt R2 C2 C2
dv3 v3 i3 Fig. 5. Mode 3 of operation for SIBBI.
=− − . (18)
dt R3 C3 C3
n +p
Substituting the value of 2 , the state space representation
becomes
⎡ ⎤
i̇L
⎢ v̇1 ⎥
⎣ ⎦
v̇2
v̇3
⎡0 0 0 0 ⎤
⎢0 − L1 0 0 ⎥
⎢ 1 d 1 −d 1 d 0 ) T (d 2 d 1 +d 2 d 0 −d 2 )⎥
=⎢
⎢ C1 − R1 C1
1
+ T (d 22L C1 0 2L C 1
⎥
⎥
⎣0 0 − R 21C 2 0 ⎦
0 0 0 − R 31C 3
⎡ ⎤
iL
Fig. 6. Mode 4 of operation for SIBBI.
⎢ v1 ⎥
×⎣ ⎦
v2
v3 Mode 3: The inductor starts discharging through the negative
⎡ ⎤
1
0 0 0 ⎡ ⎤ output (v2 ) through S2 . S2 turns ON and S0 , S1 , and S3 remain
L v
⎢ T (d 0 −d 20 −2d 2 d 0 −2d 1 d 0 +d 2 ) ⎥ in OFF as explained in the timing diagram in Fig. 2. The circuit
⎢ − C11 0 0 ⎥ ⎢ i1 ⎥
+⎢ 2L C 1 ⎥ ⎣ ⎦. is illustrated in Fig. 5. The corresponding differential equations
⎣ 0 0 − C12 0 ⎦ i2 for all the state variables (iL , v1 , v2 , v3 ) can be written as
0 0 0 − C13 i3
diL diL vin − v2
(19) vin = L + v2 → = (20)
dt dt L
1940 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 4, APRIL 2012

dv1 v1 i1 B. Averaged Model of the Converter

=− − (21)
dt R1 C1 C1 The four modes of operation of the converter have already
dv2 p+q v2 i2 been illustrated and (14), (19), (24), and (29) correspond to
=− − − (22)
dt 2C1 R2 C2 C2 Modes 1–4, respectively. Thus, the converter switches among
dv3 v3 i3 four modes in one cycle. Averaging the converter dynamics
=− − . (23) over an entire switching cycle, the averaged representation of
dt R3 C3 C3
the system is
p+q
Substituting the value of 2 , the state space representation
becomes ẋ = ax + bu (30)

⎡ ⎤ where a = a0 d0 + a1 d1 + a2 d2 + a3 (1 − d0 − d1 − d2 ) and
i̇L
⎢ v̇1 ⎥ b = b0 d0 + b1 d1 + b2 d2 + b3 (1 − d0 − d1 − d2 ) (since d0 +
⎣ ⎦ d1 + d2 + d3 = 1 → d3 = 1 − d0 − d1 − d2 ) and, as shown in
v̇2
v̇3 (31)–(35) at the bottom of the next page.
⎡ ⎤ 1) Steady-State Solution: In steady state, ẋ = 0. Thus, the
0 0 − L1 0
steady-state solution becomes
⎢0 − R1 C1
1
0 0 ⎥
=⎢⎣ 1 − T (d 1 +d 0 d 1 −d 1 d 2 ) − 1 − T (d 2 d 0 +d 1 d 2 )
⎥
0 ⎦
C2 2L C 2 R2 C2 2L C 2 X = A−1 BU (36)
0 0 0 − R 31C 3
⎡ ⎤ ⎡ 1
0 0 0 ⎤ ⎡ vin ⎤ with X, U , A, and B defined as follows where A = A0 D0 +
iL L
⎢v ⎥ ⎢ 0 − C1
1
0 0 ⎥ ⎢ i1 ⎥ A1 D1 + A2 D2 + A3 (1 − D0 − D1 − D2 ) and B = B0 D0 +
×⎣ 1⎦+⎢ ⎣ T (d 0 −d 20 −d 1 )
⎥⎣
⎦ i2 ⎦ . B1 D1 + B2 D2 + B3 (1 − D0 − D1 − D2 ) and, as shown in
v2 2L C 2 0 − C2
1
0
v3 i3 (37)–(40) at the bottom of the next page. The steady-state so-
0 0 0 − 1 C3 lutions for IL , V1 , V2 , and V3 can, thus, be obtained from (36)
(24) for the corresponding duty cycles of D0 , D1 , and D2 and all
the other parameters of the system, inductor L, switching time
Mode 4: The inductor discharges through the buck output cycle Ts , and the load resistances at the output terminals (R1 ,
(v3 ) through S3 . S3 turns ON and S1 , S2 , and S3 remain OFF R2 , and R3 , respectively).
as explained in the timing diagram in Fig. 2. The circuit is 2) Small-Signal Perturbation and Linearization: The
illustrated in Fig. 6. The corresponding differential equations steady-state representation of the system given by (36) is non-
for all the state variables (iL , v1 , v2 , v3 ) can be written as linear since the matrices are functions of the duty cycles di .
Therefore, it is necessary to linearize the system equations. Such
diL diL vin − v3
vin = L + v3 → = (25) a linearized model helps define the different transfer functions.
dt dt L The dynamic equations for the converter can be expanded to
dv1 v1 i1
=− − (26) ẋ = (a0 d0 + a1 d1 + +a2 d2 + a3 (1 − d0 − d1 − d2 ))x
dt R1 C1 C1
dv2 v2 i2 + (b0 d0 + b1 d1 + b2 d2 + b3 (1 − d0 − d1 − d2 ))u. (41)
=− − (27)
dt R2 C2 C2
Now consider the inputs to the system, d0 , d1 , d2 , and u to be
dv3 q+m v3 i3
=− − − . (28) varying around their quiescent operating points D0 , D1 , D2 ,
dt 2C1 R3 C3 C3 and U , respectively. Thus, the system variables can be repre-
sented as (vin = Vin + v̂in ), (v1 = V1 + v̂1 ), (v2 = V2 + v̂2 ),
Substituting the value of q +m 2 , the state space representation (iL = IL + îL ), (i1 = I1 + î1 ), (i2 = I2 + î2 ), (d0 = D0 +
becomes dˆ0 ), (d1 = D1 + dˆ1 ), and (d2 = D2 + dˆ2 ). These time-varying
⎡ ⎤ ⎡ 0 0 0 − L1
⎤ inputs produce perturbations in the dynamic variables x =
i̇L X + x̂. Thus, the system can be perturbed and represented as
⎢ v̇1 ⎥ ⎢ 0 − R1 C1 1
0 0 ⎥
⎣ ⎦=⎣ 0 ⎢ ⎥
v̇2 0 − R 21C 2 0 ⎦
T (d 2 d 1 −d 1 d 0 )
Ẋ + x̂˙ = [a0 (D0 + dˆ0 ) + a1 (D1 + dˆ1 ) + a2 (D2 + dˆ2 )
v̇3 1
− T (d 0 d 2 +d 1 d 2 )
− 1
C3 2L C 3 2L C 3 R3 C3
+ a3 ((1 − D0 − D1 − D2 ) − (dˆ0 + dˆ1 + dˆ2 ))]
⎡ ⎤ ⎡ 1 0 0 0 ⎤⎡ ⎤
iL L vin
⎢ v1 ⎥ ⎢ 0 − C11 0 0 ⎥ ⎢ i1 ⎥ × (X + x̂) + [b0 (D0 + dˆ0 ) + b1 (D1 + dˆ1 ) + b2 (D2 + dˆ2 )
× ⎣ ⎦+⎢ ⎣ 0 0 − C2 1 ⎥⎣
0 ⎦ i2 ⎦ .
v2 + b3 ((1 − D0 − D1 − D2 ) − (dˆ0 + dˆ1 + dˆ2 ))](U + û).
2
v3 T
− 2L C 3
d 1
0 0 − C3
1 i3
(42)
(29)
PATRA et al.: SINGLE-INDUCTOR MULTIPLE-OUTPUT SWITCHER WITH SIMULTANEOUS BUCK, BOOST, AND INVERTED OUTPUTS 1941

As evident from (32)–(35), the state matrices ai , bi are functions where

of duty ratio (d0 , d1 , and d2 ) in the ripple space analysis. For
the ac analysis, the steady-state terms are removed from the ⎡ ⎤ ⎡ ⎤
îL v̂in
perturbed equation, and only the linear small-signal terms and x̂ = ⎣ v̂1 ⎦ , û = ⎣ î1 ⎦ (44)
nonlinear terms are considered. The higher order perturbation v̂2 î2
terms are neglected since they are very small. The linear model
can, thus, get transformed to â0 = 0
or â0 = A00 dˆ0 + A01 dˆ1 + A02 dˆ2 (45)

where A00 = A01 = A02 = 0

x̂˙ = [(A0 dˆ0 + â0 D0 ) + (A1 dˆ1 + â1 D1 ) + (A2 dˆ2 + â2 D2 )
⎡ ⎤
+ (A3 (−dˆ0 − dˆ1 − dˆ2 ) + â3 (1 − D0 − D1 − D2 ))]X 0 0 0 0
⎢ 0 − 2L
Ts D1
0 Ts D2
⎥ˆ
+ [A0 D0 + A1 D1 + A2 D2 + A3 (1 − D0 − D1 − D2 )]x̂ â1 = ⎣ C1 2L C 1 ⎦ d0
0 0 0 0
0 0 0
+ [(B0 dˆ0 + b̂0 D0 ) + (B1 dˆ1 + b̂1 D1 ) + (B2 dˆ2 + b̂2 D2 )
⎡ ⎤
0 0 0 0
+ (B3 (−dˆ0 − dˆ1 − dˆ2 ) + B̂3 (1 − D0 − D1 − D2 ))]U T s (D 2 −D 1 ) Ts D2
⎢0 0 ⎥ˆ
+⎣ 2L C 1 2L C 1 ⎦ d1
0 0 0 0
+ [B1 D0 + B2 D1 + B3 (1 − D0 − D1 )]û (43) 0 0 0 0

⎡ ⎤ ⎡ ⎤
iL vin
⎢v ⎥ ⎢ i ⎥
x = ⎣ 1 ⎦, u = ⎣ 1 ⎦ (31)
v2 i2
v3 i3
⎡ ⎤
0 0 0 0
⎢ 0 − R 1C 0 0 ⎥
a0 = ⎢
⎣0
1 1 ⎥
⎦
0 − R2 C2
1
0
0 0 0 − R 31C 3
⎡1 ⎤
L 0 0 0
⎢ 0 −C 1
0 0 ⎥
b0 = ⎢
⎣0
1 ⎥ (32)
0 − C2
1
0 ⎦
0 0 0 − C13
⎡ 0 0 0 0 ⎤
⎢ 0 − L1 0 0 ⎥
⎢ 1 T s (d 2 d 1 −d 1 d 0 ) T s (d 2 d 1 +d 2 d 0 −d 2 ) ⎥
a1 = ⎢
⎢ C1 − R 11C 1 + 2L C 1 0 2L C 1
⎥
⎥
⎣ 0 0 − R 21C 2 0 ⎦
0 0 0 − R 31C 3
⎡ 1 ⎤
L 0 0 0
⎢ T s (d 0 −d 20 −2d 2 d 0 −2d 1 d 0 +d 2 ) ⎥
⎢ − C11 0 0 ⎥
b1 = ⎢ 2L C 1 ⎥ (33)
⎣ 0 0 − C12 0 ⎦
0 0 0 − C13
⎡ ⎤ ⎡ 0 ⎤
0 0 − L1 0 1
L 0 0
⎢ 0 − R 11C 1 0 0 ⎥ ⎢ 0 − C11 0 0 ⎥
a2 = ⎢
⎣ 1
⎥,
⎦ b2 = ⎢
⎣ T s (d 0 −d 20 −d 1 )
⎥ (34)
0 ⎦
T s (d 1 +d 0 d 1 −d 1 d 2 ) T s (d 2 d 0 +d 1 d 2 )
C2 − 2L C 2 − R 21C 2 − 2L C 2 0 2L C 2 0 − C12
0 0 0 − R 31C 3 0 0 0 − C13
⎡ ⎤ ⎡ ⎤
0 0 0 − L1 1
L 0 0 0
⎢ 0 − R 11C 1 0 0 ⎥ ⎢ 0 − C11 0 0 ⎥
a3 = ⎢
⎣ 0
⎥,
⎦ b3 = ⎢
⎣ − C12
⎥
0 ⎦. (35)
0 − R 21C 2 0 0 0
T s (d 2 d 1 −d 1 d 0 ) d 21
1
C3 2L C 3 − T s (d 02L
d 2 +d 1 d 2 )
C3 − R 31C 3 T
− 2L C 3 0 0 − C13
1942 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 4, APRIL 2012

⎡ ⎤ ⎡ ⎤
0 0 0 0 0 0 0 0
Ts D1 T s (D 0 +D 1 −1)
⎢0 0 ⎥ˆ ⎢0 0 0 0 ⎥ˆ
+⎣ 2L C 1 2L C 1 ⎦ d2 +⎣ ⎦ d1
0 0 0 0 0 0 0 0
0 −D 2 )
0 0 0 0 0 − T s (D
2L C 3 0 2L Ts D2
C3
⎡ ⎤
or â1 = A10 dˆ0 + A11 dˆ1 + A12 dˆ2 (46) 0 0 0 0
⎡ ⎤ ⎢0 0 0 0 ⎥ˆ
s0 0 0 0 +⎣ ⎦ d2
0 0 0 0
⎢ 0 0 0 0 ⎥ˆ
â2 = ⎣ T s D 2 ⎦ d0
Ts D1
0 2L 0 T s (D 0 +D 1 )

0 − 2L Ts D1
C2 0 − 2L C2
C3 2L C 3

0 0 0 0 or â2 = A30 dˆ0 + A31 dˆ1 + A32 dˆ2 (48)

⎡ ⎤
0 0 0 0 b̂0 = 0
⎢0 0 0 0 ⎥ˆ
+⎣ 0 −D 2 ) T s D 2 ⎦ d1 or b̂0 = B00 dˆ0 + B01 dˆ1 + B02 dˆ2 (49)
0 − T s (1+D
2L C 2 0 − 2L C 2
0 0 0 0
⎡ ⎤ where B00 = B01 = B02 = 0
0 0 0 0
⎢0 0 0 0 ⎥ˆ ⎡ ⎤
+⎣ Ts D1 T s (D 0 +D 1 ) ⎦ d2 0 0 0 0
0 2L 0 T s (1−2D 0 −2D 1 −2D 2 )
C2 2L C 2 ⎢ 0 0⎥ ˆ
0 0 0 0 b̂1 = ⎣ 2L C 1 ⎦ d0
0 0 0 0
or â2 = A20 dˆ0 + A21 dˆ1 + A22 dˆ2 (47) 0 0 0
⎡ ⎤ ⎡ ⎤
0 0 0 0 0 0 0 0
⎢0 0 0 0 ⎥ˆ ⎢ − T2L
s 2D 0
0 0⎥ ˆ
â2 = ⎣ ⎦ d0 +⎣ C1 ⎦ d1
0 0 0 0 0 0 0 0
0 − 2L Ts D1
C3 0 − 2L
Ts D2
C3 0 0 0

⎡ ⎤ ⎡ 1 ⎤
0 0 0 0 L 0 0 0
⎢ 0 − R 1C 0 0 ⎥ ⎢0 − C11 0 0 ⎥
A0 = ⎢
⎣0
1 1 ⎥,
⎦ B0 = ⎢
⎣0
⎥ (37)
0 − R 21C 2 0 0 − C12 0 ⎦
0 0 0 − R 31C 3 0 0 0 − C13
⎡ 0 0 0 0 ⎤
⎢ 0 − L1 0 0 ⎥
⎢ 1 T s (D 2 D 1 −D 1 D 0 ) T (d 2 D 1 +D 2 D 0 −D 2 ) ⎥
A1 = ⎢
⎢ C1 − R 11C 1 + 2L C 1 0 2L C 1
⎥
⎥
⎣ 0 0 − R 21C 2 0 ⎦
0 0 0 − R 31C 3
⎡ 1 ⎤
L 0 0 0
⎢ T (D 0 −D 02 −2D 2 D 0 −2D 1 D 0 +D 2 ) ⎥
⎢ − C11
0 0 ⎥
B1 = ⎢ 2L C 1 ⎥ (38)
⎣ 0 0 − C12 0 ⎦
0 0 0 − C13
⎡ ⎤
0 0 − L1 0
⎢ 0 − R1 C11
0 0 ⎥
A2 = ⎢
⎣ 1 − T s D 1 +D 0 D 1 −D 1 D 2 ) − 1 − T s (D 2 D 0 +D 1 D 2 )
⎥
⎦
C2 2L C 2 R2 C2 2L C 2 0
0 0 0 − R 31C 3
⎡ 1
0 0 0 ⎤
L
⎢ 0 − C11 0 0 ⎥
B2 = ⎢
⎣ T s (D 0 −D 02 −D 1 )
⎥ (39)
2L C 2 0 − C12 0 ⎦
0 0 0 − C13
⎡ ⎤ ⎡ ⎤
0 0 0 − L1 1
L 0 0 0
⎢ 0 − R 11C 1 0 0 ⎥ ⎢ 0 − C11 0 0 ⎥
A3 = ⎢
⎣ 0
⎥,
⎦ B3 = ⎢
⎣ − C12
⎥.
⎦ (40)
0 − R 21C 2 0 0 0 0
T s (D 2 D 1 −D 1 D 0 ) T s D 12
1
C3 2L C 3 − T s (D 0 2L
D 2 +D 1 D 2 )
C3 − R 31C 3 − 2L C 3 0 0 − C13
PATRA et al.: SINGLE-INDUCTOR MULTIPLE-OUTPUT SWITCHER WITH SIMULTANEOUS BUCK, BOOST, AND INVERTED OUTPUTS 1943

⎡ ⎤
0 0 0 0
T s (1−2D 0 )
⎢ 0 0⎥ ˆ
+⎣ 2L C 1 ⎦ d2
0 0 0 0
0 0 0
or b̂1 = B10 dˆ0 + B11 dˆ1 + B12 dˆ2 (50)
⎡ ⎤
0 0 0 0
⎢ 0 0 0 0⎥ ˆ
b̂2 = ⎣ T s (1−2D 0 ⎦ d0
− 2L C 2 0 0
0 0 0
⎡ ⎤
0 0 0 0
⎢ 0 0 0 ⎥ˆ
+⎣ ⎦ d1
− 2LTCs 2 0 0
0 0 0 0 Fig. 7. Operating range of the output voltages with variation in duty cycles.

or b̂2 = B20 dˆ0 + B21 dˆ1 + B22 dˆ2 , where B22 = 0 (51)
⎡ ⎤ Hij where i = 1, 2 . . . , 4 and j = 1, 2 . . . , 7 represent the co-
0 0 0 0
efficient of its corresponding control/input and cross-regulation
⎢ 0 0 0 0⎥ ˆ
b̂3 = ⎣ T s (2D 1 ⎦ d1 transfer functions.
− 2L C 3 0 0
0 0 0
IV. OPERATING RANGE
or b̂3 = B30 dˆ0 + B31 dˆ1 + B32 dˆ2 , where B30 = B32 = 0.
The small-signal analysis for the SIBBI was illustrated in the
(52) previous section. Based on the steady-state calculations from the
evaluated formulas for the output voltages, the possible operat-
Thus, the modified state equation is
ing ranges can be defined based on the loads at the outputs for
x̂˙ = Ax̂ + B û + E0 dˆ0 + E1 dˆ1 + E2 dˆ2 all possible configurations with the variations in duty cycles at
the primary and output switches. It has already been illustrated
→ x̂˙ = Ax̂ + B û + E dˆ (53)
that the operation of SIBBI and the level of the output voltages
where possible at each of the outputs are defined by the amount of rip-
ple in the inductor and the switching sequence of the switches.
A = [A0 D0 + A1 D1 + A2 D2 + A3 (1 − D0 − D1 − D2 )] It should also be noted that to have one output as negative, the
B = [B0 D0 + B1 D1 + B2 D2 + B3 (1 − D0 − D1 − D2 )] output switched prior to that should be mandatorily a boost one
since only a high voltage can force the inductor current to nega-
E0 = [(A0 − A3 ) + A00 D0 + A10 D1 + A20 D2 ]X tive which ensures generation of a negative output at one of the
+ [(B0 − B3 ) + B00 D0 + B10 D1 + B20 D2 ]U nodes. Thus, one of the outputs has to be mandatorily a boost
output. However, which output is to be defined by what level of
E1 = [(A1 − A3 ) + A01 D0 + A11 D1 + A21 D2 ]X voltage is decided by the switching sequence.
+ [(B1 − B3 ) + B01 D0 + B11 D1 + B21 D2 ]U This study is a particular application with the switching se-
quence illustrated in the timing diagram (see Fig. 2). Based on
E2 = [(A2 − A3 ) + A02 D0 + A12 D1 + A22 D2 ]X such a switching sequence, it is defined that V1 would be boost,
+ [(B2 − B3 ) + B02 D0 + B12 D1 + B22 D2 ]U (54) V2 would be inverted, and V3 would be buck. But with the vari-
ation in the duty cycles for the switches, the levels of voltages
E = [ E0 E1 E2 ] , d = [ d0 d1 d2 ]T . (55) feasible for a set of system parameters are illustrated in Fig. 7. It
3) Transfer Functions of the Converter: Writing state vari- shows the operating range for V1 , V2 , and V3 with the variation
ables with respect to control variables and disturbance variables in D0 , D1 , and D2 as the three independent duty cycles. Fig. 8
combined in (53), the equation can be transformed to shows the operating range of the output voltages with the varia-
tion of the load currents in V1 , V2 , and V3 for a set of duty cycles
x̂˙ = Ax̂ + Bn ûn (56) D0 = 0.2, D1 = 0.3, D2 = 0.1. It establishes that the inverted
outputs can be achieved for a wide load range variation at the
where
outputs.
Bn = [ B E ], un = [ u d ]T . (57)
V. RESULTS AND DISCUSSIONS
Thus, taking the Laplace transform of (56), the frequency-
domain transfer functions for the state variables can be ob- An SIBBI converter that is capable of generating buck, boost,
tained with respect to control variables and input variables and inverted outputs simultaneously has been simulated, with
as X̂(s) = −A−1 Bn Ûn (s) = H(s)Ûn (s). Writing it in matrix specifications given in Table I. This is used to validate the model
form, as shown in (58), at the bottom of the next page, each of described in the previous sections. Open-loop ideal simulations,
1944 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 4, APRIL 2012

Fig. 8. Operating range of the output voltages with variation in load currents.

TABLE I
PARAMETERS OF THE CONVERTER FOR SIMULATION AND EXPERIMENTATION

based on the parameters presented in the table, were carried out
in Cadence and the steady-state results and transfer function
Bode plots are illustrated in Section V-A. Finally, the system
has been implemented in the laboratory using discrete compo-
nents on a two-layer PCB, designed in-house. The open-loop
steady-state experimental results are given in Section V-B1, and
the Bode plots for the control and coupling transfer functions
for the converter are discussed in Section V-B2. Table II com-
pares the results obtained from model calculation, Cadence-
based ideal circuit simulation and prototype experimentation.
Finally, Section V-C compares the simulated and experimen-
tal results. All the results verify the accuracy of the developed
model.
A. Simulation Results for SIBBI
Steady-state, time-domain, open-loop simulation results for
the SIBBI converter, with parameters presented Table I, are il-
lustrated in Fig. 9. The open-loop output voltages match the
calculated output voltages (obtained from the steady-state for-
mula in (36)), for the duty cycles given.
Figs. 10–12 show the Bode plots for the control, cross-
coupling, and cross-regulation transfer functions. The con-
trol and cross-coupling transfer function plots show the pres-
ence of right half-plane zeros as evaluated from the model.
The right half-plane zeros affect the system significantly in
open loop and can be observed in the oscillations in the

⎡ ⎤
V̂in (s)
⎡ ⎤ ⎡ ⎤ ⎢ Î (s) ⎥
ÎL (s) H11 (s) H12 (s) H13 (s) H14 (s) H15 (s) H16 (s) H17 (s) ⎢ 1 ⎥
⎢ Î (s) ⎥
⎢ V̂1 (s) ⎥ ⎢ H21 (s) H22 (s) H23 (s) H24 (s) H25 (s) H26 (s) H27 (s) ⎥ ⎢ 2 ⎥
⎣ ⎦=⎣ ⎦ ⎢ Î (s) ⎥ (58)
V̂2 (s) H31 (s) H32 (s) H33 (s) H34 (s) H35 (s) H36 (s) H37 (s) ⎢ 3 ⎥
⎢ D̂ (s) ⎥
V̂2 (s) H41 (s) H42 (s) H43 (s) H44 (s) H45 (s) H46 (s) H47 (s) ⎣ 0 ⎦
D̂1 (s)
D̂2 (s)
PATRA et al.: SINGLE-INDUCTOR MULTIPLE-OUTPUT SWITCHER WITH SIMULTANEOUS BUCK, BOOST, AND INVERTED OUTPUTS 1945

TABLE II
COMPARISON OF CALCULATED, SIMULATED, AND EXPERIMENTAL RESULTS

Fig. 9. Simulation results of steady-state output voltages and inductor current. (a) Simulation results. (b) Simulation results (zoomed).

Fig. 10. Bode plots for control transfer functions.

steady-state responses of the output voltages and inductor
current.
B. Experimental Results
The prototype of the SIBBI converter with the parameters
referred to in Table I was laid out in a two-layer PCB and
the board manufactured in-house. The circuit was realized by
discrete components. The following illustrates the steady-state
output voltages, inductor current, and the corresponding duty
cycles.
1) Steady State: The duty cycles calculated based on the
model were used for simulation as well as experimentation.
1946 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 4, APRIL 2012

Fig. 11. Bode plots for cross-coupled transfer functions.

Fig. 12. Bode plots for cross-regulation transfer functions.

Fig. 13. Steady-State experimental waveforms. (a) Output voltages and inductor current. (b) Duty cycles representing the switching sequence.
PATRA et al.: SINGLE-INDUCTOR MULTIPLE-OUTPUT SWITCHER WITH SIMULTANEOUS BUCK, BOOST, AND INVERTED OUTPUTS
Fig. 14. Control transfer function plot for v 1 w.r.t v 1 , v 2 w.r.t d2 , and v 3 w.r.t d0 .
The open-loop experimentation was targeted to achieve out-
put voltages of 5.6 V, −1.5 V, and 1.8 V from an input of
2.3 V. Fig. 13(a) shows the steady-state output voltages and
the inductor current observed from the test setup. The duty cy-
cle waveforms that switch the inductor current in the decided
sequence to generate the outputs shown in Fig. 13(a) are il-
lustrated in Fig. 13(b). With reference to Fig. 1, D0 switches
ON the main switch, thus charging the inductor. D1 switches
ON the boost output which is sequenced just after the inductor
charging consequently driving the inductor current negative to
enable generation of the inverted output in the next switching
sequence. Then, D2 switches ON the inverted output connection
and finally D3 drives the buck output. Fig. 13(b) replicates the
switching scheme very accurately. To validate the steady-state
performance, Table II draws a comparison of the steady-state
outputs modeled and simulated with those achieved through
experimentation.
2) AC analysis: The ac responses for various transfer func-
tions were observed using a network analyzer. The con-
trol transfer functions and the cross-coupling transfer func-
tions have been measured using the setup. Fig. 14 shows
the control transfer functions, V̂1 (s)/D̂1 (s), V̂2 (s)/D̂2 (s),
and V̂3 (s)/D̂0 (s), respectively. The cross-coupling trans-
fer functions, V̂1 (s)/D̂0 (s), V̂1 (s)/D̂2 (s), V̂2 (s)/D̂0 (s),
1947
V̂2 (s)/D̂1 (s), and V̂3 (s)/D̂1 (s), V̂3 (s)/D̂2 (s), are plotted
in Fig. 15. The realistic values of the dc gain and crossover
frequencies of the control transfer function are compared with
those achieved from the model and are reported in Table II.
C. Steady-State Comparison of Modeling, Simulation,
and Experimental results
Figs. 16–18 show a comparison of the steady-state output
voltages in calculation (as per modeling), simulation, and ex-
perimentation for various operating points of duty cycles. Of
the four duty cycles, two are kept constant and the other
two are varied to note the variations in the output voltages.
Fig. 16 shows the variation in V1 with variations in D0 , D1 ,
and D2 , respectively, keeping two as constant and varying the
other. The rest of the duty cycles are kept constant when one
is varied. Figs. 17 and 18 give the comparative study for out-
put voltages V2 and V3 with variations in D0 , D1 , and D2 ,
respectively, once again with two of them as constant and the
other varying. The plots give the differences between the ex-
perimental output voltages with those of ideal simulation and
calculated from the model. It must be noted that the experimental
results are with discrete components which have their associated
1948
Fig. 15. Cross-coupling transfer functions: v 1 w.r.t d0 and d2 ; v 2 w.r.t d0 and d1 ; v 3 with d1 and d2 .
parasitics. As a result, the experimental results deviated from
those of ideal simulations and model calculations typically by
5%. A few worst case conditions deviated by at most 10%. The
model calculations and ideal simulations match accurately, thus,
proving that the model is quite accurate. On the whole, this is a
good match of the experimental observed values with calculated
or simulated values.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 4, APRIL 2012
VI. CONCLUSION
This study presents a single-inductor multiple-output dc–dc
switching converter scheme that can produce simultaneously, in-
dependently controlled, one positive boost output, one inverted
buck output, and one positive buck output. Each of the outputs
can be adjusted to produce buck or boost or inverted outputs
as desired on the condition that at least one output must be a
PATRA et al.: SINGLE-INDUCTOR MULTIPLE-OUTPUT SWITCHER WITH SIMULTANEOUS BUCK, BOOST, AND INVERTED OUTPUTS 1949

Fig. 16. Comparative study of calculated (using model), simulated, and experimental results of output voltage waveforms with variations in D 0 , D 1 , and D 2
for V 1 .

Fig. 17. Comparative study of calculated (using model), simulated, and experimental results of output voltage waveforms with variations in D 0 , D 1 , and D 2
for V 2 .
1950
Fig. 18. Comparative study of calculated (using model), simulated, and experimental results of output voltage waveforms with variations in D 0 , D 1 , and D 2
for V 3 .
boost. This topology can, however, be extended to generate “n”
outputs each of which can be adjusted to generate a desired
output from among positive and negative buck or boost outputs.
The operating range has also been presented here. An inductor
current ripple-based modeling scheme has been incorporated
to accurately model the operation of this converter since the
conventional cycle-based averaging method does not work well
for these ripple-based converters. The model is used to accu-
rately analyze the steady state and dynamic responses of the
converter so that the predominant cross-regulation problem in
SIMO converters can be estimated and controlled easily. Finally,
the converter has been implemented on a two-layered PCB with
discrete components and the experimental results match up well
with the simulated and calculated values, thus validating the
model for the converter.
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Amit Patra (M’87) received the B.Tech., M.Tech.,
and Ph.D. degrees from the Indian Institute of Tech-
nology (IIT) Kharagpur, Kharagpur, India, in 1984,
1986, and 1990, respectively.
From 1992 to 1993 and again in 2000, he visited
Ruhr-University, Bochum, Germany, as a Postdoc-
toral Fellow of the Alexander von Humboldt Foun-
dation. He joined the Department of Electrical Engi-
neering, Indian Institute of Technology, Kharagpur,
in 1987 as a Faculty Member, and is currently a Pro-
fessor. He was the Professor In-Charge at Advanced
VLSI Design Laboratory, IIT Kharagpur, from 2004 to 2007. He is currently the
Dean (Alumni Affairs and International Relations) at IIT Kharagpur. His cur-
rent research interests include power management circuits, mixed-signal VLSI
design, and automotive-embedded control systems. He has guided 14 doctoral
students and published approximately 200 research papers in various journals
and conferences. He is the coauthor of a research monograph entitled General
Hybrid Orthogonal Functions and Their Applications in Systems and Control
(Berlin, Germany: Springer Verlag, 1996). He has carried out a number of spon-
sored projects in the areas of fault detection and diagnosis, fault tolerant control,
power management circuits, analog layout automation, sensor signal processing,
and built-in self-test circuits. He has collaborated with National Semiconductor
Corporation, Infineon Technologies and Freescale Semiconductor in the VLSI
area. As the Professor In-Charge of Advanced VLSI Design Laboratory, he also
took the lead role in the formation of the AVLSI Consortium at IIT Kharagpur
to strengthen VLSI research in India. The consortium has been joined by more
than a dozen leading VLSI companies worldwide.
Dr. Patra received the Young Engineer Award of the Indian National Academy
of Engineering in 1996 and the Young Teachers’ Career Award from the All
India Council for Technical Education in 1995. He was a Young Associate of the
Indian Academy of Sciences from 1992 to 1997. He is a member the Institution
of Engineers (India) and a Life Member of the Systems Society of India.
Neeraj Misra is currently working toward the
B.Tech. degree in electrical engineering at the Indian
Institute of technology (IIT) Kharagpur, Kharagpur,
India.
His research interests include power electronics
and control system.

Pradipta Patra received the B.Tech. degree from

Kalyani Government Engineering College, Kalyani,
West Bengal, India, in 1997 and the M.S. degree
from the Indian Institute of Technology Kharagpur,
Kharagpur, India, in 2007, where he has submitted
his Ph.D. thesis.
He was with Andrew Yule group of companies as
an R&D Engineer from 2001 to 2004. He is currently
at Intel Technology India Pvt. Ltd., Bangalore, India.
He won the Cadence Design Contest in 2007 and
has quite a number of international publications and
patents. In 2008, he visited Robert Bosch, Bangalore, and Germany for an
internship.