Job description

Responsibilities:

5.B.E./B.Tech./M.E./M.Tech./Ph.D in Electronics/VLSI

Circuit Theory, Control Systems, Signal Processing.

6. BTech(Electronics) - 7.5 CGPA/M.Tech(VLSI) - 8 CGPA/10th and 12th - 75%

7. Test of shortlisted students would be at our Campus on 29th Jan 2019 and Interview
date of selected students would be on 30th January

1.Design and development of state of the art Analog and Mixed Signal IPs (variety of
technologies).

2.Design of blocks and IPs and PLS analysis and verification

3.Design Documentation 

4.Design reviews

5.B.E./B.Tech./M.E./M.Tech./Ph.D in Electronics/VLSI

Circuit Theory, Control Systems, Signal Processing.

6. BTech(Electronics) - 7.5 CGPA/M.Tech(VLSI) - 8 CGPA/10th and 12th - 75%

7. Test of shortlisted students would be at our Campus on 29th Jan 2019 and Interview
date of selected students would be on 30th January

8 CGPA/10th and 12th - 75%

7. Test of shortlisted students would be at our Campus on 29th Jan 2019 and Interview
date of selected students would be on 30th January

ng.

6. BTech(Electronics) - 7.5 CGPA/M.Tech(VLSI) - 8 CGPA/10th and 12th - 75%

7. Test of shortlisted students would be at our Campus on 29th Jan 2019 and Interview
date of selected students would be on 30th January

Job description
Responsibilities:

5.B.E./B.Tech./M.E./M.Tech./Ph.D in Electronics/VLSI

Circuit Theory, Control Systems, Signal Processing.

6. BTech(Electronics) - 7.5 CGPA/M.Tech(VLSI) - 8 CGPA/10th and 12th - 75%

7. Test of shortlisted students would be at our Campus on 29th Jan 2019 and Interview
date of selected students would be on 30th January

1.Design and development of state of the art Analog and Mixed Signal IPs (variety of
technologies).

2.Design of blocks and IPs and PLS analysis and verification

3.Design Documentation 

4.Design reviews

5.B.E./B.Tech./M.E./M.Tech./Ph.D in Electronics/VLSI

Circuit Theory, Control Systems, Signal Processing.

6. BTech(Electronics) - 7.5 CGPA/M.Tech(VLSI) - 8 CGPA/10th and 12th - 75%

7. Test of shortlisted students would be at our Campus on 29th Jan 2019 and Interview
date of selected students would be on 30th January

8 CGPA/10th and 12th - 75%

7. Test of shortlisted students would be at our Campus on 29th Jan 2019 and Interview
date of selected students would be on 30th January

ng.

6. BTech(Electronics) - 7.5 CGPA/M.Tech(VLSI) - 8 CGPA/10th and 12th - 75%

7. Test of shortlisted students would be at our Campus on 29th Jan 2019 and Interview
date of selected students would be on 30th January

Job description
Responsibilities:

5.B.E./B.Tech./M.E./M.Tech./Ph.D in Electronics/VLSI

Circuit Theory, Control Systems, Signal Processing.

6. BTech(Electronics) - 7.5 CGPA/M.Tech(VLSI) - 8 CGPA/10th and 12th - 75%

7. Test of shortlisted students would be at our Campus on 29th Jan 2019 and Interview
date of selected students would be on 30th January

1.Design and development of state of the art Analog and Mixed Signal IPs (variety of
technologies).

2.Design of blocks and IPs and PLS analysis and verification

3.Design Documentation 

4.Design reviews

5.B.E./B.Tech./M.E./M.Tech./Ph.D in Electronics/VLSI

Circuit Theory, Control Systems, Signal Processing.

6. BTech(Electronics) - 7.5 CGPA/M.Tech(VLSI) - 8 CGPA/10th and 12th - 75%

7. Test of shortlisted students would be at our Campus on 29th Jan 2019 and Interview
date of selected students would be on 30th January

8 CGPA/10th and 12th - 75%

7. Test of shortlisted students would be at our Campus on 29th Jan 2019 and Interview
date of selected students would be on 30th January

ng.

6. BTech(Electronics) - 7.5 CGPA/M.Tech(VLSI) - 8 CGPA/10th and 12th - 75%

7. Test of shortlisted students would be at our Campus on 29th Jan 2019 and Interview
date of selected students would be on 30th January