Question Bank

Subject: Computer Organization & Architecture

Answer the short questions (each question has 2 or 3 marks).

1. What are the bottlenecks of Von Neumann concept?
2. What is meant by Harvard Architecture?
3. “The program counter is called memory pointer”- justify your answer
4. Can an input port and an output port have the same port address?
5. Subtract (1101)2 from (1001)2 using 2’s complement subtraction method.
6. What are the functions of MAR and MDR?
7. What is program status word?
8. What is bootstrap loader and where does it remain?
9. What is the function of instruction register?
10. What is ‘miss penalty’?
11. What is Princeton architecture?
12. What is the purpose of stack in microprocessor?
13. What is bus? How many buses are present in computer?
14. What is “Dumb” memory?
15. What is dirty bit?

Answer the following questions (each question has 5 marks).

1. Describe the function of Major Components of a digital computer with neat sketch.
2. Draw a logic diagram for carry look-ahead adder and discuss its advantages over conventional parallel adder.
3. Draw a circuit diagram to show how a full adder can be modified to work full subtraction.
4. Give an algorithm for Booth’s multiplication algorithm for 2’s complement numbers.
5. Give an algorithm or flowchart for non-restoring division for unsigned numbers with example.
6. Give an algorithm / flowchart for restoring division for unsigned numbers with example
7. a. Write +7 10 in IEEE 64-bit format.
b. Convert IEEE 32-bit format 4040000016 in decimal value.
c. Convert IEEE 64-bit format ABCD00000000000016 in decimal value. 2+2+1
8. With a neat sketch show the various fields in a typical instruction format and explain.
9. Evaluate the arithmetic statement X= (A+B) * (C+D) in zero, one and two Address machine.
10. What do you mean by instruction cycle, machine cycles and T states?

11. Show the circuit diagram for implementing the following register transfer operation. If ( a b = 1) then R1←
R2 else R1 ← R3, where a and b are control variables.
12. What is the difference between direct-addressing and indirect-addressing mode? Explain relative and base-
register addressing.
13. What are the various displacement addressing schemes? Where are they used? Explain each one of them with
the help of an example.
14. Explain the memory hierarchy pyramid, showing both primary and secondary memory in the diagram and
explain the relationship of cost, speed and capacity. .
15. Draw the logic circuit of the cell of RAM. Construct a 4 bit RAM having 2 words, using this cell.
16. Explain how a RAM of capacity 2 kbytes can be mapped into the address space (1000) H to (17FF)H of a CPU
having a 16-bit address lines. Show how the address lines are decoded to generate the chip select condition for the
RAM.
17. Compare and contrast: (3 X 5)
a. Static RAM versus Dynamic RAM
b. Flash Memory versus EEPROMs
c. Memory Interleaving versus Memory having multi-port
18. What is Cache? What is set associative mapping in cache memory?
19. What is cache mapping? Explain direct mapping for 256 x 8 RAM and 64 x 8 cache.
20. Draw the block diagram for an associative memory cell and explain it.
21. Suppose a computer using direct mapped cache has 2 20 words of main memory and a cache of 32 blocks,
where each cache block contains 16 words.
a. How many blocks of main memory are there?
b. What is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, block, and
word fields?
c. To which cache block will the memory reference 0DB6316 map? 2+2+1
22. Explain the concept of locality of reference and state its importance to memory systems.
23. Discuss the reading and writing operation with suitable logic diagram of an SRAM cell.

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24. Compare CISC and RISC.
25. Distinguish between Daisy chaining arbitration and independent request arbitration?
26. What are the reasons of having interrupts in computers?
How can the interrupts be handled in a computer?
Suggest a scheme that can handle multiple interrupts at a time. 2+2+1
27. What are vectored interrupts? How are they used in implementing hardware interrupts?
28. What are the differences between hardwired control unit and micro-programmed control unit?
29. Draw the block diagram and describe the functionality of micro-programmed control unit.
30. What are the different hazards in pipeline?

Answer the following questions (each question has 15 marks).

1. a. What is the Von Neumann concept and its bottleneck?

b. Represent the decimal value -7.5 in IEEE 754 single precision floating point format.
c. Compare parallel adder with serial adder.
d. Explain and draw 4-bit binary decrementer circuit. 4+3+4+4

2. a. Give the Booth’s algorithm for multiplication of signed 2’s complement numbers in flowchart and explain.
b. Multiply -7 and -3 using Booth’s algorithm.
c. Give the flowchart for division of two binary numbers and explain. 5+5+5

3. a. Explain Booth’s algorithm. Apply Booth’s algorithm to multiply the two numbers (+15) 10 and (-11)10.
Assume the multiplier and multiplicand to be of 5 bits each.
b. With suitable logic diagram explain the design of carry save adder. [ 10 + 5]

4. a. What is cache mapping? Explain cache mapping for 256 x 8 RAM and 64 x 8 cache.
b. Explain how a RAM of capacity 2 Kbytes can be mapped into the address space (1000)H to (17FF)H of a CPU
having a 16 bit address lines. Show how the address lines are decoded to generate the chip-select condition for
the RAM. [5 + 10]

5. a. Give the merits and demerits of the floating point and fixed-point representations for storing real numbers.
b. What are guard bits?
c. A floating-point number system uses 16 bits for representing a number. The most significant bit is the sign bit.
The least significant nine bits represent the mantissa and remaining 6 bits represent the exponent. Assume that
the numbers are stored in normalized format with one hidden bit.
i. Give the representation of –1.6 X 103 in this number system.
ii. What is the value represented by 0000100110000000.
d. Give the timing diagrams of basic memory read and write operations. [4+ 2+6+3]

6. Write short notes :

a. Von Neumann Architecture
b. Carry look ahead adder
c. Non restoring Division method [3 x 5]

7. a. Use 8-bit two’s complement integers, perform the following computations:

i. -34 + (-12)
ii. 17 – 35
iii. -22 – 7
iv. 18 – (-5)
b. Compute the product of the following pair of unsigned integers.
Generate the full 8 bit result.
i. 0b1001 x 0b0110
ii. 0b1111 x 0b 1111
iii. 0b 1100 x 0b 0011 8+7

8. a. What is a destructive and non-destructive read out memory? Give examples

b. Among dynamic MOS cell and static MOS cell which one is used for the construction of cache memory and
which one for main memory? Why?
c. Show the bus connection with a CPU to connect for RAM chips of size 256 X 8 bits each and a ROM chip of
512 X 8 bit size. Assume the CPU has 8 bit data bus and 16 bit address bus. Clearly specify generation of chip
select signals.
d. Define volatile and non-volatile memory. [4 + 3 + 6 + 2]

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9. a. Explain the reading and writing operations of a basic Static MOS cell.
b. Why a DRAM cell needs refreshing?
c. Given the following, determine size of the sub-fields (in bits) in the address for the Direct Mapping, associative
and set associative mapping cache schemes:
 We have 256 MB main memory and 1 MB cache memory.
 The address space of this processor is 256 MB.
 The block size is 128 bytes
 There are 8 blocks in a cache set. [6+ 3+ 6]

10. a. With example explain spatial and temporal locality.

b. What is an associative memory? With a suitable diagram explain the search operation in associative memory.
c. Briefly explain the two write policies write through and write back for cache design. What are the advantages
and disadvantages of both the methods?
[4 + 7 + 4]

11. a. What is a control memory and control word?

b. Explain the organization of control memory. How is control unit implemented using control memory?
c. Write a symbolic micro-program of a basic FETCH routine.
d. Briefly explain a vertical microinstruction format and a horizontal microinstruction format.
[2+ 4 + 5 + 4]

12. a. Differentiate between I/O mapped I/O and memory mapped I/O.
b. Distinguish between vectored and non-vectored interrupt.
c. Why do peripherals need interface circuit with them?
d. Discuss the advantage of interrupt initiated I/O over programmed I/O. [4 + 4 + 4 + 3]

13. a. What are some typical distinguishing characteristics of RISC organization?

b. A large register file in RISC design is substitute of cache memory in CISC design-Justify.
c. Explain the concept of register window for procedure calls in RISC design. [6 + 4 + 5]

14. a. What is the difference between computer organization and computer architecture?
b. Name the characteristics present in Von-Neumann architecture.
c. How does the fetch-decode-execute cycle work?
d. Assume you have a machine that uses 32-bit integers and you are storing the hex value 1234 at address 0:
i. Show how this is stored on a big endian machine.
ii. Show how this is stored on a little endian machine. [3 + 4 + 4 + 4]

16. a. Draw the internal cell diagram of PROM and explain its functionality.
b. What is cache memory? How does it increase the performance of a computer? What is hit ratio?
c. A three-level memory system having cache access time of 5 nsec and disk access time of 40 nsec, has a cache
hit ratio of 0.96 and main memory hit ratio of 0.9. What should be the main memory access time to achieve
an overall access time of 16 nsec?
d. Define i) rotational latency ii) seek time. [4+4+5+2]

17. a. What is instruction cycle? Draw the time diagram for memory write operation.
b. Explain the basic DMA operations for transfer of data between memory and peripherals.
c. Evaluate the arithmetic statement X = (A* B) / (C+D) in one, two and three address machines.
[1+4+5+5]

18. a. What is Cache memory? Why is it needed? Explain the Write-through and Write –back mechanism.
b. Why is set-associative mapping technique more advantageous than direct or associative mapping technique?
c. A computer has 512 KB cache memory and 2 MB main memory. If the block size is 64 bytes, then find out
the subfields for
i. direct mapping cache
ii. associative
iii. 8-way set associative cache
d. Why memory hierarchy is needed? What are the different levels in memory hierarchy? [ 2+2+2+2+3+2+2]

19. a. Show that when K jobs are processed over an N-stage pipeline, the speed-up obtained is S=NK/
(N+K-1)
b. Define speed-up of a parallel processing system.
c. Explain structural hazards in a pipeline processing.
d. With the help of a neat diagram, show the structure of a typical arithmetic pipeline performing subtraction.

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 e. Show that if a single powerful processor P is replaced by n small processors PZ having computational speed
1/nth the computational speed P then no advantage in speed-up is obtained. [3+2+3+4+3]

20. a. Compare RISC with CISC

b. What are instruction and arithmetic pipeline? Give examples.
c. Write a short notes on Flynn’s Classification of computers. [5 + 4 + 6]

21. a. What is meant by DMA? Why is it useful? Briefly explain with suitable diagram, the DMA operation in
association with CPU.
b. Draw the schematic diagram for daisy chain polling arrangement in case of vectored interrupt for three
devices
[2+2+4+7]

22. a. What is interrupt? What are the difference between vectored and non vectored interrupt?
b. Why is refreshing required in Dynamic MOS? Define volatile and non volatile memory.
c. How do ALU and CU work? Explain. [1+4+2+3+3+2]

23. a.
Explain the basic DMA operation for transfer of data bytes between memory and peripherals.
b.
Give the main reason why DMA based I/O is better in some circumstances than interrupt drive I/O?
c.
What is programmed I/O technique? Why is it not very useful?
d.
According to the following information, determine size of the subfields ( in bits) in the address for direct
Mapping and Set Associative Mapping cache memory.
 256 MB main memory and 1 MB cache memory
 The address space of the processor is 256 MB
 The block size is 128 bytes
 There are 8 blocks in a cache set
24. a. What are the various modes of data transfer between computer and peripherals? Explain.
b. Differentiate isolated I/O and memory mapped I/O.
c. Show how computer bus is organized using tri-state buffer. [5+5+5]

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