80-Va736-29 Msm7200 Chipset Training Power Management Topics - Pm7540 Ic 1354180002765

MSM7200 Chipset Training Slides:
Power Management Topics – PM7540 IC

80-VA736-29 Rev. A
QUALCOMM Confidential and Proprietary
Restricted Distribution. Not to be distributed to non-employees of QUALCOMM or its subsidiaries without the express approval of QUALCOMM’s
Configuration Management.
Not to be used, copied, reproduced in whole or in part, nor its contents revealed in any manner to others without the express written permission of
QUALCOMM.
QUALCOMM is a registered trademark and registered service mark of QUALCOMM Incorporated. Other product and brand names may be trademarks
or registered trademarks of their respective owners. CDMA2000 is a registered certification mark of the Telecommunications Industry Association, used
under license. ARM is a registered trademark of ARM Limited. QDSP is a registered trademark of QUALCOMM Incorporated in the United States and
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other countries.
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Export of this technology may be controlled by the United States Government. Diversion contrary to U.S. law prohibited.
QUALCOMM Incorporated
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5775 Morehouse Drive
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San Diego, CA 92121-1714
U.S.A.
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Copyright © 2007 QUALCOMM Incorporated. All rights reserved.
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80-VA736-29 Rev. A Page 1 QUALCOMM Confidential and Proprietary

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The following information

is licensed and
proprietary material.
Copyright © 2007 QUALCOMM Incorporated. All rights reserved.
Revision history
Revision Date Description

A April 2007 Initial release

April 2007
Agenda
• High-level PM7540™ Power Management IC information

– PM7540 IC introduction – functions and interfaces
– Features
Comparisons between the
– Block diagram
PM7540 and the PM7500
– Package IC are highlighted
– Pin assignments
– Controls and operating modes
• Detailed design guidelines organized by major functional blocks

– Input power management – input circuits, regulation, battery charging, etc.
– Output voltage regulation – summary of regulators, external components, etc.
– General housekeeping – analog multiplexer circuits, system clocks, etc.
– Handset-level user interfaces – current drivers, speaker driver, etc.
– IC-level interfaces – power on and off sequences, USB, RUIM, etc.
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• Additional material
– Not enough time to discuss everything in detail
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– Documents worthy of independent study are listed
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PM7540 IC Introduction – Functions and Interfaces

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2) Output voltage regulation
1) Input power management
3) General
housekeeping
4) User interfaces
5) IC interfaces
Functionally identical to the PM7500 IC

April 2007
Power Management IC Features (1 of 3)
• Complete power management, housekeeping, and user interface

functions for wireless devices—CDMA and non-CDMA handsets,
modems, PC cards, PDAs, etc.
• This list of features is organized according to the five major
functional blocks:
Feature description
1) Input Power Management
Valid external supply attachment and removal detection
Supports external charger supplies and USB supplies as input power sources
Supports lithium-ion main batteries
Main battery charging (trickle, constant current, constant voltage, pulsed)
Supports coin cell back-up battery (including charging)
Battery voltage detectors with programmable thresholds
Under-voltage lockout function turns off IC at severely low VDD condition
VDD collapse protection
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Charger current regulation and real-time monitoring for over-current protection
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Charger transistor protection by power limit control
Control drivers for two external pass transistors and one battery MOSFET (optional)
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Voltage, current, and power control loops
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Automated recovery from Sudden Momentary Power Loss
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Feature description
2) Output Voltage Regulation Flexible voltage regulator
One boost (step-up) switched-mode power supply (SMPS) architecture allows multiple
supply configurations
Four buck (step-down) switched-mode power supplies
18 low dropout regulator circuits with programmable output voltages
One MIC bias regulator circuit
Regulators can be individually enabled / disabled to save power
Supports dynamic voltage scaling (DVS) for MSMC1, MSMC2, and PA outputs
Low power mode available on most regulators
All regulated outputs are derived from common reference - close tracking
3) General Housekeeping
Analog multiplexer selects from 5 internal and up to 28 external inputs
Multiplexer output's offset and gain are adjusted to increase effective ADC resolution
Adjusted multiplexer output is buffered and routed to an MSM ADC
Dual oscillators (off-chip crystal and on-chip RC) assure MSM sleep clock
Crystal oscillator detector and automated switchover upon lost oscillation
Real Time Clock for tracking time and generating associated alarms
On-chip adjustments compensate for crystal oscillator frequency errors
Circuits control TXCO warm-up and synchronize, deglitch, and buffer the TCXO signal
TCXO buffer control for optimal QPH / catnap timing
Three stage over-temperature protection (smart thermal control)

April 2007
Feature description
5) IC-level Interfaces
Configurable SBI (3-wire or single-wire) for efficient initialization, status, and control
Supports MSM's interrupt processing with an internal Interrupt Manager
Many functions monitored and reported through real-time and interrupt status
Dedicated circuits control power-on sequencing, including MSM reset
Events continuously monitored that might trigger power-on / power-off sequences
Supports and orchestrates soft resets
USB-OTG transceiver for interfacing between MSM and external devices
Two sets of RUIM level translators enable MSM interfacing with external modules
MPP Multi-Purpose Pins
22 pins can be configured as digital or analog I/Os, bi-directional I/Os, or current sinks
Pkg Package
137 CSP (7 mm x 7 mm x 1.2 mm) with many dedicated ground pins
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The PM7540 IC provides the same functionality in a smaller
package—the PM7500 used the 9 × 9 mm 116 BCCS package
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PM7540 Block Diagram

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USB-OTG host REF_ISET REF +5V Boost VSW_5V MPP_4 (CBL1PWR_N)

VREG_5V REF_BYP MPP_3 (CBL0PWR_N) Power-on
power ckt Circuit Controller VREG_5V PON_RST_N
REF_GND VREG_5V PS_HOLD Circuits
USB_VBUS VDD_C1_E Core_1 Buck VSW_MSMC1 KPD_PWR_N
External Supply
Detector Regulator VREG_MSMC1 SBCK
VCHG Serial Bus
VDD_C2_PA VSW_MSMC2 I/F SBST
IMAXSEL_FC Core_2 Buck internal Interface
USB_CTL_N SBDT/SSBI
Charger det Regulator VREG_MSMC2 interface
Control VMAXSEL connections
Interrupt Mgr MSM_INT_N
CHG_CTL_N EBI_1 Buck VSW_MSME1
det
Regulator VREG_MSME1 IC
ISNS_P
Under-Volt
PA Buck VSW_PA Interfaces
MUX Regulator VREG_PA USB_OE_N USB_D_P
Lockout USB-OTG
to / from USB_DAT USB_D_M
ISNS_M Power On Circuits Transceiver
diff VDD_MSMP MSM_PAD USB_SE0 USB_ID
VREG_MSMP
Regulator to digital MPP_1 (AMUX_IN1) MPP_2 (AMUX_IN2)
VDD_MSME2 EBI_2 I/O circuits MPP_3 (CBL0PWR_N) RUIM/UIM MPP_4 (CBL1PWR_N)
Battery to internal
BAT_FET_N Regulator MPP_5 (RUIM_M_RST) MPP_6 (RUIM_RST)
Control analog ckts VREG_MSME2 Level
Input Power MPP_7 (GP1_DRV_N)
Translators
MPP_8 (REF_OUT)
VDD_ANA MSM_A MPP_9 (RUIM_M_CLK) MPP_10 (RUIM_CLK)
Management Regulator
VREG_MSMA
MPP_11 (RUIM_M_IO) MPP_12 (RUIM_IO)
Trickle Charger
VREF
V_INT MIC MPP_13 MPP_14
MIC_BIAS RUIM/UIM
VBATDET I/F Regulator MPP_15 MPP_16
Battery I/F MPP_17 Level MPP_18
VBAT MDDI
THLVB
Detectors VREG_GP2 (MDDI) MPP_19 Translators MPP_20
VDD_MMC Regulator MPP_21 MPP_22
Coin Cell MMC
VREG_MMC
Charger Regulator
PON_RESET_N
RUIM_1
VCOIN VDD_RUIM VREG_RUIM1
Regulator
VIB_DRV_N
Voltage
Control
VREG_MSMP V_BACKUP
Vcoin RUIM_2
VREG_5V VREG_GP3 (RUIM2)
Regulator
switch USB KPD_DRV_N
I/F VREG_USB
Regulator
Scaling
VUSB EACH MULTI-

16:1 Multiplexer
from TCXO
VREF TCXO PURPOSE PIN (MPP)
Controller
Offset and
VREG_TCXO
Regulator IS SHOWN MORE LCD_DRV_N
Scaling
VDD_TCXO
Current Controls
MPP_1 (AMUX_IN1) THAN ONCE

MPP_2 (AMUX_IN2) AMUX_OUT Synthesizer
2:1
VREG_SYNT
MPP_3 (CBL0PWR_N) Output Regulator
MPP_7 (GP1_DRV_N)
MPP_4 (CBL1PWR_N) Voltage
2:1
Switch Matrix
AUX_2
MPP_5 (RUIM_M_RST) General VREG_GP5 (AUX2)
Regulation Regulator
0.5xVREF
1xVREF
MPP_6 (RUIM_RST)
Housekeeping
2:1
MPP_7 (GP1_DRV_N) RF_RX1 FLSH_DRV_N

MPP_8 (REF_OUT) VDD_RF1 VREG_RFRX1
TCXO Regulator
2:1
MPP_9 (RUIM_M_CLK) Controller TCXO_EN

to RF_RX2
Die temp
MPP_10 (RUIM_CLK) TCXO VREG_RFRX2

MPP_11 (RUIM_M_IO) Reg Regulator I/F User
2:1
MPP_12 (RUIM_IO) TCXO_IN Interfaces

AUX_1 VREF
TCXO_OUT VREG_GP4 (AUX1)
MPP_13 Regulator
SMPS
to SMPS
VIDEO_IN VIDEO_OUT
circuits
MPP_14 Clock 0.5xVREF MPP_8 (REF_OUT) RF_TX

MPP_15 Ckts 1xVREF VREG_RFTX
Switch Matrix
Regulator SPKR_IN_L_P SPKR_OUT_L_P

MPP_16 2xVREF VDD_RF2
RC Osc SPKR_IN_L_M SPKR_OUT_L_M
MPP_17 div Camera
Circuits VREG_GP1 (CAM)
mux
MPP_18 SLEEP_CLK Regulator VDD_L_SPKR

Ref
MPP_19 VDD_R_SPKR
MPP_20 VDD_GP6 (BT) BT/SDIO
Real VREG_GP6 (BT) SPKR_IN_R_P SPKR_OUT_R_P
detect
MPP_21 Regulator
Time SPKR_IN_R_M SPKR_OUT_R_M
MPP_22 VDD_WLAN WLAN
Clock VREG_WLAN
VREF to other Regulator
PM7540 circuits
XTAL_OUT XTAL_IN Functionally identical to the PM7500 IC

April 2007
PM7540 Package
• 137 CSP package: 7 × 7 mm body,

1.2 mm height
• Many dedicated ground pins for
electrical ground, mechanical support,
and thermal relief.
The PM7540 IC provides the same

functionality in a smaller package –
the PM7500 used the 9 × 9 mm 116
BCCS package …
0.49 vs. 0.81 mm2
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• See PM7540 Device Specification
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(80-VD691-1), for detailed
dimensions, PCB land pattern, and
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PM7540 Pin Assignments

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1 2 3 4 5 6 7 8 9 10 11 12 13
VREG VREG SPKR_ SPKR_ SPKR_ SPKR_ VREG VREG VREG VREG REF REF
A MPP_6 A
_GP1 _RFTX OUT_R_P OUT_R_M OUT_L_M OUT_L_P _RFRX1 _GP4 _RFRX2 _MSMA _ISET _GND
VIDEO VIDEO SPKR_ SPKR_ SPKR_ SPKR_ VDD VDD VDD VREG
B MPP_17 VCOIN MPP_4 B
_OUT _IN IN_R_P IN_R_M IN_L_M IN_L_P _L_SPKR _RF1 _ANA _GP5
KPD_ REF
C ISNS_P ISNS_M C
PWR_N _BYP
USB_ CHG_ VDD VDD TCXO MSM VDD VREG

D MPP_5 MPP_18 MPP_3 D
CTL_N CTL_N _RF2 _R_SPKR _EN _INT_N _TCXO _TCXO
KPD_ BAT_ PS_ VREG VREG

E VCHG GND GND GND GND GND E
DRV_N FET_N HOLD _SYNT _GP6
LCD_ PON_ VDD VDD

F VBAT MPP_19 GND GND GND GND GND F
DRV_N RESET_N _GP6 _MSME2
VREG VDD TCXO MIC_ VREG

G MPP_20 GND GND GND GND GND G
_WLAN _WLAN _OUT BIAS _MSME2
FLSH_ USB USB_ TCXO VREG

H GND GND GND GND GND SBCK H
DRV_N _ID OE_N _IN _MSMP
VREG USB_ VDD VREG

J MPP_21 GND GND GND GND GND SBST J
_5V DAT _MSMP _GP2
VSW USB_ SLEEP SBDT/ VDD VREG

K MPP_22 MPP_11 MPP_12 MPP_9 MPP_10 K
_5V SE0 _CLK SSBI _GP2 _MMC
USB_ USB_ V_
L MPP_7 L
VBUS D_P BACKUP
VREG USB_ VREG VREG VREG VREG VDD AMUX XTAL

M MPP_13 MPP_16 MPP_1 MPP_8 M
_USB D_M _PA _MSMC2 _MSMC1 _MSME _RUIM _OUT _IN
VIB_ VSW VSW VDD VSW VDD VSW VREG VREG XTAL
N MPP_14 MPP_15 MPP_2 N
DRV_N _PA _MSMC2 _C2_PA _MSMC1 _C1_E _MSME _RUIM1 _GP3 _OUT
1 2 3 4 5 6 7 8 9 10 11 12 13
INPUT PWR MGT GEN HK IC I/F Power New package – all new pin
OUTPUT V REG USER I/F MPP Ground
assignments vs. the PM7500 IC

April 2007
Device Controls and Operating Modes
Static Mode Enabling Signals Mode Description

Active - Valid main battery or external power supply - Normal operating mode for PM7540 IC
(I_BAT1) - SBI functional - MSMA, MSMC1, MSMC2, MSME, MSME2,
- PS_HOLD = HIGH MSMP, & TCXO regs on (plus others as desired)
- Crystal oscillator and RTC are enabled
- TCXO buffers are on
- All other functions controlled individually via SBI
SLEEP - Valid main battery or external power supply - Power saving mode for PM7540 IC
(I_BAT2) - SBI functional and used to disable most PM ckts - MSMA, MSMC1, MSME, and MSMP regs are on
- PS_HOLD = HIGH - Crystal oscillator and RTC are enabled
- TCXO buffers are off
- All other functions and regulators are controlled
individually via SBI and are typically disabled
for minimum power dissipation
OFF1 - Valid main battery - Device almost completely turned-off, powered by
(I_BAT3) - SBI not functional the main battery
- PS_HOLD = LOW - Crystal oscillator and RTC are enabled
- RTC_OSCDIS = LOW - All other functions and regulators are disabled
OFF2 - Valid coin cell only - Device almost completely turned-off, powered by
(I_COIN1) - SBI not functional the coin cell
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- PS_HOLD = LOW - Crystal oscillator is enabled
- RTC_OSCDIS = LOW - All other functions and regulators are disabled
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OFF3 - Valid coin cell or backup capacitor - Device completely turned-off
(I_COIN2) - SBI not functional - Crystal oscillator and RTC are disabled
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- PS_HOLD = LOW co :1 - All other functions and regulators are disabled
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- RTC_OSCDIS = HIGH
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Operationally identical to the PM7500 IC

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Questions
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PM7540 overview
questions?
• Service requests:
https://support.cdmatech.com

April 2007
Input Power Management
• Input circuits overview

• Second power source default: battery or USB_VBUS
• External supply detection
• USB_VBUS as A-device or B-device
• USB regulator power sources
• Pass transistor controls and limiting power dissipation
• Voltage and current regulation
• Main battery charging
• Coin cell: charging, SRAM back-up, and solder-down installation
• Under-voltage Lockout (UVLO)
• Sudden momentary power loss (SMPL)
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• VDD voltage collapse protection
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• Input power management PCB layout guidelines
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• See the material referenced at the end of this presentation for details and
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additional input power management topics
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Input Circuits Overview

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• Input power source options

1) external charger supply from Ext Supply USB_VBUS
• Output voltage source at
2) external USB supply (3.3 to 5.25 V)
USB_VBUS supports peripherals 47k 4.7uF
3) main battery
(and backup coin cell)
from Ext Supply VCHG
• Input shunt resistors and capacitors (3.3 to 14.5 V)
- pulls VCHG low when its external supply removed 10k 1.0uF
E PM7540
- correct resistor to GND meets USB requirements
B USB_CTL_N
- capacitors for EMC, filtering, and circuit stability
C E
• Pass transistors must be bipolar PNP B CHG_CTL_N
C
• Active pass transistor is ISNS_P
closed-loop controlled to • 0.1 Ω sense resistor is assumed R_SNS

0.1 ohm
regulate voltage or current in all current calculations though 1% ISNS_M
alternate values are permitted
• V & I measurements enable
PM7540 limiting of transistor VDD_ANA, _GP2 (MDDI),
• 22 uF _GP6 (BT), _L_SPKR,
power dissipation
or more _MSMC1, _MSMC2, _MSME,
• Handset supply voltage (VDD) _MSME2, _MSMP, _PA,
22 uF
handset supply or more _R_SPKR, _RF1, _RF_2,
or “phone power” is
voltage (VDD) _RUIM, _TCXO, _WLAN
distributed from this node
BAT_FET_N
S
• Route power to PAs carefully G
Battery
• Battery transistor has to P-channel MOSFET
be a P-channel MOSFET D
VBAT
• Be aware of body diode leakage

• VCHG, USB_VBUS, and VDD (ISNS_M) Main
path in battery transistor Battery
are monitored continuously to detect
external supply additions or removals
(details on next slide)

April 2007
Second Power Source Default: Battery or USB_VBUS
Default 2
power source
• Default primary phone power source External supply at L1
USB_VBUS
USB connector
– If a valid USB supply and a battery are both connected, 47 k 4.7 uF
USB_VBUS is used by default
• But there is an option to use the battery by default External supply at E2
DC power connector
VCHG
– If a valid USB supply and a battery are both connected, Default 1 10 k 1.0 uF
the battery is used by default E
power source
B D1
• Procedure USB_CTL_N
– Set the initialization code USB_PWR_DEFAULT bit C E
through API B D2
CHG_CTL_N
– Power phone off; this bit remains set as long as the main
C
battery is present
– Plug the phone into a USB port; the PMIC senses the C1
ISNS_P
USB_VBUS voltage and initiates a power-on sequence
Current flow,
using the main battery instead of USB_VBUS
default 1 or 2 C2
– No current is drawn from USB_VBUS ISNS_M
VPH_PWR
• Additional notes handset supply VDD pins
voltage (VDD) 22 uF
– If the main battery is removed or becomes invalid, the or more
USB_PWR_DEFAULT bit is cleared and the USB_VBUS
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supply is used as the power source E4
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S BAT_FET_N
G
– All these steps and features remain true whether a coin Current flow,
cell backup is installed or not default 3 D
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F2
VBAT
Default 3
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main
power source battery
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External Supply Detection

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• PM7540 continuously monitors

VUSB, VCHG, and VDD to:
1) recognize when either external
supply is connected or removed
2) verify they are within range
if connected
• Hysteresis prevents undesired

switching near thresholds
• Nominal thresholds:
3.3 VCHG 14.5 V
3.3 USB_VBUS
• Removal detection considers the voltage drop

across the pass transistor; if less than 30 mV or so
the pass transistor is turned off—this prevents • When both a wall charger and a USB charger is connected,
reverse pass transistor operation that could keep the wall charger will take priority over the USB charger.
the PM7540 from realizing the supply was removed Two sources cannot be used for charging simultaneously.
• The PM7540 responds automatically to external supply changes

while reporting their conditions to the MSM through interrupts

April 2007
USB_VBUS as A-device or B-device
• When the PM7540 IC detects a mini-B plug

• When the PM7540 IC detects a mini-A plug (USB_ID pin = floating), the PMIC becomes
(USB_ID pin = 0V), the PMIC becomes an a B-device and draws power from the
A-device and provides output power on USB_VBUS pin
the USB_VBUS pin: >4V @ 25 mA
• Remote Device examples: PC, USB HUB,
OTG device, carkit, wall adapter
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USB Regulator Power Sources

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• The USB Transceiver cannot

be powered by VDD due to the
USB regulator is powered by 1 of 2 voltage sources: 0.7 V drop through the diode
1) VREG_5V – used during USB-OTG operation.
− PMIC recognizes USB peripheral, provides DC power to
the peripheral and to transceiver circuits.
- Peripheral is powered off VREG_5V through USB_VBUS
pin (via input power management circuits).
- Handset’s transceiver circuits are powered off VREG_USB (which is regulated off VREG_5V).
− VREG_5V is the default source voltage.
− 5 V Boost SMPS and USB regulator must be software enabled; neither circuit defaults to its on state.
2) USB_VBUS – when a host USB device is connected that device provides power to the handset.
− Software needs to select the external power source as the USB regulator supply voltage.
− USB regulator still powers the USB transceiver, but now it is regulating off USB_VBUS rather than VREG_5V.
NOTE: If a USB device is connected software must make different selections (per above) based upon whether the
handset is in the USB-OTG mode or not.
• For OTG operation: use default source (VREG_5V) for USB regulator, enable both VREG_5V and USB regulator.
• For non-OTG operation: use external source (at USB_VBUS) for USB regulator, enable the USB regulator;
enable VREG_5V regulator only if it is used for other purposes (such as Flash current driver).

April 2007
Pass Transistor Control and Dissipation Limiting
• PM7540 provides closed-loop control

of the active pass transistor to:
1) regulate VDD during normal operation
2) regulate Idet during fast charging
3) regulate VBAT near end of charging
4) increase R for over-current protection
5) increase R to limit transistor dissipation
• Voltage and current regulation are

addressed on later pages
• Either pass transistor could be active

#1: CHG_CTL_N controls charger xstr
#2: USB_CTL_N controls USB xstr
• Pass transistor dissipation is limited as follows:

1) measure the voltage drop across transistor (V)
2) measure total detected current (I)
3) calculate transistor power dissipation P = IxV
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4) compare to programmed power threshold
(between 0.3 to 2.0 W or “no limit”)
5) if needed: increase pass transistor resistance
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to reduce dissipation
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• Further design recommendations are given next
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Pass Transistor Power Dissipation (1 of 3)

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• Power dissipation = ΔV × I
• External supply and pass transistor selections

are interdependent; transistor power
dissipation is a key factor
• Desired ext supply features:

− output voltage > 4.3 V
(at least 0.1 V > VDD)
− max Vout as low as possible
(high Vout increases ΔV & P)
− current limit at 0.5 to 1.0 A
− provide voltage fold back
(limiting ΔV & I = lower P)
• Desired transistor features:

− low saturated VCE at Imax
− high dissipation rating
− low de-rating at high temp
− low thermal resistance
− small package
• Consider all ΔV & I conditions throughout the charging cycle

− wall and USB charger examples are shown on the following pages

April 2007
• This example assumes a 5-V wall charger with a 1 A limit

− the PMIC accepts up to 14.5 V … much higher ΔV and P
• Early:
− constant current mode (1 A limit)
− external supply folds back to VBAT + ~200 mV
− as battery charges, VBAT increases and VCHG follows it
− transistor dissipation nearly constant, fairly low
• Transition from constant current to constant voltage charging:
− current limiting stops, still near the limited value
− VCHG jumps from fold back to normal
− power dissipation spikes due to higher ΔV
• Late:
− constant voltage mode
− after spike, power drops non-linearly along with current
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• This example assumes a 5-V USB charger

− Does not provide voltage fold back
− current limits at 0.5 A
• Early:
− constant current mode (0.5 A limit)
− external supply does not fold back: large ΔV, high P
− dissipation is highest when charging first starts
− as battery charges, VBAT increases so ΔV & P decreases
− transistor dissipation continues to drop along with ΔV
• Transition from constant current to constant voltage charging:
− current limiting stops, still near the limited value
− VCHG doesn’t jump because USB supply doesn’t fold back
− no power dissipation spike
• Late:
− constant voltage mode
− after spike, power drops non-linearly along with current
• These curves illustrate the importance of:
1) limiting the maximum external supply voltage,
2) utilizing voltage fold back if possible, and
3) limiting the charging current externally.
• They also provide transistor power dissipation examples.

April 2007
Voltage Regulation
! VDD Regulation Loop ! VBAT Regulation Loop
from Ext Supply USB_VBUS USB-OTG from Ext Supply USB_VBUS USB-OTG
VREG_5V VREG_5V
(3.3 to 5.25 V) host power ckt (3.3 to 5.25 V) host power ckt
4.7 uF 4.7 uF
47 k 47 k
External Supply External Supply

from Ext Supply VCHG Detector from Ext Supply VCHG Detector
(3.3 to 14.5 V) (3.3 to 14.5 V)
1.0 uF 1.0 uF
10 k 10 k
E E
B USB_CTL_N det B USB_CTL_N det
IMAXSEL_FC IMAXSEL_FC
Charger Charger
C E C E
Control det VMAXSEL Control det VMAXSEL
B CHG_CTL_N B CHG_CTL_N
C C
ISNS_P ISNS_P
R_SNS R_SNS
0.1 ohm
MUX 0.1 ohm
MUX
ISNS_M ISNS_M
diff diff
VDD pins VDD pins
handset supply 22 uF handset supply 22 uF

or more or more
voltage (VDD) PM7540 voltage (VDD) PM7540
S
BAT_FET_N Battery Input Power S
BAT_FET_N Battery Input Power
G Control Management G Control Management
D VBATDET D VBATDET
VBAT Battery VBAT Battery
THLVB
Detectors THLVB
Detectors
Main Main
Battery Battery
T
• VDD is regulated during normal operation (when the main • VBAT is regulated during charging as the main battery
PD
battery is not being charged) approaches its final charge
• Internal multiplexer selects the VDD voltage at ISNS_M • This improves the charged battery’s final voltage by
.c 29
for comparison to the programmed threshold VMAX_SEL eliminating the battery transistor’s voltage drop
• The error voltage drives the charger control circuit which • Internal multiplexer selects the VBAT voltage
m 9:
controls the pass transistor to achieve desired VDD co :1 for comparison to the programmed threshold VMAX_SEL
• Other voltage regulation comments apply to VBAT as well
n
• Either pass transistor (charger or USB) could be active,
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Current Regulation
20
! Current Regulation Loop
from Ext Supply USB_VBUS USB-OTG

VREG_5V
(3.3 to 5.25 V) host power ckt
4.7 uF
47 k
External Supply
from Ext Supply VCHG Detector
(3.3 to 14.5 V)
• Current regulation (and pass transistor power 1.0 uF
10 k
limiting and over-current protection) requires E
the external sense resistor B USB_CTL_N det IMAXSEL_FC
• Over-current protection: Charger
C E
1) Differential V across sense R is monitored Control det VMAXSEL
B CHG_CTL_N
2) Compared to programmed threshold IMAXSEL
C
3) If threshold exceeded pass transistor R is increased ISNS_P
4) Disrupts voltage regulation but limits current
R_SNS
0.1 ohm
MUX
• Same circuits regulate current during fast charging ISNS_M
– Detected current is compared to IMAXSEL diff
VDD pins
– Error voltage drives charger controller which 22 uF
handset supply
sets pass transistor to achieve desired current voltage (VDD) or more
PM7540
• “Detected” current is inversely proportional to S
BAT_FET_N Battery Input Power
sense R; scale IMAXSEL as needed if value other G Control Management
than 0.1 Ohm is used
D VBATDET
VBAT Battery
• Either pass transistor (charger or USB) could be Detectors
THLVB
active, but only one is active at a time Main
Battery

April 2007
Main Battery Charging
Charging of a severely depleted battery

begins with trickle charging, which
limits the current and avoids pulling
VDD down.
After a minimum battery voltage is

established using trickle charging,
constant current charging is enabled
via software to charge the battery
quickly—this mode is sometimes called
fast charging.
After the battery approaches its target

voltage (through constant current
charging) the charge is completed
using either constant voltage or pulse
charging.
T
PD
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Trickle Charging
20
1) Pass transistor (not

shown) is turned ON Under-Volt
R_SNS MUX
0.1 ohm Lockout
ISNS_M
VDD pins
diff Trickle Charger Algorithm
handset supply 22 uF Software checks VBAT as soon as

or more
voltage (VDD) BAT_FET_N Battery a valid external supply is detected:
Control PM7540
S
G Input Power • If VBAT < 2.4 V:
2) Battery transistor Battery
P-channel MOSFET Trickle Charger Management Faulty battery, too low to chg;
is turned OFF D
Charging PM7540 powers up normally
Current
VBAT VBATDET
Main Battery • If 2.4 V < VBAT < 3 V:
Battery Detectors Battery good but depleted;
Monitored THLVB
Voltage trickle charging auto-started.
VCOIN
Special algorithm followed.
3) On-chip programmable • If VBAT > 3 V:
current source runs off VDD PM7540 General
Normal PM7540 power-up
Housekeeping
4) Current is set by software: • All thresholds are software
Scaling
0 (off) to 80 mA; 8 states

16:1 Multiplexer
ICHG_BYP programmable
Offset and
Scaling
5) Charging current (blue) AMUX_OUT

2:1
flows out the VBAT pin

2:1
6) Battery voltage is routed to MSM

through PM analog multiplexer
(tan); MSM HKADC measures VBAT
7) Trickle charging is finished ! NOTE: battery transistor is not needed if trickle charging is not used
when the battery reaches
! Battery charging continues with constant current charging
the desired threshold

April 2007
Constant Current Charging - Implementation
1) Pass active transistor is “on” –

continuously closed-loop controlled
to regulate the total current
2) Battery transistor is turned on,

connecting battery to VDD node
3) Charging current (blue) flows

from the external supply
4) Total current is set by the current

regulation loop as described earlier
T
PD
5) Battery voltage is routed to MSM through the PM7540
analog mux (tan); MSM HKADC measures VBAT
.c 29
6) Constant current charging is finished when
the battery reaches its target voltage
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Constant Current Charging - Curves

20
VBAT 2) Battery voltage increases

non-linearly, approaches
VMAXSEL target VMAXSEL
VBATDET
3) Target voltage VMAXSEL is

transition to residual
charging operation
programmed a little higher than 4) As target voltage is approached

the specified battery voltage to charging current decreases—
overcome the battery ESR and end of constant current charging
to achieve faster charging
constant current operation
time
Curves are
conceptual illustrations
ICHG
1) Constant current, limit LIMIT

set by PM7540 regulation
time

April 2007
Constant Voltage Charging - Curves
1) VBAT is regulated by the PM7540 to match the

target voltage VMAXSEL as discussed earlier
2) VBAT is regulated rather than

3) Battery voltage is nearly constant
VDD for better final accuracy
VBAT
VMAXSEL
VBATDET
charging operation
constant current
end of charge
transition from
Curves are
conceptual illustrations
constant voltage operation
time
4) Current decreases as 5) End of charge is implemented by
ICHG battery charges customer software (not QCT
software), detected 1 of 2 ways:
LIMIT a) monitor charging current using the
T
end of charge
MSM HKADC and terminate charge
PD
when it decreases to desired value
b) allow constant voltage operation
.c 29
for a predetermined duration after
crossing the VBATDET threshold
m 9:
co :1 time (on the order of one-half to two hrs)
n
! Do not allow charging to continue indefinitely – charging too long will damage the battery
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Pulse Charging Sequence

20
• Pulse charging repetitiously opens and closes the battery

transistor to deliver current pulses to the battery
• The battery’s open circuit voltage is checked and rechecked

to confirm a full charge before the process is terminated
! Benefits of pulsed charging (vs constant voltage): faster, more accurate, and dissipates
less power in the pass transistor when switching from constant current charging

April 2007
Pulse Charging - Curves
VBAT detail A - early pulsed charging waveforms

A B C
VMAXSEL VMAXSEL
VBATDET VBATDET
T_OFF
charging operation
T_ON
constant current
transition from
end of charge
pulsed operation
I_LIMIT
0
not to scale
(voltage or time)
1) Current pulse magnitude
is set by PM7540 regulation time detail B - near the end of pulsed charging
or the external supply limit
conceptual illustration - actually requires VMAXSEL
ICHG thousands of pulses to achieve full charge
VBATDET
T_OFF
T_OFF
T_OFF
T_OFF
LIMIT
T_ON
end of charge
I_LIMIT
0
time
2) Battery transistor is closed for T_ON – current pulse is applied
detail C - end of charge (for T_DONE = 4 x T_OFF)
3) Battery transistor is opened for T_OFF, then multiples of T_OFF – current
T
pulse is removed and battery voltage drops VMAXSEL
PD
4) T_ON, T_OFF, and T_DONE are software programmable; T_DONE is a VBATDET
binary multiple of T_OFF. Example values: 0.25s, 0.50s, and x16.
charge
end of
T_OFF
T_OFF
T_OFF
T_OFF
T_ON
.c 29
5) Three distinct phases are illustrated to the right:
I_LIMIT
A) Early – The detected voltage drops below threshold before one T_OFF
m 9:
B) Later – The detected voltage stays above threshold for several T_OFF
co :1 0
n
C) At end – The detected voltage stays above threshold for T_DONE
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Coin Cell Charging and Backup Voltage

20
! Rechargeable coin cell (Lithium Manganese Dioxide battery) is accommodated to power crystal oscillator
and real time clock circuits when other power sources are absent.
! Coin cell charging ! Coin cell backup
Scaling
Scaling
16:1 Multiplexer
16:1 Multiplexer
Offset and
Offset and
Scaling
Scaling
2:1
2:1
2:1
2:1
1) On-chip coin cell charger 1) With PM7540 on: 3) SRAM requirements:

- Voltage regulator and series R - SRAM is powered by VREG_MSMP - Able to operate off default
- Both programmable - Routed internally to VBACKUP VREG_MSMP voltage (+2.6 V)
- Operates off main battery - Full SRAM current provided - Retain data with +1.5 V supply
- Current through VCOIN (blue)
2) With PM7540 off:
4) Connect PON_RST_N to SRAM chip select:
- MSMP regulator is off
2) Coin cell voltage monitored by MSM - SRAM never selected during MSM resets
- Coin cell voltage is routed
- Routed through analog mux (tan) - Prevents data corruption while MSM powers
internally to VBACKUP (blue)
up and down
- SRAM keep-alive current provided
(usually ~1 uA)

April 2007
Avoiding RTC Corruption during Coin Cell Soldering
• Without proper precautions, the PM7540 real-time clock (RTC) registers can be corrupted
when simultaneously installing the PMIC and a solder-down coin cell
– Both components are exposed to significantly elevated temperatures simultaneously
– Coin cell voltage increases with temperature; PMIC is more susceptible to applied voltage
– If coin cell is connected to PMIC during high temperature the RTC registers may be corrupted
• QUALCOMM has identified a software solution that should be implemented

• Write ‘0’ to register 0 one time during production to reset the entire PM7540 IC
– API is: pm_hard_reset(void)
– Used during the phone’s production – not part of the shipped product’s operational SW
High voltage is
2
applied to PMIC
PMIC at high temperature is more
3 Coin cell voltage increases
susceptible to high voltage—RTC 1
with high temperature
registers may be corrupted
T
PD
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Under-voltage Lockout (UVLO)

20
! Handset supply voltage VDD is monitored continuously by UVLO

circuit that automatically turns IC off when VDD goes severely low
• As soon as VDD drops below the falling threshold

the UVLO condition is detected, PON_RST_N is
forced low, and the device is powered down
• Although UVLO is a hardware feature, software interaction realizes additional features:

Sudden Momentary Power Loss, Watchdog Timeout Soft Reset, and Power-on Abort

April 2007
Sudden Momentary Power Loss (SMPL)
! If SMPL is enabled and VDD returns to its valid range quickly enough, the PM7540 IC achieves an
immediate and automatic recovery from momentary power loss—without MSM intervention.
VDD
UVLO rising threshold
UVLO falling threshold
0V time
SMPL_SEL
• A coin cell or large capacitor (1.5 to 6.8 µF) must be installed and SMPL function must be enabled by software
T
• UVLO clears PON_RST_N – PM7540 regulators are not turned off
PD
• If VDD returns to its valid range before the SMPL counter expires the PM7540 initiates a power-on sequence
• An interrupt is sent to the MSM indicating that power was momentarily lost, current actions not a normal power-on
.c 29
• If SMPL counter expires the handset must undergo the normal power-on sequence, triggered by one of five events
m 9:
co :1
• For a normal power down when using SMPL:
n
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- Software must disable SMPL function before forcing PS_HOLD low to avoid an inadvertent SMPL override
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VDD Voltage Collapse Protection

20
! The PM7540 prevents a sudden load from inadvertently collapsing the VDD
voltage when a low current charger is used
1) The battery MOSFET source voltage

(VDD) is monitored through ISNS_M 1
2) The battery MOSFET drain voltage

(VBAT) is monitored through VBAT
3) If VDD drops below VBAT by ~50 mV,

the BAT_FET_N signal turns on the 3
battery MOSFET so the battery can
source current, prevent VDD collapse

April 2007
Input Power Management Layout Guidelines
pin L1 = USB_VBUS sense from
USB
13
12
11
10
• To minimize IR drops in high current paths, locate key
9
8
7
6
5
4
3
2
1
source
components near the PMIC:
N
M
M
- Dual pass transistor (Q3)
U
SB
L
_V
- Sense resistor (R35)
B
pin F2 = VBAT sense
U
- Battery transistor (Q4)
S
H
H
G
G
• Use very wide traces or fill areas in high current paths,
F
E
E
plus multiple vias to connect layers:
D
- VCHG
C
B
B
- USB_VBUS
C75
A
A
- VDD
13
12
11
10
9
8
7
6
5
4
3
2
1
- VBAT
pin E2 = VCHG sense
R35
pin C2 = R sense (-) C74
• Route sense lines carefully, separate from high current pin C1 = R sense (+)
R34
paths; sense resistor lines as differential pair:
VDD
Control signals:
C69
Pin D1 = USB_CTL_N
- VCHG (pin E2) Pin D2 = CHG_CTN_N
- USB_VBUS (pin L1) Pin E4 = BAT_FET_N
- VDD & ISNS_M (pin C2) Extend pass transistor collector

- ISNS_P (pin C1) pads as much as possible to Common collector
Q3
- VBAT (pin F2) outputs, VCHG or
Q4
maximize heat transfer USB_VBUS pass
transistor output
R30
PD
= critical inner layer (or combination
of inner layers) routing
T
A
VCHG
= critical inner layer (or combination
VB
.c 29
of inner layers) routing
• Routing of control signals are not critical:
m 9:
- USB_CTL_N (pin D1) co :1 = critical outer layer routing
- CHG_CNT_N (pin D2)
n
from
- BAT_FET_N (pin C4) = control signal on any combination
e. 20
from external
of outer and inner layers battery source
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Battery Charging High Current Path

20

April 2007
VDD Distribution
C
C
N M L K J H G F E D C B A
13 13
12 12
11 C C 11
C C
10 10 Bypass each VDD pin
9 9C 3
C as directly as possible
C
8 8
C
7 7
C
6 6
5 5
C
4 4
3 C 3
2 2
1 1
N M L K J H G F E D C B A
common collector
outputs, VCHG or
Use extremely wide traces USB_VBUS pass
2 transistor output
or fill areas to route VDD
Q3
R35
T
to PM7540
PD
VDD is routed to PAs and PMIC VDD node
1
without sharing high current traces – start of wide
.c 29
distribution
C75 Black = outer layer
to power
m 9:
amplifier(s)
co :1 Q4 Blue = inner layer
Red = inner layer
n
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Green = inner layer
to/from battery via Q4
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Questions
20
Input power
management questions?

April 2007
Output Voltage Regulation
• Voltage regulator summary – voltages, currents, defaults, etc.

• Switched-mode power supplies – boost (step-up) and buck (step-down) DC-to-DC
converters
– Beware of high-frequency switching current loops
• External component requirements (with emphasis on SMPS)

• Regulator performance specifications
• Power connections to the MSM7200 IC
• PM7540 dash numbers and MSM core voltages
• See the material referenced at the end of this presentation for more details and
additional output voltage regulation topics
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Voltage Regulator Summary (1 of 2)

20
• Two regulator categories • Linear designs on next page

1) Switched-mode power supplies • All regulators have default voltages, even
(SMPS) or DC-to-DC converters if they default to OFF at power-up
2) Low drop-out linear regulators • All regulators use a common bandgap
• Two types of SMPS designs reference circuit
1) Boost (step-up) – used 1 place; • Rated current values can be exceeded
rated for 500 mA significantly with slight degradation in
2) Buck (step-down) – used 4 places; some specifications. See the Device
rated for 500 or 300 mA each Specification for details.
• Some values are design targets and may
not be tested in production.
! SMPS summary
Default Low
Type/name Voltage range and increment Intended use
conditions power
Boost
+ 5V (500 mA) Off, 5.000 V 3.000 to 6.100 V; 100 mV steps PBM USB-OTG host, white LED backlight; camera flash
Buck
MSMC1 (500 mA) On, 1.200 V 0.750 to 3.050 V; 25 mV steps PFM MSM digital core #1 at 1.2 V or dynamically adjusted
MSMC2 (500 mA) On, 1.200 V 0.750 to 3.050 V; 25 mV steps PFM MSM digital core #2 at 1.2 V or dynamically adjusted
MSME (500 mA) On, 1.800 V 0.750 to 3.050 V; 25 mV steps PFM Devices on EBI #1 bus
PA (300 mA) Off, 1.800 V 0.750 to 3.050 V; 25 mV steps PFM Power amp; dynamically adjusted for min dissipation
• Functions are implied by naming convention, though most outputs can be user-defined.

April 2007
Voltage Regulator Summary (2 of 2)
• Four types of linear designs

1) rated for 300 mA ea – used 4 places 3) rated for 50 mA ea – used 4 places
! Linear regulator summary 2) rated for 150 mA ea – used 10 places 4) microphone bias – used 1 place
Default Low
Type/name Voltage range and increment Intended use
conditions power
300 mA design
MSMA On, 2.600 V 1.500 to 3.050 V; 50 mV steps LP MSM analog circuits; should be on at default voltage
MSMP On, 2.600 V 1.500 to 3.050 V; 50 mV steps LP MSM periphery circuits; should be on at default voltage
WLAN Off, 2.850 V 1.500 to 3.050 V; 50 mV steps LP 802.11 wireless LAN
GP6 (BT) Off, 2.850 V 1.500 to 3.050 V; 50 mV steps LP Bluetooth
150 mA design
MMC Off, 2.850 V 1.500 to 3.050 V; 50 mV steps LP SD/MMC module
MSME2 On, 1.500 V 0.750 to 1.525 V; 25 mV steps LP Devices on EBI #2 bus
RFRX1 Off, 2.850 V 1.500 to 3.050 V; 50 mV steps LP Primary Rx circuits
RFRX2 Off, 2.850 V 1.500 to 3.050 V; 50 mV steps LP Secondary Rx circuits
RFTX Off, 2.850 V 1.500 to 3.050 V; 50 mV steps LP Transmitter circuits
RUIM1 Off, 2.850 V 1.500 to 3.050 V; 50 mV steps LP RUIM module #1
GP1 (CAM) Off, 2.850 V 1.500 to 3.050 V; 50 mV steps LP Camera circuits
GP2 (MDDI) Off, 2.850 V 1.500 to 3.050 V; 50 mV steps LP MDDI circuits
GP3 (RUIM2) Off, 2.850 V 1.500 to 3.050 V; 50 mV steps LP RUIM module #2
T
GP5 (AUX2) Off, 2.850 V 1.500 to 3.050 V; 50 mV steps LP Auxiliary #2 analog circuits
PD
50 mA design
SYNT Off, 2.850 V 1.500 to 3.050 V; 50 mV steps LP Tx VCO & PLL
.c 29
TCXO On, 2.850 V 1.500 to 3.050 V; 50 mV steps LP Rx VCO & PLL; VCTCXO
m 9:
USB Off, 3.300 V 3.000 to 6.100 V; 100 mV steps
co :1 LP Internal USB transceiver; not for external loads
GP4 (AUX1) Off, 2.850 V 1.500 to 3.050 V; 50 mV steps LP Auxiliary #1 circuits
n
MIC bias Off, 2.000 V 1.73, 1.80, 1.93, or 2.00 V none Bias voltage for microphones
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Switched-Mode Power Supplies

20
! Boost converter – steps up the output voltage • Rated for 500 mA, though more is available
with some degraded performance
• Efficiency depends upon • Intended for generating +5 V to power USB-
external components OTG, camera flash, etc.
• Nominal component values are shown; small

size inductor is okay only for low current
applications (USB_OTG only)
• Ceramic capacitor is required for stability

Both converter types:
1) 1.6 MHz switching rate • Due to external Schottky diode there is no
(small external components) protection if VREG_5V is shorted to ground
2) PWM for low output ripple
3) Burst mode for low quiescent
• Rated for 500 or 300 mA each, though more is
available with some degraded performance
! Buck converter – steps-down the output voltage
• Intended for powering MSMC1, MSMC2, MSME,
and power amplifier (PA) functions
• VREG_PA can be used to power the RTR6275,
thereby reducing DC consumption – details later
• Efficiency depends upon
external components • Buck converters have better efficiency than
LDOs when in-to-out voltage difference is high
• Nominal component values are shown
• Ceramic capacitor is required for stability
• PA SMPS can be turned off by the TCXO controller to minimize dissipation when
transmissions are not allowed. Dissipation minimized further through dynamic
adjustment of PA voltage when handset Tx power at less than maximum.

April 2007
SMPS High Frequency Switching Current Loops
VREG_MSME to
! Schematic Boost example ! Layout MSM & pin M9
L1
VREG_MSME
C16
switching loop C28
C104 C31
A B C D E F G H J K L M N
C105 C45
13 13
C30 VREG_MSMC1 C29
12 12
11 11
switching loop
10 10 L2
9 9
8 8 VREG_MSMC1
7 7 to MSM & pin M8
6 6
5 5 VREG_MSMC2
4 4
to MSM & pin M6
3 3
Buck example 2 2
L3
1 1 VREG_MSMC2
C44 switching loop C43
A B C D E F G H J K L M N
! Comments C103 C60
• Each SMPS has higher efficiency than linear, but

switching transients require low value input and C102 C71
output capacitors as well as a careful layout C59 VREG_PA C58
T
switching loop
• Low value capacitors (0.1 µF, 100 pF) are critical to CR6
PD
L5
routing high frequency switching currents L4
VREG_PA to
• Provide low resistance path between capacitor PAs & pin M4
.c 29
grounds for switching currents
• Key pins are on the outer ring to allow direct
m 9:
C114 Cadd
connections on the outer PCB layer VDD
co :1
n
• Allow extra space & pads to experiment with inductors C57 C76
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Different color for each loop
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External Component Requirements

20
Load capacitor SMPS inductor

Regulator Value Type Value Type
+ 5V boost 10 uF Ceramic 2.2 uH Low or high power chip
MSMC1 buck 4.7 uF Ceramic 4.7 uH High power chip
MSMC2 buck 4.7 uF Ceramic 4.7 uH High power chip
MSME buck 4.7 uF Ceramic 4.7 uH High power chip
PA buck 4.7 uF Ceramic 4.7 uH High power chip
MSMA linear 4.7 uF Ceramic --- ---
MSMP linear 4.7 uF Ceramic --- ---
• Use X5R or X7R ceramic capacitors on the
output pins. Designs are stable with half to WLAN linear 4.7 uF Ceramic --- ---
five times the listed capacitance values, GP6 (BT) linear 2.2 uF Ceramic --- ---
taking into account the worst-case MMC linear 2.2 uF Ceramic --- ---
capacitance changes of X5R or X7R
MSME2 linear 2.2 uF Ceramic --- ---
dielectric
RFRX1 linear 2.2 uF Ceramic --- ---
• The +5 V boost (step-up) converter can use a RFRX2 linear 2.2 uF Ceramic --- ---
smaller, low power chip inductor only if low RFTX linear 2.2 uF Ceramic --- ---
currents are required (when the only load is
RUIM1 linear 2.2 uF Ceramic --- ---
the USB peripheral and supporting handset
circuits) GP1 (CAM) linear 2.2 uF Ceramic --- ---
GP2 (MDDI) linear 2.2 uF Ceramic --- ---
• More about SMPS external components next GP3 (RUIM2) linear 2.2 uF Ceramic --- ---
GP5 (AUX2) linear 2.2 uF Ceramic --- ---
SYNT linear 1.0 uF Ceramic --- ---
TCXO linear 1.0 uF Ceramic --- ---
USB linear 1.0 uF Ceramic --- ---
GP4 (AUX1) linear 1.0 uF Ceramic --- ---
MIC bias linear 1.0 uF Ceramic --- ---

April 2007
SMPS External Components (1 of 2)
2.2 uH
VSW_5V K1
VDD
1000
4.7 uF
pF
int RB551V-30
VDD +5V
Boost
VREG_5V J1 to off-chip circuits
Controller (USB-OTG host, white
1000 LEDs, camera flash)
10 uF
to USB circuits pF
N9 VDD_C1_E VSW_MSMC1 N8
VDD
1000
4.7 uF
pF • Select inductors based upon:
Core #1
4.7 uH
− rated current
Buck
Controller VREG_MSMC1 M8 to off-chip circuits
− DC resistance (critical to efficiency)
(MSM Core #1)
1000
pF
4.7 uF − converter efficiency (most critical!)
VSW_MSME N10 − parasitic capacitance
− shielding (may or may not be required)
4.7 uH − size & form factor (must fit!)
EBI
Buck
Controller VREG_MSME M9 to off-chip circuits
• Capacitors must be ceramic for stability
(EBI Bus on MSM)
1000
pF
4.7 uF
• Boost converter requires Schottky diode
N7 VDD_C2_PA VSW_MSMC2 N6
1000
4.7 uF
pF • Example efficiency curves and suggested
4.7 uH components are shown on next page
Core #2
Buck
T
Controller VREG_MSMC2 M6 to off-chip circuits
PD
(MSM Core #2)
1000
4.7 uF
pF
VSW_PA N4
.c 29
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4.7 uH
PA
co :1
Buck
n
Controller VREG_PA M4 to off-chip circuits
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internal VREF (PA_DVS)
1000
4.7 uF
pF
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SMPS External Components (2 of 2)

20
! Suggested inductors
Inductor value Manufacturer / Model Features Size (mm)
2.2 uH (boost) Vishay IHLP-2525CZ 0.020 Ohm 6.47 x 6.86 x 3
4.7 uH (buck) Toko D52LC 1.14 A, 0.087 Ohm 5x5x2
4.7 uH (buck) Toko 312C 720 mA, 0.24 Ohm 3.6 x 3.6 x 1.2
4.7 uH (buck) Murata LQH32 450 mA, 0.20 Ohm 3.2 x 2.5 x 2
! Example efficiency curves for different inductors (A and B) 4.7 uH (buck) Murata LQH31 340 mA, 0.65 Ohm 3.2 x 1.6 x 1.8
4.7 uH (buck) Taiyo-Yuden LBC2518 430 mA, 0.20 Ohm 2.5 x 1.8 x 1.8
− the most critical factor in selecting inductors 4.7 uH (buck) Taiyo-Yuden LB2016 210 mA, 0.25 Ohm 2 x 1.6 x 1.6
! Suggested capacitors
Capacitor value Manufacturers Voltage Size (mm)
10 uF (boost) Taiyo-Yuden, Vishay 6.3 V 2 x 1.25 x 0.5
4.7 uF (buck) Taiyo-Yuden, Vishay 6.3 V 2 x 1.25 x 0.5
4.7 uF (buck) Taiyo-Yuden 4.0 V 1.6 x 0.81 x 0.35
! Suggested diodes
Manufacturer / Model Features Size (mm)
Panasonic MA2ZD18 500 mA, 20 V 2.5 x 1.7 x 0.7
Rohm RB551V-30 500 mA, 30 V 2.5 x 1.7 x 0.7

April 2007
Using VREG_PA to Power the RTR6275 IC
• The PA SMPS could be used as the primary DC power source for the
RTR6275 IC rather than linear regulators
• Implementation requirements:
– MSM7200 IC
– PM7540 IC
– Platform D RF implementation (RTR6275 + RFR6500/RFR6525)
– AMSS 3.X (3080) only
• SMPS DC consumption is less than linear:

Expected GSM current savings Expected WCDMA current savings
Average current Average current
GSM RF band CH Tx level Rx level savings @ 3.75 V UMTS RF band CH Tx level BST level savings @ 3.6 V
900 MHz 37 +29 dBm -55 dBm 12 mA 2100 MHz (RTR) 9750 0 dBm -60 dBm 28 mA
900 MHz 37 +5 dBm -55 dBm 12 mA 2100 MHz (RFR) 9750 0 dBm -60 dBm 20 mA
T
1900 MHz 661 +28 dBm -55 dBm 12 mA 1900 MHz (RTR) 9400 0 dBm -60 dBm 31 mA
PD
1900 MHz 661 0 dBm -55 dBm 12 mA 1900 MHz (RFR) 9400 0 dBm -60 dBm 20 mA
800 MHz (RFR) 4180 0 dBm -60 dBm 20 mA
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– Platform D estimated values are based upon Platform B measurements
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Recommended VREG_PA Distribution

20
VREG_PA
• Three regulated voltages are used for the RTR6275:

MSMP, SYNTH, & PA; VREG_PA supplies most current
• Start with a conservative implementation – more series
isolating elements (reserve space using zero-Ohm
resistors) and more bypass capacitors, even those
shown as DNI (do not install)
• Power supply noise makes some components

necessary and sets some component values
• Final set of components depends upon the application,

PCB details, trace layouts, operating frequency, etc
• Characterize your handset design carefully,

empirically determining which DC components
are absolutely needed and which may be removed
without performance degradation
• VREG_PA is also used to power the antenna switch

April 2007
Related VREG_PA Design Guidelines
Include space and pads for a 10 uF

cap near the RTR6275 VDDA node
Larger output capacitor values

(0.1 uF and 22 uF)
The GSM transmit spurious performance might be

improved by splitting the 22 uF VREG_PA output capacitor
3
T
into two components – one near the PMIC VREG_PA
PD
output pin (12 uF) and one near the RTR IC (10 uF)
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All RFR6500/RFR6525 power supply connections remain
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Output Regulation Specifications

20
! Boost (step-up) SMPS ! Linear, rated for 300 mA

Parameter Min Typ Max Units Parameter Min Typ Max Units
Output voltage range 3.000 5.000 6.100 V Output voltage range 1.500 3.050 V
Output voltage accuracy -5 +5 % Output voltage accuracy -2 +2 %
Output voltage temp coefficient 100 +100 ppm/C Output voltage temp coefficient 100 +100 ppm/C
Load regulation 0.65 % Load regulation 0.65 %
Line regulation 0.2 % Line regulation 0.2 %
Efficiency, 80 mA load 85 % Dropout voltage at rated current 350 mV
Efficiency, 10 to 500 mA load 80 % Power supply ripple rejection 40 dB
! Buck (step-down) SMPS ! Linear, rated for 150 mA and 50 mA

Parameter Min Typ Max Units Parameter Min Typ Max Units
Output voltage range 0.750 1.375 3.050 V Output voltage range, MSME2 0.750 1.500 1.525 V
Output voltage accuracy -2 +2 % Output voltage range, USB 3.000 3.300 6.100 V
Output voltage temp coefficient 100 +100 ppm/C Output voltage range, all others 1.500 3.050 V
Load regulation 0.65 % Output voltage accuracy -2 +2 %
Line regulation 0.3 % Output voltage temp coefficient 100 +100 ppm/C
Efficiency, 0.5 to 500 mA 85 % Load regulation 0.65 %
Efficiency, 300 mA 90 % Line regulation 0.2 %
Efficiency, 600 mA load 80 % Dropout voltage at rated current 350 mV
PSSR, 50 to 1000 Hz, MSME2 35 dB
PSSR, 50 to 1000 Hz, all others 50 55 dB
! See the Device Specification for complete specs
! Some values are design targets and may not be tested in production
! Efficiencies depend upon external components

April 2007
Power Connections to the MSM7200 IC
VDD_A
B2
D5
E8
E9
A11 bypass/filter Bypass capacitors per MSM7200 User Guide (80-VA736-3) H1, H2, J2, J4
VREG_MSMA
as specified R2
T2
All VREG_MSMA decoupling caps should connect to the PCB V2, V5, W2, W5
PM7540 inner ground plane, NOT to the first layer digital ground flood. U2
MSM7200
B13 bypass/filter VDD_QFUSE_PROG
VREG_GP5 (AUX2) P8
as specified
N8 VDD_C1 B3, B10, B16, B18, B22,

bypass/filter
VSW_MSMC1 Bypass capacitors per MSM7200 User Guide (80-VA736-3) J27, L2, M27, Y2, Y27,
as specified
AG12, AG17, AG20, AG24
M8 VDD_C1_SENSE
VREG_MSMC1 AE27
N6 bypass/filter VDD_C2 AA2, AC2, AG2, AG4,

VSW_MSMC2 Bypass capacitors per MSM7200 User Guide (80-VA736-3)
as specified AG5, AG7, AG10, AG11
M6 VDD_C2_SENSE
VREG_MSMC2 AF2
VDD_MDDI
AD15
VDD_P1 A25, B11, B12, B15, B17,
B19, B20, E27, F27
N10 bypass/filter VDD_P2
T
VSW_MSME Bypass capacitors per MSM7200 User Guide (80-VA736-3) N27, U27, AA27
as specified
VDD_SMIP D27, G27, H27, K27, P27,
PD
M9 R18, W27, AB27, AD27
VREG_MSME VDD_SMIC
C27, L27, R27, V27, AF27
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Locate MSME sense node at the
branch of MSM, DDR, and NOR
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VDD_P4
H13 bypass/filter E10, N2
VREG_MSMP
co :1
Bypass capacitors per MSM7200 User Guide (80-VA736-3) VDD_P3
n
as specified AB2, AE2, AG3,
AG9, AG19, AG21
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PM7540 Dash Numbers and MSM Core Voltages

20
• An MSM core voltage is determined by its fabrication technology (line width)

• A PMIC having the correct default core voltage must be selected to match the MSM
requirement
• The PM7540 currently has two dash numbers to distinguish between two different
default VREG_MSMC output voltages
• The line width / core voltage / PMIC dash number combinations are:
line width core voltage PM7540 part # For MSM7200 devices

currently available
90 nm 1.200 V CD90-Vxxxx-1
65 nm x.xxx V CD90-Vxxxx-2 For MSM7xxx devices

available in the future

April 2007
General Housekeeping
• Analog multiplexer with offset and scaling

• Offset and gain options
• System clocks
• Selecting the crystal oscillator load capacitors
• Crystal resonator layout guidelines
• Housekeeping connections to the MSM7200 IC
– Including using an MPP as the GSM PA DAC reference voltage
• See the material referenced at the end of this presentation for more
details and additional general housekeeping topics
T
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Analog Multiplexer with Offset and Scaling

20
• Voltages at five external pins are B11 VCOIN

2/3 PM7540
scaled and routed to 16:1 mux
F2 VBAT
- VCOIN = coin cell 1/2
- VBAT = battery E2 VCHG

1/8
- VCHG = external charger supply C1 ISNS_P
- VDD = primary phone supply C2 ISNS_M diff
• 16:1 multiplexer
- VBUS = external USB supply 1/2
VDD ctl
M7 MPP_1 (AMUX_IN1)
• Offset & gain adjustment
N5 MPP_2 (AMUX_IN2) 0 optimizes mux output to
• Differential voltage across sense 1
D8 MPP_3 (CBL0PWR_N) fit MSM HKADC range
resistor is amplified, routed to mux 2
B12 MPP_4 (CBL1PWR_N) 3 (details on next page)
D4 MPP_5 (RUIM_M_RST) 4
ctl
5
A1 MPP_6 (RUIM_RST)
6
L12 MPP_7 (GP1_DRV_N) 7
8
offset AMUX_OUT M12
M11 MPP_8 (REF_OUT)
K8 MPP_9 (RUIM_M_CLK)
9 adjust
10
K9 MPP_10 (RUIM_CLK) 11
K5 MPP_11 (RUIM_M_IO) 12 ctl
• Any 5 of the 22 MPPs can be 13
K6 MPP_12 (RUIM_IO)
routed to the mux; no scaling 14
15
M3 MPP_13
N1 MPP_14
N3 MPP_15 0.5xVREF MPP_8 (REF_OUT) M11
1xVREF
M5 MPP_16 2xVREF any MPP can be
B3 MPP_17 configured as a scaled,
• External MPP connections used for: D5 MPP_18 buffered REF output
- thermal sensors F4 MPP_19 temp • VREF is buffered
- Tx power detection G4 MPP_20 sensor and available at
- battery ID J2 MPP_21
• Max input = +2.5 V K2 MPP_22
MPP for use by
- etc
MSM HKADC,
L1 USB_VBUS
2/5
GSM PA DAC, or
other functions
• CH 11: on-chip sensor monitors die temp • CH 13: scaled VREF = 1xVREF • CH 15 (no connection) is used
• CH 12: scaled VREF = VREF/2 • CH 14: reserved when AMUX_OUT is not active

April 2007
Offset and Gain Options
• Offset and gain are SBI-programmable; options are shown in table below
• These adjustments optimize the voltage swing into the MSM to fully use its 0.05 to 2.50 V input range
• This extends the resolution of the HKADC
Multiplexer Output Range Scaling Circuit Output Range

(input to the scaling circuits) (input to the MSM HKADC)
V_LOW_IN V_HIGH_IN Offset Gain V_LOW_OUT V_HIGH_OUT
0.05 2.50 0.000 1.000 0.05 2.50
0.04 2.00 0.000 1.250 0.05 2.50
0.03 1.50 0.000 1.667 0.05 2.50
0.02 1.00 0.000 2.500 0.05 2.50
0.01 0.50 0.000 5.000 0.05 2.50
0.54 2.50 0.500 1.250 0.05 2.50
0.53 2.00 0.500 1.667 0.05 2.50
0.52 1.50 0.500 2.500 0.05 2.50
0.51 1.00 0.500 5.000 0.05 2.50
1.03 2.50 1.000 1.667 0.05 2.50
T
1.02 2.00 1.000 2.500 0.05 2.50
PD
1.01 1.50 1.000 5.000 0.05 2.50
1.52 2.50 1.500 2.500 0.05 2.50
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1.51 2.00 1.500 5.000 0.05 2.50
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2.01 2.50 co :1 2.000 5.000 0.05 2.50
0.05 2.50 0.000 1.000 0.05 2.50 bypass
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System Clocks
20
to / from
! The PM7540 provides D9 TCXO_EN SBI circuits 1) TCXO controller and buffer circuits facilitate TCXO
or supports five major warm-up time and de-glitches and buffers the
D12 VDD_TCXO TCXO TCXO
system clock functions Regulator sleep Controller TCXO signal for driving the MSM TCXO input
clock
D13 VREG_TCXO VREG_MSMP H13
H12 TCXO_IN TCXO_OUT G10

VCTCXO
in out
TCXO controller and buffer circuits
Dividers
& pulse stat
skipping 5) Divided down versions of the TCXO or
sel RC oscillator are divided in quadrature
and used to drive the SMPS circuits –
RC only 1-of-4 transitions at a time
3) On-chip RC oscillator oscillator (minimizes transients)
provides start-up clock circuits
and back-up clocks if SMPS clock circuits
primary sources fail to RTC,
div-by-S SMPL, etc
SLEEP_CLK K7
Crystal oscillator circuits
stat sel
detect
SLEEP clock circuits
XTAL_OUT XTAL_IN
N13 xtal M13
Optional external 4) XTAL or on-chip RC oscillator
2) Crystal (XTAL) oscillator circuits module XTAL_OUT XTAL_IN (divided down) is buffered
support an external XTAL C C N13 M13 and available as MSM sleep clk
or oscillator module, including
NC
detection of lost oscillation
oscillator
module

April 2007
Selecting XTAL Load Capacitors
Example XTAL characteristics (EPSON MC-146)
Parameter Specification
Nominal frequency 32.768 kHz
Frequency tolerance +/- 50 ppm
Temperature coefficient -0.04 ppm/C^2
Load capacitance 7 pF Load capacitance
Series resistance 65k max CM 13 × C N 13

Shunt capacitance 0.8 pF typ CL = + Cstray
Operating temperature -40 to +85 C CM 13 + C N 13
Size (mm) 7.0 W x 1.5 D x 1.4 H
Series resistance
• Load capacitance includes serially connected external

• The PMIC is guaranteed to capacitors (at PM7540 pins M13 and N13) plus stray capacitance
oscillate as long as the XTAL
ESR is < 100k; easily met by • Correct load capacitance is critical; if incorrect …
this example (65k max). − circuit may never achieve oscillation
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− circuit may oscillate at an unintended frequency
• Example: 7 pF load capacitance is required
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− With external caps of 10 pF each, series combination is 5 pF
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Crystal Resonator Layout Guidelines

20
• Locate components near PMIC pins M13 and N13 (XTAL_IN and XTAL_OUT)
• Connect components to pins with short, direct traces
• Incorporate input and output capacitors at points along the traces
• Connect caps directly to internal PCB ground plane (vias at pads)
• Isolate traces from digital clock and logic signals
− Route very wide traces around the XTAL connections, tying
them to the internal ground plane with several plated vias
− Route threatening signals using vias to inner layer, then
route away from XTAL pins, traces, and components:
SBI, pins H10, J10, and K10
TCXO_IN, pin H12
MPP7 (GP1_DRV_N), pin L12 – if a threat
AMUX_OUT, pin M12
MPP8 (REF_OUT), pin M11 – if a threat
MPP1 (AMUX_IN1), pin M7
SLEEP_CLK, pin K7
MPP9 (RUIM_M_CLK), pin K8 – if a threat
MPP10 (RUIM_CLK), pin K9 – if a threat

April 2007
Housekeeping Connections to the MSM7200 IC
any MPP can be configured as a

scaled, buffered REF output and
used for the GSM PA refererence
ctl PM7540
voltages and
networks
scaling
currents
off-chip
0
0.5 x VREF MPP8 (REF_OUT) M11 T4
1 GSM_PA_PWR
1 x VREF
2 _CTL_REF
2 x VREF
3
analog multiplexer
4
5
ctl
networks
and signals
6
voltages
switch
off-chip
7
8
offset AMUX_OUT M12 F2
HKAIN[0]
9 adjust
10
11
ctl
& sensors
12
voltages
on-chip
13
14 TCXO_EN D9 AE1 TCXO_EN
15 GPIO[105]
to / from
SBI circuits
TCXO
VDD
VDD_TCXO TCXO
Regulator sleep Controller
MSM7200
clock
VREG_TCXO VREG_MSMP
VREG_MSMP
TCXO_IN TCXO_OUT G10 AB4

VCTCXO TCXO
in out 51
RC
oscillator 1/S
multiplexer
circuits SLEEP_CLK
T
K7 AG8
SLEEP_CLK
PD
sel
detect
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stat
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Questions
20
Voltage regulation or
general housekeeping
questions?

April 2007
Handset-level User Interfaces
• Current drivers, including camera flash

• Using an MPP as a flash or vibration motor driver control
• Dual-channel speaker driver
– Architecture
– External connections and output protection
– Variable input impedance
– Audio path multiplexing
– Parts placement and routing guidelines
• Video amplifier
– Connections and off-chip components
– Features and layout guidelines
• User interface connections to the MSM7200 IC

• See the material referenced at the end of this presentation for more
T
details and additional user interface topics
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Current Drivers
20
! The PM7540 IC provides three dedicated current driver circuits

plus has one MPP default to its current driver mode
KPD_DRV_N
LCD_DRV_N
MPP7 (GP1_DRV_N)
FLSH_DRV_N
• Independently programmable current settings

• Ground-referenced current sinks
• Low voltage compliance
• Highly flexible, suitable for many applications
• Intended applications and currents:
- Pin E1 for keypad backlight (to 150 mA)
- Pin F1 for LCD backlight (to 150 mA)
- Pin H1 for high voltage, high current (to 600 mA)
such as camera flash
- Pin L12, an MPP, defaults as a general purpose
LED driver to 40 mA

April 2007
Using MPP as Flash or Vibration Motor Driver Control
• On / Off control of the flash or vibration motor driver is exercised 1 of 2 ways:

1) Through SBI
2) Through a multi-purpose pin (MPP)
• Procedure for using MPP:
− Configure the MPP to be a digital input
− Define that MPP to be 1 of 3 DBUS signals
− Define the polarity of the control signal
− Define the Flash or motor driver on/off control to be the DBUS signal
− All selections are made via API software
• Benefits:
− More flexibility in defining driver timing
− High rate toggling for flashing LEDs
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Speaker Driver Architecture

20
! Versatile dual-channel speaker driver
4) Stereo-to-mono converter allows left 5) Gain control provides 8 programmable

and right channels to be summed settings: -16 to +12 dB in 4-dB steps
6) Output drivers are class-AB

1) Variable input impedance sets HPF stages that drive the speakers
corner frequency per AC-coupling each channel drives 500 mW into 8 Ω
capacitor (details later)
from MSM device
2) Audio path multiplexer provides

3) USB carkit block provides support
routing options for numerous
interface for USB carkit feature
configurations (details later)

April 2007
Typical External Connections and Output Protection
The 0.1 µF input AC-coupling capacitors are required:

1) yields a range of HPF corner frequencies that match typical speakers
2) satisfies carkit path requirements for full audio range (down to 20 Hz)
and/or protection
optional filtering
and/or protection
optional filtering
Optional filtering and protection at outputs address
three issues:
T
PD
1) Electro-magnetic Interference (EMI) – ferrite
beads are recommended
2) RF leakage – small capacitors (10 to 40 pF);
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value depends upon bands supported
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All these functions are now available in single modules
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Variable Input Impedance

20
The speaker driver inputs must be AC-coupled using a 0.1 µF capacitor. This value allows the PMIC input
impedance to be programmed to achieve the desired HPF corner frequency as follows:
• Review speaker data sheet to determine the expected resonant frequency (typically 450 to 1200 Hz)
• External series capacitors plus on-chip, programmable impedance create a highpass filter at the speaker input
• Program the input impedance (and therefore the HPF corner frequency) to match the speaker resonance
• Programmable HPF corner frequencies (assuming 0.1 µF input caps) include:
– 110, 450, 470, 490, 510, 540, 570, 600, 640, 680, 730, 760, 860, 950, 1060, 1200, or 1390 Hz
• If possible, empirically determine the best bass response with no distortion by varying the input impedance while driving
the actual speaker. This requires extra effort but results in the best possible sound.
• Tolerances of the input impedance and capacitor cause the intended cutoff frequency to shift up or down.
If this is a major concern tight tolerance 0.1 µF capacitors are recommended.
• The filtering can be disabled if the PMIC is driving an 8-Ω earpiece. In this case, the cutoff frequency will
be about 120 Hz. The MSM codec highpass filter can be used to further attenuate sub 300 Hz frequencies
that are not needed for voice.

April 2007
Audio Path Multiplexing
• The dual speaker paths, combined with the audio path multiplexer, allows support of
many speaker configurations under API software control.
• PM7540 design guidelines (80-VD691-5) gives instructions for API programming to
achieve the following configurations:
– MP3 playback
and/or protection
optional filtering
– Stereo phone/video phone
– 8-Ω receiver
– FM radio
– USB carkit (example shown)
and/or protection
optional filtering
Programmable parameter Mono Stereo
Right channel enable disabled disabled
Left channel enable disabled disabled
Right plus left summing disabled disabled
T
Audio mux configuration stereo disabled stereo disabled
PD
USB carkit option enabled enabled
USB left channel: data or audio buffer audio buffer audio buffer
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USB right channel: data or audio buffer data audio buffer
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Carkit interrupt hysteresis 50 msec 50 msec
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USB transceiver: regular or OTG OTG OTG
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Parts Placement
20
place close
to speakers
place close
to PMIC
left speaker
A6
LINE_O_L B7 SPKR_OUT_L_M
SPKR_IN_L_P
or AUXOP 0.1 uF
B6
SPKR_IN_L_M A7
0.1 uF
SPKR_OUT_L_P
4.7
0.1 uF
MSM
device
right speaker
A5
LINE_O_R B4 SPKR_OUT_R_M
SPKR_IN_R_P
or AUXON 0.1 uF
B5
SPKR_IN_R_M A4
0.1 uF
SPKR_OUT_R_P
4.7
PM7540
0.1 uF
… but minimize the

this distance is
distance between the
allowed to vary …
PMIC and speakers
Flip-phone designs: Ideally, the MSM device, PM7540 IC, and speakers should all be on the same side of the flip. If
not possible, the PMIC should be on the same side as the MSM for best routing of all the regulated voltages to the
MSM. Although not ideal (long traces from PMIC to speakers; narrow trace widths due to signal bottleneck at flip;
noise pick-up due to high speed video, digital, and RF signal proximity), it is better than running the PMIC input
signals through the flip. Inputs are sometimes single-ended (no common-mode rejection) and corruptive noise can
couple in before the speaker driver gain. This could degrade signal-to-noise ratio and cause higher idle noise.

April 2007
Routing Guidelines – Input Traces
• The dual speaker paths can be configured for stereo single-ended or mono differential
operation. Optimal input trace routing depends upon the type(s) of operation supported
in a particular phone.
• PM7540 design guidelines (80-VD691-5) gives recommendations for routing input traces
to support the following configurations:
– Mono differential only (1)
– Stereo single-ended (2)
– Both – mono and stereo (3) MSM 2
device 3 mil traces SPKR_OUT_L_M
SPKR_IN_L_M
3 mil traces 0.1 uF
LINE_O_L
SPKR_IN_L_P
or AUXOP 0.1 uF
SPKR_OUT_L_P
4 mil separation 10 mil
both sides separation PM7540
1
LINE_O_R SPKR_OUT_R_M
SPKR_IN_R_P
or AUXON 3 mil traces 0.1 uF
SPKR_IN_R_M
3 mil traces 0.1 uF
SPKR_OUT_R_P
a compromise between solutions 1 & 2

3
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• The design guide also provides a detailed
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Routing Guidelines – Output Traces

20
• Due to the speaker driver circuits’ high output current (and power) the routing of traces
between the driver outputs and the speakers are critical.
• In addition to the guidelines for mono differential inputs, these output traces require:
– Wider trace widths
– Larger separation between traces
– Use vias with extreme caution – they must be large enough to minimize power loss due to resistance
– If possible, route entirely on one side of the PCB – the side of the speaker contacts
• Example values are shown below

and/or protection
optional filtering
and/or protection
optional filtering

April 2007
Video Amp – Connections & Off-chip Components
! The video amplifier allows the MSM + PM7540 to drive a NTSC or PAL TV. An analog
composite video baseband signal (CVBS) plus synchronized analog stereo is provided.
• Use tight tolerance (1%) resistors to minimize gain errors • ESD protection should have low
capacitance (10 pF or less)
• Standard (5%) capacitors are adequate
• Use your preferred vendors, but one
T
• The inductor (15 µH) should have a DC rating of 5 mA or more candidate is the Semtech SR05
PD
• Use your preferred vendors, but candidate devices include:
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- Coilcraft 0805LS-153XJB
m 9:
- Vishay ILSB-0805 equivalent co :1
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- TDK MLF1608C150
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Video Amp – Features & Layout Guidelines

20
• Features
– Enables camcorder applications for playing videos or making slide presentations
– Drives a TV directly with synchronized video and analog stereo outputs
– Enables mobile display processing and TV encoding
– 10-bit video DAC with gain-setting resistors
– Works seamlessly with the MSM7200 TV Out feature
– Built-in TV-present detection circuit; interrupt-based readable status register
– Supports major NTSC (National Television System Committee) and PAL (Phase Alternate
Line) standards
» NTSC-M; NTSC-J; PAL-B, D, G, H, I; PAL-M; PAL-60
• Layout guidelines
– Component placements:
» 0.1 µF bypass capacitor very close to the MSM VDD_TVOUT_DAC pin
» 4.87k DAC current setting resistor very close to the MSM TVDAC_R_SET pin
» First 649-Ω resistor close to MSM; filter and second 649-Ω resistor close to PMIC
» 75 Ω-series resistor very close to the PM7540 VIDEO_OUT pin
– Do not route any traces within three trace widths of the video signals
– Provide grounded guard traces on both sides of the video signals and fill the areas above
and below with ground plane – similar to microstrip and/or stripline

April 2007
User Interface Connections to the MSM7200 IC
stereo
gain output
to mono
control driver
B8 B7 SPKR_IN_L_P converter
variable
LINE_OP
input Z
0.1 uF
audio routing multiplexer

B6 SPKR_IN_L_M
0.1 uF
D7
AUXIP
0.1 uF
E7
AUXIN
0.1 uF
A8 B4 SPKR_IN_R_P
variable
LINE_ON
input Z
0.1 uF SPKR_IN_R_M
B5 USB carkit
0.1 uF
interface
reconstruction filter
MSM7200
2.7 pF TV present
PM7540 interrupt
detection
T
15 uH
U4 B2 VIDEO_IN
PD
TVOUT
39 pF
649 30 pF 649
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IC-level Interfaces
20
• Power sequences overview

• Power-on and power-off triggering events
• Watchdog timeout and software resets
• Serial Bus Interface configurations
• USB-OTG transceiver
• RUIM level translators
• IC-level interface connections to the MSM7200 IC
• Multi-purpose pins
• PCB assembly and the PM7540 ground pins
• See the material referenced at the end of this presentation for more details
and additional IC-level interface topics

April 2007
Power Sequences Overview
! Example power sequence for the most common condition –

a phone being powered from its battery that is turned on and off via the keypad
T
High-level power-off sequence:
PD
High-level power-on sequence:
- keypad pressed pulls KPDPWR_N low - keypad pressed pulls KPDPWR_N low
- battery MOSFET turned on to power IC - MSM drives PS_HOLD low, requests power-down
.c 29
- default ON regulators turned on sequentially - PM drives PON_RST_N low – resets MSM, others
- PON_RST_N goes high, releasing MSM reset - regulators turned off sequentially
m 9:
- MSM drives PS_HOLD high to keep phone on co :1 - battery MOSFET turned off, disconnecting phone power
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! Much greater detail available in PM7540 Device Specification and User Guide
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Power-on and Power-off Triggering Events

20
• When the MSM signal PS_HOLD is low the PM7540 power-on circuits continually monitor these
five events:
1. Keypad power-on: the keypad power button being pressed
2. External supply detection: either charger (VCHG) or USB (VUSB) is connected and voltage
exceeds its threshold
3. Alarm: the real time clock, running off coin cell backup, generates an alarm interrupt
4. Cable insertion: a serial cable is attached to the handset and both CBLXPWR_N pins are
pulled low
5. Sudden momentary power loss (SMPL) recovery: SMPL condition was detected and an
SMPL recovery was initiated
• If any of these events occur a power-on sequence is initiated.
• When the MSM signal PS_HOLD is high the PM7540 IC is in one of its ON states. Circuits
continually monitor these three events:
1. MSM drives PS_HOLD low responding to keypad power button being pressed.
2. Detected VDD voltage drops below the UVLO threshold
3. PM7540 die temperature exceeds its “severe” over-temperature threshold
• If any of these events occur a power-off sequence is initiated immediately.

April 2007
Watchdog Timeout and Software Resets
1) MSM drives PS_HOLD low because the watchdog timer expired
2) PM7540 responds immediately by driving PON_RST_N low to reset the MSM and others
3) PM7540 connects VCOIN to VBACKUP to provide backup power to SRAM and Flash RAM
4) After a proper interval the TCXO buffer is disabled
5) After another interval several conditions are checked to determine what caused this power-down sequence to start
6) In this case the PM7540 realizes that a watchdog timeout has occurred and a software reset is being executed
7) Since this is a soft reset, the PM7540 does not power down. Instead it resets all SBI registers to default values,
waits 20 milliseconds, and then drives PON_RST_N high to take the MSM (and others) out of reset.
NOTES:
a) A watchdog reset requires that the watchdog feature is enabled
b) During a watchdog reset the PMIC does not turn the regulators off and on; they stay on, but go to their default states
T
c) To avoid an inadvertent watchdog override and conduct a normal power-down the watchdog feature must be
PD
disabled via software before PS_HOLD goes low
d) The differentiating factor between SMPL recovery and watchdog timeout is the UVLO detector state:
.c 29
– If a UVLO did not occur (VDD stayed above threshold) the power-up is a watchdog reset
– If a UVLO did occur the power-up is an SMPL event
m 9:
– Either event triggers its respective interrupt so the MSM knows what caused the power-up
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Serial Bus Interface Configurations

20
• Two SBI configurations are supported

– One 3-wire SBI supports earlier devices such as the MSM6550 and earlier
– One single-wire SBI supports later devices such as the MSM6800, MSM7200, and later
• The 3-wire SBI uses the following pins:
– Data: SBDT/SSBI, pin K10
– Strobe: SBST, pin J10
– Clock: SBCK, pin H10
• The single-wire SBI uses pin K10 only (SSBI)
– Connect pin J10 (SBST) to VREG_MSMP, pin H10 (SBCK) to ground

April 2007
USB-OTG Transceiver
! The PM7540 includes USB interface

circuits for connecting the MSM7200 to
handset-external peripheral devices
MSM
Device
Peripheral
T
Devices
PD
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m 9: switches
speaker
VREF
! USB-OTG details will be presented
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RUIM Level Translators

20
! The PM7540 includes MPPs whose intended configurations implement level translating MSM to RUIM connections
6) RUIM regulator circuit includes active pull-down when

disabled to meet RUIM transition speed requirements
2) RUIM side is referenced to

1) MSM side is powered by (or referenced VREG_RUIM
to) VREG_MSME or VREG_MSMP
3) Different reference voltages
(SBI selected)
on each side = level translator
MSM side
RUIM side
4) Clock and reset lines are unidirectional

(always MSM to RUIM)
5) IO data line is bidirectional - both sides
must be driven by open-drain outputs

April 2007
IC-level Connections to the MSM7200 IC
AG27 F10 PON_RST_N

RESIN_N
Power-on
C12 KPDPWR_N
PHONE_ON_N Circuits
PS_HOLD AB18 E10 PS_HOLD
GPIO[25]
SBST_PRI V7
J10 SBST
GPIO[57]
SBDT_PRI V8 K10 SBDT/SSBI Serial Bus
GPIO[58] Interface
H10 SBCK
SBCK_PRI W7
GPIO[59]
PM_INT_N AE18 D10 MSM_INT_N
GPIO[24] Interrupt Mgr
AE9 H4 USB_OE_N
USB_OE_INT_N
AD12 J4 USB_DAT USB-OTG
USB_DAT_VP
AB12 K4 USB_SE0
Transceiver
USB_SE0_VM
UIM1_RESET AH6
D4 MPP5 (RUIM_M_RST)
GPIO[48]
T
UIM1_CLK AD8 K8 MPP9 (RUIM_M_CLK)
PD
GPIO[47]
K5 MPP11 (RUIM_M_IO) RUIM/UIM
UIM1_DATA AD9
GPIO[50] Level
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Translators
MSM7200
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Multi-Purpose Pins
20
! 22 PM7540 pins are multi-purpose pins (MPP) having six configurable options:
1) Digital input meeting normal PM7540 logic specifications

2) Digital output meeting normal PM7540 logic specifications
3) Analog input that is routed to the analog mux through switch networks
4) Analog output that is a scaled and buffered version of the bandgap
reference voltage
5) Programmable current sink; tri-state (0 mA) to 40 mA
6) Two complementary MPPs can be jointly configured as a bi-directional,
level-translating pair – as utilized for the RUIM level translators
MUX
In each case, several configuration parameters are programmable.

The MPP pairings are:
MSM device side <===> RUIM side

Pin # Pin name Pin # Pin name
M7 MPP1 (AMUX_IN1) <===> N5 MPP2 (AMUX_IN2)
D8 MPP3 (CBL0PWR_N) <===> B12 MPP4 (CBL1PWR_N)
D4* MPP5 (RUIM_RST) <===> A1* MPP6 (RUIM_RST)
L12 MPP7 (GP1_DRV_N) <===> M12 MPP8 (REF_OUT)
K8* MPP9 (RUIM_M_CLK) <===> K9* MPP10 (RUIM_CLK)
K5* MPP11 (RUIM_M_IO) <===> K6* MPP12 (RUIM_IO)
M3 MPP13 <===> N1 MPP14
N3 MPP15 <===> M5 MPP16
B3 MPP17 <===> D5 MPP18
F4 MPP19 <===> G4 MPP20
J2 MPP21 <===> K2 MPP22
* These three pairs are intended to be used as an RUIM level translator.

April 2007
PCB Assembly and the PM7540 Ground Pins
• The PM7540 137-pad bump chip scale package (137 CSP) package includes several
ground pins near the center of the package for improved electrical ground,
mechanical strength, and thermal continuity
– These pins must be soldered to PCB pads located directly below the device
– Use many, many ground vias to conduct the heat directly to several inner layers
– The inner layers should provide very large areas of ground fill plus several additional
ground vias connected to outer layer ground fill areas
• Further mounting instructions are included in the BGA/CSP Package User Guide
(80-V2560-1)
T
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Questions
20
Handset-level or IC-level
interface questions?

April 2007
Additional Material for Independent Study
• More details and additional topics are

included in the referenced docs
– Input power management
– Output voltage regulation
– General housekeeping
– User interfaces
– IC-level interfaces
– Multi-purpose pins
• PM7540 Device Specification (80-VD691-1)

• PM7540 User Guide (80-VD691-3)
T
PD
• PM7540 Device Revision History (80-VD691-4)
• PM7540 Design Guidelines (80-VD691-5)
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• MSM7500 Baseband Reference Schematic (80-V9038-41)
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• PM7500 Application Board User Guide (80-V7773-7)
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Questions?
20

April 2007

80-Va736-29 Msm7200 Chipset Training Power Management Topics - Pm7540 Ic 1354180002765

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MSM7200 Chipset Training Slides:

Power Management Topics – PM7540 IC

QUALCOMM Confidential and Proprietary

80-VA736-29 Rev. A Page 1 QUALCOMM Confidential and Proprietary

The following information

Copyright © 2007 QUALCOMM Incorporated. All rights reserved.

Revision Date Description

80-VA736-29 Rev. A Page 2 QUALCOMM Confidential and Proprietary

• High-level PM7540™ Power Management IC information

• Detailed design guidelines organized by major functional blocks

80-VA736-29 Rev. A Page 3 QUALCOMM Confidential and Proprietary

PM7540 IC Introduction – Functions and Interfaces

2) Output voltage regulation

1) Input power management

Functionally identical to the PM7500 IC

80-VA736-29 Rev. A Page 4 QUALCOMM Confidential and Proprietary

• Complete power management, housekeeping, and user interface

80-VA736-29 Rev. A Page 5 QUALCOMM Confidential and Proprietary

Power Management IC Features (2 of 3)

80-VA736-29 Rev. A Page 6 QUALCOMM Confidential and Proprietary

80-VA736-29 Rev. A Page 7 QUALCOMM Confidential and Proprietary

PM7540 Block Diagram

USB-OTG host REF_ISET REF +5V Boost VSW_5V MPP_4 (CBL1PWR_N)

VUSB EACH MULTI-

MPP_1 (AMUX_IN1) THAN ONCE

MPP_7 (GP1_DRV_N) RF_RX1 FLSH_DRV_N

MPP_9 (RUIM_M_CLK) Controller TCXO_EN

MPP_10 (RUIM_CLK) TCXO VREG_RFRX2

MPP_12 (RUIM_IO) TCXO_IN Interfaces

MPP_14 Clock 0.5xVREF MPP_8 (REF_OUT) RF_TX

Regulator SPKR_IN_L_P SPKR_OUT_L_P

MPP_18 SLEEP_CLK Regulator VDD_L_SPKR

XTAL_OUT XTAL_IN Functionally identical to the PM7500 IC

80-VA736-29 Rev. A Page 8 QUALCOMM Confidential and Proprietary

• 137 CSP package: 7 × 7 mm body,

The PM7540 IC provides the same

80-VA736-29 Rev. A Page 9 QUALCOMM Confidential and Proprietary

PM7540 Pin Assignments

USB_ CHG_ VDD VDD TCXO MSM VDD VREG

KPD_ BAT_ PS_ VREG VREG

LCD_ PON_ VDD VDD

VREG VDD TCXO MIC_ VREG

FLSH_ USB USB_ TCXO VREG

VREG USB_ VDD VREG

VSW USB_ SLEEP SBDT/ VDD VREG

VREG USB_ VREG VREG VREG VREG VDD AMUX XTAL

80-VA736-29 Rev. A Page 10 QUALCOMM Confidential and Proprietary

Static Mode Enabling Signals Mode Description

Operationally identical to the PM7500 IC

80-VA736-29 Rev. A Page 11 QUALCOMM Confidential and Proprietary

80-VA736-29 Rev. A Page 12 QUALCOMM Confidential and Proprietary

• Input circuits overview

80-VA736-29 Rev. A Page 13 QUALCOMM Confidential and Proprietary

Input Circuits Overview

• Input power source options

• Pass transistors must be bipolar PNP B CHG_CTL_N

closed-loop controlled to • 0.1 Ω sense resistor is assumed R_SNS

• Be aware of body diode leakage

80-VA736-29 Rev. A Page 14 QUALCOMM Confidential and Proprietary

80-VA736-29 Rev. A Page 15 QUALCOMM Confidential and Proprietary

External Supply Detection

• PM7540 continuously monitors

• Hysteresis prevents undesired

• Removal detection considers the voltage drop