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Project 2
Open Loop H-Bridge Inverter Design using
Traditional PWM Method
and
One Cycle Control

EECS 267B: Industrial & Power Electronics, Spring 2005

Professor K. Smedley

Tong Lin Huang student

Ethan Matthes student
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Table of Contents

H-Bridge Specifications ...................................................................................................... 3

Problem Statement.............................................................................................................. 3

Pulse Width Modulation ....................................................................................................... 4

Bipolar Open-Loop PWM Controlled H-bridge.............................................................. 4

Driving Signals ................................................................................................................. 5
Simulation of the circuit in steady-state............................................................................ 5

Energy-Saving Mode (Unipolar) ....................................................................................... 6

Designing the control circuit............................................................................................. 6
Energy Saving Mode (Unipolar) Truth Table ......................................................... 6
Schematic for PWM H-bridge with the energy saving gating scheme............... 8
Energy Saving Mode, PWM Controlled H-bride gating Signals.......................... 9
Simulation of the circuit in steady-state............................................................................ 9

One Cycle Controlled (OCC) H-bridge in Energy Saving Mode ................................. 11

Introduction of Input Voltage Disturbance ......................................................................... 14
Output response to Input disturbance: Open-Loop PWM Bipolar ................................. 14
Output response to Input disturbance: Open-Loop PWM Energy Saving Mode ........... 15
Output response to Input disturbance: Open-Loop OCC Energy Saving Mode............. 15

Closed-Loop OCC Energy Saving Mode ........................................................................ 16

Output response to Input disturbance: Closed-Loop OCC Energy Saving Mode .......... 16

Tracking Abilities Compared .......................................................................................... 17

Conclusion ......................................................................................................................... 17
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H-Bridge Specifications
Switching Input Voltage Output Voltage Output Output Power
Frequency Frequency
fs = 20kHz VG = 300VDC V = 100VRMS 60Hz POUT = 1kW
(Ts = 50µs) (Vpeak =
141.41V)

(LOAD)RATED = VOUT2 /POUT= (100VRMS)2 /(1000W) = 10Ω

An input voltage disturbance of 118Hz sinusoidal ripple at 45VRMS ( 2 * 45 = 63.64V peak ) is

introduced separately to gauge the converter’s response for different control schemes.

The four switches have the non-idealities: on-resistance, RON = 25mΩ, and a body diode
(though VON is neglected).

An H-bridge is like two Buck converters: One converter operates during the positive half-
cycle, and the second during the negative half-cycle. Therefore the H-bridge inductor
current and output voltage ripple should be similar to that of a Buck converter.

V 100
For an H-bridge: V = VG*d during (+) and V = -VG*d during (-). ∴ d = = = 0.33
VG 300
Simulation output filter parameters:
Inductance was desired to be large, but not too large. L = 5mH, with resulting inductor
current ripple of 33.3%. Output voltage ripple was held much tighter at 2.1% using C =
100µF. Simulation took place at full load.

Problem Statement (30 points total)

I. (7 points) Design the control circuit providing the correct trigger signals.
a. (4 points) Design the control circuit.
b. (1 point) Draw the entire circuit schematic.
c. (2 points) Show the trigger signal during a line period in steady-state.
II. (4 points) Simulate the circuit in steady-state. Show the reference, input voltage,
and output voltage waveforms.
III. (4 points) Simulate the circuit when the input dc voltage with 15% ripple at 118Hz
sinusoidal. Show the reference, input voltage, and output voltage waveforms.
IV. (15 points) Repeat I-III for OCC control.
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Pulse Width Modulation

Bipolar Open-Loop PWM Controlled H-bridge

Special Explanation: The reason we have two separate references, one for (+) and the
other for (-), is because of ORCAD Lite convergence issues; That is, adding inverters to
two of the gates inputs resulted in convergence problems.
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Driving Signals:
The driving signals Mpos and Mneg are generated by PWM. To be specific, we compare s
sawtooth signal with the sinusoidal signal using an Op Amp to create each driving signal of
the four switches. The resulting driving signals, Mpos and Mneg, will have a duty cyle directly
related to the amplitude of the sinusoidal input.

As one can see from the image above, the two control signals, Mpos and Mneg, are
complimentary to each other at all times. Thus, switch S1 and S2 would never be ON at the
same time, so the input voltage would not be shorted.

Simulation of the circuit in steady-state

The output signal tracks the ideal sinusoid well with an addition of a phase delay.
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Energy-Saving Mode (Unipolar)

Designing the control circuit:

Here is the placement of the four H-bridge switches (FETs):

Energy Saving Mode (Unipolar) Truth Table

Half Cycle Duty Ratio M1 M2 M3 M4
(d1) (d2)
0 0 0 1 0 1
0 1 0 1 1 0
1 0 1 0 1 0
1 1 0 1 1 0
Where ‘1’ indicates switch Mn = ON and ‘0’ indicates switch Mn = OFF,
‘1’ for d1 means (+) half cycle, and ‘0’ for d1 means (-) half cycle.

The table indicates that in the positive half cycle, switch M3 is always ON and M4 always
OFF. M2 is the same as duty ratio (d2), and M1 is the inverted value of the duty ratio d2.
During the negative half cycle, M1 is always OFF and M2 is always ON. The M3 gate signal
is triggered by the duty cycle d2, M4 is triggered opposite to d2. In addition, the M2 gate
signal should be the compliment of M1’s at all times, otherwise the input voltage Vg is
shorted. Likewise, the M3 gate signal should take the complimentary value of M4’s.

Therefore, by inspection, the values of M1 through M4 are:

M 1 = d1 • d 2
M 2 = M1
M 4 = d1 • d 2
M3 = M4

An alternative way of deriving M2 and M3 is as follows:

( ) ( ( )) (
M 2 = d1 + d1 • d 2 = d1 • (d1 • d 2 ) = d1 • d1 + d 2 = d1 • d 2 = M 1 )
M 3 = d 1 + d 1 • d 2 = ( d 1 • ( d 1 • d 2 )) = ( d 1 • ( d 1 + d 2 ) = ( d 1 • d 2 ) = M 4
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Logic Optimized
ORCAD Simulated Logic

Our logic circuit (above left) could be logically reduced to the circuit on the right. However,
we consistently experienced unknown component errors in the ORCAD simulation using
the NAND gate reduction to the right. For this reason, we chose to simulate the circuit to
the left even though it is not minimal.
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The following image is the full schematic for a Pulse Width Modulated H-bridge with
the energy saving gating scheme.
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Energy Saving Mode Pulse Width Modulation Controlled H-bride gating Signals

Simulation of the circuit in steady-state

Energy Saving Mode PWM H-bride Output Voltage compared to an ideal sinusoid The
large inductor causes a phase delay (lag). ORCAD Lite does not give us the ability to
create a delayed reference sinusoid.
(Contains Input Voltage with perturbation, reference sinusoid, and Output Voltage)
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The unipolar output voltage signal is very similar to the bipolar one. However, the VA
voltage swing is only half that of the bipolar case. VA is defined as the voltage differential
just prior to the output filter. This makes the unipolar PWM case “energy saving.”
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One Cycle Controlled (OCC) H-bridge in Energy Saving Mode

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In OCC unipolar, the gating logic is unchanged from the PWM case. However, OCC
contains an integrator, with a switch utilized for resetting (across the capacitor). During
dT
1
RC ∫0
each individual switching period, V INT = xdt = VREF . The integrating time constant τ

should be close to, but a bit shorter than the switching period TS. Since
1 1
TS = = = 50µs , an acceptable integration time constant ( τ = 40µs ) is given by
f S 20kHz
R = 100kΩ and C = 400 pF .

The open-loop circuitry special to OCC is shown below. The upper left section of the
schematic shows the SET-RESET latch. The integrator output is fed back to RESET, and a
clock corresponding to the switching period drives SET.
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The following image shows the OCC process:

Each time the integrated signal reaches the sinusoid reference, RESET is activated, and
the integration process begins anew. Consequently, the duty ratio, d2, increases with
increasing sinusoid and vice versa.

The following image shows the open-loop OCC controlled H-bride output voltage compared
with an ideal sinusoid. Note: The ORCAD Lite software only permits a limited number of
logic transitions, so the OCC case, which requires more logic transitions, has a shorter
simulation time. The input voltage is 300 V.

The large inductor causes a phase delay (lag). Closed-loop control is required to appreciate
OCC’s fast tracking. Therefore, the above waveform is comparable to PWM’s open-loop
response.
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Introduction of Input Voltage Disturbance

To introduce the input disturbance, the schematic is modified in each case.

Output voltage response to Input voltage disturbance: Open-Loop PWM

Bipolar
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Output voltage response to Input voltage disturbance: Open-Loop PWM

Energy Saving Mode
(Contains Input Voltage with perturbation, reference sinusoid, and Output Voltage.)

Output voltage response to Input voltage disturbance: Open-Loop OCC

Energy Saving Mode
(Contains Input Voltage with perturbation, reference sinusoid, and Output Voltage)
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Closed-Loop OCC Energy Saving Mode

Since OCC doesn’t require an extra PID controller in Closed-Loop configuration, we can
make a slight modification to the schematic, and close the loop.

The voltage differential just prior to the

output filter is scaled down and fed back to
the integrator input shown right.

Output voltage response to Input voltage perturbation: Closed-Loop OCC

Energy Saving Mode. (Contains Input Voltage with perturbation, reference sinusoid,
Output Voltage, and closed-loop feedback signal)

OCC more faithfully tracks the response even with the input perturbation in the closed-loop.
Remember the inductor causes a phase lag.
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Tracking Ability of Individual Open-Loop Control Schemes Compared

Output Voltage Output Voltage with VG Percent
Perturbation Error at
VPEAK
PWM Bipolar (Open-Loop) 145.1 VPEAK 164.8 VPEAK 13.6 %
PWM Energy Saving Mode 141.7 VPEAK 158.9 VPEAK 12.1 %
(Open-Loop)
OCC Energy Saving Mode 140.3 VPEAK 158.3 VPEAK 12.8 %
(Open-loop)
OCC Energy Saving Mode 141.2 VPEAK 138 VPEAK 2.27 %
(Closed-loop)

As expected, the Open-loop control schemes had comparable tracking error. The Closed-
loop OCC provided greatly improved performance. If time permitted, it would have been
nice to design a PID controller to close the PWM loop. This speaks to the advantage of
OCC and its simplicity.

Conclusion
Through this exercise we analyzed the design and implementation of two open-loop control
schemes: Pulse Width Modulation and One Cycle Control. These schemes were further
specialized to Bipolar gating and Energy-Saving (unipolar) gating. Energy-Saving gating is
preferred since it consumes much less power. One Cycle Control, though not meant for
open-loop control, is great in a closed-loop since it eliminates the need to design a PID
controller. Since duty cycle is recalculated each switching period, waveforms are more
faithfully reproduced, especially when an input disturbance is introduced.

It would be desirable to analyze the efficiency of both Bipolar and Unipolar cases.
Additionally we would like to quantify cross-over and total harmonic distortion as well.
However, the ORCAD Lite software wattmeter does not function properly, and distortion
analysis is not available. Future students using the recently donated Saber software should
be able to accomplish this.